MSV11-Q MOS Memory User's Guide EK- MSV1

MSV11-Q MOS  Memory User's  Guide EK- MSV1
EK- MSV1 Q- UG-002
MSV11-Q
MOS Memory
User's Guide
1st Edition, March 1985
2nd Edition, May 1985
Copyright © May 1985 by Digital Equipment Corporation.
All Rights Reserved.
Printed in U.S.A.
The reproduction of this material, in part or whole, is strictly prohibited. For
copy information, contact the Educational Services Department, Digital
Equipment Corporation, Maynard, Massachusetts 01754.
The information in this document is subject to change without notice. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document.
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CONTENTS
CHAPTER 1 CHARACTERISTICS AND SPECIFICATIONS
1.1
1.2
1.3
1.3.1
1.3.2
1.3.2.1
1.3.2.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.3.4
1.3.5
1.3.6
1.3.7
1.3.7.1
1.3.8
1.4
Introduction ...............................................
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications .............................................
Functional Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltages...........................................
Power Requirements ..............................
Environmental Specifications. . . . . . . . . . . . . . . . . . . . . . . . ..
Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Relative Humidity ..................................
Operating Airflow.. . . . .. .. . . . . . . . .. . . . . . .. . . .. . . . ..
Altitude ............................................
Refresh ................................................
Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Backplane Pin Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Electrical Specifications ...............................
Power Supply Requirements. . . . . . . . . . . . . . . . . . . . . ..
Bus Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Related Documents .......................................
1
3
4
5
7
7
7
11
11
12
12
12
12
12
12
15
15
15
15
CHAPTER 2 CONFIGURATION (MSV11-QA, ETCH REVISION A)
2.1
2.2
2.2.1
2.2.2
2.2.3
General ...................................................
Configuring the MSV11-QA (Etch Revision A) .............
Test Jumper (W5, W6) .................................
CSR Register Selection (R, P, N, M) Jumpers ..........
Enable/Disable CSR Selection Jumper ................
17
17
19
19
21
iii
iv
CONTENTS
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
Enable/Disable Block Mode Jumper ...................
Enable/Disable Extended Error Address Jumper ......
Test Jumper C, D ......................................
Enable Parity Error Detection Jumper .................
Battery Backup ........................................
Address Switches .....................................
21
22
22
23
23
24
CHAPTER 3 (MSV11-QA ETCH REVISION C OR LATER,
MSV11-QB AND MSV11-QC)
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
General ...................................................
Configuring the MSV11-Q .................................
CSR Register Selection (Jumpers J4 through J11) ....
Test Jumpers J1 through J3 ...........................
Battery Backup ........................................
Chip Select Jumpers ..................................
Address Switches .....................................
27
27
29
30
31
31
33
CHAPTER 4 UNPACKING AND INSTALLATION
4.1
4.1.1
4.1.2
4.1.3
4.1.4
CHAPTER 5
5.1
5.2
5.2.1
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.4
General ...................................................
Unpacking and Inspection .............................
Pre-installation ........................................
Installation ............................................
Module Checkout .....................................
35
35
36
37
37
FUNCTIONAL DESCRIPTION
Introduction ...............................................
LSI-11 Bus Signals and Definitions ........................
LSI-11 Bus Dialogues .................................
Functional Description of Memory Module ................
Xcvrs (Transmit - Receive) . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Address Logic .........................................
Control Signal Xcvrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Address Select Logic ..................................
Cycle Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Access .......................................
Parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Control and Status Register (CSR) Bit Assignment ........
39
40
52
58
58
58
58
58
60
60
61
62
CONTENTS
v
General ...................................................
Preventive Maintenance ...................................
Visual Inspection " " " " " " " , .......................
Power Voltage Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Diagnostic Testing ........................................
MicroVAX Memory Diagnostic I (EHXMS) ..............
Bootstrapping Procedure ..........................
Operation ..........................................
Command Syntax ..................................
Using the Commands ..............................
Test Procedure .................................. ,.
Error Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MSV11-Q Diagnostic (LSI-11 Bus) .....................
Hardware Requirements ...........................
Software Requirements ............................
Hardware Restrictions ..................... . . . . . . ..
Related Documents and Standards ................
Diagnostic Hierarchy Prerequisites ................
Assumptions ............ , ..........................
Loading the Program ..............................
Special Environments .............................
Program Options ..................................
Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Error Reporting ....................................
Error Halts .........................................
Sub-test Summaries ...............................
Toggle-In-Program 1 ...............................
Toggle-In-Program 2 ...............................
Digital's Services ..........................................
Digital Repair Service .................................
65
66
66
66
66
66
67
67
67
69
71
73
75
75
76
76
76
76
76
77
77
77
77
78
78
79
81
82
83
83
CHAPTER 6 MAl NTENANCE
6.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.2.5
6.3.2.6
6.3.2.7
6.3.2.8
6.3.2.9
6.3.2.10
6.3.2.11
6.3.2.12
6.3.2.13
6.3.2.14
6.3.2.15
6.4
6.4.1
INDEX
vi
CONTENTS
FIGURES
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3-5
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
6-1
6-2
Module Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumper and Switch Locations MSV11-QA .................
Jumper Block Example ....................................
Jumper Settings for CSR Address of 17772100 ...........
Enable/Disable CSR Selection ............................
Enable/Disable Block Mode ...............................
Enable/Disable Extended Error Address ...................
Test Jumper ...............................................
Enable/Disable Parity Error Detection ....... " ..... " .... ,
Battery Backup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MSV11-Q Jumpers and Switches ..........................
Jumper Settings for CSR Address of 17772102 ...........
Manufacturing Test Jumpers ..............................
Battery Backup ............................. '" ............
Chip Select Jumpers ......................................
Typical System ............................................
MSV11-Q Memory Interface ...............................
DATO or DATOB Bus Cycle.. .. .. .. .. .. . .. .. .. . .. .. .. . .. ...
DATI Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DATIO or DATIOB Bus Cycle ..............................
DATBO Bus Cycle .........................................
DATBI Bus Cycle ..........................................
MSV11-Q Functional Block Diagram ......................
CSR Bit Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Diagnostic Relocation ............................
Sample Diagnostic Run for MSV11-QA/MSV-11 P .........
2
18
19
20
21
21
22
22
23
23
28
29
30
31
32
40
41
53
54
55
56
57
59
61
70
72
CONTENTS
vii
TABLES
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
2-1
2-2
3-1
3-2
5-1
5-2
5-3
6-1
6-2
6.3.1
6.3.2
MSV11-QA Access and Cycle Times. . . . . . . . . . . . . . . . . . . . . . .
MSV11-QA, MSV11-QB, and MSV11-QC Access and
Cycle Times ...............................................
Voltage Pins (MSV11-QA) .................................
Voltage Pins [MSV11-QA, MSV11-QB, and MSV11-QC] ....
MSV11-QA Power .........................................
MSV11-QB Power ............ - ............................
MSV11-QC Power .........................................
Backplane Pin Utilization (MSV11-QA) .....................
Backplane Pin Utilization (MSV11-QA, MSV11-QB,
MSV11-QC) ...............................................
CSR Register Selection ...................................
Starting and Ending Address Selection ....................
CSR Register Selection ...................................
Starting and Ending Address Selection ....................
Summary of Bus Cycles ...................................
Bus Signals ...............................................
Dialogues to Perform Memory Data Transfers .............
Control Keys ..............................................
Command Summary .......................................
MicroVAX Memory Diagnostic 1 (EHXMS) .............
MSV11-Q Diagnostic (LSI-11 Bus) .....................
5
6
8
8
9
10
11
13
14
20
24
30
33
40
41
52
68
68
66
75
CHARACTERISTICS
AND SPECIFICATIONS
1.1
1
INTRODUCTION
This manual describes the MSV11-Q memory module. The module contains
metal oxide semiconducters (MOS) random access memory (RAM). It is used
with the LSI-11 bus and provides 1024K byte to 4096K byte storage for 18-bit
words (16 data bits and 2 parity bits). It also contains parity control circuitry and
a control and status register (CSR).
There are four variations of the MSV11-Q module.
• MSV11-QA (etch revision A) - 64K RAMs fully populated; cannot be
configured for battery backup
• MSV11-QA (etch revision C or later) - 64K RAMs fully populated; can be
configured for battery backup
• MSV11-Q8 - 256K RAMs half populated; can be configured for battery
backup
• MSV11-QC - 256K RAMs fully populated; can be configured for battery
backup
The MSV11-QA (etch revision A) is indicated as shown in Figure 1-1 A. Differences between the MSV11-QA, etch revision A, and the other variations will be
pointed out as they occur.
The MSV11-QA (etch revision C), iviSV11-Q8, and iviSVII-QC aii use the same
etch (refer to Figure 1-18).
2
CHARACTERISTICS AND SPECIFICATIONS
5017547Al
~
PRINTED CIRCUIT
BOARD NO.
(COMPONENT SIDE)
(A) MSVll·QA (ETCH REV A ONLY)
(COMPONENT SIDE)
(B) MSVll·QA (ETCH REV C OR LATER) MSVll·QB. AND MSV11·QC
SH"·OJ2'·8A
$Hf'I-QOO1-85
Figure 1-1 Module Identification
CHARACTERISTICS AND SPECIFICATIONS
3
The major features of the MSV11-Q are:
• 1 megabyte of MOS memory on a single quad module (MSV11-QA).
2 megabyte of MOS memory on a single quad module (MSV11-QB).
4 megabyte of MOS memory on a single quad module (MSV11-QC).
• 22-bit addressing standard.
• Parity is generated and checked for each byte for data integrity.
• Self-contained Control and Status Register (CSR) for full parity
implementation.
• Full parity control enables the CPU to trap on a parity error with LED
display for parity status.
• Completely LSI hardware and software compatible.
• Switch selectable starting address in 128K byte increments.
• 16 jumper selectable CSR addresses (17772100 through 17772136).
• Single +5 V power. MSV11-QA (etch revision A) does not support battery
backup.
• Supports Block-Mode for efficient multiple DMA transfer.
1.2 GENERAL DESCRIPTION
The MSV11-Q memory module consists of a single, quad-height module
(M7551) that contains the LSI-11 bus interface, timing and control logic, refresh
circuitry, and a MOS storage array. The module also contains circuitry to
generate and check parity, and a control and status register. The MSV11-Q
memory uses +5 V from the backplane.
The memory module's starting address can be set on any 128 KB boundary
within the 4096 KB LSi-ll address space or 256 KB LSi-ll address space.
The MSV11-Q allows the top 4K of the LSI-11 address space to be reserved for
the I/O peripheral page. There is no address interleaving with the MSV11-Q.
4
CHARACTERISTICS AND SPECIFICATIONS
The memory storage elements for the MSV11-QA are 65,536 by 1 bit MOS
dynamic RAM devices. The storage elements for the MSV11-QB and MSV11QC are 262,144 by 1 bit MOS dynamic RAM devices. The MOS storage array
for the MSV11-QA and MSV11-QC has 8 rows with each row containing 18
devices for a total of 1024K bytes on the MSV11-QA and 4 megabytes on the
MSV11-QC. The MSV11-QB is half populated and therefore contains 4 rows
for a total of 2 megabytes of memory. The read operation for MOS storage
devices is non-destructive. The MOS storage devices must be refreshed every
12.0 IlS so that the data remains valid.
The control and status register in the MSV11-Q contains bits used to store the
parity error address bits. You can force wrong parity by setting a bit in the CSR.
This is a useful diagnostic tool for checking out the parity logic. The CSR has
its own address in the top 4K of memory. Bus masters can read or write to the
CSR.
The parity control circuitry in the MSV11-Q generates parity bits based on data
being written into memory during a DATO or DATOS bus cycle. One parity bit is
assigned to each data byte and is stored with the data in the MOS storage
array. When data is retrieved from memory during DATI or DATIO bus cycles,
the parity of the data is determined. If parity is good, the data is assumed
correct. If the parity bits do not correspond, the data is assumed unreliable and
memory initiates the following action.
1. If a parity error occurs, CSR bit 15 is set and a red LED on the module
lights.
In the case of MSV11-QA (etch revision C or later), MSV11-QS and
MSV11-QC, the memory asserts SDAL 16 and 17 if bit 0 in the CSR is set.
This warns the processor that a parity error has occurred.
For this to
occur in the MSV11-QA (etch revision A), jumper H must be connected
(refer to Paragraph 2.2.7).
2. Part of the address of the faulty data is recorded in the CSR.
1.3 SPECIFICATIONS
This section gives functional, electrical, and environmental specifications and
backplane pin utilization information. The specifications in this section are
applicable to all variations of the MSV11-Q memory except where differences
are noted.
CHARACTERISTICS AND SPECIFICATIONS
5
1.3.1 Functional Specifications
Table 1-1 provides access and cycle time specifications for the MSV11-QA
(etch revision A) memory. Table 1-2 provides access and cycle times for the
other MSV11-Q variations.
Table 1-1
MSV11-QA (etch revision A) Access and Cycle Times
Tacc(ns)
Meas
Typ
Max
Tcyc(ns)
Notes
Meas
Typ
Max
Notes
520
550
1220
578
597
1255
4
5
6
Parity-CSR Configurations (Notes 1,8,9)
DATI
DATO(B)
DATIO(B)
DATBI
DATBO
320
350
1000
358
376
1045
320
20
320
358
31
376
350
20
280
387
31
668
2
2
3
2
10
11,12
N/A
2
10
13,14
N/A
520
500
569
N/A
N/A
N/A
15
547
N/A
N/A
N/A
16
6
CHARACTERISTICS AND SPECIFICATIONS
Table 1-2
MSV11-QA (Etch Revision C or Later), MSV11-QB, and
MSV11-QC Access and Cycle Times
Tacc(ns)
Meas
Typ
Max
Tcyc(ns)
Notes
Typ
Max
Meas
Notes
510
550
1220
563
592
1250
4
5
6
Parity-CSR Configurations (Notes 1,8,9)
DATI
OATO(B)
OATIO(B)
320
160
780
358
189
847
2
2
3
OATBI
320
20
340
358
31
363
2
10
11,12
N/A
OATBO
160
20
250
189
31
292
518
N/A
N/A
N/A
569
2
10
13,14
N/A
655
15
N/A
N/A
N/A
695
16
The following notes (1 through 16) refer to Tables 1-1 and 1-2.
Notes for DA TI, DA TO(B), DA TlO(B) Cycles:
1. Assuming memory not busy and no arbitration.
2. SYNCH to RPLYH with minimum times (25/50 ns) from SYNCH to
(DINH/DOUTH). The DA TO(B) access and cycle times assume a minimum
of 50 ns from SYNCH to DOUTH inside memory receivers. For actual LSI11 bus measurements, a constant (K-50 ns) where K = 200 ns should be
added to DATI(B) times, i.e. acc (Typ) = 100 + (200 - 50) = 250 ns.
3. SYNCH to RPL YH DA TlO(B), with minimum time (25 ns) from SYNCH to
DINH and minimum 350 ns from RPL YH (DATI) asserted to DOUT
asserted.
4. SYNCH to MBSY L negated.
5. SYNCH to MBSY L negated with minimum time (50 ns) from SYNCH to
DOUTH.
6. SYNCH to MBSY L (DATIO(B)) with minimum times (25 ns) from SYNCH to
DINH and minimum 350 ns from RPL YH (DA TI) asserted to DOUT
asserted.
CHARACTERISTICS AND SPECIFICATIONS
7
7. REF REO L to MBSY L negated.
8. The MSV11-0 Module does not lose any time due to refresh arbitration.
9. REFRESH conflict adds 250 ns Typical and 542 ns maximum to access and
cycle time.
Notes for DA TBI AND DA TBO Cycles:
10. DIN/DOUT negation to MRPL Y negation
11. DIN negation to TRPL Y assertion
12. DIN remains asserted for 200 ns minimum after TRPL Y with 150 ns minimum from TRPL Y negation to assertion of next DIN.
13. DOUT remains asserted for 150 ns minimum after TRPL Y with 150 ns
minimum from TRPL Y negation to assertion of next DOUT.
14. DOUT assertion to TRPL Y assertion.
15. DIN negation to MBSY L negation after first DIN cycle. Use DA TI cycle time
for first DINjTRPL Y cycle in block mode ready cycle.
16. DOUT assertion to MBSY L negation after first DOUT cycle. Use DA TO(B)
cycle time for first DOUT/TRPL Y cycle in block mode write cycle.
1.3.2 Electrical Specifications
The electrical specifications state the voltage and power requirements for the
MSV11-Q.
1.3.2.1 Voltages - Single voltage MOS RAMs require only +5 V. Voltage
margins for +5 V are ±5 percent (Tables 1-3 and 1-4).
1.3.2.2 Power Requirements - Power requirements are provided in Tables 15, 1-6 and 1-7.
8
CHARACTERISTICS AND SPECIFICATIONS
Table 1-3
Voltage Pins (MSV11-QA, Etch Revision A)
Voltage
Pins
Service
+5 V
AA2, BA2, BV1,CA2, DA2
Single voltage
MOS RAMs*
Table 1-4
Voltage Pins [MSV11-QA (Etch Revision C or Later,) MSV11QB, and MSV11-QC]
Voltage
Backplane Pins
+5 V
AA2,BA2,BV1,CA2, and DA2
+5 V BBU
AV1, and AE1 *
Single voltage
MOS RAMs
* Check backplane voltages to ensure proper configurations.
CHARACTERISTICS AND SPECIFICATIONS
Table 1-5
MSV11-QA Power (All Etch Revisions)
MSV11-QA With 64K RAMs Fully Populated
Current (Amps)
Standby
Active
Typ
Measured
Max
Typ
Measured
Max
+5 V total
+5 V BBU total
1.0
1.28
1.32
2.33
1.0
1.4
1.32
2.67
Module total
2.28
3.65
2.4
3.99
Power (Watts)
Standby
Active
Typ
Measured
+5 V total
+5 V BBU total
Module total
Max
Typ
Measured
' Max
5.0
6.4
6.93
12.23
5.0
7.0
6.93
14.02
11.4
19.16
12.0
20.95
9
10
CHARACTERISTICS AND SPECIFICATIONS
Table 1-6
MSV11-Q8 Power
MSV11-QB With 256K RAMs Half Populated
Current (Amps)
Standby
Active
Typ
Measured
Max
Typ
Measured
Max
+5 V total
+5 V BBU total
1.0
1.18
1.32
1.66
1.00
1.30
1.32
2.27
Module total
2.18
2.98
2.30
3.59
+5 V total
+5 V BBU total
Module total
Power (Watts)
Standby
Active
Typ
Measured
Typ
Measured
Max
Max
5.0
5.90
6.93
8.72
5.0
6.50
6.93
11.92
10.90
15.65
11.50
18.85
CHARACTERISTICS AND SPECIFICATIONS
11
Table 1-7 MSV11-QC Power
MSV11-QC With 256K RAMs Fully Populated
Current (Amps)
Standby
Active
Typ
Measured
Max
Typ
Measured
Max
+5 V total
+5 V BBU total
1.0
1.34
1.32
2.37
1.0
1.50
1.32
2.98
Module total
2.34
3.69
2.50
4.30
+5 V total
+5 V BBU total
Module total
Power (Watts)
Standby
Active
Typ
Measured
Typ
Measured
Max
Max
5.00
6.70
6.93
12.44
5.00
7.50
6.93
15.65
11.70
19.37
12.50
22.58
1.3.3 Environmental Specifications
Environmental specifications cover storage and operating temperature, relative
humidity, altitude, and air flow specifications.
1.3.3.1 Temperature - Temperature is separated into the following two
groups.
1. Operating Temperature Range - The operating temperature range is
+5°C to +60°C. Lower the maximum operating temperature by 1°C for
every 1000 feet of altitude above 8000 feet.
12
CHARACTERISTICS AND SPECIFICATIONS
2. Storage Temperature Range - The storage temperature range is -40°C
to +66°C. Do not operate a module that has been stored outside the
operating temperature range before bringing the module to an environment within the operating range and allowing at least five minutes for the
module to stabilize.
1.3.3.2 Relative Humidity - The relative humidity for the MSV11-QA memory
modules must be 10% to 90 percent noncondensing for storage or operating
conditions.
1.3.3.3 Operating Airflow - Adequate airflow must be provided to limit the
inlet to outlet temperature rise across the module to 5°C when the inlet temperature is +60°C. For operation below +55°C, airflow must be provided to limit
the inlet to outlet temperature rise across the module to 10°C maximum.
1.3.3.4 Altitude - The module resists mechanical or electrical damage at
altitudes up to 50,000 feet (90 MM mercury) under storage or operating
conditions.
NOTE: Lower the maximum operating temperature by 1°C for every 1000 feet
of altitude above 8000 feet.
1.3.4 Refresh
The MSV11-Q memory module uses a self-contained refresh OSCillator, with
rate that is typically 535 ns every 12,000 ns. The refresh overhead maximum is
542 ns/12,500 ns or 4.3 percent.
1.3.5 Diagnostics
The diagnostics are CVMSAA for 22-bit systems and EHXMS for MicroVAX.
1.3.6 Backplane Pin Utilization
Backplane pin utilization for the MSV11-QA (etch revision A) is shown in Table
1-8. Backplane pin utilization for the MSV11-QA (etch revision C or later),
MSV11-Q8 and MSV11-QC is shown in Table 1-9. Blank spaces indicate pins
not used.
Table 1-8
Backplane Pin Utilization (MSV11-QA, Etch Revision A)
A Connector
Pin
A
B
C
D
*E
F
H
J
K
L
M
N
P
R
S
T
U
*V
Side 1
BDAL16L
BDAL17L
+5 V BB
GND
REFIKILL
GND
BREF L
GND
+5 V BB
B Connector
C Connector
o Connector
Side 1
Side 1
Side 1
Side 2
+5 V
BDCOK H
+5 V
+5 V
+5 V
GND
BDAL
BDAL
BDAL
BDAL
GND
GND
UND
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
GND
*BIAKIL
GND
*BIAKOL
BBS7L
*BDMGIL
*BDMGOL
BINIT L
GND
BDALOO L
BDAL01 L +5 V
18L
19L
20L
21L
BDAL 02L
BDAL 03L
BDAL 04L
BDAL 05L
BDAL 06L
BDAL 07L
BDAL 08L
BDAL 09L
BDAL 10L
BDAL11L
BDAL12L
BDAL13L
BDAL14L
BDAL15L
B
L
A
N
K
Side 2
Side 2
Side 2
*BIAKIL
*BIAKOL
B
L
A
N
K
B
L
A
N
K
()
I
»J)
»
()
-I
m
J)
Ci5
::!
*BDMGIL
*BDMGOL
GND
()
GND
(j)
»
z
0
(j)
"'tI
* Hardwired via etch on module. If a system uses the pin for anything but power, user must cut gold finger AE 1 on
the board.
m
()
::!!
()
):>.
::!
0
z
(j)
w
Table 1-9
Backplane Pin Utilization (MSV11-QA, Etch Revision C or Later, MSV11-QB, MSV11-QC)
A Connector
C Connector
B Connector
o Connector
+:>.
()
I
Pin
Side 1
Side 2
Side 1
Side 2
Side 1
Side 2
Side 1
Side 2
~
JJ
~
()
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
+5 V
BDCOK H
+5 V
+5 V
+5 V
--I
m
JJ
BDAL 16L
BDAL17L
+5 V BB
GND
REFKILL
GND
BREF L
GND
+5 V BB
GND
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
BDAL 18L
BDAL19L
BDAL 20L
BDAL 21L
GND
*BIAKIL
GND
*BIAKOL
BBS7L
*BDMGIL
*BDMGOL
BINIT L
GND
BDALOO L
BDAL01 L +5 V
BDAL 02L
BDAL 03L
BDAL 04L
BDAL 05L
BDAL 06L
BDAL 07L
BDAL 08L
BDAL 09L
BDAL10L
BDAL 11L
BDAL 12L
BDAL 13L
BDAL14L
BDAL15L
GND
GND
GND
en--I
0
(j)
~
z
B
L
A
N
K
*BIAKIL
*BIAKOL
B
L
A
N
K
B
L
A
N
K
(j)
"'0
m
()
11
0
~
--I
(5
z
*BDMGIL
*BDMGOL
GND
0
(j)
GND
• Hardwired via etch on module.
NOTE: If you are using AEI (sspare 1) for anything other than battery backup voltage (+5 V 88), jumper WI
must not be installed. However, Digital Equipment Corporation recommends backpanel pin <AE1> be used as
+5.0 V battery backup power in this application. Refer to Paragraph 3.2.3 for additional information.
CHARACTERISTICS AND SPECIFICATIONS
1.3.7 Electrical Specifications
1.3.7.1 Power Supply Requirements - The module operates on +5 V only.
1.3.8 Bus Loading
MSV11-QA (etch revision A)
AC load units = 1.9
DC load units = 0.5
MSV11-QA (etch revision C)
AC load units = 2.4
DC load units = 0.5
1.4 RELATED DOCUMENTS
Refer to the following documents for more information.
• MSV11-QA, MSV11-QB, and MSV11-QC (all etch revisions) Field
Maintenance Printset (MP01931)
• Microcomputer and Memory Handbook (EB-18451-20)
• Microcomputer Interface Handbook (EB-20175-20)
• LSI-11 System Service Manual (EK-LSI-FS-SV)*
• MicroVAX I Owner's Manual (EK-KD32A-OM) (For
Diagnostics Section)
These documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
ATIN: Communications Services (NR2jM15)
Customer Services Section
* Field Service Use Only
15
CONFIGURATION
(MSV11-QA, ETCH REVISION A)
2
2.1 GENERAL
This chapter contains information for configuring the MSV11-QA memory module (etch revision A). Jumper and address switch settings are included.
NOTE: Configuration and installation for the MSVll-QA (etch revision C or
later), and the MSVll-Q8 and MSVll-QC are provided in Chapter 3.
2.2 CONFIGURING THE MSV11-QA (Etch Revision A)
The MSV11-QA (etch revision A) has one red LED to indicate parity errors. The
module contains the following jumpers (Figure 2-1).
•
•
•
•
•
•
•
•
Test jumper (W5, W6)
CSR register selection jumpers (R, P, N, M)
Enable/disable CSR selection jumper (A, B)
Enable/disable block mode jumper (W1, W2)
Enable extended error address jumper (K, L)
Test jumper (C, D)
Enable parity error detection jumper (J, H)
+5 V/+5 VB
The MSV11-QA has two DIP (dual in-line package) switch packs. Each DIP
switch pack consists of six switches. The two DIP switch packs are used to
set:
• Starting address.
• Ending address.
17
18
CONFIGURATION (MSV11-QA ETCH REVISION A)
5017547Al
A".- - - - - - - = - - PARITY
U
W58:J....-L
Rm} W6 I
·
~
~:'l
:I
tj ~
I
~}..
8!
B
I
.
~
LED
TEST JUMPER (USED
BY MFG ONLY)
CSR REGISTER
SELECTION
ENABLE/DISABLE
CSR SELECTION
STARTING ADDRESS
~w*1 SWITCHES (56 NOT USED)
W 2
OFF ON 6
I
ENABLE/DISABLE
BLOCK MODE
I=I~LLENABLE/DISAB.
ti
~ EXTENDED LE
(COMPONENT SIDE)
SW2
8= ~}
I
1
8:J. I
=65
OFF
C
o
ERROR ADDRESS
ENDING ADDRESS
SWITCH ES
ON
I
TEST JUMPER (USED
BY MFG. ONLY)
ITD------ENABLE PARITY
J H
ERROR DETECTION
+5V
EF~·----=-- ~g~su~~~'s~~~~i
o
+5 VB
BATTERY BACKUP
A
SHR0321·84
$tiR-0G0'2..aP;
Figure 2-1
Jumper and Switch Locations MSV11-QA (Etch Revision A)
Figure 2-1 shows the physical location of the jumpers and switches. The
jumpers and switches are described in the following paragraphs. To jumper
two pins, a 0 ohm connector block is used. For example, to enable parity error
detection, jumper H (Figure 2-2) is connected (pin J2 to J3) and to disable parity
error detection, jumper J is connected (pin J1 to J2). Factory configuration has
parity error detection enabled.
CONFIGURATION (MSV11-QA, ETCH REVISION A)
19
JUMPER BLOCK
PINS
a.
PARITY ERROR DETECTION ENABLED
H
J
1 1
J1
b.
J2
o
J3
PARITY ERROR DETECTION DISABLED
SHR-0322-84
Figure 2-2
Jumper Block Example
2.2.1 Test Jumper (W5, W6)
This test jumper is used by manufacturing and should not be changed. W6
should be jumpered and W5 should be open.
2.2.2 CSR Register Selection (R, P, N, M) Jumpers
The MSV11-QA can provide up to 16 GSR register address selections when
the user installs or removes appropriate jumper blocks (Figure 2-2). For example, in Figure 2-2, the parity error detection jumper block is shown. Table 2-1
shows the jumper positions and the corresponding GSR register addresses.
Figure 2-3 shows the jumper settings for a GSR register address of 17772100.
20
CONFIGURATION (MSV11-QA ETCH REVISION A)
Table 2-1
CSR Register Selection
Number CSR Memory
Jumper Position
R
P
N
M
CSR Register Address
1st
2nd
3rd
4th
5th
out
in
out
in
in
in
out
out
in
in
in
in
in
out
in
in
in
in
in
17772100
17772102
17772104
17772106
17772110
6th
7th
8th
9th
10th
out
in
out
in
out
in
out
out
in
in
out
out
out
in
in
in
in
in
out
out
17772112
17772114
17772116
17772120
17772122
11th
12th
13th
14th
15th
16th
in
out
in
out
in
out
out
out
in
in
out
out
in
in
out
out
out
out
out
out
out
out
out
out
17772124
17772126
17772130
17772132
17772134
17772136
In
If more than one CSR parity type of memory is installed in the system, use care
to ensure that no two modules have the same address.
J22 (R)
J23 (R)
J20 (P)
J21 (P)
J18 (N)
J19 (N)
J16 (M)
J17 (M)
SHR·0323·84
Figure 2-3 Jumper Settings for CSR
Address of 17772100
CONFIGURATION (MSV11-QA, ETCH REVISION A)
21
2.2.3 Enable/Disable CSR Selection Jumper (Figure 2-4)
This jumper disables GSR selection when non-parity memory is used. Since
the MSV11-QA is a parity memory, this jumper should be set for "enable GSR
selection" Uumper B connected).
J15
0
J14
000-
A
ENABLE CSR SELECTION
B
J13
(FACTORY CONFIGURATION)
000SHR-0324-84
Figure 2-4 Enable/Disable GSR Selection
2.2.4 Enable/Disable Block Mode Jumper (Figure 2-5)
This jumper enables or disables block mode operation. The jumper should be
set for "enable block mode" Uumper W1 connected).
J12
ENABLE BLOCK MODE
""-'-+-1 W1
(FACTORY CONFIGURATION)
J11
....-.--IW2
J10
o
SHR-0325-84
Figure 2-5 Enable/Disable Block Mode
22
CONFIGURATION (MSV11-QA ETCH REVISION A)
2.2.5 Enable/Disable Extended Error Address Jumper (Figure 2-6)
This jumper selects 18- or 22-bit addressing. The jumper should be set for
"enable extended error address" (jumper L connected).
J9
o
~--t
K
J8
1---+..... L
ENABLE EXTENDED ERROR ADDRESS
(FACTORY CONFIGURATiON)
J7
SHR-0326-84
Figure 2-6
Enable/Disable Extended Error Address
2.2.6 Test Jumper C, 0 (Figure 2-7)
This jumper is a test jumper for use by manufacturing. Jumper C should be
connected and jumper D should be open.
J6
NORMAL
POSITION
--0
C
J5
--0
0
D
J4
SHR-0327-B4
Figure 2-7
Test Jumper
CONFIGURATION (MSV11-QA, ETCH REVISION A)
23
2.2.7 Enable Parity Error Detection Jumper (Figure 2-8)
This jumper enables or disables parity error detection. The jumper should be
set for "enable parity error detection" (jumper H connected).
H
I
0
Y
j
-
-
I
ENABLE PARITY ERROR DETECTION
(FACTORY CONFIGURATION)
----_---IL..--_.J
Jl
J2
J3
SHR-0328-84
Figure 2-8
Enable/Disable Parity Error Detection
2.2.8 Battery Backup (Figure 2-9)
Not used or supported in etch revision A of MSV11-QA.
+5 V
o
0
NOT USED
o
+5 VB
SHR-0329-84
Figure 2-9
Battery Backup
24
CONFIGURATION (MSV11-QA ETCH REVISION A)
2.2.9 Address Switches
There are two DIP (dual-in-line package) switch packs on the MSV11-QA module. DIP switch pack SW1, containing six switches, selects the starting
address. DIP switch pack SW2, containing six switches, selects the ending
address. The starting address is set first and then the ending address is set to
a number greater than the starting address. Table 2-2 shows the switch settings for the starting addresses and ending addresses. Switch 6 of SW1 is not
used. Switch 6 of SW2 is turned on or enabled (0) for a starting address of all
O's and is turned off or disabled (1) for all other starting addresses.
Table 2-2
Starting and Ending Address Selection
Desired
Starting
Address
SW 1
Switch
Position
SW2
Switch
Position
Desired
Ending
Address
SW2
Switch
Position
In Kbyte
12345
6
In Kbyte
12345
00000
11111
o1 1 1 1
10111
00111
0
1
1
1
1
0
128
256
384
512
640
768
896
1024 (1 MB)
1152
11011
o1 0 1 1
10011
000 1 1
11101
o1 1 0 1
128
256
384
512
640
11111
o 1 111
10111
00111
11011
768
896
1024 (1 MB)
1152
1280
o1 0 1 1
100
000
111
o1 1
1
1
0
0
1
1
1
1
1280
1408
1536
1664
1792
10101
001 0 1
1 1 001
o 1 001
1
1
1
1
1
1408
1536
1664
1792
1920
10101
001 0 1
1 1 001
o 1 001
1 000 1
1920
2048 (2 MB)
2176
2304
2432
1 000 1
00001
11110
o1 1 1 0
10110
1
1
1
1
1
2048 (2 MB)
2176
2304
2432
2560
00001
11110
o1 1 1 0
10110
001 1 0
CONFIGURATION (MSV11-QA ETCH REVISION A)
Table 2·2
25
Starting and Ending Address Selection (Cont)
Desired
Ending
Address
SW2
Switch
6
In Kbyte
12345
001 1 0
11010
o1 0 1 0
1 001 0
00010
1
1
1
1
1
2688
2816
2944
3072 (3 MB)
3200
11100
1
1
1
1
1
3328
3456
3584
3712
3840
10100
00100
1 1 000
o 1 000
1
1
3968
4096 (4MB)
1 0000
00000
Desired
Starting
SW 1
Switch
Address
Position
In Kbyte
12345
2560
2688
2816
2944
3072 (3 MB)
3200
3328
3456
3584
3712
3840
3968
o 1 1 00
1 0 1 00
00100
1 1 000
o 1 000
1 0000
SW2
Switch
Position
Position
11010
o1 0 1 0
1 001 0
00010
11100
o1 1 0 0
1 = Off Position
o = On Position
NOTES: Switch S6 of SW1 is not used. For a memory starting address of 0,
switch S6 of SW2 should be set to 0 (on). For all other starting addresses,
switch S6 of SW2 should be off (1).
CONFIGURATION
(MSV11-QA ETCH REVISION C OR
LATER, MSV11-Q8 AND MSV11-QC)
3
3.1 GENERAL
This chapter contains information for configuring and installing the MSV11-QA
(etch revision C or later), the MSV11-QB and the MSV11-QC memory module.
Jumper and address switch setups are included. Hereafter, in this chapter
these variations will be referred to as the MSV11-Q.
NOTE: Configuration and installation for the MSV11-QA (etch revision A) is
provided in Chapter 2 of this manual.
3.2 CONFIGURING THE MSV11-Q
The MSV11-Q has one red LED to indicate parity errors. The module contains
the following jumpers (Figure 3-1).
• CSR register selection Oumpers J4 through J11)
• Test jumpers used by manufacturing (J1 through J3)
(do not remove)
• Battery backup (W1, W2, W3, W4)
• Test jumpers (chip select) used by manufacturing Uumpers J12 through
J 17) (do not remove)
27
28
CONFIGURATION(MSV11-QA, ETCH REVISION COR LATER, MSV11-QB, MSV11-QC)
J11,J9,J7,J5
5017547,01,C1
~
EEE3 ••-------:--
~
CSR REGISTER
SELECTION
J10, J8, J6, J4
J3
o
J2
J1
U
_.- - : - -
TEST JUMPER
(USED BY
MANUFACTURING,
DO NOT REMOVE)
SW2
I
=~} -STARTING ADDRESS
=
§
3
~
SWITCHES (S6 NOT USED)
=6
OFF ON
(COMPONENT SIDE)
SW1
1l=§5=
~
OFF
o
J17 J1a J15
J14 J13 J12
W3
t
4~i} ••-~-ENDING
ADDRESS
SWITCHES
ON
0
~
W1
~~\I-------..
TEST JUMPERS
(USED BY MANUFACTURING DO NOT REMOVE)
Figure 3-1
BATTERY BACKUP
JUMPERS
MSV11-Q Jumpers and Switches
The MSV11-Q has two DIP (dual in-line package) switch packs. Each DIP
switch pack consists of six switches. The two switch packs are used to set:
• Starting address.
• Ending address.
Figure 3-1 shows the physical iocation of the jumpers and switches. The
jumpers and switches are described in the following paragraphs.
CONFIGURATION (MSV11-QA ETCH REVISION C OR LATER, MSV11-Q8, MSV11-QC)
29
3.2.1 CSR Register Selection (Jumpers J4 through J11)
The MSV11-Q can provide up to 16 GSR register address selections when the
user installs or removes appropriate jumper blocks (Figure 3-2). Table 3-1
shows the jumper positions and the corresponding GSR register addresses.
Figure 3-2 shows the jumper settings for a CSR register address of 17772102
representing a second MSV11-Q installed.
J4
J5
J6
J7
J8
J9
J10
Jll
SH R-0004-85
Figure 3-2
Jumper Settings for
GSR Address of 17772102
30
CONFIGURATION (MSV11-QA ETCH REVISION C OR LATER, MSV11-QS, MSV11-QC)
Table 3-1
CSR Register Selection
Jumper Connections
J4
J10
J6
J8
to
to
to
to
Number CSR Memory J5
J11
J7
J9
CSR Register Address
1st
2nd
3rd
4th
5th
in
out
in
out
in
in
in
out
out
in
in
in
in
in
out
in
in
in
in
in
17772100
17772102
17772104
17772106
17772110
6th
7th
8th
9th
10th
out
in
out
in
out
in
out
out
in
in
out
out
out
in
in
in
in
in
out
out
17772112
17772114
17772116
17772120
17772122
11th
12th
13th
14th
15th
in
out
in
out
in
out
out
in
in
out
in
in
out
out
out
out
out
out
out
out
17772124
17772126
17772130
17772132
17772134
16th
out
out
out
out
17772136
If more than one CSR parity type of memory is installed in the system, use care
to ensure that no two modules have the same address.
3.2.2 Test Jumpers J1 through J3
Test jumpers on J1 through J3 are used by manufacturing and should not be
removed by the user (Figure 3-3). Jumper J1 is always connected to J2.
J3
J2
Jl
SH R-0005-85
Figure 3-3
Manufacturing Test Jumpers
CONFIGURATION (MSV11-QA, ETCH REVISION C OR LATER, MSV11-QB, MSV11-QC)
31
3.2.3 Battery Backup
The battery backup jumpers are shown in Figure 3-4. Figure 3-4A shows 0 ohm
jumpers W2 and W4 connected in a non-battery backed up configuration.
Figure 3-48 shows 0 ohm jumpers W1 and W3 connected for the battery
backup configuration. These are the only two valid combinations; for example,
jumpers W1 and W2 cannot be connected in the circuit at the same time. Other
illegal jumper configurations are W1 and W4; W2 and W1; and W2 and W3.
NOTE: On systems using backpanel pin <AE1> sspare 1 for signals other
than +5.0 V BBU, jumper W1 may be omitted when module is strapped for
battery backup operation. However, Digital Equipment Corporation recommends backpanel pin <AE1> be used as +5.0 V battery backup power in this
application. Refer to Paragraph 3.2.3 for additional information.
o
0
W4
W3
o
0
(A) NON-BATTERY BACKED UP
CONFIGURATION
(B)
BATTERY BACKUP
CONFIGURATION
SH R-0006-8S
Figure 3-4
Battery Backup
32
CONFIGURATION (MSV11-QA, ETCH REVISION C OR LATER, MSV11-QB, MSV11-QC)
3.2.4 Chip Select Jumpers
The chip select jumpers are J12 through J17 (see Figure 3-5). To select 64K
RAMs used in the MSV11-QA (etch revision C or later) memory module, jumper
J16 must be connected to J15 and jumper J14 must be connected to J13. To
select 256K RAMs used in the MSV11-Q8 and MSV11-QC memory modules,
jumper J17 must be connected to J16 and jumper J13 must be connected to
J12. All other jumper combinations are illegal and should not be attempted by
the user.
on
n
J17 J16 J15
J14 J13 J12
0
~jj-ffijj---A. MSVll-QA SELECT (64K RAMS)
noon
\ \\
rl\\\
\_\_\--.J L\_\_\
J17 J16 J15
J14 J13 J12
B. MSV11-QB/MSV11-QC SELECT (256K RAMS)
SHR-0007-B5
Figure 3-5 Chip Select Jumpers
CONFIGURATION (MSV11-QA ETCH REVISION C OR LATER, MSV11-QB, MSV11-QC)
33
3.2.5 Address Switches
There are two DIP switch packs, each containing six switches. DIP switch SW2
selects the starting address of the MSV11-Q. DIP switch SW1 selects the
ending address. Table 3-2 shows the switch settings for the starting addresses
and ending addresses. Switch 6 of SW2 (starting address) is not used. Switch 6
of SW1 (ending address) is turned on or enabled (0) for a starting address of all
O's and is turned off or disabled (1) for all other starting addresses.
Table 3-2
Starting and Ending Address Selection
Desired
Starting
Address
SW2
Switch
Position
SW 1
Switch
Position
Desired
Ending
Address
SW 1
Switch
Position
In Kbyte
1 2345
6
In Kbyte
1 2345
00000
1 1 111
1111
10111
00111
0
1
1
1
1
0
128
256
384
512
640
768
896
1024 (1 MB)
1152
o
110 11
o 1 011
1 001 1
000 1 1
11101
o1 1 0 1
128
256
384
512
640
11111
o1 1 1 1
10111
00111
110 11
o 1 011
768
896
1024 (1 MB)
1152
1280
1 001
000 1
1110
o1 1 0
1
1
1
1
1280
1408
1536
1664
1792
10 101
001 0 1
1 1 001
o 1 001
1408
1536
1664
1792
1920
10 10 1
001 0 1
1100 1
o 1 001
1 000 1
1920
2048 (2 MB)
2176
2304
2432
1 000 1
00001
11110
o1 1 1 0
10110
2048 (2 MB)
2176
2304
2432
2560
0000
1111
111
10 11
001 1
2560
2688
2816
2944
3072 (3 MB)
00110
11010
o 1 010
1 001 0
000 i 0
2688
2816
2944
3072 (3 MB)
3200
o
1
0
0
0
0
110 10
o 1 010
10010
000 1 0
11100
34
CONFIGURATION (MSV11-0A, ETCH REVISION C OR LATER, MSV11-0B, MSV11-0C)
Table 3-2
Starting and Ending Address Selection (Cont)
Desired
Starting
Address
SW2
Switch
Position
SW 1
Switch
Position
Desired
Ending
Address
SW 1
Switch
Position
In Kbyte
12345
6
In Kbyte
12345
3328
3456
3584
3712
3840
o 1 1 00
1 0 1 00
001 00
1 1 000
01 000
3968
4096 (4 MB)
1 0000
00000
3200
3328
3456
3584
3712
3840
3968
11100
o 1 1 00
1 0 1 00
001 00
1 1 000
o 1 000
1 0000
1 = Off Position
o = On Position
NOTES: Switch S6 of SW2 is not used. For a memory starting address of 0,
switch S6 of SW1 should be set to 0 (on). For al/ other starting addresses, switch
S6 of SW1 should be off (1).
UNPACKING AND INSTALLATION
4
4.1 GENERAL
This chapter describes unpacking, pre-installation, and installation procedures
for verifying proper system configuration for all variations of the MSV11-Q.
NOTE: This memory is static sensitive. Electro-static Discharge (ESD) precautions must be taken when handling this module outside of its protective
container. Use Velostat Kit 29-11762 when handling the module.
4.1.1 Unpacking and Inspection
The MSV11-Q is shipped in special packing cartons to protect the boards from
excessive mechanical shock, electrical shock, and vibration, and to give the
boards maximum protection during shipment. To unpack the memory, remove
any packing materials and visually inspect the memory board for physical
damage. Check all hardware attached to the board.
35
36
UNPACKING AND INSTALLATION
4.1.2
Pre-installation
CAUTION:
1. You must remove dc power from the backplane during module insertion or
removal.
2.
Be careful when replacing the memory module. Make sure that the component side of the module faces in the same direction as the other modules
on the system. The memory module, backplane, or both can be damaged if
the module is inserted backwards.
Before installing any MSV11-Q variation make sure the system is correctly
configured.
The pre-installation procedure is given in the following checklist.
1. Check if system power is hooked up correctly and make sure all cables
are securely attached.
2. Verify proper system operation.
3. Check if other memory is present and check the addressing range of the
memory.
4. Check the CSA address setting of the existing memory, and make necessary CSA jumper settings on the MSV11-Q module according to Table 2-1
for MSV11-QA (etch revision A), or Table 3-1 for MSV11-QA (etch revision
C or later), MSV11-QB and MSV11-QC. If no other memory exists in the
system, the memory module is factory set at the first CSA address
location.
5. If no other memory is present, set the starting address of the MSV11-Q to
O. If other memory is present, set the module starting and ending address
accordingly. (See Table 2-2 for MSV11-QA, etch revision A or Table 3-2
for MSV11-QA (etch revision C or later), MSV11-QB and MSV11-QC.)
6. Verify that your system (CPU, peripherals, backplane, and software) is
capable of supporting 22-bit addressing.
UNPACKING AND INSTALLATION
37
4.1.3 Installation
The MSV11-Q (all variations) is designed to install in backplanes that are wired
for LSI-11 /23, PDP-11/23, PDP-11/23 Plus, Micro/PDP-11 computer systems,
and MicroVAX I.
After verifying that the appropriate jumpers and switch settings are correct,
insert the MSV11-Q memory board into its designated slot.
CAUTION: Do not try to install or remove memory modules with dc power
applied to the backplane. Damage to the memory board may occur.
4.1.4 Module Checkout
When memory modules are installed, apply dc power and verify memory operation by running the system diagnostics; in particular, those that test the memory. (Refer to Chapter 6.)
FUNCTIONAL DESCRIPTION
5
5.1 INTRODUCTION
The MSV11-Q memory modules (all variations) interface with the LSI-11 bus.
The CPU and DMA devices can become bus master of the LSI-11 bus to
transfer or obtain data from memory. The memory is always a slave to
whatever device becomes bus master. Figure 5-1 shows the CPU and DMA
devices connected to memory via the LSI-11 bus.
Devices that are ready to use the LSI-11 bus must gain control of the bus
through the arbitration that takes place in the CPU. The device that wins the
arbitration is able to use the bus as soon as bus signals BSYNC and BRPLY
are negated. This device is now bus master and can initiate a bus cycle. The
types of bus cycles that can be performed are shown in Table 5-1.
All bus cycles are divided into three sequential events.
• Address cycle
• Data cycle
• Bus cycle termination
39
40
FUNCTIONAL DESCRIPTION
LSI-"
BUS
MA-7161
SHR-0330-84
Figure 5-1
Table 5-1
Typical System
Summary of Bus Cycles
Bus Cycle
Mnemonics
Description
DATI
DATO
DATOB
DATIO
Data
Data
Data
Data
DATIOB
Data word input/byte output
DATBI
DATBO
Data word block mode input
Data word block mode output
word input
word ouput
Byte output
word input/output
Function with Respect
to Bus Master
Read word
Write word
Write byte
Read word, modify,
write word
Read word, modify,
write byte
Block mode read
Block mode write
5.2 LSI-11 BUS SIGNALS AND DEFINITIONS
To transfer data, the bus master must generate the signals shown in Figure
5-2. The slave device (memory) receives the signals and initiates BRPL Y. This
starts a chain reaction to terminate the bus cycle. Table 5-2 gives the signal
names and definitions of the bus signals.
FUNCTIONAL DESCRIPTION
BDAL 21-00L
BBS7 L
BWTBT L
BSYNC L
BDOUT L
BDIN L
BRPLY L
BDCOKL---.....
MA-7331
SHR-0331-84
Figure 5-2
Table 5-2
MSV11-0 Memory Interface
Bus Signals
Bus
Pin
Mnemonics
Description
AA1
BIR05 L
Interrupt request priority level 5
AB1
BIR06 L
Interrupt request priority level 6
AC1
BDAL16 L
Extended address bit during
addressing protocol; memory error
data line during data transfer
protocol.
AD1
BDAL17 L
Extended address bit during
addressing protocol; memory error
logic enable during data transfer
protocol.
AE1
SSPARE1
On the MSV11-0A (etch revision A),
this pin is directly shorted to AV1
and is used for +5 V battery backup
power to keep critical circuits
alive during power failures.
(Alternate
+5 8)
41
42
FUNCTIONAL DESCRIPTION
Table 5-2
Bus
Pin
Bus Signals (Cont)
Mnemonics
Description
AF1
SSPARE2
SRUN
simultaneously
Special Spare - not assigned or
bused in Digital cable or backplane
assemblies; available for user
interconnection. In the highestpriority device slot, the processor
may use this pin for a signal to
indicate its RUN state.
AH1
SSPARE3
SRUN
simultaneously
Special Spare - not assigned or
bused in Digital cable or backplane
assemblies; available for user
interconnection. An alternate
SRUN signal may be connected in the
highest-priority set.
AJ1
GND
Ground - System signal ground and
dc return.
AK1
MSPAREA
Maintenance Spare - Normally
connected together on the backplane
at each option location (not bused
connection).
AL1
MSPAREB
Maintenance Spare - Normally
connected together on the backplane
at each option location (not bused
connection).
AM1
GND
Ground - System signal ground and
dc return.
FUNCTIONAL DESCRIPTION
Table 5-2
Bus
Pin
Bus Signals (Cont)
Mnemonics
Description
AN1
BDMR L
Direct Memory Access (DMA) Request
- A device asserts this signal to
request bus mastership. The
processor arbitrates bus mastership
between itself and all DMA devices
on the bus. If the processor is not
bus master (it has completed a bus
cycle and BSYNC L is not being
asserted by the processor), it
grants bus mastership to the
requesting device by asserting BDMGO
L. The device responds by negating
BDMR L and asserting BSACK L.
AP1
SHALT L
Processor Halt - When BHALT L is
asserted for at least 25 J,LS, the
processor services the halt
interrupt and responds by halting
normal program execution. External
interrupts are ignored but memory
refresh interrupts in LSI-11 are
enabled if W4 on M7264 and M7264-YA
processor modules is removed and
DMA request/grant sequences are
enabled. The processor executes the
ODT microcode and the console device
operation is invoked.
AR1
BREF L
Memory Refresh - Asserted by a DMA
device. This signal forces all
dynamic MOS memory units requiring
bus refresh signals to be activated
for each BSYNC L/BDIN L bus
transaction.
CAUTION: The user must avoid
multiple DMA data transfers (burst
or "hog" mode) that could delay
refresh operation. Complete refresh
cycles must occur once every 1.6
msec if required.
43
44
FUNCTIONAL DESCRIPTION
Table 5-2
Bus
Pin
Bus Signals (Cont)
Mnemonics
Description
AS1
+12 B
or
+5 B
+ 12 Vdc or +5 V battery backup power
to keep critical circuits alive
during power failures. * This signal
is not bused to BS1 in all Digital
backplanes. A jumper is required on
all LSI-11 Bus options to open
(disconnect) the backup circuit from
the bus in systems that use this
line at the alternate voltage.
AT1
GND
Ground - System signal ground and
dc return.
AU1
PSPARE 1
Spare (Not assigned. Customer usage
not recommended.) Prevents damage
when modules are inserted upside
down.
AV1
+5 B
+5V Battery Power* - This pin is
directly shorted to AE1 on the
MSV11-0A (etch revision A only), and
is a secondary +5 V power
connection.
BA1
BDCOK H
DC Power OK - Power supplygenerated signal that is asserted
when there is sufficient dc voltage
available to sustain reliable system
operation.
BB1
BPOK H
Power OK - Asserted by the power
supply 70 ms after BDCOK negated
when ac power drops below the value
required to sustain power (about 75
percent of nominal). When negated
during processor operation, a
power-fail trap sequence is
initiated.
BC1
SSPARE4
BDAL 18L
(on 022 only)
On the 022 Bus, SSPARE4 is bused
address line BDAL 18 and is
currently not used during data time.
FUNCTIONAL DESCRIPTION
Table 5-2
Bus
Pin
Bus Signals (Cont)
Mnemonics
Description
BD1
SSPARE5
BDAL19L
(on 022 only)
On the 022 Bus, SSPARE5 is bused
address line BDAL 19 and is
currently not used during data time.
BE1
SSPARE6
BDAL 20L
On the 022 Bus, SSPARE6 is bused
address line BDAL 20 and is
currently not used during data time.
BF1
SSPARE7
BDAL 21L
On the 022 Bus, SSPARE7 is bused
address line BDAL 21 and is
currently not used during data time.
BH1
SSPARE8
Special Spare - Not assigned or
bused in DIGITAL cable and backplane
assemblies; available for user
interconnection.
BJ1
GND
Ground - System signal ground and
dc return.
BK1
BL1
MSPAREB
MSPAREB
Maintenance Spare - Normally
together on the backplane at each
option location (not a bused
connection).
BM1
GND
Ground - System signal ground and
dc return.
BN1
BSACK L
This signal is asserted by a DMA
device in response to the
processor's BDMGO L signal,
indicating that the DMA device is
bus master.
BP1
BIR07 L
Interrupt request priority level 7
BRi
BEVNT L
Externai Event interrupt Request When asserted, the processor
responds (if PS bit 7 is 0) by
entering a service routine via
vector address 100a. A typical use
of this signai is a iine time ciock
interrupt.
45
46
FUNCTIONAL DESCRIPTION
Table 5-2
Bus Signals (Cont)
Bus
Pin
Mnemonics
Description
BS1
+12B
+ 12 Vdc battery backup power (not
bused to AS 1 in all Digital
backplanes). *
BT1
GND
Ground - System signal ground and
dc return.
BU1
PSPARE2
Power Spare 2 (not assigned a
function, not recommended for use).
If a module is using -12 V (on pin
AB2) and if the module is
accidentally inserted upside down in
the backplane, -12 Vdc appears on
pin BU1.
BV1
+5
+5 V Power - Normal +5 Vdc system
power.
AA2
+5
+5 V Power - Normal +5 Vdc system
power.
AB2
-12
-12 V Power* - -12 Vdc (optional)
power for devices requiring this
voltage.
NOTE: L81-11 modules that require negative voltages have an inverter
circuit (on each module) that generates the required voltage(s). Hence,
- 12 V power is not required with Digital-supplied options.
* Voltages normally not supplied by DIGITAL.
FUNCTIONAL DESCRIPTION
Table 5-2
Bus Signals (Cont)
Bus
Pin
Mnemonics
Description
AC2
GND
Ground - System signal ground and
dc return.
AD2
+12
+12 V Power - 12 Vdc system power.
AE2
BDOUT L
Data Output - BDOUT, when asserted,
implies that valid data is available
on BDAL <0: 15) L and that an output
transfer, with respect to the bus
master device, is taking place.
BOOUT L is deskewed with respect to
data on the bus. The slave device
responding to the SDOUT L signal
must assert BRPLY L to complete the
transfer.
AF2
BRPLY L
Reply - BRPLY L is asserted in
response to BDIN Lor BOOUT Land
during IAK transactions. It is
generated by a slave device to
indicate that it has placed its data
on the BDAL bus or that it has
accepted output data from the bus.
47
48
FUNCTIONAL DESCRIPTION
Table 5-2
Bus Signals (Cont)
Bus
Pin
Mnemonics
Description
AH2
BDIN L
Data Input - BDIN L is used for two
types of bus operation:
1.
When asserted during BSYNC L
time, BDIN L implies an input transfer with respect to the current bus
master, and requires a response
(BRPLY L). BDIN L is asserted when
the master device is ready to accept
data from a slave device.
2.
When asserted without BSYNC L, it
indicates that an interrupt operation
is occurring.
The master device must deskew input
data from BRPLY L.
AJ2
BSYNC L
Synchronize - BSYNC L is asserted
by the bus master device to indicate
that it has placed an address on
BDAL <21 :0> L. The transfer is in
process until BSYNC L is negated.
AK2
BWTBT L
Write/Byte - BWTBT L is used in two
ways to control a bus cycle:
1.
It is asserted at the leading edge of
BSYNC L to indicate that an output
sequence is to follow (DATO or
DA TOB), rather than an input
sequence.
2.
It is asserted during BDOUT L, in a
DATOB bus cycle, for byte
addressing.
FUNCTIONAL DESCRIPTION
Table 5-2
Bus Signals (Cont)
Bus
Pin
Mnemonics
Description
AL2
8!RQ4 L
Interrupt Request Priority Leve! 4
- A level 4 device asserts this
signal when its interrupt enable and
interrupt request flip-flops are
set. If the PS word bit 7 is 0, the
processor responds by acknowledging
the request by asserting BDIN Land
BIAKO L.
AM2
AN2
BIAKI L
BIAKO L
Interrupt Acknowledge - In
accordance with interrupt protocol,
the processor asserts BIAKO L to
acknowledge receipt of an interrupt.
The bus transmits this to BIAKI L of
the device electrically closest to
the processor. This device accepts
the interrupt acknowledge under two
conditions:
1.
The device requested the bus by
asserting BIRQx L.
2.
The device has the highest-priority
interrupt request on the bus at that
time.
If these conditions are not met, the
device asserts BIAKO L to the next
device on the bus. This process
continues in a daisy-chain fashion
until the device with the
highest-interrupt priority receives
the interrupt acknowledge signal.
AP2
BBS7 L
Bank 7 Select - The bus master
asserts this signal to reference the
I/O page (including that portion of
the I/O page reserved for
nonexistent memory). The address in
BDAL <0: 12> L when BBS7 L is
asserted is the address within the
I/O page.
49
50
FUNCTIONAL DESCRIPTION
Table 5-2
Bus
Pin
AR2
AS2
Bus Signals (Cont)
Mnemonics
BDMGI L
BDMGO L
Description
Direct Memory Access Grant - The
bus arbitrator asserts this signal
to grant bus mastership to a
requesting device, according to bus
mastership protocol. The signal is
passed in a daisy-chain from the
arbitrator (as BDMGO L) through the
bus to BDMGI L of the next priority
device (electrically closest device
on the bus). This device accepts the
grant only if it requested to be bus
master (by a BDMR L). If not, the
device passes the grant (asserts
BDMGO L) to the next device on the
bus. This process continues until
the requesting device acknowledges
the grant.
CAUTION: DMA device transfers must not interfere with the memory
refresh cycle.
AT2
BINIT L
Initialize - This signal is used
for system reset. All devices on the
bus are to return to a known,
initial state; i.e., registers are
reset to zero, and logic is reset to
state O. Exceptions should be
completely documented in programming
and engineering specifications for
the device.
AU2
AV2
BDALO L
BDAL1 L
Data/ Address Lines - These two
lines are part of the 16-line
data/address bus over which address
and data information are
communicated. Address information is
first placed on the bus by the bus
master device. The same device then
either receives input data from, or
outputs data to the addressed slave
device or memory over the same bus
lines.
FUNCTIONAL DESCRIPTION
Table 5-2
Bus Signals (Cont)
Bus
Pin
Mnemonics
BA2
+5
+5 V Power - Normal +5 Vdc system
power.
BB2
-12
-12 V Power* - -12 Vdc (optional)
power for devices requiring this
voltage.
BC2
GND
Ground - System signal ground and
dc return.
BD2
+12
+12 V Power - +12 V system power.
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2
BDAL2 L
BDAL3 L
BDAL4 L
BOAL5 L
BDAL6 L
BDAL? L
BDAL8 L
BDAL9 L
BDAL10 L
BDAL11 L
BDAL12 L
BDAL13 L
BDAL14 L
BDAL15 L
Data/Address Lines - These 14 lines
are part of the 16-line data/address
bus previously described.
Description
SPARES
Nomenclature
Pin Assignment
SSpare1
SSpare3
SSpare8
AE1
AH1
BH1
C'C' .... ,.. ........ t)
vvtJ Q1v "
1\1::1
1"'\1
I
MSpareA
AK1
MSpareB
MSpareB
MSpaieB
PSpare1
ASpare2
AL1
BK1
01
-I
DL.I
AU1
BU1
51
52
FUNCTIONAL DESCRIPTION
5.2.1 LSI-11 Bus Dialogues
The MSV11-Q memory module (all variations) responds to these dialogues:
DATI, DATO(B), DATIO(B), DATBO and DATBI. Table 5-3 explains which figure
to use with each dialogue.
Table 5-3
Dialogues to Perform Memory Data Transfers
Dialogue
Figure
DATO(B)
DATI
DATIO(B)
DATBO
DATBI
5-3
5-4
5-5
5-6
5-7
FUNCTIONAL DESCRIPTION
SLAVE
(MEMORY OR DEVICE)
BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
=
•
•
ASSERT BDAL <21 :00> L WITH
ADDRESS AND
ASSERT BBS7 L IF THE ADDRESS
IS IN THE 2044K - 2048K WORD RANGE
ASSE RT BSYNC L
~
~ DECODE ADDRESS
•
STORE "DEVICE SELECTED"
OPERATION
REQUEST DATA
• REMOVE THE ADDRESS FROM
BDAL <21 :00> L AND NEGATE
BBS7 L
• ASSERT BDIN L
~INPUTDATA
•
•
PLACE DATA ON BDAL <15:00> L
ASSERT BRPLY L
TERMINATE INPUT TRANSFER
• ACCEPT DATA AND RESPOND
BY NEGATING BDIN L
------OPERATION COMPLETED
- - - - - - . NEGATE BRPL Y L
TERMINATE BUS CYCLE
•
NEGATE BSYNC L
Figure 5-3
---------------
DATa or DATOS Sus Cycle
53
54
FUNCTIONAL DESCRIPTION
BUS MASTER
(PROCESSOR OR DEVICE)
SLAVE
(MEMORY OR DEVICE)
ADDRESS DEVICE/MEMORY
• ASSERT BDAL <21 :00> L WITH
ADDRESS AND
• ASSERT BBS7 L IF THE ADDRESS
IS IN THE 2044K - 2048K WORD RANGE
• ASSE RT BWTBT L (WR ITE CYCLE)
• ASSERT BSYNC L
~
DECODE ADDRESS
• STORE "DEVICE SELECTED"
OPERATION
OUTPUT DATA
• REMOVE THE ADDRESS FROM
BDAL <21:00> L AND NEGATE
BBS7 LAND BWTBT L
• PLACE DATA ON BDAL <15:00> L
• ASSERT BDOUT L
____________
TAKE DATA
•
RECEIVE DATA FROM BDAL
LINES
ASSERT BRPL Y L
TERMINATE OUTPUT TRANSFER
• NEGATE BDOUT L (AND BWTBT L
IF A DATOB BUS CYCLE)
~
• REMOVE DATE FROM BDAL <15:00> L
OPERATION COMPLETED
• NEGATEBRPLYL
TERMINATE BUS CYCLE
•
NEGATE BSYNC L
Figure 5-4
DATI Bus Cycle
FUNCTIONAL DESCRIPTION
BUS MASTER
(PROCESSOR OR DEVICE)
SLAVE
(MEMORY OR DEVICE)
ADDRESS DEVICE/MEMORY
• ASSERT BDAL <21 :00> L WITH
ADDRESS
(j
ASSERT BBS7 L iF THE ADDRESS
IS IN THE 2044K - 2048K WORD RANGE
• ASSERT BSYNC L
~
DECODE ADDRESS
• STORE "DEVICE SELECTED"
_____
OPERATION
REQUEST DATA
•
REMOVE THE ADDRESS FROM
•
BDAL<21:00>L
ASSERT BDIN L
~
INPUT DATA
• PLACE DATA ON BDAL <15:00> L
• ASSERT BRPL Y L
TERMINATE INPUT TRANSFER
_________
• ACCEPT DATA AND RESPOND
~
BY TERMINATING BDIN L
~
COMPLETE INPUT TRANSFER
•
REMOVE DATA
~.
NEGATE BRPL Y L
OUTPUT DATA
~
• PLACE OUTPUT DATA ON BDAL<15:00> L
•
(ASSERT BWTBT L IF AN OUTPUT
•
BYTE TRANSFER)
ASSERT BDOUT L
~
TAKE DATA
•
RECEIVE DATA FROM BDAL LINES
• ASSERT BRPL Y L
TERMINATE OUTPUT TRANSFER
________
•
REMOVE DATA FROM BDAL LINES
• NEGATE BDOUT L
~
~ OPERATION COMPLETED
TERMINATE BUS CYCLE _______________
•
NEGATE BSYNC L
(AND BWTBT L IF IN
A DATIOB BUS CYCLE)
Figure 5-5
DATI or DATIOB Bus Cycle
•
NEGATE BRPL Y L
55
56
FUNCTIONAL DESCRIPTION
SLAVE
(MEMORY OR DEVICE)
BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
• ASSERT BDAL <21 :00> L WITH
ADDRESS AND BWTBT L ____________
• ASSERT BSYNC L
.
DEVICE ADDRESS
• STORE "DEVICE SELECTED"
OPERATION
"A"
OUTPUT DATA
• REMOVE THE ADDRESS FROM
BDAL <21 :00> L AND NEGATE
BWTBT L
• PLACE DATA ON BDAL <15:00> L
• ASSE RT BDOUT L
_______
TAKE DATA
_______ •
RECEIVE DATA FROM BDAL LINES
• ASSERT BRPL Y LAND BREF L
(IF BLOCK MODE DEVICE)
• ASSERT BRPLY L ONLY. B REF
IS ASSERTED WHEN NOT ON
16-WORD BOUNDARY.
TERMINATE OUTPUT TRANSFER
• NEGATE BDOUT L
•
REMOVE DATA FROM BDAL <15:00> L
~ OPERATION COMPLETED
•
IF BREF L WAS ASSERTED WHEN
BDOUT L NEGATED, THEN GO TO
"A" ELSE:
TERMINATE CYCLE
• NEGATE BSYNC L
Figure 5-6
DATBO Bus Cycle
NEGATE BRPL Y LAND BREF L
FUNCTIONAL DESCRIPT!ON
BUS MASTER
(PROCESSOR OR DEVICE)
57
SLAVE
(MEMORY OR DEVICE)
ADDRESS DEVICE/MEMORY
• ASSERT BDAL <21:00> L WITH
ADDR ESSES
_______________
• ASSERT BSYNC L
DEVICE ADDRESS
• STORE "DEVICE SELECTED"
OPERATION
"A"
REQUEST DATA
•
REMOVE THE ADDRESS FROM
BDAL <21 :00> L
• ASSERT BDIN LAND BBS7 L IF
BLOCK MODE READ IS DESI RED
~
INPUT DATA
PLACE DATA ON BDAL<15:00>L
• ASSERT BRPLY LAND BREF L IF
DEVICE CAN PERFORM BLOCK
MODE TRANSFERS
• ASSERT BRPLY L ONLY. B REF
ASSERTED WHEN NOT ON
16-WORD BOUNDARY.
~.
TERMINATE INPUT TRANSFER
• ACCEPT DATA AND RESPOND
BY NEGATING BDIN L
•
IF BREF L IS ASSERTED.
PREPARE FOR NEXT DATA INPUT
TRANSFER
•
IF BREF L IS NOT ASSERTED. ~
OR NO FURTHER TRANSFER IS
DESIRED NEGATE BBS7 L
OPERATION COMPLETED
• NEGATE BRPL Y LAND BREF L
IF BREF L WAS ASSERTED WHEN
BDIN L NEGATED. THEN GO TO
"An ELSE:
•
•
TERMINATE BUS CYCLE
NEGATE BSYNC L
Figure 5-7
DATBI Bus Cycle
58
FUNCTIONAL DESCRIPTION
5.3 FUNCTIONAL DESCRIPTION OF MEMORY MODULE
Figure 5-8 is a functional block diagram of the MSV11-Q memory module. The
following paragraphs describe the basic functions.
5.3.1 Xcvrs (Transmit - Receive)
The Xcvrs are an interface between the Q-bus and the memory array and allow
memory to transmit or receive:
Address,
Data, and
Control signals.
In addition, they also provide parity checking and generation, and output data
storage.
5.3.2 Address Logic
The memory module contains starting address and ending address switches to
set the starting and ending memory addresses. Both starting and ending
address switches must be set; otherwise, false accesses above the memory
range of addresses may occur. For example, on the MSV11-QA module, if the
starting address is set to 0, and only half of the memory array is used, the
ending address switch should be set to 0.5 Mb. A set of four CSR jumpers
provide for selection of 1 of 16 possible CSR addresses.
5.3.3 Control Signal Xcvrs
The control signal Xcvrs receive and transmit all control signals from the
Q-bus. The memory module decodes the control signals to determine what
type of access is to occur. The signals entering and leaving the control signal
Xcvrs are the normal Q-bus protocol signals previously described.
5.3.4 Address Select Logic
The address select logic detects whether the MSV11-Q is addressed via the
Q-bus. If the address select logic decides that the Q-bus address corresponds
to the MSV11-Q, a module select (BDSEL) signal is generated. This signai is
applied to the cycle arbitration logic to arbitrate the type of cycle.
I
\J
1\
)
V
PARITY
CONTROL
I
r--
BDALO;1.BDAL17
PARITY DIN
1\
11
DATA &
ADDRESS
XCVRS
~~
CSR OUT
1
(/)
~
en
...J
BDAL18BDAL21 ~
V
POUT
1
~
CSR
CONTROL
EXTENDED
f--ADDRESS
RCVRS
n
1\
V
PIN
Y
..
r---
co
"
PARITY DOUT
DATA IN 00-015
C~
;t
~
ADDRESS
MUX
1\
11
MOS
MEMORY
ARRAY*
MAO-MA8J\
-n'
DOUT
DATA OUT 00-015
I
.....I---
ADDRESS
SELECT
DIN
RAS
CAS
WEN
.o=:::::~~";:::..c:::;";Sa.
REF
"TI
C
Z
BSEL7
BREF
(')
BBS7
-I
BDIN
BDOUT
BWTBT
6
z
»
r
MSEL:
BSYNC
CONTROL
SIGNAL
RCVRS
-
i---
CONTROL SIGNALS
BINIT
BREPLY
1\
11
CYCLE
ARBITRATION
I
~
o
m
MEMORY
CONTROL
en
(')
:JJ
'""0
,.
-I
* MSV11·QA 512 KW X 18
MSV11·QB 1024 KW X 18
MSV11·QC 2048 KW X 18
Figure 5-8
MSV11-Q Functional Block Diagram
SHR-0382-84
6
z
60
FUNCTIONAL DESCRIPTION
5.3.5 Cycle Arbitration
Control signals are supplied to the cycle arbitration logic which arbitrate
between a CSR access, a memory access, or refresh cycle. If the access is a
CSR access, appropriate timing signals are generated to read or write the
CSR. If the cycle is a memory access (read, write, write byte, or block mode),
RAS (row address strobe) and CAS (column address strobe) signals are generated to enable the row and column address to occur. If the access is a refresh
cycle, only RAS is generated. The refresh logic consists of a timer which
requests that a memory refresh be performed every 12 p,S. The refresh logic
also generates a refresh address defining the rows to be refreshed. This
occurs asynchronously. All RAMs are refreshed at the same time. Eight RAS
pulses are generated to allow one row in each bank of RAMs to be refreshed at
the same time. Then the refresh address is incremented and the next row in
each bank is refreshed on the next REF REQ until all rows are refreshed. There
are 128 rows to be refreshed on the MSV11-QA. There are 256 rows to be
refreshed on the MSV11-Q8 and MSV11-QC. The total refresh time is 535
nanoseconds for each refresh cycle.
5.3.6 Memory Access
During a memory cycle, the Q-bus address is compared with the address
space defined by the address switches on board the module. If the addresses
match, the address is then transferred to the RAM array via the address
multiplexer. First, the row address is latched and the required RAS signal is
asserted. Then, the memory control logic switches to provide the column
address and CAS is asserted.
During block mode, the address is incremented at the end of each memory
cycle. The cycle is restarted, and a new address is supplied to the RAMs. Up to
16 words can be transferred in rapid succession in this mode.
FUNCTIONAL DESCRIPTION
61
5.3.7 Parity
During a write cycle, parity is generated on each byte written to the memory
array; consequently, two parity bits are generated for each memory word (one
parity bit for upper byte and one for lower byte). During a read cycle (DATI)
parity is checked in the parity control logic. If a parity error occurs, a red LED
on the board turns on and the error address is strobed into the CSR. Bits 11
through 21 of the address containing the parity error are stored in the CSR in
bit locations 5 through 11, as described below (Figure 5-9).
15
14
13
12
11
10
09
08
07
06
05
------------------y~-----------------ERROR ADDRESS
PARITY
ERROR
WRITE
WRONG
PARITY
EXTENDED
CSR READ
ENABLE
PARITY
ERROR
ENABLE
MA-7169
SHR-0383-B4
Figure 5-9
CSR Bit Allocation
To determine the failed address, perform the following:
1. Read the CSR. This provides bits 11 through 17 of the failed address.
2. Set bit 14 of the CSR (extended CSR read enable).
3. Read the CSR. CSR bit locations 5 through 8 store bits 18 through 21 of
the failed address. These bits are referred to as extended error address
bits.
4. Reset bit 14.
62
FUNCTIONAL DESCRIPTION
5.4 CONTROL AND STATUS REGISTER (CSR) BIT ASSIGNMENT
The control and status register (GSR) in the MSV11-Q allows program control
of certain parity functions, and contains diagnostic information if a parity error
has occurred. The GSR is assigned an address and can be accessed by a bus
master via the LSI-11 bus. Some GSR bits are cleared by assertion of BUS INIT
L. This Signal is asserted for a short time by the processor after system power
has come up, or in response to a reset instruction. Figure 5-9 shows the GSR
bits. They are described in the following paragraph.
Bits 1, 3, 4, 12, and 13
These bits are not used and are always
read as logical zeros. Writing into these bits
has no effect on the GSR.
Bit 0
Parity Error Enable - If a parity error occurs
on a DATI or DATIO(B) cycle to memory,
and bit 0 is set (1), then BDAL 16 Land
BDAL 17 L are asserted on the bus simultaneously with data. This is a read/write bit
reset to zero on power up or BUS INIT.
Bit 2 Maintenance Only
Write Wrong Parity - If this bit is set (1) and
a DATO or DA TOB cycle to memory occurs,
wrong parity data is written into the parity
MOS RAMs. This bit can be used to check
the parity error logic as well as failed
address information in the GSR.
•
Bits 3, 4
Bit 2 is a read/write bit reset to zero on
power up or BUS INIT.
Not used.
FUNCTIONAL DESCRIPTION
Bits 05 through 11
63
Error Address Bits - If a parity error occurs
on a DATI or DATIO(B) cycle, then A 11
through A17 are stored in GSR bits 5
through 11 and bits A18 through A21 are
latched" The 128K word machines (18-bit
address) require only one read of the GSR
register to obtain the failed address bits.
GSR bit 14 = 0 allows the logic to pass A 11
through A17 to the LSI-11 bus. A 2048K
word machine (22-bit address) requires two
reads. The first read (CSR bit 14 = 0) sends
contents of GSR bits 5 through 11. Then the
program must set GSR bit 14 (1). This
enables A18 through A21 to be read from
GSR bits 05 through 08.
The parity error addresses locate the parity
error to a 1K segment of memory. These
bits are read/write and are not reset to zero
via power up or BUS INIT. If a second parity error is found the new failed address is
stored in the GSR.
Bit 14
Extended GSR Read Enable - The use of
this bit was explained in the error address
description.
Bit 14 = 0, always for 128K word machine
Bit 14 = 0, first read on 2048K word
machine
Bit 14 = 1, second read on 2048K word
machine
Bit 14 is a read/write bit reset to 0 on power up or BUS INIT.
64
FUNCTIONAL DESCRIPTION
Bit 15
Parity Error - This bit, when set, indicates
that a parity error has occurred. The bit
then turns on a red parity LED on the module. This provides visual indication of a parityerror.
Bit 15 is a read/write bit. It is reset to zero
via power up or BUS INIT and remains set
unless rewritten or initialized.
MAINTENANCE
6
6.1 GENERAL
The maintenance procedures in this chapter apply to the MSV11-Q memory
module. To perform corrective maintenance on this module, the user must
understand basic operation of the MSV11-Q memory module as described in
the previous chapters. This knowledge, together with diagnostic testing knowledge, will help the user isolate MSV11-Q malfunctions.
CAUTION: ALL power must be off before installing or removing modules.
Always be sure the component side of the memory faces in the same direction
as the other modules within the LSI system.
NOTE: This memory is static sensitive. ESD (electro static discharge) precautions must be taken when handling the module outside of the protective
container. Use Velostat kit 29-11762 when handling the module.
65
66
MAl NTENANCE
6.2 PREVENTIVE MAINTENANCE
Preventive maintenance pertains to specific tasks, performed at intervals, to
detect conditions that may lead to performance deterioration or malfunction.
The following tasks can be performed along with other preventive maintenance
procedures for the LSI computer system, but are not mandatory on a scheduled basis.
1. Visual inspection
2. Voltage measurements
3. Diagnostic testing
6.2.1 Visual Inspection
Inspect the modules and backplane for broken wires, connectors, or other
obvious defects.
6.2.2 Power Voltage Check
Once primary power has been turned on, check the dc power voltage at the
backplane. Refer to Table 1-3 for MSV11-QA, (etch revision A). Refer to Table
1-4 for MSV11-QA (etch revision C or later), MSV11-Q8, and MSV11-QC.
6.3 DIAGNOSTIC TESTING
Memory diagnostic programs to test the MSV11-Q memory modules are available from Digital.
For MicroVAX systems, the memory test (EHXMS) is part of MicroVAX Diagnostics I contained on the diagnostic diskette.
For fault isolation in other 22-bit systems and 18-bit systems use the
MAINDEC-11 CVMSA (22-bit system) diagnostic.
Detailed operating instructions and program listings are included with each
diagnostic software kit.
6.3.1 MicroVAX Memory Diagnostic 1 (EHXMS)
The MicroVAX Memory diagnostic 1 (8L-T856C-DE) verifies the correct functioning of MSV11-Q memory modules. The lowest acceptable revision for
EHXMS is Version 1.3.
WARNING:
memory.
This diagnostic will eliminate the current contents of system
MAl NTENANCE
67
Each MSV11-QA memory module has 1 megabyte of MOS memory using 64K
memory chips.
Each MSV11-QB memory module has 2 megabytes of memory using 256K
memory chips (half-populated). Each MSV11-QC memory module has 4
megabytes of memory using 256K memory chips (full populated).
This diagnostic identifies a memory board that failed. Run this diagnostic when
the operating system detects memory errors or when intermittent program
failures suggests a problem in the memory subsystem.
Run this diagnostic after first running the CPU diagnostic to verify that the CPU
is functioning correctly.
The Memory diagnostic (EHXMS) is distributed on the diskette labeled
"MicroVAX Diagnostics 1." The diagnostic requires 30 kilobytes of memory to
run. It takes approximately 48 minutes to run the diagnostic with parity test
enabled. Without parity test enabled, run time is 28 minutes. The default occurs
with parity enabled. To disable parity, use EHXMS>DISABLE PARITY.
6.3.1.1 Bootstrapping Procedure - The memory diagnostic is a standalone
diagnostic and is bootstrapped by inserting the diskette into the RX50 diskette
drive n and typing:
»>B/100 DUAn (where n = 0 through 7)
Bootfile: [SYSO.SYSMAINT]EHXMS.EXE
6.3.1.2 Operation - Once the diagnostic is bootstrapped, it produces a header message that contains the Memory diagnostic version number. You are then
prompted to issue commands that control the diagnostic.
6.3.1.3 Command Syntax - You may issue commands either in upper- or
lowercase. They are displayed in uppercase. Before ending a line with a Carriage Return, you may enter any of the editing characters shown in Table 6-1.
The convention AU or AR means that you hold down the CTRL (Control) key
and press the U or R key at the same time.
Commands and option keywords may be abbreviated to the first letter. The
commands are summarized in Table 6-2 and then fully described.
68
MAINTENANCE
Table 6-1
Control Keys
Key
Function
Delete
Backspaces one character and deletes it. A backs lash (\) is
printed, followed by the deleted character and another
backslash.
You may use "u instead of Delete to delete an entire line.
The text you have typed on the current line is ignored and a
Carriage Return is performed. You may then reenter the line.
Performs a Carriage Return and redisplays the current line.
The cursor is left at the end of the line so that you can
continue typing input. Use "R when you have deleted a lot of
characters on the line and cannot easily read its contents.
Table 6-2 Command Summary
Command
Function
DISABLE
Disables a feature selected with the ENABLE command.
ENABLE
Selects a test feature.
HELP
Produces information about using the memory diagnostic commands.
MEMORY_SIZE
Specifies the amount of available memory.
START
Starts the test sequence.
VIEW
Lists the status of all ENABLE and DISABLE command
options.
MAl NTENANCE
69
6.3.1.4 Using the Commands - Commands may be issued in any order, but
the START command must be the last command issued. No testing occurs until
the START command is issued.
All commands are optional except the MEMORY_SIZE and START commands. An informational message is issued if you specify a START command
without first specifying the size of memory. The most common way to use this
diagnostic is to issue a MEMORY_SIZE command followed by a START command. This begins run of the full diagnostic with all of the default ENABLE and
DISABLE options.
When a START or START 0 command is issued, the diagnostic begins testing
at the first test and continues until all tests run or an error is found. If test 2
(Memory Configuration Test) is run, and a memory map is requested, a short
pictorial map is output on the console terminal. This map may be used to detect
installation errors and is also used to map a failing address to the appropriate
MSV11-Q memory module. At the end of the last test, the diagnostic relocates
itself in memory (if the RELOCATE option is enabled) and the test sequence is
repeated on the memory that the diagnostic occupied. After this second test
sequence, the diagnostic is moved back to the memory it previously occupied.
Figure 6-1 shows this concept.
At the end of the test pass, a message is output indicating that testing is
completed and the entire test is then repeated.
If a test number is specified with the START command, testing starts at the
specified test, and continues executing that test (looping) until you stop it.
Typing ftC (CTRL/C) any time during the test process causes the diagnostic to
halt testing (software halt) and return the command prompt. The ENABLE and
DISABLE command options and the memory size are saved. You may rerun
the same test sequence by issuing a START command on its own, or you may
change the commands to run the test in a different way. The HALT pushbutton
on the system unit front control panel provides a hardware halt. This action is
not recommended unless the user understands the diagnostic and the various
implications.
70
MAl NTENANCE
END OF
INSTALLED
MEMORY
ALREADY
TESTED
START OF
INSTALLED
MEMORY
BEFORE DIAGNOSTIC
RELOCATION
AFTER DIAGNOSTIC
RELOCATION
MEMORY OCCUPIED BY THE DIAGNOSTIC
MEMORY UNDER TEST
SHA-0384-84
Figure 6-1
Memory Diagnostic Relocation
MAINTENANCE
71
Figure 6-2 shows a sample diagnostic run. The test system has 2 megabytes
(2048 kilobytes) of memory (one MSV11-QA configured to start at physical
address 0, and one MSV11-PL configured to start at physical address
00100000 and one MSV11-PL configured to start at physical address
00180000) (hex notation).
6.3.1.5 Test Procedure - Memory must be contiguous in the physical
address space and the first memory module installed must be jumpered to start
at physical address O. The diagnostic produces an optional memory map that
provides a picture of how memory modules have been installed. This map
correlates a failing memory location to a particular memory module. The map is
a matrix of 256 elements, one element for each possible 16 kilobyte memory
element in the 22-bit memory address space. The map is organized in four
rows of 64 columns; each row represents 1 megabyte of memory. The row and
column headings may be used to form the starting physical address of the 16
kilobyte element in memory. The row headings provide the most significant 2
bits of the 22-bit physical address. They are represented as 32-bit hexadecimal
numbers in the actual map output, with five placeholding X's for the 20 least
significant bits (five hexadecimal digits) of the memory address.
The five least significant hexadecimal digits may be read down vertically as the
column headings.
For example, the physical base address of the memory described by the
intersection of row two and column four is 0010COOO (001 X XOOO + OCOOO).
The address range is from the base address for 16 kilobytes, or from
0010COOO to 0010FFFF inclusive.
In each memory element of the matrix there is a flag describing the status of
memory at that location. The entry is any of the following.
A blank - signifying that no memory is installed at that address.
A hexadecimal digit - containing the memory controller number associated
with that memory.
A ? - signifying that more than one memory controller is specified (this indicates a configuration error).
An * - signifying that non-MSV11-QA memory, such as MRV11-D PROM, is in
the bank.
EHXHS>STA
Testing started.
He.or~
Hap:
OOOX XOOO
001X XOOO
002X XOOO
003X XOOO
100001111222233334444555566667777 88889999AAAABBBBCCCCDDDDEEEEFFFFI
1048C048C048C048C048C048C048C048C 048C048C048C048C048C048C048C048CI
+--------------------------------+--------------------------------+
1000000000000000000000000000000001000000000000000000000000000000001
+--------------------------------1------------------------.--------+
1111111111111111111111111111111111222222222222222222222222222222221
+--------------------------------+--------------------------------+
1
1
I
+--------------------------------+-------------------------------_.+
I
1
1
+--------------------------------+--------------------------------+
Ke~:
<SPACE>
O-F
?
*
He.or~
Hellor~
Hellor~
No
responds in this 16 Kb bank.
controller nu.ber
Error - .ore than one .e.or~ controller.
Non-HSV11 .e.or~ in this bank.
.e.or~
He.or~
.odule 0 is an HSV11-Q and contains 00000000 to 00100000 (CSR = 772100)
lIodule 1 is an HSV11-PL and contains 00100000 to 00180000 (CSR
772102)
.odule 2 is an HSVll-PL arid contains 00180000 to 00200000 (CSR = 772104>
Each co.plete pass of this diaSinostic takes about 96 lIinutes.
Disablins parit~ test ins (via ['ISABLE PARITY) reduces this to 56 .linutes.
End of test pass 1, no errors detected.
End of test pass 2, no errors detected.
End of test pass 3, no errors detected.
End of test pass 4, no errors detected.
End of test pass 5, no errors detected.
End of test pass 6, no errors detected.
End of test pass 7, no errors detected.
End of test pass 8, no errors detected.
End of test pass 9, no errors detected.
End of test pass 10, no errors detected.
End of test pass 11, no errors detected.
Figure 6-2 Sample Diagnostic Run for MSV11-QA/MSV-11 P
s:
~
Z
-f
m
Z
»
z
()
m
MAINTENANCE
73
For example, in the example map output, the entry for 00190000 is 2, signifying
that memory is contained on the third memory card (controller 2) on the
system.
At the end of the map, a summary is printed. This summary shows which
memory modules control which memory ranges, and the type of memory used.
6.3.1.6 Error Messages - Whenever the diagnostic finds an error it produces
an error message. The format of the error message depends on whether the
error is caused by an invalid command entered by you, or an error in the
memory under test.
Error messages produced as a result of incorrect input have the format:
EHXMS - [text]
The message test can be:
EHXMS - Command [command name] is unknown. Try HELP for some
information.
EHXMS - The [command name] command takes no arguments. Excess user
input [input] ignored.
EHXMS - The [command name] command accepts an optional decimal number. [text] is not decimal.
EHXMS - The [command name] command requires an argument.
EHXMS - [command name] is not a valid DISABLE or ENABLE option
keyword. Try HELP for help information.
EHXMS - Test number [number] is incorrect. Test numbers range from 1 to 12.
EHXMS - The memory size specified is incorrect; valid memory sizes range
from 256 kilobytes to 4096 kilobytes.
EHXMS - The memory size specified is incorrect; valid memory sizes are
multiples of 256 kilobytes.
74
MAINTENANCE
Error messages produced as a result of an error in the memory under test are
listed if the MESSAGE option is specified with the ENABLE command.
NOTE: The default is to have messages enabled. The messages have the
format:
EHXMS - Error during test [number] subtest [number] [testname], [subtestname] [test]
The first line of the error message identifies the test and subtest numbers of
the test item that failed.
The second line of text supplies the test and subtest names.
The third line of the error message is a description of the error detected. The
message text can be:
Data error at location [location]; expected [data], received [data]
Memory Parity error detected testing location [location]
Memory Timeout error detected testing location [location]
Memory does not respond from [location] to [location]
Memory module [module] did not respond to any memory addresses
Memory module with CSR at [address] is misconfigured; CSRs must be
contiguous.
Memory size incorrect; expected [number] kilobytes, actually found [number]
kilobytes
Memory size of [number] kilobyte is not a multiple of 256 kilobytes
There are addressing conflicts present; see map for more details
Unexpected Machine Check (reason = [number]) testing location [location]
MAINTENANCE
75
First 256 kilobytes of memory not present
Interrupt/exception/trap via SCB offset [offset] testing location [location]
The fol!owing error message requires that you run the CPU diagnostic, recheck
the memory and replace any faulty memory modules. If the fault persists you
may need to replace the CPU.
Unexpected trap or exception or interrupt
Via SCB vector [vector]
Return PC would be [number]
6.3.2 MSV11-Q DIAGNOSTIC (LSI-11 BUS)
The CVMSAA diagnostic tests the MSV11-Q memory on the LSI-11 bus. This
program has the ability to test memory from address 000000 to address
17757777. It does so using:
1. Unique addressing techniques.
2. Worse case noise patterns, and
3. Instruction execution throughout memory.
6.3.2.1 Hardware Requirements - The following hardware is needed to run
CVMSAA.
LSI-11/2,
LSI-11/23 bus family processors
Minimum of 32 kilobytes of memory.
Optional Hardware
Any parity memory control module
KTF11 memory management
76
MAl NTENANCE
6.3.2.2 Software Requirements - The smallest unit of memory this program
recognizes is 16 kilobytes. If any address in a 16 kilobyte bank causes a time
out trap, the program ignores that entire bank of memory. The program tests
memory in 16 kilobyte banks, unless it is the last 8 kilobytes before the I/O
page or last 12 kilobytes in a 60 kilobyte system.
The program exercises the vector portion of memory (locations 0 - 776) in
exactly the same manner as the rest of memory.
This means that the results are unpredictable if:
•
•
•
•
Memory management is not available or is disabled (SW12=1)
Program is relocated out of bank 0
Locations 0 - 776 are selected for test
Unexpected hardware trap occurs
6.3.2.3 Hardware Restrictions - It is recommended not to mix 18-bit memories with 22-bit memories.
6.3.2.4 Related Documents and Standards - Refer to these documents as
needed.
Programming Practices - Document Number 175-003-009-01
PDP-11 MainDEC Sysmac Package - MainDEC-11-DZQAC-C5-D
Applicable Memory System Maintenance Manual
Applicable Circuit Schematics
6.3.2.5 Diagnostic Hierarchy Prerequisites - Before running this program,
run a CPU diagnostic to verify the functionality of the processor and PDP-11
instruction set. For LSI-11 /23:CJ KDB Diag (latest revision); for LSI11/2:CVKAA Diag (latest revision)
If memory management is to be used, then also run the KTF11 diagnostic
CJKDA.
6.3.2.6 Assumptions - This program assumes correct operation of the CPU
and the memory management option (if used).
MAl NTENANCE
77
6.3.2.7 Loading the Program - Load the program using XXDP or any standard absolute loader. At starting address 200: Normal program execution proceeds. At starting address 204: Program is restarted using previously selected
parameters.
6.3.2.8 Special Environments - If the program is run in automatic mode
under ACT11 or APT11 the program is done after the first pass. Also, the
program does not relocate to test the lower 16 kilobytes of memory after the
first pass.
6.3.2.9. Program Options - The software switch register (location 176) is
used for all operational switch settings. The user can type CTRL G (AG) to
allow switch register changes during program execution.
SW15
SW14
SW13
SW12
up ................. HALT ON ERROR
up .............. '" LOOP ON TEST
up ................. INHIBIT ERROR TYPEOUT
up ................. INHIBIT MEMORY MANAGEMENT (INITIAL
START ONLY)
SW11 = 1 or up ................. INHIBIT SUBTEST ITERATION (NOT USED)
SW10 = 1 or up ................. RING BELL ON ERROR
SW9 = 1 or up ................ '" LOOP ON ERROR
SW8 = 1 or up ................... LOOP ON TEST IN SWR<4:0>
SW7 = 1 or up ................... INHIBIT PROGRAM RELOCATION
SW6 = 1 or up ................... INHIBIT PARITY ERROR DETECTION
SW5 = 1 or up ................... INHIBIT EXERCISING VECTOR AREA
LOCATIONS (0-1000)
=
=
=
=
1 or
1 or
1 or
1 or
6.3.2.10 Execution Times - Execution time is dependent on type of memory
and amount of memory. The following are worse case run times with MOS
memories.
For Parity Memory
Full Pass:
Approximately 40 minutes for
1024 kilobytes
78
MAINTENANCE
6.3.2.11 Error Reporting - There are a total of 31 (octal) types of error reports
generated by the program. The following describes some of the key column
heading mnemonics for clarity.
pc=
Program counter of error detection code
(V/PC=PfPC)
V/PC =
Virtual program counter. This is where the error
detection code can be found in the program listing.
P/PC =
Physical program counter. This is where the error
detection code is actually located in memory.
TRP/PC =
Physical program counter of the code which caused
a trap.
MA=
Memory address
REG =
Parity register address
PS
Processor status word
=
IUT =
Instruction under test
SIB =
What contents should be
WAS =
What contents were (was)
6.3.2.12 Error Halts - With the 'Halt on Error' switch (SW15) not set, there are
several programmed 'Halts' in the program.
1. In the error trap service routine for unexpected traps to vector 4, one
occurs if a second trap to 4 occurs before the error report for the first has
had a chance to print out.
2. In the relocation routine, if the program is relocated back to the first 16
kilobytes of memory and the program code was not able to be transferred
properly.
MAl NTENANCE
79
3. In the case of error reporting and there is no terminal to allow the information transfer.
4. In the power fail routine, if the power up sequence was started before the
power down sequence had a chance to complete itself.
5. Failures to find a meaningful map in the memory mapping routine or any
of the address control routines.
6.3.2.13
Sub-test Summaries - The following briefly describes the tests.
Section 1: Address Tests
These tests verify the uniqueness of every memory address.
Test 1 writes and reads the value of each memory word address into that
memory location. After all memory has been written, all locations are checked
again.
Test 2 writes the byte value of each address into that byte location and checks
it.
Test 3 writes the complement of each word address into that location and
checks it.
Test 4 writes the 8K bank number into each byte of that bank and checks it.
Test 5 writes the complement of the bank number into each byte of that bank
and checks it.
Section 2: Worst Case Noise Tests
These tests apply maximum stress to the various types of PDP-11 MOS
memories.
Test 6 and 7 allow the operator to select a single word data pattern (SA=204)
and scope on either the writing (DATO) in test 6 or the reading (DATI) in Test 7
of that data.
Location: .CONST:O should be changed if a different Single word data pattern
is considered.
80
MAl NTENANCE
Test 10 writes and then checks a series of single word patterns designed to
stress parity memory.
Test 11 writes all memory with 1's in every bit and then "ripples" a "0" through
it.
Test 12 writes all memory with O's in every bit and then "ripples" a "1" through
it.
Test 13 writes wrong parity in each byte of memory and checks that the parity
detection logic works. This test is skipped for non-parity memory.
Test 14 writes "random" program code through memory and checks it.
Section 3: Instruction Execution Tests
This group of tests places instructions in the memory under test, then executes
the instructions, and finally, checks that they are executed correctly.
Test 15 executes an instruction which does a DATI and a DA TO on the memory
under test.
Test 16 executes an instruction which does a DATI and a DATOS on the low
byte of memory under test.
Test 17 executes an instruction which does a DATI and a DATOS on the high
byte.
Test 20 executes an instruction which does a DATIO and a DATO.
Test 21 executes an instruction which does a DATIO and a DATOS on the low
byte.
Test 22 executes an instruction which does a DATIO and a DATOS on the high
byte.
MA! NTENANCE
81
Section 4: MOS Tests
Test 23 writes a pattern of 000377 through memory, then complements it
addressing downward, complements the new pattern addressing upward,
complements the third pattern addressing upward and finally complements this
new AB patterns addressing downward.
Tests 24 and 25 write a checkerboard through memory, stall for 2 seconds,
and then verify that no data has changed.
6.3.2.14 Toggle-In-Program 1 - The following is a Toggle-In-Memory
Address Test. This test is useful when an address selection failure is suspected involving the first 16 kilobytes of memory. This program writes the value of
each address into itself starting with the lower limit (200) and continuing to the
upper limit. After all addresses have been written, each address is checked for
the correct contents, starting with the upper limit and continuing to the lower
limit.
Location
Contents
Mnemonic
Comment
10
12
012700
000200
MOV #200,RO
14
010001
MOV RO,R1
;GET FIRST ADDRESS
;TO TEST
;(EXAMPLE START
ADDRESS)
;SAVE IN R1
16
20
020037
000176
1$: CMP RO,@#SWR
22
001403
SEQ 2$
24
010010
MOV RO,(RO)
26
30
32
34
005720
000772
010004
020001
TST (RO)+
BR 1$
2$: MOV RO,R4
3$: CMP RO, R1
36
40
42
44
46
001767
024000
001774
000000
000772
SEQ 1$
CMP -(RO),RO
SEQ 3$
HALT
SR 3$
;CHECK UPPER LIMIT
;(IN SOFTWARE SWITCH
REGISTER)
;BRANCH IF AT UPPER
LIMIT
;LOAD VALUE INTO
ADDRESS
;STEP TO NEXT ADDRESS
;LOOP UNTIL DONE
;SAVE UPPER LIMIT
;CHECK IF AT LOWER
LIMIT
;SRANCH IF DONE
;CHECK DATA WRITTEN
;BRANCH IF OK
;ERROR
;LOOP BACK
82
MAINTENANCE
6.3.2.15 Toggle-In-Program 2 - The following is also a Toggle-In-Program
and is used with Toggle-In-Program 1 for more complete address testing. This
program writes the complement value of each address into itself starting with
the upper limit and continuing to the lower limit. After all addresses have been
written, each address is checked for the correct contents, starting with the
lower limit address and continuing to the upper limit. Toggle in the following
patches to the program above.
This is the patch to Toggle-In-Program 1.
Location
36
Contents
Mnemonic
Comment
001404
SEQ 4$
;SRANCH TO PROGRAM
#2
These are the additions to Toggle-In-Program 1.
Location
50
52
54
Contents
010402
005142
020201
Mnemonic
4$: MOV R4,R2
5$: COM -(R2)
CMP R2,R1
56
60
001375
020204
SNE 5$
6$: CMP R2,R4
62
001755
SEQ 1$
64
66
70
72
74
76
010203
005103
020322
001772
000000
000770
MOV R2,R3
COM R3
CMP R3,(R2)+
SEQ 6$
HALT
SR 6$
Comment
;GET UPPER LIMIT
;COMPLEMENT ADDRESS
;CHECK IF AT LOWER
LIMIT
;LOOP UNTIL DONE
;CHECK IF AT UPPER
LIMIT
;GO TO PROGRAM 1 IF
DONE
;GET VALUE OF ADDRESS
;COMPLEMENT VALUE
;CHECK ADDRESS
;SRANCH IF OK
;ERROR
;GO CHECK NEXT
ADDRESS
MAl NTENANCE
83
6.4 DIGITAL'S SERVICES
Maintenance can be performed by the user or by Digital. Digital's maintenance
and on-site services are described in Chapter 1 of the Microcomputer
Processor Handbook (EB-18451-20).
6.4.1 Digital Repair Service
Digital Field Service offers a range of flexible service plans.
ON SITE SERVICE offers the convenience of service at your site and insurance
against unplanned repair bills. For a small monthly fee you receive personal
service from our Service Specialist. Within a few hours the specialist is dispatched to your site with equipment and parts to give you fast and dependable
maintenance.
BASIC SERVICE offers full coverage from 8 a.m. to 5 p.m., Monday through
Friday. Options are available to extend your coverage to 12-, 16-, or 24-hour
days, and to Saturdays, Sundays, and holidays.
DECservice offers a premium on-site service that guarantees extra-fast
response and nonstop remedial maintenance. We don't leave until the problem
is solved, which makes this service contract ideal for those who need uninterrupted operations.
Under Basic Service and DECservice all parts, materials, and labor are covered
in full.
CARRY-IN SERVICE offers fast, personalized response, and the ability to plan
your maintenance costs for a smaller monthly fee than On-Site Service. When
you bring your unit to one of 160 Digital Servicenters worldwide, factory-trained
personnel repair your unit within two days (usually 24 hours). This service is
available on selected terminals and systems. Contact your local Digital Field
Service Office to see if this service is available for your unit.
Digital Servicenters are open during normal business hours, Monday through
Friday.
DEC mailer offers expert repair at a per use charge. This service is for users
who have the technical resources to troubleshoot, identify, and isolate the
module causing the problem. Mail the faulty module to our Customer Returns
Center where the module is repaired and mailed back to you within five days.
84
MAINTENANCE
PER CALL SERVICE offers a maintenance program on a noncontractual, time-
and-materials-cost basis. This service is available with either On-Site or
Carry-In service. It is appropriate for customers who have the expertise to
perform first-line maintenance, but may occasionally need in-depth support
from Field Service.
Per Call Service is also offered as a supplementary program for Basic
Service customers who need maintenance beyond their contracted coverage hours. There is no materials charge in this case.
On-Site Per Call Service is provided on a best effort basis, with a normal
response time of two to three days. It is available 24 hours a day, seven
days a week.
Carry-In Per Call Service is available during normal business hours, with a
two to three day turnaround.
For more information on these Digital service plans, prices, and special rates
for volume customers, call one of the following numbers for the location of the
Digital Field Service office nearest you.
Digital International Field Service Information Numbers
U.S.A.
Canada
United Kingdom
Belgium
West Germany
Italy
Japan
France
1-(800)-554-3333
(800)-267 -5251
(0256)-57122
(02)-242-6790
(089)-9591-6644
(02)-617 -5381/2
(03)-989-7161
1-6873152
Denmark
Spain
Finland
Holland
Switzerland
Sweden
Norway
430-1005
91-7334370
90-423332
(01820)-34144
01-8105184
08-987350
2-256422
INDEX
o
A
Access and cycle times, 5,6
Address logic, 58
Address switches, 24, 33
Airflow, 12
Altitude, 12
B
Backplane, 3
Backplane pin utilization, 13
Battery backup, 3
Block mode enable, 21
Bootstrapping procedure, 67
DATSI bus cycle, 57
DATSO bus cycle, 56
DATI bus cycle, 54
DATIOS bus cycle, 55
DATO bus cycle, 53
DECmailer, 83
Diagnostic
MicroVAX, 66
MSV11-Q, 75
Diagnostic run
Sample, 71
Diagnostic testing, 66
E
c
Carry-In service, 83
Column address strobe, 60
Command syntax, 67
Configuration, 1, 17
CSR, 3
CSR bit assignment, 62
CSR address selection, 19, 27
CSR enable, 21
Cycle arbitration, 60
Ending address, 17, 24, 28
Error halts, 78
Error messages, 73
Error reporting, 78
Execution times, 77
Extended error address enable,
22
H
Humidity,
12
85
86
INDEX
R
Installation,
Refresh, 12
Related documents, 15, 76
Repair service, 83
Row address strobe, 60
37
J
Jumpers,
17
s
L
LSI-11 bus, 39
LSI-11 bus dialogues,
Starting address, 3, 17, 24, 28, 33
Software requirements, 76
52
T
M
Temperature, 11, 12
Tests
address, 79
worst case noise, 79
instruction execution, 80
MOS, 81
toggle in memory address,
toggle in program, 82
Test procedure, 71
Memory access, 60
Module, 3
Module checkout, 37
p
Parity, 61
Parity control circuitry, 3, 4
Parity error, 4, 61
Parity error detection enable,
Per-Call service
on site, 84
carry-in, 84
Power, 3,7-11
Power voltage check, 66
Pre-Installation, 36
Preventive maintenance, 66
Printset, 15
Program loading, 77
Program options, 77
u
18
Unpacking, 35
Using the commands,
69
v
Visual inspection,
Voltage, 7
Voltage pins, 8
66
x
XCVRS,
58
81
Digital Equipment Corporation. Shrewsbury, MA 01545
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