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OEM COMPUTERS

SBC 41616K PROM/ROM

EXPANSION BOARD

HARDWARE REFERENCE MANUAL

$5.00

SBC 416

16K PROM/ROM BOARD

HARDWARE REFERENCE MANUAL

",.

Copyright

©

1976

Intel Corporation

3065

Bowers Avenue

Santa Clara, California

95051

98-265A

'---

"

,--_.'

SBC 416

16K PROM/ROM EXPANSION BOARD

HARDWARE REFERENCE MANUAL

Copyright

No part

©

1976 by Intel Corporation.

All rights reserved.

of this publication may be reproduced, stored in a retrieval system, or transmitted, in means, electronic, any form or by any mechanical, photocopying, recording, or otherwise, without the prior written permission of Intel

Corporation.

Intel Corporation assumes no responsibility for the any circuitry other than circuitry use of embodied in an Intel product.

No other circuit patent licenses are implied.

i

---

.

SBC

416

16K PROM/ROM BOARD

TABLE OF CONTENTS

Page

1.0 FUNCTIONAL ORGANIZATION ·

2.0

THEORY OF OPERATION

1

3

2.1

2.2

PHYSICAL MEMORY IMPLEMENTATION

MEMORY ADDRESS DECODING

2.2.

1

. .

.

.

. ·

"GROUP BIAS ADDRESS" JUMPERS

2.2.2

CHIP SOCKETS

.

. .

.

. . .

·

2.2.3

"ROM RESIDENT ENABLE" SWITCH

· · ·

·

2.2.4

2.2.5

"RAM NOT OVERLAPPED" SWITCH

"WORD WIDTH SELECTION" SWITCH

·

·

· ·

· ·

·

·

·

·

·

· ·

·

·

· ·

·

· ·

· ·

·

·

·

2.2.6

"GROUP ENABLE/DISABLE" SWITCH

2.3

TIMING CONTROL

2.4

LOGIC SCHEMATIC

· .

.

• .

.

3.0

HARDWARE INSTALLATION

.

3

3

3

8

8

8

9

9

10

.

·

.

· 12

16

3.1

INSTALLATION OF SWITCHES AND JUMPERS

3.2

INSTALLATION

OF

BOARD

16

. 17

3.3

POWER REQUIREMENTS

• • 20

3.4

PIN LISTS

• • • 20

4.0 OPERATING CHARACTERISTICS .

4.1

AC CHARACTERISTICS

4.2 DC CHARACTERISTICS

• 20

• • • • • • • • • • • • 20

• • • 20 i i

........

-

..

~.

~.

Figure

1

2

3

4

5

LIST OF FIGURES

FUNCTIONAL BLOCK DIAGRAM .

SCHEMATIC - PRINTED WIRING

ASSEMBLY . .

. .

SCHEMATIC - 16K PROM/ROM

MEMORY BOARD

BOARD CONNECTORS

TIMING DIAGRAM . . .

. . .

.

. . .

Page

13

19

21

2

5

~ Table

1

2

6

7

3

4

5

LIST OF TABLES

Page

MEMORY LOCATION OF A PROM/ROM

CHIP IN X GROUP

·

·

.

CHIP IN Y GROUP

DC POWER REQUIREMENTS

Pl CONNECTOR PIN LIST

P2 CONNECTOR PIN LIST

AC CHARACTERISTICS

DC CHARACTERISTICS

.

.

.

.

·

·

·

·

· ·

· ·

·

·

·

. .

.

6

7

22

23

24

25

26 i i i

tt·

16K

PROM/ROM BOARD

The PROM/ROM Board has been designed to provide up to 16,384

(16K)

X 8-bit words of PROM/ROM storage for 8-bit computer systems or 8,192

(8K)

X

16-bit words of storage for 16-bit computer systems.

Up electrically programmable can be inserted on the board.

bits of storage.

to sixteen 8708 read-only-memory erasable

(PROM) and devices

Each PROM provides 1024

X

8

Intel's 2708 PROMs or 8308 ROMs can also be used on the board in place organized into two each any bank address can of block

8K

the within

8708s.

memory banks.

the

The 16 PROM elements are be set independently.

The address

8K

range of

Each bank can occupy maximum

64K

selected address block must, however, begin on range.

The boundary.

The address assigned to the two banks on the board can coincide.

X

This configuration can be used to implement 8,192

16-bit PROM storage capacity.

This capability is implemented on a single 12 in. X 6.75 in. printed circuit board.

The SBC 416 requires DC power at levels of +5VDC, +12 VDC and

-5VDC.

This manual is supplemental to the

Hardware Reference Manuals

SEC

(e.g.,

Reference Manual, 98-230).

80

SBC series

80/10 of OEM

Hardware iv

,il'

Page

1

1.0

FUNCTIONAL ORGANIZATION

For descriptive purposes, the 16K PROM/ROM viewed as consisting of four functional blocks: board

Memory storage block

Address control block

Timing and control block

Byte selection block

These functional units are illustrated in Figure 1.

can be

The memory erasable storage and block electrically consists of up to 16 8708 programmable-read-only-memory

(PROM) elements.

(8,192 bits).

Each

The

8708

16 switch-selectable banks of stores elements

8,192

1024 X 8

(8K)

are

X bits organized

8

bits of in of data two

PROM storage.

o

00

INH2/

MROCI

CCLX/

L

"

I

I

I

I f

------AO-ORE-SS7EC-ODE-RS-LQC-X-----',

U

...

...

~

ADDRESS

BtJTFERS

~

~

ADRD-F

.....t

ADR9- 9

I ? I

...

1

..

; ,

BIAS ADDI

GROUP ENABLE

ROM RESIDENT

RAM NOT OVERLAP

• I -

CHI? SELECTS

~

---l

~

I

I

I

F

~""""""'''''''''''''''''''''''''''-''I~

I

. - - - - - - - ,

MEMORY BLOCK

I

I

8X-BYTES

MEMORY

I

I t t

I

~

I

I

8 BITS DATA

I

~

~

I

. :

I I

DATA

BUFFERS

I

I

I

I

I

I

I

I

I -,--...

I

I

I

«1/16 BITS/:,ORD

SELECT t-~~~l«-

~

I

I

I

I

I

I ...

~_-~::::::::.:;

I ....

.....---t...'"'

.)

BIAS ADOI

GROUP ENABLE

ROM RESIDENT

RAM SOT OVP.Rt,AP

CHIP SELECTS

...

~

~

-n

J

I

I

I I...

L aX-BYTES

MEMORY

-J

I

I

I

I

I

I

I

I

,

I

L

...

...

;>

~

DATA

BUFFERS

_

I-

_ _ _ _ ..J

I

I

I -

I

I

I

I

L ...

.-_

...

-

....

----

-

----

~

-".....--------------------...

L.

-----___It__---..

-

=

8i16

BIT WORD

-------t---~

ROM

RESIDENT

..:_--

~----+~------------------

.... - - - - - ,

RAM--..........

IT

I

I

I

=_ wtl

J-

I

I

I

~

...-..

RAM

NOT OVERLAP

~.~~~~~R~Y~~~A~D~~_~~~~~~:D~-----------------~:~------

~:~C~~~.,~~7~~~~~.~r~~~OC~K~-

_ _

----------------~-~ ~MmG

BUF-

~

~

~~SnR~~~~ l

I

~

I

I

I

,

XACK/

~

DAT8/-DATF/

DATI/-CAT7/

INHl/ t-e1

SlJ

\Q

0

...J

1

2I~.:..AN..2.~~L~~

.....

-

FIGURE 1

FUNCTIONAL BLOCK DIAGRAM

.)

oj}

~.

.

~

Page

3

2.0 THEORY OF OPERATION

In this section, we provide a detailed theory description for the

16K

PROM/ROM board.

of operation

Figure 2 shows the printed wiring assembly of sheets) for the board.

The schematic (3 the 16K PROM/ROM board is provided in Figure 3 located in Section 2.4 .

2.1 PHYSICAL MEMORY IMPLEMENTATION

The actual memory on·the 16K PROM/ROM board consists up of to sixteen 8708 programmable-read-only-memory (PROM) elements.

capacity.

memory banks.

Each 8708 element has a 1024 X 8-bit

The 16 PROM elements are partitioned into two

Each bank includes 8,192 (8K) X 8 bits of storage (8 PROM elements).

The address ranges for the two banks are jumper-selectable as described in Section

2.2.

In addition, one bank can be used with 8,192 words in the other bank to implement 8K X 16-bit word storage; as previously described.

The 8708 PROMs are schematic, Figure

3.

shown on sh·eet 2 of the board

ROM elements 8308 with CS2/ option

(negative true chip select 2) may also be used.

2.2 MEMORY ADDRESS DECODING

The address control block is the 16-bit address output responsible for decoding by the CPU during PROM/ROM read operations.

follows: the

These 16 three address bits are used as highest bits (ADRF, ADRE AND ADRD) are group bias address; the next three bits

ADRB, AND ADRA) select 1 of 8 chips in a group;

(ADRC, and the remalnlng 10 bits (ADR9 through ADRO) address one of the

1024 memory locations in a chip.

The memory space of the board is divided into two groups

X group and Y group.

The following jumpers and switches are used to select a desired mode of operation.

2.2.1 GROUP BIAS ADDRESS JUMPERS

The starting address of X called group bias address.

group or Y group is

The group bias address is jumper-programmable by setting the the jumper pads called jumpers on

"BIASED ADD SELECTION".

The bias address of the X group is set by X3, X2 an~ X1 jumpers, while the bias address of the Y group is set by Y3, Y2 and Y1 jumpers.

Selecting

1 or 0 with each jumper determines the value of a group bias address bit.

See Table 1 for memory

Page 4 locations for PROM/ROMs in X-group and Table 2 for

PROM/ROM memory locations in Y-group.

Exam~: as COOO,

To set the group bias address of X group the jumpers X3, X2 and X1 should be programmed as "1", "1" and "0", respectively, because COOO

X

at

=

1 (8000)

+

1 (4000)

+

0 (2000).

group memory space now begins at COOO, and

DFFF.

The ends

Example: as EOOO, programmed as bee a use

E

000

=

" 1" ,

1 ( 80

"1" a

0)

+ and " 1" ,

1 (4 000 )

+ respec ti vely,

1 (2 00

0) •

Th e

Y group memory space then begins at EOOD, and ends at

FFFF.

To set the group bias address of Y group the jumpers Y3, Y2 and Y1 should be

Note that addresses jumpers.

there that are can

Consequently, be

8 possible selected the memory by group the space bias three of a group must begin at one of the boundaries 0000,

2000, 4000, 6000, 8000, AOOO, COOO and EOOO.

,

....

,

• ••

•Qdooo

,,'.an

\'rh~

••

••••••••••

~.'\I

10 - R " " " ,

(II

"'OT

WAS ADO +0000" lW'

• •••••••••

O·~II~A"'OfQ -"'w~

, . t-t a s•• -.

• ••••

..1t••

8OM ...

~uo

••

1'11~,.a"'"A''OO''t'''I·oa·IO·''''·'''.'''

• • • • • • • • •

~>

.....

~:: ~~: ~~

••,

4.00.0000.. IW'

• • • • • • •

.....

• • • • •

••

.'J1"I',11111J

CJ4

cC3

& 2 7 " .

.0.. .

etc.

_

-'-0

A~! A2~.~.~efUU"l.

~cC)

-AM

",--~

.......

~.....

X

"0·

'J

""0

".1 ADO

J

c.o

U't)

~

;1:==' yt.lOOO..

IIAI AOOu •••an

:

•..

(4

p

c

I&AI AOO_ •

"Lfcr~·Y2·" (3t~

'OfDOO:t==·C

t...- .

~

••

.2""

C 17

::~~::::] llla20gr)M . . .

•••••:.....

·

A29

16. PROM/ROM MEMORy

c· ·

. p

'w

COOl

.. . .. .. . .

AhC

t:::J •

•• '.2

txJUI •

.

~

~C

• 0

AI.'O·,

all

::.mn

(lllJllIllJlllllllliillllllllll

NOTE:

~LESS

OTHERWISE SPECIF'EO

I. ASSEMBLY

{Z::>MARK DASH

M>.

IS 1000 Gtfo

~"'N q • xx.

POSITION SHOWN.

(5::>

[i::>

APP\.Y

A~'

COMPOU....

O

(I'T.M

C ...

a.T~I""~.

~RAP f=~O'" 11~

-u

W)

0 ... -01

81:rWa... u

~~IOU o......

v.

FIGURE 2

*

SCHEMATIC PRINTED WIRING ASSEMBLY

16K PROM/ROM MEMORY BOARD

SBC 416

IS

"-02" VERSION

TABLE 1

MEMORY LOCATION OF A

PROM/ROM

CHIP IN X-GROUP

X-GROUP BIAS

ADDRESS

JUMPERS: X

3

X

2

X l

000

001

010 all

100

101

110

I I I

A

23

0000

2000

4000

6000

8000

AOOO

COOO

EOOC

SWI

A

1s

0400

2400

4400

6400

8400

A400

C400

E400

SW2

0800

2800

4800

6800

8800

A800

eaoo

E800

SW3

A

IO

X-GROUP

PROM/ROM CHIP

SOCKET NUMBER

A

4

A

22

A

14

A g

A

3

ceoo

2COO

4COO

6COO

8COO

ACOO

CCOO

ECOO

SW4

1000

3000

5000

7000

9000

BOOO

0000

FOOO

SW6

1400

3400

5400

7400

9400

B400

D400

F400

SW7

1800

3800

5800

7800

9800

B800

D800

F800

SW8 lCOO

3COO sCOO

7COO

9COO

BCOO

DCOO

FCOO

SW9 .... "ROM Resident

Enable" Switch for X-Group

NOTE: sws, SWIO are used as "RAM NOT OVERLAPPED" switch.

J

J

"

Ir-

J

J

~

'tfJ

J

)

TABLE 2

MEMORY LOCATION OF A PROM/ROM CHIP IN Y-GROUP

Y-GROUP BIAS ADDRESS

JUMPERS: Y3 Y2Yl

000

001

010 all

100

101

110

I I I

A

21

0000

2000

4000

6000

8000

AOOO

COoo

EOOO

SWI

A

I3

0400

2400

4400

6400

8400

A400 e400

E400

SW2

0800

2800

4S00

6800

8800

A800 e800

Eeoo

AS

Y-GROUP PROM/ROM CHIP SOCKET NUMBER

A

2

A

20

A

12

A

7

Al oeoo

2COO

4COO

6COO

8COO

ACOO

ecoo

ECOC

1000

3000

5000

7000

9000

BODO

0000

FOOO

1400

3400

5400

7400

9400

B400

D400

F400

1800

3800

5800

7S00

9800

B800

0800

F800

ICOO

3COO

SCOO

7COO geoo

BCOO

Deoo

Feoo

SW3 SW4 SW6 SW7 SW8

SW9 +"ROM Resident

Enable" Switch for Y-Group

NOTE: SWS,

SWIO are used as

"RAM NOT OVERLAPPED" switch.

Page

8

2.2.2 CHIP SOCKET

The next three address bits indicate eight chip sockets within a group.

of a chip is determined by the difference magnitude of the between the chip address and the group bias address.

one of the

The location

Exam~: chip

Assume the memory space begins at for X group is COOO.

of a

Then, the difference

PROM/ROM

D400, and the group bias address

=

D400

COOO

=

1400.

This PROM/ROM chip should be located at the chip socket labelled as "BIAS ADD

+

1400".

2.2.3 ROM RESIDENT ENABLE SWITCH

When a group bias address is jumper programmed for a group, a memory space of

8K

bytes is occupied by the group.

space is

For many often

PROM/ROM chips.

applications, partially

For example, only 2K this populated by bytes memory some are occupied by two bytes remain unused.

PROM/ROM chips and the other

It may be desired to

6K

allow this unused memory space memory types, such as RAM.

to be used by other

If a PROM/ROM overlaps a RAM at a specific memory location, the PROM/ROM should take higher priority over RAM.

In other words, a memory access to the memory location will access PROM/ROM rather than

Therefore, user the overlapped RAM.

must indicate to PROM/ROM memory board that there specific socket.

exists a PROM/ROM chip on a

This is accomplished by setting

"ROM RESIDENT ENABLE" switches.

A "ROM Resident Enable" switch number is to each PROM/ROM socket.

labelled as "BIAS ADD

+

For example, the assigned socket

1400" is also labelled with

"SW 7".

When a PROM/ROM chip is inserted into this socket, the ROM RESIDENT ENABLE switch SW 7 should be set to "ON" position.

See Tables 1 and 2.

If a socket is not occupied by a PROM/ROM chip, the associated "ROM RESIDENT ENABLE" switch of the socket should be reset to "OFF" position, for enabling that 1K byte memory space to be used by other types of memory.

2.2.4 RAM NOT OVERLAPPED SWITCH

If a PROM/ROM locations, overlaps a RAM at some memory the PROM/ROM board must be so notified

~

~

$.

~

Page

9 by resetting the associated "RAM switch.

NOT OVERLAPPED"

The SW5 and SW10 "ROM are used as

RESIDENT ENABLE" switches

"RAM NOT OVERLAPPED" switches.

SW5 must be reset to "OFF" position, if PROM/ROM and

RAM are overlapped at some memory locations within the 4K byte labelled as: memory space of the four sockets

BIAS ADD

BIAS ADD

BIAS ADD

BIAS ADD

+

+

+

+

0000

0400

0800

OCOO

SW5 should be set to "ON" position, if PROM/ROM and RAM are not overlapped at any of the memory locations within this memory space.

Similarly, SW10 must be reset to if

"OFF" position,

PROM/ROM and RAM are overlapped at some memory locations within the 4K byte memory space four sockets labelled as: of the

BIAS ADD

BIAS ADD

BIAS ADD

BIAS ADD

+

+

+

+

1000

1400

1800

1COO

SW 10 should be set to "ON" position, if and RAM are

PROM/ROM not overlapped at any of the memory locations within this memory space.

2.2.5 WORD WIDTH SELECTION PLUG

If the "Word Width Selection" plug is inserted

J1, the board is operated at 16 bit mode.

at

Two bytes will be delivered to the data bus read operation.

If the for each

"Word Width Selection" plug is loaded at J2, the board is operated bit mode.

at 8

One byte will be delivered to the data bus for each read operation.

When the board is programmed at 16 bit

"Group mode, the

Bias Address", of X group and Y group must be identical.

Otherwise, respond to a read access.

the board will not

2.2.6 GROUP ENABLE/DISABLE SWITCH

The X group and Y group of PROM/ROM can be enabled or disabled by flipping two switches.

These two

P~ge 10 switches are not physically mounted on the

If this part no.

feature is

101A can be installed on the board board.

required, a switch of "C

K"

area designated as "84" and "85".

If the switch is at

DISABLE position, the board will not respond to a read group.

access to any memory location within the

2.3 TIMING CONTROL

When a ROM is accessed, the timing and control block is notified by the address decoder logic to a) send out the

RAM inhibit signal and b) enable the "Transfer

Acknowledge" (XACK) delay counter to count the number of clock pulses by which the

XACKI

will

XACKI

must be delayed.

then be sent upon, either the counter

The valu~ being equal to the code in the "Access Time Switch", if the of 15.

"RAM NOT OVERLAPPED" switch is set, or to the count

Exam.Ql~: code of

If the user sets the access time

4 and the "RAM position then the transfer acknowledge switches

NOT OVERLAP" is set at "on"

(XACK/)

will to be sent shortly after the falling edge of the fourth

Bu t if the swi tch is not set at" on" posi tion, the

CCLK/.

XACKI

signal

15th shall

CCLK/.

be delayed until the falling edge of the

The period of

CCLKI

from the SBC

80/10

is 0.101

microseconds, making the timing of the above example

0.404 microseconds, and 1.5 microseconds, respectively.

The control logic is also responsible for indicating the bytes selection logic when to enable to the data buffers.

In the even t the ROM board is opera ting in 8 bit mode and, two chips in X and Y groups have mistakenly been assigned the same location, the logic will prevent the read ~ycle.

control

(For example, in order to avoid erratic operatio'n or damage to drivers,

INH11

is sent; XACK is not sent).

the data

Whenever a ROM is assigned to locations already occupied by RAM, the RAM board must be prevented from driving the data accessed.

bus whenever

This is the overlapped accomplished by locations the ROM are module sending an inhibit signal

However,

(INH1/)

as both RAM and ROM upon board being selected.

receive the address code and command simultaneously and some delay with possible for the respect

~AM to

INH11

command happens address, with it is to begin an irreversible operation.

~,

~

~

~

-#

r

.s

r

@ r r

~.

,"

ce;

...

Page

11

One of the four RAM overlap switches the

(4) indicates to timing logic that the current read operation is for

ROM and that INH1/ has to be maintained terminated its internal process.

until RAM has

In systems with dynamic RAMs, such as SBC

Board the longest time occurs begun a refresh cycle prior to the refresh operation must then

016 16K RAM if the RAM module had read command.

The be completed, before the read operation transfer is executed aknowledge is sent).

(at the end of which,

The maximum access delay imposed by this operation is 1.5

this state: time, INH1/ otherwise must

XACKI

be microseconds.

During maintained in the asserted may be resulted which will cause a possible conflict.

Generation of INH1 by the control logic is based on receiving of any RSn/ signal.

the

This signal is in turn generated when the address contained in the address lines.

of a resident ROM is

The signal path is A29,

1, 2,

4,

5, -6 and A29 10, 12, 13,

8 (Figure 3).

If INH2 is active, however, no occur in memory read the ROM module.

command (MRDC) action is required to

If INH2 is not active and a occurs, a module select signal is generated (MS/.

The signal path is A25

4,

2,

5 -6; A16 3-4).

When signal RSO or RS1 is active while MS/ is true,

"low byte enable" is generated, the

(signal path is A36 Pin

12, high

12,

13, - 11 ; A36 Pin s 1, 2- 3 ; Fig ur e 3, Sh e e t 3.

The byte signal path is A36 pins

15 and 11.

Note that A36

4,

9, 10, 8 and A34 pin

5-6 detects that both bytes are selected.

If the established by the presence of the paths across shorting plug,

J2 output of this gate prevents generation of MS signal.

is the

When MS is false (low) the delay counter is held cleared when MS is true, this counter (A19) will count the clock pulses.

A26 the to an~ counter the

A17 form a four bit comparator.

switches and RAMOV/ is not

The output present.

comparator output will be true .(A17 pin 8 is low).

of is matched with the setting of the "access time" code switches.

equal

A high at the counter will compare with a closed switch when all four bits are equal

The

If RAMOV/ is active (low), no output occurs.

The counter

A18, will proceed to the count of 15 which satisfies

1, 2, 4, 5 -6.

When either of these signals (A17 pin 8 or 18 pin 6) is true, the count enable at the pins

5 and 6 counter input goes false (signal path A25 pins

Page 12

12, 13,

9,

10,8; A16

pins

5

and

6).

If

RAM

access is not overlapped

A17

pin time comparator enabled.

11

will be high and the

The counter stops when its output is identical to the code in the "access time" switches.

If

RAM

is overlapped

A17

will have no output and the satisfied counter

A18

(code proceeds

15).

to the fixed code that

Note that as

MSI

becomes true,

A34

will be enabled with i ts inpu t in false s ta te (low).

XAC·KI

line is firs t driven high, then low (true) at the proper count of counter.

A19

The timing logic is cleared directly by the requesting master removing

MRCD/,

upon

INH21

becoming true, or changed in the address that is generating

MS/.

If positions resident

SW5

signal and

SW10

of

S1

and

S2

are open, the

(A27-6, 27-8, 5-6, 5-8)

ROM

will propagate through

A28-6, 28-8.

The outputs effectively being an the control logic.

connection

OR gate for of

RAMOVI

these gate signal to

The byte selection block directed places by the control logic.

data on the bus as

It supplies the control logic with the word selection status.

Two internal data busses collect data from group, each and feed the input of the data bus drivers memory

(A32,

33, 34).

to the

These drivers are in two groups high and low

Data drivers also form a bytes of the

16

to 8

16

multiplexer bit word operation when J2 is installed . .

corresponding bits data word.

in the

8

2.4 LOGIC SCHEMATIC

Figure

3, the board.

sheets 1, 2 and

3 show the logic schematic of

,

<0

,

,II

«l

, tJJ tf·

J

~

••

I

"'."'1'

~ ~ l~~j~

• - )

+SI

•..."",..., • -.

~

-sv

-'OV

~

~ 0--

I .

a,")

"

....

...,

·SY

~

.

• . , .

• ••v

Cla-"

.0..& c.&

-~ r c•o -..,

..0 • ." caa

0i1

~

AOOA 0')

~ ~E~

\N.£~~

It

L

[t>

8>.

OtH£R'N'S lSPTWC2K

~..t., .....e.t\

Ita.--:"~'O" VAL.&J£~

POwC"

P,~&

APE

'Y'

I~

T~ a.

Cl'tMl.;,

OlVICE

V-=C:

~.15 J~

~,'"

~cc t.,a·")-~,,, ,~

CO....

linI."t~'O'"

:~(.t~~:~~~

2,'It'8

POuua"T:.

451.

L.ve.L. ,.

C~.C~

_.v

,.w, ...

(;n06)

A.

~

NW; M fIDI..&.OWV

t

(a.o.

cw.~ ~

~. ~o ou PM" toIAva

C••/ OPT'oa.a) lOOOc.tt4t-01 O&JL.V. ".

S>

(Ii:>

~

4 t

:5

S. 2

~TV.~ f..

F'2OM

I P!.".STOA

~~1Q~+ ~

ACR(\~,'i

PwA

E.a E2.

ARe.

'~Gt9-02.

eU5TOMEA

C'Jl.v.

'~~TAu.2a.

*(i.e., used on MDS,not used on OEM SBC)

SCHEMATIC

FIGURE 3

16K PROM/ROM MEMORY BOARD

(1 of

3) t"d

~ lQ

CD f-'

W

"i&l

_.::~:==::...:.:..;;;-.:";""'----------r----------------""'~------------------

...----------------.........

~

....

{

HY(jIJf

0

• ok

•.;;::..

.....

--------------------+------""

FIGURE

3

.~

(ContinuE?~" tv

2

of

3)

",(.f"

J

~

~"

J

••

12m. __

~

TA--..iII8,,---..:;r:;"-"

Ill»-As~

~!'~- -~ ~ tATA

D

CATAE

CA1"A ..

~

_1IIAAAO-.....;.;;.;y:...:::,:.-

~

I~~

..

-.J

FIGURE

3

(Continued 3 of

3)

I

I

I t1ATA "

O1l1"A

4-

DlTA A

0161.7

~:::f

."

..""A1.i"-~'.,

-.,...

" , - ' A

,

1ft'

I

..

'

~

I

~

~ I~.

'

I

I.

.

AL~LliII"II"'JL.~"

I

~_

'.....

W'_I~

Page 16

3.0

HARDWARE INSTALLATION

3.1 INSTALLATION OF SWITCHES AND JUMPERS

The switches and following sequence: jumpers may be installed in the

Step 1: "Word Width Selection" Plug - to select mode or 8 bit mode.

16 bit

Step 2: "Group Bias Address" Jumpers - to assign a group bias address for X group and Y group.

Step

3:

Insert PROM/ROM chip in a

Tables 1 and 2.

socket according to

Step

4:

"ROM Resident Enable" Switch - to indicate residency of a PROM/ROM chip to the board.

the

Step 5: "RAM NOT OVERLAP" Switch - to board that the PROM/ROM indicate to the overlaps RAM at some memory locations.

Step

6: "Access Time Code" Switch to set the read access time of the board such that the board can accommodate the slowest PROM/ROM chip resident on the board.

currently

Step

7:

If "Group Enable/Disable Switch" the X group is installed, or Y group PROM/ROM memory on the board can be masked out or unmasked by the switch.

fl~pping

.~

Page 17

3.2 INSTALLATION OF BOARD

In installing the board, the user must take account of:

(a) environmental extremes

(b) mounting considerations

(c) electrical connections

(d) power requirements

(e) signal requirements

(f) address assignments

(g) access timer selection

(h) byte selection

ENVIRONMENT

Temperature extremes can cause instability, or result in permanent damage to the circuits on the module.

Ambient temperature must limits of 0

Centigrade.

therefore degrees

Remember that be

Centigrade the maintained and module within

55 the degrees itself, when installed, will contribute some heat to the environment.

Maintain an adequate clearance, to permit the convective dissipation of heat from the elements on the card.

Relative humidity should not exceed 90% noncondensing.

MOUNTING

Avoid locating

Exposure to the module prolonged or fatigue or impact failure of connections on resulting in abnormally the board, high noise levels or outright failure of the assembly.

near vibrating machinery.

violent vibration may cause

Dimensions of the module are 12 in.

X 6.75 in.

Be sure to allow enough additional clearance to ensure adequate cooling.

The or board

SBC is designed to plug directly into the SBC 604

614 cardcage/backplanes double-sided PC edge connectors; or into two standard, an 86-pin connector and a 60-pin auxiliary connector.

The connectors can serve as a mounting, as well as an electrical junction, if the environment is not too severe.

Card guide slots are desirable, afford.

Should for should the assembly be the vibration used additional be a protection they problem, however, or in a portable equipment application, an to be provided.

additional retaining bracket will have

ELECTRICAL CONNECTIONS

The 16K PROM/ROM board communicates with the motherboard and, consequently, the rest standard 86-pin, double-sided PC of the system, through edge connector (P1), a

Page 18

0.156

in.

Control Data contact centers,

VPBOIE43AOOAI is as shown in one suitable

Figure 4.

type of connector.

in Table 4.

Pin allocations on this connector are given

The auxiliary 60-pin, double-sided PC edge connector (P2), 0.1 in. contact centers is used for test purposes.

(see Figure 4)

Pin allocations for this connector (primarily used for test points) in Table 5.

are listed

Refer to Table 3 for DC Power Requirements.

Refer to the pin list in Table 4 for power connections.

~.,

..

,

0.25

X

45°

(2PLACESJ

0.109 CIA

(3 HOLES)

0.06 A

(12 PLACESJ

------------------II~~I

COMPONENT

SIDE

86-PIN

0.156" cc

------~--

........

_-

-

SO-PIN

0.1" cc

---

..

~-----

6.767

t

0.005

FIGURE 4

BOARD CONNECTORS

5.950

~O.OO5

6.20

6.75 REF

Page 20

3.3 POWER REQUIREMENTS

The SBC 416 uses +5, +12 and -5V

Table 3.

at levels listed in

3.4 PIN LISTS

Th~

and pin list for the PROM/ROM board is shown in Tables

5.

4

4.0 OPERATING CHARACTERISTICS

4.

1

AC CHARACTERISTICS

The AC characteristics are described

Figure

5.

in Table

6, and

4.2

DC CHARACTERISTICS

The DC characteristics are described in Table 7.

~

,

~,

~.

,.

ADRn/

(in)

INH2/

(in)

MRCD/

(in) tAS

ADDRESS STABLE

INH2/ STABLE

INHI/

(out)

DATA

FLOATING tIO

XACK/

FLOATING t

AE t

DS

DRIVEN

DRIVEN t

AC

FIGURE

5

TIMING DIAGRAM

DATA STABLE t

DH t

XH

FLOATING

FLOATING toO

PJ

()Q

(1)

N f-I

Page 22

TABLE 3

DC POWER REQUIREMENTS

USING 16 8708 PROMs

(Fully loaded with 16 8708 PROMs)

POWER

+5V

+12V

-SV

CURRENT (AMPs)

TYPICAL CASE

WORST CASE

. 7

• 8

.480

.972

1.04

.720

USING 16 8308

(Fully loaded with 16 8308 PROMs)

POWER

+SV

+12V

-5V

CURRENT (AMPs)

TYPICAL CASE WORST CASE

-

-

.512

. 9

.96

.020

NO PROMs INSERTED

POWER

+SV

+12V

-SV

CURRENT

(AMPs)

WORST CASE

~

~

.700

Page

21

TABLE 4

PI CONNECTOR PIN LIST

"

'.

PIN

12

13

14

IS

16

17

18

19

9

10

11

S

6

7

8

1

2

3

4

25

26

27

28

29

20

21

22

23

24

34

35

36

37

38

39

40

30

31

32

33

41

42

43

SIGNAL

GND

GND

+SVDC

+SVDC

+5VDC

+SVDC

+12 VDC

+12

VDC

"SVOC

"SVOC

GND

GND

{ Ground

{ Ground

FUNCTION

{ Power inputs

{Power inputs

MRDC/

XACK/

IN!-II/

AACK/

IN1-12/

CCLK/

ADREI

Memory read command

T.ransfer acknowledge

Inhibit RAM

Advance acknowledge

Inhibit ROM

ComlDon clock

Address hus

PIN

44

4S

46

47

48

49

SO

51

52

53

S4

5S

56

57

58

59

60

61

62

63

64

65

66

74

7S

76

77

78

79

80

81

82

83

84

85

86

67

68

69

70

71

72

73

SIGNAL

ADR2/

ADR3/

ADRI/J/

ADRII

DATE/

DARF/

DATe/

DATDI

DATAl

DATB/

DAT81

DAT9/

DAT6/

DAT7/

DAT4/

OATS/

DAT21

DAT3/

DAT_/

ADRFI

ADRC/

ADRD/

ADRA/

ADRB/

ADR8/

ADR9/

ADR6/

ADR71

ADR4/

ADRS/

DATI/

GND

GND

-IOVne

-IOVDC

I

~

Address bus

I

\

~

Data bus

\

{ Ground

FUNCTION

{ Power inputs

+SVDC

+SVDC

+SVDC

+SVDC

GND

GND

{ Power inputs

{ Ground

Page 24

TABLE

5

P2 CONNECTOR PIN LIST

PIN

20

24

2S

26

21

22

23

21

28

29

30

4

5

1

2

3

6

12

13

14

IS

16

9

10

11

7

8

17

18

19

CSA2S

eSA29

CSA23 eSA24

CSA19 eSAl7

C8Al8

CSA16 eSAl4

CSAIS eSAl3

SIGNAL

84-10

I~

CSA30

83·.10

CSA27 e8A26

CSA2S

I..J

CSA23

CSAl2

CSA6 eSA7

CSA4

CSAS

CSA2 eSA3

RESERVED PINS

FOR BACK-UP POWER

INH

FUNCTION

xl

SIGNAL

SI-l eSAI

SI·3

81·2

83·8

82·13

83-1

83-6

83-5

834

83·2

S34

82·1S

83·1

82-14

82-16

82·11

82-12

82·9

82·10

84-2

84·1

84-4

84-3

84-8

84·3

S4·6

54·7

PIN

46

41

48

49

50

51

52

S3

41

42

43

44

4S

S4

55

56

57

58

36

37

38

39

40

31

32

33

34

35

59

60

INH

FUNCTION

yl

INH

ALLI

Note: Pins 21 through 60 are reserved for test points.

.

"'~,

~

;~

.~j

~

1

TA~

6

AC CHARACTERISTICS

DESCRIPTION

MINIMUM (nsec) MAXIMUM (nsec) t

AS

=

Address Set-up Time tIS t t t IH

ro

CCy

=

=

=

INH2/ After Address

INH2/ Hold Time

INRI/ Out From Address t t t

tAC:~

DH

IH

XH t

DE t

AE

tey

=

Constant Clock Cycle

CCLK/

Pulse width

=

Data Stable from

Address if t

AS behind Address

2..

50 nsee

=

=

=

=

=

Module

Data

Inhibit

Access Time

Hold

1

XACK/Hold after

Hold from Address

Data ENABLE

MORC/ Removal

=

XACK Line Driven

=

CCLK/Period

NOTE:

27.5

92

30

2708: 309)

(

8308: 229

55+(n)t

CY

20

62.5

479

79+(n+l)t

CY

91

62.5

44

81

~

54

101.72

MOS

186.5 SBC-aO/20 n

*1

= the number set by switch

53.

There is no required relation between MRDC/ and address for this board, but

MRDC/ t

AE is dependent on the latest arriving signal.

precedes the address, add 43 nsec to t if the cycle is terminated by

AC as described.

If

Also, an address change before MORC/ is removed, add 43 nsec to t

DR -

*2 Minimum: based on all involved devices having minimum propagation and the clock edge is coincident with the counter being enabled.

Maximum: based on all involved devices having maximum propagation and the clock edge just preceded the instant the counter was enabled.

*3 No response

(INH2/) is if addressed invoked.

PROM is disabled or if the

PROM inhibit

TABLE 7

DC CHARACTERISTICS OF THE 16K PROM/ROM BOARD

SIGNALS

(DEVICE)

ADRO/-ADRF/

RD CMD/CCLK/

PARAMETERS v1L-Input low voltage

V1H-Input high voltage

IR-Input leakage current

IF-Input load current

INH2/

INRI/

XACK/

DAT$J/-E>ATF/

V1L-Input low voltage

VIR-Input high voltage

IR-Input leakage current

IF-Input load current

VOL-Low level output voltage

VOH-High level output voltage

VOL-Low level output voltage

VOH-High level output voltage

ILH-Input current at high voltage

ILL-Input current at low voltage

MIN.

2.0

2.0

2.4

2.4

MAX.

0.85

10

-0.25

0.8

1

-1.6

0.4

0.4

-40

40

V pA lJA l1A

UNIT

V

V pA rnA

V

V rnA

. IDA

V

TEST CONDITIONS

VCC=S.OV

VCC=S.OV

V cc

=V a

=S.2S"

V cc

=S.2S,V

R

=O.45V

VCc=5.25V,VR=S.SV

V

CC

=5.25V

lOL=20 rnA

Open collector

V cc

=4.5V,I

OL

=32 rnA

V cc

=4.5V,I

OH

=-S.2

rnA

Vcc

=S.25V,High z,VR=0"S,DIS-2.0V

VCC=S.25V~High Z~VO=2.4V

'1j

OJ

\.Q

it) l\.)

0'\

~~~~~~

J

~j f',

J

J

'-'/"" l

inter

INTEL

CORPORATION, 3065 Bowers Avenue, Santa Clara, CA 95051 (408) 987-8080

Printed

in U.S.A./B-60/0778/1

K BL

... ·i

.~

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