A Floating Point Package for the HPC A Floating

A Floating Point Package for the HPC A Floating

A Floating Point Package for the HPC

National Semiconductor

Application Note 486

Ashok Krishnamurthy

April 1987

INTRODUCTION

This report describes the implementation of a Single Precision Floating Point Arithmetic package for the National

Semiconductor HPC microcontroller. The package is based upon the IEEE Standard for Binary Floating-Point Arithmetic

(ANSI/IEEE Std 754 – 1985). However, the package is not a conforming implementation of the standard. The differences between the HPC implementation and the standard are described later in this report.

The following single precision (SP) operations have been implemented in the package.

(1) FADD.

Addition of two SP floating point (FLP) numbers.

(2) FSUB.

Subtraction of two SP FLP numbers.

(3) FMULT.

Multiplication of two SP FLP numbers.

(4) FDIV.

Division of two SP FLP numbers.

(5) ATOF.

Convert an ASCII string representing a decimal

FLP number to a binary SP FLP number.

(6) FTOA.

Convert a binary SP FLP number to a decimal

FLP number and output the decimal FLP number as an ASCII string.

The report is organized as follows. The next section discusses the representation of FLP numbers. Then, the differences between the HPC implementation and the IEEE/

ANSI standard are described. This is followed by a description of the algorithms used in the computations. Appendix A is a User’s Manual for the package, Appendix B describes the test data for the package and Appendix C is a listing of the code.

Note that this report assumes that the reader is familiar with the IEEE/ANSI Binary Floating-Point Standard. Please refer to this document for an explanation of the terms used here.

REPRESENTATION OF FLOATING POINT NUMBERS

The specification of a binary floating point number involves two parts: a mantissa and an exponent. The mantissa is a signed fixed point number and the exponent is a signed integer. The IEEE/ANSI standard specifies that a SP FLP number shall be represented in 32 bits as shown in Figure 1 .

1

S

8

E

FIGURE 1

23

F

The significance of each of these fields is as follows:

1. SÐthis 1-bit field is the sign of the mantissa. S e

0 means that the number is positive, while S e

1 means that it is negative.

2. EÐthis is the 8-bit exponent field. The exponent is represented as a biased value with a bias of 127-decimal.

3. FÐthis is the 23-bit mantissa field. For normalized FLP numbers (see below), a MSB of 1 is assumed and not represented. Thus, for normalized numbers, the value of the mantissa is 1.F. This provides an effective precision of 24 bits for the mantissa.

Normalized FLP number: A binary FLP number is said to be normalized if the value of the MSB of the mantissa is 1.

Normalization is important and useful because it provides maximum precision in the representation of the number. If we deal with normalized numbers only (as the HPC implementation does) then since the MSB of the mantissa is always 1, it need not be explicitly represented. This is as specified in the IEEE/ANSI standard.

Given the values of S , E and F, the value of the SP FLP number is obtained as follows.

If 0 k

E k

255, then the FLP number is ( b

1)

>S*1.F*2>(E b

127).

If E e

0, then the value of the FLP number is 0.

If E e

255, then the FLP number is not a valid number

(NAN).

The above format for binary SP FLP numbers provides for the representation of numbers in the range b

3.4*10>38 to b

1.75*10> b

38, 0, and 1.75*10> b

38 to 3.4*10>38. The accuracy is between 7 and 8 decimal digits.

DIFFERENCES BETWEEN THE IMPLEMENTATION AND

THE IEEE/ANSI STANDARD

The IEEE/ANSI standard specifies a comprehensive list of operations and representations for FLP numbers. Since an implementation that fully conforms to this standard would lead to an excessive amount of overhead, a number of the features in the standard were dropped. This section describes the differences between the implemented package and the standard.

1. Omission of b

0. The IEEE/ANSI standard requires that both a and b zero be represented, and arithmetic carried out using both. The implementation does not represent b

0. Only a

0 is represented and arithmetic is carried out with a

0 only.

2. Omission of Infinity Arithmetic. The IEEE/ANSI standard provides for the representation of plus and minus Infinity, and requires that valid arithmetic operations be carried out on Infinity. The HPC implementation does not support this.

3. Omission of Quiet NaN. The IEEE/ANSI standard provides for both quiet and signalling NaNs. The HPC implementation provides for signalling NaNs only. A signalling

NaN can be produced as the result of overflow during an arithmetic operation. If the NaN is passed as input to further floating point routines, then these routines will produce another NaN as output. The routines will also set the Invalid Operation flag, and call the user floating point error trap routine at address FPTRAP.

4. Omission of denormalized numbers. Denormalized numbers are FLP numbers with a biased exponent, E of zero and a non zero mantissa F. Such denormalized numbers are useful in providing gradual underflow to zero. Denormalized numbers are not represented or used in the HPC implementation. Instead, if the result of a computation cannot be represented as a normalized number within the allowable exponent range, then an underflow is signaled, the result is set to zero, and the user floating point error trap routine at address FPTRAP is called.

5. Omission of the Inexact Result exception. The IEEE/

ANSI standard requires that an Inexact Result exception be signaled when the rounded result of an operation is not exact, or it overflows without an overflow trap. This feature is not provided in the HPC implementation.

C1995 National Semiconductor Corporation

TL/DD/9248 RRD-B30M105/Printed in U. S. A.

6. Biased Rounding to Nearest. The IEEE/ANSI standard requires that rounding to nearest be provided as the default rounding mode. Further, the rounding is required to be unbiased. The HPC implementation provides biased rounding to nearest only. An example will help clarify this.

Suppose the result of an operation is .b1b2b3XXX and needs to be rounded to 3 binary digits. Then if XXX is

0YY, the round to nearest result is .b1b2b3. If XXX is

1YY, with at least one of the Y’s being 1, then the result is

.b1b2b3

a

0.001. Finally if XXX is 100, it is a tie situation.

In such a case, the IEEE/ANSI standard requires that the rounded result be such that its LSB is 0. The HPC implementation, on the other hand, will round the result in such a case to .b1b2b3

a

0.001.

DESCRIPTION OF ALGORITHMS

1. General Considerations. The HPC implementation of the SP floating point package consists of a series of subroutines. The subroutines have been designed to be compatible with the CCHPC C Cross Compiler. They have, however, not been tested with the CCHPC Cross Compiler.

The Arithmetic subroutines that compute F1 op F2

(where op is a

, b

, * or /) expect that F1 and F2 are input in the IEEE format. Each of F1 and F2 consists of two 16-bit words organized as follows.

Fn – HI: S EXP 7 MS bits of F

Fn – LO: 16 LS bits of F

In the above, S is the sign of the mantissa, EXP is the biased exponent, and F is the mantissa.

On input it is assumed that F1 – HI is in register K, F1 – LO is in the accumulator A, and F2 – HI and F2 – LO are on the stack just below the return address i.e., F2 – HI is at

W(SP-4) and F2 – LO is at W(SP-6). The result, C, is also returned in IEEE format with C – HI in register K and C – LO in the accumulator A.

The two Format Conversion routines, ATOF and FTOA expect that on entry, register B contains the address of the start of the ASCII byte string representing the decimal

FLP number. ATOF reads the byte string starting from this address. Note that the string must be terminated with a null byte. The binary floating point number is returned in registers K and A. FTOA, on the other hand, writes the decimal FLP string starting from the address in register B on entry. A terminating null byte is also output. Also,

FTOA expects that the binary FLP number to be converted is in registers K and A on entry.

Most of the storage required by the subroutines is obtained from the stack. Two additional words of storage in the base page are also used. The first is W(0), and is referenced in the subroutines as W(TMP1). The second word of storage can be anywhere in the base page and is used to store the sticky flags used to signal floating point exceptions. This is referenced in the subroutines as

W(FPERWD). Thus any user program that uses the floating point package needs to have the symbols TMP1 and

FPERWD defined appropriately.

2. Exception Handling. The following types of exception can occur during the course of a computation.

(i) Invalid Operand. This exception occurs if one of the input operands is a NaN.

(ii) Exponent Overflow. This occurs if the result of a computation is such that its exponent has a biased value of 255 or more.

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(iii) Exponent Underflow. This occurs if the result of a computation is such that its exponent is 0 or less.

(iv) Divide-by-zero. This exception occurs if the FDIV routine is called with F2 being zero.

The package signals exceptions in two ways. First a word at address FPERWD is maintained that records the history of these exception conditions. Bits 0 – 3 of this word are used for this purpose.

Bit 0ÐSet on Exponent Overflow.

Bit 1ÐSet on Exponent Underflow.

Bit 2ÐSet on Illegal Operand.

Bit 3ÐSet on Divide-by-zero.

These bits are never cleared by the floating point package, and can be examined by the user software to determine the exception conditions that occurred during the course of a computation. It is the responsibility of the user software to initialize this word before calling any of the floating point routines.

The second method that the package uses to signal exceptions is to call a user floating point exception handler subroutine whenever an exception occurs. The corresponding exception bit in FPERWD is set before calling the handler. The starting address of the handler should be defined by the symbol FPTRAP.

3. Unpacked Floating Point Format. The IEEE/ANSI standard floating point format described earlier is very cumbersome to deal with during computation. This is primarily because of the splitting of the mantissa between the two words. The subroutines in the package unpack the input

FLP numbers into an internal representation, do the computations using this representation, and finally pack the result into the IEEE format before return to the calling program. The unpacking is done by the subroutine FUN-

PAK and the packing by the subroutine FPAK. The unpacked format consists of 3 words and is organized as follows.

Fn-EXP.Fn-SIGN 8 bits biased sign (extended to exponent 8 bits)

Fn-HI MS 16 bits of mantissa

(implicit 1 is present as MSB)

Fn-LO LS 8 bits of mantissa

Eight

Zeros

Since all computations are carried out in this format, note that the result is actually known to 32 bits. This 32-bit mantissa is rounded to 24 bits before being packed to the

IEEE format.

4. Algorithm Description. All the arithmetic algorithms first check for the easy cases when either F1 or F2 is zero or a NaN. The result in these cases is immediately available.

The description of the algorithms below is for those cases when neither F1 nor F2 is zero or a NaN. Also, in order to keep the algorithm description simple, the check for underflow/overflow at the various stages is not shown. The documentation in the program, the descriptions given below, and the theory as described in the references should allow these programs to be easily maintained.

(i) FADD.

The processing steps are as follows:

1. Compare F1-EXP and F2-EXP. Let the difference be D. Shift right the mantissa (Fn-HI.Fn-LO, n e

1 or 2) of the FLP number with the smaller exponent

D times. Let the numbers after this step be F1-

EXP.F1-SIGN, F1-HI, F1-LO and F2-EXP.F2-SIGN,

F2-HI and F2-LO. This step equalizes the two exponents.

2. Take the XOR of F1-SIGN and F2-SIGN. If this is 0, then go to step 4, else go to step 3.

3. Do a true subtract of F2-LO from F1-LO. (A true subtract is when the SUBC instruction is preceded by a SET C instruction.) Then do a 1’s complement subtract of F2-HI from F1-HI. If the last subtract resulted in C e

1, then go to step 3.2, else go to step 3.1.

3.1. Get here means that F2 is larger than F1, and the computed result is negative. Take the 2’s complement of the result to make it positive. Set the sign of the result to be the sign of F2. Go to step

3.3.

3.2. Get here means F1 is larger than F2, and the result of the mantissa subtract is positive. Set the sign of the result to be the sign of F1. Go to step

3.3.

3.3. The result after a subtract need not be normalized. Shift left the result mantissa until its MSB is 1.

Decrement the exponent of the result by 1 for each such left shift. Go to step 5.

4. Add F2-LO to F1-LO. Next add with any carry from the previous add, F2-HI to F1-HI. If this last add results in C e

1, then go to step 4.1, else go to step 5.

4.1. Rotate Right with carry C-HI. Next load C-LO in and rotate it right with carry. Increase the exponent of the result, C by 1. Go to step 5.

5. Round the result. Go to step 6.

6. Pack the result and return.

(ii) FSUB.

The processing steps are as follows:

1. Copy F2 to the stack and change its sign. Go to step 2.

2. Call FADD.

3. Remove the copy of -F2 from the stack and return.

(iii) FMULT.

The processing steps are as follows.

1. Add F1-EXP and F2-EXP to get C1-EXP. Subtract from C1-EXP 127-decimal which is the IEEE bias, to get C-EXP. Go to step 2.

2. Take the XOR of F1-SIGN and F2-SIGN to get C-

SIGN. Go to step 3.

3. Compute F1-HI*F2-HI. Let the upper half of the product be C1-HI and the lower half C1-LO. Go to step 4.

4. Compute F1-HI*F2-LO. Let the upper half of this product be C2-HI. Add C2-HI to C1-LO to give

C11-LO. If this last add results in C e

1, then increment C1-HI. Go to step 5.

5. Compute F1-LO*F2-HI. Let the upper half of this product be C3-HI. Add C3-HI to C11-LO to get

C12-LO. If this last add results in C e

1, then increment C1-HI. Go to step 6.

6. Mantissa normalization. If the MSB of C1-HI is 1, then increment C-EXP, else shift left C1-HI.C12-

LO. Go to step 7.

7. Round C1-HI.C12-LO to get C-HI.C-LO. Go to step 8.

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8. Pack C-EXP.C-SIGN, C-HI and C-LO and return as the answer.

(iv) FDIV.

The processing steps are as follows:

1. Compare F1-HI and F2-HI. If F2-HI is greater than

F1-HI then go to Step 3, else go to step 2.

2. Shift right F1-HI.F1-LO. Increase F1-EXP by 1.

3. Subtract F2-EXP from F1-EXP. Add to the result

127-decimal to get C1-EXP. Go to step 4.

4. Take the XOR of F1-SIGN and F2-SIGN to get

C-SIGN. Go to step 5.

5. Compute F1-HI*F2-LO. Let the result be M1-

HI.M1-LO. Go to step 6.

6. Divide M1-HI.M1-LO by F2-HI. Let the quotient be

M2-HI. Go to step 7.

7. Do a true subtract of M2-HI from F1-LO. Let the result be M3-LO. If C e

1 as a result of this subtract, then go to step 8, else decrement F1-HI and go to step 8.

8. Divide F1-HI.M3-LO by F2-HI. Let the quotient be

C1-HI and the remainder R1. Go to step 9.

9. Divide R1 .0000 by F2-HI. Let the quotient be C1-

LO. Go to step 10.

10. If the MSB of C1-HI is 1 then go to step 11, else shift left C1-HI.C1-LO, decrease C1-EXP by 1 and go to step 11.

11. Round C1-HI.C1-LO to get C-HI.C-LO. go to step

12.

12. Pack C1-EXP.C-SIGN, C-HI and C-LO and return as the result.

(v) ATOF.

The processing steps in this case are as follows.

1. Set M-SIGN, the mantissa sign to 0.

Set M10-EXP, the implicit decimal exponent to 0.

Set HI-INT to 0.

Set LO-INT to 0.

Go to step 2.

2. Get a character from the input string. Let the character be C.

If C is a ‘ a

’, then go to the start of step 2.

If C is a ‘ b

’, then set M-SIGN to FF and go to start of step 2.

If C is a ‘.’, then go to step 5.

If C is none of the above, then go to step 3.

3. Subtract 30 from C to get its integer value. Let this be I. Check and see if (HI-INT.LO-INT)*10 a

9 can fit in 32 bits. If it can, then go to step 3.1, else go to step 3.2.

3.1. Multiply HI-INT.LO-INT by 10 and add I to the product. Store this sum back in HI-INT.LO-INT. Go to step 4.

3.2. Increase M10-EXP by 1 and go to step 4.

4. Get a character from the input string. Let the character be C.

If C is a ‘.’, then go to step 5.

If C is a ‘E’, then go to step 7.

If C is the space character, then go to the start of step 4.

If C is none of the above, then go to step 3.

5. Get a character from the input string. Let the character be C.

If C is a ‘E’, then go to step 7.

If C is the space character, then go to the start of step 5.

If C is none of the above, then go to step 6.

6. Subtract 30 from C to get its integer value. Let this be I. Check and see if (HI-INT.LO-INT)*10 a

9 can fit in 32 bits. If it can, then go to step 6.1, else go to step 5.

6.1. Multiply HI-INT.LO-INT by 10 and add I to the product. Store this sum back in HI-INT.LO-INT.

Decrement M10-EXP by 1. Go to step 5.

7. Set SEXP, the exponent sign to be 0. Go to step 8.

8. Get a character from the input string. Let the character be C.

If C is a ‘ a

’, then go to start of step 8.

If C is a ‘ b

’, then set SEXP to be FF and go to the start of step 8.

If C is none of the above, then go to step 9.

9. Set M20-EXP, the explicit decimal exponent to 0.

Go to step 10.

10. Subtract 30 from C to get its integer value. Let this be I. Multiply M20-EXP by 10 and add I to the product. Store this sum back in M20-EXP. Go to step 11.

11. Get a character from the input string. Let this be

C. If C is the null character, then go to step 12, else go to step 10.

12. Add M10-EXP and M20-EXP (with the proper sign as determined by SEXP) to get the 10’s exponent

M-EXP. Save in M-EXP the magnitude of the sum and in SEXP the sign of the sum. Go to step 13.

13. Check and see if HI-INT.LO-INT is 0. If it is, then set the resulting floating point number, C, to zero and return. If it is not then go to step 14.

14. Normalize HI-INT.LO-INT by left shifts such that the MSB is 1. Let the number of left shifts needed to do this be L. Set B1-EXP to 32-decimal b

L. Go to step 15.

15. If SEXP is 0, then set P-HI.P-LO to the binary representation of 0.625, else set P-HI.P-LO to the binary representation of 0.8. Go to step 16.

16. Multiply HI-INT.LO-INT by P-HI.P-LO M-EXP times. After each multiplication, normalize the partial product if needed by left shifting. Accumulate the number of left shifts needed in B2-EXP. Let the final product be C-HI.C-LO. Go to step 17.

17. Subtract B2-EXP from B1-EXP. Let the result be

B-EXP. Go to step 18.

18. If SEXP is 0, then multiply M-EXP by 4, else multiply M-EXP by b

3. Let the result be B3-EXP. Go to step 19.

19. Add B-EXP and B3-EXP. Let the result be C1-

EXP. Add 126 to C1-EXP to restore the IEEE bias, getting C-EXP. Go to step 20.

20. Round C-HI.C-LO. Go to step 21.

21. Pack C-EXP.M-SIGN, C-HI and C-LO and return.

(vi) FTOA.

The processing steps are as follows.

1. Unpack the input FLP number. Let the unpacked number be represented by C-EXP.C-SIGN, C-HI and C-LO. Go to step 2.

2. Subtract 126-decimal from C-EXP to remove the

IEEE bias. Let the result be C1-EXP. Go to step 3.

3. Multiply C1-EXP by the binary representation of log(2). Let the product be U-HI.U-LO. Go to step

4.

4. Subtract 8 from U-HI.U-LO. Let the magitude of the integer part of the result be V and its sign

VSIGN. Go to step 5.

5. If VSIGN is 0, then set P-HI.P-LO to the binary representation of 0.8, else set P-HI.P-LO to the binary representation of 0.625. Go to step 6.

6. Multiply C-HI.C-LO by P-HI.P-LO V times. Normalize the partial product after each multiplication, if needed, by left shifting. Accumulate any left shifts needed in B1-EXP. Let the final product be HI-

INT.LO-INT. Go to step 7.

7. Subtract B1-EXP from C1-EXP. Let the result be

B2-EXP. Go to step 8.

8. If VSIGN is 0, then multiply V by b

3, else multiply it by 4. Let the result be B3-EXP. Go to step 9.

9. Add B2-EXP and B3-EXP. Let the result be B4-

EXP. Go to step 10.

10. If B4-EXP is more than 32-decimal, then increase

V and go to step 6, else go to step 11.

11. If B4-EXP is less than 28-decimal, then decrease

V and go to step 6, else go to step 12.

12. Subtract B4-EXP from 32. Let the result be B5-

EXP. Go to step 13.

13. Shift HI-INT.LO-INT right B5-EXP number of times. Go to step 14.

14. Add 16-decimal to the address of the start of the decimal string. Output a null byte there. Go to step

15.

15. Divide V by 10-decimal. Let the quotient be Q and the remainder R. Add 30 to R and output it to the decimal string. Next add 30 to Q and output it to the decimal string. Go to step 16.

16. If VSIGN is 0, then output ‘ a

’ to the output string, else output ‘ b

’ to the output string. Go to step 17.

17. Output ‘E’ to the output string. Output ‘.’ to the output string. Go to step 18.

18. Divide C-HI.C-LO by 10-decimal 10 times. Let the remainder in each division be R. Add 30 to each R and output it to the output string. Go to step 19.

19. If C-SIGN is 0, then output the space character to the output string, else output ‘ b

’ to the output string. Then return to the calling program.

REFERENCES

1. ANSI/IEEE Std 754-1985, IEEE Standard for Binary

Floating-Point Arithmetic, IEEE, Aug. 12, 1985.

2. J.T. Coonen, ‘‘An Implementation Guide to a Proposed

Standard for Floating-Point Arithmetic,’’ IEEE Computer,

Jan. 1980, pp. 68 – 79.

3. K. Hwang, Computer Arithmetic, John-Wiley and Sons,

1979.

4. M. M. Mano, Computer System Design, Prentice-Hall,

1980.

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APPENDIX A

A USER’S MANUAL FOR THE HPC

FLOATING POINT PACKAGE

The Single Precision Floating Point Package for the HPC implements the following functions.

ARITHMETIC FUNCTIONS

1. FADDÐAdd two floating point numbers.

2. FSUBÐSubtract two floating point numbers.

3. FMULTÐMultiply two floating point numbers.

4. FDIVÐDivide two floating point numbers.

FORMAT CONVERSION FUNCTIONS

5. ATOFÐConvert an ASCII string representing a decimal floating point number to a single precision floating point number.

6. FTOAÐConvert a single precision floating point number to an ASCII string that represents the decimal floating point value of the number.

The entire package is in the form of a collection of subroutines and is contained in the following files.

1. FERR.MAC

2. FNACHK.MAC

3. FZCHK.MAC

4. FUNPAK.MAC

5. FPAK.MAC

6. FPTRAP.MAC

7. ROUND.MAC

8. BFMUL.MAC

9. ISIOK.MAC

10. MUL10.MAC

11. ATOF.MAC

12. FTOA.MAC

13. FADD.MAC

14. FMULT.MAC

15. FDIV.MAC

The first 7 files are general utility routines that are used by all the Arithmetic and Format Conversion subroutines. The next 3 files, BFMUL.MAC, ISIOK.MAC and MUL10.MAC are used only by the Format Conversion subroutines, ATOF and

FTOA. Depending on the functions being used in the user program, only the necessary files need be included.

INTERFACE WITH USER PROGRAMS

1. All the Arithmetic routines expect the input to be in the

IEEE Single Precision format. This format requires 2 words for the storage of each floating point number. If the required arithmetic operation is FlopF2, where op is a

, b

, * or /, then the routines expect that F1 is available in registers K and A on entry, with the high half in K. Also, the two words of F2 are expected to be on the stack. If

SP is the stack pointer on entry into one of the Arithmetic function subroutines, then the high word of F2 should be at W(SP-4) and the low word at W(SP-6). The result of the

Arithmetic operation is returned in IEEE format in registers K and A, with the high word in K.

2. The Format Conversion subroutine ATOF expects that on entry, B contains the address of the ASCII string representing the decimal floating point number. This string must be of the form

Siiiii.ffffffEsNND

where

S is an optional sign for the mantissa. Thus S can be ‘ a

’,

‘ b

’ or not present at all.

iiiii is the optional integer part of the mantissa. If it is present, it can be of any length, must contain only the characters ‘0’ through ‘9’ and must not contain any embedded blanks.

. is the optional decimal point. It need not be present if the number has no fractional part.

ffffff is the optional fractional part of the mantissa. ffffff, if it is present must consist of a sequence of digits ‘0’ through ‘9’. It can be of any length. Note that either iiiii, the integer part or .ffffff the fractional part must be present.

E is the required exponent start symbol.

s is the optional sign of the exponent. If it is present, it must be ‘ a

’ or ‘ b

’.

NN is the exponent and consists of at most two decimal digits. It is required to be present.

D is the null byte the string.

k

00 l and must be present to terminate

The floating point number represented by the above string is returned by ATOF in IEEE format in registers K and A.

3. The format conversion routine FTOA expects the floating point number input to be in registers K and A in the IEEE format. Register B is expected to contain the starting address of a 17 byte portion of memory where the output string will be stored.

4. Three global symbols need to be defined in the user program before assembling the user program and any included floating point package files. These symbols are:

(i) TMP1 which must be set to 0. The package uses

W(TMP1) for temporary storage.

(ii) FPERWD which must be set to an address in the base page. The package signals floating point exceptions using W(FPERWD). This is described below.

(iii) FPTRAP which must be set to the address of the start of a user floating point exception handler. Again this is described below.

FLOATING POINT EXCEPTS

The package maintains a history of floating point exceptions in the 4 least significant bits of the word W(FPERWD). The value of the symbol FPERWD should be defined by the user program, and should be an address in the base page. This word should also be cleared by the user program before calling any floating point routine. The word is never cleared by the floating point package, and the user program can examine this word to determine the type of exceptions that may have occurred during the course of a computation.

5

The following 4 types of error can occur in the course of a floating point computation.

1. Invalid Operand. This happens if one of the input numbers for an Arithmetic routine or the input for FTOA is not a valid floating point number. An invalid floating point number (or NaN) can be created either by an overflow in a previous computation step, or if the ASCII decimal floating point number input to ATOF is too large to be represented in the IEEE format. The result, if one of the inputs is a NaN is always set to a NaN.

2. Overflow. This happens if the result of a computation is too large to be represented within the exponent range available. Overflow can occur in any of the arithmetic routines or ATOF. On overflow, the result is set to a representation called NaN. An NaN is considered an illegal operand in all successive steps.

3. Underflow. This occurs if the result of a computation is too small to be represented with the precision and exponent range available. On underflow, the result is set to zero.

4. Divide-by-zero. This error occurs if F2 is zero when computing F1/F2. The result is set to an NaN.

Each of the above errors results in a bit being set in

W(FPERWD). This is done as follows:

Bit 0ÐSet on Overflow.

Bit 1ÐSet on Underflow.

Bit 2ÐSet on Illegal Operand.

Bit 3ÐSet on Divide-by-zero.

One further action is taken when a floating point exception occurs. After the result has been set to the appropriate value, and the corresponding bit in W(FPERWD) set, the package does a subroutine call to address FPTRAP. The user can provide any exception handler at this address. The file

FPTRAP.MAC contains the simplest possible user exception handler. It does nothing, but merely returns back to the calling program.

6

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FLP

1

2

3

4

5

6

0071

F000

0002

0000

LISTER:

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FLP

THE FLP ROUTINES

7

PAGE: 1

.TITLE FLP

.LIST 071

.

4 0F000

FPERWD

4 W(2)

TMP1

4 W(0)

PAGE: 2

.FORM ’THE FLP ROUTINES’

The code listed in this App Note is available on Dial-A-Helper.

Dial-A-Helper is a service provided by the Microcontroller Applications Group. The Dial-A-Helper system provides access to an automated information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a day. The system capabilities include a MESSAGE SECTION (electronic mail) for communicating to and from the Microcontroller Applications Group and a FILE SECTION mode that can be used to search out and retrieve application data about

NSC Microcontrollers. The minimum system requirement is a dumb terminal, 300 or 1200 baud modem, and a telephone.

With a communications package and a PC, the code detailed in this App Note can be down loaded from the FILE SECTION to disk for later use. The Dial-A-Helper telephone lines are:

Modem (408) 739-1162

Voice (408) 721-5582

For Additional Information, Please Contact Factory

7

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FLP

FERR.MAC

1

2

8

9

3

4 F000 820802FA

5 F004 00

6 F005 B17F80

7 F008 3093

8 F00R 3FCC

9 F00C 3FCE

10 F00E 3C

11

12

13 F00F 820402FA

14 F013 00

15 F014 B17F80

16 F017 3084

17 F019 3FCC

18 F01B 3FCE

19 F01D 3C

20

21

22 F01E 820202FA

23 F022 00

24 F023 ACC8CA

25 F026 3075

26 F028 3FC4

27 F02A 3FCC

28 F02C 3FCE

29 F02E 3C

30

31

32 F02F 820102FA

33 F033 00

34 F034 B17F80

35 F037 3064

36 F039 3FC4

37 F03B 3FCC

38 F03D 3FCE

39 F03F 3C

40

41

PAGE: 3

; EXCEPTION HANDLING.

; DIVIDE BY ZERO.

DIVBY0:

.FORM ’FERR.MAC’

.INCLD FERR.MAC

OR FPERWD, 08

CLR A

; SET THE DIVIDE BY 0 BIT.

LD K, 07F80

JSR FPTRAP

POP B

POP X

RET

; ILLEGAL OPERAND - ONE OF F1 OR F2 IS A NAN.

FNAN:

OR FPERWD, 04 ; SET THE ILLEGAL OPERAND BIT.

CLR A

LD K, 07F80

JSR FPTRAP

; RETURN NAN IN K AND A.

; GO TO USER TRAP ROUTINE.

RET

; EXPONENT UNDERFLOW.

UNDFL:

POP B

POP X

OR FPERWD, 02

CLR A

LD K, A

JSR FPTRAP

POP SP

POP B

; SET THE EXPONENT UNDERFLOW BIT.

POP X

RET

; EXPONENT OVERFLOW.

OVRFL:

OR FPERWD, 01

CLR A

LD K, 07F80

JSR FPTRAP

POP SP

POP B

POP X

RET

;

.END

; SET THE EXPONENT OVERFLOW BIT.

8

10

11

1

2

3

4

5

8

9

6

7

10

11

12

13 F040 AECA

14 F042 E7

15 F043 BDFEFF

16 F046 45

17 F047 D7

18 F048 03

19 F049 AECA

20 F04B 3C

21

22 F04C D7

23 F04D 02

24 F04E AECA

25 F050 3C

26

27

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FLP

FNACHK.MAC

PAGE: 4

.FORM ’FNACHK.MAC’

.INCLD FNACHK.MAC

.TITLE FNACHK

.LOCAL

;

; SUBROUTINE TO CHECK IF A SP FLOATING POINT NUMBER STORED IN THE

; IEEE FLOATING POINT FORMAT IN REGS. K AND A IS NAN.

;

; RETURNS 0 IN C IF THE NUMBER IS NOT A NAN.

; RETURNS 1 IN C IF THE NUMBER IS A NAN.

;

; PRESERVES REGS. K, A, X AND B. DESTROYS C.

;

FNACHK:

X A, K

SHL A

IFGT A,OFEFF

JP $ISNAN

RRC A

RESET C

X A, K

RET

$ISNAN:

RRC A

SET C

X A, K

RET

;

.END

9

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FNACHK

FZCHK.MAC

12

13

1

2

3

4

5

8

9

6

7

10

11

12 F051 AECA

13 F053 E7

14 F054 9DFF

15 F056 45

16 F057 D7

17 F058 02

18 F059 AECA

19 F05B 3C

20

21 F05C D7

22 F05D 03

23 F05E AECA

24 F060 3C

25

26

PAGE: 5

.FORM ’FZCHK.MAC’

.INCLD FZCHK.MAC

.TITLE FZCHK

.LOCAL

;

; SUBROUTINE THAT CHECKS IF A SP FLOATING POINT NUMBER STORED

; IN THE IEEE FORMAT IN REGS K AND A IS ZERO.

;

; RETURNS 0 IN C IF THE NUMBER IS NOT ZERO.

; RETURNS 1 IN C IF THE NUMBER IS ZERO.

; SAVES REGS. K, A, X, AND B BUT DESTROYS C.

;

FZCHK:

X A, K

SHL A

IFGT A,OFF

JP $ANOTO

RRC A

SET C

X A, K

RET

$ANOTO:

RRC A

RESET C

X A, K

RET

;

.END

10

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FZCHK

FUNPAK.MAC

10

11

12

13

14

15

16

8

9

6

7

14

15

1

2

3

4

5

17

18

19

20

21

22

23 F061 ABCC

24 F063 00

25 F064 D1

26 F065 88CC

27 F067 D1

28 F068 88CD

29 F06A D1

30 F06B A8CA

31 F06D 96C80F

32 F070 D1

33 F071 A8CA

34 F073 E7

35 F074 B9FF00

36 F077 07

37 F078 9AFF

38 F07A F1

39 F07B 3C

40

41

PAGE: 6

.FORM ’FUNPAK.MAC’

.INCLD FUNPAK.MAC

.TITLE FUNPAK

.LOCAL

;

; SUBROUTINE TO UNPACK A SP FLOATING POINT NUMBER STORED IN THE

; IEEE FORMAT IN REGS. K AND A. THE UNPACKED FORMAT OCCUPIES 3

; WORDS AND IS ORGANIZED AS FOLLOWS:

;

; increasing addrs

;

;

;

; l l l l l l

EEEEEEEESSSSSSSS l

FEXP-FSIGN l

MMMMMMMMMMMMMMMM l

FHI l l

MMMMMMMM00000000 l

FLO l k

1 X on exit k

1 X on entry

;

; EEEEEEEE

1 8 BIT EXPONENT IN EXCESS-127 FORMAT

; SSSSSSSS

1 SIGN BIT k

00

1 l

0, FF 1 l

1 l

; M ... M

1 24 BITS OF MANTISSA. NOTE THAT IMPLIED 1 IS PRESENT HERE.

;

; ON ENTRY TO THE SUBROUTINE X SHOULD POINT TO FLO. ON EXIT, X POINTS

; TO THE WORD AFTER FSIGN.

; REGS. K, A AND B ARE DESTROYED BY THIS SUBROUTINE.

;

FUNPAK:

; SAVE A IN B.

ST A,B

CLR A

X A, M(X

0)

LD A, L(B)

X A, M(X

0)

LD A, H(B)

X A, M(X

0)

LD A, K

SET A.7

X A, M(X

0)

LD A, K

SHL A

AND A, 0FF00

IF C

OR A, OFF

X A, W(X

0)

RET

; ZERO LOW BYTE OF FLO.

; MOVE LOW BYTE OF F-RO INTO HIGH BYTE OF FLO.

; MOVE MID BYTE OF MANT INTO LOW BYTE OF FHI.

; SET IMPLIED 1 IN MANTISSA

; MOVE HIGH BYTE OF MANT INTO HIGH BYTE OF FHI.

; SIGN BIT TO CARRY.

; ZERO SIGN.

; PUT SIGN BACK IF

; SAVE FEXP-FSIGN.

1.

;

.END

11

16

17

1

2

3

4

5

10

11

12

13

8

9

6

7

14 F07C D1

15 F07D D1

16 F07E ABCA

17 F080 D1

18 F081 3B

19 F082 3B

20 F083 B9FF00

21 F086 A0C8CAFA

22

23 F08A D1

24 F08B 96C81F

25 F08E ABCC

26 F090 D4

27 F091 C7

28 F092 F0

29 F093 B9FF00

30 F096 D7

31

32 F097 96CCFA

33 F09A AECA

34 F09C 3C

35

36

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FUNPAK

FPAK.MAC

PAGE: 7

.FORM ’FPAK.MAC’

.INCLD FPAK.MAC

.TITLE FPAK

.LOCAL

;

; SUBROUTINE TO PACK A SP FLOATING POINT NUMBER STORED IN THE

; 3 WORD FEXP-FSIGN/FHI/FLO FORMAT INTO THE IEEE FORMAT IN REGS.

; K AND A.

;

; ON ENTRY TO THE SUBROUTINE, X POINTS TO FLO. ON EXIT, X POINTS

; TO THE WORD AFTER FSIGN.

;

; REGS. K, A AND B ARE DESTROYED.

;

FPAK:

X A, M(X

0)

X A, M(X

0)

ST A, K

X A, M(X

0)

SWAP A

; GET RID OF ZERO LOW BYTE OF FLO.

; GET HIGH BYTE OF FLO.

; STORE IT IN K.

; GET LOW BYTE OF FHI.

SWAP A

AND A, 0FF00

OR K, A

; SHIFT LEFT 8 TIMES.

; LOW WORD OF RESULT IS NOW IN K.

;

X A, M(X

0)

RESET A.7

ST A,B

LD A, M(X)

SHR A

LD A, W(X

0)

AND A, 0FF00

RRC A

OR A, B

X A, K

RET

; GET HIGH BYTE OF FHI.

; ZERO IMPLIED MSB 1 IN MANT.

; SAVE IN REG. B.

; GET SIGN BYTE FROM ASIGN.

; MOVE 1 SIGN BIT INTO CARRY.

; GET FEXP-FSIGN.

; ZERO SIGN.

; MOVE RIGHT 1 BIT. SIGN BIT FROM C

; ENTERS INTO THE MSB.

; GET MANT BITS IN FROM B.

; SWAP A AND K

;

.END

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FPAK

FPTRAP.MAC

18

19

1

2

3

4 F09D 3C

5

6

PAGE: 8

.FORM ’FPTRAP.MAC’

.INCLD FPTRAP.MAC

.TITLE FPTRAP

; USER SUPPLIED FP TRAP ROUTINE.

FPTRAP:

RET

;

.END

12

20

21

1

2

3

4

5

10

11

12

13

8

9

6

7

14 F09E F2

15 F09F F4

16 F0A0 96C817

17 F0A3 43

18 F0A4 F0

19 F0A5 F0

20 F0A6 5F

21

22

23 F0A7 B80100

24 F0AA F1

25 F0AB 07

26 F0AC 42

27 F0AD F0

28 F0AE 57

29

30

31 F0AF F4

32 F0B0 B8

F0B1 00

F0B2 01

33 F0B3 07

34 F0B4 42

35 F0B5 F1

36 F0B6 4F

37

38

39 F0B7 D7

40 F0B8 F3

41 F0B9 F4

42 F0BA D7

43 F0BB F1

44 F0BC F0

45 F0BD F4

46 F0BE B80100

47 F0C1 07

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FPTRAP

ROUND.MAC

PAGE: 9

.FORM ’ROUND.MAC’

.INCLD ROUND.MAC

.TITLE SROUND

.LOCAL

;

; THIS SUBROUTINE IS USED TO ROUND THE 32 BIT MANTISSA OBTAINED

; IN THE FLOATING POINT CALCULATIONS TO 24 BITS.

;

; THE UNPACKED FLOATING POINT NUMBER SHOULD BE STORED IN

; CONSECUTIVE WORDS OF MEMORY. ON ENTRY, X SHOULD CONTAIN

; THE ADDRESS OF C-HI. C-EXP.C-SIGN IS AT W(X

02) AND

; C-L0 IS AT W(X

12).

;

; ON EXIT X HAS THE ADDRESS OF C-EXP.C-SIGN.

SROUND:

LD A, W(X

1)

LDA, W(X)

; REMEMBER X POINTS TO C-HI.

; LOAD C-L0.

IF A.7

; IF BIT 25 OF MANTISSA IS 1,

; THEN NEED TO INCREASE MANTISSA.

JP $RNDUP

LD A, W(X

0)

LD A, W(X

0)

JP $EXIT

; INCREASE MANTISSA.

$RNDUP:

; X NOW POINTS TO C-EXP.C-SIGN.

; DONE, SO GET OUT.

ADD A, 0100

X A, W(X

0)

IF C

; INCREASE LOW BYTE BY 1.

JP $HIUP

LD A, W(X

0)

JP $EXIT

; IF THERE IS A CARRY,

; THEN NEED TO INCREASE C-HI.

; X NOW POINTS TO C-EXP.C-SIGN.

; DONE, SO GET OUT.

; MANTISSA INCREASE PROPAGATING TO HIGH WORD.

$HIUP:

LD A, W(X)

.BYTE 0B8,00,01 ; D0 ADD A, 01 BUT WITH WORD CARRY!!

IF C

JP $EXIN2

X A,W(X

0)

JP $EXIT

; IF THERE IS A CARRY,

; THEN NEED TO INCREASE EXPONENT.

; GET OUT.

; ROUND UP LEADS TO EXPONENT INCREASE.

$EXIN2:

RRC A

X A,W(X

1)

LD A,W(X)

; CARRY

1 l MSB, LSB

1 l CARRY.

; LOW WORD IS NOW IN A.

RRC A

X A, W(X

0)

LD A, W(X

0)

LD A, W(X)

; X NOW POINTS TO C-EXP.CSIGN.

ADD A, 0100

IF C

13

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

SROUND

ROUND.MAC

48 F0C2 BAFF00

49 F0C5 F6

50

51

52 F0C6 3C

53

54

;

$EXIT:

;

OR A, 0FF00

ST A, W(X)

RET

PAGE:

.END

10

; MAKE IT A NAN.

14

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

SROUND

BFMUL.MAC

10

11

12

13

14

15

16

8

9

6

7

22

23

1

2

3

4

5

17

18

19

20

21 F0C7 AFCE

22 F0C9 AFC8

23 F0CB AFCA

24 F0CD ABCA

25 F0CF A6FFF6C4FE

26 F0D4 3FCA

27 F0D6 AFCE

28 F0D8 AFC8

29 F0DA A8CA

30 F0DC A6FFF2C4FE

31 F0E1 3FC8

32

33 F0E3 3FCA

34 F0E5 96CEF8

35 F0E8 07

36 F0E9 A9CA

37 F0EB 3FCE

38 F0ED AFCA

39 F0EF AFC8

40 F0F1 A8CE

41 F0F3 A6FFF6C4FE

42 F0F8 3FC8

43 F0FA 3FCA

44 F0FC 96CEF8

45 F0FF 07

46 F100 A9CA

47 F102 3FCE

48 F104 3C

49

PAGE: 11

.FORM ’BFMUL.MAC’

.INCLD BFMUL.MAC

.TITLE BFMUL

;

; THIS SUBROUTINE IS USED TO MULTIPLY TWO 32 BIT FIXED POINT FRACTIONS.

; THE ASSUMED BINARY POINT IS TO THE IMMEDIATE LEFT OF THE MSB.

;

; THE FIRST FRACTION IS STORED IN REGS K AND A, WITH THE MORE

; SIGNIFICANT WORD BEING IN K.

;

; THE SECOND FRACTION IS STORED ON THE STACK. THE MORE SIGNIFICANT

; WORD IS AT W(SP-4) AND THE LOWER SIGNIFICANT WORD

; IS IN THE WORD BELOW IT.

;

; THE 32 BIT PRODUCT IS LEFT IN REGS. K AND A, WITH THE MORE

; SIGNIFICANT WORD BEING IN K.

;

; IMPORTANT NOTE : THE FRACTIONS ARE ASSUMED TO BE UNSIGNED.

;

; REGS. B AND X ARE UNCHANGED.

;

BFMUL:

PUSH X

PUSH A

PUSH K

LD A, K

; SAVE X.

; SAVE F1-L0

; SAVE F1-HI.

; MOVE F1-HI TO A.

MULT A, W(SP-0A); MULTIPLY F1-HI BY F2-HI.

POP K ; GET FI-HI.

PUSH X ; SAVE PR-HI.

PUSH A

LD A, K

; SAVE PR-L0.

; MOVE F1-HI TO A.

MULT A, W(SP-OE); MULTIPLY F1-HI BY F2-L0.

POP A ; GET PR-L0 SAVED. NOTE THAT THE

POP K

ADD A, X

IF C

INC K

POP X

PUSH K

; L0 WORD OF THIS PRODUCT IS DISCARDED.

; GET PR-HI SAVED.

; ADD TO PR-L0 THE HI WORD OF THIS PRODUCT.

; ON CARRY,

; PROPAGATE THRU TO PR-HI.

; GET F1-L0.

; SAVE PR-HI.

PUSH A

LD A, X

; SAVE PR-L0.

; MOVE F1-L0 TO A.

MULT A, W(SP-0A); MULTIPLY BY F2-HI.

POP A ; GET PR-L0 SAVED.

POP K

ADD A, X

IF C

INC K

POP X

RET

; GET PR-HI SAVED.

; ADD TO PR-L0 THE HI-WORD OF THIS PRODUCT.

; PROPAGATE ANY CARRY TO PR-HI.

; RESTORE X.

;

15

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

BFMUL

BFMUL.MAC

50

PAGE:

.END

12

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

BFMUL

ISIOK.MAC

5

6

7

3

4

24

25

1

2

8

9

10

11 F105 02

12 F106 861999CAFC

13 F10B 47

14 F10C 861999CAFD

15 F111 03

16 F112 3C

17 F113 BD9998

18 F116 03

19 F117 3C

20

21

PAGE: 13

.FORM ’ISIOK.MAC’

.INCLD ISIOK.MAC

.TITLE ISIOK

.LOCAL

;

; THIS SUBROUTINE IS USED TO DETERMINE IF ANOTHER DECIMAL DIGIT CAN

; BE ACCUMULATED IN THE 32 BIT INTEGER STORED IN REGS. K AND A.

; THE MORE SIGNIFICANT WORD IS IN K.

; SETS THE CARRY TO 1 IF IT CAN BE ACCUMULATED; RESETS THE CARRY

; OTHERWISE. PRESERVES ALL REGS.

;

ISIOK:

SET C

IFEQ K, 01999

JP $CHKOT

IFGT K, 01999

RESET C

RET

$CHKOT: IFGT A, 09998

RESET C

RET

;

.END

16

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ISIOK

MUL10.MAC

26

27

1

2

3

4

5

6

7

8

9

10 F118 AFCE

11 F11A AFC8

12 F11C A8CA

13 F11E 9E0A

14 F120 AFC8

15 F122 A6FFFCC4A8

16 F127 9E0A

17 F129 3FCA

18 F12B AOCECAF8

19 F12F 3FCE

20 F131 3FCE

21 F133 96CEF8

22 F136 07

23 F137 A9CA

24 F139 3C

25

26

28

PAGE: 14

.FORM ’MUL10.MAC’

.INCLD MUL10.MAC

.TITLE MUL10

.LOCAL

;

; THIS SUBROUTINE MULTIPLIES THE 32 BIT INTEGER STORED IN REGS K AND A

; BY 10-DECIMAL AND ADDS TO IT THE INTEGER STORED IN X.

; THE RESULT IS RETURNED IN K AND A.

; REGS. B AND X ARE NOT CHANGED.

;

MUL10:

PUSH X

PUSH A

LD A, K

MULT A, OA

; SAVE INTEGER.

; SAVE LONG INT-L0.

PUSH A

LD A, W(SP-4)

MULT A, OA

; MULT LONG INT-HI BY 10.

; SAVE LOW WORD OF PRODUCT.

; GET LONG INT-L0.

POP K

ADD K, X

POP X

POP X

ADD A, X

IF C

INC K

RET

; GET L0 WORD OF LAST PRODUCT.

; ADD TO IT HI WORD OF THIS PRODUCT.

; GET RID OF GARBAGE.

; GET INTEGER TO BE ADDED.

;

.END

;

17

10

11

12

13

14

15

16

8

9

6

7

29

30

1

2

3

4

5

21

22

23

24

17

18

19

20

25

26

27

28 F13A AFCE

29 F13C AFCC

30 F13E 00

31 F13F AFC8

32 F141 AFC8

33 F143 AFC8

34 F145 AFC8

35

36

37

38

39

40

41

42

43 F147 C0

44 F148 40

45 F149 9C2B

46 F14B 64

47 F14C 9C2D

48 F14E 45

49 F14F 9C2E

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

MUL10

ATOF.MAC

PAGE: 15

.FORM ’ATOF.MAC’

.INCLD ATOF.MAC

.TITLE ATOF

.LOCAL

;

; THIS SUBROUTINE CONVERTS A DECIMAL FLOATING POINT STRING TO

; AN IEEE FORMAT SINGLE PRECISION FLOATING POINT NUMBER. THE

;

;

; INPUT DECIMAL STRING IS ASSUMED TO BE OF THE FORM

; SMMMMMMM.FFFFFEDNN

; WHERE S IS THE SIGN OF THE DECIMAL MANTISSA,

; M...M IS THE INTEGER PART OF THE MANTISSA,

; AND

;

F...F IS THE FRACTIONAL PART OF THE MANTISSA,

D IS THE SIGN OF THE DECIMAL EXPONENT,

NNN IS THE DECIMAL EXPONENT.

; ON ENTRY, B SHOULD POINT TO THE ADDRESS OF THE ASCII

; STRING HOLDING THE DECIMAL FLOATING POINT NUMBER. THIS STRING

; MUST BE TERMINATED BY A NULL BYTE.

;

; THE BINARY FLOATING POINT NUMBER IS RETURNED IN

; REGS. K AND A.

;

;

;

; REGS. B AND X ARE LEFT UNCHANGED.

;

;

;

ATOF:

PUSH X

PUSH B

CLR A

PUSH A

PUSH A

PUSH A

; ZERO A.

; STORAGE FOR MANTISSA SIGN.

; STORAGE FOR IMPLICIT 10’S EXPONENT.

; STORAGE FOR HI-INT.

PUSH A ; STORAGE FOR L0-INT.

;

; DECIMAL STRING MUST START WITH A ’

0’, ’1’, ’.’ OR A DIGIT.

; RESULTS ARE UNPREDICTABLE IF IT DOES NOT.

; THE ’

0’ MEANS THAT THE MANTISSA IS POSITIVE. IT CAN BE OMITTED.

; THE ’

1’ MEANS THAT THE MANTISSA IS NEGATIVE.

; THE ’.’ MEANS THAT THE MANTISSA HAS NO INTEGER PART.

;

$LOOP1:

LDS A, M(B

0)

NOP

IFEQ A, ’

0’

JP $LOOP1

IFEQ A, ’

1’

JP $MSIGN

IFEQ A, ’.’

; GET THE CHARACTER.

; IF IT IS A ’

0’,

; DO NOTHING, BUT GET 1 MORE.

; IF IT IS A ’

1’,

; GO AND CHANGE THE MANTISSA SIGN.

; IF IT IS A ’.’,

18

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

ATOF.MAC

50 F151 9438

51

52 F153 48

53

54 F154 90FF

55 F156 A6FFF8C4AB

56 F15B 74

57

58

59

60

61 F15C 02

62 F15D 8230C8EB

63 F161 ACC8CE

64 F164 3FCA

65 F166 3FC8

66 F168 3463

67 F16A 07

68 F16B 4B

69

70

71 F16C 3FCE

72 F16E A9CE

73 F170 AFCE

74 F172 AFC8

75 F174 AFCA

76 F176 46

77

78

79

80 F177 345F

81 F179 AFC8

82 F17B AFCA

83

84

85 F17D C0

86 F17E 40

87 F17F 9C2E

88 F181 49

89 F182 9C45

90 F184 9434

91 F186 9C20

92 F188 6B

93

94 F189 952D

95

96

97

98

99 F18B C0

100 F18C 40

PAGE: 16

JMP $FRCOL

JP $INCOL

; GO AND COLLECT THE FRACTION PART.

; GET HERE MEANS IT IS A DIGIT.

; SO GO AND COLLECT THE INTEGER PART.

$MSIGN:

LD A, OFF

ST A, W(SP-08) ; CHANGE MANTISSA SIGN TO NEG.

JP $LOOP1 ; GO BACK FOR SOME MORE.

;

$INCOL:

; GET HERE MEANS COLLECTING INTEGER PART OF MANTISSA.

;

SET C

SUBC A, ’0’

LD X, A

POP K

POP A

JSR ISIOK

IF C

; CONVERT DIGIT FROM ASCII TO INTEGER.

; MOVE INTEGER TO X.

; GET HI-INT COLLECTED SO FAR.

; GET LO-INT COLLECTED SO FAR.

; CHECK IF THE DIGIT CAN BE ACCUMULATED.

; LOOK AT C.

JP $ACCM ; YES, IT CAN BE SO GO DO IT.

; GET HERE MEANS CAN ACCUMULATE ANY MORE.

; SO INCREASE THE IMPLICIT 10’S EXPONENT.

; GET IMPLICIT 10’S EXPONENT COLLECTED POP X

INC X

PUSH X

PUSH A

PUSH K

JP $ISNXT

; SO FAR AND INCREMENT IT.

; SAVE IT BACK.

; SAVE LO-INT.

; SAVE HI-INT.

;

$ACCM:

; GET HERE MEANS THE PRESENT DIGIT CAN BE ACCUMULATED.

JSR MUL10 ; MULTIPLY BY 10 AND ADD DIGIT.

PUSH A

PUSH K

; SAVE L0-INT.

; SAVE HI-INT.

$ISNXT:

; PROCESS THE NEXT CHARACTER.

LDS A, M(B

0)

NOP

IFEQ A, ’.’

JP $FRCOL

IFEQ A, ’E’

JMP $EXCOL

IFEQ A, ’ ’

JP $ISNXT

; IF IT IS A ’.’

; GO COLLECT FRACTION PART.

; IF IT IS ’E’,

; GO COLLECT EXPONENT PART.

; IF IT IS A SPACE,

; GO GET SOME MORE.

; GET HERE MEANS IT IS A DIGIT.

JMP $INCOL

;

$FRCOL:

; GET HERE MEANS COLLECT THE FRACTIONAL PART OF THE MANTISSA.

;

LDS A, M(B

0)

NOP

19

101 F18D 9C45

102 F18F 9429

103 F191 9C20

104 F193 68

105

106 F194 D2

107 F195 8230C8EB

108 F199 ACC8CE

109 F19C 3FCA

110 F19E EFC8

111 F1A0 349B

112 F1A2 07

113 F1A3 45

114

115 F1A4 AFC8

116 F1A6 AFCA

117 F1A8 7D

118

119

120

121 F1A9 3491

122 F1AB 3FCE

123 F1AD 86FFFFCEF8

124 F1B2 AFCE

125 F1B4 AFC8

126 F1B6 AFCA

127 F1B8 952D

128

128

130

131

132 F1BA 03

133

134 F1BB C0

135 F1BC 40

136 F1BD 9C2B

137 F1BF 64

138 F1C0 9C2D

139 F1C2 44

140 F1C3 9C20

141 F1C5 6A

142

143 F1C6 42

144

145 F1C7 02

146 F1C8 6D

147

148

149

150 F1C9 9100

151 F1CB 07

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

ATOF.MAC

PAGE: 17

IFEQ A, ’E’

JMP $EXCOL

IFEQ A, ’ ’

JP $FRCOL

; IF IT IS A ’E’,

; GO COLLECT EXPONENT.

; IF IT IS SPACE,

; GO GET SOME MORE.

; GET HERE MEANS IT IS A DIGIT.

SET C

SUBC A, ’0’

LD X, A

POP K

; GET INTEGER FROM DIGIT.

; SAVE IT IN A.

; GET HI-INT.

POP A

JSR ISIOK

IF C

JP $ACCF

; GET L0-INT.

; CHECK IF IT CAN BE ACCUMULATED.

; YES, SO GO DO IT.

; GET HERE MEANS CAN’T COLLECT MORE DIGITS.

PUSH A

PUSH K

JP $FRCOL ; SO JUST IGNORE IT.

;

$ACCF:

; ACCUMULATE THE FRACTIONAL DIGIT.

JSR MUL10

POP X

ADD X, OFFFF

PUSH X

;

$EXCOL:

; GET HERE MEANS THE EXPLICIT 10’S EXPONENT NEEDS TO BE

; COLLECTED FROM THE STRING.

RESET C ; MAKE EXPONENT SIGN POST.

$EXCHR:

PUSH A

PUSH K

JMP $FRCOL

; SAVE L0-INT.

; SAVE HI-INT.

; GO GET SOME MORE.

LDS A, M(B

0)

MOP

IFEQ A, ’

0’

JP $EXCHR

IFEQ A, ’

1’,

JP $ESIGN

IFEQ A, ’ ’

; IF IT IS A ’

0’,

; GET SOME MORE.

; IF IT IS A ’

1’,

; GO FIX EXPONENT SIGN.

; IF IT IS SPACE,

JP $EXCHR

; MULTIPLY BY 10 AND ADD DIGIT.

; GET IMPLICIT 10’S EXPONENT COLLECTED SO FAR,

; AND DECREMENT IT BY 1.

; SAVE IT BACK.

JP $EXACC

; GO GET SOME MORE.

; GET HERE MEANS IT IS A DIGIT.

; SO GO COLLECT THE EXPONENT.

$ESIGN:

SET C

JP $EXCHR

;

$EXACC:

; ACCUMULATE THE EXPLICIT 10’S EXPONENT.

LD K, 0

IF C

20

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

ATOF.MAC

152 F1CC 91FF

153 F1CE AFCA

154 F1D0 9300

155 F1D2 AFCE

156

157 F1D4 02

158 F1D5 8230C8EB

159 F1D9 ACC8CE

160 F1DC 3FC8

161 F1DE A0C8CEF8

162 F1E2 A0C8CEF8

163 F1E6 E7

164 F1E7 E7

165 F1E8 E7

166 F1E9 96CEF8

167 F1EC AFC8

168 F1EE C0

169 F1EF 40

170 F1F0 9C00

171 F1F2 41

172

173

174 F1F3 7F

175

176

177

178

179 F1F4 3FC8

180 F1F6 3FCA

181 F1F8 8200CAFC

182 F1FC 42

183 F1FD 01

184 F1FE 04

185

186 F1FF AGFFFAC4F8

187 F204 BD7FFF

188 F207 43

189 F208 9300

190 F20A 44

191

192 F20B 93FF

193 F20D 01

194 F20E 04

195

196 F20F ACC8CC

197 F212 3FC8

198 F214 3FCA

199 F216 AFCE

200 F218 AFCC

201

202

PAGE: 18

LD K, OFF

PUSH K

LD X, 0

PUSH X

; GET SIGN BITS SET.

; SAVE EXPLICIT EXPONENTS SIGN.

; ZERO EXPLICIT EXPONENT COLLECTED SO FAR.

$EXCLP:

SET C

SUBC A, ’0’

LD X, A

POP A

ADD X, A

ADD X, A

SHL A

SHL A

; GET INTEGER FROM ASCII DIGIT.

; GET EXPLICIT EXPONENT COLLECTED SO FAR.

; X CONTAINS DIGIT

0 EXP.

; X CONTAINS DIGIT

0 2*EXP.

SHL A

ADD A, X

PUSH A

LDS A, M(B

0)

NOP

IFEQ A, 0

JP $A10EX

; A CONTAINS 8

*EXP.

; A CONTAINS DIGIT

0 10*EXP.

; SAVE BACK ON STACK.

; GET NEXT CHAR.

; IS IT A NULL ?

; YES SO ADD EXPLICIT AND IMPLICIT

JP $EXCLP

; 10’S EXPONENT.

; GET HERE MEANS IT IS A DIGIT,

; SO GO BACK AND ACCUMULATE IT.

;

$A10EX:

; DONE COLLECTING DIGITS. ADD THE EXPLICIT AND IMPLICIT

; 10’S EXPONENT COLLECTED SO FAR.

POP A ; GET EXPLICIT 10’S EXPONENT.

POP K ; GET ITS SIGN.

IFEQ K, 0

JP $ADDEX

COMP A

INC A

; IS IT POSITIVE ?

; YES SO ADD ’EM.

; CHANGE TO 2’S COM.

$ADDEX:

ADD A, W(SP-06) ; ADD IMPLICIT EXPONENT.

IFGT A, 07FFF

JP $NEG10

; IS IT NEGATIVE ?

; YES, CHANGE IT.

LD X, 0

JP $ESAVE

; LOAD POST. SIGN IN X.

$NEG10

LD, X, OFF

COMP A

INC A

; LOAD NEG. SIGN IN X.

; MAKE IT POSITIVE.

$ESAVE:

LD B, A

POP A

POP K

PUSH X

; SAVE 10’S EXPONENT IN A.

; GET HI-INT.

; GET L0-INT.

; SAVE SIGN OF 10’S EXPONENT.

PUSH B ; AND ITS VALUE.

;

; NOW CONVERT HI-INT.LO-INT TO A NORMALIZED FLOATING POINT

21

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

ATOF.MAC

203

204

205 F21A 9000

206 F21C 58

207 F21D 8200CAFD

208 F221 4E

209

210 F222 00

211 F223 ACC8CA

212 F226 02

213 F227 8208C4EB

214 F22B 3FCC

215 F22D 3FCE

216 F22F 3C

217

218

219

220 F230 AECA

221 F232 9210

222 F234 42

223

224

225

226 F235 9220

227

228 F237 E7

229 F238 07

230 F239 4D

231 F23A AECA

232 F23C E7

233 F23D 07

234 F23E 96CA08

235 F241 AECA

236 F243 AACC

237 F245 40

238 F246 6F

239

240 F247 D7

241 F248 AB00

242 F24A 3FCE

243 F24C 3FC8

244 F24E AE00

245 F250 AFCC

246 F252 AFCE

247 F254 AECA

248 F256 960010

249 F259 58

250

251

252

253

PAGE: 19

; NUMBER. THE BINARY EXPONENT IS COLLECTED IN B.

;

IFGT A, 0

JP $NORM2

; IF HI-INT IS NOT 0,

; NEED TO SHIFT K AND A.

IFGT K, 0

JP $NORM1

; IF HI-INT IS 0, BUT NOT LO-INT,

; NEED TO SHIFT ONLY K.

; GET HERE MEANS MANTISSA IS 0.

CLR A

LD K, A

SET C

SUB SP, 08 ; ADJUST SP. DONE!!!

POP B

POP X

RET

;

$NORM1:

; HI-INT IS 0, SO WORK WITH LO-INT ONLY.

X A, K

LD B, 010

JP $NRLUP

; LOAD 16 INTO EXPONENT COUNTER.

;

$NORM2:

; HI-INT IS NOT 0, SO NEED TO HANDLE BOTH.

LD B, 020 ; LOAD 32 INTO LOOP COUNTER.

$NRLUP:

SHL A

IF C

JP $NRDUN

X A, K

; DID A 1 COME OUT ?

; YES IT IS NORMALIZED NOW.

SHL A

IF C

SET K.0

X A, K

DECSZ B

NOP

JP $NRLUP

; SHOULD NEVER BE SKIPPED!!

$NRDUN:

RRC A

ST A, TMP1

POP X

POP A

X A, TMP1

PUSH B

PUSH X

; RESTORE SHIFTED 1.

; STORE IN W(0).

; GET 10’S EXPONENT.

; GET 10’S EXPONENT SIGN.

; A IS HI-INT ONCE MORE.

; SAVE BINARY EXPONENT.

; SAVE 10’S EXPONENT.

X A, K

IF TMP1.0

; HI-INT TO K, LO-INT TO A.

; IS 10’S EXPONENT NEGATIVE ?

JP $DIV10 ; YES, GO TO DIVIDE BY 10.

; GET HERE MEANS 10’S EXPONENT IS POSITIVE, SO MULTIPLY BY 10.

; ACTUALLY, WHAT IS USED IS

; 10>N 4 (0.625*(2>4)>N

; SO MULTIPLY BY 0.625 NOW AND TAKE CARE OF 2>(4*N) LATER.

22

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

ATOF.MAC

254 F25A A4F26ACCAB

255 F25F AFCC

256 F261 A4F26CCCAB

257 F266 AFCC

258 F268 57

259

260

261

262 F269 40

263 F26A 0000

264 F26C 00A0

265 F26E CDCC

266 F270 CCCC

267

268

269

270

271

272

273 F272 A4F26ECCAB

274 F277 AFCC

275 F279 A4F270CCAB

276 F27E AFCC

277

278

279

280 F280 9200

281

282 F282 8200CEFC

283 F286 57

284

285 F287 35C0

286 F289 AECA

287 F28B E7

288 F28C 07

289 F28D 4A

290 F28E A9CC

291

292 F290 AECA

293 F292 E7

294 F293 07

295 F294 96CA08

296 F297 43

297

298 F298 D7

299 F299 AECA

300

301 F29B AACE

302 F29D 76

303

304

PAGE: 20

LD B, W($MTL0)

PUSH B

LD B, W($MTHI)

PUSH B

JP $JAMIT

; SAVE L0 WORD OF 0.625 ON STACK.

; SAVE HI WORD OF 0.625 ON STACK.

; GO TO ROUTINE THAT JAMS 0.625>N

; BY REPEATED MULTIPLICATION INTO HI-INT.LO-INT.

;

; DEFINE SOME CONSTANTS.

. EVEN ; FORCE EVEN ADDRESS.

$MTLO: .WORD 0

$MTHI: .WORD 0A000

$DTLO: .WORD 0CCCD

$DTHI: .WORD 0CCCC

;

$DIV10:

; GET HERE MEANS 10’S EXPONENT IS NEGATIVE, SO DIVIDE BY 10.

; ACTUALLY WHAT IS DONE IS

; 10>(1N) 4 ((2>3)/(0.8))>(1N) 4 ((0.8)>N)*(2>(13*N)))

; SO MULTIPLY BY 0.8 NOW AND TAKE CARE OF 2>(13*N) LATER.

LD B, W($DTLO)

; SAVE LO WORD OF .8

; SAVE HI WORD OF .8

;

$JAMIT:

; JAM IN THE MULTIPLICATION PART NEEDED TO HANDLE THE 10’S EXP.

LD B, 0

IFEQ X, 0

JP $JAMDN

; B IS USED TO TRACK ANY BINARY POWERS

; THAT COME UP DURING NORMALIZATION.

; IS 10’S EXPONENT 0 ?

; YES, DONE ALREADY.

$JAMLP:

PUSH B

LD B, W($DTHI)

PUSH B

JSR BFMUL

X A, K

SHL A

IF C

; MULTIPLY USING 32 BIT UNSIGNED.

; SWAP HI AND LO WORDS.

JP $ISNED

INC B

; IS THERE A CARRY ?

; YES, SO IT IS ALREADY NORMALIZED.

; NEED TO SHIFT LEFT TO NORMALIZE, SO

; INCREASE B BY 1.

X A, K

SHL A

IS C

SET K.0

JP $OVR1

$ISNED:

RRC A

X A, K

$OVR1:

DECSZ X ; DONE YET ?

JP $JAMLP ; NO SO DO IT ONCE MORE.

; GET HERE MEANS MULTIPLICATIONS HAVE BEEN DONE. NOW TAKE

; CARE OF THE EXPONENTS.

23

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

ATOF.MAC

305

306 F29E 3FCE

307 F2A0 3FCE

308 F2A2 3FCE

309 F2A4 AFC8

310 F2A6 AFCA

311 F2A8 A6FFFAC4A8

312 F2AD 02

313 F2AE 96CCEB

314

315 F2B1 ACC8CC

316 F2B4 A8CE

317 F2B6 960010

318 F2B9 49

319

320

321 F2BA E7

322 F2BB E7

323 F2BC 96CCF8

324 F2BF B8007E

325 F2C2 4C

326

327

328

329

330 F2C3 E7

331 F2C4 96CEF8

332 F2C7 01

333 F2C8 04

334 F2C9 96CCF8

335 F2CC B8007E

336

337

338 F2CF ACC4CE

339 F2D2 02

340 F2D3 820ACEEB

341 F2D7 AFCE

342 F2D9 BD7FFF

343 F2DC B4FD3F

344 F2DF 9C00

345 F2E1 B4FD3A

346 F2E4 9DFE

347 F2E6 B4FD46

348

349 F2E9 3FCE

350 F2EB E7

351 F2EC E7

352 F2ED E7

353 F2EE E7

354 F2EF E7

355 F2FD E7

PAGE: 21

$JAMDN:

POP X

POP X

POP X

PUSH A

PUSH K

LD A, W(SP-6)

SET C

SUBC A, B

; GET 0.625 OR 0.8 OFF THE STACK.

; GET THE 10’S EXPONENT.

; SAVE LO WORD OF FLP NUMBER.

; SAVE HI WORD OF FLP NUMBER.

; GET THE BINARY EXPONENT THAT WAS SAVED.

LD B, A

LD A, X

IF TMP1.0

JP $NAGAS

; SUBTRACT FROM IT BINARY EXPONENT COLLECTED

; DURING THE JAMMING.

; SAVE IT IN B.

; MOVE THE 10’S EXPONENT TO A.

; IS THE 10’S EXPONENT NEGATIVE ?

; YES, SO GOT TO SUBTRACT.

; GET HERE MEANS 10’S EXPONENT IS

SHL A

SHL A

ADD A, B

ADD A, 07E

JP $EXCPT

; POSITIVE, SO MUL IT BY 4.

; MULTIPLY BY 2.

; MULTIPLY BY 2 AGAIN.

; GET THE BINARY EXPONENT IN ALSO.

; AND THE IEEE BIAS.

; GO CHECK FOR OVER/UNDERFLOW.

;

$NAGAS:

; GET HERE MEANS 10’S EXPONENT IS NEGATIVE, SO GOT TO MULTIPLY

; IT BY

13.

SHL A ; MULTIPLY BY 2.

ADD A, X

COMP A

INC A

; ADD TO GIVE MULTIPLY BY 3.

ADD A, B

ADD A, 07E

; MAKE IT NEGATIVE.

; GET IN THE BINARY EXPONENT.

; AND THE IEEE BIAS.

$EXCPT:

; CHECK FOR OVERFLOW/UNDERFLOW.

LD X, SP

SET C

SUBC X, OA

PUSH X

; FIRST DO SOME JUGGLING

; TO BE COMPATIBLE WITH EXCEPTION

; HANDLING IN OTHER ROUTINES.

IFGT A, 07FFF

JMPL UNDFL

IFEQ A, 0

; IS BIASED EXPONENT NEGATIVE ?

JMPL UNDFL

IFGT A, OFE

; IS IT 0 ?

; YES IT IS STILL UNDERFLOW.

; IS IT GT THAN 254 ?

JMPL OVRFL

; GET HERE MEANS VALID SP FLP NUMBER.

POP X

SHL A

; X POINTS TO MANTISSA SIGN.

SHL A

SHL A

SHL A

SHL A

SHL A

24

356 F2F1 E7

357 F2F2 E7

358 F2F3 8FFA

359 F2F5 AB00

360 F2F7 3FCA

361 F2F9 3FC8

362 F2FB F1

363 F2FC A8CA

364 F2FE F1

365 F2FF A800

366 F301 F3

367 F302 3664

368 F304 F2

369 F305 F2

370 F306 AFCE

371 F308 368C

372 F30A 3FC4

373 F30C 3FCC

374 F30E 3FCE

375 F310 3C

376

377

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

ATOF.MAC

;

SHL A

SHL A

OR A, W(X)

ST A, TMP1

POP K

POP A

X A, W(X

0)

LD A, K

X A, W(X

0)

LD A, TMP1

X A, W(X

1)

JSRL SROUND

LD A, W(X

1)

LD A, W(X

1)

PUSH X

JSR FPAK

POP SP

POP B

POP X

RET

PAGE:

.END

22

; MOVE EXPONENT TO HIGH BYTE.

; GET THE MANTISSA SIGN IN.

; SAVE IT IN TMP1.

; FI-HI TO K.

; F1-LO TO A.

; SAVE F1-L0.

; SAVE F1-HI.

; SAVE F1-EXP.F1-SIGN, X POINTS TO F1-HI.

; ROUND THE RESULT.

; X POINTS TO F1-HI.

; X POINTS TO F1-LO.

; PACK IT INTO IEEE FORMAT.

25

10

11

12

13

14

15

16

8

9

6

7

31

32

1

2

3

4

5

17

18

19

20

21 F311 AFCE

22 F313 AFCC

23

24 F315 3605

25 F317 07

26 F318 B401B4

27

28 F31B 36CA

29 F31D 07

30 F31E B401C8

31

32 F321 ACC4CE

33 F324 8206C4F8

34 F328 36C7

35

36

37

38

39

40

41

42

43

44

45

46 F32A D2

47 F32B D2

48 F32C B7000000

49 F330 B8FF82

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

ATOF

FTOA.MAC

PAGE: 23

.FORM ’FTOA.MAC’

.INCLD FTOA.MAC

.TITLE FTOA

.LOCAL

;

; THIS SUBROUTINE CONVERTS A SINGLE PRECISION, BINARY FLOATING

; POINT NUMBER IN THE IEEE FORMAT TO A DECIMAL FLOATING POINT

; STRING. THE DECIMAL FLOATING POINT STRING IS OBTAINED TO A

; PRECISION OF 9 DECIMAL DIGITS.

;

; THE ALGORITHM USED IS BASED ON:

; J.T. COONEN, ’AN IMPLEMENTATION GUIDE TO A PROPOSED STANDARD

; FOR FLOATING POINT ARITHMETIC,’ IEEE COMPUTER, JAN. 1980, PP 68-79.

;

; ON INPUT, THE BINARY SP FLP NUMBER IS IN REGS. K AND A.

; B CONTAINS THE ADDRESS OF THE LOCATION WHERE THE DECIMAL FLOATING

; POINT STRING IS TO START. NOTE THAT AT LEAST 17 BYTES ARE NEEDED

; FOR THE STORAGE OF THE STRING. THE LAST BYTE IS ALWAYS NULL.

;

; ALL REGISTERS ARE PRESERVED BY THIS SUBROUTINE.

;

FTOA:

PUSH X

PUSH B

; SAVE X ON THE STACK.

; SAVE B ON THE STACK.

; CHECK AND SEE IF F1 IS A NAN.

JSR FNACHK

IF C

JMPL $NAN ; YET IT IS, SO GET OUT.

; CHECK AND SEE IF F1 IS ZERO.

JSR FZCHK

IF C

JMPL $ZERO ;YES IT IS, SO GET OUT.

; GET HERE MEANS F1 IS A NON-ZERO, NON-NAN FLP NUMBER.

LD X, SP

ADD SP, 06

JSR FUNPAK

; ADJUST SP.

; UNPACK THE NUMBER.

; X POINTS ONE WORD PAST F1-EXP.F1-SIGN

; ON RETURN.

;

; COMPUTE THE EXPONENT OF 10 FOR DECIMAL FLP NO.

; THIS IS DONE AS FOLLOWS:

;

;

;

SUPPOSE F1

4 FM * (2>M)

LET U

4 M*LOG(2)

THEN V

4 INT(U0119)

;

NOTE: LOG IS TO BASE 10.

IS USED AS THE 10’S EXPONENT.

; NOTE: INT REFERS TO INTEGER PART.

;

LD A, M(X

1)

LD A, M(X

1)

LD TMP1, 0

ADD A, 0FF82

; X POINTS TO F1-EXP.

; LOAD F1-EXP. X POINTS TO F1-SIGN.

; FIRST GUESS POSITIVE SIGN FOR EXP.

; REMOVE IEEE BIAS FROM F1-EXP.

26

97

98

99

100

90

91

92

93

94

95

96

50 F333 AFC8

51 F335 AFCE

52 F337 07

53 F338 46

54 F339 B700FF00

55 F33D 01

56 F33E 04

57

58

59 F33F BE4D10

60

61 F342 AECE

62 F344 960010

63 F347 41

64 F348 4B

65

66 F349 01

67 F34A AECE

68 F34C 01

69 F34D B80001

70 F350 AECE

71 F352 07

72 F353 04

73

74 F354 04

75 F355 B8FFF7

76 F358 BD7FFF

77 F35B 45

78 F35C B7000000

79 F36D 4F

80

81 F361 B700FF00

82 F365 01

83 F366 AECE

84 F368 01

85 F369 B80001

86 F36C AECE

87 F36E 07

88 F36F 04

89

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FTOA.MAC

PAGE: 24

PUSH A

PUSH X

IF C

JP $MLOG2

LD TMP1, OFF

COMP A

INC A

$MLOG2:

; MULTIPLY M BY LOG(2).

MULT A, 04D10

; SAVE IT ON THE STACK.

; SAVE F1-SIGN ADDRESS ALSO.

; WAS THERE A CARRY ON THE LAST ADD ?

; YES, SO 2’S EXP IS POSITIVE.

; 2’S EXPONENT IS NEGATIVE.

; MAKE IT POSITIVE.

X A, X

IF TMP1.0

JP $CSIGN

JP $REMV9

; LOG(2) IS 0.0100110100010000 TO 16 BITS.

; X CONTAINS INTEGER PART, AND A FRACT. PART.

; SWAP THE TWO.

; WAS THE 2’S EXPONENT NEGATIVE ?

; YES, SO MAKE U NEGATIVE.

; NO, SO GO DO V

4 U 0 1 1 9.

$CSIGN:

COMP A

X A, X

COMP A

ADD A, 01

X A, X

IF C

INC A

; COMP INTEGER PART.

; FRACTION PART.

$REMV9:

INC A

ADD A, 0FFF7

IFGT A, 07FFF

JP $CHNGS

LD TMP1, 0

JP $DIV10

; INCREASE FRACTION PART.

; SUBTRACT 9.

; IS IT NEGATIVE ?

; YES, SO CHANGE ITS SIGN.

; REMEMBER POSITIVE SIGN.

$CHNGS:

LD TMP1, OFF

COMP A

X A, X

COMP A

; REMEMBER NEGATIVE SIGN.

; MAKE V POSITIVE.

ADD A, 01

X A, X

IF C

INC A

$DIV10:

;

; V

4 INT (U0119) HAS BEEN COMPUTED AND IS IN A.

; NOW COMPUTE W

4 F1/(10>V). W SHOULD BE AN INTEGER, AND IT IS

; COMPUTED TO A 32 BIT PRECISION.

; THIS COMPUTATION IS DONE AS FOLLOWS:

;

;

IF V l

0, THEN F1/(10>V) 4 F1*(0.8>V)*(2>(13V)).

IF V k

0, THEN F1/(10>V) 4 F1*(0.625>U)*(2>(4V)).

; SO FIRST MULTIPLY THE MANTISSA OF F1 V TIMES BY 0.8 (OR 0.625)

; AND THEN ADJUST THE EXPONENT OF F1. NOTE THAT THE PARTIAL PRODUCTS

; IN MULTIPLYING BY 0.8 (OR 0.625) ARE KEPT NORMALIZED. THIS IS

; ESSENTIAL TO PRESERVE 32 BIT ACCURACY IN THE FINAL RESULT.

27

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FTOA.MAC

101

102

103

104

105 F370 3FCE

106 F372 AFC8

107 F374 ACC8CC

108 F377 F2

109 F378 F2

110 F379 ACC8CA

111 F37C F4

112 F370 960010

113 F380 57

114

115 F381 A4F390CEAB

116 F386 AFCE

117 F388 A4F392CEAB

118 F38D AFCE

119 F38F 56

120

121

122 F390 CDCC

123 F392 CCCC

124 F394 0000

125 F396 00A0

126

127

128 F398 A4F394CEAB

129 F39D AFCE

130 F39F A4F396CEAB

131 F3A4 AFCE

132

133

134 F3A6 9300

135

136

137 F3A8 8200CCFC

138 F3AC 57

139

140 F3AD 36E6

141 F3AF AECA

142 F3B1 E7

143 F3B2 07

144 F3B3 4A

145

146 F3B4 A9CE

147 F3B6 AECA

148 F3B8 E7

149 F3B9 07

150 F3BA 96CA08

151 F3BD 43

PAGE: 25

; SINCE THE MANTISSA OF F1 IS NORMALIZED, AND 0.8 (OR 0.625 IS ALSO

; NORMALIZED, EACH PRODUCT NEEDS AT MOST 1 LEFT SHIFT FOR

; RENORMALIZATION. THE SHIFTS ACCUMULATED DURING RENORMALIZATION ARE

; TRACKED AND ACCOUNTED FOR IN THE CALCULATION.

POP X

PUSH A

LD B, A

LD A, W(X

1)

LD A, W(X

1)

LD K, A

LD A, W(X)

IF TMP1.0

JP $MUL10

; X NOW POINTS TO F1-SIGN.

; SAVE U ON THE STACK.

; MOVE V TO B ALSO.

; X POINTS TO F1-HI.

; LOAD F1-HI. X POINTS TO F1-L0.

; LOAD F1-L0.

; IS V NEGATIVE?

; YES, SO MULTIPLY V TIMES BY .625.

; GET HERE MEANS MULTIPLY V TIMES BY .8.

LD X, W($DTL0)

PUSH X

LD X, W($DTHI)

PUSH X

; L0 WORD OF 0.8 TO STACK.

; HI WORD OF 0.8 TO STACK.

; GO DO MULTIPLICATION.

JP $JAMIT

;

.EVEN

$DTL0: .WORD OCCCD

$DTHI: .WORD 0CCCC

$MIL0: .WORD 0

$MTHI: .WORD 0A000

;

$MUL10:

LD X, W($MTL0)

PUSH X

LD X, W($MTHI)

PUSH X

; FORCE EVEN ADDRESS.

; L0 WORD OF 0.625 TO STACK.

; HI WORD OF 0.625 TO STACK.

;

$JAMIT:

LD X, 0

IFEQ B, 0

JP $JAMON

; INIT X TO TRACK ANY POWERS OF

; 2 GENERATED DURING NORMALIZATION

; OF PARTIAL PRODUCTS.

; IS B ALREADY 0 ?

; YES, SO SKIP MULTIPLY LOOP.

$JAMLP:

JSR BFMUL

X A, K

SHL A

IF C

JP $ISNED

INC X

X A, K

SHL A

IF C

SET K.0

JP $OVR1

; MULTIPLY.

; SWAP HI AND LO WORDS OF PART. PROD.

; IS THERE A CARRY ?

; YES, SO SKIP OVER RENORMALIZATION.

; GET HERE MEANS NEED TO RENORM.

; UPDATE RENORM COUNT.

; SWAP HI AND LO PART. PROD.

; SET BIT SHIFTED OUT FROM LO WORD.

28

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FTOA.MAC

152

153 F3BE D7

154 F3BF AECA

155

156 F3C1 AACC

157 F3C3 76

158

159

160

161 F3C4 3FCC

162 F3C6 3FCC

163 F3C8 AFC8

164 F3CA AFCA

165 F3CC A6FFF8C4A8

166 F3D1 02

167 F3D2 96CEEB

168

169 F3D5 ACC8CE

170 F3D8 A6FFFAC4A8

171 F3DD 960010

172 F3E0 49

173

174 F3E1 E7

175 F3E2 A6FFFAC4F8

176 F3E7 01

177 F3E8 04

178 F3E9 42

179

180 F3EA E7

181 F3EB E7

182

183 F3EC 96CEF8

184

185

186 F3EF 9020

187 F3F1 5A

188 F3F2 9D1B

189 F3F4 9435

190

191

192 F3F6 3FC8

193 F3F8 3FC8

194 F3FA 3FC8

195 F3FC 96D010

196 F3FF 56

197

198

199 F400 B8FFFF

200 F403 07

201 F404 5A

202 F405 01

PAGE: 26

$ISNED:

RRC A

X A, K

; PUT BACK SHIFTED BIT.

$OVR1:

DECSZ B

JP $JAMLP

; IS B 0 YET ?

; NO, SO DO IT AGAIN.

$JAMON:

; GET HERE MEANS MULTIPLICATION HAS BEEN DONE, SO TAKE CARE

; OF EXPONENT.

POP B

POP B

PUSH A

PUSH K

; GET RID OF 0.8 (OR 0.625) FROM STACK.

; SAVE LO WORD OF PROD.

; SAVE HI WORD OF PRODUCT.

LD A, W(SP-08) ; GET F1’S BINARY EXPONENT.

SET C

SUBC A, X ; SUBTRACT FROM IT ANYTHING COLLECTED

; DURING RENORM.

LD X, A ; AND SAVE IT IN X.

LD A, W(SP

106) ; GET V FROM THE STACK.

IF TMP1.0

; IS V NEGATIVE ?

JP $ML4 ; YES, SO MULTIPLY V BY 4.

; GET HERE MEANS MULTIPLY V BY

13.

SHL A ; NOW A CONTAINS 2

*V.

ADD A, W(SP

106) ; NOW A CONTAINS 3*V.

COMP A

INC A

JP $ADEM

; NOW A CONTAINS

13*V.

; GO FIGURE FINAL EXPONENT.

$ML4:

$ADEM:

SHL A

SHL A

ADD A, X

; NOW A CONTAINS 4

*V.

;

; A SHOULD NOW BE A POSITIVE INTEGER

; IN THE RANGE 0 TO 32.

; NOW CHECK AND SEE IF A HAS ENOUGH PRECISION.

IFGT A, 020 ; NEED MORE THAN 32 BITS ?

JP $INCRV

IFGT A, 01B

JMP $GOON

; YES, SO GO INCREASE V.

; NEED AT LEAST 28 BITS ?

; YES, SO ALL IS OK. GO ON.

; GET HERE MEANS NEED MORE

; PRECISION, SO DECREASE V.

POP A

POP A

POP A

IF TMP1.0

JP $VUP

ADD A, 0FFFF

IF C

JP $GOBAK

COMP A

; GET HI-PROD OFF STACK.

; GET LO WORD OFF STACK.

; GET MAGN. OF V.

; IS V NEG. ?

; YES, SO GO INCR. MAGN. OF V.

; GET HERE MEANS V IS POSITIVE,

; AND NEED TO DECREMENT IT.

; SUBTRACT 1 FROM A.

; GOT A CARRY ?

; THEN OK.

29

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FTOA.MAC

203 F406 04

204 F407 B700FF00

205 F40B 53

206

207 F40C 3FC8

208 F40E 3FC8

209 F410 3FC8

210 F412 960010

211 F415 42

212

213 F416 04

214 F417 47

215

216 F418 AAC8

217 F41A 44

218 F41B B7000000

219

220 F41F ACC4CE

221 F422 02

222 F423 8204CEEB

223 F427 AFCE

224 F429 95B9

225

226 F42B 01

227 F42C 04

228 F42D B80020

229 F430 ACC8CE

230 F433 3FCA

231 F435 3FC8

232 F437 8200CEFC

233 F43B 49

234

235

236 F43C AECA

237 F43E C7

238 F43F AECA

239 F441 D7

240 F442 AACE

241 F444 68

242

243

244

245 F445 AFC8

246 F447 AFCA

247 F449 A6FFF0C4A8

248 F44E B80010

249 F451 ACC8CC

250 F454 00

251 F455 C3

252 F456 40

253 F457 A6FFFAC4A8

PAGE: 27

INC A

LD TMP1, OFF

JP $GOBAK

; U CHANGES SIGN.

$INCRV:

POP A

POP A

POP A

IF TMP1.0

JP $VDOWN

; GET HI PROD. OFF STACK.

; GET LO PROD. OFF STACK.

; GET MAGN. OF V.

; IS V NEGATIVE ?

; YES.

$VUP:

INC A

JP $GOBAK

$VDOWN:

DECSZ A

JP $GOBAK

LD TMP1, 0 ; V CHANGES SIGN.

$GOBAK:

LD X, SP

SET C

SUBC X, 04

PUSH X

JMP $DIV10

$GOON:

COMP A

INC A

ADD A, 020

LD X, A

POP X

POP A

; NEGATE A.

; SUBTRACT IT FROM 32.

; AND MOVE IT TO X.

; GET HI WORD OF PRODUCT.

; GET LO WORD OF PROD.

IFEQ X, 0

JP $INDUN

X A, K

SHR A

; IS X 0 ?

; YES, SO ALREADY A 32 BIT INTEGER.

$INTFY:

; NOW ADJUST THE PRODUCT TO FORM A 32 BIT INTEGER.

; SWAP HI AND LO WORDS.

X A, K

RRC A

DECSZ X

JP $INTFY

; SHIFT IT RIGHT ONCE.

; X 0 YET ?

; NO SO GO DO SOME MORE.

$INDUN:

; GET HERE MEANS K.A CONTAIN THE 32 BIT INTEGER THAT IS THE

; MANTISSA OF THE DECIMAL FLP NUMBER.

PUSH A

PUSH K

; SAVE LO-INT.

; SAVE HI INT.

LD A, W(SP-010) ; GET STARTING ADDRESS OF DECIMAL STRING.

ADD A, 010 ; ADD 16 TO IT.

LD B, A

CLR A

XS A, M(B

1)

NOP

; AND MOVE IT B.

; OUTPUT TERMINATING NULL BYTE.

LD A, W(SP-06) ; GET V.

30

254 F45C 9F0A

255

256 F45E AECE

257 F460 B80030

258 F463 C3

259 F464 40

260 F465 A8CE

261 F467 B80030

262 F46A C3

263 F46B 40

264 F46C 902B

265 F46E 960010

266 F471 902D

267 F473 C3

268 F474 40

269 F475 9045

270 F477 C3

271 F478 40

272 F479 902E

273 F47B C3

274 F47C 40

275

276 F47D B7000A00

277

278 F481 3FC8

279 F483 9FOA

280

281 F485 ACC8CA

282 F488 3FC8

283 F48A AFCC

284 F48C ACCACC

285 F48F 82

F490 0A

F491 C8

F492 EF

286

287

288

289

290 F493 ACCCCA

291 F496 3FCC

292 F498 AFC8

293 F49A AFCA

294 F49C A8CE

295 F49E B80030

296 F4A1 C3

297 F4A2 40

298 F4A3 AA00

299 F4A5 9524

300

301 F4A7 3FC8

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FTOA.MAC

PAGE: 28

DIV A, OA

X A, X

ADD A, 030

XS A, M(B

1)

NOP

LD A, X

ADD A, 030

XS A, M(B

1)

NOP

LD A, 028

IF TMP1.0

LD A, 02D

XS A, M(B

1)

NOP

LD A, 045

XS A, M(B

1)

NOP

; DIVIDE IT BY 10. QUOT. IN A,

; REM. IN X.

; REM TO A.

; MAKE IT INTO ASCII BYTE.

; OUTPUT IT.

; FINISHED OUTPUTING EXPONENT.

; SAY EXP SIGN IS ’

; NOPE, IT IS ’

; OUTPUT IT.

; OUTPUT ’E’.

1’.

0’.

LD A, 02E

XS A, M(B

1)

NOP

; OUTPUT ’.’.

; NOW NEED TO OUTPUT 10 DECIMAL DIGITS.

LD TMP1, OA ; LOAD 10 INTO TMP1 AS LOOP COUNTER.

$DOLUP:

POP A

DIV A, OA

; A CONTAINS HI INT.

; DIVIDE IT BY 10. QUOT. IN A,

; REM. IN X.

LD K, A

POP A

PUSH B

LD B, K

; A CONTAINS LO INT.

; SAVE DEC. STR. ADDR.

; B CONTAINS HI-QUOT.

.BYTE 082,0A,OC8,OEF

; THE ABOVE 4 BYTES REPRESENT THE INSTRUCTION DIVD A, OA.

; BECAUSE THE ASSEMBLER DOES NOT KNOW ABOUT IT YET, WE HAVE TO

; KLUDGE IT THIS WAY.

; AFTER THE DIVD, A CONTAINS THE LO-QUOT. AND X THE REM.

LD K, B ; MOVE HI-QUOT TO K.

POP B

PUSH A

PUSH K

LD A, X

ADD A, 030

XS A, M(B

1)

NOP

DECSZ TMP1

; B CONTAINS DEC. STR. ADDR.

; SAVE LO INT.

; SAVE HI INT.

; MOVE REM TO A.

; ASCII-FY IT.

; AND OUTPUT IT.

; IS TMP1 0 YET ?

JMP $DOLUP ; NO, GO GET SOME MORE.

; GET HERE MEANS DONE WITH OUTPUTING MANTISSA.

POP A

31

302 F4A9 3FC8

303 F4AB 3FC8

304 F4AD 3FC8

305 F4AF 3FCA

306 F4B1 9020

307 F4B3 96CA10

308 F4B6 902D

309 F4B8 C6

310 F4B9 AFCA

311 F4BB ACC4CE

312 F4BE 02

313 F4BF 8206CEEB

314 F4C3 AFCE

315 F4C5 B5FBB4

316 F4C8 3FC4

317 F4CA 3FCC

318 F4CC 3FCE

319 F4CE 3C

320

321

322

323 F4CF AFC8

324 F4D1 ACCCCE

325 F4D4 8210CEF8

326 F4D8 00

327 F4D9 03

328 F4DA 9210

329

330 F4DC 90FF

331 F4DE D3

332 F4DF AACC

333 F4E1 65

334 F4E2 3FC8

335 F4E4 3FCC

336 F4E6 3FCE

337 F4E8 3C

338

339

340

341 F4E9 AFC8

342 F4EB ACCCCE

343 F4EE 8210CEF8

344 F4F2 00

345 F4F3 D3

346 F4F4 9030

347 F4F6 D3

348 F4F7 9030

349 F4F9 D3

350 F4FA 902B

351 F4FC D3

352 F4FD 9045

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FTOA.MAC

0

PAGE: 29

POP A

POP A

POP A

POP K

LD A, 02D

IF K.0

LD A, 02D

ST A, M(B)

PUSH K

LD X, SP

SET C

SUBC X, 06

PUSH X

JSR FPAK

POP SP

POP B

POP X

RET

; GET SOME GARBAGE OFF THE STACK.

; GET F1-EXP.F1-SIGN TO K.

; LOAD SP INTO A.

; IF MAINT. IS NEG. LOAD ’

; OUTPUT SIGN.

1’.

; F1-EXP.F1-SIGN BACK ON STACK.

; X POINTS TO F1-LO.

; PACK IT, SO RESTORING K AND A.

; RESTORE B.

; RESTORE X.

;

$NAN:

; GET HERE MEANS F1 IS A NAN.

PUSH A

LD X, B

ADD X, 010

CLR A

X A, M(X

1)

LD B, 010

$NANLP:

LD A, OFF

X A, M(X

1)

DECSZ B

JP $NANLP

POP A

POP B

POP X

RET

;

$ZERO:

; GET HERE MEANS F1 IS ZERO.

PUSH A

; X CONTAINS DECIMAL STRING ADDR.

LD X, B

ADD X, 010

CLR A

X A, M(X

1)

LD A, 030

X A, M(X

1)

LD A, 030

X A, M(X

1)

LD A, 02B

X A, M(X

1)

LD A, 045

; OUTPUT TERMINATING NULL BYTE.

; LOAD 0 INTO A.

; OUTPUT 00 FOR EXPONENT.

; LOAD ’

0’ SIGN.

; LOAD ’E’

32

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FTOA.MAC

353 F4FF D3

354 F500 902E

355 F502 D3

356 F503 920A

357

358 F505 9030

359 F507 D3

360 F508 AACC

361 F50A 65

362 F508 9020

363 F50D D5

364 F50E 3FC8

365 F510 3FCC

366 F512 3FCE

367 F514 3C

368

369

$ZERLP:

LD A, 030

X A, M(X

1)

DECSZ B

JP $ZERLP

LD A, 020

X A, M(X)

POP A

POP B

POP X

RET

;

X A, M(X

1)

LD A, 02E

X A, M(X

1)

LD B, OA

.END

PAGE: 30

; LOAD ’.’.

; LOAD SP.

33

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FTOA

FADD.MAC

PAGE: 31

10

11

12

13

14

15

16

8

9

6

7

33

34

1

2

3

4

5

17

18

19 F515 AB00

20 F517 A6FFFAC4A8

21 F51C AFC8

22 F51E A6FFFAC4A8

23 F523 BB8000

24 F526 AFC8

25 F528 A800

26 F52A 3009

27 F52C AB00

28 F52E 3FC8

29 F530 3FC8

30 F532 A800

31 F534 3C

32

33

34

35 F535 AFCE

36 F537 AFCC

37 F539 ACC4CE

38 F53C 86FFF6CEF8

39 F541 ACCE00

40

41 F544 B5FAF9

42 F547 07

43 F548 B4FAC4

44

45 F54B ACCACC

46 F54E ACC8CE

47 F551 A20200A8

48 F555 ACC8CA

49 F558 AECE

0

.FORM, ’FADD.MAX’

.INCLD FADD.MAC

.TITLE FADD

.LOCAL

;

; SUBROUTINE TO ADD/SUBTRACT TWO SP FLOATING POINT NUMBERS.

; C

4 F1 0 F2 OR C 4 F1 1 F2

;

; F1 IS STORED IN THE IEEE FORMAT IN REGS K AND A.

; THE HIGH WORD OF F1 WILL BE REFERRED AS F1-R1 AND IS IN K.

; THE LOW WORD OF F1 WILL BE REFERRED TO AS F1-R0 AND IS IN A.

;

; F2 IS STORED IN THE IEEE FORMAT ON THE STACK. IF SP IS THE

; STACK POINTER ON ENTRY, THEN

; THE HIGH WORD OF F2, REFERRED TO AS F2-R1 IS AT SP – 4 AND

; THE LOW WORD OF F2, REFERRED TO AS F2-R0 IS AT SP - 6.

;

; C IS RETURNED IN THE IEEE FORMAT IN REGS K AND A.

;

FSUB:

ST A, TMP1

LD A, W(SP-06) ; LOAD F2-R0.

PUSH A ; AND SAVE ON STACK.

LD A, W(SP-06) ; LOAD F2-R1.

XOR A, 08000

PUSH A

LD A, TMP1

JSR FADD

ST A, TMP1

; CHANGE THE SIGN.

; AND SAVE ON THE STACK.

; RESTORE A.

; CALL THE ADD ROUTINE.

; SAVE A.

POP A

POP A

LD A, TMP1

RET

; GET RID OF JUNK

; FROM THE STACK.

; RESTORE A.

;

FADD:

; SAVE ADDRESS OF F2-R0 IN TMP1.

PUSH X ; SAVE X ON ENTRY.

; AND B ON ENTRY.

PUSH B

LD X, SP

ADD X, 0FFF6 ; SUBTRACT 10.

LD TMP1, X ; AND SAVE IN TMP1.

; CHECK AND SEE IF F1 IS A NAN.

JSR FNACHK

IF C

JMPL FNAN ; F1 IS A NAN.

; CHECK AND SEE IF F2 IS A NAN.

LD B, K

LD X, A

LD A, W(TMP1

02)

LD K, A

X A, X

34

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FADD

FADD.MAC

PAGE: 32

50 F55A B5FAE3

51 F55D 07

52 F55E B4FAAE

53

54 F561 B5FAED

55 F564 06

56 F565 48

57 F566 ACCCCA

58 F569 3FCC

59 F56B 3FCE

60 F56D 3C

61

62

63 F56E ACCCCA

64 F571 B5FADD

65 F574 06

66 F575 4F

67 F567 A20200AB

68 F57A ACC8CA

69 F57D AD00A8

70 F580 3FCC

71 F582 3FCE

72 F584 3C

73

74

75

76 F585 ACC4CE

77 F588 8210C4F8

78 F58C AFCE

79 F58E B5FAD0

80 F591 AC00CC

81 F594 ACCE00

82 F597 EO

83 F598 40

84 F599 AECA

85 F59B E4

86 F59C AECA

87 F59E B5FACO

88

89 F5A1 F2

90 F5A2 AC00CC

91 F5A5 E2

92 F5A6 40

93

94 F5A7 F2

95 F5A8 B9FF00

96 F5AB A6FFFCC4AB

97 F5B0 E2

98 F5B1 40

99 F5B2 B9FF00

100 F5B5 02

0

0

0

0

0

JSR FNACHK

IF C

JMPL FNAN ; F2 IS NAN.

; CHECK AND SEE IF F2 IS ZERO.

JSR FZCHK

IFN C

JP $F1CHK ; F2 IS NOT ZERO. CHECK F1.

; F2 IS ZERO, SO ANSWER IS F1.

LD K, B

POP B

POP X

RET

; CHECK AND SEE IF F1 IS ZERO.

$F1CHK:

LD K, B

JSR FZCHK

; RESTORE F1-R1 FROM B.

IFN C

JP $NTZERO ; JUMP SINCE F1 IS ALSO NOT ZERO.

LD A, W(TMP1

02) ; GET HERE MEANS F1 IS ZERO,

LD K, A ; SO ANSWER IS F2.

LD A, W(TMP1)

POP B

POP X

RET

; GET HERE MEANS NORMAL ADDITION.

; UNPACK F1 AND F2.

$NTZERO:

LD X, SP

ADD SP, 010

PUSH X

; X POINTS TO F1-LO.

; MOVE SP PAST LOCAL STORAGE.

; SAVE SP ON STACK FOR QUICK RETURN.

JSR FUNPAK

LD B, TMP1

LD TMP1, X

LDS A, W(B

0)

NOP

X A, K

LD A, W(B)

X A, K

; UNPACK F1.

; B NOW POINTS TO F2-RO.

; TMP1 NOW POINTS TO F2-LO.

; LOAD F2-RO INTO A.

; LOAD F2-R1 INTO K.

JSR FUNPAK ; UNPACK F2.

; SET X TO POINT TO F2-SIGN AND B TO POINT TO F1-SIGN.

LD A, W(X

1)

LD B, TMP1

LDS A, W(B

1)

NOP

LD A, W(X

1)

AND A, 0FF00

ST A, W(SP-4)

LDS A, W(B

1)

NOP

AND A, 0FF00

SET C

; LOAD F2-EXP.F2-SIGN INTO A.

; MASK OUT SIGN.

; SAVE IN C-SIGN.C-EXP.

; LOAD F1-EXP.F1-SIGN INTO A.

; CHANGE TO F1-EXP.00000000.

35

101 F5B6 A6FFFCC4EB

102 F5BB 06

103 F5BC 942D

104

105 F5BE 80C9CAAB

106 F5C2 A6FFFCC4FB

107 F5C7 A6FFFCC4AB

108 F5CC 8217CAFD

109 F5D0 51

110

111 F5D1 8200CAFC

112 F5D5 943B

113

114 F5D7 F4

115 F5D8 C7

116 F5D9 F3

117 F5DA F4

118 F5DB D7

119 F5DC F1

120 F5DD AACA

121 F5DF 68

122 F5E0 9430

123

124

125 F5E2 F0

126 F5E3 00

127 F5E4 F3

128 F5E5 00

129 F5E6 F3

130 F5E7 00

131 F5E8 F1

132 F5E9 9427

133

134

135 F5EB 01

136 F5EC 04

137 F5ED 80C9CAAB

138 F5F1 8217CAFD

139 F5F5 51

140

141 F5F6 8200CAFC

142 F5FA 57

143

144 F5FB E4

145 F5FC C7

146 F5FD E3

147 F5FE 40

148 F5FF E4

149 F600 D7

150 F601 E1

151 F602 40

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FADD

FADD.MAC

PAGE: 33

SUBC A, W(SP-4) ; SUBTRACT F2-EXP.00000000.

IFN C

JMP $F2GTR ; F2-EXP IS BIGGER THAN F1-EXP.

; GET HERE MEANS F1-EXP IS BIGGER THAN F2-EXP.

; SAVE DIFF. IN K TO BE USED AS LOOP COUNTER.

LD K, H(A)

ADD A, W(SP

14)

ST A, W(SP

14)

IFGT K, 017

JP $ZROF2

; RESTORE F1-EXP AND STORE IN C-SIGN.

; K GT 23-DEC MEANS F2 GETS ZEROED IN SHIFTS.

; LOOP TO SHIFT F2 INTO ALIGNMENT.

IFEQ K, 0

JMP $ADDMN ; K

4 0 MEANS DONE SHIFTING.

$LOOP2:

LD A, W(X)

SHR A

X A, W(X

1)

LD A, W(X)

RRC A

X A, W(X

0)

DECSZ K

JP $LOOP2

JMP $ADDMN

$ZROF2:

; SET F2 MANTISSA TO 0.

LD A, W(X

0)

CLR A

X A, W(X

1)

CLR A

X A, W(X

1)

CLR A

X A, W(X

0)

JMP $ADDMN

; X POINTS TO F2-EXP.F2-SIGN.

; AND STORE IT BACK.

; F2 EXPONENT IS GREATER THAN F1 EXPONENT.

$F26TR:

COMP A

INC A

LD K, H(A)

; CHANGE DIFF IN EXP TO POSITIVE.

; LOAD K WITH LOOP COUNTER.

IFGT K, 017

JP $ZROF1 ; F1 MANT. REDUCED TO 0 IN SHIFTS.

; LOOP TO SHIFT F1 MANT INTO ALIGNMENT.

IFEQ K, 0

JP $ADDMN ; K

40 MEANS DONE SHIFTING.

$LOOP1:

LD A, W(B)

SHR A

XS A, W(B

1)

NOP

LD A, W(B)

RRC A

XS A, W(B

0)

NOP

36

152 F603 AACA

153 F605 6A

154 F606 4B

155

156 F607 E0

157 F608 40

158 F609 00

159 F60A E3

160 F60B 40

161 F60C 00

162 F60D E3

163 F60E 40

164 F60F 00

165 F610 E1

166 F611 40

167

168

169 F612 E0

170 F613 40

171 F614 F0

172 F615 D4

173 F616 D8

174 F617 9C00

175 F619 9451

176

177 F61B F2

178 F61C F2

179 F61D E2

180 F61E 40

181 F61F E2

182 F620 40

183 F621 E0

184 F622 40

185 F623 02

186 F624 8FEB

187 F626 F1

188 F627 E0

189 F628 40

190 F629 8FEB

191 F62B F1

192 F62C 07

193 F62D 55

194

195 F62E A6FFFCC4A8

196 F633 8FDA

197 F635 F3

198 F636 F4

199 F637 D1

200 F638 F3

201 F639 F4

202 F63A 01

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FADD

FADD.MAC

PAGE: 34

DECSZ K

JP $LOOP1

JP $ADDMN

;

$ZROF1:

LOS A, W(B

0)

NOP

CLR A

XS A, W(B

1)

NOP

CLR A

XS A, W(B

1)

NOP

CLR A

XS A, W(B

0)

NOP

; SET F1 MANT TO 0.

; B POINTS TO F1-EXP.F1-SIGN.

; STORE IT BACK.

; DETERMINE IF MANTISSAS ARE TO BE ADDED OR SUBTRACTED.

$ADDMN: ; B POINTS TO F1-HI, X TO F2-HI.

LDS A, W(B

0)

NOP

LD A, W(X

0)

LD A, M(X) ; LOAD F2-SIGN.

XOR A, M(B) ; XOR WITH F1-SIGN.

IFEQ A, 0

JMP $TRADD ; SAME SIGN SO GO TO ADD MANTISSA.

; GET HERE MEANS TRUE SUBTRACT OF MANTISSA.

LD A, W(X

1)

LD A, W(X

1)

LDS A, W(B

1)

; X POINTS TO F2-LO.

NOP

LDS A, W(B

1)

; B NOW POINTS TO F1-LO.

NOP

LDS A, W(B

0)

NOP ; A NOW CONTAINS F1-LO.

SET C

SUBC A, W(X)

X A, W(X

0)

LDS A, W(B

0)

NOP

SUBC A, W(X)

X A, W(X

0)

IF C

JP $F1SIN

; SUBTRACT F2-LO.

; A CONTAINS F1-HI.

; SUBTRACT F2-HI.

; F1 GE F2, SO SIGN IS F1-SIGN.

; GET HERE MEANS F1 LT F2, SO SIGN IS F2-SIGN.

LD A, W(SP

14)

OR A, M(X)

X A, W(X

1)

LD A, W(X)

; C-EXP.C-SIGN HAS BEEN DETERMINED.

COMP A

X A, W(X

1)

LD A, W(X)

COMP A

37

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FADD

FADD.MAC

203 F63B B80001

204 F63E F1

205 F63F 07

206 F640 8FA9

207 F642 47

208

209

210 F643 A6FFFCC4A8

211 F648 DA

212 F649 F3

213

214

215 F64A ACCECC

216 F64D E0

217 F64E 40

218 F64F C0

219 F650 40

220 F651 9118

221

222 F653 F4

223 F654 E7

224 F655 07

225 F656 9448

226 F658 F3

227 F659 F4

228 F65A E7

229 F65B F1

230 F65C 07

231 F65D 8F08

232 F65F ADCC8A

233 F662 43

234 F663 B4F9B8

235

236 F666 AACA

237 F668 75

238 F669 B4F9B2

239

240

241 F66C E2

242 F66D 40

243 F66E E2

244 F66F 40

245 F670 F2

246 F671 F2

247 F672 F4

248 F673 F8

249 F674 F1

250 F675 E0

251 F676 40

252 F677 F4

253 F678 E8

PAGE: 35

ADD A, 01

X A, W(X

0)

IF C

INC W(X)

JP $ANORM

$F1SIN:

LD A, W(SP

14)

OR A, M(B)

X A, W(X

1)

; NORMALIZE THE MANTISSA.

$ANORM:

LD B, X

LDS A, W(B

0)

NOP

LDS A, M(B

0)

NOP

LD K, 018

; B POINTS TO C-HI.

; B NOW POINTS TO C-EXP BYTE.

; SET UP LOOP LIMIT OF 24-DEC IN K.

$NLOOP:

LD A, W(X)

SHL A

IF C ; CARRY MEANS NORMALIZED.

; SO JUMP TO ROUNDING CODE.

JMP $ROUND

X A, W(X

1)

LD A, W(X)

SHL A

X A, W(X

0)

IF C

SET W(X).0

DECSZ M(B)

JP $0V1

JMPL UNDFL

; ADJUST EXPONENT.

; C-EXP ZERO MEANS UNDERFLOW.

$OV1:

JMPL UNDFL ; UNDERFLOW

;GET HERE MEANS TRUE ADDITION OF MANTISSA.

$TRADD:

DECSZ K

JP $NLOOP

; DECREMENT LOOP COUNTER.

; GO BACK TO LOOP.

LDS A, W(B

1)

NOP

LDS A, W(B

1)

NOP

LD A, W(X

1)

LD A, W(X

1)

LD A, W(X)

ADD A, W(B)

X A, W(X

0)

LDS A, W(B

0)

NOP

LD A, W(X)

ADC A, W(B)

; B NOW POINTS TO F1-HI.

; LOAD F2-LO INTO A.

; ADD F1-LO.

; STORE IN F2-LO.

; B NOW POINTS TO F1-HI.

; LOAD F2-HI INTO A.

; ADD F1-HI WITH CARRY FROM L0 ADD.

38

254 F679 07

255 F67A 4A

256 F67B F1

257 F67C A6FFFCC4A8

258 F681 8FDA

259 F683 F3

260 F684 5B

261

262

263 F685 D7

264 F686 F3

265 F687 F4

266 F688 D7

267 F689 F1

268 F68A F0

269 F68B A6FFFCC4A8

270 F690 B80100

271 F693 07

272 F694 B4F998

273 F697 BDFEFF

274 F69A B4F992

275 F69D 8FDA

276 F69F F3

277

278

279 F6A0 B5F9FB

280

281 F6A3 D0

282 F6A4 D2

283 F6A5 9C00

284 F6A7 B4F974

285 F6AA 90FE

286 F6AC B4F980

287 F6AF F2

288 F6B0 F2

289 F6B1 B5F9C8

290 F6B4 3FC4

291 F6B6 3FCC

292 F6B8 3FCE

293 F6BA 3C

294

295

0

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FADD

FADD.MAC

PAGE: 36

IF C

JP $ADJEX

X A, W(X

0)

LD A, W(SP

14)

OR A, M(X)

K A, W(X

1)

JP $ROUND

; IF CARRY, NEED TO INCREASE EXP.

; STORE RESULT IN F2-HI.

; GET C-EXP.00000000.

; INTRODUCE SIGN.

; STORE IN F2-EXP.F2-SIGN.

; GET HERE MEANS NEED TO INCREASE EXP BY 1.

$ADJEX:

RRC A

X A, W(X

1)

LD A, W(X)

RRC A

X A, W(X

0)

LD A, W(X

0)

LD A, W(SP

14)

ADD A, 0100

IF C

; X NOW POINTS TO F2-EXP.F2-SIGN.

; GET C-EXP.00000000.

; INCREASE EXP BY 1.

; IS BIASED EXPONENT 255-DEC ?

JMPL OVRFL

OR A, M(X)

X A, W(X

1)

; NEED TO ROUND THE RESULT. X POINTS TO C-HI.

$ROUND:

JMPL OVRFL

IFGT A, OFEFF

JSRL SROUND

; FINAL CHECK OF EXPONENT.

LD A, M(X

0)

LD A, M(X

1)

; X NOW POINTS TO C-EXP.

IFEQ A, 0

JMPL UNDFL

IFGT A, OFE

JMPL OVRFL

LD A, W(X

1)

LD A, W(X

1)

JSR FPAK

POP SP

; X NOW POINTS TO C-LO.

; PACK C.

; SET UP SP FOR RETURN.

POP B

POP X

RET

;

.END

39

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FADD

FMULT.MAC

PAGE: 37

10

11

12

13

14

15

16

8

9

6

7

35

36

1

2

3

4

5

17

18

19

20 F6BB AFCE

21 F6BD AFCC

22

23 F6BF ACC4CE

24 F6C2 86FFF6CEF8

25 F6C7 ACCE00

26

27 F6CA B5F973

28 F6CD 07

29 F6CE B4F93E

30

31 F6D1 ACCACC

32 F6D4 ACC8CE

33 F6D7 A20200A8

34 F6DB ACC8CA

35 F6DE AECE

36 F6E0 B5F95D

37 F6E3 07

38 F6E4 B4F928

39

40 F6E7 B5F967

41 F6EA 07

42 F6EB 94DC

43

44 F6ED ACCCCA

45 F6FD B5F95E

46 F6F3 07

47 F6F4 94D3

48

49

0

0

0

0

.FORM ’FMULT.MAC’

.INCLD FMULT.MAC

.TITLE FMULT

.LOCAL

;

; SUBROUTINE TO MULTIPLY TWO SP FLOATING POINT NUMBERS.

; C

4 F1*F2

;

; F1 IS STORED IN THE IEEE FORMAT IN REGS K AND A.

; THE HIGH WORD OF F1 WILL BE REFERRED AS F1-R1 AND IS IN K.

; THE LOW WORD OF F1 WILL BE REFERRED TO AS F1-R0 AND IS IN A.

;

; F2 IS STORED IN THE IEEE FORMAT ON THE STACK. IF SP IS THE

; STACK POINTER ON ENTRY, THEN

; THE HIGH WORD OF F2, REFERRED TO AS F2-R1 IS AT SP - 4 AND

; THE LOW WORD OF F2, REFERRED TO AS F2-R0 IS AT SP - 6.

;

; C IS RETURNED IN THE IEEE FORMAT IN REGS K AND A.

; REGS. X AND B ARE PRESERVED.

;

FMULT:

PUSH X ; SAVE X ON ENTRY.

PUSH B ; SAVE B ON ENTRY.

; SAVE ADDRESS OF F2-RO IN TMP1.

LD X, SP

ADD X, 0FFF6 ; SUBTRACT 10.

LD TMP1, X ; SAVE IN TMP1.

; CHECK AND SEE IF F1 IS A NAN.

JSR FNACHK

IF C

JMPL FNAN ; F1 IS A NAN.

; CHECK AND SEE IF F2 IS A NAN.

LD B, K

LD X, A

LD A, W(TMP1

02)

LD K, A

X A, X

JSR FNACHK

IF C

JMPL FNAN ; F2 IS NAN.

; CHECK AND SEE IF F2 IS ZERO.

JSR FZCHK

IF C

JMP $CZERO ; F2 IS ZERO.

; CHECK AN SEE IF F1 IS ZERO.

LD K, B ; RESTORE F1-R1 FROM B.

JSR FZCHK

IF C

JMP $CZERO ; F1 IS ZERO.

; GET HERE MEANS NORMAL MULTIPLICATION.

; UNPACK F1 AND F2.

40

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FMULT

FMULT.MAC

50 F6F6 ACC4CE

51 F6F9 8210C4F8

52 F6FD AFCE

53 F6FF B5F95F

54 F702 AC00CC

55 F705 ACCE00

56 F708 E0

57 F709 40

58 F70A AECA

59 F70C E4

60 F70D AECA

61 F70F B5F94F

62

63 F712 F2

64 F713 AC00CC

65 F716 E2

66 F717 40

67

68 F718 F4

69 F719 C7

70 F71A ACC8CA

71 F71D E4

72 F71E B9FF00

73 F721 C7

74 F722 96CAF8

75 F725 F6

76 F726 E2

77 F727 40

78 F728 99FF

79 F72A C7

80 F72B 8FFB

81 F72D B8C080

82 F730 07

83 F731 46

84

85 F732 E7

86 F733 07

87 F734 B4F8E7

88 F737 C7

89

90

91 F738 E7

92 F739 07

93 F73A B4F8F2

94 F73D 96C817

95 F740 96C808

96 F743 F3

97

98

99

100 F744 F2

PAGE: 38

0

0

LD X, SP

ADD SP, 010

PUSH X

JSR FUNPAK

; X POINTS TO F1-LO.

; MOVE SP PAST LOCAL STORAGE.

; SAVE SP ON STACK FOR QUICK RETURN.

; UNPACK F1.

LD B, TMP1

LD TMP1, X

LOS A, W(B

0)

NOP

X A, K

LD A, W(B)

X A, K

; B NOW POINTS TO F2-R0.

; TMP1 NOW POINTS TO F2-LO.

; LOAD F2-RO INTO A.

; LOAD F2-R1 INTO K.

JSR FUNPAK ; UNPAK F2.

; SET X TO POINT TO F2-SIGN AND B TO POINT TO F1-SIGN.

LD A, W(X

1)

LD B, TMP1

LDS A, W(B

1)

NOP

; COMPUTE C-EXP AND C-SIGN AND STORE IN F2-EXP AND F2-SIGN.

LD A, W(X)

SHR A

LD K, A

LD A, W(B)

AND A, 0FF00

SHR A

ADD A, K

ST A, W(X)

LOS A, W(B

1)

NOP

AND A, OFF

; A IS (EEEEEEEE-F2).(SSSSSSSS-F2)

; SHR SINCE SUM OF EXPS CAN BE 9 BITS.

; K IS (DEEEEEEEE-F2).(SSSSSSS-F2)

; A IS (EEEEEEEE-F1).(SSSSSSSS-F1)

; MASK OUT SIGN BITS.

; A IS (DEEEEEEEE-F1).(0000000)

; A IS (EEEEEEEEE-C).(SSSSSSS-F2)

; STORE IN F2-SIGN.

; A IS (EEEEEEEE-F1).(SSSSSSSS-F1)

SHR A

XOR A, W(X)

ADD A, 0C080

IF C

; MASK OUT EXP BITS.

; A IS (000000000SSSSSSS-F1)

; A IS (EEEEEEEEESSSSSSS-C)

; REMOVE EXCESS BIAS OF 127-DEC FROM EXP.

JP $EXCH2 ; IF CARRY, THEN NO UNDERFLOW NOW

; CHECK TO SEE IF EXP IS ZERO. IF NOT, UNDERFLOW FOR SURE.

SHL A

IF C

JMPL UNDFL

SHR A

; UNDERFLOW, SO JUMP.

; RESTORE BIT SHIFTED OUT (0).

; CHECK FOR EXPONENT OVERFLOW.

$EXCH2:

SHL A

IF C

JMPL OVRFL

; IF C IS 1,

; THEN OVERFLOW FOR SURE.

IF A.7

SET A.0

X A, W(X

1)

; RESTORE LAST BIT OF SIGN.

; STORE C-EXP. C-SIGN IN F2-EXP.F2-SIGN.

;

; MULTIPLY THE MANTISSA.

; FIRST COMPUTE F1-HI

*F2-HI.

LD A, W(X

1)

41

101 F745 ACCE00

102 F748 FE

103 F749 A6FFFAC4AB

104 F74E AECE

105 F750 A6FFFCC4AB

106

107 F755 AC00CE

108 F758 F0

109 F759 ACCE00

110 F75C FE

111 F75D AECE

112 F75F A6FFFAC4F8

113 F764 A6FFFAC4AB

114 F769 07

115 F76A A6FFFCC4A9

116

117 F76F E2

118 F770 40

119 F771 AC00CE

120 F774 F4

121 F775 FE

122 F776 AECE

123 F778 A6FFFAC4F8

124 F77D A6FFFAC4AB

125 F782 A6FFFCC4AB

126 F787 07

127 F788 04

128

129

130 F789 AC00CE

131 F78C BD7FFF

132 F78F 4D

133

134 F790 E7

135 F791 F3

136 F792 A6FFFAC4AB

137 F797 E7

138 F798 F1

139 F799 07

140 F79A 8F08

141 F79C 51

142

143

144 F79D F3

145 F79E A6FFFAC4A8

146 F7A3 F1

147 F7A4 F0

148 F7A5 F4

149 F7A6 B80100

150 F7A9 07

151 F7AA B4F882

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FMULT

FMULT.MAC

PAGE: 39

LD TMP1, X ; TMP1 NOW POINTS TO F2-LO.

MULT A, W(B)

ST A, W(SP

16)

X A, X

ST A, W(SP

14)

; STORE LOW WORD OF PRODUCT ON STACK.

; STORE HIGH WORD OF PRODUCT ON STACK.

; NOW COMPUTE F1-HI *F2-LO.

LD X, TMP1

LD A, W(X

0)

LD TMP1, X ; TMP1 NOW POINTS TO F2-HI.

MULT A, W(B)

X A, X

ADD A, W(SP

16) ; ADD LOW WORD OF LAST PROD. TO HIGH WORD.

ST A, W(SP

16)

IF C

INC W(SP

14)

; IF CARRY, INCREASE HIGH WORD BY 1.

; FINALLY COMPUTE F1-LO

*F2-HI.

LDS A, W(B

1)

; ADJUST B TO POINT TO F1-LO.

NOP

LD X, TMP1

LD A, W(X)

MULT A, W(B)

X A, X

ADD A, W(SP

16) ; ADD LOW WORD ACCUMULATED SO FAR.

ST A, W(SP

16)

LD A, W(SP

14)

; A CONTAINS HIGH WORD OF PRODUCT.

IF C ; IF CARRY ON LAST LOW WORD ADD,

INC A ; THEN INCREASE HIGH WORD.

;

; MANTISSA MULTIPLICATION DONE. NOW CHECK FOR NORMALIZATION.

LD X, TMP1

IFGT A, 07FFF

JP $EXINC

; IS MSB OF PRODUCT 1 ?

; YES, INCREASE MANTISSA.

; NEED TO SHIFT MANTISSA LEFT BY 1 BIT.

SHL A

X A, W(X

1)

LD A, W(SP

16)

SHL A

X A, W(X

0)

IF C

SET W(X).0

; DID SHIFT OF LOW WORD PUSH OUT A 1 ?

; YES SO SET LSB OF HIGH WORD.

JP $ROUND ; GO TO ROUNDING CODE.

$EXINC:

; NEED TO INCREASE EXPONENT BY 1. REMEMBER X POINTS TO F2-HI.

X A, W(X

1)

LD A, W(SP

16)

X A, W(X

0)

LD A, W(X

0)

; A CONTAINS HIGH WORD, X POINTS TO F2-LO.

; GET LOW WORD.

; STORE LOW WORD.

LD A, W(X) ; GET C-EXP.C-SIGN

; INCREASE C-EXP.

ADD A, 0100

IF C

JMPL OVRFL ; EXPONENT OVERFLOW.

42

152 F7AD F3

153

154

155 F7AE B5F8ED

156

157 F7B1 D0

158 F7B2 D2

159 F7B3 9C00

160 F7B5 B4F866

161 F7B8 9DFE

162 F7BA B4F872

163 F7BD F2

164 F7BE F2

165 F7BF B5F8BA

166 F7C2 3FC4

167 F7C4 3FCC

168 F7C6 3FCE

169 F7C8 3C

170

171

172

173 F7C9 00

174 F7CA ACC8CA

175 F7CD 3FCC

176 F7CF 3FCE

177 F7D1 3C

178

179

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FMULT

FMULT.MAC

0

PAGE: 40

X A, W(X

1)

; ROUNDING CODE.

$ROUND:

JSRL SROUND

; NO OVERFLOW, SO SAVE C-EXP.C-SIGN.

; FINAL CHECK OF EXPONENT.

LD A, M(X

0)

LD A, M(X

1)

; X NOW POINTS TO C-EXP.

IFEQ A, 0

JMPL UNDFL

IFGT A, OFE

JMPL OVRFL

LD A, W(X

1)

LD A, W(X

1)

JSR FPAK

POP SP

; X NOW POINTS TO C-LO.

; PACK C.

; SET UP SP FOR RETURN.

POP B

POP X

RET

; EXCEPTION HANDLING.

; C IS ZERO B’COS ONE OF F1 OR F2 IS ZERO.

$CZERO:

CLR A

LD K, A

POP B

POP X

RET

;

.END

43

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FMULT

FDIV.MAC

PAGE: 41

10

11

12

13

14

15

16

8

9

6

7

37

38

1

2

3

4

5

17

18

19 F7D2 AFCE

20 F7D4 AFCC

21

22 F7D6 ACC4CE

23 F7D9 86FFF6CEF8

24 F7DE ACCE00

25

26 F7E1 85F85C

27 F7E4 07

28 F7E5 B4F827

29

30 F7E8 ACCACC

31 F7EB ACC8CE

32 F7EE A20200A8

33 F7F2 ACC8CA

34 F7F5 AECE

35 F7F7 B5F846

36 F7FA 07

37 F7FB B4F811

38

39 F7FE B5F850

40 F801 07

41 F802 B4F7FB

42

43 F805 ACCCCA

44 F808 B5F846

45 F80B 07

46 F80C 94F1

47

48

49 F80E ACC4CE

0

0

0

0

.FORM ’FDIV.MAC’

.INCLD FDIV.MAC

.TITLE FDIV

.LOCAL

;

; SUBROUTINE TO DIVIDE TWO SP FLOATING POINT NUMBERS.

; C

4 F1/F2

;

; F1 IS STORED IN THE IEEE FORMAT IN REGS K AND A.

; THE HIGH WORD OF F1 WILL BE REFERRED AS F1-R1 AND IS IN K.

; THE LOW WORD OF F1 WILL BE REFERRED TO AS F1-RO AND IS IN A.

;

; F2 IS STORED IN THE IEEE FORMAT ON THE STACK. IF SP IS THE

; STACK POINTER ON ENTRY, THEN

; THE HIGH WORD OF F2, REFERRED TO AS F2-R1 IS AT SP - 4 AND

; THE LOW WORD OF F2, REFERRED TO AS F2-RO IS AT SP - 6.

;

; C IS RETURNED IN THE IEEE FORMAT IN REGS K AND A.

;

FDIV:

PUSH X

PUSH B

; SAVE ADDRESS OF F2-RO IN TMP1.

LD X, SP

ADD X, 0FFF6

LD TMP1, X

; SUBTRACT 10.

; AND SAVE IN TMP1.

; CHECK AND SEE IF F1 IS A NAN.

JSR FNACHK

IF C

JMPL FNAN ; F1 IS A NAN.

; CHECK AND SEE IF F2 IS A NAN.

LD B, K

LD X, A

LD A, W(TMP1

02)

LD K, A

X A. X

JSR FNACHK

IF C

JMPL FNAN ; F2 IS NAN.

; CHECK AND SEE IF F2 IS ZERO.

JSR FZCHK

IF C

JMPL DIVBYO ; F2 IS ZERO.

; CHECK AND SEE IF F1 IS ZERO.

LD K, B

JSR FZCHK

; RESTORE F1-R1 FROM B.

IF C

JMP $CZERO ; F1 IS ZERO.

; GET HERE MEANS NORMAL DIVISION.

; UNPACK F1 AND F2.

LD X, SP ; X POINTS TO F1-LO.

44

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FDIV

FDIV.MAC

77 F839 E0

78 F83A 40

79 F83B AECA

80 F83D B80100

81 F840 E3

82 F841 40

83 F842 E4

84 F843 C7

85 F844 E3

86 F845 40

87 F846 E4

88 F847 D7

89 F848 E1

90 F849 40

91

92

93

94 F84A F0

95 F84B E0

96 F84C 40

97 F84D F4

98 F84E B9FF00

99 F851 C7

100 F852 ACC8CA

50 F811 8210C4F8

51 F815 AFCE

52 F817 B5F847

53 F81A AC00CC

54 F81D ACCE00

55 F820 EO

56 F821 40

57 F822 AECA

58 F824 E4

59 F825 AECA

60 F827 B5F837

61

62

63

64 F82A F2

65 F82B F2

66 F82C AC00CC

67 F82F E2

68 F830 40

69 F831 E2

70 F832 40

71 F833 ACC8CA

72 F836 F4

73 F837 FD

74 F838 51

75

76

PAGE: 42

0

0

ADD SP, 010

PUSH X

JSR FUNPAK

LD B, TMP1

LD TMP1, X

LDS A, W(B

0)

NOP

; MOVE SP PAST LOCAL STORAGE.

; SAVE SP ON STACK FOR QUICK RETURN.

; UNPACK F1.

; B NOW POINTS TO F2-RO

; TMP1 NOW POINTS TO F2-LO.

; LOAD F2-RO INTO A.

X A, K

LD A, W(B)

X A, K

JSR FUNPAK

;

; ENSURE THAT F1-HI IS LESS THAN F2-HI.

;

; LOAD F2-R1 INTO K.

; UNPAK F2.

LD A, W(X

1)

LD A, W(X

1)

LD B, TMP1

LDS A, W(B

1)

NOP

LDS A, W(B

1)

NOP

LD K, A

; X POINTS TO F2-EXP.F2-SIGN.

; X POINTS TO F2-HI.

; B POINTS TO F2-LO.

; B POINTS TO F1-EXP.F1-SIGN.

; LOAD F1-EXP.F1-SIGN.

; B POINTS TO F1-HI.

; SAVE F1-EXP.F1-SIGN IN K.

LD A, W(X)

IFGT A, W(B)

JP $FEXSN

; LOAD F2-HI.

; IS F2-HI l

FI-HI ?

; YES, SO ALL IS WELL.

; GET HERE MEANS NEED TO SHR F1,

; AND INCREASE ITS EXPONENT.

LOS A, W(B

0)

NOP

X A, K

ADD A, 0100

XS A, W(B

1)

NOP

; GET FI-HI.

; B POINTS TO F1-EXP.F1-SIGN.

; SWAP F1-EXP.F1-SIGN AND F1-HI.

; INCREASE F1-EXP BY 1.

; STORE BACK IN F1-EXP.F1-SIGN.

; B POINTS TO F1-HI.

; LOAD F1-HI.

LD A, W(B)

SHR A

XS A, W(B

1)

NOP

LD A, W(B)

RRC A

XS A, W(B

0)

NOP

; STORE BACK IN F1-HI.

; B POINTS TO F1-LO.

; LOAD F1-LO.

; PUT IT BACK IN F1-LO.

; B POINTS TO F1-HI.

;

$FEXSN:

; DETERMINE C-EXP AND C-SIGN.

LD A, W(X

0)

LDS A, W(B

0)

; X POINTS TO F2-EXP.F2-SIGN.

; B POINTS TO F1-EXP.F1-SIGN.

NOP

LD A, W(X)

AND A, 0FF00

; LOAD F2-EXP.F2-SIGN.

; MASK OUT THE SIGN.

SHR A

LD K, A

; ALLOW 9 BITS FOR EXP CALCULATIONS.

; SAVE IT IN K.

45

101 F855 E4

102 F856 B9FF00

103 F859 C7

104 F85A 02

105 F85B 96CAEB

106

107

108 F85E B7000000

109 F862 E7

110 F863 07

111 F864 B700FF00

112 F868 D7

113 F869 B83F00

114 F86C E7

115 F86D 06

116 F86E 49

117 F86F 960010

118 F872 B4F7A9

119 F875 B4F7B7

120

121

122

123

124 F878 BCFF00

125 F87B B4F7B1

126 F87E 9C00

127 F880 B4F79B

128 F883 AB00

129 F885 F4

130 F886 99FF

131 F888 FB

132 F889 99FF

133 F88B 9600FA

134 F88E F3

135

136 F88F F2

137 F890 E2

138 F891 40

139

140

141

142 F892 F0

143 F893 ACCE00

144 F896 FE

145

146

147 F897 AECC

148 F899 AE00

149 F89B AECC

150

151 F890 EF

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FDIV

FDIV.MAC

PAGE: 43

LD A, W(B)

AND A, 0FF00

SHR A

SET C

SUBC A, K

; LOAD F1-EXP.F1-SIGN.

; MASK OUT SIGN.

; SUBTRACT THE EXPONENTS.

; NOTE THAT NOW THE MS 9 BITS

; OF A CONTAIN A 2’S COMP. INTEGER.

LD TMP1, 0

SHL A

IF C

LD TMP1, OFF

RRC A

ADD A, 03F00

SHL A

IFN C

JP $FSIGN

IF TMP1.0

JMPL UNDFL

; SAVE SIGN OF NUMBER IN TMP1.

; RESTORE IEEE BIAS.

; MAKE EXPONENT 8 BITS.

; NO CARRY ?

; THEN ALL IS WELL.

; WAS EXP NEGATIVE BEFORE ?

; YES, SO UNDERFLOW.

JMPL OVRFL ; OTHERWISE OVERFLOW.

;

$FSIGN:

; C-EXP HAS BEEN COMPUTED. NOW FIND C-SIGN.

; BUT FIRST TAKE CARE OF SPECIAL OVER/UNDERFLOW CASES.

IFEQ A, 0FF00

JMPL OVRFL

IFEQ A, 0

JMPL UNDFL

ST A, TMP1

LD A, W(X)

AND A, OFF

XOR A, W(B)

; SAVE C-EXP.00000000 IN TMP1.

; LOAD F2-EXP.F2-SIGN.

; MASK OUT F2-EXP.

; A NOW HAS F1-EXP.C-SIGN.

AND A, OFF

OR A, TMP1

X A, W(X

1)

; MASK OUT F1-EXP.

; BRING IN C-EXP.

; STORE IN F2-EXP.F2-SIGN.

; X POINTS TO F2-HI.

LD A, W(X

1)

LDS A, W(B

1)

NOP

; X POINTS TO F2-LO.

; B POINTS TO F1-HI.

;

; NOW DO THE MANTISSA DIVISION.

;

LD A, W(X

0)

LD TMP1, X

MULT A, W(B)

; LOAD F2-LO. X POINTS TO F2-HI.

; SAVE ADDRESS OF F2-HI IN TMP1.

; COMPUTE F2-LO *F1-HI.

; X CONTAINS MS WORD AND A IS LS WORD.

;

X A, B

X A, TMP1

X A, B

; A POINTS TO F1-HI, B CONTAINS LS WORD.

; A POINTS TO F2-HI, TMP1 POINTS TO F1-HI.

; A CONTAINS LS WORD, B POINTS TO F2-HI.

;

.BYTE OEF ; DIVD A, W(B) - KLUDGED !!

46

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FDIV

FDIV.MAC

152

153 F89E ACC8CA

154 F8A1 A8CC

155 F8A3 AE00

156 F8A5 AECC

157 F8A7 E2

158 F8A8 40

159 F8A9 E0

160 F8AA 40

161 F8AB 02

162 F8AC 96CAEB

163 F8AF ACC8CE

164 F8B2 E4

165 F8B3 06

166 F8B4 05

167 F8B5 AECE

168 F8B7 AC00CC

169

170 F8BA EF

171

172

173 F8BB AB00

174 F8BD 00

175

176 F8BE EF

177

178 F8BF AE00

179

180

181 F8C1 E7

182 F8C2 07

183 F8C3 56

184

185 F8C4 AE00

186 F8C6 E7

187 F8C7 AE00

188 F8C9 07

189 F8CA 96C808

190 F8CD ABCA

191 F8CF E1

192 F8D0 40

193 F8D1 E4

194 F8D2 B8FF00

195 F8D5 E3

196 F8D6 40

197 F8D7 A8CA

198 F8D9 E7

199

200 F8DA D7

201 F8DB E3

202 F8DC 40

PAGE: 44

;

LD K, A

LD A, B

X A, TMP1

X A, B

LDS A, W(B

1)

NOP

LOS A, W(B

0)

NOP

SET C

SUBC A, K

LD X, A

LD A, W(B)

IFN C

DEC A

X A, X

LD B, TMP1

; SAVE QUOTIENT IN K.

; A POINTS TO F2-HI.

; A POINTS TO F1-HI, TMP1 POINTS TO F2-HI.

; B POINTS TO F1-HI.

; B POINTS TO F1-LO.

; LOAD F1-LO.

; B POINTS TO F1-HI.

; SUBTRACT QUOTIENT SAVED IN K.

; AND SAVE IN X.

; LOAD F1-HI.

; IF C WAS NOT SET IN THE LAST SUBTRACT,

; ADJUST THE BORROW.

; B POINTS TO F2-HI.

;

.BYTE OEF

;

;

.BYTE OEF ; DIVD A, W(B) - KLUDGED YET AGAIN !

;

X A, TMP1 ; SWAP OLD AND NEW QUOTIENTS.

;

; CHECK FOR NORMALIZATION. CAN BE OFF BY AT MOST 1 BIT.

SHL A

IF C

JP $NMED ; IT IS NORMALIZED.

; GET HERE MEANS NEED TO SHIFT LEFT ONCE.

; SWAP HI AND LO WORDS.

X A, TMP1

SHL A

X A, TMP1

IF C

SET A.0

ST A, K

XS A, W(B

0)

NOP

LD A, W(B)

ADD A, 0FF00

XS A, W(B

1)

NOP

LD A, K

SHL A

; HI WORD IS IN A, LO WORD IN TMP1.

; WAS 1 SHIFTED OUT OF LO WORD?

; YES, THEN SET LSB OF HI WORD.

; SAVE HI WORD IN K.

; B POINTS TO F2-EXP.F2-SIGN.

; LOAD F2-EXP.F2-SIGN.

; SUBTRACT 1 FROM EXPONENT.

; STORE BACK IN F2-EXP.F2-SIGN.

; B POINTS TO F2-HI.

; HI WORD TO A.

$NMED:

ST A, TMP1

CLR A

; SAVE QUOTIENT IN TMP1.

; ZERO A.

RRC A

XS A, W(B

1)

NOP

; DIVD A, W(B) - KLUDGED AGAIN !

; QUOTIENT IN A, REM IN X.

; RESTORE BIT OUT.

; SAVE HI-WORD IN F2-HI.

; B POINTS TO F2-LO.

47

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FDIV

FDIV.MAC

203 F8DD A800

204 F8DF E1

205 F8E0 40

206 F8E1 ACCCCE

207

208

209 F8E4 B5F7B7

210

211 F8E7 DO

212 F8E8 D2

213 F8E9 9C00

214 F8EB B4F730

215 F8EE 9DFE

216 F8F0 B4F73C

217 F8F3 F2

218 F8F4 F2

219 F8F5 B5F784

220 F8F8 3FC4

221 F8FA 3FCC

222 F8FC 3FCE

223 F8FE 3C

224

225

226 F8FF 00

227 F900 ACC8CA

228 F903 3FCC

229 F905 3FCE

230 F907 3C

231

232

0

PAGE: 45

LD A, TMP1

XS A, W(B

0)

NOP

LD X, B

;

; ROUNDING CODE.

JSRL SROUND

; SAVE C-LO.

; B POINTS TO F2-HI.

; MOVE ADDRESS OF F2-HI TO X.

; FINAL CHECK OF EXPONENT.

LD A, M(X

0)

LD A, M(X

1)

; X NOW POINTS TO C-EXP.

IFEQ A, O

JMPL UNDFL

IFGT A, OFE

JMPL OVRFL

LD A, W(X

1)

LD A, W(X

1)

JSR FPAK

POP SP

; X NOW POINTS TO C-LO.

; PACK C.

; SET UP SP FOR RETURN.

RET

; C IS ZERO B’COS F1 IS ZERO.

$CZERO:

POP B

POP X

CLR A

LD K, A

POP B

POP X

RET

;

.END

48

39

40

1

2

3

4

5

8

9

6

7

10

11 F908 AFCE

12 F90A AFC8

13 F90C AFCA

14 F90E 3653

15 F910 AFC8

16 F912 AFCA

17 F914 B6F994A8

18 F918 A4F996CAAB

19 F91D 3662

20 F91F AFC8

21 F921 AFCA

22 F923 B6F998A8

23 F927 A4F99ACAAB

24 F92C B5FBE6

25 F92F 3FCE

26 F931 3FCE

27 F933 3678

28

29 F935 AFC8

30 F937 AFCA

31 F939 B6F99CA8

32 F93D A4F99ECAAB

33 F942 B5FBD0

34

35 F945 3FCE

36 F947 3FCE

37 F949 368E

38

39 F94B AFC8

40 F94D AFCA

41 F94F B6F9A0A8

42 F953 A4F9A2CAAB

43 F958 B5FBBA

44

45 F95B 3FCE

46 F95D 3FCE

47 F95F 36A4

48

49 F961 AFC8

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

FDIV

FSINX.MAC

PAGE: 46

.FORM ’FSINX.MAC’

.INCLD FSINX.MAC

;

.TITLE SINX

.LOCAL

; A VERY DIRTY APPROXIMATION TO SIN(X).

; X SHOULD BE IN RADIANS.

;

; ON INPUT X SHOULD BE IN IEEE FLP FORMAT IN REGS. K AND A.

; ON RETURN SIN(X) IS IN IEEE FLP FORMAT IN REGS. K AND A.

;

SINX:

PUSH X ; SAVE X.

1

1

1

1

1

PUSH A

PUSH K ; X TO THE STACK.

JSRL FMULT

PUSH A

JSRL FMULT

PUSH A

; COMPUTE X>2.

PUSH K ; X>2 TO THE STACK.

LD A, W($A5LO)

LD K, W($A5HI) ; LOAD A5.

; COMPUTE A5

*X>2.

PUSH K

LD A, W($A4LO)

LD K, W($A4HI) ; LOAD A4.

JSRL FSUB ; COMPUTE A4-A5 *X>2.

POP X

POP X

JSRL FMULT ; COMPUTE

; X>2(A4 1 A5*X>2).

PUSH A

PUSH K

LD A, W($A3LO)

LD K, W($A3HI) ; LOAD A3.

JSRL FSUB ; COMPUTE

; A3 - X>2(A4 - A5*X>2).

POP X

POP X

JSRL FMULT ; COMPUTE

; X>2(A3 - X>2(A4 - A5*X>2)).

PUSH A

PUSH K

LD A, W($A2LO)

LD K, W($A2HI) ; LOAD A2.

JSRL FSUB ; COMPUTE

; A2 - X>2(A3 - X>2(A4 - A5*X>2)).

POP X

POP X

JSRL FMULT ; COMPUTE

; X>2(A2 - X>2(A3 - X>2(A4 - A5*X>2))).

PUSH A

49

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

SINX

FSINX.MAC

50 F963 AFCA

51 F965 B6F9A4AB

52 F969 A4F9A6CAAB

53 F96E B5FBA4

54

55 F971 3FCE

56 F973 3FCE

57 F975 36BA

58

59 F977 AFC8

60 F979 AFCA

61 F97B B13F80

62 F97E 00

63 F97F B5FB93

64

65 F982 3FCE

66 F984 3FCE

67 F986 3FCE

68 F988 3FCE

69 F98A 36CF

70

71 F98C 3FCE

72 F98E 3FCE

73 F990 3FCE

74 F992 3C

75

76 F993 40

77

78 F994 2B32

79 F996 D732

80 F998 1DEF

81 F99A 3836

82 F99C 010D

83 F99E 5039

84 F9A0 8988

85 F9A2 083C

86 F9A4 ADAA

87 F9A6 2A3E

88

89

90

91

92 F9A8 AFCE

93 F9AA ACC8CE

94 F9AD B6F9C8A8

95 F9B1 AFC8

96 F9B3 B6F9CAA8

97 F9B7 AFC8

98 F9B9 A8CE

99 F9BB B5FB77

100 F9BE 3FCE

PAGE: 47

1

1

PUSH K

LD A, W($A1LO)

LD K, W($A1HI) ; LOAD A1.

JSRL FSUB ; COMPUTE

; A1 - X>2(A2 - X>2(A3 - X>2(A4 - A5*X>2))).

POP X

POP X

JSRL FMULT ; COMPUTE

; X>2(A1 - X>2(A2 - X>2(A3 1 X>2(A4 - A5*X>2)))).

PUSH A

PUSH K

LD K, 03F80

CLR A

JSRL FSUB

; LOAD 1.0 INTO K-A.

; COMPUTE

; 1 - ALL THE JUNK ABOVE.

POP X

POP X

POP X

POP X

JSRL FMULT

; NOW X IS AT THE TOP OF STACK.

; COMPUTE

; X(1 - X>2(A1 - X>2(A2 - X>2(A3 - X>2(A4 - A5*X>2))))).

POP X

POP X

POP X

RET

;

.EVEN

;

$A5LO: .WORD 0322B

$A5HI: .WORD 032D7

$A4LO: .WORD 0EF1D

$A4HI: .WORD 03638

$A3LO: .WORD 00D01

$A3HI: .WORD 03950

$A2LO: .WORD 08889

$A2HI: .WORD 03C08

$A1LO: .WORD OAAAD

$A1HI: .WORD 03E2A

;

; A DIRTY APPROXIMATION TO COS(X) USING SIN(X).

;

COSX:

PUSH X

LD X, A

LD A, W($PI2LO)

PUSH A

LD A, W($PI2HI)

PUSH A

LD A, X

JSRL FADD

POP X

; COMPUTE X

0 PI/2.

50

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

SINX

FSINX.MAC

101 F9C0 3FCE

102 F9C2 34BA

103 F9C4 3FCE

104 F9C6 3C

105

106 F9C7 40

107 F9C8 DBOF

108 F9CA C93F

109

110

111

112

113 F9CC AFCE

114 F9CE AFCC

115 F9D0 AFC8

116 F9D2 AFCA

117 F9D4 342C

118 F9D6 ACC8CE

119 F9D9 ACCACC

120 F9DC 3FCA

121 F9DE 3FC8

122 F9EO AFCE

123 F9E2 AFCC

124 F9E4 34DC

125 F9E6 3614

126 F9E8 3FCC

127 F9EA 3FCC

128 F9EC 3FCC

129 F9EE 3FCE

130 F9F0 3C

131

132

41

42

43 FFFE 00F0

PAGE: 48

;

;

1

POP X

JSRL SINX

POP X

RET

;

.EVEN

$PI2LO: .WORD 00FDB

; COMPUTE SIN(X

0PI/2).

$PI2HI: .WORD 03FC9

;

; A DIRTY APPROXIMATION TO TAN(X) USING SINX AND COSX.

;

TANX:

PUSH X

PUSH B

PUSH A

PUSH K

JSR COSX

LD X, A

; COMPUTE COS(X)

LD B, K

POP K

POP A

PUSH X

PUSH B

JSR SINX

JSR FDIV

POP B

POP B

POP B

POP X

RET

; COMPUTE SIN(X).

; COMPUTE TAN(X)

4 SIN(X)/COS(X).

;

.END

.END LISTER

51

A

COSX

00C8 W

F9A8

FMULT F6BB

FPERWD 0002 W

FUNPAK F061

LISTER F000

SINX F908

TMP1 0000 W

$A1HI F9A6

$A3HI F99E

$A5HI F996

$ADDEX F1FF

$ANORM F64A

$CSIGN F349

$DIV10 F370

$DTLO F26E

$EXACC F1C9

$EXCOL F1BA

$EXIT F0C6

$TEXSN F84A

$GOON F42B

$INDUN F445

$ISNED F3BE

$JAMIT F280

$LOOP1 F147

$MLOG2 F33F

$MTLO F26A

$NAN F4CF

$NMED F8DA

$NRLUP F237

$OVR1 F3C1

$RNDUP F0A7

$VDOWN F418

$ZROF1 F607

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

SINX

SYMBOL TABLE

ATOF F13A

*

DIVBY0 F000

FNACHK F040

FPTRAP F09D

FZCHK F051

MUL10 F118

SP 00C4 W

UNDFL F01E

$A1LO F9A4

$A3LO F99C

$A5LO F994

$ADDMN F612

$ANOTO F05C

$CZERO F7C9

$DOLUP F481

$DTLO F390

$EXCH2 F738

$EXCPT F2CF

$F1CHK F56E

$FRCOL F18B

$HIUP F0AF

$INTFY F43C

$ISNXT F17D

$JAMIT F3A6

$LOOP1 F5FB

$MSIGN F154

$MTLO F394

$NANLP F4DC

$NORM1 F230

$NTZER F585

$PI2HI F9CA

$ROUND F6AO

$VUP F416

$ZROF2 F5E2

PAGE:

B

FADD

FNAN

FSUB

00CC W

F535

F00F

F515

ISIOK F105

OVRFL F02F

SROUND F09E

X 00CE W

$A2HI F9A2

$A4HI F99A

$ACCF F1A9

$ADEM F3EC

$CHKOT F113

$CZERO F8FF

$DTHI F270

$ESAVE F20F

$EXCHR F1BB

$EXIN2 FOB7

$F1SIN F643

$FSIGN F878

$INCOL F15C

$ISNAN F04C

$JAMDN F29E

$JAMLP F287

$LOOP2 F5D7

$MTHI F26C

$MUL10 F398

$NEG10 F20B

$NORM2 F235

$0V1 F666

$PI2LO F9C8

$ROUND F7AE

$ZERLP F505

49

BFMUL F0C7

FDIV F7D2

FPAK

FTOA

K

PC

F07C

F311 *

00CA W

00C6 W

TANX F9CC *

$A10EX F1F4

$A2LO F9A0

$A4LO F998

$ACCM F177

$ADJEX F685

$CHNGS F361

$DIV10 F272

$DTHI F392

$ESIGN F1C7

$EXCLP F1D4

$EXINC F79D

$F2GTR F5EB

$GOBAK F41F

$INCRV F40C

$ISNED F298

$JAMDN F3C4

$JAMLP F3AD

$ML4 F3EA

$MTHI F396

$NAGAS F2C3

$NLOOP F653

$NRDUN F247

$OVR1 F29B

$REMV9 F354

$TRADD F66C

$ZERO F4E9

52

NATIONAL SEMICONDUCTOR CORPORATION

HPC CROSS ASSEMBLER,REV:C,30 JUL 86

SINX

MACRO TABLE

NO WARNING LINES

NO ERROR LINES

2547 ROM BYTES USED

SOURCE CHECKSUM

4 A31F

OBJECT CHECKSUM

4 2AC3

INPUT FILE C:LISTER.MAC

LISTING FILE C:LISTER.PRN

OBJECT FILE C:LISTER.LM

PAGE: 50

53

Lit.

Ý

100486

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

National Semiconductor

Corporation

1111 West Bardin Road

Arlington, TX 76017

Tel: 1(800) 272-9959

Fax: 1(800) 737-7018

National Semiconductor

Europe

Fax: (a49) 0-180-530 85 86

Email: cnjwge @ tevm2.nsc.com

Deutsch Tel: (a49) 0-180-530 85 85

English Tel: (a49) 0-180-532 78 32

Fran 3ais Tel: (a49) 0-180-532 93 58

Italiano Tel: (a49) 0-180-534 16 80

National Semiconductor

Hong Kong Ltd.

13th Floor, Straight Block,

Ocean Centre, 5 Canton Rd.

Tsimshatsui, Kowloon

Hong Kong

Tel: (852) 2737-1600

Fax: (852) 2736-9960

National Semiconductor

Japan Ltd.

Tel: 81-043-299-2309

Fax: 81-043-299-2408

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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