Data Manual "MEAN" I/O "NCR 86COS Sprinp

Data Manual "MEAN" I/O "NCR 86COS Sprinp
Microelectronic Products Division
Colorado Sprinp
"NCR 86COS
"MEAN" I/O
Data Manual
REV.
REVISION HISTORY
A1
A2
A3
A4
A5
A6
A7
A8
Unreleased
Unreleased
Unreleased
Unreleased
Unreleased
Unreleased
Unreleased
Unreleased
PRINT DATE
August 26, 1988
December 19, 1988
January 5, 1989
January 9, 1989
January 16,1989
February 21, 1989
March 13,1989
The infonnation in this publication is subject to change without notice. No parts of this
publication may be reproduced, stored in a retrieval system, or transmitted, in any fonn or by
any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written pennission of NCR.
All Rights Reserved
The following products trademarked by other companies are referenced in this manual:
MicroChannel is a trademark of IBM
AT is a trademark of IBM
NuBus is a trademark of Texas Instruments
NCR
1635 Aeroplaza Drive
Colorado Springs, CO 80916
(719) 596-5612
(800) 525-2252
86C05 Features
• Connects to the following host buses:
1. IBM MicroChannel Bus
2. IBM AT (ISA) Bus
3. EISA Bus
4. Apple NuBus
• Master mode host bus operation with programmable data transfer width of 8, 16, or 32 bits
• Data transfer rate to 20 MBytes/sec
• Three independent host bus ports and interrupts to support multi-processing environments.
• Programmable host bus parameters; arbitration level, etc.
• On chip 32 word deep by 32 bit FIFO
• Programmable FIFO throttle which produces an extremely high host bus utilization
• 24 bit host bus address counter (32 bit NuB us)
• 24 bit transfer counter
• Six configuration registers
• Six user defined host I/O registers
• 8 or 16 bit DMA interface supports DMA controller or DMA device operation
• Programmable conditions for control microprocessor interrupt
• Connects to a non-multiplexed or multiplexed (address/data) control microprocessor bus
• BIOS PROM support
• Lock host bus and set semaphore command
• Clock rate to 40 MHz
• Built in host bus drivers for control signals
• Internal power on reset and flag
• Single +5 volt supply, CMOS low power consumption
Chapter 1
Functional Description
To help simplify interface logic even further the
86C05 provides a built in BIOS PROM support
logic. The PROM provides the host operating system with initialization parameters for the 86C05
and may also provide routines to communicate
with the I/O card.
1.1 INTRODUCTION
1.1.1 General Description
As shown in Figure 1, the NCR 86COS provides
a single chip "master mode" host interlace to the
MicroChannel, EISA, AT, or NuBus. The 86COS
perlorms data transfers to 20 MBytes/sec. Eight,
sixteen, or thirty two bit data transfers are supported on the host interlace. A 32 word deep by
32 bit FIFO is provided to buffer data transfers
between the host interlace and the DMA or microprocessing unit (MPU).
The DMA interface is programmable to support
eight or sixteen bit transfers to a local DMA controller or intelligent peripheral. The 86COS supports a simple REQIACK handshake and it also
provides parity for each eight bits on the DMA
bus. The DMA interface may be programmed to
operate in DMA controller or DMA device mode.
The 86C05 is available in a 160 pin quad plastic
flat pack.
BIOS PROM
Interface
32 Bit
MicroChannel
ATtEISA t
or NuBus
Interface
t
86COS
BUS
CONTROLLER
8 bit Control
MPU Interface
When the DMA interface is configured for 8 bit
transfers then the high byte of the DMA interlace
(bits 8-1S) may be used to carry the high byte (bits
8-1S) of the MPU interlace. This provides the capability for the MPU to transfer 8 or 16 bits of data
to the host or DMA interface.
Figure 1. Data Flow through the 86C05
All 86COS MPU registers are eight bits wide. The
86COS connects directly to a non-multiplexed or
multiplexed (address/data) MPU bus, thus supporting most popular microprocessors including Z8,
80S1, and 80188/80186.
1-1
16 Bit
DMA
1.1.2 Block Diagram
The block diagram of the 86C05 is shown on the following page. This illustration shows the MicroChannel
host interface:
32 Word X 32 Bit
FIFO
. . . 321 ,....
,
"-
DO
thru
D31
0
S
T
AO
H . . . 241 ,..... thru
"'
,
o
I
A23
S
T
B ,..... 28,1 ,...
U
N
T
E
R
F
cntl
S
A
...... 3
...
,
I
.....
,
H
C
E
INTO
,. thru
INT2
...
32 1 ...
,
hfinO
thru ......
"hfin32
....
32
$
32X 8 bit
(bits 0-7)
I
I
32 X 8 bit
(bits 8-15)
hfoutO
thru ......
hfout32 "'
32 X 8 bit
(bits 16-23)
hreq
and ......
hack "'
-
32 X 8 bit
(bits 24-31)
61
,
FIFO CONTROL,
ADDRESS, AND
COUNTER
,."
Control,
Config,
and Status
Registers
L ..... 8 I
o
,
"'
C
A
L
,
,.
"
51 ...
.....
,...
,....
M
P
U
,....
,...
......
,
B
U ......,
S
,......
..... 4
"'
I
I
,."
MA_DO
thru
MA_D7
MAO
thru
MA4
-lOWR
-lORD
-M_lO
MALE
MINT
CLOCK
FIFO_RDY
CONFlGO
thru
CONFIG3
M
P
U
I
N
T
E
R
F
A
C
E
mfinO
......
thru I'
mfin8
dfinO
,.... thru
dfin15
mfoutO
thru
mfout8
dfoutO
.....
~thru
"'
dfoutl5
mreq
and ......"'
mack
dreq
,.... and
dack
Figure 2. Block diagram of the 86C05
1-2
D
M
A
I
N
T
E
R
F
A
C
E
D
DD(O)
. . . 16 1 .... M
thru ...
...
A
DD(15)
,
,.
"'
,....
DO(I) ......
...."
DP(O)
"'
.....
DMA_REQ "-
DMA_ACK ,.....
C
o
N
T
,... R
o
,... L
L
E
R
1.2 OVERVIEW
DMA device mode the 86C05 asserts the
DMA_REQ signal and expects to send/receive
data when the DMA_ACK signal is received.
When the 86C05 is operating as a DMA controller
it receives a REQ signal from a device on the I/O
card and sends/receives data when it asserts the
ACKsignal.
.
1.2.1 Host Interface
The 86C05 provides all the control and data signals
to interface to the MicroChannel, EISA, AT, or
NuBus host buses (transceivers required on most
lines). Bus selection is made via configuration pins
on the 86C05. Host bus parameters are programmable as outlined below:
When the DMA interface is configured for 8 bit
transfers then the high byte of the DMA interface
(bits 8-15) may be used to carry the high byte (bits
8-15) of the MPU interface. This provides the capability for the MPU to transfer 8 or 16 bits of data
to the host or DMA interface.
a. Data Width - The firmware engineer may configure host data transfers in any width combinations (8, 16, or 32). Data is packed and unpacked in
the on-chip FIFO. For the MicroChannel andAT
host buses the 86C05 transfers to memory sizes
smaller then specified. For example, if a 16 bit host
transfer was requested but host memory is only 8
bits wide then the 86C05 performs two eight bit
transfers. Data transfers can occur to/from I/O or
Memory Space.
In addition, the 86C05 can transfer 8 bit DMA data
over either the high or low byte. This feature helps
the firmware engineer "clean-up" word transfers
with odd transfer counts.
1.2.3 MPU Interface
b. FIFO Throttle - Since the 86C05 operates in bus
master mode the maximum number of burst transfers per host bus ownership is programmable from
1 to 64 bus cycles. In addition the 86C05 supports
a hog mode which causes the chip to stay on the
bus until one of the following events occur:
The microprocessor (MPU) on the I/O card controls all data flow through the card and communicates to the host system via the 86C05. In a typical
system, the code contained within the BIOS
PROM would communicate an operating system
request to the I/O registers on the 86C05. A write
to these registers would generate an interrupt to the
local MPU on the I/O card. The MPU would then
direct the 86C05 to fetch the command block from
system memory and transfer it to local MPU memory. The MPU would then decode the command
and direct the data flow, for example from the
DMA interface to host memory. It should be noted
from this example that data can flow through the
86C05 in any direction from the the host, DMA, or
MPU interface.
1. A higher priority device requests the bus
2. The FIFO is full
3. The transfer counter is equal to zero and the
FIFO is empty
c. Host Interrupts - To facilitate multiprocessing
environments the 86C05 provides three independent host interface interrupts.
1.2.4 BIOS PROM Interface
d. Arbitration Priority - The host bus arbitration
priority is programmable.
The four host buses supported by this product require a BIOS PROM to aid the operating system in
configuring and using the I/O card The code contained within the BIOS PROM is executed by the
operating system to initialize the 86C05, the I/O
card, and infonn the operating system of the I/O
card presents. It may also provide the interface routines which communicate between an I/O driver
and the I/O card (86C05). It should be noted that
when the BIOS PROM interface is 8 data bits
wide, any code run directly from this PROM will
execute slowly. For higher performance systems
the BIOS code should be copied into system RAM
and executed from RAM. The method used to
e. I/O Registers - Six general purpose I/O registers
are provided for communication between the host
system and the local MPU.
1.2.2 DMA Interface
The DMA Interface transfers 8 or 16 bit data to
logic contained on the I/O card. This logic could be
a DMA controller or any device that supports the
REQ/ACK handshake. The interface is configurable to act as a DMA controller (8237 handshake
with RD / -WRTstrobes) or aDMAdevice. In
1-3
provide the BIOS PROM with a latched address
bus is specified below:
1.3 REGISTERS
1.3.1 86COS Register Organization
a. NuBus - 18 bits of latched memory address bus
is provided by the 86C05.
Register numbers 0-13 are shared between the
host interface and the MPU interface. They are
used for communication between the system processor and the MPU. Registers 15-31 are for the
exclusive use on the local MPU and are used to
control the operation of the 86C05. In Table 1, the
I/O register defInitions are proceeded by an access
code letter as outlined below:
b. MicroChannel - External address latches must
be provided when interfacing to this bus. The
address range is specified in register 6 and is
used by the 86C05 to gate PROM data to the
MicroChannel.
c. ATIEISA Bus - Since the lower address bits,
SA(0-19), are latched by theAT/EISA Bus
these lines connect directly to the address pins of
the BIOS PROM. As with MicroChannel explained above, register 6 specifies the address
range for the BIOS PROM.
H =Host Access
M =MPU Access
TABLE 1. REGISTER ASSIGNMENTS AND ADDRESSING
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address
3
2
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register
Number
o(OOh)
1 (Olh)
2 (02h)
3 (03h)
4 (04h)
5 (05h)
6 (06h)
7 (07h)
8 (08h)
9 (09h)
10 (OAb)
11 (OBh)
12 (OCh)
13 (ODh)
14 (OEh)
15 (OFh)
16 (10h)
17 (llh)
18 (12h)
19 (13h)
20 (14h)
21 (15h)
22 (16h)
23 (17h)
24 (18h)
25 (19h)
26 (lAb)
27 (lBh)
28 (lCh)
29 (lDh)
30 (lEh)
31 (lFh) ,
Register Function
Write
M-ConfigO
M-Config 1
HM- Config2
HM-Config3
HM-Config4
HM-Config5
HM-Config6
HM-I/OPort
HM-I/OCmdO
HM-I/OCmd 1
HM-I/OCmd2
H- I/O Data 0
H-I/OData 1
H- I/O Data 2
Not Defmed
System Control
System Config
Host Control 0
Host Control 1
Host Blk Count
Host Preempt Time
DMAControl
Xfer Command
Interrupt Mask
Xfer Count 0-7
Xfer Count 8-15
Xfer Count 16-23
Host Address 0-7
HostAddress 8-15
HostAddress 16-23
HostAddress 24-31
MPU Data Buffer
1-4
Read
H- ConfigO
H- Config 1
HM-Config2
HM-Config3
HM-Config4
HM-Config5
HM-Config6
HM-I/OPort
HM - I/O Stat 0
HM - I/O Stat 1
HM - I/O Stat 2
M-I/ODataO
M-I/OData 1
M-I/OData2
Not Defined
System Status
Not Defmed
Host Status 0
Host Status 1
Revision Number
Not Defmed
Not Defmed
Extended Status
Interrupt Status
Xfer Count 0-7
Xfer Count 8-15
Xfer Count 16-23
Host Address 0-7
HostAddress 8-15
HostAddress 16-23
Host Address 24-31
MPU Data Buffer
Register 0, 1 (OOh, Olh) - Configuration 0
Register 3 (03h) - Configuration 3 _
andl
This register contains the I/O address of the 86C05
chip when it is interfaced to the MicroChannel or
AT host bus. The reader should note that after a
power-up condition the 86C05 does not respond to
an I/O address until after this register has been
written (MicroChannel or AT bus only).
WRITE (mpu) / READ (host)
When the host interface is the MicroChannel or
EISA buses, these registers must contain a
unique card slot ID during I/O card set-up.
Mter this initialization is completed, or for the
NuBus or the AT interface these registers are
defined by the user. This register is not affected
by a firmware or hard reset.
For EISA bus operation this register must contain
byte 3 of the card slot ID during I/O card initialization. Once initialization is completed this register is
available for general I/O communications between
the host and local MPU. The reader should note
that the base I/O address (EISA bus) for this chip is
hard wired to ZC80h (where Z is EISA bus slot
specific).
Register 2 (02h) - Configuration 2
This register contains configuration data that is
written by the host or local MPU. When the host
interface is EISA, this register must contain byte 2
of the card slot ID during I/O card initialization.
This register is not affected by a firmware or hard
reset
When the 86C05 is interfaced to the NuBus this
register is used for general purpose configuration.
The I/O address space of the NuBus is FSXOOOII
where S is equal to the slot ID bits 3-0, F and 0 are
the hexadecimal digits, X is don't care, and I is the
32 I/O register decode. Each card in the NuBus
backplane is hardwired for a unique slot ID from
Oh to Fh.
WRITE (host and mpu) / READ (host and mpu)
REGISTER 2 (02h)
FUNCTION
7 6 5 4 3 2 1 0
I I I I I I I I
I I I I I I I + --- Enable I/O card (MC)
I I I I I I + ------ User Defined
I I I I I + ---------- User Defmed
I I I I + ------------- User Defmed
I I I + ----------------- User Defined
I I + --------------------- User Defmed
I + ------------------------ User Defined
+ ---------------------------- User Defined
Bit 0
WRITE (host and mpu) / READ (host and mpu)
For MicroChannel operation the I/O address
placed in this register is compared against
address bits 15-8. The I/O address is written
by the Host processor during I/O card configuration.
When this chip interfaces to the AT bus the
I/O address placed in this register is compared
against the AT address bits 9-5. The I/O address
is written to this register by the local MPU as
soon as possible after power-up.
- This bit is pre-defmed for MicroChannel operation. It is user defined for all
other host buses. For MicroChannel
operation this bit is cleared anytime the
86C05 is hard reset. The host processor
would typically initialize the I/O registers and then write a one to this bit thus
enabling the card (and chip) for normal
operation. When this bit is cleared the
86C05 does not respond to any host bus
access (except set-up).
Register 4 (04h) - Configuration 4
This register provides the capability for the firmware engineer to hard reset the 86C05 chip. Bits 0,
1, and 2 are cleared by a hard reset. Bit 1 is also
cleared by a firmware reset.
Bits 1-7 - User Defmed
1-5
WRITE (host and mpu) / READ (host and mpu)
WRITE (host and mpu) / READ (host and mpu)
REGISTER 4 (04h)
REGISTER 5 (05h) FUNCTION DEFINED FOR
MCATEISA
FUNCTION
7 654 3 2 1 0
I
I
I
I
I
I
I
I
I I I
I I +---Enable I/O card (EISA)
I + ------ Chnl Chk Indicator (EISA)
+ ---------- Hard Reset (Write Only)
+ ------------- Not Defined
+ ----------------- Not Defined
+ --------------------- Not Defmed
+ ------------------------ Not Defined
+ ---------------------------- Not Defined
Bit 0
Bit 1
Bit2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
7 6 5 4 3 2 1 0
I I I I I I I I
I I I I I I I +--HostBus
I I I I I I + -----Arbitration
I I I I I + ---------Priority
I I I I + ------------- of 110 card
I I I + ----------------Linear Algorithm
I I I
10or!20CLK
I I + --------------------16 Bit Host Data
I + ----------------------- Chnnl Chk Status
+ --------------------------Chnnl Chk
Indicator
- This bit is pre-defined for EISA operation. It is user defined for all other host
buses. This bit is cleared anytime the
86C05 is hard reset. The host processor
would typically initialize the I/O registers and then write a one to this bit thus
enabling the card for nonnal operation.
This bit does not disable or enable any
86C05 functions.
XX
XX
XX
XX
X
X
XX X
XX
XX
Bits 0-3 - These bits indicate the arbitration priority for the MicroChannel and DMA
Channel usage for the AT Bus. For
MicroChannel operation a hexadecimal
value ofF (1111) has the lower priority
and a hexadecimal value of 0 (0000)
has the highest priority.
- When this bit is asserted the EISA bus
I/O CHCK signal is asserted. For all
other host bus this bit is user defined.
For AT bus operation the 86C05 asserts
the DRQ signal as shown below:
- This latched bit provides a hard reset to
the 86C05 chip. This programmable reset is similar to a host or power-up reset
with the following exceptions:
Bits
3210
0001
0010
0100
1. Registers 2,3,5,6, and 16 are not
reset
86C05DMA
Request Si~al
DRQ(O)
DRQ(l)
DRQ(2)
The slot specific master request signal
(-MREQx) is asserted when the 86C05
requires EISA bus access.
2. NuBus slave logic is not reset
3. Dual port register control logic is not
reset
The NuBus arbitration priority is set by
ID(0-3) pins. Therefore for NuBus operation these bits are user defmed.
Bits 3-7 - These bits are not defined and should
not be used by the firmware engineer.
Bit 4
Register 5 (05h) - Configuration 5
This register is user defined when the host interface is the NuBus and it is pre-defmed for MicroChannel, EISA, and AT operation as outlined
below. It is cleared by a hard reset.
- For MicroChannel operation, when this
bit is deasserted the 86C05 implements
the fairness algorithm for host bus arbitration. When this bit is asserted the
86C05 implements the linear priority
arbitration algorithm.
For AT operation, this bit indicates the
number of 86C05 clocks (25ns) the
chip should wait from the time DMA
1-6
3--0, F is the hexadecimal digit, X is don't care, and
Pis 64K BIOS PROM space. Each card in the
NuBus backplane is hardwired for a unique slot ID
from Oh to Ph.
acknowledge is received until the
86C05 starts to access the AT Bus.
When this bit is asserted the 86C05
waits 10 clocks and when it is deasserted it waits 20 clocks. The ffiM AT
specification states the I/O Card must
wait two BCLKs after receiving DACK and driving MASTER low before it can drive the AT bus command
strobes.
BitS
Bit 6
Bit 7
WRITE (host and mpu) / READ (host and mpu)
When this chip interfaces to the MicroChannel,
EISA, or AT bus the BIOS PR01\1 starting address and size information is placed in this register. The BIOS PROM normally resides in the
OCOOOOh to ODFFFFh address range. When this
chip interfaces to the MicroChannel or EISA
bus the BIOS PROM address range is written
by the host processor during I/O card configuration. When this chip interfaces to the AT bus
the BIOS PROM address range is written by
the local MPU as soon as possible after powerup. For mM BIOS PROM selection, address
bits 23-13 are specified as shown below:
- This bit is only defined for MicroChannel, AT, or EISA bus operation.
It is user defined for NuBus operation.
If the hardware engineer needs only 16
bits of data transferred over the MicroChannel, EISA, or AT bus then the upper data word (bits 15-31) is re-defined
as an I/O port (register 7). Data bits
16-23 are for output and data bits
24-31 are input. The host or MPU may
read or write this port thru register 7.
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13
o
- This bit is pre-defmed for the MicroChannel host bus and is user defmed for
all other hosts. It indicates additional
check status infonnation.
0
0
0
1
1
0 bit4 bit3 bit2 bid
For 32 bit addresses (MicroChannel and EISA)
the hardware engineer should externally decode
address bits A31-A24. For MicroChannel operation when the MADE24 bit is deasserted
(32 bit address) and for all EISA operation the
-HST_MEM pin (result of external decode) must
be asserted to enable a BIOS PROM access.
- When this bit is asserted the MicroChannel CHCK signal is active or the
AT signal I/O CHCK is active. For
NuBus and EISA operation this pin is
user defmed. The fmnware engineer
must exercise care when setting this bit
and bit 6. A read operation should fIrst
be performed to find the value of bits
0-5. The write operation should then
rewrite these bits to their original value.
The BIOS PROM address range is specified
below:
REGISTER 6 (06h)
FUNCTION
7 6 5 4 3 2 1 0
Register 6 (06h) - Configuration 6
This register contains the BIOS PROM address
range when the 86C05 is interfaced to the MicroChannel, EISA, or AT bus. The reader should note
that after a reset the 86COS does not respond to a
BIOS PROM address until after this register has
been written (MicroChannel, EISA, or AT bus
only). When the 86C05 is interfaced to the NuBus
all bits in this register, except 6 and 7, are user defmed. The contents of this register are not affected
by a firmware or hard reset.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I I I I I
I I I I I +---NotDefined
I I I I + ------ BIOS PROM Addr Bit 13
I I I + ---------- BIOS PROM Address Bit 14
I I + -------------BIOS PROM Address Bit 15
I + ----------------- BIOS PROM Address Bit 16
+ ---------------------Not Defined
o
0 ------------------------ 8K BIOS PROM Size
o 1 ------------------------ 16K BIOS PROM Size
1 0 ------------------------ 32K BIOS PROM Size
1 1 ------------------------64K BIOS PROM Size
The reader should note that the BIOS PROM starting address must be on a memory boundary equal
to the size of the BIOS PROM. For example, a
32K PROM must start on a 32K memory address
(Le. bits 1 and 2 must equal zero).
The address of the NuBus BIOS PROM is
FSXFPPPP where S is equal to the slot ID bits
1-7
Register 7 (07h) - 110 Port
Register 11, 12, 13 (OBh, OCh, ODh) - 110 Data
This I/O port is always available when the 86C05
is connected to the NuBus. For MicroChannel,
EISA, or A bus operation, this port is available
only if register 5, bit 5 is asserted. A write to this
register sends the data to eight output pins. A read
of this register provides eight unlatched bits of data
from the input pins (see register 5 for more information). This port is not affected by finnware or
hard reset.
WRITE (host) / READ (mpu)
These registers are used to communicate information from the host to the MPU. They could, for
example, hold a 24 bit address that points to a host
mailbox structure. If the 86C05 is operating as
three separate virtual ports these.registers could
contain unique information about each port. These
registers are not affected by a firmware or hard
reset
Register 8, 9 and 10 (08h, 09h and OAh) - 110
Command
Register 15 (OFh) - System Control/System
Status
These registers can be written or read by both the
host processor and the local MPU. In a typical
operation the host processor would write a command (with bit 7 asserted) to one of these registers.
The local MPU would receive an interrupt and
read the command. It would then execute the command, write status information to this register, clear
bit 7 in this register, and generate a unique host
interrupt for this port. Bit 7 is asserted when the
86C05 is hard reset (a hard reset occurs when the
host interface reset pin is asserted) or a ftrmware
reset occurs (a fmnware reset takes place when bit
2 of register 4 is asserted). Bits 0--6 are not affected
by a firmware or hard reset.
Bits 0-5 of this control register are cleared by a
fmnware or hard reset.
WRITE (mpu)
REGISTER 15 (OFh) FUNCTION
7 654 3 2 1 0
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WRITE (host and mpu) / READ (host and mpu)
REGISTER 8, 9, or 10 FUNCTION
(08h, 09h, OAh)
I I I I I I I
I I I I I I +--- User Defmed
I I I I I + ------ User Defined
I I I I + ---------- User Defined
I I I + ------------- User Defmed
I I + ----------------- User Defmed
I + --------------------- User Defmed
+ ------------------------ User Defmed
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0
0
1
1
0
0
1
1
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0--- Test and Set Bit 0
1 --- Test and Set Bit 1
0--- Test and Set Bit 2
1 --- Test and Set Bit 3
0---TestandSetBit4
1 --- Test and Set Bit 5
0 --- Test and Set Bit 6
1 --- Test and Set Bit 7
+ ------------------------ Simulate Power On Reset
+ ---------------------------- Reset Power on Flag
Bits 0-2 - Speciftes which bit to test when the Set
Semaphore command is executed.
Bit 3
- When this bit is asserted the currently
executing command is halted. This bit
is normally set by the fmnware engineer prior to setting the hard abort bit
(bit 4). It forces the chip to release the
host bus, halt DMA activity, etc. Asserting this bit terminates the execution of
most commands.
Bit 4
- When this bit is asserted the currently
executing command is hard aborted.
+ ---------------------------- Busy
Bits 0--6 - User Defmed
Bit 7
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0
0
0
1
1
1
1
+ ------------- Halt State Machines
+ ----------------- Hard Abort
+ --------------------- Diagnostic Bit
7 6 5 4 3 2 1 0
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- This bit is asserted by a hard reset or a
write from the host or MPU interface.
For example, the host would assert this
bit when it issues a new command to
the 86C05. When this bit is asserted an
interrupt (if not masked) is generated to
the local MPU.
1-8
Bit 5
- This bit allows the MPU to read internal nodes in the 86C05.
Bit 6
- When this bit is asserted its simulates a
power-up condition. The power on flag
is set and the chip is hard reset.
Bit 7
- Asserting this unlatched bit clears the
power on flag (register 15, bit 7)
only when the corresponding port is
transferring data into the 86C05.
Bit 7
- When this bit is asserted a power-on
condition is present. This bit can be
reset by writing a one to bit 7 of register
15.
Register 16 (IOh) - System Configuration
READ (mpu)
This register is cleared by a hard reset and is not
affected by a fmnware reset.
REGISTER 15 (OFh) FUNCTION
WRITE (mpu)
7 6 543 2 1 0
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+
I I I I I I
I I I I I +---MPUDataReady
I I I I + ------ Transfer Counter =0
I I I + ---------- FIFO Empty
I I + ------------- FIFO Full
I + ----------------- Host Operation Done
+ ---------------------DMA Operation Done
------------------------ MPU Operation Done
+ ---------------------------- Power On Flag
Bit 0
Bit 1
REGISTER 16 (10h) FUNCTION
7 6 5 4 3 2 1 0
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- When the MPU is transferring data to/
from the 86C05 (register 31) this bit indicates the chip is ready to accept more
data.
- When asserted the FIFO is pseudo
empty.
Bit 3
- When asserted the FIFO is pseudo full.
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0
0
1
1
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I I + --- Polarity MINT pin
I + ------EnableFJFO_RDYpin
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0 ---------- Disable DMA Parity
1 ---------- Enable DMA Odd Parity
0 ----------DMA -RD/-WRT Strobes
1 ---------- Enable DMA Even Parity
+ ----------------- Upper byte DMA path
I + --------------------- FIFO or /Xfer
+ ------------------------ Don't Reset FIFO
+ ----------------------------Disable ResecOut pin
- When this bit is asserted the transfer
counter is equal to pseudo zero. The
transfer counter may in fact be non-zero
but for the transfer size there are zero
bytes left to transfer. For example, if
performing a 32 bit transfer (four bytes)
from the host to the DMA interface and
the transfer counter equals 3 (bytes)
then this bit is set. The 86C05 can not
read anymore data from the host (32
bits at a time) until the fmnware
changes the transfer size and re-issues
the command.
Bit 2
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Bits 4--6 - These bits indicate the corresponding
interface has completed its task. For example, when transferring data from the
host to the MPU and the transfer
counter equals pseudo zero and the
86C05 chip has released the bus, then
bit 4 is asserted. These bits are valid
Bit 0
- This bit indicates the polarity of the
interrupt pin. When this bit is a one the
interrupt pin is high true polarity. When
this bit is a zero the interrupt pin is low
true polarity.
Bit 1
- When this bit is asserted the MPU
FIFO_RDY pin is enabled. The
FIFO_RDY pin nonnally connects to a
DMA controller on the MPU bus. This
allows the fmnware engineer to transfer
data between MPU memory and the
86C05 under DMA control. Alternately,
the finnware engineer may poll bit 0 of
register 15 before transferring data between the 86C05 FIFO and local MPU
memory.
Bits 2-3 - These bits control the function of the
parity bits as outlined above.
Bit 4
1-9
- When this bit is asserted and an 8 bit
DMA transfer is requested (via register
22) then the 8 bit transfer is performed
on the upper data byte.
Bit 5
- This bit affects the definition of registers 24 through 30 as outlined below:
AT since all transfers on the NuBus are
into memory space. When this bit is
asserted the data is transferred to/from
host I/O space. This bit allows the
86C05 to transfer data directly to/from
an I/O card without using system
memory.
Reg 24--26
Reg 27-30
Bit 5 = 0 Xfer Counter Xfer Address
Bit 5 = 1 FIFO Counter FIFO Address
Bit 6
Bit 7
- When a new 86C05 command is issued
the FIFO is reset and data contained
within the FIFO is lost. If this bit is
asserted the 86C05 does not reset the
FIFO when a new command is issued
and therefore any data contained in the
FIFO is processed. This bit is usually
only set for error recovery.
Bit 2
- When this bit is asserted the 86C05 perfonns a resource lock on the NuBus or
locks the EISA bus during the requested
transfer.
Bit 3
- When this bit is asserted the 86C05
does not halt the currently executing
command when an access error occurs.
The access error is still reporteD. An access error occurs when the I/O CHCK
signal is asserted. In addition, for
MicroChannel operation an access error
is reported if the accessed slave does
not assert the -SD SFDBK signal.
Bit 4
- When asserted a 32 bit MicroChannel
or AT address is requested. The hardware engineer must connect the
HOST_OWN pin to the output enable
of a byte wide MSI driver. This driver
gates the address bits 24--31 onto the
host bus. All NuBus and EISA bus
transfers use a 32 bit address. The
reader should note that the AT bus
(ISA-16) is only defmed for 24 address
bits.
Bit 5
- For MicroChannel and AT operation
the 86C05 nonnally inserts four clocks
between the trailing edge of the command strobe and the leading edge of the
next command strobe. When this bit is
asserted the 86C05 inserts 6 clocks.
Bit 6
- When this bit is asserted the 86C05 perfonns continuous access to the same
host address.
Bit 7
- The 86C05 arbitrated for the host bus
access once the FIFO count specified in
register 19 has been met. It then transfers the count in register 19 to/from the
host and releases the host bus. When
this bit is set the 86C05 stays on the bus
and transfers data to/from the host until
the FIFO is empty/full or the 86C05 is
forced off the bus by a higher priority
- When asserted the reset out pin can not
go low true. This signal is used during a
fmnware reset to prevent the MPU
from being reset.
Register 17 (llh) - Host Control 0/ Host
.
Status 0
This control register is cleared by a firmware or
hard reset.
WRITE (mpu)
REGISTER 17 (llh) FUNCTION
7 654 3 2 1 0
I I I I
I I I I
I I I I
I I I
I I +---BlockXferMode(NB)
I + ------ I/O / Memory Space
(Me, EISA, AT)
+ ---------- Enable Resource Lock
(NB,EISA)
+ ------------- Ignore Access Error
(Me, EISA, NB)
+ ----------------- 32 bit Host Address (Me, AT)
+ --------------------- Six elks between Strobes
(Me, AT)
+ ------------------------ Don't Inc Host Address
+ ----------------------------Stay on Host bus till FIFO
full/empty
Bit 0
- When this bit is asserted the 86C05
uses block mode to transfer data to/
from NuBus memory. The NuBus
memory at the address specified must
support block mode. When this bit is
deasserted only one transfer is perfonned per NuBus transaction.
Bit 1
- This bit is only valid for MC, EISA, or
1-10
device (no higher priority device for
NuBus interface). READ (mpu)
Register 18 (12h) - Host Control 1 / Host
Status 1
REGISTER 17 (llh) FUNCTION
This control register is cleared by a firmware or
hard reset.
7 654 3 2 1 0
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I I I
I I +---HostSize16/NuBusTMO
I + ------ Host Size 32/NuB us TM1
+ ----------1/0 CHCK Pin (MC, EISA, An
WRITE (mpu)
REGISTER 18 (12h) FUNCTION
+ -------------Not Defined
+ -----------------Not Defined
+ ---------------------Host Term Count
+ ------------------------ Host Threshold
+ ----------------------------Connected to Host
7
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6 5 4 3 2 1 0
I I I I I I I
I I I I + + + --- Transfer Rate
I I I + -------------Not Defined
I I + ----------------- Not Defmed
I + --------------------- Assert Host Interrupt 0
I + ------------------------ Assert Host Interrupt 1
+ ---------------------------- Assert Host Interrupt 2
Bits 0-1 - These bits are valid after a host access
has completed. They indicate the host
memory size (MicroChannel, EISA, or
AT) or access error (NuBus):
BitBit
1Q
o0
o1
10
11
NuBus
Function
Try Again Later
Bus Timeout Error
Error
Normal Completion
Bits 0-2 - Regardless of the number of additional
clocks inserted into the bus access the
86C05 does not terminate the MicroChannel, EISA, or AT bus cycle until
the I/O Channel Ready signal is active.
These bits are not defined for NuB us
and EISA bus operation.
MC, EISA, or AT
Function
8 Bit Memory
16 Bit Memory
32 Bit Memory
32 Bit Memory
Bit 2
- This unlatched pin provides the fImlware engineer with the status of the I/O
CHCKpin.
Bit 3
- Not Defined
Bit 4
- Not Defined
BitS
- When asserted the 86C05 chip must
load the host transfer counter with the
count in the FIFO (host write operations) or transfer counter (host read
operations). This bit is asserted for the
last host transfer before a command
completes. This bit is for diagnostic
purposes only.
Bit 6
- This bit indicates the FIFO is ready for
another block of data. This bit is for diagnostics purposes only.
Bit 7
- When this bit is asserted the 86C05 is
connected (bus master) to the host bus.
For MicroChannel operation these bits
indicate the number of additional clock
(ac) periods to add to the -CMD strobe.
For AT bus operation these bits select a
transfer rate. Additional clock periods
are added to the access strobes as outlined below (assuming 40 WIz clock
input / 2 =50 ns per additional clock
added):
Strobe Pulse
Bits
Width/ac
2lQ
!Jill
000
001
010
011
100
101
110
111
100/0
150/1
200/2
250/3
300/4
350/5
400/6
450/7
32 Bit
Transfer Rate
(Mbytes!sec)
20
16
13.4
11.4
10
8.9
8.0
7.3
Bits 3-4 - Not Defined
Bits 5-7 - Asserting these unlatched _bits produce
a host interrupt as shown above. The
1-11
interrupt is cleared when the host or
MPU writes to the I/O register indicated
below:
Interrupt
o
1
2
bus until the FIFO is empty/full. For NuBus
transfers in block mode, the value in this register must correspond to 2, 4, 8, or 16. The value
placed in bits 0, 1, and 2 of this register inOicates the block count as shown below:
I/O Register
Register 8
Register 9
Register 10
Bits
2.1 Q
000
001
010
o 11
100
101
110
111
READ (mpu)
REGISTER 18 (12h) FUNCTION
7 6 5 4 3 2 1 0
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I I I I
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I I I + --- MicroChannel Mode
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I I + ------ AT Mode
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I + ---------- EISA Mode
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+ ------------- NuBus Mode
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I + ----------------- Host ID Bit 0 (NB)
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+ ---------------------Host ID Bit 1 (NB)
I + ------------------------ Host ID Bit 2 (NB)
+ ----------------------------Host ID Bit 3 (NB)
Number of
Host Transfers
1
2
4
8
16
32
64
64
READ (mpu)
REGISTER 19 (13h) FUNCTION
7 6 5 4 3 2 1 0
I I I I I I I I
I I I I I I I +---Revision
I I I I I I + ------ Number
I I I I I + ---------- of
I I I I + ------------- 86C05
I I I I
I I I + -----------------Not Defined
I I + ---------------------Not Defined
I + ------------------------Not Defined
+ ----------------------------Not Defined
Bits 0-3 - The host interrace of the 86C05 chip is
configured (CONFIG2 and CONFIG3
pins) to operate in one of the modes indicated by these bits.
Bits 4-7 - These bits indicate the slot ID for the
NuBus.
Register 19 (13h) - Host Blk Count lRevision
Number
Bits 0-3 - This number represents the current revision number of the 86C05. The count
began with the prototype chip at zero.
The Host Block Count register is cleared by a fmnware or hard reset.
Bits4-7 - Not Defined
Register 20 (14h) - Host Preempt Time
WRITE (mpu)
This register is not affected by a firmware or hard
reset
The value written to this register indicates the
number of requested transfers to/from the host
when the 86C05 becomes bus master. For example, if the 86C05 is transferring data to the
host and 32 bit transfers are enabled and these
bits equal 1 (see below), then the 86C05 waits
until the FIFO contains at least eight bytes before arbitrating for host bus access. Once bus
ownership is obtained the 86C05 attempts to
transfer the block count specified in this register
before releasing the bus. The transfer tenninates
early if the 86C05 loses bus priority or is on the
bus for too long (register 20). If bit 7 of Register
17 is asserted the 86C05 attempts to stay on the
WRITE (mpu)
The value written to this register is the number
of clock cycles divided by 4 that the 86C05 can
stay on the bus after a bus release condition is
present This register is not used for NuBus
operation.
The bus release condition varies for each host
bus supported as shown below:
1. MicroChannel- assertion of the -PREMPT
signal
1-12
2. EISA - deassertion of the -MACKx signal
3. AT - bus release timeout starts immediately
after bus ownership begins.
or leading edge asserted. When this bit
is asserted edge mode is enabled.
When the 86C05 DMA interface is
operating as a DMA controller, this bit
specifies a hold off period. That is, after
the 86C05 asserts then deasserts DMA
ACK it does not re-assert DMAACK
until the time specified by bits 0--2 has
passed.
Register 21 (ISh) - DMA Control
Bits 0-6 of the DMA Control register are cleared
by a finnware or hard reset.
WRITE (mpu)
REGISTER 21 (15h) FUNCTION
Bit 5
- When this bit is asserted it indicates the
86C05 is operating with a high true
DMA REQ signal.
Bit 6
- When this bit is asserted it indicates the
86C05 is operating with a high true
DMAACK signal.
Bit 7
- When this unlatched bit is asserted the
7 6 5 4 3 2 1 0
I I I I I
I I 0 0 0 --- 2 clocks DMA REQ pin width
I I 0 0 1 --- 3 clocks DMA REQ pin width
I I 0 1 0 ---4 clocks DMA REQ pin width
I I 0 1 1 --- 5 clocks DMA REQ pin width
I I 1 0 0 --- 6 clocks DMA REQ pin width
I I 1 0 1 --- 7 clocks DMA REQ pin width
I I 1 1 0 --- 8 clocks DMA REQ pin width
I I 1 1 1---9 clocks DMAREQ pin width
I I
I + ------------- DMA !Device or Controller
+ ----------------- Level or /Edge (DMA Device)
DMA REQ signal is toggled. This bit is
required to "un-hang" edge asserted
DMA controllers.
Register 22 (16h) - Transfer Command /
Extended Status
ACKHoldOff
(DMA Controller)
+ --------------------- DMA REQ high true
+ ------------------------ DMA ACK high true
+ ---------------------------- Toggle DMAREQ
This register is cleared by a firmware or hard reset.
WRITE (mpu)
Bits 0--2 - These bits specify the width of the
DMAACK signal when operating as
a DMA controller. The 86C05 waits
until the DMA REQ signal is asserted
and there is data to transfer to/from the
FIFO. It then asserts the DMAACK
signal the number of clock pulses specified by these bits.
REGISTER 22 (16h) FUNCTION
7 6 5 4 3 2 1 0
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When the 86C05 is operating as a
DMA device, it drives the DMA REQ
signal and transfers data when the
DMAACK signal is received. Under
this condition, these bits are not used.
Bit 3
Bit 4
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0
0
1
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0
0
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0 --- Transfer Host -> DMA
1--- Transfer DMA -> Host
0 --- Transfer HOST -> MPU
1--- Transfer MPU -> HOST
0 --- Transfer DMA -> MPU
1--- Transfer MPU -> DMA
0 --- Set Semaphore1--- No Operation
o 0 -------------- Transfer 8 bit host data
o 1-------------- Transfer 8 bit host data
1 0-------------- Transfer 16 bit host data
1 1-------------- Transfer 32 bit host data
- This bit specifies whether the 86C05 is
operating as a DMA controller or DMA
device. When this bit is asserted DMA
controller mode is enabled. See discussion of bits 0--2.
o 0 --------------------- Transfer 8 bit DMA data
o 1 --------------------- Transfer 8 bit DMA data
1 0 --------------------- Transfer 16 bit DMA data
1 1 --------------------- Transfer 16 bit DMA data
- When the 86C05 DMA interface is op-
erating as a DMA device, this bit specifies whether the DMA REQ pin is level
+ ----------------------------16 bit MPU data
1-13
Bits 0-2 - When these bits are written the command indicated above begins execution.
The fmnware engineer must initialize
all other registers (transfer count, etc.)
before issuing a command to this register. The fmnware engineer can poll
(register 23) for command complete or
receive an interrupt.
register is asserted, bit 1 (extended status) of register 23 is also asserted.
REGISTER 22 (16h) FUNCTION
7 6 5 4 3 2 1 0
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The Set Semaphore Command executes
on the host bus and performs a read
modify write operation. This command
frrst locks host memory, reads a byte
from host memory, transfers the byte
into the FIFO, sets the indicated bit,
writes the byte back to host memory,
and unlocks host memory. Once the
command has completed the local
MPU should read the semaphore (register 31) to determine if it now owns the
resource. A bit value of zero indicates
the resource is ours. A bit value of one
indicates the resource is owned by another processor.
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I I I
I I +---ForcedOffBus (MC)
I + ------Host Timeout Error (NB)
I
orSlaveNotAvailable(MC)
+ ----------FIFO or TC Contains Data
I I I + -------------Cbip Reset Occurred
I I I + ----------------- Command Aborted
I I + --------------------- Parity Error
I + ------------------------ MPU Overrun
+ ---------------------------- Command Busy
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Bits 3-4 - These bits indicate the size 'of the host
transfer. For MicroChannel or AT
operation the 86C05 senses the slave
device memory width and performs
smaller size transfers if required. For
example, if these bits request the 86C05
to perform a 32 bit transfer but the
memory width is only 16 bits, then the
86C05 performs two 16 bit transfers
over host data bus bits 0-15.
Bit 0
- If the 86C05 stays on the MicroChannel
longer then 7.5 usec after -PREMPT is
asserted it could be forced off by the
central arbitration unit, when this occurs this status bit is asserted and the
command is aborted.
Bit 1
- If the accessed NuBus memory card
does not respond within the 255 clock
timeout period this bit is asserted.
When memory or I/O space is accessed
on the MicroChannel a signal is returned to indicate if a card is present.
When this signal is not returned this bit
is set and the data transfer terminated
(see register 17,bit 2).
Bit 2
- If the FIFO contains data or the transfer
counter is not equal to pseudo zero
when a command completes, this bit is
set.
Bit 3
- When a chip reset occurs this bit i~
asserted.
Bit 4
- When the fmnware engineer performs a
hard abort or halts command execution,
this status bit is asserted.
Bit 5
- When this bit is asserted a parity error
was detected on data received over the
DMA interface.
Bit 6
- This bit indicates an over/underrun condition occurred while transferring data
between the 86C05 and the local MPU.
The 86C05 needs 12 clocks from the
trailing edge of an access to the MPU
For EISA bus operation the 86C05 allows the system board to perform the
size translations.
Bits 5-6 - These bits indicate the width of the
DMA interface data path.
Bit 7
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- When this bit is asserted 16 bits of data
is transferred when register 31 (MPU
Buffer Data) is accessed. This bit
should only be asserted if the hardware
engineer has connected the. upper byte
DD1(0-7) oftheDMA interface to the
MPUbus
READ (mpu)
This register provides extended status for the fmnware engineer. When any error bit (bits 0-6) in this
1-14
Data Buffer (register 31) to the leading
edge of the next access. The overrun
condition can be avoided by polling
register 15, bit 0 before transferring data
to/from register 31 or by connecting the
FIFO RDY pin to a DMA controller on
theMPUbus.
this register. These bits are not latched
by this register.
Bits 5--7 - These bits indicate the condition of the
three host interrupt pins. The 86C05 has
the capability to drive or receive these
lines. These bits are not latched.
- This bit is asserted while a 86C05 com-
Bit 7
Register 24, 25, 26 (ISh, 19h, 1Ah) - Transfer or
FIFO Counter
mand is executing. The firmware engineer may poll this bit for a command
complete condition.
The 24 bit Transfer Counter is not affected by a
fmnware or hard reset. The FIFO Up!Down
Counter, Host Transfer Counter, and Partial Host
Transfer Counter are cleared by a frrmware or hard
reset
Register 23 (17h) -Interrupt Mask / Status
WRITE (mpu)
WRITE(mpu)/~(mpu)
When the mask bit in this register is asserted and
the corresponding bit is a one for the interrupting
condition (listed below) the 86C05 generates an
interrupt to the local MPU. This register is cleared
by a firmware or hard reset.
When register 16 bit 5 is zero, these registers
contain the 24 bit data transfer count as shown
below:
READ (mpu)
Register 24 (18h) - Low Byte
Register 25 (19h) - Middle Byte
Register 26 (lAb) - High Byte
REGISTER 23 (17h) FUNCTION
7 6 5 4 3 2 1 0
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Bit 1
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During data transfers this register is decremented on writes to the FIFO. It is used to control the requests for more data into the FIFO.
When determining the number of bytes that
have been transferred the frrmware engineer
should consider the transfer count~r, and the
FIFO counter (contents of register 24 when register 16, bit 5 is one). If the contents of these·
registers are read during a data transfer they
must be debounced.
I I I
I I + --- 86C05 Cmd Completed
I + ------ 86C05 Extended Status
+ ---------- Bit 7 of Register 8 asserted
+ ------------- Bit 7 of Register 9 asserted
+ ----------------- Bit 7 of Register 10 asserted
+ --------------------- Host Interrupt 0 asserted
+ ------------------------ Host Interrupt 1 asserted
+ ---------------------------- Host Interrupt 2 asserted
Bit 0
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- This latched bit indicates the command
specified in the Data Flow Control Register (22) completed. Bit 0 is cleared
when this register is read.
When register 16 bit 5 is a one, these registers
are defmed as shown below:
Register 24 (18h) - FIFO Transfer Counter,
8 bits
(bit 7 forces FIFO full
condition)
Register 25 (19h) - Current Host Transfer
Counter, 7 bits
Register 26 (lAh) - Partial Host Transfer
Counter, 2 bits
- If the command specified in the Data
Flow Control Register (22) completed
with an error, this bit is asserted. Bit 1 is
cleared when this register is read. The
ftrmware engineer should note that this
bit may be set before the transfer command completes, therefore this bit
should not be used to indicate command done status.
A write to one of these registers sets the count
to any value and a read shows the current
contents.
Bits 2-4 - When the host issues a command to this
chip it should assert bit 7 of register 8,
9, or 10. This asserts the indicated bit in
1-15
Register 27, 28, 29, 30 (IBh, lCh, IDh, lEh) Host Address or FIFO Address
The Host Address register is not affected by a fumware or hard reset. The FIFO Address register is
cleared by a finnware or hard reset.
WRITE (mpu)/READ (mpu)
When register 16 bit 5 is a zero, these registers
contain the host bus address as shown below:
Register 27 (IBh) Register 28 (1 Ch) Register 29 (IDh) Register 30 (lEh) -
Bits 0-7
Bits 8-15
Bits 16-23
Bits 24-31 (NB) or
Current Preempt Count
(MC,EISA,AT)
The address placed in this register is incremented by 0, 1, 2, or 4 after each host bus access. The frrmware engineer may read (and
debounce) these registers to monitor the progress of the data transfer. The contents of these
registers are also useful for error recovery. Register 30 is the upper address byte for NuB us and
it is the preempt counter for the MicroChannel,
EISA, or AT bus.
When register 16 bit 5 is a one, these registers
contain the FIFO In and FIFO Out Transfer
Address as shown below:
Register 27 (IBh) - FIFO In Address, 7 bits
Register 28 (lCh) - FIFO Out Address, 7 bits
The frrmware engineer may read these registers
as an aid to error recovery or set their contents
for diagnostic or error recovery purposes.
Register 31 (IF h) - MPU Data Buffer
WRITE (mpu)/READ (mpu)
When data is transferred between the MPU
and the FIFO, this register provides a buffer for
the data. The MPU should read or write to this
register when the FIFO RDY pin is asserted or
status bit 0 of register 15 is asserted. This register is not affected by a finnware or hard reset.
1-16
Chapter 2
86C05 Pin Definitions
The 86C05 supports four host interfaces; MicroChannel, AT, EISA, and NuBus. The following table defines
the pin names and shows the pin cross reference between the four host interfaces:
Table 9. Host Interface - Pin Definition and Cross Reference
MicroChannel
Signals
AT Bus
Signals
EISA
Signals
NuBus
Signals
A(O-l)
A(2-17)
A(18-19)
A(20-23)
D(0-31)
ADL
DS16RTN
SBHE
MADE24
M_-I/O
Sl
SO
CMD
CDSFBKI
CD SFB KO
CHRDYRTN
ARB_IN (0)
ARB_IN(1-2)
ARB_IN(3)
ARB_OUT(O)
ARB_OUT(1-2)
ARB_OUT(3)
BURST
PREEMPT
ARB/-GNT
IRQ(0-2)
CDSETUP
CHCK
CHRESET
BE (0-2)
BE3
DS32RTN
TR32
SA(O-l)
SA(2-17)
SA(18-19)
LA(20-23)
SD(0-31)
BALE
-IOCS16
-SBHE
MADE24
-SWEN
-IOWR
-lORD
-MEMW
LA17
AEN
-IOCS32
-DACK(O)
-DACK(1-2)
VDD
DRQ(O)
DRQ(1-2)
LA19
IOCHRDY
-MASTER
-MEMR
-IRQ(0-2)
-MEMCS16
-I/OCHCK
RESETDRV
VDD
VDD
-MEMCS32
LA18
SA(O-l)
LA(2-17)
LA(18-19)
LA(20-23)
SD(0-31)
VDD
VDD
no connect
-LOCK
M-IO
W-R
-START
-CMD
no connect
AENx
-EX32
-MACKx
VDD
-EX16
-MREQx
no connect
no connect
-EXRDY
no connect
no connect
-IRQ(0-2)
VDD
-I/OCHCK
RESETDRV
-BE(0-2)
-BE(3)
BCLK
-BEOE
NA(O-l)
NA(2-17)
PO(O-l)
PO(2-5)
AD(0-31)
-START
-PI(5)
PO(6)
-ACK
-PO(7)
-TM1
-TMO
SLOT
PI(O)
PI(l)
, PI(2)
-ARB_IN(O)
-ARB_IN(1-2)
-ARB_IN(3)
-ARB_OUT(O)
-ARB_OUT(1-2)
-ARB_OUT(3)
SSLOT
-RQST
PI(3)
-NMRQ(0-2)
PI(6)
PI(4)
-RESET
-ID(0-2)
-ID3
-CLK
PI(7)
HAOE
HADIR
HDOE(0-2)
HDDIR
HOST_OWN
HST_MEM
PROMOE
-HAOE
HADIR
-HDOE(0-2)
HDDIR
-HOST_OWN
-HST_MEM
-PROMOE
-HAOE
HADIR
-HDOE(0-2)
HDDIR
-HOST_OWN
-HST_MEM
-PROMOE
no connect
RSLOCK
-HDOE(0-2)
HDDIR .
-HOST_OWN
-HST_MEM
-PROMOE
2-1
These host interface pins are common to all four host buses supported by the 86C05 chip. There are 7 common
pins. The following abbreviations are used:
I/O = Input and Output Pin
= Input Pin Only
o = Output Pin Only
TS =Tri-statePin
OC = Open Collector Pin
1P = Totem Pole Pin
I
Table 10. Host Interface-Common Pin Summary
Pines)
Name
Number
of Signals
Input!
Output
Pin
Pin
Type
Drive(ma)
1
1
1
1
1
1
1
0
0
0
1P
1P
1P
0
I
0
1P
8
8
8
8
8
1P
8
HADIR
BAOE
HDDIR
HDOE(0-2)
HOST_OWN
HST_:MEM
PROMOE
a
1P
Table 11. Host Interface-Common
Symbol
HADIR
Signal
Name
Host
Address
Direction
. I/O
Function
Pin
Number
0
46
This totem pole output signal connects to the
DIR pin of the LS245s which gate the address
bits to the MicroChannel, EISA, or AT bus.
When this pin is low the host address bus is
gated to the 86C05 chip. When this pin is high
the address bus from the 86C05 is gated to the
host address bus.
For NuBus operation this pin indicates a
Resource Lock condition.
BAOE
Host
Address
Output
Enable
o
This active low totem pole output signal
connects to the -OE pin of the LS245s which
gate the address bus between the 86C05 and
the MicroChannel, EISA, or AT bus.
47
This pin is not defmed for NuBus operation.
2-2
Table 11. Host Interface-Common (continued)
Symbol
Signal
Name
HDDIR
Host
Data
Direction
I/O
Pin
Number
o
19
Function
This totem pole output signal connects to the
DIR pin of the LS245s which gate the data bus
between the 86C05 chip and the MicroChannel, EISA or AT bus. When this pin is low
the host data bus is gated to the 86C05 chip.
When this pin is high the data bus from the
86C05 chip is gated to the host data bus.
For NuBus operation, this pin connects to the
DIR pin of the ALS640s which gate the multiplexed address/data bus between the 86C05
chip and the NuB us. When this pin is low the
NuBus address/data bus is gated to the 86C05
chip. When this pin is high the address/data bus
from the 86C05 chip is gated to the host data
bus.
HDOE(2)
HDOE(1)
HDOE(O)
Host
Data
Output
Enable
o
These active low totem poleoutput signals
connects tothe -OE pin of the LS245s (MicroChannel, EISA, or AT) or ALS640s (NuBus)
which gate data between the 86C05 and the
host bus. These signals pin out as indicated
below:
16
17
18
Host byte
o
1
2
3
Host
o
15
When this active low totem pole signal is
asserted, the 86C05 is the owner of the host
bus. This signal is also discussed under each
individual host bus.
I
80
This active low input signal is used to qualify
BIOS PROM access as outlined below .
Own
Host
Memory
Enable
-HDOEpin
-HDOE(O)
-HDOE(1)
-HDOE(2)
-HDOE(2)
a For AT bus this signal would normally be
tied to ground.
2-3
Table 11. Host Interface-Common (continued)
Symbol
Signal
Name
I/O
Pin
Number
Function
b. For MicroChannel and EISA bus (both support a 32 bit host address), this pin would-typically connect to an address comparator for host
address bits 24--31. The 86C05 chip compares
address bits 13-23. For MicroChannel operation, if the MADE24 pin is high then an active
level on this pin is not required.
c. The 86C05 chip does not decode address bits
20-23 for the NuB us. This pin could decode
these bits.
PROMOE
BIOS
PROM
Output
Enable
o
This totem pole active low output signal
connects to the -OE pin of a BIOS PROM.
When this signal is asserted the 86C05 has
detected a BIOS PROM access. The 86C05
also enables the host bus transceiver (byte 0) to
gate the BIOS PROM data to the host bus.
68
The 86C05 MicroChannel Interrace consists of 90 signals as outlined below. The 86C05 is configured to operate in the MicroChannel interrace mode when CONFIG2 is low and CONFIG3 is high. The following abbreviations are used:
I/O
I
=Input and Output Pin
=Input Pin Only
o =Output Pin Only
TS = Tri-state Pin
OC = Open Collector Pin
1P =Totem Pole Pin
Table 12. Host Interface-MicroChannel Bus Pin Summary
Pin(s)
Name
A(0-23)
ADL
ARB_IN(0-3)
ARB_OUT(0-3)
ARB/-GNT
BE (0-3)
BURST
Number
of Signals
Input!
Output
24
1
4
4
1
4
1
I/O
I/O
I
0
I
0
I/O
Pin
Pin
Type
Drive(ma)
TS
TS
4
24
1P
4
1P
4
24
OC
2-4
Table 12. Host Interface-MicroChannel Bus Pin Summary (continued)
Pines)
Name
CDSETUP
CDSFBKI
CD SFB KO
CHCK
CHRDYRTN
CHRESET
CMD
D(0-31)
DS16RTN
DS32RTN
IRQ(0-2)
MADE24
M_I/O
PREEMPT
SBHE
Sl
SO
TR32
Number
of Signals
Input!
Output
1
1
1
1
1
1
1
32
1
1
3
1
1
1
1
1
1
1
I
I
0
I/O
I
I
I/O
I/O
I
I
I/O
I/O
I/O
I/O
0
I/O
I/O
0
Pin
Type
Pin
Drive(ma)
1P
OC
24
TS
TS
24
4
OC
TS
TS
OC
TS
TS
TS
1P
4
24
24
24
24
24
24
4
8
Table 13. Host Interface-MicroChannel Bus
Symbol
Signal
Name'
A (0-2)
A(3-7)
A(8-14)
A(14-23)
Address
Bits
I/O
48-50
55-59
61-67
71-79
These active high tri-statesignals address
memory or I/O devices within the system.
They connect to the host bus thru LS245s and
provide 24 bits of direct addressing capability.
Only the lower 16 bits are decoded for I/O
operations. These signals are latched
(-ADL) by bus slaves. The user may drive 32
bits of address by connecting the HOST_OWN
pin to the -OE pin of a byte wide MSI driver.
ADL
Address
Decode
Latch
I/O
12
This active low, tri-state signal is used to latch
the contents of the address bus. The latch is .
open when this signal is low. Devices on the
MicroChannel must latch the address since
pipelining is possible. That is, the address may
change for the next MicroChannel cycle before
the -CMD strobe for the current cycle has been
deasserted. This pin connects directly to the
MicroChannel.
I/O
Pin
Number
2-5
Function
Table 13. Host Interface-MicroChannel Bus (continued)
Symbol
Signal
Name
ARB_IN(3)
ARB_IN(2)
ARB_IN(l)
ARB_IN(O)
Function
I/O
Pin
Number
Arbitration
Bus
Priority
In
I
143
144
145
146
These active high input pins connect directly to
the MicroChannel and receive arbitration bus
priority levels.
ARB_OUT(3)
ARB_OUT(2)
ARB_OUT(1)
ARB_OUT(O)
Arbitration
Bus
Priority
Out
°
138
139
141
142
These active high totem pole output signals are
used to present arbitrating bus participant
priority levels. The highest value of (hex Fh)
has the lowest priority and the lowest value
(hex Oh) has the highest priority. The priority
level of the 86C05 is programmed into register
5. These pins should connect to the MicroChannel through a 7407 open collector driver.
ARB/-GNT
Arbitrate/
Grant
I
149
This active high input signal indicates an
arbitration cycle is in process. When this signal
is low it is the grant to the winner to access the
channel. This pin connects directly to the
MicroChannel.
BE(3)
BE(2)
BE(l)
BE(O)
Byte
Enable
°
134
These active low totem poleoutputs are used
during 32 bit data transfers to indicate which
data bytes to placed on the MicroChannel.
These signals should connect to the MicroChannel thru a LS244 driver. The driver is
enabled by the -HOST_OWN pin.
BURST
Burst
I/O
148
This active low open collector signal is driven
low by arbitrating bus participants to indicate
the extended use of the MicroChannel. The
86C05 asserts this signal for all "master mode"
transfers. It deasserts -BURST during the last
transfer cycle. This pin connects directly to the
MicroChannel.
CDSETUP
Card
Setup
I
156
This active low input signal is used to force a
chip select. When it is active the host processor
may read or write registers 0-7. Register
135
136
137
2-6
Table 13. Host Interface-MicroChannel Bus (continued)
Symbol
Signal
Name
I/O
Pin
Number
Function
selection is made via the address bitsAO, AI,
andA2. This pin connects directly to the
MicroChannel.
CDSFBKI
Card
Select
Feedback
In
I
158
This active low input signal is used when the
86C05 is the bus master to indicate a slave is
present at the address requested.
CDSFBKO
Card
Select
Feedback
Out
a
157
This active low output signal indicates when
the 86C05 is being accessed by the MicroChannel. It is generated from an address
decode of the I/O registers or BIOS PROM.
When the 86C05 is bus master this signal must
be return from all addressed slaves. This pin
connects directly to the MicroChannel.
CHCK
Channel
Check
I/O
151
This active low open collector signal is used to
indicate a serious error. It is asserted when the
host processor or local MPU writes a one to bit
7 of register 5. A zero written to this register
deasserts this signal. The 86C05 tenninates the
host bus transfer, with an access error, if this
signal is asserted. This pin should connect directly to the MicroChannel.
CHRDYRTN
Channel
Ready
Return
I
159
This active high input indicates that the slave
addressed by the 86C05 needs additional time
to complete the requested read or write operation. When the slave needs more time it pulls
this signal low. The 86C05 inserts wait states
until this signal is high. This pin connects directly to the MicroChannel.
CHRESET
Channel
Reset
I
154
This active high input provides a hard reset to
the 86C05 chip. Intemallogic is ip.itialized by
this signal and any transfer operations are
aborted.
2-7
Table 13. Host Interface-MicroChannel Bus (continued)
I/O
Symbol
Signal
Name
C:MD
Command
I/O
28
This active low tri-state signal is used to define
when data is valid on the data bus. During
write opemtions, the data must be valid on the
bus throughout the period -C:MD is low. For
read operations, the data must be valid before
the trailing edge of -CMD and held on the bus
(hold time) until after CMD is high. This pin is
connected directly to the MicroChannel.
D(4--D)
Data
Bits
I/O
41-45
31-40
21-26
1-10
These are active high, tri-state signals. All data
transfers between the MicroChannel and the
MPU or DMAinterface flows through these
pins. These pins connect to the MicroChannel
thru LS245 transceivers. When the 86C05
transfers only 16 bits of data to the host, then
D(16--31) maybe progmmmed (register 5,
bit 5) as an I/O port.
-
D(14-5)
D(20-15)
D(30-21)
D(31)
Pin
Number
160
Function
DS16RTN
Data
Size
16
Return
I
153
This active low signal indicates that the slave
device which the 86C05 addressed is providing
(driving orreceiving) 16 bits of data. If this
signal is not returned from the slave device and
the 86C05 is progmmmed for 16 bit tmnsfers,
then the 86C05 performs two 8 bit transfers.
This pin connects directly to the MicroChannel.
DS32RTN
Data
Size
32
Return
I
152
This active low input signal is driven low by
32 bit slaves. When the firmware engineer
requests the 86C05 to perform 32 bit transfers
but the slave only supports 8 or 16 bit transfers,
then the 86C05 breaks the transfers into the
size supported by the slave. This pin connects
directly to the MicroChannel.
Host
o
15
When this totem pole signal isasserted the
86C05 is the owner of the MicroChannel. If
32 bit addressing is specified (register 17, bit 4)
then this signal should connect to the output
Own
2-8
Table 13. Host Interface-MicroChannel Bus (continued)
Symbol
Signal'
Name
I/O
Pin
Number
Function
enable pin of a bus driver (24 ma) that gates
address bits 24-31 onto the MicroChannel. It is
also required to drive the -BE(0-3) and TR32
signals onto theMicroChannel.
IRQ(2)
IRQ(l)
IRQ(O)
Interrupt
Request
I/O
129
130
133
These active low open collector signals are
used to infonn a system or concurrent
processor of the completion of a task.
The86C05 can also monitor these signals
and interrupt the local MPU when one or more
lines become active (register 23). The 86C05
drives these lines by setting the corresponding
bit in register 18. The system or concurrent
processor clears the interrupt by writing to the
I/O register indicated below:
Intemu?t
IRQ(O)
IRQ(1)
IRQ(2)
UO Re~ster
Register 8
Register 9
Register 10
External selection logic must be added to the
I/O card to provide programmability of these
signals. For example, if it is required that under
program control the -IRQ(O) signal generate an
interrupt on one of the MicroChannel pins IRQ
3--7, then -IRQ(O) must be gated through selector logic. These signals are internally pulled
high (400 Jla). These pins connect to the
MicroChannel thru a 7407 open collector
driver.
MADE24
Memory
Address
Enable
24
I/O
This active high tri-state signal indicates when
an extended (address bits 24-31) address is
used on the MicroChannel. When this signal is
Iowa 32 bit memory address is placed on the
bus. When this signal is high a 24 bit address is
on the bus. When the frrmware engineer requests 32 bit transfers, the additional 8 address
bits must be provided external to the 86C05.
This pin connects directly to the MicroChannel.
13
2-9
Table 13. Host Interface-MicroChannel Bus (continued)
Symbol
Signal
Name
I/O
Function
Pin
Number
Memory
or I/O
I/O
132
This tri-state signal distinguishes a memory
cycle from an I/O cycle. When this signal is
high a memory cycle is in progress. When
M_-IO is IowanI/O cycle is in progress. This
pin connects directly to the MicroChannel.
PREEMPT
Preempt
I/O
29
This active low open collector signal is driven
low by arbitrating bus participants to request
usage of the channel through arbitration. The
requesting arbitration bus participant removes
it preempt upon being granted the channel. The
86C05 asserts this signal when the use of the
channel is needed and the fairness algorithm
(if enabled, through register 5) allows the access. This pin connects directly to the MicroChannel.
SBHE
System
Byte
High
Enable
o
69
This active low tri-state signal enables the
transfer of data on byte 1 (bits 8-15) of the
data bus. It is used with AO to distinguish
between byte 0 (bits 0-7) and byte 1 (bits
8-15) transfers. This pin connects directly to
the MicroChannel.
~
SO
Status
Bit 0
Status
Bit 1
I/O
53
I/O
52
These active low tri-state signals indicate the
start of a MicroChannel cycle andalso defme
the type of cycle when used with the M_-10
signal (see above). When the 86C05 is a channel slave it latchs these bits with the trailing
edge of ADL. These pins connect directly to
the MicroChannel.
S1
M..:ILQ ..:S.Q
2-10
..:£!
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
Fynction
Reserved
I/O Write
I/O Read
Reserved
Reserved
MemWrite
MemRead
Reserved
Table 13. Host Interface-MicroChannel Bus (continued)
Symbol
Signal
Name
TR32
Translate
I/O
Pin
Number
o
155
Function
This active high totem pole output is driven
low when the 86C05 is perfonning 32 bit data
transfers. When this signal is low, the 86C05
drives MicroChannel signals -BE(0-3) to gate
data between 32 bit slaves and the 86C05. This
pin connects to the MicroChannel thru a
LS244 driver.
The 86C05 EISA Bus Interface consists of 79 signals as outlined below. The 86C05 is configured to operate in
the EISA bus host interface mode when CONFIG2 is high and the CONFIG3 pin is low.
The following abbreviations are used:
I/O = Input and Output Pin
I = Input Pin Only
o = Output Pin Only
TS =Tri-statePin
OC = Open Collector Pin
1P = Totem Pole Pin
Table 14. Host Interface-EISA Bus Pin Summary
Pin(s)
Name
AENx
BCLK
BE (0-3)
BEOE
C:rvm
EX16
EX32
EXRDY
HOST_OWN
I10CHCK
IRQ(0-2)
LA (2-23)
LOCK
MACKx
M_IO
MREQx
SA(O-I)
SD(0-31)
START
RESETDRV
W-R
Number
of Signals
Input!
Output
1
1
4
1
1
1
1
1
1
1
3
22
1
1
1
1
2
32
1
1
1
I
I
0
0
I
I
I
I
0
I/O
I/O
I/O
0
I
I/O
0
I
I/O
I/O
I
I/O
2-11
Pin
Type
Pin
Drive(ma)
TS
TS
4
4
1P
OC
OC
TS
TS
8
24
4
4
24
TS
TS
24
8
TS
TS
4
24
TS
24
Table 15. Host Interface-EISA Bus
Symbol
Signal
Name
I/O
Function
Pin
Number
AENx
Address
Enable
I
157
This active high, slot specificinput signal
indicates (when deasserted) that the 86C05
may respond to address and I/O commands.
This pin connects directly to the EISA bus.
BCLK
Bus
Clock
I
152
This active high input is provided for synchronizing EISA bus events with the main system
clock. BCLK operates at a frequency between
8.333 and 6 MHz with a duty cycle of 50 percent. This pin connects directly to the EISA
~~
-
BE(3)
BE(2)
BE(I)
BE(O)
Byte
Enable
o
134
135
136
137
These active low output totempole signals are
the byte enables that identify the specific bytes
addressed in a double word. These signals and
the address lines, LA(2-23), are pipelined from
one cycle to the next. -BE(3) enables the high
byte (byte 3) of a double word while -BE(O)
enables the low byte. These pins connect to the
EISA bus through an LS244 driver. The -OE
pin of the LS244 must connect to the -BEOE
pin.
BEOE
BE
Output
Enable
o
155
This active low totem pole output is driven low
to enable the -BE(0-3) signals onto the EISA
bus when the 86C05 is bus master. The
-BE(0-3) signals require a separate output enable pin from the address signals since they
must be floated while the system board performs data size translation.
CMD
Command
Strobe
I
28
This active low input signal provides timing
control within the EISA bus cycle. The system
board asserts this signal on the rising edge of
BCLK, simultaneous with the deassertion of
the -START signal. This pin connects directly
to the EISA bus.
2-12
Table 15. Host Interface-EISA Bus (continued)
Symbol
Signal
Name
I/O
EX16
16 Bit
Slave
I
143
This active low input signal indicates an EISA
memory or I/O slave is capable of transferring
16 bit size. During 16 bit bus master transfers
the 86C05 samples EX16 on the rising edge of
BCLK after -START is asserted. If this signal
is not asserted the 86C05 floats the -BE(0--3),
START, and SD(0-15) lines to allow the system board to perform a size translation. Once
completed the system board asserts this signal
and the 86C05 completes the cycle. This pin
connects directly to the EISA bus.
EX32
32 Bit
Slave
I
159
This active low input signal indicates an EISA
memory or I/O slave is capable of transferring
32 bit double word size. During 32 bit bus
master transfers the 86C05 samples EX32 on
the rising edge of BCLK after -START is asserted. If this signal is not asserted the 86C05
floats the -BE(0-3), START, and SD(0--31)
lines to allow the system board to perform a
size translation. Once completed the system
board asserts this signal and the 86C05 completes the cycle. This pin connects directly to
the EISA bus.
EXRDY
EISA
Channel
Ready
Input
I
148
This active high input signal lengthen a bus
cycle from its standard one BCLK time. It is
asserted by a memory or I/O device when it
can not respond quickly enough. When
EXRDY is low the 86C05 inserts wait cycles
(one BCLK) until the device or memory brings
it high. This pin connects directly to the EISA
bus.
Host
o
15
When this totem pole signal is asserted the
86C05 is the current owner of the EISA bus.
For the EISA bus this signal should connect to
the output enable pin of a bus driver (24 ma)
that gates address bits 24--31 onto the EISA
bus.
Pin
Number
Own
2-13
Function
Table 15. Host Interface-EISA Bus (continued)
Symbol
Signal
Name
I/OCHCK
I/O
I/O
Pin
Number
I/O
151
This active low open collector signal is used to
indicatea serious error. It is asserted when the
host processor or local MPU writes a one to bit
1 of register 4. A zero written to this register
deasserts this signal. The 86C05 tenninates the
host bus transfer, with an access error, if this
signal is asserted. This pin should connect directly to the EISA bus.
I/O
129
130
132
These active low open collector signals are
used to inform a system or concurrent
processor of the completion of a task. The
86C05 can also monitor these signals and
interrupt the local MPU when one or more
lines become active (register 23). The 86C05
drives these lines by setting the corresponding
bit in register 18. The system or concurrent
processor clears the interrupt by writing the I/O
register indicated below:
Channel
Check
IRQ(2)
IRQ(1)
IRQ(O)
Interrupt
Request
Function
Interrupt
IRQO
IRQ 1
IRQ2
UORegister
Register 8
Register 9
Register 10
If the user needs the capability to change inter-
rupt lines than external selection jumpers must
be added to the I/O card. For example, 86C05
pin IRQO could be jumper selectable to EISA
bus interrupts IRQ(3-7). These signals are
internally pulled high (400 ua). These pins
connect to the EISA bus thru a 74LS04 driver.
LA(2)
LA(3-7)
LA(8-14)
LA(15-19)
LA (20-23)
LOCK
Latchable
Address
I/O
50
55-59
61-67
71-75
76-79
These active high tri-statesignals address
memory or I/O devices within the system.
They form bits 2-23 of the address bus. These
lines are latched by the 86C05 on the
deasserting edge of -START. These pins are
onnected to the EISA bus thru an LS245 bus
transceiver.
Bus
o
13
This active low tri-state output pin is asserted
by the 86C05 to guarantee exclusive memory
Lock
2-14
Table 15. Host Interface-EISA Bus (continued)
Symbol
Signal
Name
I/O
Pin
Number
Function
access during the time -LOCK is asserted. This
pin is controlled by bit 2 of register 17. It is
always asserted during the Set Semaphore
command. This pin connects directly to the
EISA bus.
MACKx
Master
I
Acknowledge
146
This active low slot specific signal is asserted
by the system board to grant access to the
EISA bus. This signal is in response to the
86C05 asserting the -MREQx signal. The
86C05 must release the EISA bus within 8
usec after this signal is deasserted. Register 20
must be programmed for this preempt time.
This pin connects directly to the EISA bus.
M-IO
Memory
I/O
132
This tri-state signal or I/O distinguishes a
memory cycle from an I/O cycle. When this
signal is high a memory cycle is in progress.
When M-IO is IowanI/O cycle is in progress.
M-10 is pipelined from oneEISA bus cycle to
the next. This pin connects directly to the EISA
bus.
MREQx
Master
Request
0
142
This active low totem pole, slot specific, output signal is asserted by the 86C05 to request
EISA bus access. The system board asserts
-MACKx in response to this signal. This pin
connects to the EISA bus thru a 7407 open
collector driver.
SA(O-l)
System
I
48-49
These active high input signals are the lower
two bits of the system address bus. They are
latched by the system board on the deasserting
edge of BALE. The 86C05 uses these signals
for address selection and does not generate the
lower two address bits from the -BE(0-3)
lines. This simplifies 86C05 decode logic.
These pins connect directly to the bus.
2-15
Table 15. Host Interface-EISA Bus (continued)
Symbol
Signal
Name
SD(0-4)
SD(5-14) Bits
SD(15-20)
SD(21-30)
SD(31)
Data
I/O
I/O
Pin
Number
45-41
40-31
26-21
10-1
160
Function
These are active high, tri-state signals. All data
transfers between the EISA bus and the MPU
or DMA intetface flow through these signals.
These pins connect to the EISA bus thru
LS245 transceivers.
When the 86C05 only transfers 16 bits of data
to the EISA bus, then D(16-31) maybe programmed (register 5, bit 5) as an I/O port.
START
Start
I/O
53
This active low tri-state signal indicates the
beginning of an EISA bus access. It is asserted
for one BCLK period after the address is valid
on the bus. This pin connects directly to the
EISA bus.
Command
RESETDRV
Bus
Reset
I
154
This active high input signal provides a hard
reset to the86C05 chip. Internal logic is initialized by this signal and any transfer operations
are aborted.
W-R
Write/
Read
I/O
52
This tri-state pin indicates whether to petfonn
an EISA bus write or read operation. When this
pin is high a write operation is requested and
when Iowa react This pin connects directly to
the EISA bus.
2-16
The 86C05 AT Bus Interface consists of 86 signals as outlined below. The 86C05 is configured to operate in
the AT bus host interface mode when CONFIG2 is high and the CONFIG3 pin is high. The following abbreviations are used:
I/O = Input and Output Pin
I
=Input Pin Only
o = Output Pin Only
TS = Tri-state Pin
OC = Open Collector Pin
1P = Totem Pole Pin
;
Table 16. Host Interface-AT Bus Pin Summary
Pin(s)
Name
AEN
BALE
DACK(0-2)
DRQ(0-2)
HOST_OWN
I/OCHCK
IOCHRDY
IOCS16
IOCS32
IOWR
lORD
IRQ(0-2)
LA17
LA18
LA19
LA(20-23)
MADE24
MASTER
MEMCS16
MEMCS32
MEMR
MEMW
SA(0-19)
SBHE
SWEN
SD(0-31)
RESETDRV
Number
of Signals
Input/
Output
Pin
Type
Pin
Drive(ma)
1
1
3
3
1
1
1
1
1
1
1
3
1
1
1
4
1
1
.1
1
I
I/O
I
TS
24
o
o
TS
1P
I/O
I
I
I
I/O
I/O
I/O
DC
8
8
24
TS
TS
DC
TS
TS
TS
TS
TS
DC
o
o
o
I/O
I/O
o
24
24
4
4
4
4
4
24
24
I
I
1
I/O
1
20
1
1
32
1
I/O
I/O
TS
TS
TS
TS
TS
TS
o
I/O
I/O
I
2-17
24
24
4
24
24
4
Table 17. Host Interface-AT Bus
Symbol
Signal
Name
I/O
Pin
Function
Number
AEN
i\ddress
Enable
I
157
This active high, input signal indicates a DMA
cycle is in progress. The 86C05 uses the low
level of this signal to qualify all i\T bus access
to the internal registers. This pin connects directly to the i\T bus.
BALE
i\ddress
Latch
Enable
I/O
12
This active high, tri-state signal is used to latch
the contents of the address bus bits Li\(17-23).
The address latch is opened when BALE is
high and the address is latched on the high to
low transition of this signal. This signal is not
driven when the 86C05 is bus master in i\T
mode. BALE connects directly to the i\T -bus.
Di\CK(2)
Di\CK(l)
Di\CK(O)
DMA
I
i\cknowledge
144
145
146
When the 86C05 asserts one of the DRQ lines
thecorresponding, active low, DMA
acknowledge is returned from the DMA subsystem. This signal indicates the 86C05 now
has priority to use the i\T bus. For i\T bus operation the 86C05 asserts the -MASTER signal
and waits 10 clocks or 20 clocks (register 5, bit
4) before asserting an i\T bus control signal.
These pins connect directly to the i\T bus.
DRQ(2)
DRQ(l)
DRQ(O)
DMA
Request
0
139
141
142
These trl-state outputs are used to request
ownership of the i\T bus. These signals are
high true. The 86C05 asserts one of these lines
then waits for the corresponding Di\CK to be
returned from the system board. These pins
connect directly to the i\T bus.
Host
0
15
When this totem pole signal is asserted the
86C05 is the current owner of the i\T bus.
I/O
151
This active low totem pole signal is used to
indicate a serious error. It is asserted when the
host processor or local MPU writes a one to bit
Own
I10CHCK
I/O
Channel
Check
2-18
Table 17. Host Interface-AT Bus (continued)
Symbol
Signal
Name
I/O
Pin
Number
Function
7 of register 5. A zero written to this register
deasserts this signal. The 86C05 tenninates the
host bus transfer, with an access error, if this
signal is asserted. This pin should connect directly to the AT bus.
IOCHRDY
I/O
Channel
Ready
Input
I
148
This active high input signal lengthens a bus
cycle from its standard time when a device or
memory cannot respond quickly enough.
When IOCHRDY is low the 86C05 inserts
wait cycles until the device or memory brings
it high. This pin connects directly to the AT
bus.
IOCS16
I/O
Chip
Select
16 bits
I
153
When this active low input signal is asserted it
notifies the 86C05 that the addressed I/O
device is capable of transferring 16 bits of data
at once. When this signal is asserted, the internal 8 bit bus conversion logic is disabled. This
signal should be generated by the I/O device
from an address decode of the SA bits. This pin
connects directly to the AT bus.
IOCS32
I/O
Chip
Select
32 bits
I
159
When this active low input signal is asserted it
notifies the 86C05 that the addressed I/O
device is capable of transferring 32 bits of data
at once. When this signal is asserted, the internal8 bit and 16 bit bus conversion logic is disabled. This signal is generated by the I/O device from an address decode of the SA bits.
The hardware engineer should connect this pin
to VDD when using a 16 bit data bus. The
reader should note that this signal is not one of
the "standard" AT bus lines.
lORD
I/O
Read
I/O
53
This active low tri-state signal indicates when
an I/O device is to send data to the data bus.
This pin connects directly to the AT bus.
2-19
Table 17. Host Interface-AT Bus (continued)
Symbol
IOWR
Signal
Name
I/O
I/O
Pin
Number
I/O
52
This active low tri-state signal indicates when
an I/O device is to accept data from the data
bus. This pin connects directly to the AT bus.
I/O
129
130
132
These active low open collector signals are
used to infonn a system or concurrent
completion of a task. The 86C05 can also processor of the monitor these signals and interrupts the local MPU when one or more lines
become active (register 23). The 86C05 drives
these lines by setting the corresponding bit in
register 18. The system or concurrent processor·
clears the interrupt by writing the I/O register
indicated below:
Write
IRQ(2)
IRQ(l)
IRQ(O)
Interrupt
Request
Function
Interrupt
IRQO
IRQ 1
IRQ2
yo Register
Register 8
Register 9
Register 10
If the user needs the capability to change Jnter-
rupt lines than external selection jumpers must
be added to the I/O card. For example, 86C05
pin IRQO could be jumper selectable to AT bus
interrupts IRQ(3--7). These signals are internally pulled high (400 Jla). These pins connect
to the AT bus thru a 74LS04 driver.
LA17
LA18
LA19
Latchable
Address
LA20
LA21
LA22
LA23
MADE24
Memory
Address
Enable
24
o
158
155
138
I/O
76
77
78
79
I/O
13
These active high tri-state signals are latchable
address bits which are used to decode zero or
one wait state memory. They are valid through
out the memoryaccess cycle and connect to the .
AT bus thru an LS245 bus transceiver.
This active high tri-state signal indicates when
an extended (address bits 24 -31) address is
used on the AT bus. When this signal is Iowa
32 bit memory address is placed on the bus.
When this signal is high a 24 bit address is on
2-20
Table 17. Host Interface-AT Bus (continued)
Symbol
Signal
Name
I/O
Pin
Number
Function
the bus. When the fmnware engineer requests
32 bit transfers, the additional 8 bits must be
provided external to the 86C05. The reader
should note that this signal is not one of the
"standard" AT bus control lines.
MASTER
Master
o
29
This active low output signal indicates that the
86C05 is controlling the AT bus. It is asserted
when the DRQO, DRQ1, or DRQ2 is active
and the corresponding -DACK signal is received. This pin connects directly to the AT
bus.
:MEMCS16
Memory
Chip
Select
I
156
This active low input signal notifies the 86C05
that the addressed memory is capable 16 bits
transferring 16 bits of data at once. Asserting
this signal prevents the 16 bit to 8 bit bus conversion logic from being activated. This pin
connects directly to the AT bus.
:MEMCS32
Memory
Chip
Select
32 bits
I
152
This active low input signal notifies the 86C05
that the addressed memory is capable of
transferring 32 bits of data at once. Asserting
this signal prevents the 16 bit to 8 bit bus conversion logic and the 32 bit to 16 bit bus conversion logic from being activated. The hardware engineer should tie this input to VDD
volts when using a 16 bit data bus. The reader
should note that this signal is not one of the
"standard" AT interface lines.
:MEMR
Memory
Read
I/O
149
This active low tri-state signal indicates read
memory cycle. This pin connects directly to
the AT bus.
MEMW
Memory
Write
I/O
This active low tri-state signal indicates a
memory write cycle. This pin connects directly
to the AT bus.
28
2-21
Table 17. Host Interface-AT Bus (continued)
I/O
Symbol
Signal
Name
SA(0-2)
SA(3-7)
SA(8-14)
SA(15-19)
System
Address
I/O
48-50
55-59
61-67
71-75
These active high tri-state signals address
memory or I/O devices within the system.
They fonn the low-order 20 bits of the 24 bit
address bus. These lines are latched on the bus
when BALE goes from a high to low state.
These pins are connected to the AT bus thru an
LS245 bus transceiver.
SBHE
System
Byte
High
Enable
o
69
This active low tri-state signal enables the
transfer of data on byte 1 (bits 8-15) of the data
bus. It is used with AO to distinguish between
byte 0 (bits 0-7) and byte 1 (bits 8-15) transfers. This pin connects directly to the AT bus.
SD(0-4)
SD(5-14)
SD(15-20)
SD(21-30)
SD(31)
Data
Bits
I/O
45-41
40-31
26--21
10-1
160
These are active high, tri-state signals. All data
transfers between the AT bus and the MPU or
DMA interface flow through these signals.
These pins connect to the AT bus thru LS245
transceivers.
Pin
Number
Function
When the 86C05 only transfers 16 bits of data
to the bus, then D(16--31) maybe programmed
(register 5, bit 5) as an I/O port.
SWEN
System
Word
High
Enable
o
132
This active low tri-state signal enables the
transfer of data on bytes 2 and 3 (bits 16--32) of
the data bus. It is used withAl to distinguish
between word 0 (bits 0-15) and word 1 (bits
16--31) transfers. The reader should note that
this pin is not one of the "standard" AT control
signals.
RESETDRV
Bus
Reset
I
154
This active high input signal provides a hard
reset to the 86C05 chip. Intemallogic is initialized by this signal and any transfer operations
are aborted.
2-22
The 86C05 NuBus Interface consists of91 signals as outlined below. The 86C05 is configured to operate in
the NuBus host interface mode when CONFIG2 is low and the CONFIG3 pin is low. The following abbreviations are used:
I/O
I
0
TS
DC
1P
=Input and Output Pin
=Input Pin Only
=Output Pin Only
=Tri-state Pin
=Open Collector Pin
=Totem Pole Pin
Table 18. Host Interface-NuBus Bus Pin Summary
Pin(s)
Name
Number
of Signals
Input!
Output
Pin
Type
Pin
Drive(ma)
1
32
4
4
1
1
4
18
2
8
8
1
1
1
1
1
1
2
I/O
I/O
I
0
I
0
I
0
I/O
I
0
I
0
I/O
0
I/O
0
I/O
TS
TS
24
4
1P
4
TS
8
1P
DC
4
4
1P
4
1P
1P
1P
TS
TS
TS
4
24
24
24
24
24
ACK
AD(0-31)
ARB_IN(0-3)
ARB_OUT(0-3)
CLK
HOST_OWN
ID(0-3)
NA(0-17)
NMRQ(0-2)
PI(0-7)
PO(0-7)
RESET
RSLOCK
RQST
SLOT
START
SSLOT
TM(O-l)
Table 19. Host Interface-NuBus Bus
Symbol
Signal
Name
ACK
Ack
I/O
I/O
Pin
Number
Function
This active low tri-state signal indicates the
slave has completed the read or write request.
During a read operation data is valid when this
signal is low. Data is clocked into the bus master on the high to low transition of the CLK.
For a write operation the data must be held
throughout the Acknowledge cycle. This pin
connects directly to the NuB us.
13
2-23
Table 19. Host Interface-NuBus Bus (continued)
Symbol
Signal
Name
AD (0--4)
AD(5-14)
AD(15-20)
AD(21-30)
Address/
Data
I/O
45-41
40-31
26-21
10-1
160
These active high tri-state signals are the multiplexed address and data bus. During the Start
cycle of a transaction these lines contain the
address of the slave. For a write transaction
these signals then carry the write data until the
beginning of the next Start cycle. For a read
transaction these signals are unknown until the
Acknowledge cycle, at which time they hold
the data from the slave. These lines connect to
the NuBus thru a ALS640 bus transceiver.
Arb
I
143
These active low input pins connect directly to
the NuBus and receive arbitration bus priority
levels.
I/O
AD(31)
ARB_IN(3)
ARB_IN(2)
ARB_IN(1)
ARB_IN(O)
Pin
Number
Bus
Priority
144
In
146
ARB_OUT(3)
ARB_OUT(2)
ARB_OUT(l)
ARB_OUT(O)
Bus
Priority
Out
CLK
Clock
Arb
145
Function
°
138
139
141
142
These active low totem pole output signals are
used topresent arbitrating bus participant
priority levels. The priority level of the 86C05
is programmed into register 5. These pins are
connected to the NuBus by paralleling LS240s
inverters. That is, connect the respective
-ARB_OUT pin to the OE pin of the LS245.
Tie the inputs to the four inverters to ground
and connect the outputs from the inverters, in
parallel, to the NuBus. Each of the four
ARB_OUT lines should be connected in this
manner. This type of connection is required to
achieve the 60 rna drive current required for
NuBus.
I
152
This input clock line is used to synchronize all
NuBus address, data, control, and arbitration
signals. It has a period of 1()() ns and a duty
cycle of 75% high and 25% low. The low to
high transition of this signal is called the driving edge and the high to low transition is called
the sampling edge. This pin connects directly
to the NuBus.
2-24
Table 19. Host Interface-~uBus Bus (continued)
Symbol
-ID(3)
-ID(2)
Function
Signal
Name
I/O
Pin
Number
Host
o
15
When this totem pole signal is asserted the
86C05 is the current owner of the NuB us.
ID
I
134
135
136
137
These active low inputs signals produce a
hexidecimal ID digit between the value Oh and
Ph. Each card slot in the NuBus backplane has
its own unique ID. This ID is used for arbitration and also defmes the card's memory or I/O
space. These pins connect directly to the
NuBus.
Bits
ID(1)
-ID(O)
NA(0-2)
NA(3-7)
NA(8-14)
NA(15-17)
NuBus
Latched
Address
o
48-50
55-59
61-67
71-73
These active high output lines are the latched
address for the current NuBus transaction.
These lines typically connect to a BIOS PROM
and/or other I/O card logic.
NMRQ(2)
NonMaster
Request
I/O
129
130
133
These active low open collector signals are
used to indicate a non-master device request
interrupt processing. The 86C05 can also
monitor these signals and generate an interrupt
to the local MPU when they are active (register
23). One of these lines connect to the Apple
NuBus thru a driver.
Port
I
155
156
153
154
149
159
157
158
These active high input signals are read by the
MPU or Host processor as register 7. These
signals are unlatched and therefore could be
changing asynchronously with respect to the
processor.
o
74-79
69
132
These active high totem pole output signals are
set or cleared when the MPU or host processor
writes to register 7.
NMRQ(I)
NMRQ(O)
PI(7)
PI(6)
PI(5)
PI(4)
PI(3)
PI(2)
PI(I)
PI(O)
PO (0-5)
PO(6)
PO(7)
In
Port
Out
2-25
Table 19. Host Interface-NuBus Bus (continued)
Symbol
Signal
Name
I/O
Pin
Number
RESET
Bus
Reset
I
154
This active low input signal provides a hard
reset to the 86C05 chip. Intemallogic is initialized by this signal and any transfer operations
are aborted. This pin connects directly to the
NuBus.
Resource
Lock
°
46
When this active high totem pole signal is ,
assertedthe 86C05 has detected a NuBus resource lock cycle.
RQST
Request
I/O
29
This active low tri-state signal is asserted when
a bus master wants to use the NuBus. It may
only be asserted if it was not active on the previous cycle. When this signal is asserted the ARB_IN(0--3) andARB_OUT (0--3) lines
detennine which of the arbitrating slots will
become the next bus master. Once asserted,
this signal stays active until the 86C05 becomes bus master. This pin is connected to the
NuBus by paralleling LS240s inverters. That
is, connect this pin to the -OE pin of the _
LS245. Tie the inputs to the four inverters to
ground and connect the outputs from the inverters, in parallel, to the NuB us. This type of
connection is required to achieve the 60 rna
drive current required for NuBus.
SLOT
Slot
Space
Accessed
°
28
When this active high totem pole signal is
asserted, the 86C05 has detected an access to
this cards slot space.
START
Start
I/O
12
This active low tri-state signal is asserted to
indicate the address cycle of a NuBus transaction. It also initiates an arbitration contest. This
pin connects directly to the NuBus.
RSLOCK
2-26
Function
Table 19. Host Interface-NuBus Bus (continued)
Symbol
Signal
Name
I/O
Pin
Number
SSLOT
Super
Slot
Space
0
148
When this active high totem pole signal is
asserted, the 86C05 has detected an access to
Accessed this cards super slot space.
TM(I)
TM(O)
Transfer
Mode 0
I/O
52
53
These active low tri-state signals are used at the
beginning of a transaction to indicate the type
of transaction being initiated. Later in the
transaction the responding module uses them
to indicate success or failure of of the requested
transaction. These pins connect directly to the
NuBus.
Function
The 86C05 MPU Interface consists of 18 signals as outlined below. The following abbreviations are used:
I/O = Input and Output Pin
=Input Pin Only
o =Output Pin Only
TS =Tri-state Pin
1P =Totem Pole Pin
I
Table 20. MPU Interface-Pin Summary
Pines)
Name
MFIFO_RDY
MIORD
MIOWR
MA(0-2)
MA_D(0-7)
MALE/MA(3)
MINT
MIO_-MEM
OSC_D2/MA(4)
Number
of Signals
Input!
Output
1
1
1
3
8
1
1
1
1
0
I
I
I
I/O
I
0
I
I/O
2-27
Pin
Pin
T)1)e
Inive(ma)
1P
4
TS
4
1P
4
1P
4
Table 21. MPU Interface
Symbol
MIORD
Signal
Name
"I/O
Pin
Number
FIFO
Ready
I
127
This totem pole active high signal is asserted
when the FIFO is waiting for a new byte from
the MPU, or it has a new byte to send to the
MPU. When the MPU FIFO Buffer Register
31 is accessed, this signal is cleared. This pin is
enabled by bit 1 of register 16.
I/O Read
I
104
When the CONFIGO pin is low this active low
input signal is used by the MPU to read status
infonnation from the 86C05.
Function
When the CONFIGO pin is high, this active
low input signal is data strobe (-DS). If 10WR
is low (RI-W) when this signal is active, a
write operation to the 86C05 is initiated. If IOWR is low when this signal is active, a read
operation is initiated.
MIOWR
I/O Write
I
105
When the CONFIGO pin is low, this active low
input signal is used by the MPU to write data
to the 86C05.
When the CONFIG 1 pin is high, this signal
determines whether the MPU wants to perfonn
a read operation (-lORD high) or write operation (-lORD low) from/to the 86C05.
OSC_D2/MA(4)
MALE/MA(3)
MA(2)
MA(1)
MA(O)
Address
Bit 3
I
118
103
123
124
125
When the CONFIG 1 signal is low, these active
high signals provide address bits 0-4 respectfully. This is used for internal register selection.
The reader should note that MA(3) is the
MALE pin and MA(4) is the OSC_D2 pin.
This implies the OSC_D2 pin is not available
when a non- multiplexed bus is specified.
When the CONFIG 1 pin is low bits MA(0-2)
are used for address comparison with de-multiplexed address bits 5, 6, and 7 respectfully.
When a comparison is made an internal chip
select is generated.
2-28
Table 21. MPU Interface (continued)
Symbol
Signal
Name
I/O
Address/
Data Bus
I/O
MDO-MD7
Data Bus
I/O
MALE/MA(3)
Address
Latch
Enable
I
Pin
Number
115-111
109-107
Function
These are active high, tri-state signals. When
the CONFIGO pin is high, these address/data
lines intetface with the MPU lower 8-bit address/data bus. The addresses are latched into
the internal address register by the deasserting
edge of MALE. If the address is within the
range of the internal chip select, A(0-2), the8bit data is written/read to/from a 86C05 register depending on the I/O write or I/O read input
control lines.
When CONFIG 1 pin is pulled low these lines
carry only data.
103
When the CONFIGO pin is low, this active
high input strobe is for latching the address
from the multiplexed MA_D(0-7) (Address/
Data) bus. The address is latched into an internal address register on the high to low transition of this signal. The latched address bits are
used for internal chip and register selection.
When the CONFIGO pin is high this active low
input strobe is for latching the address from the
MA_D(0-7) bus. The address is latched into an
internal address register on the low to high
transition of this signal.
When the CONFIG 1 pin is low this input provides bit 3 of the demultiplexed address bus.
MINT
MPU
Interrupt
128
2-29
The active polarity of this signal is determined
by bit 0 of register 16. This signal is asserted
when an interrupt condition is present and the
mask bit for that condition is a one (see register
23). For latched bits, the MPU interrupt is
cleared when the MPU reads Interrupt Status
Register 23. For unlatched bits, it is cleared
when the pass-through interrupt condition disappears.
Table 21. MPU Interface (continued)
Symbol
Signal
Name
I/O or
Memory
I/O
Pin
Number
I
106
Function
When CONFIGO pin is low this high true input
signal enables I/O read and I/O write signals.
When this signal is low, 86C05 MPU access is
disabled.
When CONFIGO pin is high this low true
(-DM) Data Memory signal is used to enable
data strobe (-lORD signal). If this signal is
high data strobe is disabled.
The 86C05 DMA Interface consists of 20 signals as outlined below. The following abbreviations are used:
I/O
=Input and Output Pin
I
=
Input Pin Only
o = Output Pin Only
TS =Tri-state Pin
1P =Totem Pole Pin
Table 22. DMA Interface-Pin Summary
Pin(s)
Name
Number
of Signals
DDO(0-7)
DDl(0-7)
DMA_ACK
DMA_REQ
8
8
1
1
1
1
DP(O)IRD
DP(1)IWRT
Input!
Pin
Pin
Outpu~
Type
Drive(ma)
I/O
I/O
I
0
I/O
I/O
TS
TS
4
4
4
4
4
4
1P
1P
TS
TS
Table 23. DMA Interface
Symbol
DDO(0-7)
DD 1(0-7)
Signal
Name
DMA
Data
I/O
Pin
Function
Number
I/O
99-92
89-82
2-30
These active high, tri-state signals pass 8 or 16
bits of data to/from the internal FIFO and the
DMA interface. The DMA interface could be
connected to an intelligent peripheral chip
(86C05 is a DMA controller) or to a DMA
controller (86C05 is a DMA device).
Table 23. DMA Interface (continued)
Symbol
Signal
Name'
I/O
DMA
I
Acknowledge
Pin
Number
102
Function
The active polarity of this signal is set by register 21, bit 6. When the DMA Interface is programmed to operate as a DMA device, this
signal is an acknowledge (in response to
DMA_REQ being asserted) from the external
DMA controller or device. It indicates the
86COS may now transfer data between the
FIFO and the DMA Interface.
When operating as a DMA controller, this signal indicates the peripheral device is requesting
a data transfer.
DMA
Request
o
100
The active polarity of this signal is set by register 21,bit S. When the DMA Interface is programmed to operate as an DMA device, this
signal is a request to transfer data to/from the
86COS and the external DMA controller or
device. It maybe asserted in level or edge mode
(register 21, bit 4) when acting as a DMA
device.
When operating as a DMA controller, the
86COS waits until the DMA_ACK signal is
asserted and there is data to transfer to/from the
FIFO. It then asserts this signal and transfers
the data as specified (write or read) by the data
flow bits (register 22, bits 0-2).
DP(l)!WRT
DP(O)IRD
DMA
Parity
I/O
These active high, tri-state signals provide
parity for the DMA interface. DPOIRD is the
parity bit for DD(0-7) and DP1/WRT is the
parity bit for DD(8-1S). Parity is check!
generated at the DMA interface.
81
90
When the DMA interface is functioning as a
DMA controller these bits may be programmed to function as the 8237 -RD and
-WRT strobes. See register 21 for more details.
2-31
The Utility Interlace consists of 24 signals as outlined below. The following abbreviations are used:
I/O = Input and Output Pin
I =Input Pin Only
o =Output Pin Only
TS =Tri-state Pin
1P =Totem Pole Pin
Table 24. Utility Interface-Pin Summary
Pines)
Name
Number
of Signals
Input!
Output
4
I
I
I/O
I
0
0
I
CONFIG(0-3)
GND
OSC_D2/MA(4)
OSC_IN
OSC_OUT
RESET_OUT
VCC
12
1
1
1
1
4
Pin
Pin
T)1)e
l)cive(ma)
1P
4
1P
4
Table 25. Utility Interface
Symbol
Signal
Name
I/O
Function
Pin
Number
CONFIGO
ConfigO
I
122
This line is pulled up internally and used to
select the MPU's strobe inputs. When this signal is low the 86C05 is configured for an 8085/
8051 type MPU that uses individual read and
write strobes. When this signal is left open, the
86C05 chip is configured for a Z8 type MPU
that uses separate strobe and read/write signals.
CONFIG1
Config1
I
121
When this internally pulled high input is high,
the 86C05 is configured to operate with a
multiplexed address and data MPU bus. When
this line is low, pins MA(0-4) are used to select internal registers.
CONFIG2
CONFIG3
Config2
Config3
I
I
120
119
These internally pulled high inputs specify the
host interface as outlined below:
CONFIG3
0
0
1
1
2-32
CQNFIG2
0
1
0
1
Interface
NuBus
EISA
MicroChannel
AT
Table 25. Utility Interface (continued)
Symbol
Signal
Name
GND
Ground
I/O
Pin
Number
I 110,131,147
150,11,14
27,30,51
54,70,91
Osc
o
118
Function
These inputs must all be connected to system
ground.
The clock frequency of this output pin is a divide by two of the oscillator input when the
CONFIG 1 is high.
When the CONFIG 1 pin is low this input pin is
the non-multiplexed address bus bit 4.
I
Osc
Input
Osc
Output
I
116
o
117
Reset
Out
o
126
The OSC_IN active high input pin is for a 40
l\1Hz crystal or oscillator. The OSC_OUT is
for a crystal connection.
This totem pole output is nonnally used to
reset I/O card logic. It is an "or" of the following signals:
a Host Reset pin
b. Power on reset
c. Write to register 4 bit 2(fmnware reset)
Prior to a firmware reset this pin can be disabled by asserting bit 7 of register 16.
VDD
Power
I
101,140
20,60
2-33
These input pins must connect
to I/O card power
Chapter 3
D.C. Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
3.3 D.C. VALUES
• Voltage on all pins with respect to GND range
from -0.3 to 7.0 Vdc.
Parameter
• Ambient operating temperature is ooe to
+70 o e.
• Storage temperature is from -65°e to +150o e.
Note that stresses greater than those indicated
may cause permanent damage. Operation of the
chip at conditions above those shown is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect the
chip's reliability.
Min
Max
Unit
2
Input High Voltage
-0.3
Input Low Voltage
2
Output High Voltage
Output Low Voltage
-30
Input Leakage
Output Leakage
vee Supply Current
vee
0.8
vee
0.4
10
10
50
v
V
V
V
/lA
/lA
rnA
3.4 DRIVERSIRECEIVERS
• Drivers
Sink 24 rnA @ 0.4 Vdc asserted
• Receivers Asserted at input = 0 to 0.8 Vdc
Non-asserted at input = 2.0 to
5.25 Vdc
Minimum hysteresis = 0.2 Vdc
3.2 STANDARD TEST CONDITIONS
The characteristics shown below apply for the
following test conditions, unless otherwise
noted. Voltages are referenced to GND. Positive
current flows into the reference pin. Standard
conditions are as follows:
• vee = 5.0 Vdc +/- 0.25 Vdc.
• GND =OVdc
3-1
PIN NAME
PIN NAME
(I)
CONFIG8
(Il
CONFIG8
IIJ
CONFIGI
(I)
CONFIGI
III
MID_MEM
110_-MeM)
II)
MID_MEM
Ii o_-MeM)
(1)
MIORO
I-iord)
III
MIOWA
(-lowr)
IIJ
J
'--
(Il
MIORO
(-iord)
(Il
MIOWA
(-lowr)
([)
MALE
(elel
T2
MALE
leI e)
J
{
'-}
T1
T7
II I
NAME
T1
T2
T3
T4
T5
T6
T7
MA_DI8-71
lIlo) MA_D [8-71
PARAMETER
MIN.
I-lowr) low pulse width
lole) low to (-iowr) low
(ole) high pulse width
Address setup to lolel low
Address hold frOM lalel low
Ooto se1up lo (-iowr) high
Dolo hold aFter (-iowr) high
TYP.
MAX.
68
25
28
15
15
38
15
UNIT
NAME
ns
ns
ns
ns
ns
ns
ns
Tl
T2
T3
Ttl
T5
T6
PRRAMETER
(-iordl low pulse width
lole) high pulse width
Address setup 10 lole) low
Address hold FrOM lole) low
Data valid frOM (-iord) low
DO 10 f'l 00 1 FrOM I-iord) high
Figure 11-2.
Figure 11-1.
MPU Write Operation 8885/8B51 Mode
TiMing Characteristics
MIN.
TYP.
MRX.
68
28
15
15
58
28
MPU Reod Operation 8085/8051 Mode
TIMing Characteristics
UNIT
ns
ns
ns
ns
ns
ns
PIN NAME
PIN NAME
II )
CONFIG8
(II
CONFIGO
I I)
CONFIGI
II)
CONFIGI
II)
MID_MEM
(-dM)
II)
MID_HEM
(-dM)
!I)
MIORD
I-de)
III
MIOWA
(r-w)
III
MALE
I-as)
III
MA_010-71
NAME
Tl
T2
T3
T4
T5
T6
\
\
J
~
~
(Il
MIORO
I-del
(II
MlmO/A
Ir-w)
II)
MALE
(-os)
11/0)
PARAMETER
MIN.
(-de) low pulse width
(-asl low pulse width
(-os) high to (-ds) low
Rddress setup to (-as) high
Address hold frOM (-as) low
Doto setup to (-ds) high
Figure 11-3.
Tl
r
TYP.
MRX.
S8
20
25
15
15
30
MPU Write Operotton ZB Mode
TIMing Characteristics
UNIT
ns
ns
ns
ns
ns
ns
NAME
Tl
T2
T3
H
T5
T5
TS
\
y
\
T1
r
I
'{
MA_O [8-71
PARAMETER
MIN.
I-ds) low pulse width
I-as) low pulse width
Address setup to I-os) high
Address hold frOM (-os) high
Oato valid frOM (-ds) low
Ooto volid frOM (-ds) low
Ooto floot frOM (-ds) high
Figure ll-ll.
TYP.
MRX.
S8
28
15
15
58
50
20
HPU Read Operotion ZB Hade
T1Ming Chorocter1stics
UNIT
ns
ns
ns
ns
ns
ns
ns
PIN NAME
PIN NAHE
II)
CONFIG1
(ll
MIO_HEH
(I)
=x
MAUl-ill
(I)
,
VALID ADDRESS
Tl
(l)
x=
see note 1
110 strobe
(see no te 2)
..
II
(OJ
T6
MA_DHI-71
reed operetlon
NAHE
Tl
T2
T3
Til
T5
T6
T7
PARAMETER
Velid eddress to lID strobe
low
lID slrobe low pulse width
Address hold frOM 1/0 strobe
high
Write data set-up to I/O
strobe high
Write dete hold F'rol'l 110
strobe high
Read dolo valid FrOM 110
strobe low
Reed de to Fl oe 1 frol'l 110
strobe high
Tl
if
MIN.
1
MF I FO_RDT
3r1
PARAMETER
HIN.
J----L
TTP.
MAX.
UNIT
(
TTP.
I/O strobe low to MfIFO_RDT
low
I/O strobe signal high 10
HFIFO_ROT high
38
ns
llCP
'-
DATA
I
T7
II
DATA
MAX.
}UNIT
28
ns
60
28
ns
ns
30
ns
15
ns
Note:
1. Actual 110 strobe pin besed on polarity of CONFIG8 pin.
2. This Pigure aSSUMes on HPU 1/0 access to register 31.
3. CP is clock period (OSCI pin).
4. Register 16 bit 1 !'lust be equol to one to eneble the
MFIFO_ROY pin.
5. Status of the HPU MFIFO_RDY pin is reod frOM register
15 bit 8. This bit Is independent of the MPU HFIFO_ROT
pin being enabled (Register 16 bll 1).
Figure 4-5
58
28
Note:
1. Polority of HIO_MEM slgnel besed on CONFIGO pin.
2. Autuol I/O strobe pin bosed on polarity of CONFIG8 pin.
Figure 11-4.
T2
~
TIl
,
p eretlon
NAME
J
I
0
(0)
T2
T3
L
...,rl ta
Jt--
110 strobe
(see note 1)
HPU Non-Multiplexed Address/Dolo Bus
TIl'ling Cherocterlstlcs
ns
ns
MPU MFIFO_RDT Cycle
TiMing Characteristics
ns
PIN NAME
(Il
PIN NAME
008IEl-71.
001(8-71.
OPO/RO
OPI/WR t
(OJ
OOflIG-71.
DOIIG-7J
,
Tl
VAllO DATA
,-----
1\
f
J1"------""1
1f---tI
(0)
~i~
13
\
(I J
f------------}j
-
Tq
T5
(0)
OPO/AO
OPl/WRT
---",\.,.~t----"""""'''
'J
1\
T2
.-----~
_
(0)
T4
NAME
T1
T2
T3
T4
T5
PARAMETER
Oatc valid to OMR_RCK high
Date hold frOM OMR_ACK high
OMA_ACK low to DMA_REQ high
OMR_RCK pulse width
OMA_ACK high to OMR~EO low
MIN.
TYP.
MRX.
UNIT
25
ns
ns
ns
ns
ns
18
18
2CP
8
Figure 4-7.
OHR Interface, Device Mode Transfer to
86C85 frOM OMA TIMing Characteristics
\~
(ll
NAME
T1
T2
Note:
1. See registers 16 and 21 for DMA configuration.
2. Device Mode set when register 21 bit 3 1s zero.
3. This figure aSSUMes OMA_ACK end OMA_REO ere low true.
II. CP is the clock period of the DSCI pin.
5. The 86C8S brings DMA_REQ high only efter DMA_ACK is
received end the chip i8 in edge Mode or the transfer
counter is equal to zero.
6. ParaMeter T5 is valid only for edge Mode, 1.e. when
register 21 bl ts 3 and II ere equal to zero.
VRLl 0 DATA
13
TIl
T5
T6
,
'Jo-----
~
~
Ij---------~--~
'
T5
J
\'----_-.1
PRRRMETER
Data velid frOM OHA_ACK low
Parity valid frOM OMA_ACK low
Bus float frOM DMA_ACK high
OMR_RCK low to OMR_REC high
DMR_RCK pulse width
OMA_ACK high to DMA.-REa low
HIN.
TYP.
MRX.
UNIT
28
35
ns
ns
ns
ns
ns
ns
2fl
25
2CP
0
Note:
1. See registers 16 and 21 for DMA configuration.
2. Device Mode set when register 21 bit 3 is zero.
3. This figure aSSUMes OMA_ACK and OMA_REa are low true.
4. CP Is the clock period of the D5CI pin.
5. The 86C05 brings OMA_REa high only after OMA_ACK is
received and the chip is In edge Mode or the transfer
counter Is equal to zero.
6. ParaMeter T6 Is valid only for edge Mode, I.e. when
regisler 21 bits 3 and 4 are equal to zero.
Figure 4-8.
OHA Interface. Device Mode Transfer frOM
86C05 to OMA TiMing Characteristics
,
PIN NAME
PIN NRHE
III
(01
DDEl(8-7).
DOl (B-7)
DOEl[El-7).
001 [0-7)
\~
Tl
III
(-req
DHR RCK
\.
Fro" devleel
1
(01
~~---.~-~;--}--------
Tl
T2
T3
PARAHETER
Dela velld to (-ack) high
Deta hold frOM (-eck) high
(-req) high to (-ack) high
(see note 6)
\~
MIN.
TYP.
MAX.
UNIT
lEl
IEl
CP+-28
OHA Interface, Controller Hade (wi th pori tyl
TransFer to 86C85 frOM DHA TiMing Characlerislics
ns
ns
ns
.,
VALID DATA
.t"
T3
f'r-Tll---:-----J
T2
I.
OHR RCK ~
(-req fro~ device)
~
Note:
1. See registers 16 and 21 for OHA interface configurotion.
2. Controller ~ode set when register 21 bit 3 is one.
3. The width of the (-ack) pulse is set by regisler
21 bits El, 1, end 2.
ll. This figure assu~es OMA_ACK and DMA_RED are low true.
5. CP is Lhe clock period of the aSCI pin.
6. The device Must deessert its (-reqJ within para~eter T3
tiMe to ensure the 86CaS stops DHA transfer. PoraMeter
T3 Is extended if the ock hold-off bit is true
(register 21. bit ij). This extension oppl1es to within
T3 tiMe of the end of the hold off period.
7. If the device continues to assert l-reql then the
86CEl5 May begin a new DHA cycle within 2CP of
(-oclo:) going high frOM the previous cycle.
Figure ij-9.
OPEl/RD
OPI/WAT
~
...J
(II
(01
DHR_RED
(-ack to devicel
NRME
(01
.,
VALID DATA
1\
(01
OHR_RED
(-eck to dev ice)
NAME
Tl
T2
T3
TIl
\\-
..
"'
I
\.
PRRRMETER
Doto volid fro~ (-ockl low
Pority volid frOM (-ock) low
Bus fl oe t frOM (-ock) high
(-req) high to (-ock) high
(see no te 6)
HIN.
TYP.
MAX.
UNIT
2El
35
ns
ns
ns
ne
20
CP+2El
Note:
1. See registers 16 ond 21 for OMA interface configuration.
2. Conlroller ~ode sel when register 21 bit 3 is one.
3. The width of the (-ack) pulse is set by register
21 bits O. 1. and 2.
lJ. This figure assu~es (-req) ond (-eck) ere low true.
S. CP is the clock period of the aSCI pin.
6. The device ~ust deassert its (-req) within paroMeter TIl
llMe to ensure the 86C85 stops OMR tronsfer. PoroMeler
TlJ is extended if the eck hold-off bi t is true
(register 21. bi t 4). This extension applies to wi thin
TlJ tiMe of the end of the hold off period.
7. If the device continues to esserl (-req) then the
86C85 May begin e new OHR cycle within 2CP of
(-ack) going high frOM the previous cycle.
Figure 4-1El.
DMA Inlerface. Conlroller Mode (wi th pori tyl
Transfer frOM 86C85 to OMA TiMing Cherecterislics
(I)
PIN NAHE
00IH8-7).
001(8-71
PIN NRME
\~
f
OHA_ACK ~
(-req frOM devicel
~
\~
OHA_AED
(-eck La device)
,
TIl
(OJ
(0)
OPO/AO
(-rd s lbl
T1
T2
T3
Tit
T5
T5
\
I
(-rd stb) high
(-rd s tbl high
I-eckl high
TYP.
-MAX.
18
18
CP+28
(-rd s tb) low
2CP+18
to (-ecle I high CP-18
2CP+18
CP+18
~
J
T2
,-------------T3
I
J
J
OPO/AD
(-rd 8 tb)
(0)
OPl/WAT
I-wr t s lb)
UNIT
NAME
ns
ns
ns
T1
T2
ns
ns
TIl
OHA Interface, Controller Mode (B237 slrobesl
Trensfer to 86C85 frOM OHA TiMing Characteristics
,
VRLlO DATA
L
~~
OHA_AED
(-ocle lo dev ice)
Note:
1. See registers 16 end 21 for OHA interface configuration.
2. Controller Mode set when register 21 bit 3 is one.
3. The width of the (-eclel pulse is set by register
21 bits B. 1 • and 2 (Must be > 31.
It. This figure eSSUMes (-reql end (-eclel are low true.
5. CP is the clocle period of the OSCI pin.
6. The device Must deossert its (-req) wilhin tiMe T3
to ensure the 86C8S stops OHA trensfer. PoreMeter
T3 is extended i f the ecle hold-off bi t 1a true
(regisler 21. bil q). This extension epplles to
wi thin T3 tiMe of the end of the hold off period.
7. If the device continues to essert (-req) then lhe
86C85 Mey begin e new OHA cycle within 2CP of
I-ock) going high frOM lhe previous cycle.
Figure 11-11.
(I)
OHA ACK
I-req frOM d-;v i eel
(0)
MIN.
,
\~
(OJ
J
.
PARAMETER
Oele ve Ii d to
Dote hold frOM
(-req) high to
(see note 6)
I-acle) low to
(-rd 8 tbl high
::t
00818-7).
001(0-71
T1
\~
OPl/WRT
(-wr l s tb)
NAME
tT2
'(
\
\~
Tl
I·r---T3----------
(Il
(0)
(OJ
VALID DATA
13
TS
PAAAMETER
\~,
"1
\~
Ts
TI!
\',
If-
I
\
HIN.
(-acle) low 10 valid data
De to fl 00 t frOM I-ack) high
CP+2B
I-req) high to (-ocle) high
(see no te 6)
(-aclel low to (-wr t s tbl low 2CP-18
(-wrt stb) high to (-acle) high CP-lB
TYP.
MAX.
UNIT
28
n9
ns
ns
2CP+lG
CP+HI
ns
ns
28
Note:
1. See registers 16 end 21 for OHA interface configuration.
2. Controller Mode set when register 21 bit 3 is one.
3. The width of lhe (-ecle I pulse is set by register
21 bits B. 1. and 2 IMus t be > 31.
4. This figure aSSUMes (-req) and (-ock) are low lrue.
s. CP is the clock period of the OSCI pin.
S. The device Must deossert 1 ts (-req) within ti Me T3
to ensure the BSCBS slops OHA transfer. ParaMeter
T3 is extended if the (-eck) hold-off bi t is lrue
(regisler 21. bi t q) . This exlension applies to
within T3 ti Me of lhe end of the hold off period.
7. If lhe device continues to assert (-reql lhen the
the 86C8S May begin a new OMA cycle within 2CP of
(-oclel going high frOM the previous cycle.
Figure tt-l2.
OHA Inlerface. Controller Mode (8237 strobes)
Transfer to OMA frOM 86CBs TiMing Characteristics
PIN NAME
PIN NAME
Tl
(OJ
HOOEIE)J
(0)
HOOE [1-21
(I) D32_H32_CLK
(/clk)
--+-~I-
- - - - - _\\- - - - - (see no 1e
1)
~,.----
(01
HOOEIB-21
T2
(0)
HROE
(01
HOOIR
T3
(0)
(see no te 2)
HOOIR
(see note 11
----~~------\\---------____________T_3,.
~
(0)
-
\
(0)
HAOIR
IOJ
HOST_OWN
NAME
T1
T2
T3
n
NAME
Tl
T2
T3
PRRRMETER
HOOEI0-2J and HAOE deasserl
pulse widlh
HDOEIO-21 end HAOE high 10
HDOIR end HADIR high
HAOE high to HADIR low.
HOOIR low. and HOST_OWN high
MIN.
TYP.
MAX.
UNIT
2CP
ns
CP
ns
CP
ns
Note:
1. HDOEII-21 are asserted for 16 and/or 32 bit transfers.
2. HDDIR Is high for 86C85 to host dete transFer.
3. CP i8 1he clock period of the OSCI pin.
ij. HOOEIO-21. HAOE. end HOST_OWN pins ere low true signels.
Figure 4-13.
Host Transceivers. HicroChonnel. EISA. end AT
TiMing Cherocteristics
MIN.
PARAMETER
(-elk)
(-c 1kJ
(-clkl
(-c lk)
high
high
high
high
to
to
to
to
TYP.
HOOIR high
HOST_OWN low
HOOIR low
HOST_OWN high
Nole:
1. HDOIR is high for 0 86C05 to host doto transfer
or 86C05 NuBus stort cycle.
2. CP is the clock period of the aSCI pin.
3. HOOEle-21 and HOST_OWN pins ore low true slgnols.
Figure 1I-1ij.
Hosl Transceivers. NuBus
TiMing Charecteris1ics
MAX.
UNIT
21
24
22
20
ns
ns
ns
ns
PIN NAME
(11
110 strobe
TI) ,
(see note
J
\~
T2-1
r
(OJ
(OJ
(OJ
NAME
T1
T2
T3
HDOEI3!
(-prol'loe)
~
..
II
....
HDDE(B!
HDDIR
,
1)
'(
T3
''II.
(~~e no te 2)
~
\
-------\\0---------
J
PARRMETER
MIN.
TlP.
110 strobe low to (-prOl'loe)
low. ond HDDIR high
110 strobe high to (-prol'loe)
high
110 strobe high to HDDIR
low
Note:
1. 110 strobe pulse based on host interfoce:
o. MicroChonnel or EISA --> -CMO
b. AT --> -lORD or -IOWR
b. NuBus --> trai11ng edge of -STAAT to trai11ng
edge of B6CBS -RCK cycle.
2. HDOIA Is high for host bus reod cycle.
3. HODE!S! ond HDOE(3! are low true s1gnals.
Figure 4-15.
J
BIOS PROM Recess Cycle
TiMing Characteristics
MRX.
UNIT
27
ns
22
ns
28
ns
PIN NAME
(01
COl
NAME
S81 I OADITM8.
Sl/(OWRITHI
(-aG. -all
AOL/ALE/STA
(-od })
HAIB-231
HIO/SWEN/P07
M2VACK
(odd. M/-lo. Mod241
(01
SHEN/P06
(-sbhel
BE/BEIIO [8-31
(-be[Q-3JI
Tl3
(Il
D32/M32/CLK
OI6/II6/PIS
(-cd ds 161321
1111
(Il
OBKIIL17/PI8
(-cd sf"dbk 1
T15
(01
T16
T23
I-CMd to -cMdl
T23A
CMO/MEMW/SL
(-cMdl
T17
(OJ
HOI8-3J
(wd te do tal
T20
(ll
HO[B-3J
(read dotol
MIN.
TYP.
MAX.
T1
(0)
(01
PARAMETER
T19
Note:
1. CP Is the clock period of the OSC( pin.
2. Defoult pulse width of (-cl'ldl is prgroMMoble In register 18.
Figure 4-16.
(-aD, -all low true frOM (odd,
M/-io, Mod2111 volid
(-cMdl low true frOM (-s8. -511
ItCP-H)
T2
low true
T3
(-odll low true frOM (odd,
2CP
1'1/-10, Mod241 low true
TIt
(-ad)) low true to (-cMdl
2CP-IEl
low true
T5
(-odll low true fro", (-s8, -sll
2CP-18
low true
T6
(-odll pulse wIdth
2CP-IO
T7
(-sB, -sll hold frOM (-odll high 2CP-IO
T8
(odd, M/-lo, Mod2ltl and (-sbhel
2CP-18
hold frOM (-odl) high
T9
(odd, M/-lo, Mod21!) and (-sbhel
2CP-H)
ho 1d frOM (-cMdl low true
TH)
(-50. -511 hold frOM (-cMd) low
2CP-18
Til
(-sbhel setup to (-ad)) high
2CP-IEl
2CP-H)
T12
(-sbhel setup to (-cMdl low
T 13
(-cd ds 16/321 low frOM (oddl
vol id
TIll
(-cd sfdbkl low frOM (odd) volid
TIS
(-cMdl low frOM (oddl vol id
ItCP-IEl
TIG
(-cMdl pulse width
ItCP-IS
T 17
(wr 1 te do to) se tup to (-cMdl low
B
T18
(wri te dotal hold frOM (-cMdl
2CP-IEl
high
Tl9
(-58, -sll va 11 d to (read do to)
valid
T28
(read do to) va 11 d frOM (-cMd) low
T21
(read data) hold frOM (-cMd) high
T22
(-read do tal trl-s to te frOM (-cMdl
high
T23
(-cMd) low to next (-cMdl low
8CP-18
IICP-IEl
T23A (-cl'ldl high to next (-cMdl low
2CP-1El
T23B (-cMdl high to next (-adll
T2ll Next (-sO, -511 low frOM
2CP-IEl
(-51, -58) hIgh
T2S Nex t (-sQ, -sll low to (-cMdl high
T31
(-beI8-3Jl low frOM (oddl valid
T32
(-be [8-3 Jl I low frOM (-sbhel HA (0)
HA(l) asserted
T33
(-beI0-3Jl osserted lo (-cMdl low
IB
MicroChonnel Bus Masler
TiMing Characteristics
UNIT
ns
ns
ns
ns
ns
ns
na
ns
na
2CP~5
ns
na
na
ns
2CP+IG
ns
ns
ns
ns
ns
SCP
ns
2CP+ 10
ns
ns
ns
IH)
ns
n9
ns
ns
20
48
30
na
ns
ns
na
PIN NAME
PIN NAME
sa/IORD/THB. ~
Sill OWRITM 1
(-sB. -s1)
(0)
HA[B-231
MIO/SWEN/P07
M2IUACK
ledd, M/-io, ...ed2LJl
(0)
/
=x
(OJ
HDIB-3J
(wr 1 t8 da tel
(I)
HDIB-3J
(reed datel
(
T27...,
T26 L
NAME
PARAMETER
t
L
[
r
\
T280
T28
'\
HAI(:I-23J
MIO/SWEN/P07
M241ACK
[add. I"I/-io. l'Iod241
(01
;
VALID
TISA (-cMdl pulse width
8CP-1l:l
T26 (cd chrdyl low frOM laddl
velld
T27 (cd chrdyl low frOM (-s8. -s 11
low
T28 Icd chrdryl high frol"l (-cl'ldl
low
T2BD lread dolal valid frOM (-cl'ldl
low
HP.
~--------------
~------
\'-_----J/
Ho[(:I-3J
(wd te do tal
----------------~(~_______V_A_L_I_O_______J}_
(II
HOIEl-3J
(read do tal
-------------------~~~-V-ALI-O~}-
(II
ROllI32/Pl2
(cd chrdyl
MAX.
UNIT
NAME
ns
ns
T26
68
3(:1
ns
38
n8
T2~9S
PARAMETER
Icd chrdyl
valid
T27 Icd chrdyl
low
T295 (read do to)
Icd chrdyl
_
_ _ __
MAX.
UNIT
low frOM ladd)
68
ns
low frOM 1-88. -s 11
38
ns
valid frOM
low
MIN.
TYP.
6CP-48
ns
ns
I
Nole:
1. CP 18 the clock period of the OSCI pin
2. Sieve Must release (cd chrdyl within T28 liMe of (-cl'ldl
going low for liMe T280 lo be valid.
Figure 4-17.
)(J(
VALID
T26kT27,'--_ _
BCP-LJ(:I
\,---
[OJ
,
I
MIN.
=x
CMO/MEMW/SL
I-cl'ldl
(OJ
}-
VALID
,
ROl'/I32/PI2
Icd chrdy)
(II
T1SA
{
CHo/MEMW/SL
(-cl"ldl
(0)
0
VALID
SGIIOROITMEI. ~
/
SllIOWR/TMI
\ "'-_ _ _ _ _ _ _ _.....J
(-88. -81 I
(OJ
MlcroChennel Bus Moster Synchronous Extended
Cycle TiMing Characlerislics
Nole:
1. CP is the clock period of the OSCI pin
2. Asynchrounous extended cycle occurs when lhe slave releases
(cd chrdyl asynchronous I y wi lh repec t to (-cMd).
Figure 4-18.
MicroChonnel Bus Mosler Asynchronous Exlended
Cycle TiMing Characteristics
PIN NAME
PIN NAME
(0)
sa/IORD/THe.
511l0WA/TMI
(-se. -all
(01
PHT IM5T IADT
(-preeMp 1)
(01
BAT _I DAY_55
(-busr tl
(I)
AG/IOAY/5S
(orb/-gn tl
ARB/DRD/ARBII:l-31
(orb_au t I B-31 I
(orb_in(B-311
NAME
(II
(01
HAI(3-231
MIO/SWEN/P07
M21l1Acf~
(add. 1'1/-10.
Me
I
______________-J;;
T45
l
~---------
~VALID
VAllO
______________
-J ~_____~----------
PARAMETER
TliB
T1l2
HRESET
Ich rese 1)
MIN.
(-preeMp tl low La end of xfer
(-preeMptl high frOM (orb/-gntl
low
T42A (-preeMpU high La (-sB. -511
2B
high (exiting inactive sLetel
TLl3
(-busrtJ low frOM (arb/-gnU
low
Tllll
(arb/-gnU high pulae width
lBB
TllS Driver turn-on/off delay frOM
(arb/-gn tJ low
TliS Driver turn-on/off delay frOM
low/hlgher priorIty lIne
TllB Arb bus stable before
Ie
(arb/-gn tl low
T49 Tr i-6 La te dr 1 vera to (arbl high
TYP.
MAX.
(II
MIO/5WEN/P07
(M-10J
(II
sel I OROITHB
(-s8)
CII
Sl/IOWAITMl
(-sll
II)
AOllALE/STR
(-odll
UNIT
(aee no te II
58
(Il
SET/HIS/PIG
(-cd se lupl
(I)
CMD/MEMW_SL
(-cnd)
n8
"
IHI
ns
LIB
na
ns
liB
ns
ns
llB
NAME
TSB
TSI
TS2
na
NoLe:
1. The MOX tiMe lhe B6CBS slays on lhe HicroChannel afler
(-preeMp tJ hos been osser ted 1 s progroMMb 1e In reg 1 s tel" 28.
/
\
TS2
T63,
PARAMETER
(ch rese tl high pulse wIdth
(-cd se lupl low lo (-adll low
(-cd se lupJ hold frOM I-odll
low
(-cd se tup) hold frOM I-CMd)
low
F1gure 11-2B.
MicroChonnel Bus ArbilraLion Cycle
Cycle TiMing Choraclerlslics
X
/
VALID
ns
TS3
Figure ll-19.
X
\
MIN.
/
TYP.
MAX.
UNIT
le8
IS
25
ns
ns
ns
3e
ns
HlcroChannel Configurallon Cycle
Cycle TiMing Chorocteristics
PIN NAME
(0)
(0)
(II
NAME
OBKO/AEN/P 11
(aen)
Tl
T2
T3
ARB/ORQ/ARBH)-3] .,
(drq (8-2])
....J
ARB/OCK/ARBI8-3)
(-dck (8-2])
(01
PHT IHST IR(H
(-Mas terl
II)
AOL/ALE/5TR
(bale)
(0)
HA 113-23]
TIt
~A
,
I~'------------"-
--
_--II
T12
~
~
VRLIO
T6
-II
Till
T1S
T9
T1B
~
~-q~~~T7;;;
'~
/ flr 13__
Ttl
__________:__
: :T_8
:__~1
(access strobe)
l
r
H018-31
(wri te datal
(1)
H018-31
(reod da tal
T 12 -I
r-
tt--tt
111---------1,
---------<"
,1----
VAll 0
-----------4l TI :ALfJ')o~_l_S__
TiS-
________________
101
T13
,
(access size)
(OJ
T7
T 11
__
TS
(0)
TS
T8
T9
T18
SHEN/P06
LA117-191
MIO/SWEN/P07
(add. -sbne. -swen)
(I)
TS
-
~~T~17~------
BRT/IORY/S5
(chrdyl
Figure 11-21.
T16
T17
PARAMETER
(drqIB-21l hign La (-dck 1£:)-2])
low
Bus tri-stata to drqlB-2] low
(-dckl£:)-2)} low to bus drivers on
(-dckI8-2]1 low to (-Masterl low
(access slzel reLurned frOM (addl
va lid
(odd) hold frOM (access strobel
high
(access strobel to (access
strobe)
(add) va Ii d to access s !robe
(access strobe) pulse wIdth
(access s tr'obel hIgh to nex t
(access s tr'obe) low
(access strobe) low frol'l
(-dckIB-2]) low
(wr 1 Le do to) se Lup to (access
strobel low
(wd te dotal hold frOM
(access strobel high
(reed deta) valid to (ocesss
strobe) high
(read do to) ho I d frol'l (occess
s Lrobe) high
(chrdyl low frOM unex Lended end
of (access strobel
(chrdyl h 19h to (access strobel
hIgh
MIN.
TYP.
MAX.
ns
8
2CP-IB
8
e
B
UNIT
IlCP+15
llCP+15
3CP
ns
ns
ns
ns
ICP
ns
BCP-1B
ns
llCP-1B
llCP-IEl
IlCP-1El
ns
ns
ns
IllCP
ns
B
ns
ICP
ns
2S
ns
ns
2CP
ns
SCP
ns
Nole:
1. CP Is the clock period of the OSCI pin.
2. Oefaul t pulse width of (access strobel Is prgrol'll'loble In
register 19.
3. The addressed slave Must deassert (chrdy) wIthin paraMeter T16
tiMe of the ended of the norMal transfer cycle for the 86Ce5
10 exlend the cycle. For e)(aMple. ir resgisler 19 is prograMMed
for a 250 ns (access s lrobe) then (chrdyl MUS t be deasser ted
2Be ns (CP = 25ns) af ter the 1ead 1 ng edge of the (access strobel.
II. (access strobel Is one of the following pins;
SeIlORO/TMe (-lordl.
5111 OWRITH 1 (-lowrl. CHO/HEMW/SL (-Mel'lw). or AG/HEMA/P I 3 I-MeMrl.
5. (access slzel Is one of the following pins;
ADYII32/PI2. (-10 321
0161l16/PIS (-10 161. 032/M32/CLK (-1"1 321. or SET/M1G/PIG (-1"1 lSI.
AT (lSAl Bus MosLer
Til'l1n9 Characteristics
PIN NAME
(II
Tl
~ T2
032/M32/CLK
(-c lk)
(0)
NuBus dri ver
(Il NuBus
XXX>-
--<XXX
(I)
D32/M32/CLK
(-elk)
(Il
PARAMETER
MIN.
period
width
Driver turn-on 11 Me
Driver turn-oFf' tiMe
NuBus prop delay
Set-up tiMB to I-elk) high
Hold tiMe FroM I-elk) high
(-elk)
(-elk)
Figure q-22.
TYP.
99.99
MAX.
lElEl.Ell
AOL/ALE/STR
(-start)
73
17
8
25
25
a
17
21
28
NuBus Data TransFer
TiMing Characteristics
V
/
\""'-----',
____
UNIT
ns
ns
ns
ns
ns
ns
ns
Tl
-V
~
receiver----------~X
VALID
X",,___
NAME
Tl
T2
T3
T4
T5
T6
T7
qTij~
PIN NAME
--I~
IE-J:::::ti
------~--~~
NAME
Tl
T2
T3
Tq
T5
PARAMETER
Arbitration tiMe
Arbitraton set-up tiMe
Driver turn-off' liMe
Driver turn-on tiMe
Arbitration hold tiM9
Figure Q-23.
VALID
3
T4" T
MIN.
25
lEl
lEI
TYP.
VALID
MAX.
UNIT
288
ns
ns
ns
ns
ns
3El
25
lEI
NuBus Arbitration
TiMing Characteristics
(Il
PIN NAME
032/M32/CLK
(-elk)
(OJ
HOle-3J
(wr i l8 do lol
{
ADDAESS
(JIOJ
HOle-3J
(read dolol
{
RDDRESS
(I/OJ Se/IORDITMB
SlIIOWRITMl
(- tMB. - tM 1)
(OJ
(I I
ADL/RLElSTR
(-s lor tJ
M24/RCK
(-ock)
Figure 11-211.
(
\
MODE
x::
}-
DRTR
~~
{
DRTA
}-
,\
{
STRTUS
}-
~\
~\
\
NuBus Reod/Wrile Tronsocllon
r
(ll
(0)
(OJ
PIN NRHE
D32/H32/CLK
(-c I k)
HD3 - HOt
HD8(7-61
le do to)
(
ADDRESS
(wri
x::
HD(J(S-81
{wr ils do lol
(
BLK INFO
x=::
(I/OJ se/IORD/THe
(-ll'll:H
(I/Ol 5 III OWAITM t
(-l,,11 )
(01
(I)
ADL/ALEISTA
(-slortl
H21!/ACK
(-ack)
I
\
\
\\
\~
r\
\\
Figure 4-25.
DATA
DRTA
\
/
c:
c:
r\
\\
DATA
)-
DATA
)-
'( STAT
CODE
)-
'( STRT
CODE
)-
\\
\\
NuBus Block Write Transaction
\
r
(I)
PIN NRME
D32/M321CLK
(-cl Ie)
(OJ
HD3 - HDl
HD8!7-S)
(read do to)
(
RDDRESS
}--i\
(
DATA
}--i\
(
DATA
)-
(0)
HDO(S-())
(rSeid de to)
(
BLK INFO
}--i\
(
DATR
}--i\
(
DATA
)-
(1/01
S()/IOAD/TM()
(-tI'lBl
I
\\
(1101
SllIDWR/TMl
(- tl'll I
I
S\
~\
(0)
ADL/ALE/STA
(-stortI
r\
~\
\\
~\
(ll
M21l1ACK
(-aele)
\
Figure 4-27.
\
r\
NuBus Block Aeed Transacllon
'(
STAT CODE
)-
'(
STRT CODE
)-
\
r
86C05 Pinout
~m~~~~~~~~~~~~~~;~~~~~~~~~~~~~g~~~~~~~~N
~~-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
H03(6)
H03(5)
H03(4)
H03(3)
H03(2)
H03(l)
H03(0)
H02(7)
H02(6)
H02(5)
VSS5
AOL_ALE_STR
M24_ACK
GND6
HOST_O\NN
HOOE(2)
HOOE(1)
HOOE(O)
HDOIR
VOD3
H02(4)
H02(3)
H02(2)
H02(1)
H02(0)
H01(7)
VSS7
CMO MEMW SL
PMT:.MST_RQT
VSS8
H01(6)
H01(5)
H01(4)
H01(3)
H01(2)
H01(1)
H01(0)
HOO(7)
HOO(6)
HOO(5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
•
1.097"
1.097"
86COS
160 pin
Quad Flat Pack
(TOP VIEW)
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
~~~;~~~~~~~~~~~~~~m~~~~~~~~m$~~~~~~~~~~g
CONFIG(2)
CONFIG(3)
OSC_02
OSCO
OSCI
M~O(O)
MA_0(1)
MA_0(2)
MA_0(3)
MA_0(4)
VSS1
M~0(5)
M~0(6)
M~O(7)
MIO_MEM
MIOWR
MIORO
MALE
OMA~CK
V001
OMA_REQ
000(0)
000(1)
000(2)
000(3)
000(4)
000(5)
000(6)
000(7)
VSS12
OPO
001(0)
001(1)
001(2)
001(3)
001(4)
001(5)
001(6)
001(7)
OP1
NCR MICROELECTRONICS
1635 Aeroplaza Drive
Colorado Springs, CO 80916
(719) 596-5612, (800) 525-2252
NORTH WESTERN SALES OFFICE
Suite 209
3130 De La Cruz Boulevard
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(408) 727-6575
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(612) 941-7075
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S uile 4000
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(214) 578-9113
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Suite 250
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(404) 587-3136
EUROPEAN SALES OFFICE
NCR GMBH
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West Germany
(49) 89-632-202
ASIA/PACIFIC
2501 Vicwood Plaza
199 Des Voeux Road
Central
Hong Kong
852-5-859-6888
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