~ .",. ,. Digital Computer Switching Circuits Basic operational requirements of digital computers and fundamentals of the means for obtaining them are set forth. For the most part familiar switching circuits can be used hut they must meet the special requirements of positive action that are descrih~d here a specified place. He must then be told where to find his next instruction, unless all instructions are ReriaHy listed and no variations in their order are to be made. ExpJidt instructions as to where to write K UTOMATICALLY-SEQUENC~'D digi- partial results and when and where tal computers are machines to refer back to them for further that have no intelligence, yet carry use comprise a sort of automatic out, without intervention, lengthy memory. The sheets of paper, numroutine~ of mathematical cakula.: bered for identification, form a tion. An understanding of general ~torage'for numbers; his whole prod~!lI)I'tl considerations require~ a gram is stored on paper before he 'Htf\~,\ of the procedures followed ~brts to work. by a human computer using desk Even the power of decision can calculator. be mechanized. If a human comA human computer does more puter is supposed to compute one than arithmetic; he not only carries intermediate re~mlt to a specified out the elementary processes of degree of accuracy by a method of addition, subtraction, multiplic-a- successive approximations, he must tion, and division, but he also de- continue until further steps make cides what numbers to add, multi- insignificant changes. He is thereply, etc., and what to do with his fore instructed to keep repeating results. These results of his arith- the procedure until a tentative anmetic ar~ only stepping stones to swer, taken to ten places, equals the hi .. final goal, jnst as the numbers previous tentative answer. and then IJp"n which he performs his arithto proceed with the main program. ml'til" were previous stepping We see that our automaton must stones. Some problems require mil- be given instructions, or orders, inlions of arithmetic op\1'ations to corporating the foJlowin~ informaarrive at a relatively smaH set of tion: (1) where to find operands; numbers representing the final an- that is, the two numbers to be comswer. bined by addition, multiplication, If we reduce the human computer subtraction, or division, (2) which to an automaton having only the arithmetic operation to perform, ability to read, write, and do arith- (3) where to write the result: metic, we need to givt! him a very either in a specified place for furdetailed set of working instructions. ture reference or on his final anThese instructions include original swer sheet, and (4) where to find numeri~al data from which he his next set of similar instructions. An electronic computer operates works, and an explicit program of operations to be performed. He on a similar routine. Machines be-. must be told, for example, to read - ing designed and built will pt!rform numbers in two specified places, this cycle of operations in a miHiadd them, and write the result in . second or less, working with num- B, C. H. PAGE • t ii" I. Jo:lectTOtliC Computers ~f'rtifJH \"ational Bureau of Sf ttl! (lm·tlH HCpoTtment of ('Olll"If'}"Cf' WashillgtQII. /I, c, .n • .' 110 bers having ten decimal place~. Such speed means that thesE" mRchines will make it practical tu solve problems requiring so man~' millions of arithmetic operation~ a:o' not to be considered at present. })i, recting ~uch a machine is a major administrative problem. As Dr. VOJ! Neumann of the Institute for Advanced Study expressed it, uProgramming a problem for such a machine is equivalent to writing a detailed set of instructions for twenty automatons with dE"~k calculators sufficient to keep them busy for two years, working a fort~· hour week." These automatons have no ability to think for themselves! Leaving the mathematical and administrative problems to others, we can proceed to the basic elt'(·tronic problems. We must first ha\'e (A) an electronic alphabet for writing numbers and orders, (B) :, medium on which to write, (C) means of writing and reading, and (D) means for interpreting the written word. These words may lw. numerical, as 3721499825, or coded orders, as A0173Q75B6. When a number-word (number) is read, it must be translated into what the machine recognizes as numE"I·j(·~1 form. An order-word (order) must be interpreted by being converted to a set of voltages, to operate switches. Reading a word consists in part of tran~mitting it to the organ which i.s to interpret and be affected by it. Thus numbers are tran~ mitted from storage to arithmetic unit, or vice versa, and orders art sent from storage to the central control organ, or dispatcher. In adSept• ...,~ J9U - ELECTRONICS l6{f e· II Mil o I riv~1 2· ilA nAft 3 4 5 6 or t,.,·o numbers .causes the of a third number. Wht'ther this third number is the sum, difference, product, or quotient of the other two depends upon tht' di~patching system of the arithmetic unit. Separate arithmetic units-can be built for the four cases, but it is also feasible to make a universal arithmetic unit which will perform anyone of the four processes upon request of the central control. Hence. the central control must not only dispatch numberwords and orders, but must also interpret orders and actuate circuit changes. tran~mi8sion (A) 7 TIME IN MICROSECONDS (PULSE TRAIN REP'I'IESENTING 3431 IN BINARY SYSTEM) REGISTER FLIP-FLOP TranlmilSion and Representation REGISTER • ACTIVATING PULSES (0) SHIFT SHIFTING REGISTER PULSES (ADJ,T·ONAL 6ATES ARE NECESSARY FOR wR ·I .... G IN NEw INFORMATION AND AUTOMATICALLY ERASING OLD) SIMPLIFIED MERCURY-TANK DYNAMIC MEMORY FIG. I-Put... ar..tored .tatically 1ft flip-flop •• dpamically In delay line. • dition, both kinds of words are transmitted to storage from the input as needed, and final answers or desired partial results are transmitted to the machine output. An order must not only tell the central control which numbers to dispatch to the arithmetic unit from storage, but must also tell centrol control which arithmetic operation is to be performed and where the result. is to be sent. In addition to the central control organ, there must be various local control stations. The arithmetic unit itself, for example, is primarily a traffic unit suc.h that the ar. ELECTRONiCS - s.ptembe" J941 A NUMBER, say 43712, can be read and transmitted in two fundamentally different ways. If one transmission channel is used for each column, we can simultaneously transmit a 2 aiong the first channel, a 1 along the next, 7 along the next, etc. This simultaneous transmission of the digits of each position along their appropriate channels is a PARALLEL operation. Its characteristic feature is that it distinguishes between digits by a spatial relation, transmitting all digits at the same time. Conversely, we could transmit all digit~ over a common channel, at successive times, in the order 2, 1, 7, 3, 4. The separate digits would be distinguished by their time of arrival on a common line. This is a SERIAL process, digits being distinguished by a temporal relation. If ten pulses, made recognizable from each other by modulation, are available, any number can be transmitted either serially, over one liDe, or in parallel, over many lines, from one organ to another. We will consider only serial operation because it is more illustrative of traffic (switching) dispatching problems, as well as because it is the system employed in the machines that will first be constructed. ORDERs to various parts of the machine must also be capable of transmission, hence they can be expressed conveniently as numbers in some arbitrary code. Thus numbers and orders are represented in the same way, being strings of dieits. We know which is which when we put them into the machine, so that I f our programmer dispatches only orders to central points and numbers to arithmetic points, it will not matter that the machine by itself cannot distinguish orders from numbers. In fact, this is a convenience, because by considering an order as a number we can modify an order by operating on it with the arithmetic unit. REPRESENTING the ten digits by pulses of different amplitude would reduce machine reliability, makine results depend upon tube constants and supply voltages. It is better to have only two amplitudes to distinguish. If these two amplitude!' represent digits 0 and 1, we mUflt find a way of representing numbers in term8 of these two digits. In decimal notation, the number 352 means 2 X l~ + 5 X 1()1 + 3 X 1()2 =- :2 +50+300 Each successive digit position to the left represents the coefficient of the next higher power of 10. We therefore need digits only to 9; a coefficient of lOin any place is equivalent to a coefficient of unity in the next place. If we dri use of 10 as our base, and u"•. stead, we write a number • .,dl iV 37 in the following binary m~Anner, 100101, meaning I .... - lX20+0X21 + 1 X 22+0 X ~ () X 24 + 1 X ~ - 1 + 4 + 32 = 37 + We pay for the simplicity of having only two different digits by needing approximately three times as many columns to write a number in the binary system as in the decimal system. To represent 0 and 1 and the corresponding pulse trains, we choose a basic pulse repetition rate of 2 mc, and synchronize all parts of the machine so that successive pulses (representing 0 or 1) occur at these half-microsecond intervals. It . all trains of pulses are locked to this reprate (repetition rate), we can use the presence of a pulse to represent 1, and the absence of a pulse to represent O. Thus the sixmicrosecond pulse train shown graphically in Fig. lA represents the binary word 110101100111 (read from right to left) which has the (decimal) value 3431. Voltage and tube parameters need only be held within the tolerance ran&e to 111 , I...-Q1.' • • • keep the pulses within their an. plitude range of reliable operation, Now that we have a scheme for representing numbers as pul~ trains, we are ready to analyze problems of storing numbers. STORAGE - Typical machines operate with numbers of ten significant figures i.r.l the decimal system, so will require roughly 35 binary ... places. A 35 binary place number at 2-mc rep rate will be represented by a pulse train having a duration of 17.5 microseconds. It is impractical to put information into a machine or to print results at such a rate, over 50,000 words per second. We need a speed changer, or device for storing the many words being written into it at one speed, and capable of being read at some other. ~peed. either faster or slower. One ~cheme is magnetic recording of the pulse trains on either wire or tape. :\Iagnetic pulses cannot be packed more closely than about 200 per inch if they are not to overlap and become incapable of resolution. The reprate of reading and writing magnetically for a given pac.king is proportional to the speed at which tht· wire is transported. Hen('+' Wt' can magnetically ~ecord pul:4e train~ leisurely and run them mto the machine rapidly or conversely, can record fast signals on a fast wire, arid later read the wire at speed which an electric typewriter can reliably be expected to follow. . Inside the machine we need two - types of memory, one that stores a train of pulses statically and another that stores the high rep rate t rains of pulses. ST ATIC REGISTER The first of these, the static register, is needed, among other places, in the arithmetic unit, to set up central voltages in accordance with the O's and l's of a number. Basically a static register is a flip-flop such as that of Fig. 1B which has two stable states. High and low plate voltages can be taken to represent the stora$e of a lor. O. In a practical flip-flop, grid capacitors are used to speed transition from one state to the other. Minimum transition time depends upon mutual conductance of the tubes. A more rapid flip-flop than the one shown can be made by U8- a • , 112 GATES - GRID CONTROL .IID INPUT DIODE CONTROL + + + 1ST INPUT (A) SERIES GATE FOR POSITIVE PULSES GATE POR POSITIVE INPUT PULSES 2 (8) GATE FOR NEGATIVE INPUT PULSES PARALLEL GATE FOR NEGATIVE PULSES BUFFERS -2----~~~~---(C-)--__+-+~ WIv- SERIES BUFFER FOR NEGATivE PULSES BUFFER FOR NEGATIVE INPUT PULSES (0) PARALLEL SUFFER FOR POSITIVE PULSES SUFFER FOR POSITIVE INPUT PULSES FIG. 2-Gate. and buffer. consHiu!e the operatinq element. of the arithmetic: unltL Germanium diode. may be used for compactne.. I I I I IL ________ ...JI FIG. 3-Ba.ic functional componenfa of diC)ital compuler. and their interrelatlon ing such tubes as th~ 6AK5, connected either as pentodes or triodes. Provision is also made for setting the' flip-flop in either state by applying a negative pulse to the appropriate tube. The diodes are i§olation buffers to disconnect the pulse sources when pulses are not being applied. This not only reduces loading on the transfer pulse from one tube to the other, but also prevents this pulse from being transmitted to other flip-flops via the input circuit. Tying the two input leads together provides a' binary counter. The plate-grid coupling capacitances provide enough memory (time lag) for the flip-flop to remember in which state it was prior to the application of a pulM ap- plied to both tubes. As a result, an input pulse changes the state of the flip-flop and provides a scale-oftwo, or binary co un tel'. Cascaded binary counters have many applications. For binary counter purposes, the grid input arrangement~ can be omitted and a posit.ive pulse applied to the common cathode lead. By using 35 flip-flops, one for each binary column, we can statically store a 35 place binary number. Writing a number into a register consists of setting its flip-flops in accordance with the succession of O's and l's in the binary numb(>r . Reading' the register consists of causing ~t- to generate the pulse train .orresponding to its array of 0'8 and 1's. FEEDING BEGISTEa There are ~, '''''-ELECnONICS • • • • ~ wo ways of ~nverting a serial : rain of pulses 'into the parallel I'orm for storage in th~ static rerster. The, pulses can either be fed nto the register from the end or ,t't up in' parallel alongside it. The latter scheme is indicated in Fig. Ie; the train of pulses is fed ntQ a delay line of 0.5 !'oS sections, -1/ that just as the last pulse ap·t'ars at the input the previous lulses appear at the various junc.ons. The delay line ,thus motlt>ntarily converts the serial pat"rn of voltage peaks versus time :lto a spatial pattern .of voltage .'rsus position; voltage appears at he junctions corresponding to the positions of the binary 1's in the <lImber represented, no voltage apIt'ars at the positions correspondn~ to O's. When this space pattern s obtained, all th~ ga~s are opened .y an-'lIctivating pulse, and the l's lre entered into the register via the ..et 1 input lead~. The register can tt! cleared by applying a pulse to th~ set o inputs. If the plate outputs of the flip;Iops are connected to successive lunctions of a duplicate delay line, dearing the. register (by simultaneously setting all flip-flops to 0) "'ill introduce pulses into the line at the 1 positions; thes~ pulses will I'ome out of the delay line as the desired train. The other scheme for sending a t rain into a static register is somewhat similar to the operation of some desk computing machines that have only 10 keys, 0 through 9. Pushing 3 enters 0003 on the dials, then pushing 5 shifts the 3 along as the 5 is entered, showing 0035, etc. This sequential to parallel conversion can be accomplished by the shifting register of Fig. ID. The set 0 lines are all connected to a shift pulse bus. A shift pulse then clears all flip-flops, and any registering 1 generate' output pulses. _These pulses arrive at the set I leads of the next flip-flops, transferring the l's one place to the right. Clearing a flip-flop registering 0 generates no pulse, so leaves the next flip-flop cleared to O. Hence every time a shift pulse is sent in, the contents of the register shift to the right. If the shift pulses come at a 2-mc reprate, evenly interspersed between the ELECTRON ICS - September, 1941 2-mc ltlpal, JK'lses sent into the line art' loo great. Each word to, left-hand ftip.ft.op, every time the be 8tor~ requires 17.5!&8 of line to regiswr is ahi.... jt will find the hold it; this implies a total of 17.5 next di«it of the t8in in the left- milliseconds of electrical delay line. hand flip-flop and 35 shifts will re- whether in one or several segmenb. sult in a Atatic storage of the 35 To transmit the individual 0.2 !A.~ pulses in the train. We now stop the pulses without excessive distortion shifting and have the number requires a bandwidth of 10 mc. Even with the optimistic figure of stored. Reading the register (regener- 6 db per !J.S attenuation in lines ating the train of pulses) is sim- having this bandwidth, attenuation ple. The output of the right-hand wou~d be 105,000 db, requirinJ!" flip-flop Js connected to a transmis- 7.000 tubes such as the 6AK5 ha\'sion bus 'and 35 shifts are made, ing a gain of 15 db per stage. Thi:-, sending the successive l's and O's is excessive. A practical way to simplify dyonto the line, and leaving the register cleared to all O's, assuming namic storage is to store puls{'~ that no signal is coming in from the . acoustically rather than ele('trieall~ \Ve can convert the 0.2 !A.s pulse:-: left. The static registers described into 0.2 ,""S packets of h-f u~ing a above require two tubes per binary carrier frequency of 20 or 30 mt. digit, or 70 tubes per word stored, These h-f pulses can then be used to d.ve a quartz crystal which in 80 are uneconomical for the main storage. (A general purpose com- . turn generates waves in a mercury puter needs storage facilities for column. A receiving crystal at the at least 1,000 words). However the far end senses theSE! wave!'! giving static register is useful in' the a signal that is amplified and rectiarithmetic unit for intermediate fied to regenerate the pubes. At8torage between two organs with tenuation in mercury is approxi~ different speeds, such as internal mately 0.06 db per :J.:o' at a rsrripr parts of the machine and the mag- frequency of 30 mc, or 1I1If' iN" netic wire. One word at a time can cent of that for the electrical be written at any speed, and then The pai r of crystal transducer .. read at any other, permitting syn-. with the line introduce:, a ill!''' ,.: chr0!1izing input data pulses with about 50 db. I f one long delay line is used. the 2-mc clock, which would be impossible to do by trying to run coupling losses would be negligible, but a single delay line of 17.5 millithe wire at an exact speed. The other internal high-speed seconds would require on the avermemory, or scratch paper, of the age a waiting time of 9 millisecond:;, machine can either hold pulse before the desired word would be trains as a static array, or remem- available. This is too long. A pracber them dynamically; that is, in tical compromise between equipthe form of pulse trains available ment and speed is to subdivide the for retransmission on demand. Only memory into lines, or tanks, of 20 the latter choice will be discussed word capacity. each having a dpl .. '" here. of 350 '""s. Thus 50 lines are net'dt".l DYNAMIC MEMORY-The simplest involving 50 pairs of transducerway of achieving dynamic memory having 2,500 db attenuation. Addis to feed pulses into a delay line ing the attenuation of 1,050 db in whose output is connected back to the mercury, we have a total of the input to keep the pulses circu- 3,5~0 db attenuation (to be comlating. An amplifier and pulse re- pared with the 105,000 db of elecgenerator are needed at the delay trical lines) and requiring only' line output to compensate losses. about 250 amplifier tubes. A typical Distorted pulses from the line are reci&:.culating tank circuit is shown used to control a gate feeding fresh in Fig. IE. pulses from the master pulser, or \Ve now have conceptually a clock, back into the line. Such a source of input signals, a receiver gating combination in the recircula- for output signals, an arithmetic tion system is referred to as a pulse unit. static registers and dynami<.' reshaper. nipmory tanks. Signals must be disThe losses of an electric delay patched from one to anothel' of 113 \ Table I-OperatioD ot (In Elementary Adder • He Tf"rminal~ I~PUT A I~PUT 8 I~PUT C ICA RRY) Ut"'f"n'ar~' ,\ddf"r OUTPUT 0 (DIGIT) ELEMENTARY - ADDER OUTPUT C (CARRY) " I.i~l III A .. In B. uf Hinurl Input-Output 0 0 II 0 In C." Out D. Out C .. 0 1 0 1 1 1 1 0 0 1 0 0 1 0 (I 1 0 I 0 1 0 1 0 0 (I Comhinution~ 1 1 0 1 0 1 1 1 1 1 '.' 1 ,..:plcction requil'c!-! no swit('he~ aside from the timing gate. The timing circuit can be operated by dividing the master clock rate. The 2-mc reprate drives a counter which counts up to 35 and then throws a flip-flop, giving an output which is on for 35 pulses, or one word time, and off for the next. By ff'eoing these rectangular waves of word duration into a scal€'of-20 counter, we can devise a circuit which will give an.output (to control a gate) for the duration of any desired one of the twenty words. Rult's of :\ritlarnt'ti ... Binary olH'rations A sing-Ie iuput I ~t'nerates 8 1 and 110 carry ~) Two input l's-f!t'm'rate II carry but no output J) 'n Thff~ inplit l's f!I'Jlt'rate hoth and Olltput and a carry Logical concept" (1) (A AND B) or (A AND C.) or (8 :\~D C) ,Senerate8 8 carry (2) A or B or C generates an output digit. unless one of the above AND combinations occurR. which operates 8 gate to prevent the transmission of the digit (3) A AND BAND C generates hoth digit and carry FUllc'lions of Elementary Adder Tr8J1smit a di~t if A ()fi R ()R C and not A A.ND B, A AND C, nor B or if A :\ND B .\1\0 C I ;enerate a carry if A A:XO B, A AND C, or B Al'4D C • .~ND C, th~:-.t' urgan:-;, In general, any organ use of a buffer between an oscilmay oe called upon to send signals lator and a modulated r-f amplifier to any other. The simplest way of is well known. In our case of passdoing this is to connect all tank ing pulses of only one polarity, we inputs to a common point through do not need a triode or pentode switches (electronic gate~) and to buffer, but can use a diode. This connect the arithmetic unit output diode is normally biased with back to this point. Then opening the voltage so that it presents a high proper gate will allow the signal to impedance to the common otis. A proceed to the chosen tank, and to pulse on the ous increases the back I ,t her. ('(ll)versely, if several \'olta)!e on the diodes and is pro"" an' T.O be capable of sending tected. A pulse from a sour,ce, ho~ c'" eral receivers, all sou rces can ever, reverses the polarity on that 't' \..'onnected in parallel to ., ~om one diode apd goes through with mon transmisdion bus, and the re- ::mall loss. The advantage of such ceivers connected to this bus buffers is that germanium diodes through gates. Then by opening a can be used, greatly reducing shunt receiver gate, and instructing the capacitance. proper source to transmit, the deWith gates and buffers we can sired result should follow. In prac- perform circuit switching, or spatice, this would not work, for with tial selection for traffic control. If many sources in parallel, each we stored our 1,000 words in 1,000 source would oe loaded by the paral- one-word tanks, there would be an lel combination of the output im- .exorbitant number of 5witl:ht's with pedances of all the others. \\' e need, their attendant IosRes and control Ot.'t ween each source and the com- problems. We could compromise on mun bus, a buffer which allows only 50 tanks holding 20 words each. \\'e one way traffie, so that a signal can can choose anyone i·f . liese 50 come from a source through the tanks by spatial switdllllK and any buffer to the bus, out the other one of the 20 word~ in a tank by sources cannot load the bus. The temporal selection. Thl' tt'mporal 114 Arithmetic Circuits To understand how to combine gates and buffet·s to make a circuit that will do arithmetic, it is con\jnient to interpret gates and buffers in terms of their' logical behavior. A GATE is essentially a device having two inputs and one O'JtP!Jt. Either input can be considered as the signal. and the other as tht' control. Obtaining output from a gate is dependent upon stimulating both inputs; that is, it requirE'~ stimulation of one input AND the other input. Logically the gatp detects the AND concept, one thin)! AND another.· . .. BUFFERS, on the OtlH'T hand, that feed two or more ~hmaJ~ to a ('ommon point jCiw an ilutPUt signal if anyone of the sourcE'S is excited; that is, if one OR another input of the row of buffers is stimulated. Hence two buffers connecting two inputs to one output constitute the logical concept of OR. one signal OR another. Typical gate and buffer circuits u:-ling tubes are shown in }<"ig. 2. The series gate of Fig. 2A has both grids normally biased beyond cutoff; both must be driven above cutoff to produce an output. The parallel gate of Fig, 2B has all tubes nurmally conducting. If the load -re:-\istor is large compared to the conducting re~istance of a single tuiJe, the common plate voltage wilJ remain low unle~s all tubes are cut off by si~llals. The series 'and parallel buffers of Fig. 2C and 2D represent inver~(' operating conti itiun~ on the. corresponding gute eircuits. The norSeptember, 1948 - ElECTItONICS ~-tfl • mal-abnormal conduction states are interchanged, and the circuits are stimulated by pulses of sign opposite to tho~e required by the corresponding gateR. A signal on any input produces a ch~nge in the output. Th(' diode circuits of Fig. 2 are alJ parallel circuits. Gates, requir- ing the AND or multiple coincirlence, have all their diodes normally conducting, while buffers have an their diodes normally nonconducting. Diodes are generally of the germanium type. Adder Is Basic Element '. To add two digits, the basic operation of arithmetic, we need two inputg and one output. If the sum of the two digits is greater than 9 in the decimal system, or greater than 1 in the binary system, a carry will be produced to add in the next digit position. Hence we need three inputs, one for each digit in the given position, plus one for the possible carry from the previous position. We also need two outputs, one for the output digit, and one for the carry. Thus each digit 'position requires a device as shown in Table I. Operating characteristics of this elementary adder can be deduced from the laws of arithmetic. The desired outputs for the eight p08sible input combinations of 0 and 1 on the three inputs are li~ted in the table. There are two types of adders: parallel and serial. A PARALLEL ADDER is made of 35 elementary adaers, one for. each digit position. Various digits are set up in a static register, as pre.. viously discussed, and the steady register output voltages representing O's and l's activate static elementary adders. The carry output lead of each place can be permanently connected to the ca\'ry input lead of the next, requiring one type of elementary adder to satililfy tht> rules of arithmetic. Alternclt i H·ly the sum and carry digits can be formed statically in each place, and the carrier transmitted to their neighboring adders an instant later. Part of the difference in tht> circuitry is involved with the fact that a carry may generate a carry, as in adding 7774 to 2226. PropagaELECTIONICS - September_ "4 tinn 1)( tnt, carry down the line can bf' han.U..d in various ways. ,,- times as" the next digit. " the example: THK SERIAL ADDER uses a single ~; I :n complil'att·ci elementary adder for SUl,(,p~8jve digit places in sequenct'. ;;71 I ~ _'_ :-\~, Pul~e trains are not set up in static aa form. but are fed in dynamically. :)74 the two numbers ar..riving simulta1779-' neously. If an output 1 pulse is ~enerated, it is transmitted im-' Because in' the binal'~' sy~tem, mediately as one digit of the sum. only 1's and O's occur, we have for If a carry pulse is generated, it is the partial products either the muldelayed 0.5 !L8 and returned to the tiplicand itself, or zero. carry input, arriving there coinciBinary Decimal dent with the input digits of the 10111 23 lOt 5 next place. . An elementary adder can be made 10111 11.5 00000 of gates and buffers. Rules of lOlll arithmetic shown by the list of in1110011 put digit combipations are stated in Table I. The preventing opera- This allows us to use a ghifting tion in case (2) implies a negative register (previously described) togate, or logical AND NOT, which gether with a basic adder, to peris easy to devise from diodes by form multiplication. We do or do using several bias levelg. With this not add in the multiplicand accordterminology, the functions of an ing to whether the right-hand digit elementary adder can be described of the multiplier i~ 1 or 0, shift the logically as at the bottom of the number in tht> rf"~ister, and repeat. table. The complicated combina- Thus a basic arjthmt'~ _ 1111 it contions of AND and OR are strai~ht sisting of registers, \\~. forward logically and electron ically. sh iftect Wh('ll desired. , but lead to a practical circuit em- buffer~. can (.lither .~f1d ploying (in one design) nine pen- accordiuJ.! ttl whf'th"1 _t Jl"t.~ .• ,~. todes and 36 diodes! Some of these pIe ~ignal to add, or whether it g-~t., elements are incorporated to re- ahw a signal to shift and repeat. shape pul8es, and several diodes are Other modifications permit ~lIb used as limiters and d~c level traction and division. \Vhirh operarestorers. t ion is to·l.H' performed is controlled Any adder can be con~idered as by signals from cen~ral control. a problem in traffic control where usually quasi-static voltages to kef"l' the signals (numbers) that are put certain gates open until the operain control the transmission of tion is completed. pulses throughout the adder. This Before examining mf"ans for ('onlocal control is one step more com- verting pulse trains representing plicated than the central control, or arbitrarily coded orders intI' vat.· traffic dispatch between organs. In ('ontrol voltages, Jet us yllil\\" , the ceptral control problem, control the o\'erall organization uf t ht· voltages set up the paths to be puter. taken by signal pulses. In the local The input portion of the machine control, pulse paths, and times sends all its words, both numbers (clock beats) at which pulses occur and orders, to the high spt'ed are set by the signals themselves, . memory storage. From storage, so that there is no longer a clear- orders go to the central control, cut distinction between signal and logically through a decoder, but this control pulses. decoder is the main part of the MULTIPLICATION is a more com- 'central control and so is not usually plex problem. Drdinary longhand considered separately. Central conmultiplication consists essentiall~' of trol must dispatch operating' inadding the multiplicand (57-l' it~ 8tructions to all machine unit~, including the input, for it must tell many times as the right-hand \.i~.tt the input when there is room in the of the multiplier (31) ahlfUnii columns, adding on the multiplic.a,,&.f memory for more data and orders 115 • to continue the problem. The geu(?ral scheme is ~hown in Fig. 3. Tht· only feature of the diagram that -i:-; unnecessary is the transmission of orders (not control voltages) to and frmn the arithmetic unit. This i:-; a useful wav of pyramidingthe hierarchy of 'eont~ol to :-ll'hieve H'rsatility of operation_ Because orders themse]ve~ are coded to appear as numbers, orders can be modified by performing arithmeti<.: lIpun them. This feature ~impJifie:-: proA'l"ammjn~ the mathematical problem in h'rms of dispat<.:hing orders. but need not concern the .. Ip("tronic circuit designer. We have mentioned that orders are coded in numerical form. Suppose for example that eight differt'nt orders are desired; that is, 19'ht different lines are to be ener;. i/t'd. Any eight things can be repl"t'sented in code form by the binar~' numbers 0 to 7; that i~, 000, 001, 010, 011, 100, 101, 110, 111. These are the eight combinations of three places, each having either two values. Electrically, we can hav~ three wire~, each of which ma~' h:l\'p voltage applied. If "";f,,:., .• " 11lllse trains they can be . ,'I'led to the static three wire \ nmbination by setting up a static register of three flip-flops. We then have three wires,. anyone or more of which may be hot, repr;esenting t>i~ht different possibilitie~, and we wish to excite anyone of eight leads in accordance with these choices. In general, we have N wires of two possible states each (hot or ('old) giving 2'\' combina• jlll)~. and wish to excite only one of ~ lI.1tputS. In practice, instead of ll:o'ill~ S wires from N flip-flops, ha\"in~ some hot and some cold, it is better tu bring two wires from each tf ip-ftop, one from each side. \\! e then have /ttl pairs of wires, each of which has only o"e side hot. All input pair~ are thus excited one way or the other, avoiding complif:ations of zero-voltage input signals. The simplest case of a decoder is \\'here N = 2, so that there are two input pairs and fOllr output leads. The circuit of Fig, 4A shows this ease. The horizontal and vertical lines are connected through diodes, gO that the diodes in any column form a gate, or AND circuit. If ,I pper and lower lines of the top I'air are excited positively, output f lum the left-hand lead is excited, and so on for the four possihle ,l"omoin'ations of input, SIMPLE DECODER ( 8 DIODES) ALL DIODES NORMALLY CONDUCTING(A) or • • 116 For larger decoders,' it will be convenient to indicate the presen(.'e of a diode connection between t\\"o lines by a circle at the c rossO\'e I'. There are no direct connections. Figure 4B shows a simple decodel' for foor input pairs, yielding 16 possible output excitations. Combinations of upper and lower pair excitations that result in excitation of each of the 16 lineg are indicated on the figu reo This dired check of the possible l"omhinations can be called a one~tage decoder. Fewer diodes are required if we decode in two stages, namely, by mixing two pairs as in Fig. 4A to get one line out of four, and doing the same with the other two pairs to get one line out of another set of four. \\' e then have two set~ of four line~ each, in which only one'line of each set is extited. These two sets can be fed into the circuit. of Fig. 4C. Thus in using Fig. 4B, each output line requires a quadruple coineidence fol' excitation, and 64 diodes are needed. By using two circuits of '·'ill. 4A and one of Fig. 4C, makifl~ ..;ucce~:-;i\"e simple coincidences, we nt'E:'cI 8 + 8 + 32 48 de('odt'rs, or a . sa \'ing of .25 percen t . Multistage decoding exhibits even greater savingt> as X increa.Re~. For ~T 8, allowing select ion of anyone of 256 memory tanks by virtut' of the 2' 256 different gate~ that ma~' be opened by an 8-pulse signal, a th ree-stclg'e decoding requires only 608 diodes as aga..inst 2,048 for .",ingle-stage decoding .. = U U U U U U U U L L L L L L L L U U U U L L L L U U U U L L L L U U L L U U L l U U L L U U L L L U L U L U L U . ; :"> >> :cc . :c " : U L . : > " U L U l : > : ~ " : U L : > > : I FOUR PAIR DECODER (64 DIODES) = = (8) Traffic Handling Systems -. :. :. ~ "> < ~ " • .~~ : < .? . ; flill :. : ~ > < < "> <> : : :> : • r TWO Sf TS 0, FOuR WIRES (32 :lIOOES) (e) FIG. 4-·Switchin9 circuit. use unidirectional conductance of diode. Having seen how a coded order can be eonverted to the selection of a gate opening voltage. it is of interest to consider briefly the" general traffic handling- plan. Tht' mathematician prepares his instructions to tht' machine in term~ of numerical data, coded orders to select which basic opel'ation the arithmetic unit is to perform, fOl' ~equencing the machine or for expres~il1g the routine to be followed. In general two kinds of wOl'dg al'e . put into the machine memor\": numbers and orders. Assume that the memOI"y is capable of storirig 1,000 words and, for $eptembe" 19"- ELECTRON;CS ",:;:-,,:,.2:1,,1. i'": ' . . ;,.";;,. • • • simplicity, that the two kind8~ of words are of equal duration, or number of pulse positions. TheM 1,000 words occupy definite posi, tions in two dimensional space-time. Hence we can consider their positions as' pigeonholes numbered from 1 to 1,000 and call (or transmission of a word to or from any pigeonhole. The simplest way of enterinK the input data is to take the first thousand words from a magnetic wire and store them sequentially in the thousand cells. This can be done by using a counter to ~easure off a word, and cause unity to be added to the address to which the next word is to be sent. High speed reading of the memory can also be done sequentially by giving the address 1 as the instruction for the cell to be read and by having a built in arrangement for automatically adding uni ty to the add ress of the cell to be read. It will then automatically read cell 2 as soon as it has. finished with cell 1 and- is ready to read again. A procedure that may be more flexible for repeating subsequences and setting up branch operations ( choice of next order dependinK upon present results) and also more convenient in practical programming, is the four address code. In this system each order is composed of four addresses (or memory cell locations) : the address of the first operand (number to be arithmetically operated upon), the address of th. ~~onci operand, the code for the "prratiop to be performed, and the .ddress of the next order to'be read after completion of the present instructions. This system is more efficient if memory reference is slow compared to other operations; that is, if waiting time for a word to be reached in the sequential reading of a dynamic memory is relatively large because it allows the _essentially simultaneous look-up of both operands. A variation of the four address system is the use of a fifth address in the words on the input wire, to designate the cell into which that word is to be stored. The fifth address is automatically deleted as the word is entered into the machine. In electronic digital computers, III ..... tubes, for example, are called ~pon to develop a pulse of usable level, or not called upon a.t all. Variations between tubes, aging, or tolerances of resistors do not affect accuracy, until, they become so extreme that the signal falls out of usable range. A ten to twenty per cent variation of signal strength has no effort on a series of pulses. 'ideally a computing machine works perfectly or not at all. Actually, as tubes deteriorate, there is a threshold at which operation may be erratic. By setting a limit checking circuit for a' safe level margin, this otherwise possible operation can be put in the class with complete breakdown. Errors can occur due to noise generatin~ a false pulse at an allowed pulse time when the word transmitted has a zero In that position. This noi~e pulse may be indistinguishable from a proper pulse. Oceurrence of errors due to such random causes can be guarded against by one of several checking schemes. • One of the most elaborate checking schemes that has been proposed is to check the arithmetic and the transmission. The arithmetic can be checked in a fashion similar to the ancient system of casting out 9's, where each number is expressed as ita-excess over a multiple of 9; that is, it,has a value of 0-8. This is done by adding sideways. The 9's excess of a sum of numbers is equal to the sum of their individual excesses, (expressed as an excess if larger than 9). The 9's excess of the product of two numbers equals the (excess of the) product of their excesses. A simple auxiliary addition or multiplication on the excesses has often been used for checking arithmetic. Fo·r example, multiplying 371 by 24 gives 8904. The 9's excess of 371 is found by adding the digits 3 + 7 + 1 = 11, 'I + 1 2. Similarly the 9's excess of 24 is 6. The product of these two excesses is 12, having itself an excess of 3, which agrees wi th the excess of 8904, 8 + 4 ~ 12, 1 + 2 3. A cQTresponding procedure of casting out (2" - 1) can be set up for binary computation, and a small auxiliary arithmetic unit operated simultaneously wi th the main unit. = t = This type of checking lends itself to verifying correct transmission of a number. The excess count of a number can be stored with it in the memory for performing the parallel arithmetic check. It can be used as a transmission check by taking the excess count of a number received by the arithmetic unit and comparing it with the received check count. Very peculiar transmission errors are required to make the new count of an incorrectly transmitted number agree with either its original count or an incorrectly transmitted count. This type of checking is based on arithmetic. Checking the address selection exercised by central control can be done by storing with each word its address. When the word and accompanying address is read,. the , read address is checked against the called-for address. This checks both the spatial and temporal phases of word selection in the machine. Electronic design of machines ia fast progressing to the point where they will be more perfect than the mathematics set up for them. I refer to such varied factors as round-off error, inevitably introduced by working to a fixed number of significant figures. If a machine performs 1,000 arithmetic operations a second for days on end. what relationship does the final answer have to the original hypotheses? Some mathematical research is being done on this point. A more vital question is the design of mathematics suited for machinett. Many procedures use machines for replacing human computers, using numerical computational schemes developed for the human brain. Characteristics of an electro~ic machine are different from those of a human brain, and it is reasonable to suppose that computational procedures can be devised which, although unsuited for hand computing, are well adapted to machine routines. Such procedures have been developed for a few special problems. ' The writer thanks the Raytheon Manufacturing Company and th~ Eckert-Mauchly Computer Corporation for supplyin&, some of the cir. cuit details shown in the figures.

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