United States Patent [191 4,845,573 Hardeng Jul. 4, 1989

United States Patent  [191 4,845,573 Hardeng Jul. 4, 1989
United States Patent [191
[11]
[45]
Hardeng
[54] SYSTEM WITH FILTER SYSTEM FOR
56-80118
56-108448
[21] Appl. No.: 85,390
[30]
[51]
[52]
Japan ................................... .. 360/68
Japan ................................... .. 360/68
IBM Technical Disclosure Bulletin, vol. 15, No. 3, Aug.
1972, J. D. Armitage, Jr. et al, “Magnetic Recording
and Feedback Systems”.
IBM Technical Disclosure Bulletin, vol. 23, No. 9, Feb.
1981, K. B. Klaassen, 6‘AC Bias Read-While-Write
Japan-Patent No. 57—3207(A), vol. 6, No. 62 (P-lll)
Foreign Application Priority Data
Fed. Rep. of Germany ..... .. 3634029
Int. 01.4 .............................................. .. G11B 5/09
US. Cl. ............... ..
360/46; 360/66
[581 Field ofSearch
l/l982
l/l983
Driver”.
Aug. 14, 1987
Oct. 6, 1986 [DE]
Jul. 4, 1989
OTHER PUBLICATIONS
Erik N. Hardeng, Olso, Norway
[73] Assignee: Tandberg Data A/S, Oslo, Norway
[22] Filed:
4,845,573
FOREIGN PATENT DOCUMENTS
MPROVED RELIABILITY FOR
RECORDING DATA ON A MAGNETIC
RECORDING MEDIUM
[75] Inventor:
Patent Number:
Date of Patent:
360/46,66,68
(940), Apr. 21, 1982.
Primary Examiner-Vincent P. Canney
Assistant Examiner—Kevin J. Fournier
[57]
ABSTRACT
In an arrangement for recording data or a magnetic
recording medium, the inputs of an ampli?er whose
outputs are connected to a magnetic head are preceded
[56]
References Cited
by ?lters which delay magnetic bias signals and data
signals supplied to the ampli?er and limit their steep
U.S. PATENT DOCUMENTS
3,381,098
4/1968
Pezirtzoglou .
ness. Undesirably high voltages at the magnetic head as
3,641,524
2/1972
Norris .
3,665,485
5/1972
Pear, Jr. .
Suzuki et al. ....................... .. 360/66
3,821,797
6/1974
4,202,017
5/1980 Geffon et al.
4,383,281
5/1983
4,547,818 10/1985
Lesieur
360/45
. .. . . . . . .
. . . ..
a consequence of excessively steep edges of a write
current supplied to the magnetic head are thus avoided,
and the reliability of the recording of the data on the
magnetic recording medium is increased.
360/45
13 Claims, 2 Drawing Sheets
Lia ....................................... .. 360/46
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US. Patent
Jul. 4, 1989
Sheet 1 of2
4,845,573
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4,845,573
2
signals respectively, and thus limit their steepness to a
desired value.
SYSTEM WITH FILTER SYSTEM FOR
IMPROVED RELIABILITY FOR RECORDING
DATA ON A MAGNETIC RECORDING MEDIUM
The arrangement of the invention has the advantage
that the data can be recorded with great precision on
the magnetic recording medium, and thus can be played
back with high reliability by means of a read head. The
BACKGROUND OF THE INVENTION
1. Field of the Invention
employment of the ?lter preceding the ampli?er re
The invention is directed to an arrangement for re=
quires little expense since the ?lters can be constructed
cording data on a magnetic recording medium by use of
an ampli?er at whose inputs data signals allocated to the
data to be recorded, and magnetic bias signals, are pres
with passive components.
It is possible to supply only the magnetic bias signals
or the data signals to the ampli?er via a respective ?lter;
however, it proves expedient to supply both the mag
netic bias signals as well as the data signals to the ampli
?er via respective ?lters.
ent. Outputs of the ampli?er are connected to a mag
netic head to record the data on the recording medium.
2. Description of the Prior Art
An arrangement comprising an ampli?er is usually
employed for recording data on a magnetic recording
medium, for example a magnetic tape or a magnetic
In case the ampli?er has a respectively separate am
pli?er stage both for the magnetic bias signals as well as
for the data signals to which the magnetic bias signals or
disc. Data signals are allocated to the data to be re
the data signals are supplied in non-inverted and in
corded and magnetic bias signals are supplied to the
input of this ampli?er. Its outputs are connected to a 20 verted fashion, it is expedient to precede the inputs of
every ampli?er stage by a ?lter at which the respective
write head in a magnetic head which records the data
on the recording medium. Such an arrangement is dis
signals are present in non-inverted and inverted fashion
closed, for example, by German published application
and whose outputs are connected to the inputs of the
No. 32 33 489. In this known arrangement, the data
respective ampli?er stage. The ?lter is preferably fash
signals and the magnetic bias signals are supplied to an 25 ioned as a RC low-pass ?lter. Given a design of the
ampli?er stage of the ampli?er. The outputs of the am=
?lter for the feed of inverting and non-inverting signals,
pli?er stages are connected in parallel and are con
it is advantageous when every ?lter contains two series
nected to the terminals of the two series-connected
connected resistors at which the non-inverted or in
windings of the magnetic head at whose center tap an
verted signals are present, and which contains a follow
operating voltage is present. The ampli?er stages are
ing, parallel capacitor whose terminals are connected to
fashioned as switching elements so that the current
the inputs of the respective ampli?er stage.
?owing through a respective winding of the magnetic
head exhibits extremely steep signal edges.
In case the ampli?er stages are designed as differen
tial ampli?ers, the corresponding signals are present at
the inputs of every differential ampli?er in non-inverted
and inverted fashion via a respective ?lter.
Given employment of differential ampli?ers as ampli
?er stages, it is bene?cial when the write current sup
plied to the magnetic head is adjustable in the common
branch of every differential ampli?er, and is adjustable
A further arrangement for recording data on a mag
netic recording medium is disclosed by US. Pat. No.
4,383,281, incorporated herein by reference. In this
known arrangement, two ampli?er stages connected in
parallel at their output sides are also provided, these,
being supplied with the magnetic bias signals or the data
signals. Every ampli?er stage is designed as a differen
tial ampli?er, whose common branch is designed as a
current source, and whose inputs are supplied with the
respective signals either not inverted or inverted. In this
on the basis of digital data words which are converted
into control signals for the respective differential ampli
?er by means of a respective digital-to-analog con
known arrangement, the current flowing through the
verter.
magnetic head exhibits very steep edges since the .two 45
In case a plurality of write heads are provided in the
differential ampli?ers are driven by the magnetic bias
magnetic head, it is advantageous when a switch unit is
signals or the data signals whose signal edges are steep.
arranged between the ampli?er and the magnetic head,
Since the edges of the write current flowing through
this switch unit connecting the ampli?er to one of the
the magnetic head are extremely steep, the time-wise
write heads upon employment of a channel selection
change of the write current in the magnetic head is
stage.
extremely large and the voltage at the magnetic head
A further improvement of the recording can be
would move towards in?nity if the magnetic head were
achieved
in that the corresponding write current is
loss-free and did not exhibit any stray capacitances. This
briefly boosted before and/ or after every signal edge of
can result in the fact that, due to a voltage limitation,
?ux changes allocated to the data signals and to the 55 the data signals. For this purpose, a pulse generator is
provided which emits a corresponding control signal to
magnetic bias signals are modi?ed, this potentially dete
the ampli?er at every signal edge of the data signals.
riorating the reliability against malfunction and the
In order to also avoid steep signal edges of the write
reliability against errors in the recording of the data.
current here, it is advantageous when the pulse genera
SUMMARY OF THE INVENTION
tor contains an integrating element.
It is an object of the invention to specify an arrange
ment for recording data on a magnetic recording me
BRIEF DESCRIPTION OF THE DRAWINGS
dium by means of which reliability against malfunction
FIG. 1 is a block circuit diagram of the arrangement
and reliability against errors can be increased.
According to the invention, inputs of the ampli?er
allocated to the magnetic bias signals and/or to the data
signals are preceded by ?lters designed as low-pass
?lters which delay the magnetic bias signals or the data
of the invention;
65
FIG. 2 is a time diagram of signals at various points of
the arrangement shown in FIG. 1; and
FIG. 3 is a circuit diagram of the arrangement of the
invention.
3
4,845,573
DESCRIPTION OF THE PREFERRED
EMBODIMENTS
The arrangement shown in FIG. 1 contains an ampli
?er A whose outputs are connected to a respective
write head in a magnetic head H via switch units SW1
and SW2. It is assumed in the illustration of FIG. 1 that
4
signals FD1 and FD2 are output to the switch-over unit
CS2.
The switch-over units CS1 and CS2 are designed as
analog switches, so that the write currents IB and ID do
not exhibit a rectangular curve, but likewise exhibit
signal edges having a limited slope. In the pulse genera
tor PG, a pulse P is generated at every signal edge of the
data signals D, this pulse P being likewise supplied to
the write head formed of two windings W1 and W2 is
selected, and switches within the switch unit SW1 are
closed by a channel selection circuit CH1. The switches
in the switch unit SW2 are opened by a channel selec
tion circuit CH2.
The ampli?er A contains switch-over units CS1 and
CS2 which supply a write current IW respectively
edge of a magnetic bias signal B. At point in time t3, the
generated in current sources CG1 or CG2 either to a
pulse P is ended and the write current ID in one of the
the current source CG2 after ?ltering in order to briefly
boost the write current ID after every signal edge of the
data signals D. The write current ID shown in FIG. 2
thus results when, at point in time t1, the data signal D
has an edge which should optimally coincide with an
terminal of the winding W1 or to a terminal of the
windings W1 or W2, for example in the winding W2,
winding W2. An operating voltage U is present at the
comprises the curve shown in FIG. 2. If no write cur
rent ID were present, the write current IB in the wind
respective other terminal at a common tap.
ing W2 would likewise have the curve shown in FIG. 2.
A clock generator BG generates high-frequency
20
However,
the write current ID and the write current IB
magnetic bias signals B which are supplied to the
switch-over unit CS1 via a ?lter F1 as ?ltered magnetic
bias signals FB. Dependent on the momentary value of
the magnetic bias signals FB, a write current IB allo
cated to the magnetic bias signals B is supplied to the
various terminals of the write head. The size of the
write current IB is determined in the current source
CG1 by a control signal S1 which is output by a control
unit BA. The control unit BA, for example, can contain
a digital-to-analog converter which generates the con
trol signal S1 from a corresponding digital data word.
A data source DS generates data signals D which are
allocated to the digital data to be recorded. These data
signals D proceed via a ?lter F2 to the switch-over unit
CS2 as ?ltered data signals FD, and the unit CS2 con
ducts a write current ID allocated to the data signals D
to the various terminals of the write head likewise de
pendent on the momentary value of the data signals FD.
The write current ID is set in the current source CG2
by control signals S2 whichare generated in a control
unit DA in a way similar to’ the control signals S1. In
addition, a pulse generator PG can be provided, this
are summed, so that the overall write current IW shown
in the winding W2 results when the data signal D1
exhibits the illustrated binary value. During the illus
trated chronological duration, no write current ID
flows through the windings W2 since the switch-over
unit CS2 is in the position shown with solid lines. How
ever, a corresponding write current IB does, such that
the sum of the write currents IB ?owing through the
two windings W1 and W2 is constant. The analogous
case applies when the data signal D1 changes its binary
value since the write current ID no longer flows
through the winding W1, but through the winding W2.
, In the circuit diagram of the arrangement shown in
FIG. 3, the switch-over units CS1 and CS2 are compo
nent parts of a differential ampli?er comprising the
transistors T1 and T2 or T3 and T4. The current
sources CG1 and CG2 of the differential ampli?er each
contain a transistor T5 or T6, and a resistor R1 or R2
arranged in series therewith. The control signals S1 or
40 S2 for setting the write current IE or ID are each sup
plied via resistor R4 or R3.
The magnetic bias signals B1 and B2 are supplied to
being driven by the data signals and outputting control
the bases of the transistors T1 or T2 via the ?lter Fl as
signals S3 to the current source CG2. These control
?ltered magnetic bias signals FBl or FB2. The ?lter F1
signals S3 briefly boost the write current ID at every 45 contains two serial resistors R5 and R6 and a capacitor
signal edge of the data signals D.
C1. In a corresponding way, the data signals D1 and D2
Since the outputs of the switch-over units CS1 and
are supplied to the bases of the transistors T4 or T3 via
CS2 are connected in parallel, a summation of the write
the ?lter F2 as ?ltered data signals FDl or FD2. The
current IB and ID occurs in the write head and a write
?lter F2 is fashioned in a way similar to the ?lter F1 and
current IW results. This write current flows from the
contains resistors R7 and R8 as well as a capacitor C2.
voltage source for the operating voltage U via one of
The switch units SW1 and SW2 are each formed of
the windings W1 or W2, via the switch unit SW1, via
two transistors T7 and T8 or T9 and T10 whose bases
the switch-over unit CS1, and via the switch-over unit
are selected by control signals S4 or S5 output by a
CS2 to the current sources CG1 and CG2.
channel selection unit CH1 or CH2. The switch units
Further details of the arrangement shown in FIG. 1 55 are selected in order to supply the write currents IB and
shall be set forth below in conjunction with the time
ID either to the write head formed of the windings W1
diagrams shown in FIG. 2.
and W2 or to a write head in the magnetic head H
The magnetic bias signals B output by the clock gen
formed of the windings W3 and W4.
erator BG are shown as non-inverted and inverted mag
The data signals D2 are also supplied to the pulse
netic bias signals B1 or B2 in FIG. 2. The ?lter F1, 60 generator PG which generates the pulses P by use of a
which is designed as a low-pass ?lter, obliterates and
delay element formed of a resistor R9 and a capacitor
delays the edges of the magnetic bias signals B1 and B2,
C3, and by use of an EXCLUSIVE-OR element G,
and limits their steepness. Thus, the ?ltered magnetic
bias signals FBI or FB2 are generated. The data signals
whereby the pulse duration of the pulse P is de?ned by
the time constant of the RC element. The pulse P pro
D are likewise output by the data source DS as non 65 ceeds via an integrating element formed of a transistor
inverted and inverted data signals D1 or D2, and are
T11 and of capacitors C4 and C5 to the current source
obliterated in the ?lter F2 in a way similar to the mag
CG2 as signal S3. There, it is supplied to a resistor R10
netic bias signals B1 and B2. Thus, the ?ltered data
which is arranged parallel to the resistor R2. During the
5
4,845,573
presence of the signal S3, the transistor T11 is activated
and the resistor R10 is switched parallel to the resistor
R2, so that the write current ID is briefly boosted.
When, at point in time t1, the magnetic bias signals B1
and B2 and the data signals D1 and D2 assume binary
values shown in FIG. 2, the transistors T1 and T3 are
inhibited and the transistors T2 and T4 are activated.
Given the assumption that the signal S4 activates the
6
ampli?er means connected to the magnetic head for
recording data via the magnetic head on the re
cording medium, said ampli?er means having a
?rst input connected to receive magnetic bias sig
nals and a second input connected to receive data
signals; and
a magnetic bias signal source connected to the ?rst
input via a ?rst ?lter means and a data source con
transistors T7 and T8 as a consequence of a channel
necting to the second input via a second ?lter
selection, and the signal S5 inhibits the transistors T9
means, said ?rst and second ?lter means function
and T10, a write current IW now flows from the volt
age source for the operating voltage U via the winding
W2 and the transistor T8. Write current IW flows as
write current IB via the transistors T2 and T5 and via
the resistor R1. Write current IW flows as write current
ID via the transistors T4 and T6 and the resistor R2 as
well as via the resistor R10 and the transistor T11.
When, at point in time t2, the magnetic bias signals B1
and B2 change in binary value, the transistor T1 is acti
ing as low-pass ?lters so as to delay the respective
magnetic bias signals or the data signals received at
the respective ?rst and second inputs and limit their
sharpness to a desired value.
2. A system according to claim 1 wherein said ampli
?er means has ?rst and second ampli?er stages whose
respective outputs are connected in parallel and
wherein means are provided for connecting inputs of
the ?rst ampli?er stage to either inverted or non
vated and the transistor T2 is inhibited. The write cur~ 20 inverted ?ltered magnetic bias signals from said ?rst
?lter means, and means being provided for connecting
rent ID thus continues to flow via the winding W2 and
inputs of the second ampli?er stage to either inverted or
the transistors T8 and T4. However, the write current
non-inverted ?lter data signals from said second ?lter
IB flows via the winding W1 and the transistors T7, T1,
and T5. The write current IB in the transistor T5 does
not change since the transistors T1 and T2 alternately
carry the write current IB, and as a consequence of the
?lter F1, the write current IB is delayed and the edge
steepness when switching the transistors T1 and T2 is
reduced. Thus, no excessive voltages occur at the wind
ings W1 and W2.
The pulse P is ended at point in time t3 and the tran
sistor T11 is inhibited, so that the write current ID is
slowly reduced to a nominal value.
At point in time t4, the binary values of the magnetic
bias signals B1 and B2 change again, so that, as in the
case at point in time t1, the transistor T1 is inhibited and
the transistor T2 is activated.
When, at a later point in time, the data signal D1
changes in binary value, the transistor T4 is inhibited
and the transistor T3 is activated and a new pulse P is
simultaneously generated. The write current ID then
?ows via the winding W1, the transistor T7, and the
transistor T3 to the transistor T6. Here too, the ?lter F2
carries out a soft switching so that no excessive voltages
occur at the windings W1 and W2 and the write current
ID remains constant. When a recording is to occur with
the write head formed of the windings W3 and W4, the
transistors T9 and T10 are activated by the signal S5,
whereas the transistors T7 and T8 are inhibited by the
control signal S4. The events in the windings W1 and
W2 then repeat correspondingly in the windings W3
and W4.
LC low-pass ?lters can also be employed as ?lters F1
and F2. However, the RC low-pass ?lters prove very
cost-bene?cial. It is also possible to employ only a single
?lter either for the magnetic bias signals B or for the
data signals D.
Although various minor changes and modi?cations
might be proposed by those skilled in the art, it will be
understood that I wish to include within the claims of
the patent warranted hereon all such changes and modi
?cations as reasonably come within my contribution to
the art.
I claim as my invention:
1. A system for recording data on a magnetic record
ing medium, comprising:
a magnetic head;
means.
3. A system according to claim 1 wherein said ?rst
and second ?lter means comprise RC low-pass ?lters.
4. A system according to claim 2 wherein each of the
?rst and second ?lter means has a series resistor at each
of its ?rst and second inputs and a capacitor in parallel
to the two series resistors.
5. A system according to claim 2 wherein the ?rst and
second ampli?er stages comprise differential ampli?ers
whose ?rst and second inputs are connected to ?rst and
second outputs of the respective ?rst or second ?lter
means, said ?rst and second ?lter means having ?rst and
second inputs, the ?rst ?lter means ?rst and second
inputs connecting to inverted and non-inverted bias
signals from said bias signal source and the ?rst and
second inputs of the second ?lter means connecting to
inverted and non-inverted data signals from said data
source.
6. A system according to claim 1 wherein means are
provided for setting a write current in said ampli?er
means by digital data words which are converted into
control signals for controlling the ampli?er means
through a digital-to-analog converter.
7. A system according to claim 1 wherein the mag
netic head comprises a plurality of write heads and
wherein ?rst and second switch means connect respec
tive write heads to respective outputs of said ampli?er
means.
8. A system according to claim 1 wherein a pulse
generator means is connected to an input of said second
?lter means and also to said ampli?er means for boost
ing a write current at every signal edge of the data
signals.
9. A system according to claim 8 wherein saidpulse
generator means contains an integrating circuit.
10. A system for recording data on a magnetic re
cording medium, comprising:
a magnetic head;
ampli?er means connected to the magnetic head for
recording data via the magnetic head on the re
cording medium, said ampli?er means having a
?rst input means for receiving magnetic bias signals
and a second input means for receiving data signals;
a magnetic bias signal source connected to the ?rst
input means via a ?rst ?lter means and a data
4,845,573
7
source connecting to the second input means via a
8
13. A system for recording data on a magnetic re
second ?lter means, said ?rst and second ?lter
col'dlng mefllum, comprlsmgi
means functioning as low-pass ?lters so as to delay
a magnetlc head;
the magnetic bias signals or the data signals, respec
tively, and limit their sharpness to a desired value; 5
ampli?er means connected to the magnetic head for
recording data via the magnetic head on the re
cording medium, said ampli?er means having a
?rst input for receiving magnetic bias signals and a
and
?rst and second switch~over means in said ampli?er
means respectively controlled by the magnetic bias
signals and data signals at the respective ?rst and 10
Second Inputs‘
_
_
,
11' A sy'stem acFordmg to Clam 10 wherem ?rst an?
second input for receiving data signals;
a magnetic bias signal source connected to the ?rst
input via a ?rst ?lter means and a data source con
necting to the second input via a second ?lter
means, said ?rst and second ?lter means function
second switch units are connected between the amph?er means and ?rst and second write heads in the magnetic head, said ?rst and second switch units being (3011- 15
nected to respective Channel Selection unitS12., A system for recording data on a magnetic recording medium, comprising:
ing as low_pass filters so as to delay the magnetic
bias signals 01- the data signals, respectively, and
their Sharpness to a desired value;
said ampli?er means having ?rst and second ampli?er
stages whose respective outputs are connected in
parallel and wherein means are provided for con
a magnetic head;
ampli?er means connected to the magnetic head for 20
necting inputs of the ?rst ampli?er stage to either
[email protected] 01' “PH-inverted ?ltered magnetic bias
recording data via the magnetic head on the recording medium, said ampli?er means having a
signals from said ?rst ?lter means, and means being
provided for connecting inputs of the second am
pli?er stage to either inverted or non-inverted ?lter
data signals from said second ?lter means; and
?rst input for receiving magnetic bias signals and a
second input for receiving data signals;
a magnetic bias signal source connected to the ?rst 25
input via a ?rst ?lter means and a data source con
the ?rst and second ampli?er stages comprising dif
ferential ampli?ers whose ?rst and second inputs
are connected to ?rst and second outputs of the
respective ?rst or second ?lter means, said ?rst and
necting to the second input via a second ?lter
means, said ?rst and second ?lter means function
second ?lter means having ?rst and second inputs,
mg as low'pass ?lters so as to delay the magnetlc 30
the ?rst ?lter means ?rst and second inputs con
bias Signals or the data Signals’ respectively’ and
limit their Sharpness to a desired Value; and
necting to inverted and non-inverted bias signals
from said bias signal source, and the ?rst and sec
3 P1115e generator means Connected to an input of Said
second ?lter means and also to said ampli?er means
for boosting a write current at every signal edge of 35
0nd inputs of the second ?lter means connecting to
inverted and non~inverted data signals from said
data source.
the data signals.
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