xes Xerox Data Systems

xes Xerox Data Systems
xes
Xerox Data Systems
SDS T SERIES
Integrated Circuit
Logic Modules
CONTENTS
I.
INTRODUCTION AND GENERAL SPECIFICATIONS
II.
DESCRIPTIONS OF MODULES
19
III.
ACCESSORIES AND SERVICES
75
PRODUCT INDEX AND PRICE LIST
1
Inside Back Cover
THE SDS APPROACH TO MODULES
Logic modules offered by Scientific Data Systems are designed by experienced
circuit engineers for system applications. The T Series modules were originally
designed for use in the successful SDS Sigma Series general purpose computers,
peripherals, and related special-purpose systems.
Since 1961, in the short span of eight years, SDS has produced more than three
million modules for use in over 1200 computer based standard and special SDS
systems. The first commercial computer with all silicon semiconductors ever
delivered by any manufacturer was the SDS 910, shipped in 1962. The first computer with monolithic integrated circuits was the SDS 92, shipped in March 1965.
SDS logic modules are in part respons ible for the excellent reputation these
computers have established for high reliability, flexibility, and low cost.
Now SDS offers its new T Series integrated circuits module family, as used in
the Sigma 7, Sigma 5, and Sigma 2 Computers, to solve your system or special
purpose logic problems.
©1966, 1967, 1968, 1969 Scientific Data Systems, Inc.
All specifications subject to change without notice.
Publ. No. 64-51-03
Typical T Series Logic Module
Each' ,card unitt uely
keyed for" pr91Jer installi\tiori.
"Grou;,r plaQe huninated ' ,
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gfruJ&oeJpoi'"t ,bQarC~&''''''''''-'...........""""-.
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I. INTRODUCTION AND GENERAL SPECIFICATIONS
THIS IS T SERIES:
Experience with the successful SDS Sigma computers has
shown that at the present state of component development
the best performance, coupled with lower costs, is obtained
when monolithic DTL integrated circuit flip-flops, inverters, and buffer amplifiers are combined with close tolerance, discrete diode-resistor gates and output pull-up resistors. Integrated circuits cut costs, save space, improve
reliability, and improve performance, by replacing repetitive clusters of transistor circuitry. Diode gates retain
flexibi lity where needed, in the gating structures, and help
provide a very high noise rejection of 1.5 volts. Discrete
pull-up resistors (load resistors between output collectors
and Vcc) allow the use of high current drive by keeping
most power dissipation outside the IC package~ Hi gh current drive makes fan-out large, up to 14 gates per output,
and easi Iy permits use of clock frequency up to 10 Mhz because logic line capacitance can be charged rapidly.
Through the use of integrated circuits, 2-stage buffer amplifier cost has been reduced to that of l-stage inverters.
This permits the logic designer to discard the laborious design techniques needed to implement a system entirely with
NAND or NOR logic. Logic may now be implemented in
a natural way by direct substitution of logic circuits equivalent to the Boolean expressions that appear in the most simplified design equations. This saves both design time and
hardware. In T Series these natural logic functions are provided by combining the integrated buffers, inverters, and
flip-flops with various combinations of discrete diode-resistor gating. The circuits are grouped on modules in a wide
variety of AND, OR, NAND, NOR, AND/OR, and AND/
NOR combinations, as described in Section II of this catalog.
A variety of flip-flop modules, with input gating included,
are easi Iy assembled into counters and registerso Some are
genera I purpose wh i Ie others are connected for speci a Ii zed
storage and counting functions. A unique, proprietary
monolithic IC flip-flop is used as the storage elemento It
operates in any of the classic modes: R-S, J-K, T {Toggle},
and D {Delay}, using less external wiring than is required
with the traditional flip-flop design. The clocked set input
overrides the clocked reset input when both are simultaneously True, which simplifies input logic and wiring in most
cases. Another significant improvement is trai Img edge
triggering, which reduces the input settling time required
as compared to the traditional clocking techn iques. The
flip-flop also has unclocked inputs for clearing or presetting
between clock times, and its outputs are fu Ily buffered to
prevent feedback from output Ii nes to inputs.
An economical high-speed IC memory module stores 128 bits
for bu Ik storage and input-output bufferi ng.
Many supporting circuits are provided. Interface modules
couple T Series logic into other logic systems with either
positive or negative logi c levels. An adjustable-threshold
Schmitt- Trigger circuit accepts input of arbitrary waveshape
and converts to logic levels. One-shots provide accurately
adjustable delays. Several clock osci Ilator types provide
timing references. Digital-to-analog converters (with
reference voltage regu lators) provi de outputs that can drive
recording and display devices or controllers. Cable receivers
and drivers transmit logic signals over longer distances. A
variety of lamp drivers and display lamps are avai lable for
bui Iding displays. Relay drivers and relays are also provided, as well as a manual toggle-switch module.
All of these circuits are placed on the same size epoxyglass
etched circuit card, 4-1/4 inches high by 4-3/4 inches deep.
The card has 52 gold plated connector contacts to maintain
circuit accessibi Iity and stj II provide dense packing.
The cards plug into connectors which have reliable gold
plated, spring loaded, bifurcated (2-pronged) contacts.
Thirty-two modules can be placed side-by-side in 19-inch
wide mounting cases, which are avai lable in a variety of
fixed-mount and hinged models having either wire wrap or
solder tai I back panel pins. Each mounting case incorporates
a ground plane for noise immunity, and includes built-in
power busses. Ninety-module tilting drawer cases are also
offered. Any of the cases can be mounted in one of three
types of cabinets which have 19-inch RETMA rai Is, doors,
ac power wiring, swing-out frames, and optional side panels. A 300 cfm blower is avai lable for cool ing. An extender card is provided for troubleshooting.
Jumper wire kits, spooled wire, and wiring tools are aVCAi 1able to further simpl ify mechanical assembly. Blank cards
and dri lied breadboard cards with circuit etch are available.
Two basic power supplies are offered: a compact supply
which slides into a mounting case beside the modules, and
a high-output supply which mounts on standard 19-inch rai Is.
Both supplies can operate from a variety of input voltages
and frequencies, have overvoltage and overload protection,
and ±5% output regulation. Analog and large-system
supplies are also available.
A complete range of services is available, from consulting
engineering on application problems to a wiring service~
Complete and accurate documentation is provided on all
productso Application bulletins describe the various phases
of building a system, from logic design through documentation and fabricationo Reproducible vellum logic sheets are
provided for recording the interconnecting wiring and preparing wire listso
Thus T Series provides all of the components, information,
and services required to design and bui Id a very high performance digital system quickly and at reasonable cost.
GENERAL SPECIFICATIONS
Frequency Range of Clock: dc to 10 Mhz.
Minimum Input Timing Requirements, Typical: Flipflop dc input (mark or erase) must be True for at least
40 nsec. Flip-flop clocked input (set or reset) must
be True for 30 nsec. before clock changes from True
to Fa Ise, 5 nsec. thereafter.
ELECTRICAL AND ENVIRONMENTAL
Supply Voltages
+4 volts
+8 volts
-8 volts
I
dc, ±lO%
Minimum Clock Duration: Clock must be True for
30 nsec., False for 60 nsec. Triggering takes place
on falling edge when clock reaches the +2v (nominal)
switching point. Fall time is not critical.
Logic Levels
+4 volts nominal;
+3.6 volts to + 10 volts acceptable input
range to interface with other modu Ie
series;
+3.6 volts to +4.4 volts maximum output
variation.
Logic 0:
0 volts nominal;
+1 volt to -3 volts acceptable input
range to interface with other module
seri es;
o volt to +0.5 volts maximum output
variation.
+ 1.5 volts (greater may trigger True);
+2.5 volts (lower may trigger False).
The above represents a noise rejection of 1.5 volts
in either direction.
Loading
1 unit fan-out load is defined as 3.8 ma max., at
the conducting logic level (O volts).
Input Loading: Any logic input applies 1 unit load
to the preceding signal source, unless otherwise noted.
Output Loading: Buffer amplifier, inverter amplifier,
or one flip-flop output can each drive 14 unit loads.
(One flip-flop drives 28 loads, 14 with each output).
When buffer, inverter, or flip-flop outputs are wired
together to form a wired logic function (see page 13),
each output attached to the node absorbs 2 unit loads
due to the additional pull-up resistor placed at the
node.
Timing
Typical
2
o
0
Storage Temperature Range: -55 C to + 150 C.
MECHANICAL
4-1/4 inches by 4-3/4 inches, epoxy-glass, gold
plated etched copper wiring and connector contacts.
Connectors
52 gold-plated etched copper contacts mating with
spring-loaded bifurcated (dual prong) connectors.
Contacts are O. 15 inches apart; cards are spaced
0.50 inches center to centero Keys prevent wrong
insertion.
Back Panel and Wiring
Terminations for wire-wrap, solderless push-on, or
solder-tai I connection feed through epoxy-glass
back panel which is covered with solder plated etched
copper ground plane for high frequency shielding.
Four terminals from each card position are soldered to
ground plane. Power connections are made to etched
circuit busses on back panel, soldered to appropriate
connector terminals at each card position. Recommended Wire: No. 28AWG copper with cut-through resistant insulation (see page 20).
Mounti ng Cases
Stage Delay (circuit delay):
Buffered gate:
Flip-flop:
Full-Performance Ambient Operating Temperature:
o
0
o
5 C to 71°C (41 F to 160 F)
Card Size and Type
Noise Thresholds
At logic 0:
At logic 1:
Temperature
18 nsec
40 nsec
Worst-case
30 nsec
60 nsec
19-inches wide by 5-1/4 inches high, fixed or hinged (32 cards); or 90 card ti Itable pu II-out drawer,
19 inches wide by 8-3/4 inches high. Welded all
steel cases have ventilation slots, multiposition
mounting hardware, and optional filtered blowers.
MAKE OR BUY?
As a Iways, there are cost and performance trade-offs in the
decision to make or buy a fami Iy of logic modules. In some
cases there is an advantage to making modules and buying
cabi netry and other supporti ng components. Usua Ily, however, the costs are greatly underestimated and unexpected
performance difficulties arise during checkout, after most
of the work has been done and the schedul'ed time has passed. Many system qesigners have decided that their time is
better spent on system design, and that it pays to take advantage of the modu Ie maker1s expertise.
4.
The components are properly matched in terms of logi c
mix, loading, frequency response, delay times, noise
rejection, power requirements, reliability, environmental specifications, and mechanical compatibility.
5.
Supporting circuits, which are particularly subject to
unforseen problems, have been designed and refined
to properly perform their functions, with adequate
safety margi ns.
6.
Special-configuration modules can be built to your
specifications at moderate cost.
7.
Quick delivery. The user receives finished hardware,
usually within two weeks or less after receipt of order.
Contrast this with the months of manufacturing lead
time genera Ily required.
8.
Full quality control, of assembled units as well as circuit components. One year warranty against defects.
A complete module repair facility is available.
9.
Accessories are provided which might be considered too
costly in a "make" situation, such as extender cards,
jumper wire kits, relay and toggle switch modules, etc.
10.
Free application engineering is available, as well as
desi gn literature whi ch gives detai led instructions to
help avoid mistakes. The products themselves are thorough Iy documented.
SDS offers these benefits with its T Series module family:
1.
Exclusive integrated circuits, identical to those used
in the SDS Sigma computers, which perform better
than commercially available integrated circuits.
2.
The advantages of natural logic.
3.
Great savings in engineering time. Hundreds of computer systems have been bui It by SDS using T Series
modules. The associated problems in mechanical design, interconnecting wiring design, and manufacturing
techniques have been thoroughly worked out and solutions incorporated into the hardware.
11. Reproducible logic design and wiring record forms are
provided/with complete instructions on their use.
A Portion of The SOS T Series Production Line
Seventy incoming inspection tests can be performed on this T Series
monolithic integrated circuit in less than four seconds. The integrated
circuit tester is controlled by an SDS 92 computer that accepts or rejects
circuits being tested and keeps a record from which engineers can evaluate
the quality of circuits supplied by various vendors. Only a large volume
module manufacturer can support testing on this scale.
3
HOW T SERIES MEETS
SYSTEM REQUIREMENTS
SYSTEM DESIGN GOALS
Good system design demands high performance at low cost.
In many digital applications, prime PERFORMANCE goals
are:
1.
2.
Eliminate error (erroneous triggering)
a.
Minimize noise generation or pickup, and reject noise at logic inputs
b.
Maintain accurate timing
c.
Restore attenuated signals to retain signal
integrity
2.
4
3.
Minimize replacement part quantities through
standardizati on
Minimize equipment fai lure
a.
Avoid inconvenient or costly disruption of
system operation
b.
Reduce troubleshooting and replacement costs
These goals can be translated into specific hardware design
goals. Hardware can be lumped into six broad classes for
this analysis (see diagram on page 5). Each group has its
own effects on performance and economy. Each wi II be descri bed in sequence.
GROUP 1.
DECISION NETWORKS
Achieve fast system speed
a.
Achieve fast rise and fall times on logic levels
changes
b.
Minimize propagation delays in logic circuits
(stage delay) and interconnections (wiring delay)
c.
Minimize sum of delays in series in each logic
chain by reducing the. number of elements in
seri es.
The corresponding ECONOMIC goals are:
1.
e.
Minimize engineering and related technical labor,
particularly when building one-of-a-kind systems.
a.
Design logic simply and rapidly
b.
Plan and document interconnections quickly
c.
Avoid design of special circuits
d.
Assemble system quickly, conveniently, without
expensive labor
e.
Debug system quickly
f.
Eliminate callbacks to correct fai lures
Minimize hardware cost
a.
Minimize number of logic elements required to
perform a given logic function
b.
Minimize circuit and wiring cost per element
c.
Minimize cabinet hardware required (achieve
dense packi ng)
d.
Minimize cost of other accessories (power supplies, etc.)
Design of gate networks, usually with the aid of Boolean
algebra, is often the most time-consuming task. In many
cases gates and logic amplifiers also constitute the bulk
of the system hardware. Thus, for economy, standard gateamplifier configurations should be designed to: 1) minimize implementation time, 2) minimize the total number of
gates and amp lifi ers in the system, and 3) cost less per uni t.
Minimize Implementation Time
The best way to minimize implementation time is to make
all four logic functions, AND, OR, NAND, and NOR,
avai lable to the desi gner at the same low cost. T Seri es
does just this. The technique is called natural logic. Once
the Boolean expressions that define a logic function have
been reduced to simplified form the task is almost finished.
The designer then substitutes T Series gating structures directly for equation terms (see Example 1 on page 6).
Many other manufacturers urge the exclusive use of NAND
or NOR functi ons. They standardi ze on one i nverti ng gate
type to solve their problems rather than the user's. But, implementation with only NAND or NOR functions requires
additional equation manipulation. T Series eliminates the
extra design work by economically providing all four functions. A unique combination of standardized IC logic amplifiers (both inverting and non-inverting) with flexible,
discrete diode-resistor gates makes this possible.
SDS logic element modules contain a calculated mix of
gate combinations, using gates with 2 to 5 inputs. This
selection permits the designer to choose the right combinations of circuits from each card, reducing leftover circuits
in the rack and avoi ding many wiring problems. The 52
connectors per card permit full access to each circuit.
Load calculations are simple. All T Series logic elements
are rated in unit fan-out loads of 3.8 mo. Each diode gate
places 1 unit load on the previous amplifier output.
GROUP 1. DECISION NETW~KS (a\A'FE~ED
GATES, INVEUED GATES)
GROUP 2. 8ACK PANEL INTERCONNECTIONS (WIlING,
TERMINATIONS, AND GROUND CONNECTIONS)
~OUI'
4.
ST~GE NETW~KS
(FLIP-FLOPS)
AND
Q
OR
{Return - - ta gates} __ _
AND/OR
NAND
GROUP 3. TIMING NETWORK
NOR
AND/NOR
GROUP 5. POWER NETWORK
Supply Voltages
Power Ground
Power Supplies
GROUP 6. MECHANICAL HOUSING
Minimize Hardware Quantity
The number of gates and amplifiers required to implement a
given gating functi-on must be the lowest possible.
Amplifiers in particular should be minimized, since they
are the active (and therefore expensive) components. Primarily they furnish power to drive logic signals through the
gating structure. They also can perform logical inversion,
if required. Where adequate power is available, and amplifiers are used merely to perform logic inversions not required by the most simplified form of the equations, they create
an inexcusable expense. Example 1 explains how they may
be elimi nated.
Examp Ie 1 a Iso demonstrates another T Seri es feature that
eliminates amplifiers. This is the ability to perform 3-stages
of logic (AND-OR-AND) with 1 stage of amplification,
without loss of signal quality. The combination of the AND/
OR gate with wired-AND functions formed at amplifier outputs makes this possible.
The number of amplifi ers is also cut by maki ng output driving
current high; this permits each amplifier to drive more gates.
The fan-out from a T Series buffer or inverter amplifier is
14 unit loads, compared to 10 for many other types of integrated circuits.
These three T Series features, natural logic, three levels of
logic, and high fan-out, typically yield hardware savings
of at least 1/3 when compared to other module lines.
Minimize Unit Circuit Costs
SDS T Series achieves low unit circuit costs by integrating
the repetitive clusters of components that occur mainly in
amplifiers and flip-flops. The number of different integrated circuit types is kept small to simplify design and maintenance. By retaining the inexpensive gate structure outside the integrated circuit, T series retains the flexibility
of natural logic. Logic modules {excluding supporting
circuits} use only eight different components: 3 integrated
circuit types, 3 resistor types, 1 diode type, and 1 decoupling capacitor type. Individual circuit costs are thereby
held to a minimum.
5
EXAMPLE 1 - NATURAL LOGIC IMPROVES PERFORMANCE AND COSTS LESS
The monolithic integrated buffers, inverters, and flip-flops
of T Series are designed to accept inputs from diode AND
and OR structures. The unique SDS gating and logi c amplifier designs permit three stages of logic to be performed
with a single stage of amplification. Any active element
such as a non-inverting amplifier may have AND/OR input gates (two stages) and also may have its outputs pararaIleled with other active element outputs to implement a
third stage of logic.
Mechanized With NAND Logic
As an example, mechanize the following function:
Q = (ABC + DEH)
(FGIJ)
o =(MN) P
T Series natural logic permits direct substitution of hardware for equation terms, as shown below. Note that only
two amplifiers are required, one a buffer and one an inverter (NAND).
=(M+ N)P
Mechanizing the same function with NOR gates is simi lar,
but requires 5 amplifiers if all complements are available,
or 7 amplifiers if only the given signals are available.
If ANDing at outputs is allowed the implementation is
simpler, but still requires 4 logic amplifiers:
A
B
Buffered AND/OR Gate (on LTlO Module)
C
Alternate NAND Implementation
A
B
IT
E
H
AND Function
.-+-------00
C
IT
E
H
(MN) =
M +N
1
l>i--p-----~ J
Q=
IM+ NIP
AND '""0';00
NAND Gate (on ITII Module)
Mechanized With T Series Natural Logic
NAND functions are the most commonly avai lable monolith i c gate structures offered by other manufacturers. Implementation using NAND functions alone is more complex.
First, the equation must be manipulated to represent a
series of not-AND operations, of the form Q = Y·Z, where
y = '{·X, Z = T'U, _e..!.c. As an example let M = ABC,
N = DEH, and P = FGIJ. By DeMorgan's theorem, the
original expression may be rewritten
Q
= (M + N)P = (MN)P,
which puts it in the proper form for NAND implementation,
providing one more inverter is added since the last NAND
gate results in an inversion.
The structure that results using NAND gates is shown in the
next column. Note that it uses 6 amplifiers as compared
with 2 for the natural logic version.
6
For a cost comparison, if we assume that each amplified
logic function sells for roughly the same price, then the T
Series approach costs 1/2 as much as the best NAND implementation, in this typical example.
To facilitate a comparison of relative delay times, assume
that D is the average propagation delay of a diode AND
gate or a diode OR gate. Then 5D is a realistic approximation of the delay of an inverting or a non-inverting amplifier. To favor NAND logic, further assume that 5D is also
the delay of a monolithic NAND structure. The resulting
total delay for the typical circuit illustrated above is 7D
with SDS T Series, 20D with strai ght NAND logi c, and
lOD with NANDs ANDed at the output.
This example shows how one powerful feature of T Series
becomes apparent in a system application. Comparison
with other module lines on an individual circuit-for-circuit
basis reveals only part of the full merit of T Series modules.
GROUP 2.
INTERCONNECTIONS
3.
Reduce the possibi lity of poor contact mesh at connectors.
4.
Design the gates to have hi gh immunity to noise.
Sources of Digita I System Noise
Digital noise is defined as any unwanted voltage change on
the two standard logic levels. Noise can take the form of
an i nterna Ily generated short-durati on pu Ise or a long-duration d-c drift. In addition, there can be pickup of external
signals, radiated from nearby devices outside the logic
network. Noise introduces error into the data when gating
circuits interpret noise as logic changes.
High speed digital systems are particularly subject to pulsetype noise because logic levels change rapidly. All integrated circuits have inherently fast switching speeds, typically in the 5 to 15 nsec range, due to the microscopic
scale of the circuits. The ICs will switch at this speed
regardless of the system clock frequency. These fast level
changes produce high-frequency components wh i ch coup Ie
readily into the wrong circuits through interwiring capacitance. High speed systems are also sensitive to reflections
of leading and trai ling edges of pulses. The longer segments of interconnecting wiring act as transmission lines to
the high-frequency transient components of logic signals.
If these transmission lines are not properly terminated in
their characteristic impedances, various reflections can
interfere to cause erroneous swi tch i ng.
The ground system can also create its share of problems at
high frequencies. If inductive reactance is high, which
often happens when large loops are created by using wires
as ground returns, sharp noise pulses may occur at amplifier
ground connections, proportional to the product of inductance and switching speed, Ldi/dt.
Another cause of signal degradation is poor contact mesh
at the connectors which link the modules to the back panel
wiring. Poor mesh or corrosion can lead to intermittent
high resistance in logic signal lines.
Minimize Digital System Noise
These problems can be controlled through proper design of
the interconnecting wiring and the ground system, and by
establishing adequate :10ise thresholds at the gates. A
number of specific objectives are:
1.
2.
These design goals are all incorporated in T Series.
First, the ground for each modu Ie case is a plated flat
copper sheet attached to an epoxy-glass board that runs the
full width and height of the case. It has very low resistance, and the loops formed by the p lane and each i nterconnecting wire have low inductance, four or five times
less than would be the case without a ground plane.
The ground plane is used as a return path for currents in
back panel wires. This has the effects of shielding each
conductor from each other conductor and of turning each
conductor into a transmission line. If the back panel wires
are pushed down close to the shield plane the approximate
characteristic impedance that results is about 150 ohms.
Second, the terminating impedance at the far end of a long
back panel logic signal line may be made to approximate
line impedance by connecting a standard 220 ohm terminating resistor, greatly reducing the amplitude of signal reflections. This is possible with T Series because of the
high current drive. The discrete terminating resistors {and
gate resistors} are outside the integrated circuit container,
and power dissipation therefore is not a limiting factor.
Signal reflection problems often arise in systems that rely
exclusively on monolithic integrated circuits because the
integrated load resistances must be considerably larger than
line impedance in order to avoid excessive heating of the
i nteg rated c i rcu it package.
Third, poor contact mesh is eliminated with the T Series
connector design. The connector receptacles for module
contacts have one pair of bifurcated {forked conductor},
spring loaded, gold plated fingers for each contact.
Gold plati ng reduces the probabi Iity of high resistance
oxide formation. The fingers are so designed that they
cannot distort or lose their spring pressure. Bifurcation
provides redundant contacts, further reducing the already
remote probability of contact resistance problems. These new
connectors are manufactured to SDS specifications.
Prevent inductive or capacitive coupling among backpanel wires. Also prevent coupling between these
wires and sources of noise signals external to the system.
Design the ground system to have low inductance as
well as low resistance.
Wires may be attached to the connector pins {which protrude through openings in the ground plane} with reliable
wire-wrap, solder tai I, or the new solderless push-on terminals.
Design the back-panel interconnections to approximate transmission lines in order to achieve characteristics that are independent of frequency. Then terminate these lines {when long} with resistance close to
their characteristic impedance, to reduce pulse reflections.
The preceding describes the various techniques used to reduce noise. However, since some noise is inevitable, the
gates must be able to reject it. The gate switching point is
therefore placed at +2 volts and the uncertainty band about
this value is made as small as possible through tight component tolerance control.
7
I
Input (A)
logic I
--.,__f_F_l....----+-----+------,"""'"'.+---
+4v -----J~--+--::___
Uncerta i nty {
Bond: I volt
+2v
Logic 0
A-D>-
Noise Spike (Rejected)
I
~~~~ti
Ov
Circuit May Switch Here
I
Output (B)
I
+~--------+-+-~--------+-rt---~~-d-~---
+2v (50%) -
-
-
-
-
-
Ov--------¥-+----------+~~~-~~-+_4_~
Stage Delay
Noise Rejection At Gate Inputs
Noise Re jection Specifi cations
With a signal at 0 volts (logic 0 level), noise on a gate input of up to +1.5 volts will not cause the associated amplifier output to change state. Wi~h a signa I at +4 volts (Iogi c
1 level), noise on a gate input of -1.5 volts, which brings
logic 1 voltage down to +2.5 volts, wi II not cause the associated amplifier output to change state. This leaves an uncertainty band between +1.5 volts and +2.5 volts, within
which the amplifier output will switch (see above).
These thresholds are determi ned by characteristics of the
gate diodes, gate resistors, and the integrated amplifier
input circuits. The superior noise rejection properties of
T Series stem from close tolerance control, and the use of
higher, symmetrical noise thresholds.
GROUP 3.
SYSTEM TIMING (SPEED)
Propagation Delays and Clock Frequency
Stage delay is the time required for a signal to propagate
through a logic circuit. In an idealized sense, it is defined as the time lag between arrival of a step function at
a circuit input, and the appearance of a resultant step
function at its output.
Operating Frequency Range is the repetition rate range of
clock pulses over which the clocked system performs reliably in continuous operation while meeting all other
specifi cations.
Since system speed is delay limited it makes no sense to
emphasize high clock rate by itself as a desirable feature.
A clock osci !lator may easi Iy be designed to operate at
frequencies unheard of in digital work, but this is no
8
guarantee that a system may be operated at that frequency.
The clock must operate slowly enough to permit all logic
signals to propagate through an appropriate chain of gates
to the next level of flip-flops before the next clock pulse
occurs. In other words, the logi c circuits must have time
to complete their decisions before the clock causes the
flip-flops to store the results and commence the next series
of logical decisions. Thus to achieve a high clock rate,
series delays must be minimized.
The diagram, page 9, illustrates these points. Assume the
input is true. When a clock falling edge occurs flip-flop
FFl is set. Its output changes after internal (stage) delay
Dl. This signal is propagated through a series of wiring
paths, gates, and amplifiers with a total delay D2 + D3 +
D4, until it reaches another clocked element, FF2. Then
FF2 may be triggered by a second clock falling edge after
a stabi lizing period, D5, and the output is avai lable after
an internal delay D6. The clock pulse falling edges, which
trigger the flip-flops, cannot be allowed to occur at shorter intervals than the total series delay, Dt = Dl + D2 + D3
+ D4 + D5. Thus the maximum permissible clock rate in this
example is l/Dt. (This has no direct relation to the rate at
which a single flip-flop can be toggled).
System design can be varied to some extent to minimize
total system delay be performing whole functions in para"el
rather than in series. However, the minimum delay in any
single chain of elements as i "ustrated can only be reduced
(and clock rate raised) if:
1. Stage delays of flip-flops and amplifiers are
minimized
2. Wiring delays are minimized
3. Signal settling time is minimized.
Buffered Gates
(3 levels of logic)
Wiring
Clocked Element
Clocked Element
Wiring
Output
FFI
FF2
Stage Delay
Wiring Delay
Stage Delay
Wiring Delay
Input Settling Time
Output Stage De lay
After Clock
Dl------+-----D2------~----D3----~__---D4----_+-----D5----_+-----D6----~
Typical: 40 nsec.
Typical: 5 nsec.
Typical: 18 nsec.
Minimize Active Circuit Delays
Flip-flop delay is 40 nsec. typi cal, 60 nsec. worst case,
measured as follows:
.,..,.~~~,----------------------
+4v
CI~k p~r-::::::::::::::::::::.--ov-----
F. F. True Output
30 nsec.
Typical: 40 nsec.
Example 2 (on the next page) shows the re lations between
these factors.
The T Series active circuits have very short internal delays.
Buffer and inverter amp lifi ers have stage delays (wi th input
gates included) of 18 nsec. typical, 30 nsec. worst case.
I
Typical: 5 nsec.
50%
-#4'.~~.444-/-~'
I
Stage
I
f------- De lay ---------l
The logic designer has at his disposal the means to trade
between fan-out and delay to meet higher speed requirements. He can reduce rise time (at the cost of fan-out) by
adding a 5 unit load (220 ohm) terminating resistor to the
end of a line, decreasing the RC time constant.
On the 1 to 0 transition the wiring acts generally as an inductive load because the internal impedance of the driving
transistor in the conducting condition is very low. As mentioned, this delay is generally less than during the 0 to 1
transition, and is therefore not the limiting factor.
-50%
v
Minimize Delay Due To Wiring
The stage delays of the active circuits, given above, are
measured with the active circuits loaded to permit minimum
rise time at the output. In actual practice, when the active
circuit output is used to drive a load consisting of back panel wiring and gates, the rise time is extended. This difference in rise time is the delay due to wiring.
The factors which determine delay due to wiring are driver
output characteristics, propagation velocity of the wire,
length of line driven, and load characteristi cs. Length of
Ii ne and load characteristics are the major contributors to
wiring delays. Rise time is usually longer than fall time
because the driver output presents a high impedance during
the 0 to 1 transition, and a low impedance during the 1 to
o transition.
On the 0 to 1 transition the wiring acts as a capacitance
load on the driving circuit; wiring delay thus depends on how
fast this capacitance charges. The capacitive characteristic
is due not only to stray capacitance, but also to the fact that
each wire, which approximates a 150 ohm transmission line,
is always loaded with a resistance somewhat greater than its
characteristi c impedance of 150 ohms, and therefore behaves
as a capacitive load. If terminating resistance is decreased
to more closely match line impedance, the line behaves more
like a resistive load, but fan-out is sacrificed.
Typical back-panel wiring delays are 5 to 15 nanoseconds
when wiring is properly designed.
Minimizing Flip-flop Input Settling Time
A T Series flip-flop set or reset input must be True for at
least 30 nanoseconds before clock changes from True to False
and stay True for 5 nanoseconds thereafter. This is a relatively short settling time.
Conclusion
The example shown at the top of the page is a typical configuration, having three levels of logic (AND/OR/AND)
between clocked elements. The total delay that may be
normally expected under these circumstances is obtained
by adding the fi gures given:
Dt
= D1 + D2 + D3 + D4 + D5
= 40 + 5 + 18 + 5 + 30 = 98
nanoseconds.
This allows the use of a clock frequency of _ _1_----,:_
98 x 10- 9
= approx i mate Iy 10 Mhz.
As can be seen by comparing T Series delay times with
those of other modu Ie types, the stage delays, the wiring
delays, and settling delays are at a minimum. When the
design objective is maximum speed, T Series provides the
capabi lity to reach clock rates of lOMhz using normal
logic implementation.
9
EXAMPLE 2 - HIGH CURRENT DRIVE AIDS SYSTEM SPEED
Very high current-handling capability of T Series integrated circuits (up to 60 ma) is directly responsible
for two important advantages. One is the exceptionally high fanout of 14 (compared with about 10 offered
by other integrated circuit modules). The other is faster system speed.
Shown below is a first approximation schematic of an
integrated circuit driving an RC load.
+}
1M
~
J:
les f'
I
-=-
I
o Output
C '" C + C
t
L
s
Switch S and small resistance r roughly represent the
output transistor of a monolithic gate or flip-flop.
Symbol 1M denotes the maximum current handling
ability of the output transistor at the 0 level, or fully
1I0n ll condition {S closed}. Since r typically is small,
load resistance R and supply voltage V must be chosen
so that current through the transistor in the steady lion II
condition does not exceed the limiting va lue, 1M. Thus
with a given supply voltage, V, and a given maximum
current handl ing capabi lity, 1M, R = VJIM.
Cs represents shunt and parasitic capacitance of the
transistor. Load capacitance CL is wiring and pin
capacitance to ground, and depends on the length of
line driven and the number of connector pins. The
total, C t = C s + CL.
If the transistor initially is in the "on" condition, with
maximum current 1M, output voltage wi II be nearly zero.
GROUP 4.
STORAGE NETWORKS
If the switch is then opened (transistor cut off), output
voltage rises exponentially toward V. The rate of output voltage bui Idup is controlled by the time constant:
RC t
=
V
1M Ct·
This equation shows that with a given capacitive loading, the rate of change of voltage on the interconnecting wiring in going from 0 level to 1 level is controlled
by the load resistance, and therefore is limited by the
ratio of supply voltage to transistor output current handling ability. The lower the supply voltage and the
higher the current handling ability, the lower the load
resistance{R) that can be used, and therefore the faster
the rise times when current is turned off. SDS T Series
integrated circuits operate with a relatively low supply
voltage and have output transistors with very high output current handling ability, to quickly drive the system
through logic level changes.
The real test of any circuit is its speed under load. T
Series integrated circuits maintain their high operating
speed under conditions of capacitive loading that significantly slow less powerful circuits.
Th is example is simplified to illustrate the principle
involved. In practice, as many as 14 gating circuits
are connected across the output. During a 0 to 1
level change each conducting gate supplies 1 unit
load of charging current through a pull-up resistor
connected to +8v. The supply voltages, load resistance, and pull-up resistances all are chosen so that
steady-state current through transistor S does not
exceed limiting value 1M. The conclusions of a more
detailed analysis are the same: the higher the current
handling ability, and the lower the voltages used, the
faster the capacitive load can be charged.
back through internal cross-coupling to an input, since
noise may be present on the output lines.
A flip-flop should be both versatile and economical. If
possible, it should be designed to minimize interconnecting wiring in the majority of applications. It should have
high current output to eliminate the need for amplifiers to
drive the next stages of gating.
To enhance system performance the flip-flop should have
minimum internal delay, for high speed applications.
It should also have a short, precisely timed sampling period
{time during which it is sensitive to inputs} in order to avoid
erroneous triggering. It must also be insensitive to temperature variations and have excellent long term stability, to
prevent erroneous switching due to change in circuit characteristics. Level changes at an output should not feed
10
T Series Flip-Flop Economy Features
The basic T Series flip-flop achieves these goals. In
addition, its outputs can be tied directly to other flipflop or amplifier outputs to form an AND function without additional gates. This proprietary flip-flop is produced in quantity as a monolithic integrated circuit for low
unit cost.
The II set-overrides-reset" feature makes it possible to use
one flip-flop with little external wiring in four modes of
operation (R-S, J-K, T, and D). A study of systems has
revealed that, in the majority ~f cases, wiring is sim-
pier if the set input always overrides the reset input when
both are True simultaneously:
n+ 1
Period n
set input
reset input
The fl ip-flop maya Iso be used as astra ight c locked set-reset
{R-S)flip-flop with the sand r inputs activated directly, or
asynchronously with d-c inputs, mark {m} and erase (e),
which override the sand r inputs. Note that in clocked R-S
operation there is no ambiguity because set overrides reset.
Q output
T Series Flip-Flop Performance Features
0
0
Same as n
0
1
0
1
0
1
1
1
1
The SDS flip-flop has the same fan-out as an amplifier.
Each output can drive 14 unit loads.
Using this flip-flop, the reset output can be wired to an
AND gate at the set input to create a J-K flip-flop. A
conventional flip-flop requires a second gate to achieve
the same result. The SDS model avoids this second connection because set always overrides reset.
Conventional Version
50S Version, J-K
K
input
set
input
Q
reset
input
Q
Q 1-1--+--0
True
output
K
Q t--t--+--o
False
output
The same feature saves an inverter and reduces wi ri ng in
the Delay mode of operation. When the reset input is left
open (wired True) the set input operates the circuit as a delay flip-flop--that is, the Q output state follows the set input state, delayed by one clock pulse period.
SDS Version, Delay
Conventional Version
input o--...-----f
00-----1
input
Internal delay of the basic flip-flop is 40 nanoseconds
typical, 60 nanoseconds worst case. Since the minimum
clock True time is only 30 nanoseconds a simple toggle
circuit such as used in a counter may be operated at a
clock rate of 10 Mhz (100 nanoseconds) or faster.
Two features that prevent erroneous switching are a short
sampling period and trailing edge clock triggering. Input
signal conditions do not affect flip-flop operation, even
when the clock input is True, until 30 nsec. prior to the
clock1s falling edge. The SDS circuit is not the conventional type in which the first rank is set on the 0 to 1 clock
input transition, then the state is shifted to the second rank
on the 1 to 0 transition. The SDS technique of pure trai ling edge triggering provides timing security without undue
restrictions on clock pulse shape, and also allows maximum
input signal settling time between clocks.
Both flip-flop outputs are buffered within the integrated
circuit to completely isolate output signals from inputs.
GROUP 5.
POWER
D-c power for logi c modu les must have low drift. It must
also be free from transients, which could cause false triggering. Transients normally enter the system via the a-c
power line, particularly when high starting current devices
such as motors are on the same line. A module power
supply should also be designed to protect the delicate semiconductors from overvoltage or short circuits. Finally, the
supply should be capable of being rack mounted and operating with various popular line frequencies and voltages.
T Series Power Supplies
This feature also saves wiring in the Toggle mode. In this
mode the clock input operates the circuit, causing it to
change state at each c lock trigger.
50S Version, Toggle
Conventional Version
Qt--t---o
The PTlO (20-40 module supply) and PTl2 (125-200 module
supply) provide ±5% output regulation, with inputs of either
110 or 230 volts. Both provide overvoltage and short circuit protection. The PTlO plugs into a module mounting
case, requiring only 15 module spaces. The PT12 uses the
19-inch rack width.
QI-+_--o
clock
pulse
Power busses for +4v and +8v are supplied on the back plane
to minimize high frequency pickup.
Additional transient fi Itering is provided by individual decoupling circuits on each module.
11
GROUP 6.
MECHANICAL
Diode AND
Mounting hardware should be economical, lightweight,
rugged, easy to assembly and disassemble, and compatible
with industry standard hardware. It should be available in
several options for convenience. Design must take into
account electrical properties such as shielding and ground
currents as well as heat dissipation.
) +8v
.~ 2. 2k ohms
>
When
both A AND B are true (+4 volts),
Q is true. When either A OR B is false
(0 volt), Q is false.
O---I~.""-----j""'--C Q
T Series mounting hardware is based on a standard 19-inch
rack width. A welded steel, venti lated 32-module mounting case is avai lable with 2-position front or back bracket
mounts, or right/left vertical hinges. A 9O-module pullout drawer is available for high density applications.
The diode AND is represented by the half-circle symbol:
A·B
=Q
Cabinets, blowers, and many other mechanical accessories
are also avai lable.
Diode OR
OTHER COST FACTORS
Equipment fai lure can be costly when it interrupts operation of another system. SDS modules have a proven reliability record. Natural logic results in fewer logic components per system: Integrated circuits reduce the number
of wire connection points as much as 20 to 1. All modules
are worst case designed and 100% tested. Parts standardization and fewer components per system means smaller,
less expensive stocks of replacement parts.
(
+8v
If either A OR B is true, Q is true.
If A AND B are both false, Q is false.
2. 2k ohms:
•
A-
~
~
,..
y
) +8v
2. 2k ohms
~
.>
The diode OR is represented as follows:
Time consuming special circuit design is avoided because T
Seri es offers many supporti ng ci rcui t types that S DS engi neers
have found they need to bui Id a variety of systems, and because special circuit engineering is avai lable at reasonable
cost.
A+B
=Q
SUMMARY
Diode AND and OR Gates Combined (AND/OR Gates)
T Series modules are designed for low cost, error-free, high
or low speed digital systems that may be assembled qui ckly,
to operate reliably over long periods.
A number of important features such as natura I logi c, hi gh
current drive, back panel ground p lane, and set-overridesreset flip-flop, are unique to the SDS product line. They
are responsib Ie for economy and performance benefits.
A O---I!.---.
Q
If either A AND B OR D AND E
are true, Q is true.
ABOUT THE CIRCUITS ...
GATES
A
As mentioned previously, the T Series gating structures are
composed of discrete diode-resistor combinations which are
external to the integrated circuit buffers, inverters, flipflops, and other IC elements such as the 8-bit memory circuit used with the FT40 modu Ie. Thus the number of different ICs used is very small, but complete gating flexibi lity
is retained, along with better noise rejection. The structure
of the AND, OR, and AND/OR gates is shown at right.
12
Q
C
D
A· B+D·E = Q
LOGIC AMPLIFIERS
SDS 306 Buffer Microcircuit
In order to preserve good signal characteristics, in T Series
logic the output of a diode AND, OR, or an AND/OR combination never serves as input to another stage of diode gate
circuits. It is always connected to an active element which
restores the signal to the proper power level and filters out
random noise. Active elements include inverting amplifiers,
non-inverting (buffer) amplifiers, flip-flops and others,
usua lIy in IC form. The outputs of these active elements
drive other gate i ~puts.
Inputs
Typical
Discrete
0--+4---. AND-OR Gate
Structure
Output
+8v - - - - - - .
2.2K
ohms
TO-5 can connections:
Ie
The inverting logic amplifiers perform the same driving function plus the additional function of logical negation. The
circle shown on the inverter symbol indicates this.
For convenience, buffered or inverted gates are symbolized
with combined gate-amplifier symbols as shown ·on page 21.
SDS 305 Inverter Mi crocircuit
Inputs
+4v
Typical
Discrete
AND/OR Gate
Structure
Discrete
Pull-up
Resistor
560 ohms
Discrete
Pull-up
Resistor
560 ohms
2.2K
ohms
The most basic active elements are the non-inverting logic
amplifiers (buffers) which standardize the signal waveshape
and provide power gain (fan-out) for driving parallel loads.
The illustrations below show the essentials of the buffer and
inverter circuits, with inputs preceded by a typical discrete
AND/OR gate. Note that the logic line pull-up resistors
are also kept discrete, to obtain high current drive for fast
rise time and high fan-out without reducing reliability by
overheati ng the IC conta i ner. Th is a Iso prov i des for the
possibi lity of forming wired logi c functions (or expanding
gate functions) by tying several outputs together with only
one pull-up resistor on the line, thereby preserving fan-out
for useful loads. The model numbers SDS 305 and SDS 306
refer to the ICs, which contai n four buffers or four inverters
per one high-reliabi lity TO-5 can.
+4v
Specifications:
Turn-on delay 25 nsec. max. (50% points)
Turn-off delay 25 nsec. max. (50% points)
Typical stage delay: 18 nsec. average
5 nsec. min. (not guaranteed)
Output Drive 60 ma (16 Unit Loads)
Fan-out with 560 ohm pull-up; 14 Unit
Loads (pull-up absorbs 2 Unit Loads)
10
WIRED-OUTPUT GATES
With T Series it is possible to form gate functions by wiring
buffer or inverter outputs together, thus creati ng a new gate
function without additional hardware.
T Series logic outputs are normally constructed as shown below. When outputs are connected at point X an AND function is formed, as follows: when an integrated circuit output transistor conducts it shorts the logi c Ii ne to ground,
placing the line at logic O. This is an AND function because all outputs must be at logic 1 for the line to be at
logic 1.
2.2K
ohms
Standard T Series output connected to logic line:
+8v
Output
2.2K
ohms
*4 inverters
per TO-5 can
=
IC Specifications:
Turn-on delay 20 nsec. max. (50% points)
Turn-off delay 30 nsec. max. (50% points)
Typical stage delay: 18 nsec. average
5 nsec. min. (not guaranteed)
Output Drive 60 rna (16 Unit Loads)
Fan-out with 560 ohm pull-up; 14 Unit
Loads (pu II-up absorbs 2 Unit Loads)
560 ohm load
resistor (pull-up)
+4v
TO-5 can connections
10
I.e.
Optional connection to
other active element outputs.
13
If a II outputs are inverter outputs the wi red gate can be
considered a NOR as shown below.
The results of the decisions made by gates can be stored in
one of several devices. All of them have two stable states4'
and when implemented with ICs or transistors are called
flip-flops.
Wired NOR
A
01
~----11---- 03
C
STORAGE ELEMENTS
02
D
Output 01 = H, and output 02 = C:O. By connec~
Oland 02 on AND function is formed, 03 = (A' B) (C' D).
By DeMorgan's theorem, this is equivalent to
03=(A'B)+(C'D)
whi ch is a NOR function because it has the form 0 = X + y
(where X = A· B, Y = C ·D).
The basic wired functions that can be formed with two outputs are given below. Up to seven outputs, each having a
560 ohm pull-up, may be wired together.
-Wired-output Gates
A
o
C
Dc Flip-Flop
A simple dc flip-flop made by cross-coupling two buffered
NOR gates (inverted ORs) stores 1 bit. It has the disadvantage that inputs are sensitive to changes on the output
logic lines because ,the outputs are directly fed back to the
inputs without intervening buffers to isolate them. However,
in a suitable application the dc flip-flop reduces storage
cost. When the S input is made lrue (and R is False) the
unit assumes one state (Q True, Q False) and retains this
state after S becomes Fa Ise due to the feedback from Q.
The opposite conditions flip the unit to the opposite stable
state. When both inputs are made True simultaneously the
state is indeterminate, and if the True level on both inputs
is removed simultaneously the state is indeterminate. However, if one True level is removed before the other, and
the one remaining is held True for the duration of the circuit delay of the logic amplifiers (30 nsec worst case) then
the unit assumes the state determined by the last True input.
O=A'B'C ·D
(or O=A+B+C+D)
Simple dc flip-flop, using two gated SDS 305 ICs
D
A
O=(A'B) (C'D)
o
C
:.Q=(A+B) (C+D)
(or Q=AB+CD)
D
A
o
C
O=AB (CD)
0=
sR, Q = RS
(See FT57 description)
:.O=AB (C+D)
D
C locked Flip-flop
The trade-off for this additional logic capability is a reduction of fan-out. Each additional output absorbs 2 unit
loads due to the additional 560 ohm pull-up resistor that is
placed in parallel at the node. No more than seven outputs can be connected since seven pull-ups absorb 14 unit
loads, leaving 2 unit loads for useful output.
A more sophisticated flip-flop is used for most storage
applications. Its cost is only slightly higher than that of
the simple dc flip-flop because the entire circuit is placed
on a single IC chip. This flip-flop IC is designated the
SDS 307. Its characteristics are described in the diagram
on page 15.
However, if the additional pull-up resistors were not present there would be no fan-out reduction due to loading.
Then the upper limit of fan-out is determined by the drop
across the pull-up, which decreases noise margin in the
True state. A 560 ohm pull-up can handle 6 common outputs; 220 ohms can handle 16. On some modules the pullup is omitted to permit this (see IT14 module description).
As can be seen from the logic diagram of the IC, the flipflop is essentially a structure of NOR elements, but much
more complex than the simple dc flip-flop described previously.
The wired-output technique also allows gate expansion (increase of fan-in). For instance, four 2-input NORs can be
wired together at their outputs to form one B-input NOR.
]4
The flip-flop has a pair of dc inputs (called mark for dc set
and erase for dc reset) which can be used to make the flipflop behave like the simple dc flip-flop described before.
Their primary use is to override the clocked set and reset
(s and r) inputs, so that the flip-flop can be preset or cleared between clock trai Ii ng edges.
IC Specifications:
Clock requirements:
30 nsec. min. True (50% points).
60 nsec. min. False (50% points). 1 Unit Load, standard logic signal.
Set and reset inputs:
Must be stable from 30 nsec. min. before clock trai ling edge to 5 nsec.
min. after clock trailing edge. Flip-flop is insensitive to these inputs
at other times. Require 1 Unit Load each.
Mark and erase inputs: 40 nsec. min. True on mark input to set flip-flop;
40 nsec. min. True on erase input to reset flip-flop.
Require 1 Unit Load each.
Output timing:
15 nsec. min. after clock trai ling edge (50% points);
60 nsec. max. after clock trailing edge (50% points);
60 nsec. max. after mark-erase leadi ng edge (50% poi nts).
Output Isolation:
Completely buffered (cannot alter internal flip-flop state by output
collector grounding).
_
Output drive:
Fan-out of 16 Unit loads maximum from Q output; 16 from Q output.
When 560 ohm pu II-up resistors are used, fan-out is reduced to 14 Uni t
loads.
Circuit components:
IC contains 28 transistors, 36 resistors, and 10 diodes.
Set In
I
I
Reset In 0----1
Set
I Coupling
Reset Out
Clock 0----1
L __S~F_
Grd
10
+4V
Vee
I
I
I
I
I
I
I
I
Set Out
2ND
L_~S~F~_J
RA~K
Note: MARK and ERASE Inputs not shown
1STRANK
TO-5 Can Connections
Internal Logic Diagram
SDS 307 High Speed Flip-flop Microcircuit
15
When the mark input becomes True, the Q output becomes
True and stay~True regardless of the state of the mark input, and the Q output ~comes False. When the erase input becomes True, the Q output becomes True and stays
True and the Q output becomes False. If both dc inputs
become True simultaneously, both outputs will become
False as long as both inputs are held True. If one input
then becomes False the flip-flop assumes the state determined by the other input, providing it remains True at
least 40 nsec.
The gating to the flip-flop inputs is external to the Ie, just
as with buffers and inverters. The output pull-up resistor is
also external to the chip. Gates are placed on the module;
therefore, the IC inputs are not directly accessible at the
module connector. On many modules the reset (r) inputs
are wired True. That is, they are connected via circuit
etch through a resistor to +8 volts. This eliminates external
wiring to the r input in many applications. It is possible to
wire the SDS flip-flop in this unique way because a True
signal on the set (s) input always overrides a True on the
reset (r) input.
The set-override me'chanism and the other SDS 307 features
can be understood in terms of the IC logic diagram above.
The flip-flop is a dual rank configuration of NOR elements.
The second rank is a simple NOR flip-flop, coupled to the
output pins through buffers that each provide 60 ma (16 unit
loads), normally connected to ex~ernal pull-ups. The first
rank consists of two flip-flops, one for set and one for reset. The two internal lines which couple the first rank to
the second also connect to the clock inverter. When the
clock goes True these two lines are clamped to ground, isolating the second rank so that it holds its original state.
During this time, whi Ie clock is True, the set and reset flipflops are primed to the states of thei r inputs. When clock
fa lis they assume the new states and regai n control of the
second rank flip-flop. Note that the outputs change to the
new state on the clock trai ling edge. Inputs must be steady
for 30 nsec preceding and 5 nsec following the clock trai ling edge to permit first rank flip-flops to stabi Iize.
The set inverter will always override inputs to the reset inverter when the set input is True because it is coupled to an
output of the set flip-flop, forming a wired AND, while
the reset inverter is coupled to an input. This is the basis
for the set-override feature.
The second rank output is fed back to the first rank so that
the outputs remain unchanged when clock pulses occur with
both set and reset inputs Fa lse.
Note that the mark and erase inputs are not shown in the
diagram. Essentially they bypass the first rank, activating
the second rank directly, thus overriding the entire set-reset-c1oc k structure.
mentioned in the discussion of system requirements, and
wi II be reviewed in more detai I here.
A clock pulse, which is a logic signal that is sent simultaneously to all flip-flops in a synchronous system, serves
to inhibit storage of logic signals during the periods when
changes are taking place on the logic lines (the etched
circuit and back-panel wiring that connects all inputs and
outputs). The clock accomplishes this by limiting the time
that new information can be stored in a clocked flip-flop
via the set and reset inputs to the short duration (usua lIy
5 to 10 nanoseconds) of the clock trailing edge. While
the clock is high the second rank flip-flop of the SDS 307
retains its original state. It is only when the clock level
falls that the state of the first rank flip-flops is transferred
to the second. Then, while the clock level is False, the
set and reset outputs remai n as they are. The latter can be
verified by assuming the several sand r input possibi lities
and working through the logic diagram.
The use of the clock avoids timing problems due to logic
race conditions which can result when level changes arrive
at flip-flop inputs at different times, because of different
propagation delays in the electrical components in parallel
paths leading to the same flip-flop. A logic race condition
is present when one signal causes a flip-flop to change
state before all signals have had time to settle to their final
levels.
As an illustration, consider the simple network shown below, which uses the mark and erase inputs to illustrate the
operation of a flip-flop without a clock. Assume that flipflop C is initially in the reset condition. Also assume that
level A is initially False while level B is initially True.
Now if A becomes True and simultaneously B becomes False,
the new value of A arrives at gate N before the new value
of B arrives, because the B change is delayed in going
through gates Land M. Therefore, both inputs to gate N
are True for the duration of the delay. Since the mark input of C is at all times sensitive to the output of gate N,
flip-flop C wi II erroneously set if the delay is long enough.
When the new value of B finally arrives at gate Nt the desired input condition to flip-flop C is established, but an
incorrect result has already been stored in C and cannot be
reversed.
gate N
A--------------------------~
Q
I
I
I
Advantages Of Clocked Flip-flop Operation
The use of a clock, or system time reference, was briefly
16
I
I
Assume these inputs remain at 0 -
-
_
-
-
-
-
-
-
--
Obviously the problem is avoided if the output of gate N
is not allowed to change flip-flop C state until after all
signals have settled. The t~ailing edge trigger clo.:k technique provides the longest possible settling time.
RESET---......
Buffered Latch
Another storage element used in T Series modules is the
SDS 309 Buffered Latch microcircuit. This microcircuit
provides the storage capabilities of a DC flip-flop and at
the same time eliminates noise-induced delatching which
sometimes affects other types of latch circuits.
SET
Q
Q
One TO-96 case contains two buffered latch circuits. The
logic symbol, pin connections, and schematic representation of a buffered latch are given in the figure below.
Functional Waveforms
The buffered latch circuit has two modes of operation. One
mode is defined by the reset input (r) being true (1), the
other mode is defined by r being false (O). The functional
waveforms in the figure shown at right support the followi ng
explanation of the two modes of operation.
If the reset input (r) is true (1), then the output (0) follows
the set input (s). If the reset input (r) is false (0), then
the output (0) wi II go true (1) with the fi rst occurrence
of a set pulse and remain true so long as the reset input (r)
remai ns false.
GND
VCC
GND
VCC
BUFFERED LATCH SYMBOL
.-----00
PIN CONNECTIONS
(BOTTOM VIEW)
Qo----..........
SDS 309 Buffered Latch Schematic
17
This type of logic is commonly referred to as set-overridereset logic. If the set and reset inputs are true at the same
ti me, the output wi II follow the set input.
Fast-access Memory Element
SDS 304 Memory Microcircuit
(P)
Vee
POWER
CONTROL
INPUT
ADDRESS
~
-(P)
The FT40 module uses an integrated storage element which
can store eight bits on one integrated circuit. This proprietary IC contains 178 components on a single IC chip.
Sixteen ICs plus other logic circuits are mounted on one
module to provide addressable, clocked flip-flop storage
for 128 bits. The IC schematic is given in the diagram at
right. Refer to the FT40 description and module data
sheet for additional detai I.
ADDRESS ~
ADDRESS
BIT I
I
-
,L
___ ":"" _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1-f:::jF=::::::j~F1:~:: :~~:~:: :~I~ ~~~~_~~~::::I~
Other Circuits
The supporting circuits such as clock osci lIators, one-shots,
cable drivers, etc. use a combination of integrated and
discrete-component transistor circuits, as is generally the
practice where volume of usage or the need for linear
amplifiers makes an all-IC approach too costly at full
performance. One function that does lend itse If easi Iy
to integration, however, is the cable receiver circuit,
(SDS 308 Discriminator) which is shown below. Circuit
schematics of othe; circuits are given in the module data
sheets.
~~=t:l=R_ .::.::_-__:.--=1:: .::_-_-_-~~-~_:.::.:: _-_-eel=:: .::~~
==:=~= == =.::.::~~~_-_-_-_-_-=I= ===I~
'-t-1f------11-H1-i ::
BIT 5
:
(P)
- =~-.::.::=1= = ~-.::.:: ~~-6-'::'::':: .::---1= ===I~
'-t---fFf"L_==.::--.::.::I=.::.::.::.::.::::.::.::---------=I====I~
(P)
Vee
'----FFR_::.::.::.::---:I===.::----~~~==== ==1==:: ~
(P)
_____ -______ ~~ ~ ___________ J
dO
TO-IOO can connections:
DATA
INPUT
10
Not U..
v ee
I
Cont.ollnpvt
Reed/Write Input
a
2 Address
Doto Input
7
3 Address 1 Input
a Input
G<d
Data Output 6
4 Address 2 Input
5
SDS 308 Discriminator Microcircuit
Circuit schematic:
REF
Ie
Specifications:
Housing:
Two circuits per 10-5 can
Turn-on delay: 40 nsec. max. (50% points)
Turn-off delay: 40 nsec. max. (50% paints)
Typical operation: 25 nanoseconds
Output:
Same characteristics as SDS 306 buffer
10-5 can connections:
10
Signal Input 8
Reference Voltage 7
SIG
CR2
18
2 Signal Input
3 Reference Voltage
II. DESCRIPTIONS OF MODULES
SUMMARY OF MODULE AND
ACCESSORY TYPES
Accessory modules include cable plug modules, breadboard
modules, and an extender module. Other accessories include power supplies, cabinets, mounting cases, cables and
connectors, wire, and wiring tools. Accessories are described in Secti on III.
Modules are classified as logic element modules, storage
element modules, and supporting circuit modules. The logic
element modules contain AND, OR, NAND, and NOR
gates with non-inverting or inverting amplifiers. The storage
element modules contain flip-flops that are used for storage,
counting, and shifting. These two broad classes of modules
usually form the bulk of a system. Most supporting circuit
modules are used to communicate with other equipments or
with display devi ces. Supporting modu les include cable
driver and receiver modules; interface drivers and receivers
to communicate with logic at levels other than Ov and +4v;
Schmitt Trigger level detectors for accepting input of arbitrary waveshape; one-shots for precise control of delay; and
lamp drivers, re lay drivers, and D/A converters for drivi ng
display, recording, and mechani cal control devi ces. Also
included among supporting modules are the clock osci lIators,
which furnish the system time reference.
Table 1.
LOGIC ELEMENTS PER MODULE
Model
No.
With With AND With OR
Single
Inputs
Inputs
(NOR)
Input (NAND)
With AND/OR
Inputs
(AND/NOR)
BTIO
BTl 1
12
BTl2
BT13
BT18
10
BT27
BT31
These modu les carry the prefix B, I, or L. Some F prefix
modules, the buffered latches, also operate as logic element modules when the latch control inputs are grounded.
Table 1, below, lists the modules and shows the assignment
of logi c functions to modu les.
The AND/OR structures may be very simply converted to
pure ANDs or ORs by wiring AND inputs True (leaving open)
or wiring OR inputs False (grounding). Thus the BTlO,
ITlO, LTlO, and LTl1 modules can also furnish pure ORs or
NORs, if the AND functions are bypassed.
STORAGE ELEMENT MODULES
T Series includes a number of dense and powerful modules
which use the high speed, fully gated flip-flops. In addition four latch modules provide low cost storage. A high
speed memory module, the FT40, can furnish storage for
128 bits.
SUPPORTING CIRCUIT MODULES
OUTPUT INVERTED
OUTPUT NOT INVERTED
With
With
With
With
Single AND
OR
AND/OR
Input Inputs Inputs
Inputs
LOGIC ELEMENT MODULES
Two types of high density cable driver and receiver modules
are offered. ATlO, A T1l, A T12, A T52 and A T53 are i ntended for equipment using T Series modu les at both ends of
the cable. AT47 and AT48 use Ov/+8v logic levels on outputs and inputs respectively, and are designed to interface
through cables with other lines of modules such as the SDS
discrete-component C, H, and L Series.
12
14
BT33
TABLE 2. STORAGE ELEMENTS PER MODULE
FT26
FT27
lTlO
Model No.
lTll
8d
10
lT18
IT27
12
IT31
LT11
14
FTlO
Basic flip-flops with gated set and gated
clock inputs
FTll
Flip-flops with gating for counter modes
4
FTl2
Basic flip-flops with some gated set inputs
8
FT19
MulHfunction counter-register
Two 8-bit buffered latch storage registers
with fast/slow strobe option
16
FT26
Buffered latch multiplexing matrix with
4-bit AND/OR inputs
8
FT27
Buffered latch multiplexing matrix
with 2-bit AND/OR inputs
12
4
4
4
Ig
LT67
~
Arranged as 2 separate binary-to-octal decoders
c 16 elements in matrix form, 2 independent
d With Iatch inputs grounded
e Eight 4-input AND/NORs in 4 x 8 matrix
Two 4-bit switch comparators
f Two 12-input AND Gates
~ One 12-bit comparator
Four full-adders; two bits and
. carry in, sum and carry out
I Arranged as dual-input 12-bit
multiplexer
6
FT20
LT26
LT66
No. F. F.
or Latches
12
IT14
LTIO
Description
FT40
l28-b it IC Memory
FT43
Standard flip-flops with individual, strobed,
mark and erase inputs
8
128
6
FT56
Clocked flip-flops, with common clack line
12
FT57
D-c flip-flops (crass-coupled NORs)
10
FT58
Two 10-bit buffered latch storage registers
20
19
Two types Gf interface modu les are offered. NTlO and NTl1
will drive high level positive True logic (Ov/+8v). Any T
Series gate can receive high level logic up to +lOv, thus
no special interface receiver is required to work with NTlO
or NT11. NT33 and NTl8 interface with negative True
logic systems having logic levels down to -12v.
The average current specifi cation given is the current used
when the amplifier is on half the time and off half the time.
In a system of any complexity the average current instead
of the maximum current should be used to determine total
power requirements. This gives a more accurate indicati on of the actua I current requ ired.
The LT50, LT54, and NTl9 modules can be used to interface a digital system with a Teletypewriter or other keyboardprinter, as described in application bulletin 64-51-09.
Only one current specification is given for IC flip-flops
because one half of the flip-flop always conducts. Current
requirements are therefore independent of output state.
The adjustable AT22 Schmitt Trigger circuit converts any input waveshape to discrete logic level changes of Ov and +4v.
Module Dissipation Ratings
The ST44 Read-only Memory module recognizes one of eight
16-bit patterns and energizes one of eight lines upon recognition.
The OTl8 One-shot provides outputs of adjustable pulsewidth from 100 nsec to 20 fJsec and has provision for adding
external capacitance to permit pulsewidth up to 20 milliseconds. The OTl4 One-shot provides outputs from 50 fJsec.
to 2.2 seconds.
The QTl4 Lamp Drivers and RTl4 Rei ay Drivers handle up to
200 ma at 28 volts. QTl6 decodes 1, 2, 4, 8 inputs and
drives either ten lamps or ten relays.
DTl2 and DTl3 modules drive analog devices having up to
±20 volt input requirements, in a variety of operating modes.
The DT24 provides 9-bit and sign D-to-A conversion at
O. 1% accuracy. The WT49 Analog Power Regulator supplies
precision + or - 35 volts to sixteen DT24 modules.
The dissipation figure shown for a module is a worst-case
calculation derived from the voltage-current product plus
an allowance for IC or transistor dissipation due to load
current supplied to other modules. This figure may be used
to calculate maximum cooling requirements, but normally
wi" not represent the power requ i red by the modu Ie. If
average current figures are used, dissipation will also be
substantially lower than the dissipation values given.
SUMMARY OF LOADING AND
WIRING RULES
LOADING RULES
1.
Any Ov/+4v logic output may drive any Ov/+4v logic
input.
The KTlO module provides four SPDT mercury-wetted relays
with individual 2-input NAND drivers. The STl4 module
provides fifteen SPDT toggle switches on a card.
2.
Unless otherwise noted, every gate on a logi c Ii ne
places 1 unit load (3.8 ma) on the driver. Add all
gates on a line for total load.
The HT58 and HT72 are versati Ie Operationa I Ampl ifier
modules. The HT72 and AT69 provide sensitive differential
receiving capabi lity.
3.
Each logic line terminator (220 ohms, on XTl 0) absorbs
5 unit loads. Maximum is 2 per line, 1 per branch.
4.
Every T Series buffer, inverter, or fl ip-flop output drives
14 unit loads unless otherwise noted. Fan-outs of other
circuits are as noted on individual specifications.
5.
Buffer, inverter, and flip-flop outputs may be paralleled to form logic functions (see p. 13). Each one paralleled to the first decreases fan-out by 2 loads.
CT16 and CT10 crystal (or LC) controlled clock osci Ilators
provide clock signals in two ranges: 1.8Kc to 2Mc, and
1Mc to 10 Mc, respectively. AT23 and AT24 clock drivers
are used when large numbers of clock inputs are driven
from the same source.
SPECIFICA nONS
WIRIN G RULES
Maximum operating frequency, circuit delays, fan-out,
input loads, logic levels, and noise rejection are as described in General Specifications, p.1, unless otherwise
noted in the individual module descriptions.
General
1.
Use No. 28 AWG copper/irradiated KEL-F wire, pointto-point. Push close to ground plane. Refer to Application Bulletin 64-51-07 for a description of wiring
techniques.
2.
Layout connections for shortest total wire length.
Two branches per line is maximum. Two connections
per pin is maximum for both electrical and mechanical
reasons.
Modu Ie Current Requirements
The maximum current and maximum dissipation listed for
each module is for the case where all circuits are in the
state which draws maximum current. The inverter and
buffer circuits use maximum current when the output is
logic O.
20
With 3 stages use terminator on at least 1 line if tota I
length of any line reaches 60 inches. With 1 or 2
stages no termi nators are required.
3.
Ground unused flip-flop set inputs (wire False) to
avoid set-1 permanently overriding reset. Ground unused flip-flop dc inputs. Ground unused OR inputs.
Leave open (True) unused AND inputs.
3.
4.
Power pins are: +4v, pin 49; +Bv, pin 51; -Bv, pin 50.
Ground pins are: 0, 16, 32, 4B. The +4v, +Bv, and
ground wiring is built into back panel plane. The -Bv
must be wired separately to pin 50 when required.
Operation Above 2 Mhz Clock Rate
Simplified Rules For Safe Operation Below 2Mhz
Because of relatively long settling time (>500 nsec) T Series
logic wiring for use with clock rate under 2 Mhz is simple.
Observe these rules:
1.
Maximum wire length is 60 inches per branch (max. 2
branches per line).
2.
Three stages of seri es buffers/i nverters between fli pflops is maximum unless sum of delays is calculated to
be under 500 nsec tota I.
As clock rate is increased less delay can be tolerated in the
wiring since active circuit delays are fixed. Line terminators decrease delay on the 0 to 1 transition by decreasi ng
line capacitance charge time. At clock frequencies over
2 Mhz wiring rules are more stringent than those given above,
and delays may have to be calculated. Refer to Application
Bulletin 64-51-04 for a technical discussion of delay problems and for additional data on wiring delays.
In genera I, lines under 1B inches need not be term i nated
but lines over 60 inches must be terminated. Between these
boundaries termination is optional and depends on both propagation speeds desi red and the magnitude and timi ng of
reflections.
LOGIC SYMBOLS
The SDS logic symbols shown below are used throughout this catalog.
MIL-STD-B06B logic symbols are shown beside the SDS symbols for comparison.
GATES WITHOUT LOGIC AMPLIFIERS
MIL-STD-806B EQUIVALENT
SDS SYMBOLS
Q=A· B·C
AND Gate
~ ~--+--+-D
OR Gate
O=A+B+C
-0 Q
A
A
Q
AND/OR Gate
Q=A·B+C ·D
Q
C
C
D
D
LOGIC AMPLIFIERS
SDS SYMBOLS
Buffer
Inverter
Without pull-up
resistor on the module
A~G
A~O
MIL-STD-806B EQUIVALENT
Q=A
Q=A
or Q=A
A~O A~O
Buffer
A--Q---CY-a
A-Q--t>o-o
Pull-up resistor is connected externolly.
Add note to symbol s shown above.
Inverter
21
GATES COMBINED WITH LOGIC AMPLIFIERS
MIL-STD-806B EQUIVALENT
SDS SYMBOLS
Buffered AND
Gate (BAND)
Q=A· B·C
Buffered OR Gate
Q=A+B+C
Q=A·B·C,
or Q=A· B ·C
NAND Gate
or Q=A+B+C
Q=A+B+C
or Q=A+B+C
NOR Gate
or Q=A·B·C
A
A
Buffered
AND/OR Gate
Inverted
AND/OR Gate
(AND/NOR)
Q
Q
Q=AB+CD
C
C
D
D
A
A
Q=AB+CD
Q
or Q=AB+CD
or Q=(A+B)(C+D)
C
Q
C
D
D
LOGIC FUNCTIONS FORMED AT OUTPUTS
A T Series feature is the logic function created when two or more amplifier or flip-flop outputs are tied directly together.
The rule is that any element having a false output will couse all outputs connected together to be false.
SDS SYMBOLS
MIL-STD-806B EQUIVALENT
Q
Q=A·B·C·D
Q
or Q=A+B+C+D
C
D
Q= (A B)(C D),
Q
C
or Q=(A+B)(C+D),
Q
or Q=AB+ CD
D
A
Q
C
D
22
Q=(AB)(CD)
or Q=AB (C+D)
Q
OTHER AMPLIFIERS
SDS SYMBOLS
MIL-STD-806B EQUIVALENT
Interface Cable Driver
(on A T14 Module)
Interface Cable Receiver
(on AT15 Module)
~
Emitter Follower
(on DT12/13 Modules)
*Letter is placed inside Symbol to denote function
SDS IC FLIP-FLOP
SDS SYMBOLS
MIL-STD-806B EQUIVALENT
D
Signal Relationships:
X
= Y= D + AC
(C is falling edge of clock pulse)
x
A
Y=
X = E + BCA
Q
c
C
y
TRUTH TABLE
Terminal Designations:
Period n
"mark" input (unclocked set input)
n+1
s
r
Q
0
0
Qn
0
1
0
*1
0
1
*1
1
1
"erase" input (unclacked reset input)
s = set input (must be clocked)
reset input (must be clocked)
clack input (falling edge of clock is used)
Q = set output
Q=
reset output
Terminal Designations:
SD
reset direct (equivalent to SDS e)
S
set (equivalent to SDS s)
reset (equivalent to SDS r)
C
Q
'Note the unique characteristic of the SDS flip-flop: the set input,
when True, always causes the Q output to go True (when clocked),
regardless of the state of the reset input. Mark and erase inputs,
however, always override set and reset inputs. When both mark and
erase are True simultaneously both outputs are False until one input
goes False; the flip-flop then assumes the state determined by the
other input, which was True last. Inputs must be wired Folse (grounded) when not used. Reset input is wired True (left open) in set- Trueoverrides-reset applications.
TERMI NA TORS
SDS SYMBOL
9
Line Terminator
(absorbs 5 Uni t Loads)
set direct (equivalent to SDS m)
RD
clock (equivalent to SDS c)
1 output
o output
CABLE CONNECTORS
MIL-STD-806B EQUIVALENT
!
Front edge
cable connectors
23
MODULE DESCRIPTIONS
CABLE RECEIVERS
AT10
Model A Tl0, A Tll, and A Tl2 modules, together wi th ET
cable components, constitute a high-speed logic signal interconnection system for distances up to 200 feet. Logic
levels of Ov/+2v are transmitted over 33 ohm coaxial cable.
14-conductor cables are clamped to the front edge of each
modu Ie with ETll connectors.
The ATlO module contains 14 identical cable receiver circuits which switch when input exceeds the +O.54v switching value. Output is not inverted. Up to 25 receivers can
be connected to the output of 1 cable driver, because input
capacitance is very low.
10Mhz
20 nsec typ., 40 nsec worst case
Ov (Logic 0), +2v (Logic 1)
+0 . 54v, ±O. 1v
- 1 . 5v to +4. 4v
50 I-Ia per rece iver
8 pf max. per rece iver
Ov (Logic 0), +4v (Logic 1)
14 Unit Loads (53.2 ma) each
output
+4v, 165 ma av., 256 ma max.
+8v, 11 4 ma av., 153 ma max.
-8v, 87 ma av., 117 ma max.
2.5 watts av., 3.55 watts max.
Max. Data Rate:
Circuit Delay:
Input Logic Levels:
Switching Threshold:
Input Range:
Input Current:
Input Capacitance:
Output Logic Levels:
Output Drive:
Power Requirements:
Dissipation:
>~
-
>~
>;,t
~ -
>.~
>~
>~
>.~
;~~-
>~~-
>.~
>~
>.~
>~
>~~
>;Y ~ >~~
-
>~~
>~ ~
-
-
;~~
>~ ~
-
-
>~
;~~
-
>.~
>~~
>.~
>;,}
~
-
>~
>~~
-
-
LOGIC DIAGRAM, ATlO
CABLE RECEIVERS/DRIVERS
ATll
A Tl1 contains 14 identical pairs of driver-receivers. Driver
outputs are on the same term i na Is as rece iver inputs to reduce space and connectors. Receivers normally use input
from drivers at other cable locations, not from the same
module. Circuits are identical to A Tl 0 and A Tl2.
Power Requirements:+4v, 1.05 amp. av., 2.045 amp. max.
586 ma max.
+8v, 392 mao av.,
- 8v, 87. 5 ma. av., 11 7 ma max.
Dissipation:
Other Specifications:
LOGIC DIAGRAM, ATll
24
15.2 watts max.
See A Tl 0 or A Tl2
CABLE DRIVERS
AT12
Max. Operati ng Freq. :
Circuit Delay:
Input Logic Levels:
Input Current
Output Logic Levels:
Output Loading:
Model A Tl2 contains 14 identical cable driver circuits
which accept standard T Series Ov/+4v logic level input
and convert to Ov/+2v logic level output. The A Tl2 is
designed to drive ATlO or ATl1 receiver circuits, and has
front-edge contacts for ETl1 connectors.
Driving capability depends on cable attenuation. Maximum length is 200 feet of 33 ohm coaxial cable. Any number of cable drivers can be placed on one cable but only
one driver can be raised True at one time si nce outputs add.
10 Mhz
5 nsec typ., 10 nsec worst case
Ov (Logic 0), +4v (Logic 1)
9 Unit Loads (34 rna)
Ov (Logic 0), +2v (Logic 1)
16.5 ohms to ground; use two 33
ohm cab les or 1 cab Ie and 1
dummy load (ETl3)
+4v, 805 rna av., 1.78 amps
max.
+8v, 278 rna av., 433 rna max.
11.65 watts max.
Power Requirements:
Input wiring restrictions: back panel wiring cannot exceed
18 inches, and no terminator may be placed on input line.
Dissipation:
Refer to Accessories section for cable and connectors.
~ ~~ ~> 4>-t> ~
~ ~> ~ ~> ~~
+fIV
~
1I1l
~>
~>
4>t~
~
o
R9
M
H>
E >
A>
p >
L>
G >
C >
B
N
K
>
F >
>
51 494832 16 0
LOGIC DIAGRAM, A Tl2
SCHMITT TRIGGERS
AT22
Circuit Delay:
Input Load to Common:
Model AT22 contains two dc-to-lO Mhz Schmitt Trigger circuits. Three input ranges are provided. Each Q output
rises to +4v when input exceeds the adjustable trigger level
and returns to Ov when input drops below the adjustable
hysteresis level, which is always more negative than the
trigger level.
Reso Iuti on:
Drive Capabi lity:
Power Requirements:
The Schmitt Trigger is essential for squaring sine wave or
other non-squarewave input. It is also used as a pulse amplifier. A regulator on the module keeps thresholds stable.
Outputs are fu II y buffered.
Dissipation:
Circuit 2
Circuit 1
Trigger Adjust
Trigger Adjust
R4-1
Hi level in
Med. level in
Lo level in
41
38
37
31
Schmitt
Trigger
Hysteresis Adjust
5051494832160
Q
Hi leve! in
Output
Med level in
30
R13-1
-t +r IV1111 ~
25 nsec typical
±5v range, 1k ohms
±15v range, 3k ohms
±50v range, 10k ohms
±5v range, ±50 mv
±15v range, ±150 mv
±50v range, ±.5v
12 unit loads per output
+4v, 10 rna
+8v, 35 rna
-8v, 50 rna
0.750 watts max.
Q
Lo level in
10
12
14
R4-2
3
Schmitt
Trigger
Tab Ie 1. Trigger and Hysteresi s Ranges
Q
Output
21
Q
R13-2
HyslE;resis Adjust
Trigger
(True Threshold)
Hysteresis
±5v
.5v to 1.5v
±15v
1.5v to 4.5v
±50v
4.0v to 17v
LOGIC DIAGRAM, AT22
25
AT23
HIGH CURRENT CLOCK DRIVER
The AT23 is a non-inverting high current driver which can
provide clock pulses for twelve 33-ohm clock lines simultaneously. AT23 modu les can be paralleled to obtain driver
power for additional clock lines. To eliminate skew at the
clock source, several internal buses are brought out to pins,
for connection to parallel AT23 modules.
Because of high power dissipation, an AT23 should not be
mounted in proximity to AT23 1 s or other high dissipation
modules.
However, AT23 modules connected in parallel
should not be separated by more than one module space to
minimize skew. The use of ZT23 cable plug modules to inter-leave parallel AT23 1 s is recommended.
To prevent pulse width narrowing at very low duty cycles,
connect unused input diodes to +4v through 2.2K ohm resistors.
Turn-on time (typical):
Turn-on time (minimum):
Input-output pulse width
difference (pu Ise narrowing):
Load imposed by each
AT23 input:
Output drive capabi Iity
(max. ):
Input logic level s:
Output logic levels:
Power requirements:
Dissipation:
-Bv +8v +4v
1111111
51
49
48 32 16 0
Output Bus
f
LOGIC DIAGRAM, AT23
26
6 nsec
1 unit load (3.8 ma)
1.4 amps (368 unit loads)
Logic 1: +4v
Logic 0: Ov
Logic 1: +4v to +4.7v *
Logic 0: Ov
+4v, 642 maj +8v, 539 maj
-8v, 150 ma
8.8 watts max.
*Dependent on loadj output can go as high as one diode drop
(+.7v) above +4v because of inductors in the output circuit.
Parallel Interconnection Buses
50
25 nsec
15 nsec
AT24
MEDIUM CURRENT CLOCK DRIVERS
The AT24 contains 6 non-inverting medium current drivers.
The AT24 module will drive standard 100-ohm wiring or33ohm cable. Each driver circuit can be used to ampl ify clock
pulses or other signals.
AT24 module drivers should not be paralleled when driving
clock lines because of the possibility of skew at the clock
source. Use the AT23 modu Ie for high current requirements.
Because of a high power dissipation factor, AT24 modules
should not be mounted in proximity to other AT24moduies
or other high dissipation modules.
Turn-on time (typical):
Turn-on time (min):
Input-output pulse width
difference:
Load imposed by each
input term:
Output drive capabi Iity:
Input logic levels:
Output logic levels:
Power requirements:
Dissipation:
25 nsec
10 nsec
8 nsec
1 unit load (3.8 ma)
340 ma per driver (88 unit
loads)
Logic 1: +4v
Logic 0: Ov
Logic 1: +4v
Logic 0: Ov
+4v, 330 ma; +8v, 544 ma;
-8v, 150 ma
7.9 watts max.
TIT~
50 51 49 48 32 16 0
Circuit 1
43
Circuit 4
20
Circuit 2
35
Circuit 5
11
Circuit 3
27
Circuit 6
31
LOGIC DIAGRAM, AT24
27
AT47
8-VOLT INTERFACE CABLE DRIVERS
The AT47 module has 7 cable drivers for driving 6 gates
each, with 0 and +8v leve Is, such as are used with SDS
C, H, and L series modules. It also contains 1 buffer amplifier. Each cable driver circuit is driven by a T Series
3-input buffered AND with Ov and +4v logic levelsi one of
the three inputs is common to all gates on the card, for
use as a common control line.
The drivers are designed to drive 33 ohm cable. Rise and
fall times are about 1 f.1sec to reach 50% of logic level.
If cable length is less than 60 feet the cable may be connected directly to an SDS Model ZX13 cable plug module,
which is compatible with the C, H, and L Series modules.
Power Requirements:
Dissipation:
+4v: 90 maav., 119mamax.
+8v: 135 ma, -8v: 85 ma (pin 50)
2.1 watts max.
2
44
- 8v --050
+8v--051
42
+4v
4
40
---<>49
~
48
32
16
o
LOGIC DIAGRAM, AT47
8-VOLT INTERFACE CABLE RECEIVERS
AT48
Model AT48 module has 18 cable receiver circuits which
will accept logic signals at Ov and +8v levels from a 33
ohm cable input. These circuits may be driven by the
Model AT47 cable driver or by Ov and +8v logic signals
from SDS B, C, H, K, L, or X Series modules. The output
of each receiver is a standard T Series inverter output with
Ov and +4v logic levels, capable of driving 14 unit loads.
~
~
~
~
~
~
~
~
Switching Time:
Ton .:s.. 35 nSi Toff:s' 35 ns
Power Requirements:
+4v: 145 ma av., 192 ma max.
-8v: 15 ma (pin 50)
+8v: 95 ma
1 .5 watts max.
Dissipation:
~
~
~
~
LOGIC DIAGRAM, AT48
28
~
~
~
~
~
~
-8v --050
+8v--<> 51
+4v ---<>49
~481632
0
AT52
TWISTED-PAIR LONG LINE DRIVERS
The AT52 Long Line Driver module contains seven SDS 309
buffered latches for signal storage and seven complementary
line drivers for signal transmission.
Logic One (1):
A pair of AT52 Long Line Drivers is designed to work in
conjunction with a pair of AT53 Long Line Receivers and
ET32-XXXX Long Line Cable Assembly to transmit 14 differential digital signals over distances as great as 2000 ft.
at data rates as high as 500 Khz (l.0 Mhz at 1000 ft.).
The system is designed for economy and freedom from
crosstalk or injected noise.
Input Loading:
Standard Diode Gate:
Driver Disable Pin (42):
Common Gate Lines
(pins 26 & 34):
Seven unit loads
Output Logic Levels:
Logic Zero (0):
Logic One (1):
1 Mhz
Between 8 and 60 nanoseconds
Length:
a to 0.5 volt
4.0 ± 0.4 volts
Power Requirements:
Must be a relay closure
to ground.
One driver can drive
one twisted cable pair
connected to one A T53
Cable Receiver circuit.
O. 6 to 1.3 vo Its
6. a volts nominal
(steady value)
Allowable Cable Lengths:
Cable:
Line Driver Circuit Specifications:
Input Logic Signals:
SDS 309 Gate:
Logic Zero (0):
Logic One (1):
Driver Disable Pin (42)
Logic Zero (0):
One unit load
17 ma
Output Signal Characteristics:
Module Fan-Out:
One driver has an additional circuit tied to its outputs
that allows the outputs of that circuit to be disabled by
grounding pin 42 through external relay contacts in the
event of power fai lure at the driver. Under this condition,
the complementary driver circuit is disabled with both
outputs grounded. This condi tion can then be detected
by the fault detection circuit on the AT53 receiver module
to revea I that power has fai led at the driver.
Max. Data Rate of Module:
Circuit Delay of Module:
Must be an open line or
pull-ups to +8 volts or a
minimum of 560 ohms
to +4 volts.
SDS 149444 (used in
Model ET32-XXXX
Long Line Cable Assembly)
70 to 2000 feet at
a to 500 Khz
70 to 1000 feet at
a to 1. a Mhz
+4V, 192 ma nominal,
230 ma max.
+8V, 600 ma nominal,
720 ma max.
6.6 watts max.
Dissipation:
12
NOTE:
c. p. o. == Common point a
c. p. b. == Common point b
SDS
309
SDS
309
14
c. p. b.
SDS
309
SDS
309
SDS
309
21
c.p.o
25
39
42
DRIVER DISABLE
SDS
309
SDS
309
28
38
Q
c. p.o.
,8V +4V
!!
51
49
GND
045162432404148
c. p. a
LOGIC DIAGRAM, AT52
29
AT53
LONG LINE RECEIVERS
A pair of AT52 modules and a pair of AT53 modules together
with one ET32-XXXX Long line Cable Assembly constitute
a balanced twisted pair long line transmission system for 14
digital signals. This system has a bandwidth of 500 Khz at
2000 feet and 1 . 0 Mhz at 1000 feet. It prov ides ± 7. OV
peak common mode re jecti on.
The AT53 Long line Receiver module contains seven differential receivers with input termination resistors and
eight inverter circuits. One line receiver has an additional circuit tied to its inputs, used to detect the fault
condition that occurs when both lines to the receiver
input either open or become zero volts. Under this condition, the detection circuit output goes to the logic
zero (0) state.
Data Rate:
Allowable Cable Length:
Fai lure Detector De1ay:
Dependent on input cable
length. 1 Mhz max.
(l000 feet of ET32 cable).
70 feet to 2000 feet of ET32
cable.
Between 1 and 10 jJsec.
~4
+4V
OV
Output Drive of Receiver:
11 unit loads each output
except pin 1 which is 1 unit
load.
Standard T Series
Inverter Specifications:
Power Requirements:
(Entire Modu Ie)
Dissipation:
;~
>~
~7
~
~
>~
). 1
~11
10
10
Fault
Detector
>~
LOGIC DIAGRAM, A T53
+4V, 252 ma av., 315 ma max.
+8V, 115 ma
-8V, 240 ma
4. 1 watts max.
~
NOTE:
Termination resistor network at input of each receiver circuit not shown.
30
Depends on length of cable;
guaranteed to operate when
driven by AT52 module
between length limits listed
above. (6V differential at
driver end and approximately
2-3V at receiver end).
±7V peak
Logic One (l):
Logic Zero (0):
~
~~
40
Common Mode Re jection:
Output Logic Levels:
~
~
~
~
~
Input Signal Levels:
~I11IUI !
GENERAL PURPOSE DIFFERENTIAL RECEIVERS
The AT69 module contains nine independent logic circuits
with differential inputs (see connection diagram). When
the voltage at the + input becomes at least 1 volt more
positive than the voltage at the - input, and remains in that
condition for at least 100 nsec, the output goes to logic 1
(high) level. It reaches this level 170 nsec after the input
rising edge. When the differential between + and - inputs
falls below 1 volt, the output falls 100 nsec later. An open
circuit at the inputs also results in an output of logic 0 (low).
Either a negative-going or positive-going signal is acceptable, since the circuit is sensitive only to the relative
polarity of the input pair.
A differential receiver normally receives digital signals,
over shielded cable or twisted-pair lines. A differential
receiver has the advantage over a single-ended receiver
that it re jects common-mode noise and ground potential
differences. Common-mode voltages are those which appear
between the two ends of a cab Ie but are common to both
of the input leads of the cable. With the AT69, a common
mode rejection range of ±volts is provided when +8 volts
and -8 volts are used as +V and -V. This rejection range
can be increased to ±12 volts with ±V at ±15V.
The maximum input data rate is 4 Mhz. A fi Iter network
across the input terminals re jects all transients of up to
100 nsec duration, and should be removed when operating
above 1 Mhz. This fi Iter furnishes an ac noise re jection
which is in addition to the dc noise margin provided by the
1 volt threshold.
The optional resistor Rl (see connection diagram) functions
as an impedance matching resistor for the input cable, and
is provided by the user to match his particular cable impedance.
The AT69 output high logic level is determined by the supply
vol tage connected to pin 26, which for T Series use is +4v.
Both input terminals and the Vref terminal are available at
front-edge cable connectors (--j») as well as backpanel
connectors ("",). The Vref terminal must be connected
externally to +V as shown in the connection diagram. The
circuit wi II not operate without the jumper.
AT69
The AT69 uses the same basic etched circuit board and
most of the same circuit components as the HT73 Comparator
Module.
Matching Resistor
Furnished by User
(Optional)
r-,
I
I
I
V logic
High (+4v)
Coaxial or
Twisted Pair
L~Rl
Out
,.....--J\I\I\-
-V
Connection Diagram, One Circuit
Max. Data rate:
Differential threshold
(at + input with respect
to - input):
Max. input voltage:
Input impedance
(without Rl):
Input pulsewidth
(with filter in place):
Common mode re jection range
(with ±8v at +V and -V):
Common mode re jection range
(with ±15v at +Vand -V):
Fan-out, into T Series:
Propagation delay, at 25 0 C:
To rising edge of output
To falling edge of output
+4 volt supply (Vcc):
+8 vol t supply:
-8 volt supply:
Dissipation, per module:
4 Mhz
1 volt ±20%
10 volts
200K ohms min.
100 ns min.
±5 volts
± 12 volts
37 unit loads
170 ns typo
100 ns typo
60 ma typo 68 ma max.
220 ma typo 270 ma max.
16 ma typo 25 ma max.
2.27 watts typ.,
3.07 watts max.
31
Vref
V logic
high
+V
+v
V logic
high
+V
V logic
high
+V
V logic
high
<
<
<
-v
-v
-v
V logic
high
+v
A
Vref
+V
V logic
high
-v
+V
V logic
high
A
Vref
+V
<
<
<
-v
-v
+V
-v
V logic
high
:: IC3 1, :
r
<
90
1"
Aoolog
Ground
<
-v
LOGIC DIAGRAM, AT69
32
-v
+V
-v
Note:
For T Series Differential Receivers
operation, connect Vref to +V, and
connect V logic High to +4 volts.
V logic
high
BT10
BUFFERED AND/OR GATES
Eight AND/OR gate structures are on this module. Each
circuit consists of two 3-input AND gates, the outputs of
which are ORed and amplified. One input on each AND
gate is shared with 3 other circuits. The circuits are designed to implement expressions of the type A· B· C+D • E' F.
By connecting BTl 0 circuit outputs together an AND function can be generated, of the type ( A • B • C + D • E • F )
(G' H· I + J. K· L). The ITlO module has logically equivalent inputs and common connections but its outputs are inverted (refer to IT10 description).
Power Requirements:
Dissipation:
+4v, 95 ma av., 156 ma max.
+8v, 45 ma av., 57. 5 ma max.
1.2 watts max.
41
+r:flill ~
51 494832 16 0
12
LOGIC DIAGRAM, BTlO
BTll
BUFFERED AND GATES
The BTl 1 has an assortment of Buffered AND gates for general purpose use. There are two 3-input circuits; three
4- input circuits; and seven 2- input circuits. The AND
functions can be expanded by connecting buffer outputs to
gether. The ITll modu Ie has the same configuration of
gates but all model ITll amplifiers are inverters (refer to
ITll description).
Power Requirements:
Dissipation:
+4v, 142 ma av., 234 ma max.
+8v, 33. 6 ma av., 43 rna max.
1.45 watts max.
30
~ ~ ~ ~
31
17
21
~
~
29
19
24
22
28
25
27
33
41
46
11
~ ~ ~
42
45
+r+tlill ~
51 494832 16 0
~ ~ ~
43
37
36
LOGIC DIAGRAM, BTll
33
BINARY-TO-OCTAl DECODERS
B112
BT 12 has 2 independent binary decoders. Each accepts 3bit inputs and produces an output on one of 8 pins. In addition, Enable input prevents any outputs from being True
when it is Fa Ise. Enable is used when decoding numbers
larger than 3 bits. Using Enable as the fourth input, 2
circuits can decode a 4-bit input so that only lout of 16
outputs is True at one time. Each output drives 14 unit
38
35
33
26
T
40
25
39
44
"2
45
42
36
47
"4
Power Requirements: +4v, 182maav., 312mamax.
+8v, 45 ma av., 57. 5 ma max.
Dissipation: 1.88 watts max.
IN
34
Enable
43
Enable input requires 8 unit loads, all others 4 unit
CODING CHART
OUT
IN
loads.
loads.
4
"4
2
"2
1
T True:
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
0
1
2
1
1
0
1
0
3
1
0
0
1
0
1
4
1
a a 1 1 a
a 1 a a 1
a 1 a 1 a
5
1
10
4
Enable
3
13
0
0
1
OUT
IN
OUT
6
6
T
+8v~51
+4v --049
14
"2
15
12
7
~481632
0
22
"4
24
46
Circuit 2
Circuit 1
LOGIC DIAGRAM, BTl2
BUFFERED MATRIX
B113
BT13 has a 4 x 4 matrix which can (1) select one of up to
4 groups of 4 bits each, or (2) generate up to 16 discrete
outputs from a 4 x 4 matrix input, or (3) provide 18 general purpose amplifiers when all common lines are left open
(True). IT13 has the same input logic configuration but
outputs are inverted (refer to IT13 description).
Power Requirements:
Dissipation:
+4v, 230 ma av., 375 ma max.
+8v, 50. 4 ma av., 64. 6 ma max.
2.2 watts max.
33
27
~
~ ~
26
25
+4v --049
23
22
43
6
LOGIC DIAGRAM, BTl3
34
+8v~51
24
48
32
16
o
BUFFERED AND GATES
BT18
This module contains ten AND circuits intended for
general purpose use. Each circuit can drive 14 loads.
Outputs may be paralleled with other circuits; however,
each paralle led output decreases the output drive
capability by 2 unit loads. The IT18 module has an
identi cal gate configuration but all outputs are
inverted (refer to IT18 description).
~~
~
~
26
iP
13
~
50
46
4
23
V
39
~
~
~
11
45
1.07 watts max.
3
8
12
40
Dissipation:
15
14
38
+4v, 136 ma av., 21 9 ma max.
+8v, 28 ma av., 36 ma max.
~
~
36
25
44
43
Power Requirements:
+8v--051
+4v --<>49
t§
48
32
16
o
35
22
47
LOGIC DIAGRAM, BT18
BUFFERED OR GATES
BT27
The BT27 module contains ten 3-input OR gates and two
2-input OR gates intended for general purpose use. Each
circuit can drive 14 loads. Various methods are avai lable
to expand an OR gate, to form OR-ANDS or by adding a
second level of OR gates. The IT27 module has an identical gate configuration but all outputs are inverted (refer
to IT27 description).
47
37
23
44
33
14
Power Requirements:
+4v, 142 ma av., 234 ma max.
+8v, 95 ma av., 122 ma max.
Dissipation:
2. 1 watts max.
7
~ ~ ~ ~
43
29
13
~ ~ ~ ~
41
27
11
40
26
10
38
24
21
+8v--051
+4v--049
~481632
0
~ ~ ~ ~
LOGIC DIAGRAM, BT27
35
BT31
BUFFERED AND GATES
This module contains fourteen economical 2 - input AND
gates and two l-input buffer amplifiers intended for general
purpose use. Each circuit can drive fourteen unit loads.
Gates can be expanded by paralleling outputs, with the
usual fan-out restrictions. The IT31 module has an identical gate configuration but its outputs are inverted (see IT31).
Power Requirements:
+4v, 182 ma av., 312 ma max.
+8v, 45 ma av., 57. 5 ma max.
1 . 88 watts max.
Dissipation:
The BT33 contains twelve buffered AND-OR gates arranged
as a 12-bit multiplexer. It accepts two 12-bit inputs and
produces a single 12-bit output, whose state is controlled
by the condition of the two control lines. If one control
line is True and the other False, output equals the input
whose control line is True. If both controls are False out~ut is all zeros. If both controls are True, each out~ut bit
IS the OR of the two corresponding input bits.
+4v, 141. 5 ma av., 234 ma rr
+8v, 67 ma max., 86 ma max,
1 .79 watts max.
Power requirements:
~
~
~
~
Dissipation:
~
Al 0-:.:..- - - - - - I
~
A2 0--+--+-----<
42
01
43 _ + - -_ _--1
Bl0-:-:44
~
~
BT33
DUAL-INPUT
12-BIT MULTIPLEXER
02
45
B2 0 - - + - - - + - - - 1
34
A3 0---+---+---1
~
~
~
1
~
~
3
A4
21
36
0::..:..-+--+----1
04
35
B4 0::..:..- + - - + - - - - 1
~
40
42
03
33
B30--+--+-----<
22
/l5
24
0::..:..- + - - + - - - l
B5
0---+--+-----<
05
26
27
~
A6 o---I--+--~
~
06
B60-=-:-28_+--+-_--1
15
AI 0-:..:..- + - - + - - - - 1
87
07
14
0---+---+---1
1
AS 0-;..:...8- + - - - + - - - 1
88
17
0---+--+----1
A9 0-=---1--+---1
10
B9 0-..:...-+--+----1
A10 0-1,",-1- + - - - + - - - 1
~~.1~
BIO
~
12
All 0-=--+--+----1
Bllo--+-4---I
+i'14'~
A12 o-'--+--+--~
51 49 48 32 16 0
B12 0-=--+--+----1
CONTROL A
46
CONTROL B 0-4_7 _ _...J
LOGIC DIAGRAM, BT31
On
(CONTROL AIIAnl
+
(CONTROL BIIBnl
rfJ
5149483116
LOGIC DIAGRAM, BT33
36
a
HIGH FREQUENCY CLOCK OSCILLATOR
CllD
The CTlO contains a 1 Mc to 10 Mc oscillator, a pulse
shaper, and a gated clock amplifier (driver). asci IIator is
controlled by adjustable LC or optional crystal. External
jumpers select range (Table 1). When crystal control is desired specify frequency. When using crystal, first adjust to
approximate frequency by LC control with jumper 45-20 in
place. Then remove jumper 45-20 and insert crystal. Pulsewidth control adjusts duty cycle from 40% to 60%. This adjustment is frequency dependent.
Driver control gate permits frequency division.
used gate inputs.
This module requires two card slots.
Frequency range:
Stability, crystal operation:
Crystal freq. accuracy:
Driver fan-out:
Shaper fan-out:
Gate inputs:
Power requirements:
(at 50% duty cyc Ie)
Logic wiring can be used as clock bus. Terminate logic
wire clock bus with 220 ohm resistor on XTlO modlJle. lines
should radiate from driver in equal lengths to avoid clock
skew.
TABLE 1.
~
Jumpe l
6.20 to 10 MHz
None
48
3.90 to 6.30 MHz
39, 44
32
2.48 to 4.00 MHz
40, 44
o
1.56 to 2.53 MHz
40, 41, 44
1.0 to 1.59 MHz
40, 42, 44
16
Dissipation:
1 Mhz to 10 Mhz
2 p. p. m. per 0C
±0.02%
60 unit loads (278 ma)
7 un it loads (26.6 ma)
2 unit loads ea.
+4v, 40 ma
+8v, 130 ma
-8v, 60 ma
1.7 watts max.
Fine Adjust (LC Control)
LC CONTROL RANGES
Frequency Range
-8y ---050
+8y---051
+4y ---049
Ground un-
Coarse Freq. Jumpers
LOGIC DIAGRAM, CTlO
MEDIUM FREQUENCY CLOCK OSCILLATOR
The CTl6 has a 1 Mhz to 2 Mhz osci IIator with 50% duty
cycle squarewave output, and a seven stage down-counter.
asci !lator is controlled by LC or crystal. For hi gher output drive capability add buffer modules. Clock should be
bussed via logic wiring. A 220 ohm terminator must be
used (on XTlO). lines should radiate from driver in equal
lengths to avoid clock skew. When usi ng more than one
frequency take into account the phase shift through the
ripple counter.
Cl16
Frequency range:
Stability, crystal operation:
Crysta I freq. accuracy:
Fan-out:
Power requirements:
(at 50% duty cycle)
Dissipation:
7.8 Khz to 2 Mhz
2 p. p. m. per °C
± 0.02%
Pins 35, 36, 38, 40, 42, 44
45: 13 loads; a II others, 10
loads
+4v, 240 ma
+8v, 85 ma
-8v, 52 ma
2. 1 watts max.
LC
46
Q
~
Osci Ilator
1.
9
\- _ _ _ _ _ J \... _ _ _
Jumper
for Xtal
T
10
47
35
30
4
2
f/64
f/128
~
Jumper
for LC
f/2
f/4
f/8
f/16
f/32
Note: T is a toggle input.
LOGIC DIAGRAM, CTl6
ITTITTP
50 51 494832 16 0
37
A-BIT AND 6-BIT D/A CONVERTERS
OT12,OT13
Each module has two D/A converters designed for low cost
applications where high accuracy is not required. DTl2
converters accept 4 bits; DT13 converters accept 6 bits.
The DTl2-1 and DTl3-1 modules also include a reference
regulator, and buffer amplifiers, as shown in the diagrams
below. The DTl2 modules can also be connected (with additiona I resistors) to accept BCD inputs.
The converters operate with unipolar output. With additional resistors they can also provide bipolar output. The
conversion table below, gives output value vs. input code.
Note that in the bipolar mode the input codes for negative
values must be in 2 1 s complement form if binary, and in
lOis complement form if BCD.
An external reference source of maximum +20v on + E ref
(plus additional -20v on _Eref for bipolar output) can be
used. If the +5v internal reference source is used, one
buffer amplifier must be connected between regulator output and converter E~ef input. The same amplifier can also
supply 14 additional converters, but where isolation between converter units is essential a separate buffer amplifier
between regu lator output and Eref input shou Id be used for
each converter. A buffer can be used on Eout when Eref is
+5v or less, or in bipolar operation with +5v and -5v reference voltages.
25
24
23
22
21
20
0
0
0
0
0
0
I
I
I
I
I
0
LSB
I
I
I
I
I
I
0
s~9n
*n
d
~
number of magnitude bits
= number of decimal digits
Eout, BCD Operation
Eout, BINARY Operation
INPUTS
CONVERSION TABLE
Input-Output Specifications
1. Converter (switches and precIsion resistor network)
a. Accuracy: ±1. 0% relative to reference voltage
b. Switch offset: +50 millivolts typical
c. Output impedance: 5K ohms ± 1%
d. Inputs: standard T Series logic levels, 1 unit load
e. Output voltage: as given in conversion table
f.
Conversion rate: 400 Khz max.
g. Settling time (to ±150 mv of f.v.): 2.5 jJsec after
input signal completes switching. Open output.
2. Buffer ampl ifier (em itter follower)
a. Accuracy: ± 1.0%
b. Output range: -1.67v to + 5v
c. Offset: ±100 millivolts typical
d. Loading capability: ±10 ma max.
e. Input impedance: 150K ohms m in. at dc
f. Output impedance: 50 ohms typical
g. Settling time: 2 jJsec. max. to ±50 mv of final
value, 1 jJsec. max to ±150 mv of final value
3. +5v reference regu lator
Output voltage adiustable to ±O. 1%; current: 0.2%
Power Stlecifications (max.)
1. Each bit (switch and resistor): +8v, 7.6 ma;
-8v, 1 ma (pin 50)
2. Each amplifier: +8v, 50 ma;-8v, 50 ma (pin 50)
3. +5v reference regu lator: +8v, 35 ma
UNIPOLAR
UNIPOLAR
Full Scale
0.6 Eref (1-1/10 d )*
0.6 Eref/lO d
Eref (1-1/2n)*
Eref/2 n
o volts
o volts
magn i tude bits
BIPOLAR (MSB is sign bit)
BIPOLAR (MSB is sign bit)
It
0
0
0
0
0
0
+Full Scale
1/3 (+Eref)(1-1/2 n)
0.2 (+Eref) (1-1/IOd)
0
1
1
1
1
0
+LSB
1/3 (+Eref/2 n)
0.2 (+Eref/lOd)
0
1
1
1
1
1
0
o volts
o volts
1
0
0
0
0
0
-LSB
1/3 (-Eref/2 n)
0.2 (-Eref/l0d)
1
I
I
1
1
1
-Full Scale
1/3 (-Ere!)
0.2 (-Eref)
6 Ckt.
2
E
out
Expand
-E
BCD PROVISION
r::i..
I
g :;
X"
L- - - -
Expand
a
:
:
I
I
I
I
I
I
-12112~~2~
BCD PROVISION
~
.
E :;
x"
a
l
I
I
I
L----14i-9~bl~
(Voltage ref. source and amplifiers on DT12-1 module only)
~
'1
38
Eref
+5v
46
-Bv - - 0
!
+8v--o!
ref
(Voltage ref. source and amplifiers on DT13-1 module only)
~
~
E
ref
+5v
28
OT24
9-BIT AND SIGN DjA CONVERTER
Resolution:
Full scale voltage output:
(Op. Amp.)
Full scale current output:
The DT24 is a high accuracy 9-bit and sign digital-to-analog converter with ±4 ma or ± 10 volts (±20 ma) bipolar output. The module includes a resistive ladder network, switches and drivers, and an output ampl ifier. It accepts 2 1 s complement values of input code to produce a negative output.
It can be recal ibrated to accept lis complement input.
10 bits including sign
± 10 volts
±20 ma with Ope Amp.,
±4 ma without
2.6 I-Isec per volt of output
change (worst case) plus
5 f-lsec settling time to reach
within 10 mv of final value
<100 nsec for a transition
from + fu II scale current to
- full scale current
0.1% relative to reference
vol tage
0
DoC to 55 C
* +35v, 10.5 ma; -35v, 7.5 ma
** +15v, 36 ma; -15v, 36 ma
+8v, 73 ma; -8v, 25 ma
+4v, 65 ma
2.2 watts
Vol tage output conversion
time:
Either vol tage or current output is avai Iab Ie, both with O. 1%
maximum error referred to reference source, over the full
temperature range. The voltage output is obtained by feeding the current output into an IC operational ampl ifier, provided on the board, which has a fu" scale output of ± lOv
and can drive a 20 ma resistive load with 5,000 pf of parallel capacitance.
Current output switching
time:
Accuracy:
Temperature range:
Power requirements:
Input logic levels are standard T Series, 1 unit load per input. The WT49 regulator module is available to provide
±35 volts reference source. Wire the reference voltages
and -8v to pins shown in the logic diagram below.
Dissipation:
A companion module, the FT58, is available for use as a
data register (refer to FT58 description). The FT58 contains
two lO-bit buffer registers which may be used as single-rank
storage for two DT24 1 s, or double-rank storage for one DT24.
*
The output voltage is related to digital input as shown in
Table 1.
DIGITAL INPUT
From WT49.
**
Table 1.
Sign
Bit
MSB
0
0
2-2
Output Ope Amp. voltages, from PT23.
Input vs. Output Relations
ANALOG OUTPUT VOLTAGE
2- 8
111 1111
LSB
1
2'5 Complement
Fs-E2
2
0
0
0000000
1
FS
9
0
0
0000000
0
1
1
11 11111
1
1
(
+E (REF)
(+35v)
~47
~
,,46
)9
)8
~33
)1
)6
~24
)2
)3
~
I
~
1
11 11111
0
6
1
0
0000000
0
2
0
9
9
502
mV
1'5 Complement
Fs-E2
2
9
502
95i2 v
10
mv
10
mV
FS
Ov
+0
1{)v
-0
-Ov
FS
- 29
- -10v
FS
- 28
- -10v
-FS
-10 v
9
2
512
256
FS
- -10v
9
512
2
502
-Fs+E2 -95i2 v
29
LSB
2
3
Precision
Resistor
Ladder,
Switches,
and
Drivers
4
5
6
7
14
12
~
~
Current
Output
Current
Input
Voltage
Output
8
9
MSB
Sign
-E (REF)
(-35v)
oS
Analog
ground
Digital +4v
ground
-8v
+8v
+15v
-15v
LOGIC DIAGRAM, DT24
39
FT10
BASIC FLIP-FLOPS
FT10 contains 6 identical flip-flops designed for basic operations as shift registers and binary or BCD counters, either
parallel loaded or preset by mark inputs. Terminator is for
33 ohm coaxial clock cable which is used primarily in
large computers. Ground m and e if not used.
Maximum Operating Frequency:
Mark and erase min. True time:
sand r min. stable before clock falls:
sand r min. stable after clock falls:
10 Mhz
40 nsec
30 nsec
5 nsec
C lock min. True duration: 30 nsec
Clock min. False duration: 60 nsec
Circuit Delay:
40 nsec typical,
60 nsec worst case
1 Unit load per gate
Input Current:
14 Uni t loads per output
Fan-out:
+4v, 236 ma av., 360 ma max.
Power Requirements:
+8v, 84 ma av., 107.7 ma max.
2.53 watts max.
Dissipation:
39
Common Erose
Common Clock
O;!~~-+---+--------+--""""'--------+---6-------'
t):!l!...--4-----------...+-----------........-----___h
Input
75 ohms
41 o---J\I\I\r- +4v
Clock Cable
Terminator
LOGIC DIAGRAM, FTlO
FT12
GATED FLIP-FLOPS
FT12, wlTn 8 flip-flop circuits, is designed for applications
requiring a large number of economical storage elements
on one module. Enough basic gating issupplied for shift
registers and binary or BCD counters. Synchronous or bidirectional versions are mechanized by adding gate modules. Reset input is wired True on all 8 circuits (not shown).
Since set-1 overrides reset, set input controls reset state.
With external gating this circuit can perform all the func-
tions of two FT11 modules. In many applications it can
also take the place of the FT10, at lower cost per flip-flop.
Terminator is for 33 ohm coaxial clock cable, primarily
used in large computer systems.
Ground mark and erase inputs if not used.
Timing, Input Current, Fan-out same as for FTl O.
Power Requirements: +4v, 314.4 ma av., 480 ma max.
+8v, 112 ma av., 143 . 6 ma max.
Dissipation: 3.37 watts max.
TITTTr51414132110
75 ohms
47~+4v
Clock Cable
Terminator
LOGIC DIAGRAM, FTl2
40
FTll
4-BIT HIGH SPEED COUNTER
FTl1 contains 4 fl ip-flops and gating designed for high
speed, synchronous counting functions. The modu Ie can
function as a binary or BCD up- or down-counter, or can
be used as a combination counter/shift register. It can be
preset at high speed. As with other SDS flip-flop modules,
only one logic polarity is required for presetting since set-1
overrides reset. Reset input is permanently wired True, but
is not shown in the logic diagram, below.
as clock. The 4-input gates are wired to properly condition the clock inputs for operation in the desired counting
or shifting mode, whether binary, BCD, etc.
Common dc reset (without clock) is accomplished with the
Common Erase input. This input must be Fa Ise (ground) when
not used.
Terminator is for use with 33 ohm coaxial clock cable, primari Iy used in large computers.
Presetting is accomplished through the 2-input gates marked
LOAD Control and PRESET Data. Common Control and
COUNT Pulse inputs must be False. Data is entered into
the PRESET Data inputs, LOAD Control is made True, and
LOAD Pu Ise is used as a clock. Note that the counter need
not be cleared before presetting.
Max. Operating Freq:
Timing and Delay:
Input Current:
Fan-Out:
Power Requirements:
Counting is accomplished with Common Control True, LOAD
Control False, LOAD Pulse False, and COUNT Pulse used
Commono4~1~~
Dissipation:
10 Mhz
See FTlO specifications
1 Un it Load per gate input
14 Unit Loads, pins 45, 24, 22, 2;
13 Unit Loads, pins 46, 33, 23, 1
+4v, 157.4 ma av., 240.2 ma max.
+8v, 58.9 ma av., 75.4 ma max.
1 .72 watts max.
__________________- .____________________~__________________--,
Control
+8v~51
+4v
---<>49
~
LOAD
L. C.
P. D.
Control
PRESET
Data
48
32
16
o
L. C.
P. D.
LOAD
Pulses
COUNT
Pu Ises o=-=+--..-v
75 ohms
47 o---J\I\I\r-- +4v
Common~44L-
________~____________________~____________________*-__________________~
Erase
Clock Cable
Terminator
LOGIC DIAGRAM, FTl1
41
MULTIPURPOSE COUNTERS/REGISTERS
FT19
The FTl9 contains two independent groups of four flip-flops
each. With external connections as listed in the table below the modu Ie can function in these modes:
1.
2.
3.
4.
Storage and Control - data read in and out in parallel
Counter, presetable: binary up, binary down, BCD up,
and binary up-down (no loss during mode change)
Shift Register: all combinationsof serial, parallel in/out
Shifting Up-Down Counter (accumulator)
a. Load by: parallel entry, shift in, or count up
b. Count up or down as desired
c. Read out by shifting serially, reading in parallel
or counting down (no loss during mode change)
It is a Iso possible to form dua I 4-bit combinations because
PINS
CONTROL
42, 12
38, 8
24, 14
50
30 .6
44
46
20
45
19, 15,11,47
33, 36,26, 1
Count 1 Count 2
Shift 1, Shift 2
Up 1, Up 2
Down
Clock
Q in 1
Q"I"nI
Q in 2
Common Reset
Mark (dc set)
Jumper these pins with wire on
bock ponel:
GENERAL
STORAGE
Two 4-bit counters (binary or BCD) or shift registers
One 4-bit up-counter and one 4-bit shift register
One 4-bit shifting up-counter (accumulator),
one 4-bit shift or store, or one 4-bit up-counter.
1.
2.
3.
Fan-Out: 14 Unit Loads {53. 2 ma), pins 3, 5, 25
13 Unit Loads (49.4 ma), pins 31, 7,27
12 Unit Loads (45.6 ma), pins 41, 43, 37, 39, 35,
21, 23, 13, 17, 9
Power Requirements:
+4v, 314 ma av., 480 ma max.
+8v, 157 ma av., 201 ma max.
3.88 watts max.
Dissipation:
For clock and timing specifications refer to FT10
CONNECTIONS OR LOGIC LEVEL REQUIRED
COUNTDOWN COUNT U-D
COUNT UP
SHIFT
BINARY
BIN., REVERSE
BINARY
REGISTER
F
F
T
F
F
F
F
F
Shift pulse in
Reset input
IS_erial data m
D
D
D
Q4 (pin 25)*
D
TT
TT
40 nsec T pulse 40 nsec T pu Ise to
to preset with 1 preset with 1
None
the modu Ie contains control Iines for each group of 4 bits:
None
T
F
T
F
F
Input
T**
tF
I
F
lJ
Input
D
Q4 (pin 25)*
D
T** T
T
40 nsec T pu Ise 40 nsec T pulse
to preset with 1 to preset with 1
COUNT UP
BCD
Externa I logic**
T
tT
J-
T up, F down
I down, F up
F
Up mput
Down input
Q4 (pin 25)
External logic** t
40 nsec T pulse to
preset with 1
Some jumpers for all binary counters: 27-28, 5-4,
31-34,7-10
r
F
Input I
D
Input 2
Tt
40 nsec T pulse
to preset with 1
41-34,21-10,2740,5-18,37-22,
13-2,31-28,7-4
NOTES
F = Folse (Ov, ground)
T = True (+4v, or leave open)
D =don't core (T or F is ok)
" Connect Q4 to Qin 2 to form 8-bit
unit. When tw04-bit unitsaredesired use Qin2 as second input.
"" Use Ov(F) pulse to inhibit countand
common reset lines when ~resetting in
the downmodeorwhenc angingdirection with u~and down Iines. Start
the inhibit pu se 30 nsec before changingupanddown lines.
t To clearall flip-flops in any configurat ion, place +4v (T) on common reset (pin 45); place Ov (F) on count,
shift, up, and down lines; pulse clock
lines with +4v (T), 30 nsec min.
Count 142~---T--------------------~--------------------'-------------------~
Shift 1 38~--"-+--------------------...-+-------------------.-+--------------------,
Up 1
24~~++----------------~-1-+----------------4r-++-----------------'
Qin 1
44
O;n 1
46
~
Common 45
Reset
27
+8v -.-051
+4v
Down
50
Clock [3 0
6
Count2 12
Shift 2 8
Up2
14
~49
~ ..a
32
16
f
+4v
Q
in2
20
75 ohms
29
~
NOTE:
1. Mark inputs must be grounded when not in use. 2. Subscripts refer to ckt. number. Example: Up 2 is Up control line for ckt. 2
3. Clock terminator is for use with 33 ohm coaxial coble. Do not use when clock is brought in by logic wiring.
LOGIC DIAGRAM, FTl9
42
Clock Coble
Terminator
FT20
8-BIT BUFFERED LATCH REGISTERS
A fi Itered strobe is provided for use in noisy environments.
Fi Itered strobe must be True for 200 nsec minimum. Output
is then available 300 nsec after strobe leading edge.
The FT20 contains two independent8-bit buffered latch registers, usefu I for low cost storage. Data is loaded and read
in parallel. Only one strobe, minimum 70 nsec. True, is
needed to both erase and update contents. When strobe
goes high data inputs must remain stable until 100 nsec after
strobe leading edge has risen to within 20% of final value.
Outputs can be read after 90 nsec following strobe leading
edge.
Output Drive:
Power Requirements:
Dissipation:
Data Inputs
Circuit 1
o
1 2
3
13 Unit Loads per output
+4v, 247 ma av" 385 ma max.
+8v, 62 ma av., 79 ma max.
2.39 watts max.
Circuit 2
456
Data Inputs
7
Buffer Register
6
7
+8v--051
+4v
---<>49
48
~o
32
16
Data Outputs
Filtered
Erose & load
Strobe
~
~
Data Outputs
Filtered
Erose & load
Strobe
~
~
LOGIC DIAGRAM, FT20
T SERIES Modules In SDS SIGMA 7 Computer.
Note use of Front-edge Cable Connectors.
43
FT26
BUFFERED LATCH MULTIPLEXING MATRIX
The FT26moduie contains 8 circuits which can be used individually as buffered latch circuits. The entire module can
also be used for digital multiplexing.
Each circuit can be used as a latch circuit preceded with
a 4-i nput OR, by leaving pins 28, 29, 30, and 31 open
(True) while using pins 17 and 27 as latch control inputs.
The module can be used as a 4 x 8 buffered digital multi plexing matrix with optional latch storage by wiring pins
28, 29, 30, and 31 as multiplex controls and pins 17 and
27 as latch controls. Other applications may be devised.
Fan-Out, each buffer output: 13 Unit Loads (49.4 ma)
Power Requirements: +4v, 95 ma av., 156 ma max.
+8v, 112 ma av., 144 ma max.
Dissipation: 1.95 watts max.
+8v--051
+4v --049
28
13
29
LOGIC DIAGRAM, FT26
44
48
32
16
o
BUFFERED LATCHES
FT27
FT27 contains 12 latching circuits for use as unclocked storage elements. Each latch circuit has two gated inputs shown
in the diagram below as A· B + C· D. Band D are each
common to 4 latches and can be used as common control
lines. Input R is the latching input. When R is True and
A· B or C· D is True, the buffer output goes True and relT'ains
True until R goes False. This circuit provides a low cost
memory capability and can be used in applications where
the fully buffered output of the T Series flip-flop is not
required.
Power Requirements: +4v, 142 ma av., 234 ma max.
+8v, 101 ma av., 129 ma max.
Dissipation:
2.17 watts max.
]V+flill =1
51 494832 16 0
A
B
C
D ~+------------------------~--_______________________~___________________________~
R
A
B
C
D
~+-
____________________+-____________________+-__________________
~
R
A
B
C
D ~+-----------------------4-------------------------~---------------------~
LOGIC DIAGRAM, FT27
45
FAST ACCESS MEMORY
FT40
The FT40 fast access memory module provides storage of 128
bits on one module, arranged as sixteen 8-bit bytes. Up to
32 modules can be operated with one set of address lines,
givi ng a memory size of 32 x 128 = 4,096 bits.
Input Logic Levels:
Output Logi cLeve Is:
Fan-out (each output):
The FT40 reads and writes significantly faster than a core
memory. Typical core access time is greater than 700 nsec,
while the FT40 has a write time of 165 nsec or less and a
read time of 110 nsec or less. The module interfaces directly
with other T Series modules, requiring no special read-write
electroni cs or power suppl ies.
Circuit Delay:
The FT40 costs less per bit than standard flip-flop storage.
This makes it attractive for use in long shift registers or peripheral equipment input - output buffers and simi lar large
data capacity applications.
Write Control Conditi ons:
(worst case)
The FT40 is operated as follows (refer to the logic diagram).
Data is written in or read out 8 bits at a time. The module
is addressed when all five Module Address lines, 24 through
2 8, are True. I'fany one of these five Module Address lines
is False all Data Outputs are True, but may be pulled False
by a Data Output line from another FT40 wired in parallel.
There are 16 storage locations, each holding one 8-bit byte,
on each FT40. Data is read out of anyone of these 1610cations by addressing the Byt~'Address, 20 , 2 1, and 22, and
the Column Address, 23 and 23. Readout is nondestructive.
Data is written into anyone of these 16 locati ons on the
trai ling edge of clock, by addressing the locations (2 0 , 2 1,
22, 23 , 23 ) and holding Write Enable True.
The line terminators (220 ohms each) are used as pull-up resistors for the data output lines. No pull-up resistors are
connected on the modu Ie to the data outputs. Up to sixteen
data output lines can be connected together and returned to
+4 volts through one 220 ohm resistor. A 1200 ohm clock
cable terminator is also provided on the module for use in
large systems where clock (write pulse) is distributed via 33
ohm cable, and the cable is terminated by thirty-two 1200
ohm resistors in parallel. In smaller systems, where timing
skew is not a critical factor, ordinary logic wiring can be
used to deliver the clock pulse to each module.
Load imposed by each
logic input:
Read Control Conditions:
+4 Volt
+8 Volt
-8 Volt
Module
Supply:
Supply:
Supply:
Dissipation:
Temperature Range:
Logic 1: +4v
Logic 0: Ov
Logic 1: +4v
Logic 0: Ov
11 Unit loads (42 ma) with
220 ohm pull-up resistor
connected
Pins 20, 21, 22, 26, 27: 2
unit loads; all others 1 unit
load
Read: 110 nsec worst case
(60 nsec typi ca I)
Write: 165 nsec worst case
(90 nsec typical)
Address, Data, and Writeenable should be stable 80 nsec
before clock leading edge, and
remain stable 45 nsec after clock
trailing edge. Minimum clock
pu Ise: 40 nsec.
Address should be stable 110
nsec before outputs are read.
1. 28 amp max. (550 ma typical)
146 ma max. (63 ma typical)
2 ma
6. 25 watts max. (2. 7 watts
typical)
~
0
+5 0 C to +50 C with convection'"
cooling
0
+5 0 C to +70 C with forced
air cooling, 100 linear fpm
airflow (use ZT20)
line
Terminoton
13 31
Clock
~4V
Wrlte Enable
36
42
Bit1
Bitl
Bit2
Bit 2
Bit 3
40
Bit 5
::>
Z
0
~
""
""
0
~:v7
~:v
Bit 3
::>
::>
Bit 4
39
Bit4
Bit5
8it6
Bit 6
Bitl
B;t7
BitS
Bit8
44
~4V
45
5
~::
~::
~:v
~v
14
~+4v
Clock Cable Terminator
(for lorge computer use)
25
23 21 22 2720 26
LOGIC DIAGRAM, FT40
46
~
STANDARD FLIP-FLOPS
FT43
The FT43 contains six flip-flops having separate, gated
mark and erase inputs for each flip-flop. Separate and
common clock inputs are provided. Reset inputs {not shown}
are wired True. The flip-flop is controlled via the set input in clocked applications. The circuit has many uses.
For examp Ie, all gati ng is provided for a jam-transfer regde set transfer
Common erase
de reset transfer
<¢---.-~--------
ister. The OR'ed clock permits multi-function applications
such as combination ripple-counters/shift registers.
Power Requirements:
Dissipation:
+4v, 236 ma av., 360 ma max.
+8v, 151 rna av., 194 ma max.
3.29 watts max.
__J..!!:!....--------~~------,
oL-+-----4-+------+------4-~----+----_4--_,
o:!l--+--4;;..------+------4-:t-:..:-----+------4-h.-.
+8v~51
+4v ---..049
~
~~
16
o
36
Note: reset, r, input is wired True (not shown)
LOGIC DIAGRAM, FT43
FT56
CLOCKED FLIP-FLOPS
The FT56 contains twelve economical flip-flops, in three
groups of four. Each group of four has a common clock input line. All reset inputs are wired True. Flip-flop states
are controlled by using the set input, since set True over rides reset True. Three 220 ohm line terminators are also
provided.
No mark inputs are provided.
Power Requirements:
Dissipation:
+4v, 470 rna av., 720 rna max.
+8v, 134 ma av., 172 ma max.
4.69 watts max.
line Terminators
+4v
+4v
+4v
+8·--<>51
+4v~49
1§ ~o
16
LOGIC DIAGRAM, FT56
47
DC (RS) FLIP-FLO PS
FT57
The FT57 module contains ten dc flip-flops (cross-coupled
NORs) for use where the buffered outputs and the clocked
inputs of the SDS 307 IC flip-flop are not required. These
flip-flops may be economically used in storage registers,
as control flip-flops, etc.
10
11
12
13
21
Min. True Pulse:
Power Requirements:
20 nsec.
+4v, 218 ma av., 390 ma max.
+8v, 112 ma av., 144 ma max.
2. 98 watts max.
Dissipation:
22
27
25
TITrrr=-
LOGIC DIAGRAM, FT57
FT58
33
34
51494832160
FLIP-FLOPS lO-BIT BUFFERED LATCH REGISTERS
The FT58 contains two independent 10-bit buffered latch
registers, useful for low cost storage. Data is loaded and
read in parallel. Only one strobe, minimum 70 nsec True,
is needed to both erase and update contents. When strobe
goes high, data inputs must remain stable until 100 nsec
after strobe leading edge has risen to within 20% of final
value. Outputs can be read after 90 nsec following strobe
leading edge.
Max. Operating Freq.:
Depends on strobe timing
Output drive:
13 Unit Loads per output
Power requirements:
+4v, 321 maav., 531 mamax.
+8v, 140 ma av., 180 ma max.
Dissipation:
3.92 watts max.
A filtered strobe is provided for use in noisy environments.
Filtered strobe must be True for 200 nsec minimum. Output
is then available 300 nsec after strobe leading edge.
Circuit 1
Circuit 2
Data Inputs
Filtered
Erase and
load Strobe
Filtered
Erase and
load Strobe
Erase and
load Strobe
Erase and
load Strobe
Tr~
51 ., 41 32 II 0
48
Data Inputs
0.:..:.---------\
Data Outputs
Data Outputs
LOGIC DIAGRAM, FT58
HT58
UNIVERSAL OPERATIONAL AMPLIFIER
Input vol tage range:
The HT58 is a fast, high-input impedance, high-output current, differential amplifier with provisions for adjustment of
gain and zero offset. In addition, the input offset voltage
temperature coefficient is adjustable.
Recovery ti me from
lOX overvoltage:
(not to exceed common
mode of ± 15v on either
input)
Output
A feature of the amplifier is a front-end shield plane, driven from the common mode point, and an electrical IIFET
Guard II, which reduces the effective input capacity when
used in the buffer mode. Pins adjacent to the inputs are also driven to eliminate effects of stray capacitance. This
signal may be used for external guards if desired.
Voltage swing:
Current:
Output impedance:
The amplifier is available in a variety of popular gain configurations (see Tables 1, 2, 3). Other resistor configurations may be obtained on special request. In addition, a
unit is available without gain resistors or gain pot.
Input impedance
(buffer mode):
Input bias current
(FET leakage):
(see note)
5
6
.5 x 10
± 10 ~vl'c (easi Iy adjustable)
100 db, dc; 60 db, 1 KHz
(Resistor error may be adjusted out)
Junction FET typically paralleled by less than 1 pf
capacitance
o
• 1 nanoamp at 25 C; 1 n. a.
0
at 55 C
II
Power Supply Voltage:
Power supply current:
Power supply recommended:
5V
+30v to +35v
~
+25v to +30v
~....--.......- - - -
Solder Terminals For
Mounting Input And
Feedback Components
14
-25v to -30v ~
Contact Res i stance
A
O---.t;t-J
r----.. -.
-30v to -35v
±10 volts
±40 mao (self limiting)
.01 ohm max. at D.C., all
configurations; 1 ohm max at
1 MHz, unity gain (proportional to gain)
250 ohms
2,000 pf
5 ~ec, at unity gain, full load
(+ lOv to -lOv or -Wv or + lOv)
lOv/~sec., typical
.5 mv. p-p RTO
Either at solder terminals on
board or at connector pin
(with feedback jumpered). See
General Configuration.
Pins 18 & 14, +(25 thru 30)v
and -(25 thru 30)v or pins 5 &
1, +(30 thru 35)v and -(30 thru
35)v
25 mao plus load current
PT24
Min. load impedance:
Settl ing time to within
1 mv of final value:
Slew rate:
Noise (Wideband):
Output connections:
Input
Open loop gain:
Zero drift:
Common mode rejection:
± 10 volts divided by the
closed loop gain (min.1,
max. 10)
OP Assy's and Diff. Amp.:
10 ~sec
Buffer: 12 ~sec.
9
Of
'"OkPlre",,"",",
C14
To El
R16
R46
6 (Output Pin)
6
Load Gnd
Rl
4Oo-----<>-'VV~:>_--_+---__f
11 (7, 8,
4 5 0 - - - - - - - - - -.......- - - - - 1
R2
390----<~VV~>_---_.
R3
38o----<~VV~>_---_.
C15
I
: Feedback
I Jumper
I
Alternate
Feedback
Connection
(Use Jumper)
El
Alternate
Load Connection
(Solder Terminals
On Module)
y
-&
T
Backplane
350~---_41~---~
21 thru 25, 30,
31, 33 thru 37,
41 thru 44, 46, 47
0---------.
26
0----11---.
Common Mode
Signal, Shield
Drive
Note: Use power supply connection that is appropriate
to available voltage.
280----..""'-----'
GENERAL CONFIGURATION, HT58
49
Table 1. Operational Amp. Configurations
Operational Ampl ifier
@)
C14
R16
R46
Rl
R16
+
R46
C14
R2
R3
Gain
Settl ing
TimeCV
fJsecs
-1
10K
10K
lOPF
-
Xl
S
-2
10K
lOOK
SPF
-
XlO
10
-3
lOOK lOOK
SPF
-
Xl
10
-4
Short 2.SK
lOPF
-
-
cr>
S
Dash
No.
CD
Differential Amplifier
C14
R16
Table 2. Differential Amp. Configurations
Rl
R16
+
R46
C14
R2
R3
-S
10K
10K
lOPF
10K
10K
Xl
-6
10K
lOOK
SPF
10K
lOOK
XlO
10
-7
lOOK lOOK
SPF
lOOK
lOOK
Xl
10
-
-
-
-
-
R46
R3
Dash
No.
-8
C1S
-
-
Gain
Ts
S
Table 3. Buffer Configurations
Unity Gain Buffer
R16
Dash
No.
R46
C14
R2
R3
Gain
Ts
-9
-
-
Short
-
Xl
S
-10
1K
9K
lOPF
-
-
XlO
10
CD
Buffer With Gain
C14
R1
R16
R46
Popular Gain Configurations, HTS8
50
+
R1
(1)
@
@
May be tailored for specific applications.
20v swing on output, settl ing to within. 1 mv of final value.
±4 ma input current produces +" lOy output.
Order configuration desired by dash no. suffix. Example:
HTS8-6 is second configuration listed in Table 2.
HT72
VOLTAGE COMPARATORS
The HT72 contains two general purpose operational amplifier circuits, designed for applications not requiring the
performance of the HT58 amplifier. This module uses two
integrated circuit linear amplifiers, with additional components, which provide two major improvements:
1. Additional power amplification produces
greater output current (20 ma at 1 Ov).
2. An internal supply voltage control allows
broader tolerance in supply voltage (±20%).
The i nterna I vol tage control assures that
gain is stable in spite of supply voltage
changes.
Differential or unipolar input may be used. Output is
single-ended. Configurations available are similar to
those of the HT58 module (refer to HT58 description). Due
to the excellent gain stability, accuracy of the amplifier
depends primari lyon feedback resistor accuracy. The
amplifier is provided with 1 % feedback resistors, mounted
on standoff terminals, which result in overall accuracy
better than 1.4%. If these are replaced with 0.01 %
resi stors, at user opti on, accuracy wi II be better than O. 1%.
Additional standoff terminals are provided on the module,
whi ch allow the user to modify the feedback of the ampl ifier by addi ng components.
R1S~_~\~_1
E9-1
Characteristi c
Input
Open loop gain
Temp. coefficient of
input offset voltage*
Input impedance
Input bias current
Input offset current
Input voltage range
Differential input
voltage range
Units
Min.
Typ.
12,000
45,000
f-Iv/oC
6
Kohms
f-Iamp.
nanoamp.
volts
volts
150
400
0.5
100
2.0
750
±10
±S.O
Output
Voltage swing
Current
Output impedance
(open loop)
volts
ma
ohms
22
30
Power supply voltage
Power supply current
Dissipation, per
module
volts
ma
watts
20
25
0.50
25
*
Max.
±10
20
50
30
90
2.7
The total offset of the amplifier is adjustable to
within ±300 f-Ivolts.
ES-2
ES-1
37
E10-1
E1-1ns
15
El-2ns
E12-2
E12-1
E2-2
E2-1
17
36
29
38
20
14
21
30
31
E5-1
~ES4-1
+Vee
E6-1
42 E19-1
0----0
~-1
+15V
Voltage
Reg.
50
-15V
~
35
S
22
E5-2
~:4-2
7
E19-2
0----0
~-2
+Vee
U_2~
10
+15V
Voltage
Reg.
-15V
S
-Vee
-Vee
Note: Dashed resistors are not furnished.
LOGIC DIAGRAM, HT72
51
HT73
VOLTAGE COMPARATORS
The HT73 module contains nine independent logic circuits
with differential inputs. When the voltage at the + input
becomes more positive than the voltage at the - input by a
predetermined comparison value the output goes to logic 1
(high) level. The comparison leve I is determined by the resistor and Vref connections which are made at the - input.
The HT73 is used as a sensitive level detector or interface
module. The HT73 uses the same circuit board and amplifies as the AT69 differential receiver.
Comparator sensitivity is better than 10 mVi that is, when
the + input becomes 10 mv more positive than the comparison
level, the output goes high. The comparison level is the
voltage at point P (see connection diagram).
The voltage at comparison point P is usually determined by
the combination of V ref and a voltage divider network
R3/R5 that can be placed at the - input. The resistor R3
that is provided on the module is a 4.64K ohm, 1 % precision resistor. R5 IS supplied by the user.
The voltage at the comparison point, P, should not go beyond the range -5v to +5v when supply voltages of ±8v are
used for -v and +v. The range at point P can be extended
as far as -12v to +12v by raising -v and +v to -15v and
+15v.
This voltage divider arrangement permits the use of a relatively high precision reference voltage such as the 35 volts
that is available from the WT49 module.
An external variable comparator level input may be substituted as shown in the connection diagram, if an adjustable
comparison input is available.
The HT73 output logic level is determined by the supply
voltage connected to pin 26. For T Series use pin 26 is
tied to +4 volts.
Both input terminals and the Vref terminal are available
at front-edge cable connectors (--7» as well as a
backpane I connectors (-o).
Max. Data rate:
Max. input voltage (from
+ input to ground):
Comparison level range
{at point P} with
+v=+8v and -v=8v:
with +v=15v and -v=15v:
Max. Vref:
Input impedance:
Fan-out:
Propagation delay,
at 25 0 C:
+4 volt supply (Vcc):
+8 volt supply:
-8 volt supply:
Dissipation, per module:
Mhz
15 volts
-5v min., +5v max.
-12v min., +12v max.
Depends on R3 and R5
(refer to text)
200K ohms min.
37 Unit Loads
170 ns typo
60 ma typo 68 ma max.
220 ma typo 270 ma max.
16 ma typo 25 ma max.
2.27 watts typo
3.07* watts max.
* at 10% overvoltage
V logic
+V
+V
High {+4v}
V logic
High (+4v)
~--- Out
V ref
Out
-V
With fixed V ref and voltage divider
With voltage comparator level input
HT73 Connection Diagram
52
Vref
+V
V logic
high
+V
-v
V logic
high
+V
-v
-v
+V
V logic
high
A
-v
Vref
+V
V logic
high
+V
-v
+V
V logic
high
-v
+V
V logic
high
-v
V logic
high
+V
V logic
high
-v
V logic
high
L312 ::~
9o----..i~r
~
Note:
For T Series Differential Receivers
operation, connect Vref to +V, and
connect V logic High to +4 volts.
Analog
Ground
-v
LOGIC DIAGRAM, HT73
53
IT10
INVERTED AND JOR GATES (AND jNORs)
Ei ght inverting AND/OR gate structures (AND/NORs) are
on these modules. Each circuit consists of two 3-inputAND
gates, the outputs of whi ch are ORed and inverted. One i nput on each AND gate is shared with 3 other circuits. The
circuits are designed to implement expressions of the type
A • B • C + D • E • F. By connecting ITl0circuitoutputs
together a larger NOR function can be generated, of the
type A • B • C + D • E • F + G • H • I + J • K • L. Refer to
BT10 description for non-inverting versions of these circuits.
Power Requirements:
+4v, 87 ma av., 156 ma max.
+8v, 45.0 ma max., 57.5 ma max.
1.2 watts max.
Dissipation:
41
TTTTW
12
LOGIC DIAGRAM, ITlO
ITll
51 49 48 32 16 0
INVERTED AND GATES (NAND GATES)
The ITll has an assortment of NAND gates for genera I purpose use. There are two 3-input circuits; three 4-input
circuits; and seven 2-input circuits. The NAND functions
can be ANDed by connecting outputs together. Refer to
BTl 1 description for the non-invertingversions of these cir cuits.
Power Requirements:
+4v, 130 ma av., 234 ma max.
+8v, 33.6 ma av., 43.0 ma max.
1 • 45 watts max.
Dissipation:
30
~ ~ ~ ~
33
31
17
21
~ ~
~ ~
29
19
41
46
11
~ ~
42
45
24
22
28
43
~ ~
37
LOGIC DIAGRAM, ITll
36
TTTTTP
51 49 48 32 16 0
54
1113
INVERTER MATRIX
IT13 has a 4 x 4 matrix which can (1) select one of up to4
groups of 4 bi ts each, or (2) generate up to 16 discrete outputs from a 4 x 4 matrix input, or (3) provide 18 general purpose inverters. Gate structure is identical to BTl3.
Power Requi rements:
Dissipation:
+4v, 124 ma av., 219 ma max.
+8v, 28 ma av., 36 ma max.
1.07 watts max.
33
~
~
27
26
25
23
22
24
TITrn~
51 49 48 32 16 0
34
LOGIC DIAGRAM, IT13
55
IT14
INVERTED AND/OR MATRIX (AND/NOR MATRIX)
The IT14 modu Ie contains a matrix of ei ght buffered AND/
NOR gates (AND/OR-inverters) which have common AND
inputs as shown in the logic diagram below. Each gate can
be used as an independent 4-input NOR if all common pins
are left open (True). The NOR outputs can be tied together
to form NORs with more than four inputs. The entire structure can be used as a 4 x 8 digital multiplexing matrix if
the common pi ns are strobed in sequence.
The outputs do not have pu II-up resistors connected on the
board. This permits formation of wired logic functions without a fan-out penalty, by tying outputs together. However,
at least one pu II-up resistor must be present on any combination of outputs wired together (or on a single output used
alone) to provide the high logic level for the gates connec-
43
39
29
33
22
ted to the output(s}. If no pull-up resistor is present, connectoneofthetwo5-unit-load terminating resistors supplied
on the module. Additional terminators are avai lable on the
XTl 0 modu Ie.
The structure of the ITl4 is simi lar to that of the FT26.
Power Requirements:
Dissipation:
+4v, 67. 6 ma av., 96 ma max. *
+8v, 90 ma av., 115 ma max.
1.21 watts max. +pu II-up power
*Add current drawn by output pull-up resistors, at 3.8 ma
per unit load.
18
13
Trrrr~
51 49 48 32 1& 0
+4v
4
LOGIC DIAGRAM, ITl4
56
+4v
1118
INVERTED AND GATES (NAND GATES)
Power Requi rements:
The Ill8 module contains ten NAND circuits intended for
general purpose use. Each circuit can drive 14 loads. Outputs may be paralleled with other circuitsi each paralleled
output decreases the output drive capabi Ii ty by 2 uni t loads.
Dissipation:
W
15
~ ~
26
25
38
40
13
12
11
8
~ ~
50
46
47
39
23
22
35
17
20
19
~ ~
43
+4v, 124 ma av., 21 9 ma max.
+8v, 28 ma av., 36 ma max.
1.07 watts max.
3
~
6
~
TTTm~
51 49 48 32 16 0
LOGIC DIAGRAM, ITl8
1127
INVERTED OR GATES (NOR GATES)
The IT27 module contains ten 3-input NOR gates and two
2-input NORgates which have inputandoutput pin numbers
identical to those of the BT27. Each circuit can drive 14
unit loads. Various methods are avai lable to expand a NOR
gate, by tying outputs together or by adding a second level
of gating.
47
37
23
44
33
14
Power Requirements:
Dissipation:
+4v, 131 ma av., 234 ma max.
+8v, 95 ma av., 122 ma max.
2. I watts max.
7
~ ~ ~ ~
43
13
29
~ ~ ~ ~
41
27
11
40
26
10
~
38
3ffi>A
24
21
+8v--051
+4y -----0 49
~4816
32
0
~ ~
LOGIC DIAGRAM, IT27
57
INVERTED AND GATES (NAND GATES)
IT31
Power Requirements:
This module contains fourteen economical 2-input NAND
gates and two 1-input inverters intended for general purpose
use. Each circuit can drive fourteen unit loads. Gates can
be expanded by paralleling outputs with the usual fan-out
restrictions. The BT31 module has identical gating but outputs are not inverted (see BT31).
29
34
46
31
44
18
37
21
42
Dissipation:
~
~
~
~
~
~
~
~
~
~
~
~
~
15
~TTTTI!=
LOGIC DIAGRAM, IT31
51 49 48 32 16 0
KT10
MERCURY-WETTED RELAYS
The KTlO contains four independent relays with mercurywetted Form C (non-bridging) SPDT contacts. Each relay
can be driven by its own 2-input NAND-gate/driver, furnished on the module. A clamping diode limits peak inverse
voltage. The relays are single-sided stable. The module
occupies two spaces, and must be operated in the prescribed position.
Max. operating frequency:
Circuit delays:
200 Hz
5 mi Ilisec. max. make,
1.8 mi lIisec. max. break
'
m
1] I,
~il
11
~
:
11
Circuit 1
.
.
CIrcuIt 3
10
r1
-m:
20
39
D
,
I
1
21
18
Re lay coi I supp Iy(ea. relay):
Contact rating:
30 rna at +6v
to 60 rna at +12v
100 VA max.,
500 v max.,
2 amp max.
NAND input
load (ea. input):
6 unit loads (23 rna)
at Ov logic level
Power requirements:
+8v, 63 rna avo, 81 mamax.
-8v, 2.35 ma avo, 5.22 rna rna>
0.76 watts plus relay power
r-m
~1] ,,1. ,
Dissipation:
7
15
38
I
1] "I. ,
~
1
40
::
36
D
1
I
11
Circuit 2
,;
'
m
lJ I, ,
~~42~24
II
~:
.
.
CirCUIt 4
LOGIC DIAGRAM, KTlO
58
+4v, 167 rna av., 312 rna max.
+8v, 45 rna av 0, 5705 rna max.
1.88 watts max.
"
21
n
-8iT~
50 51 48 32 16 0
LOGIC ELEMENTS
LTlO holds several general purpose elements in a useful
assortment. The mixture includes 2 Buffered AND;OR gates
in which each AND gate has 3 input terms; two 2-input
Buffered OR gates; two 3-input Buffered AND gates; two
2-input Buffered AND gates; one 2-input NAND gate and
3 inverters. Each input represents one un it load, and each
~ ~
28
31
15
14
9
~ ~
30
33
11
10
8
~ ~
lT10
output can drive 14 unit loads.
Power Requirements: +4v, 138 rna av., 234 rna max.
+8v, 44.8 rna av., 57.5 rna max.
Dissipation:
1 .54 watts max.
~
~
~
~
20
22
+8v--<>51
+4v ---<>49
~481632
0
LOGIC DIAGRAM, LTI0
lTll
LOGIC ELEMENTS
LTll has four sets of gates arranged in an AND/OR form,
especially suited for selecting sets of bits (in four bit "by_
tes"), and for forming parallel adders or subtractors, comparators, parity bit generators, and parity bit error detectors as well as many others. Each output has both True and
False outputs available. One module can form a parity bit
from an 8-bit parallel input, or detect a parity error from
8-bit inputs, or can compare the equality of two 7-bit words.
Fan-outs:
Power Requirements:
Dissipation:
14 unit loads on pins 11, 14
39, 41; 13 unit loads on pins
12, 13, 40, 42.
+4v, 87 rna av., 148 rna max.
+8v, 50.4 rna av., 64.5 rna max.
1.22 watts max.
LOGIC DIAGRAM, LTl1
59
LT26
SWITCH COMPARATORS
The LT26 module contains eight switch comparator gates,
NORed together in two sets of four. A switch comparator
compares the logical state of a signal with the state ofa
manual toggle switch. When the incoming binary pattern
equals the pattern stored in the switches the output of the
NOR gate goes True. With the two NOR outputs tied together, an eight bit number can be detected.
Note that a 220 ohm terminating resistor (or 560 ohm pullup) must be connected to each independent NOR gate output since no 560 ohm pull-up is present on either output.
Usually both NOR outputs can be connected to the same
220 ohm resistor, and other buffer or inverter outputs can
be connected to the same point to form more complex wired
logic functions. Additional terminators are available on
the module for conveniently terminating logic lines in accordance with the T Series backpanel wiring ru les. A 220
ohm resistor absorbs 5 unit loads.
The eight inverters on the card can also be used independently.
Fan-out (each output):
Power Requirements:
Dissipation:
44
1TrTTr51 49 48 32 1& 0
25
17
220 ohm
Line Terminators
13 14 18
20
+4v
(5 unit loads eo.)
30 34 36 40
LOGIC DIAGRAM, LT26
60
16-unit loads without pu Ilup
or terminator
+4v, 171.6 rna av., 324 ma max.
+Bv, 67.2 rna av., 86.2 rna max.
2.18 watts max.
TELETYPE SEND MODULE (8-11 CODE)
LT50
The LT50 is a special purpose logic module which performs
a timed parallel-to-serial conversion. It accepts .one 8-bit
character (8 bits in parallel) and serially transmits the characterl together wi th start and stop signal Sl to a keyboardprinter (such as a Teletype). LT50 contains an 8-bit shift registerl a 5-bit control counterl 3 control fl ip-flops and other
control logici all on one compact circuit card. Operating
speed is determined by the input rate of the keyboard-printer or other character-oriented terminal device. The LT50
performs no code conversion.
Complete design data is given in Appl ication Bulletin 6451-09. The LT50can be combined with LT541 NT191 0T141
CT16 1 and FT12 modules to form an economical characteroriented keyboard-printer interface.
+4vl 650 ma; +8v l 400 ma
5.8 watts max.
Power requirements:
Dissipation:
Parallel 8-bit Input
r -________~A~__________~
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
GO
Transmit
SClock (110 Hz)
21
Serial
Character
Output
19
NSSRM
Service Request
Output
High Speed Clock
Control
Inputs
LT50
Outlock
Send Module
(8- 11 Code Format)
NReset
STE
LIUL
ACK
STOPEN
NFLSP
NFRON
NC4FF
'----y------J
Status Outputs
TfTrn~
51494832160
LOGIC DIAGRAMI LT50
LT54
TELETYPE RECEIVE MODULE (8-11 CODE)
The LT54 is a special purpose logic module which performs
a timed serial-to-parallel conversion. It accepts one 8-bit
serial characterata timel togetherwith start and stop pulses.
It places the eight data bits in a registerl for parallel output. LT54 contains an 8-bit shift registerl a clock downcounterl 4 control flip-flops and other control logic i all on
one compact circuit card. Operating speed is determined
by the output rate of the keyboard-printer or other character-oriented terminal device. The LT54 performs no code
conversi on.
Complete design data is given in Application Bulletin 6451-09. The LT54 can be combined with LT50 1 NTl91 0T141
CT16 1 and FT12 modules to form an economical characteroriented keyboard-printer interface.
+4vl 650 ma; +8v l 400 ma
5.8 watts max.
Power requirements:
Dissipation:
Serial Character Input
10
Module Select
(Output Enable)
,
Control
Inputs
LT54
RECEIVE
MODULE
(8- 11 Code Format)
ReadM
RClock
~[~;}
Bit 4
Parallel
8-bit
Output
Bit 3
Bit 2
Bitl
FRON
Inlock
34
NReset
L __ .J
L. __ .1
L __ .1
NLSP RLSPM
"'------.,y,----~)
'-y----J
Internal
Clock Jumpers
Status
Outputs
NRSRM
Service Request
Output
TiTll~
51494832160
LOGIC DIAGRAM I LT54
61
LT66
12-BIT COMPARATOR
The LT66 contains an array of exclusive-OR logic circuits
connected as a comparator. The comparator determines the
equal ity of two twelve-bit words. It compares the two groups
designated A and B in the di agram below. The comparator
output is False when the two 12-bit patterns are congruent,
or True when any two corresponding bits are not equal. The
comparator circuit thus solves the equation:
Q = A 1 B1 + Bl A 1 + A2 B2 + B2 A2 + A3 B3 + B3 A3 +
The module also contains two 12-bit buffered ANDs. One
of these two outputs is True when the group A bits are all
True. The other output is True when the group A bits are
all False.
Power requirements:
0
0
•
Dissipation:
To compare two words, of the same length but less than 12bits, merely leave unused input pairs open.
+4v, 224 ma avo, 35S.5 ma max.
+Sv, 140 ma av 0, 1SO ma max.
3.06 watts max.
AI
Al
A7
61
67
A2
A8
Al
A2
A3
A4
62
68
A5
At,
A7
A8
A9
AlO
All
A12
A9
A9
A3
69
63
AlO
A4
AiO
Al
A4
Ai
~
AlO
A4
~
A6
A7
~
610
64
A9
ill
Ail
A5
ill
.A5
All
65
Bll
A12
At,
At,
A12
B6
B12
A12
LOGIC DIAGRAM, LT66
62
Tr~
51494831160
LT67
FAST FUll-ADDERS
The LT67 module contains four independent fast-full adder
circuits. Each is capable of adding two bits plus carry from
a previous stage, and producing sum, carry; sum, and carry
outputs. This circuit is a fast adder because only one buffer/
inverter delay time (18 nsec typical) is required to add the
three input bits and provi de output. Most other adder designs require at least two layers of buffers or inverters in
series, with consequent longer delay.
Maximum Operating Frequency:
Circuit delay (per stage):
Fan-out (each output):
Load imposed by inputs:
Power Requirements:
Di ssipation:
Ckt.
40
46
43
A
Ckt. 2
47
18
38
36
11
17
12
C·
7
6
5
24
37
2
Full Adder
Full Adder
39
9
C
C
S
42
Ckt. 4
Ckt. 3
C
Full Adder
10 Mhz, for 3 stages
in series
18 nsec typ., 30 nsec max.
14-unit loads
True inputs: 8 unit loads
False inputs: 4 unit loads
+4v, 78 ma av.,
100 ma max.
+8v, 182 ma av.,
312 ma max.
2.26 watts max.
41
8
10
LOGIC DIAGRAM, LT67
A
C· = (AC+AB+BC)
C
A
C·
B
B
C
A c>--+-+-t---A
B
B
C
C
S
= (ABC
+ ABC + ABC + ABC)
80---+-+--+-_AO--+-+-~p---
C 0---+-+-+---
Single Full-adder Circuit (four per module)
63
NT10
a-VOLT INTERFACE BUFFERS
NTlO contains 2 BANDs and a 4 x 4 matrix of 3-input
BANDs. All use standard T Series Ov/+4v input levels.
Output levels are Ov and +8v. This module serves as interface from T Series to many other Positive True logic systems
which use a high level of about +8v. Input tolerance is
often sufficient to permit interfacing with Ov/+6v logic.
Standard logic wiring may be used for interfacing provided
wire length is under 5 feet.
drivers.
Output Current:
Power Requirements:
Dissipation:
Otherwise use A Tl4 cable
53 ma per driver
+4v, 132 ma av., 175 ma max.
+8v, 176 ma
2. 11 watts max.
33
~
~
~
~
+8 V
+4v
---051
---<>49
4B
32
16
g
34
17
o
6
LOGIC DIAGRAM, NTlO
NTll
a-VOLT INTERFACE INVERTERS
NT11 contai ns 2 NANDs and a 4 x 4 matrix of 3 - input
NANDs. All use standard T Series Ov/+4v input levels.
Output levels are Ov and +8v. This module serves as interface from T Series to many other Positive True Logic systems
which use a high level of about +8v. Input tolerance is
often sufficient to permit interfacing with Ov/+6v logic.
Standard logic wiring may be used for interfacing provided
wire length is under 5 feet.
drivers.
Output Current:
Power Requirements:
Dissipation:
Otherwise use A Tl4 cable
53 ma per driver
+4v, 88 ma av., 175 ma max.
+8v, 176 ma
2. 11 watts max.
33
~
~
~
~
51
---<>49
+8v ---0
+4v
~
17
LOGIC DIAGRAM, NTl1
64
~
16
o
NT18
NEGATIVE lOGIC TO T SERIES INTERFACE
The NT18 contains eight 2-input AND gates which accept
Ov/-v input and convert to standard T Series Ov/+4v output.
Input Current:
Power Requirements:
Maximum negative input voltage is -12 volts. Either of two
switching values may be used, as determined by a jumper
wire:-1.5v or -3v. When input logic level exceeds-4.5v,
the -3v switching value should be used.
Dissipation:
Jumper
Jumper
-3v to -12v, 4 rna
+4v, 120 rna av., 130 rna max.
-8v, 65 rna av., 100 rna max.
1.0 watts av., 1.3 watts max.
Jumper
Electrical
Truth Table
Input A Input B Output
~ ~16
o
N
9
1
2
Jumper
Jumper
~
Ov
Ov
-v
-v
Ov
-v
Ov
-v
Ov
Ov
Ov
+4v
4
Jumper
Jumper
Note: Add jumper wire to obtain -1. 5v switching point.
LOGIC DIAGRAM, NT18
NT19
KEYBOARD INTERFACE
The NTl9 is a special purpose module meant to provide a
proper electrical match between T Series logic (LT50 and
LT54 modules) and a keyboard-printer (such as a Teletype),
using 500 feet or less of ETl2 cable. In addition the NTl9
contains special logic required when the module is used as
part of a Sigma 2 Computer. The presence of the special
logic, when not used, affects only the loading of some inputs and outputs.
-4v
P2!P3
CONNECTOR
I
WI-~__~)
)
Special Logic
for use with
Sigma Computer
Interface
440--""*--------l'\"~--_~)
210-_-------l.1/
For complete design data refer to Application Bulletin 6451-09, which describes an economical character-oriented
data interface unit.
Power requ irements:
Dissipation:
TO TELETYPE SELECTOR
MAGNET DR[VER ,20 mol
)
4 )
TO OPT[ONAL GE328
LAMP AT TELETYPE
FROM NORMALLY CLOSED
CONTACT TO GROUND
> (Keybonrd Signal
6 )
+4v, 64 ma; +8v, 325 ma
?86 watts max.
Generator)
FROM NORMALLY CLOSED
CONTACT TO GROUND
> n(1b ContC'lct)
180
'rr§
1
-8v - - - - ' V V I v - - - -...
~~)
~)
8
U)
~)
9
5[ 49 48 32 [6 U
U)
~)
LAMP RETURN
KEYBOARD CONTACT
RETURN
TAB CONTACT
RETURN
3
8v---------O~) RELAY CONTACT
~) SUPPLY
14
46 O > - - - - - - - - - - - -...
ti;~ ~
SPARE
10
t:;~
CABLE SHIELD
13
36 0 l - - - - - - - - - - - - - + 0 - + )
~)
SPARE
LOGIC DIAGRAM, NTl9
65
NT33
T SERIES TO NEGATIVE LOGIC INTERFACE
The NT33 module contains eight 2-input gates which accept
standard T Series logic levels as input and furnish Ov and -v
logic levels as output. A negative voltage as low as -30
volts can be used as a negative logic level. It must be
supplied from an external source and wired to pin 17.
The NT33 is similar to the discontinued model NT17.
important differences between the two modules are:
1.
2.
3.
4.
Other variations to NT33 output impedance and rise/fall
time can be made on special order.
The
The NT33 will accept -v down to -30 volts;
the NT17 will accept -12 volts.
NT33 max. output sinking current is 140 ma
over its output voltage range; max. NT17
current is 20 mao
NT33 rise and fall times are controlled with
a capacitor (C4).
NT33 provides a high output impedance to
the line (>200K ohms) when power is off.
~481632
0
500
ma
ma
ma
ma
Dissipation, per module
(using example of -20v):
watts:
N
>
14
OT14
N
33
15
39
N
30
36
**
At 50% duty cycle.
N
29
42
N
27
~>~
10
N
19
13
N
21
6
N
2.39**
23
Electrical
Truth Table
Input I
Input 2 Output
Ov
+4v
Ov
+4v
Ov
Ov
+4v
+4v
P.~.
50 - 350 SEC
0.3 - 3.5 MILLISEC
3 - 35 MILLISEC
25 - 300 MILLISEC
0.2 - 1.5 SEC
0.3 - 2.2 SEC
Delay is determined by connecting internal capacitors with
jumpers (Table 1) and adjusting pot within the range obtained.
Power requirements:
Dissipation:
2.02**
Ov
Ov
Ov
-v
ADJUSTABLE ONE-SHOTS (MEDIUM DELAY)
0T14 contains four one-shots having output pulsewidth adjustable from 50 !-,sec to 2.2 sec. Minimum input enable
time is 30 nsec True. Q output goes True within 75 nsec or
less after enabl ing trai I ing edge reaches +2v. Do not retrigger during recovery time.
Pu Isew idth range:
Pulsewidth tolerance:
Fan-out:
ns max.
48** 56**
20** 25**
70** 80**
depends on -v supply
voltage
control capacitor (C4) and length of cable driven.
Data rates range from 100 Khz to better than 1 Mhz.
~~~~
38
140 ma max.
* Maximum data rate depends on value of rise time
The NT33 provides an excellent match with Univac and
CDC equipment, meeting all specifications. NT33 can
be paired with AT69.
-v--017
+8v--051
+4v --049
2.0 volts typo
Switching threshold:
Output current {sinking}
{from -3v to -30v}:
Propagati on de Iay, to
90% of -v {at no load}:
+4 volt supply (Vcc):
+8 volt supply:
-8 volt supply:
-v supply:
50!-,sec to 2.2 sec.
±10%
14 unit loads/Q output
12 unit loads/O output
+4v, 185 ma; +8v, 120 ma
1.7 watts max.
CONNECTION
NONE
A - E
8 - E
C - E
0- E
C - 0 - E
42
44
46 40 37 45 41
34 26 24 35 36
TIMING JUMPERS
TIMING JUMPERS
rrfTTf
51494832160
20 18 15 23 22
TIMING JUMPERS
66
10 12 1
9 2
TIMING JUMPERS
OT18
ADJUSTABLE ONE-SHOTS (SHORT DELAY)
Pulsewidth = 1. 3C (C in I-'f, P. W. in millisec).
OTl8 contains 4 circuits having continuously adjustable
pulsewidth of 100 nsec to 20 I-'sec. Minimum input pulse is
50 nsec True. Leading output edge starts typically 45 nsec
after input trailing edge reaches +2 volts. Duty cycle is
50%; circuit may not be retriggered before end of cycle.
External capacitance may be placed on the modu Ie (standoffs El, E2) to extend the pulsewidth to 20 milliseconds.
Pu I sew i dth range:
Pulsewidth tolerance:
Fan-out:
Power requirements:
100 nsec to 20 flsec
±10%
14 unit loads per output
+4v, 260 ma
+8v, 65 ma
2 watts
Circuit 3
Dissipation:
Circuit
46
Q
Inputs
20
42
Outputs
44
40
1
a
b
c
d
e
9
Circuit 2
28
Q
Inputs
30
Outputs
26
34
33
29 127 1 25
abc
d
e
9
12
Connect
.10 to .25
None
.25 to .35
d-f
+8 v
.35 to .50
c-f
+4v
.50to.90
c-d-f
.90 to 1. 5
b-g
1.5 to 2.3
b-f
2.3 to 4.7
a-g
4.7 to 8.0
a-f
B.O to 10.0
a-b-f
10 to 20
11
Outputs
OS
18
Jumpers
P. W. (~sec)
43 145
39 141
1
Q
Inputs
e
a
9
Circuit 4
--051
--049
~
48
32
16
o
a-f, g-e
La GIC DIAGRAM, aT 18
a
b
c
d
e
9
OT14
LAMP DRIVERS
The QTl4 has 12 circuits, each capable of switchi ng an externally supplied current of 200 ma at voltage up to +28v.
Driver outputs go to front-edge contacts on the module for
use with ETll cable connectors. The keep-warm resistors
and overload protection diodes connect to common ground.
Output rise and fall are slowed to minimize noise. Oper-
ating frequency is limited by lamp response.
for similar circuit.
Power Requirements:
Dissipation:
Refer to RTl4
+4v, 268 ma av., 535 ma max.
+8v, 41 ma
2.47 watts max.
+8v~51
+4v
-<>49
~
48
32
16
o
Note: c. r. is common return
LOGIC DIAGRAM, QTl4
67
OT16
BCD-DECODER/ DRIVERS
The QTl6 module contains ten high-current drivers, suitable fordriving lamps or relays. The drivers are controlled
by a BCD-to-decimal decoding network; this makes it possible to drive a ten-lamp display directly from any BCD output without the need for intervening gating. Both logic
phases, non-inverted and complementary, must be provided.
Each AND gate in the decoding network also has an independent AND input which can be used to inhibit the driver,
or drive it independently (with all BCD input lines True).
Outputs are supplied to circuit etch contacts at the front
edge of the module for connection to cables via a pair of
ETll cable connectors. In addition, back-panel pi ns, 1, 2,
and 3 are connected strai ght through via etch to correspondi ng front-edge contacts.
Max. operating frequency:
Circuit delay:
Output switching capability:
Load imposed by each
input term:
Power Requirements:
Dissipation:
Individual lamp connection,
D~
C~~n I':••round ..'um/'---------'
common lamp ground return
1
1 2
2"
4
28 39 30 38 22 46
)H}
8
12
~
1
~-
>p
11')13
""'--
1
~
"""--
~
-L-')
1 ')
>R
')
Front edge H or 8 (common relay positive return)
o
Fro~t.
2
14
)M
edge
-=•
Individual relay connection
:2UWIY
l
Relay Connection
) F
) 6
5
) L
6
) 10
) K
J
3
11
4
7
) 9
OT17
BCD-DECODER/ INDICATORS
QTl7 contains 12 white indicator lamps mounted near the
front edge of the module. This module is pin-compatible
with QTl6 and may be used for local checkout of logic
prior to installation of that Decoder-Driver Module.
A BCD - to-decimal decoding network controls 10 lamps;
each of the other two lamps are preceded by a 2-input
AND. All lamps can be operated independently by leaving
the decoding network input lines open (True), and controling each lamp using the independent input provided.
>E
>5
8
This indicator module operates from standard T Series logic
level inputs. The lamp turns On when all inputs at its controlling gate are True.
) D
9
For pin number assignments and basic overa II logic arrangement, see QTl6 logic diagram.
) 4
~ ~
20
Lamp Connection
common relay
positive return
>--_-----<_-+-+-~)
) N
18
LOGIC DIAGRAM, QTl6
68
,
5
"4
250 Khz
0.5 fJsec
28v max., 200 ma max.
4 Unit Loads on pins 30,38,
22, 46; 5 Unit Loads on pi ns
28, 39; all others 1 Unit Load
+4v, 220 ma av., 369 ma max.
+8v, 33. 6 ma av., 43. 2 ma max.
2.0 watts max.
+rIV~
51 49 48 32 1& 0
Load imposed by each
input term:
Power Requirements:
4 Unit Loads on pins 30, 38, 22,
46; 5 Unit Loads on pins 28, 39;
all others 1 Unit Load.
+4v, 404 ma av., 504 ma max.,
plus 45 ma for each On lamp
+8v, 33. 6 ma av., 43. 2 ma max.
2.6 watts max. w/bulbs off
RT14
RELAY DRIVERS
The RTl4 has 12 circuits, each capable of switching an externally supplied current of 200 ma at voltage up to +28v.
Driver outputs go to front-edge contacts on the modu Ie for
use with ETll cable connectors. The peak inverse voltage
protecti on di odes are connected across the re lay coi Is by
connecting common return to tv. Output rise and fall are
slowed to minimize noise. Operating frequency is limited
by relay response. Refer to QTl4 for similar circuit.
Power Requirements:
Dissipation:
Note:
Tr~
514948321& 0
+4v, 268 ma av., 535 ma max.
+8v, 40.8 mao
2.47 watts max.
c. r. is common return
LO GIC DIA GRAM, RTl4
ST14
MANUAL TOGGLE SWITCHES
The STl4 module has fifteen SPDT toggle switches for manually setting logic levels into gating circuits, or other use.
Contacts are rated for 5 amp. at 115v. In the diagram below, switch is shown in the 11111 position of the handle.
Pin Connections
()
Ckt.
C2
C3
Cl
Ckt.
C2
C3
Cl
Ckt.
C2
C3
Cl
1
46
45
47
6
43
42
44
11
39
38
40
2
34
29
35
7
37
36
41
12
31
30
33
3
21
20
22
8
27
26
28
13
24
23
25
4
11
7
12
9
14
13
19
14
17
15
18
5
2
1
3
10
5
4
6
15
9
8
10
~
C2
r
1
C3
()
69
ST41*/ST44
READ-ONLY MEMORY
The 5T44 stores sixteen 8-bit bytes in a diode matrix. When
one of sixteen input lines is energized (together with its
strobe line) an 8-bit pattern appears at the outputs. The 8bit pattern that results from a given input isalwaysthe same,
and is determined by the pattern of diodes connected between the input Iine and the output Iines. Presence of a
diode between an input line and a particular output line
produces a 1 in the particular output whenever the input
goes True; absence produces a a (see examples on logic diagram).
If two input Iines are raised simu Itaneously, then each output line will contain the logical OR of the bit-pairs which
were energized. For example, if input 1 normally provi des
1001000 1 and input 2 normally provides 01010011, then the
output wi' I be 110 100 11 when both input 1 and input 2 are
raised together.
Input 1
1
a
a
The 5T44 acts as a memory: when one address (one of sixteen input lines) is made True, a predetermined 8-bit byte
appears at the output. Outputs are normally a (low) when
input is a {low). Each 5T44 module is supplied with a diode
in place at every crossover, initially providing a memory
whose output is all lis. Zeros are entered where desired by
clipping out diodes with a wire cutter (shown in the example
below by the di agram X 14
-- - ).
31
ENABLE (STROBE) A
1
a
a
a
1
+
+
+
+
+
+
+
+
Input 2
Output
a
1
1
1
a
a
1
1
a
a
a
a
1
1
1
1
12
ENABLE (STROBE) B
CR49-1
1
02
CR52-2
CR49-2
03
CR52-3
CR49-3
~
1
~
CR52-4
CR49-4
1
04
9
1
0
0
)( 14
CR49-5
~
I. CR52-5
05
0..
l
06
CR52-6
CR49-6
1
CR52-7
1
CR52-8
CR49-7
CR49-8
Note:
Typical output equation:
01 = (A)(CR49-l) + .... + (D)(CR52-l) + • . • . + (P)(CR64-1)
Where CR49-1 indicates diode CR49-1 i!t connected and term
CR52-1 indicates diode CR52-1 is disconnected, etc.
LOGIC DIAGRAM, 5T44
70
The number of words stored can also be expanded, by ORing outputs of additional 5T44 modules to maintain the same
number of output buses.
The ORing characteristic makes it possible to store more than
sixteen8-bit bytes per module, providing that more than one
input is raised at once, and providing the resulting pattern
is not already present on the module.
An example of how these two techniques can be combined
to create a read only memory containing thirty-two 16-bit
words is shown in the diagram below.
A 4-bit binary addressing control for the sixteen input lines
can be created with a BTl2 module, which accepts a 4-bit
input and decodes in straight binary fashion to 1-of-16 outputs. Input to the BTl2 can be derived from a 4-bit counter.
Thus, the combination of 4-bit counter, BTl2 decoder, and
5T44 memory creates an economical 16word program control.
Word length can be expanded in increments of 8-bits by paralleling the input I ines of additional 5T44 modules. Each
time an input on one 5T44 is raised, resulting in 8-bits of
output, a corresponding input on another 5T44 is also raised,
resulting in 8 more bits of output.
*
10 MHz
Maximum operating frequency:
Circuit delay:
Input loading:
50 nsec maximum
1 unit load/input
8 unit loads/enable (strobe)
+4v, 262 ma av., 468 ma max.
+8v, 67. 2 ma av., 86. 2 ma ma>
2.8 watts max.
Power requirements:
Module dissipation:
This module is also available with diodes not inserted. A package of 100 loose diodes is included.
the module by inserting diodes instead of removing them. Request Model 5T41.
The user programs
32 inputs
(One True at a time)
~
________________A,_________________
\
(
1-------16
17- -- -
---32
-------e----,
5T44
5T44
8
-------
-------
-------
-------
16-Bit
OUTPUT
WORD
9
I
5T44
5T44
I
16
Expansion to thirty-two 16-bit Words (512 bits)
71
WT49
REFERENCE VOLTAGE REGULATOR ,
The WT49 module contains two electrically independent
precision 35 volt regulators. The regulators have remote
sensing capabi lity and are short circuit proof for a period
of 30 seconds.
able to either leave an empty card slot beside the component side of a WT49, or place a cable-plug or other passive
module beside the component side.
Output voltage:
Each of the regulators may be used for either plus or minus
polarity, much like a battery, by grounding the appropriate side. One WT49 module can supply both +35v and
-35v reference voltages for use with digital-to-analog
converter modules such as the DT24. One WT49 module
can supply twenty-four DT24 modu les.
All pins shown below on on~ input or output should be
bussed together on the connector, or on long runs shou Id
be wired in parallel to reduce the current per wire. Where
IR drop is expected to be a problem, wire the sense inputs
to a representative point in the load. Otherwise wire
sense inputs to outputs on the WT49. The WT49 requires
one card slot. Because of the high dissipation it is advis-
1------,
I
I
I
I
I
i
I
Output current:
Load regulation:
Ripple re jection:
Temperature coeffi cient:
Operating temperature range:
Power Requirements:
(each regu lator)
Modu Ie dissipation:
(both regu lators)
4
+35v
12.5 watts max.
+ Input
+ Output
Analog
Regulator
+10%
-15%
Raw Power
50 vdc
~
35 vdc, + or -, adjustable
to within 3 mv
o to 250 ma., each regulator
0.03%
400: 1 min.
<0.003%/'e from oOe to
0
+55 e
0
oOe to +55 e
42 vdc min. to 55 vdc max.
at 300 ma max., isolated
from ground. May be obtained from PT23 supply.
+ Sense
10
- Sense
36
Ground
44
- Input
- Output
15
+ Input
+ Output
I
I
I
I
I
L
Analog
Regulator
+ Sense
I
"':O~~aw_Suppl~.J
-35v
Analog
Regulator
+10%
-15%
Raw Power
50 vdc
26
CONNECTION AS ±35 vdc SUPPLY
72
- Input
- Sense
- Output
INPUT-OUTPUT DIAGRAM, WT49
30
WT53
WT54
25V REFERENCE VOLTAGE REGULATOR
15V REFERENCE VOLTAGE REGULATOR
The WT53 and WT54 each contain two electrically independent precision regulators, which are short circuit proof
for a period of 30 seconds. The WT53 delivers ±25 volts,
while the WT54 delivers ±15 volts.
Characteristi c
Units
WT54 input current
Dissipation, per module
amp.
watts
Each regulator circuit may be used for either plus or minus
polarity, much like a battery, by grounding the appropriate side. Thus one module with its two independent regulator circuits can supply both + and - reference voltages
(see connection diagram).
Output vol tage can be ad jus ted over a range of ±2. 5
volts on WT53, and ±2 volts on WT54.
* Isolated from ground. May be obtained from PT23 or
PT26 supply.
** Do not use this value of maximum input voltage under
maximum current load.
A II pi ns that are shown on one input or output shou Id be
bussed together on the backplane connector. On long
runs use parallel wires from the regulator to the destination
to reduce IR drop.
One regulator module requires two card slots. However,
because of the high dissipation it is advisable to either
leave an empty slot beside the component side, or place
a cable-plug or other passive module beside the component side.
Min.
Typ.
1.2
24
40
42
+ Input
Raw PONer
+10%
50 vdc -15%
Max.
+ Output
- Input
43
- Output
Circuit 1
(WT53)
Characteristic
Units
Min.
Typ.
Max.
WT53 nominal output
voltage t
WT53 voltage adjust
resolution
WT53 output current,
each ckt. (I out)
WT54 nominal output
voltage t
WT54 voltage adjust
resolution
WT54 output current,
each ckt. (I out)
Load regu lation
Ripple re jection
Temperature coefficient
0
(from OOC to +55 C)
Operating temperature
range
28
(WT54)
mv
31
10
- Input
- Output
Circuit 2
11
WT54 CONNECTION DIAGRAM
15
±20
1.0
1
50:1
0.05
0
vdc
amp.
29
vdc
19
,------l
I
I
+15v
I
%I'c
°c
+ Output
0.4
vdc
amp.
%
+ Input
±40
amp.
mv
30
25
vdc
+55
Inputs
WT53 input voltage range *
(for nominal outputs)
WT53 input current
WT54 input voltage range*
(for nomi na I output)
+10%
25 vdc -15%
Outputs
49
22.5
55**
0.55
26**
I
I
I
Analog
Regulator
=p
-15v
+15v
I
I
I
I
Raw Supply
L-- _ _ _ _ _
JI
Analog
Regulator
-15v
INPUT-OUTPUT DIAGRAM
73
XT10
LINE TERMINATORS
The XTlO module has forty-six 220 ohm resistors returned to
+4v. They are used as line terminations for back panel wiring. Each terminator uses 5 unit loads of the driving circuit's fan-out. A maxi mum of 2 terminators may be used
with one driver output, connected to the ends of two driven
lines. No more than 1 terminator may be connected to one
driven line. The terminators are required to achieve high
propagation speeds and minimize signal reflections when
logic lines are long. They need not be used when lines are
short or when lower propagation speeds are acceptable.
Detai led wiring ru les, and delay formu las, are given in
Appl ication Bu Iletin No. 64-51-04B.
T-SERIES
T-SERIES
T-SERIES
T-SERIES
T-SERIES
74
Power Requirements:
Dissipation:
+4v
+4v, 414 ma av., 828 ma max.
1 .65 watts av., 3.30 watts max.
Of the 52 pins on the module, all
are individua Ily connected to terminators except 16, 32, 48, 49,
51 and O.
III. ACCESSORIES AND SERVICES
OTHER ESSENTIAL COMPONENTS
OF A MODULE FAMILY
SDS offers a full line of T Series accessories, mounting hardware, and tools. They eliminate mechanical design cost,
reduce procurement lead time, and reduce assembly time.
SDS also offers a full range of services and documentation
that save your engineering time.
Accessories include:
1.
Cabinets with doors, optional side panels, ac power
connectors, and optional swing-out mounting case
containers (swing frames).
2.
Individual 32-module mounting cases, and 3-case
90-module drawer; with hinsed doors or fixed panels
to cover mounting cases or to fill blank spaces.
3.
Blower assembly for cool ing.
4.
Both compact and high-output power suppl ies.
5.
Cable connectors and cables, and cable-plug modules.
Both ribbon and coaxial cables are offered.
6.
Spooled wire, cut-wire jumper kits, wiring tools, and
individual module connectors.
7.
Accessory modules for breadboarding and troubleshooting.
8.
Indicator lamp.
ACCESSORIES
Full specifications and detailed drawings of accessories are
given in SDS catalog 64-51-15.
YT14, YTl9 and YT24 CABINETS
Three types of cabinets are available, all with outside
dimensions 63-3/8 inches high (including casters), 29-1/2
inches wide (without side panels) and 31-5/8 inches deep
(with back door).
One cabinet, Model YTl9, is made for mounting of individual 19-inch wide, 32-module mounting cases, power
suppl ies and blowers. A vertical control panel is included.
The cabinet al so contains ac power outlets, a circu it breaker, a local/remote switch, de wiring junctions and a power
cord. Top and bottom have protective grills. Side panels
(Model YT30) are optional. An insu lated, soundproof hinged back door is standard.
A 24-inch version of this versatile system cabinet is available as Model YT24. The YT24 is ideal for use with 3-high
and 7-high swing frames.
A third type, Model YTl4, shown below, is designed to
mount one or two swing frames which can each hold three,
seven, or nine individual mounting cases, plus blowers. The
swing frames contain the blowers, and a Iso have front pane I
These cost-reducing services and documents are provided:
1.
Consulting engineering by experienced application
engi neers and by techni ca lIy ori ented sa les engi neers.
2.
SDS designed and built special-order modules, made to
your specifications at reasonable cost.
3.
Application bulletins which give detailed, step-by-step
instructions to help you design and bui Id your system,
all the way from system planning through logic design,
assembly, wiri ng and documentation.
4.
Data sheets on all products, which provide all technical detai Is.
5.
Logic sheets, on vellum, for all modules, to reduce
logic design time, wire listing time, documentation
time, and troubleshooti ng time.
6.
Fast, off-the-shelf delivery of new modules or spares.
7.
Modu Ie repair faci lity.
8.
One-year warranty on all SDS products.
75
covers in place for unused mounting case spaces. Double
doors (shown open) completely enclose the mounting cases.
Hinged back door, ac power sockets, and ac power cord are
included in the YTl4 cabinet. Side panels (Model YT30)
are optional. Swing frame model numbers are YT43 (3-high),
YT47 (7-high), and YT49 (9-high).
MT SERIES MOUNTING CASES
MTlO, MT12, MT30, and MT32 Cases
Standard cases accommodate 32 modules, are 5.25 inches
high, 7.90 inches deep, and fit into a standard 19-inch
width rack. Wiring terminals are either solder tailor wire
wrap. Each case comes with connectors, +4v and +8v
power wiring, and ground plane installed.
Four combinations of fixed or hinged mounting, and the
two pin types are available:
1.
2.
3.
4.
Solder terminals, fixed mount: MTlO
Solder terminals, vertical hinge, right or left: MT30
Wire-wrap termina Is, fixed mount: M Tl2
Wire-wrap, vertical hinge, right or left: MT32
All cases can be mounted with pins toward either front or
back of cabinet. All brackets and hinges are adjustable
and reversible, front-to-back and left-to-right. Cable
troughs and pin protectors are standard on all mounting
cases.
MT42 Two-high Mounting Case
MTDl and MTD2 High Density Cases
The MTDl and MTD2 high density drawer-type mounting
cases each contain three basic card cages with power and
ground planes, identical to those used in the mounting
cases described above, mounted in a drawer with tiltable
slides which use ball-bearing rollers. Each case holds up
to 90 modules, is 8.73 inches high, 22.03 inches deep,
and fits into a standard 19-inch rack.
The slides allow the drawer to extend full depth from the
0
0
cabinet and to be ti Ited in 45 increments over 180 from
drawer-front point up, to pointing down.
A ZT20 blower with washable air filter is included. All
power and ground connections to the three card cages are
brought out to a terminal board. A module locking bar is
provided for each card cage, and both top and bottom protective covers are furnished.
Panel mounted indicators and switches can be mounted
behind the 1.09 inch deep front panel, which comes with
two folding handles and captive fastening screws. The
MTDl case has solder-tai I terminals whi Ie the MTD2 has
wire-wrap terminals.
MT32 Hinged-Mount Case, Showing Ground Plane
M Tl3 and M T33 Cases
The MT13 (fixed mount) and MT33 (hinged mount) cases are
similar to MTlO/MT12 and MT30/MT32 cases, but are without the backplane/connector assembly. These cases facilitate combination of special equipment with T Series modules
in the same assembly. The user provides his own connectors,
ground and power bussing, etc.
MT42 Two-High Case
The latest addition to the SDS line of mounting cases is
model MT42, designed to hold both double-height socket
boards (ZJ14) and standard size modu les, as well as the
compact PTl 0 power supply.
MTDl High-Density Drawer Mounting Case
76
ZT SERIES DOORS
Model PTl2 High Output Supply
Three 19-inch wide hinged doors, reversible left or right,
are avai lab Ie. Each door has a spring loaded latch at the
end opposite the hinge. Indicator lamps, switches, meters,
and connectors can be mounted in the doors.
Model PTl2 handles higher power applications. It occupies
the full 19-inch rack width, is 5-1/4 inches high and 22inches deep. Front panel has a cooling fan, a removable
and washable air fi Iter, an on-off switch, a multi-range
switched voltmeter, and a pilot light. Included are output
voltage adjustments, short circuit and overvoltage protection,
and remote sensing. PTl2 can power from 125 to 200 modules.
Model ZTl7
Model ZTlS
Model ZTl9
5-1/4 inches high
(covers one M T seri es case *)
10-1/2 inches high
(covers two M T seri es cases *)
15-3/4 inches high
(covers three MT series cases*)
*except MTD1, MTD2, which have built-in front panels
Four 19-inch wide cover panels are also offered:
Model
Model
Mode I
Mode I
ZT40-1
ZT40-2
ZT40-3
ZT40-4
1-3/4 inches high
3-1/2 inches high
5-1/4 inches high
7 inches high
47 to 63 Hz, 1 cp, 115 vac, 127 vac,
20S vac, or 220 vac
Outputs: +4vdc, 60 amp.
+Svdc, 12 amp.
-Svdc, 4 amp.
25 vac, 4 amp.
(Regulation: ±5% on all outputs)
Weight: 100 lb.
Input:
ZT20 BLOWER ASSEMBLY
The Model ZT20 Blower Assembly includes a housing which
contains three 100 cfm muffin fans mounted side-by-side,
three finger guards, a washable air filter, and mounting
brackets. The entire assembly is 19-inches wide, 3-1/2 inches high, and 7-inches deep, and mounts with the fan blades
turning in a horizontal plane. One ZT20 assembly delivers
300 cfm.
POWER SUPPLIES
Model PTlO Compact Supply
PTl2 High Power Supply
Model PTlO fits into any MT mounting case, occupying 15
slots. It can power from 20 to 40 modules depending on
load. Included are output voltage adjustments and protection against short circuits and overvoltage. Retainers are
provided to lock the supply into the mounting case. The
supply may be mounted in any position.
Input:
47 to 66 Hz, 1 cp, 100 vac to 230 vac
Outputs: +4vdc, 10 amp.
+Svdc, 2 amp.
-Svdc, 0.6 amp.
22 vac, 1/2 amp.
1
Regu lation:
±5%
Weight: 12 lb.
Models PTl6, PTlS, PTl9 Large System Suppl ies
The PTl6 supply provides logic power (+4v, +Sv, -Sv) in
sufficient quantity to operate about 200 T Series modules.
The PT1S provides higher voltages for use in peripheral or
analog equipment: +25v, -25v, and +50v, as well as additional +Sv. Both supplies draw their input, which is at
2, 000 Hz, from the PTl9 Inverter. The PTl9 converts 60 Hz,
120 vac to 2,000 Hz, 120 vac. Use of the higher frequency
permits Iighter weight suppl ies at point of use and higher
efficiency of distribution. The PTl6 and PTlS both mount
on the side of a swing frame. All supplies have overcurrent
and overvoltage protection.
PT16 Specifications
Input:
Outputs:
PT10 Compact Power Supply Installed Beside Logic Modu les
Output load max:
2,000 Hz (±200 Hz), 1cp,
120 vac ± 10% rms, regu I ated,
modified square wave, at 10
amps. max.
+4.0 vdc (±0.2v) at 75 amp.
+S.O vdc (±0.4 v) at 40 amp.
-S.O vdc (±0.5v) at 5 amp.
600 watts
77
Output control s:
Margin switches for +10% and
- 10% steps, and ± 10% output
voltage control with potentiometer
33 Ibs.
Weight:
PTl8 Specifications
2,000 Hz (±200Hz), 1cp, 120
vac, ± 10 rms regu Iated, modified square wave, at 5 amps.
max.
+8.0 vdc, (±0.4v) at 8 amps.
+25 vdc at 6 amps
-25 vdc at 1 amp.
+50 vdc at 1 amp.
290 watts
± 15% overall
161bs.
Input:
Outputs:
Output load max:
Output regulation:
Weight:
PT19 Specifications
45 to 66 Hz, 1cp, 120 vac or
127 vac or 208 vac or 220
vac; 2,760 watts max.
2,000 Hz (± 100 Hz) modified
square wave, 120 vac, ± 10%
rms, regulated
1,200 va
101 Ibs.
Input:
Output:
Output load max:
Weight:
PT23 and PT24 Digital!Ana log Power Suppl ies
The PT23 and PT24 Supplies provide power for a typical 32module analog chassis, such as the SDS MD51 MultiplexerDigitizer, or the DA40 D-to-A Converter. Each consists
of a PTlO logic voltage supply and a separate analog voltage supply, designed for compact 19-inch mounting.
PT23
PT24
Input (47-66Hz, 1 cp
115 vac ± 10%, 225 watts
)
115 vac ± 10%, 570 watts
Outputs
of the PT23.
Specifications of the PT26 are:
Input: 47-66 Hz, 1 , 115 vac ±10%, 125 watts
Outputs:
50 vdc, 0.45 amp.
50 vdc, 0.45 amp.
25 vdc, 1.2 amp.
25 vdc, 1.2 amp.
(floati ng)
(floating)
(floati ng)
(floati ng)
unreg.
unreg.
I Panel Height:
Weight: 25 Ibs.
CABLING COMPONENTS
ET Series Coaxial Cabling Components'
These coaxial cabling components minimize noise pickup
and signal distortion, and simplify the mechanical aspects
of cabling. 'The mechanical arrangement is shown in the
diagram below. Each MT series mounting case has a cable
trough attached to its bottom edge. Severa I fourteenconductor 33 ohm coaxial cables (Model ET12) may be
placed side by side in the trough. The shields and inner
conductors of each cable are individually soldered to
fourteen common ground points and fourteen independent
signal points on a front-edge cable connector (Model ET11).
Another ET11 Cable Connector is tied to the end of another
cable and the two ET11 1s are bolted together, through holes
in the front edge of an appropriately etched module. A
pressure contact is made between the contacts on the ET11 1s
and the modu Ie etch.
A preassembled cable-with-connectors assembly, using
ET12 Cable and an ET11 Cable Connector at each end, is
avai lable as Model ET10-XX, where XX specifies the
length of cable in feet.
A preassembled cable-with-connector assembly with an
ET11 at only one end, using ET12 Cable, is avai lable as
Model ET14-XX-Y. Here, XX specifies length in feet
and Y defines whether the ET11 is to be mounted on the
etch side (normally left side) of a modu Ie or on the component side. Y = E for etch, C for component.
+4 vdc, 10 amp!} ±5%
+4 vdc, 8 amp! } ±5%
+8 vdc, 3 amp
+8 vdc, 2 amp
reg.
reg.
-8 vdc, 0.6 amp
-8 vdc, 0.6 amp
*50 vdc, 0.45 amp}
+25 vdc, 2.5 amp} ±0.5%
*50 vdc, 0.45 amp unreg.
-25 vdc, 2.50mp reg.
+15 vdc, 1 amp} ± 1%
t Adjustable to 5 Volts for
- 15 vdc, 1 amp
reg.
* floating
J Series Operation
Weight
50 Ibs.
50 Ibs.
Panel Height
5-1/4 inches
5-1/4 inches
PT26 Analog Power 'Supply
The PT26 Supply consists of the analog supply portion of the
PT23, but does not include the logic voltage supply section
Cable Component Detai I s
78
3 - 1/2 inches
A Model ETl3 Dummy Load must be placed at the end of a
cable run to properly terminate the run. This item consists
of an ETll Connector which has fourteen 33 ohm resistors
soldered between the fourteen ground and fourteen signa I
connection points.
Modules which are designed to accept ETll connectors have
front-edge contacts, twenty-eight on each side, fourteen
connected together to ground and fourteen independent for
signal connections. On most module types the ground and
signal connections on one side are connected to corresponding etch connectors on the other side by plated-through
holes. On some modules they are independent. Modules
which have the front-edge contacts are: ATlO, ATll,
ATl2, OTl4, OTl6, RTl4, and ZT23 {described below}.
When ETll Cable Connectors are attached, these modu les
cannot be located in adjacent module spaces, but a module
of another type may be placed in the intervening slot.
differential amplitudes exceeding 2 volts after 2000 feet
of travel. Terminating resistors on the AT53 1s prevent
signal reflections.
o
The system operates over the temperature range 5 C to
0
50 C. Electrical characteristics of the cable itself at
25°C are as follows:
Surge Impedance:
110 ohms -0%, +10%
D. C. Resistance:
25 nominal ohms per 1000
feet. {Single wire} wire
size: 24 gauge.
Delay Time:
1 .6 ± .025 nanoseconds
per foot, each pair of wires.
Signal Rise Time:
115 ± 15 nanoseconds per
1000 feet, measured at the
10% and 90% amp Iitude
poi nts of the waveform.
Signal Fall Time:
190 ± 15 nanoseconds per
1000 feet, measured at the
10% and 90% amplitude
poi nts of the waveform.
Crosstalk:
With all but one pair of
lines driven by a pulse
havi ng a 10 nanosecond
rise time, the noise on the
undriven pair shall not
exceed 0.25 volt peak to
peak at 1000 feet.
Dielectric Withstanding
Voltage:
5000 VDC, from wire
to wire.
Insulation Resistance:
100 Megohm minimum per
1000 feet, measured at
500 volts DC.
Maximum Dispersion:
400 nanoseconds at 2000 feet.
ET32-XXXX Long Line Cable Assembly
The ET32-XXXX Long Line Cable Assembly is designed to
be used in con junction with a pair of AT52 Long Line
Cable Driver modules and a pair of AT53 Long Line Cable
Receiver modu les to transmit 14 differential digital signals
over lines up to 2000 feet long. For distances less than
200 feet use of AT10, A Tll, and AT12 modules with
ETl2-XX Cable Assemblies is recommended.
The ET32-XXXX Long Line Cable Assembly consists of the
following three sub-assemblies:
1) A center section of customer specified length of
15 twisted pair cable with a 32 pin male connector on one end and a 32 pin female connector
on the other end.
2} A terminal section consisting of 35 feet of 15
twisted pair cable with a mating 32 pin female
connector on one end and a pair of ETll type
connectors on the other end, and
3) A terminal section consisting of 35 feet of 15
twisted pair cable with a mating 32 pin male
connector on one end and a pair of ETll type
connectors on the other end.
The ETll type connectors are designed to mate the
ET32-XXXX Long line Cable Assembly to the etched connector on the outside edge of each of the A T52 and A T53
modu les.
The ET32-XXXX Long Line Cable Assembly in conjunction
with a pair of AT52 and a pair of AT53 modules provides
a low cost transmission system with ±7 volts common mode
rejection, capable of transmitting 1 Mhz bandwidth signals
up to 1000 feet or 500 Khz bandwidth signals up to 2000
feet. The system has good immunity to crosstalk and externally injected noise. The pair of AT52 drivers send 14
complementary signals, having a starting differential amplitude of about 6 volts, along the twisted pair cables. Peak.ing filters following the drivers enhance the high frequency
r:omponents which experience greater attenuation along the
line. Signals received at the pair of AT53 receivers have
The center section of the long line cable assembly is manufactured to customer specified length. Each end section
automatically includes 35 feet of cable. When ordering,
the cable assembly should be designated as ET32-XXXX
where XXXX specifies the required length of the center
portion of the assembly in feet. Example: A long line
cable assembly with a center section 240 feet long would
be ordered as ET32-0240, and wou Id reach drivers and
receivers separated by a maximum distance of 240 feet
+ 70 feet = 310 feet.
ZT45 and ZT46 Ribbon Cable Assemblies
The ZT45 and ZT46 Ribbon Cable Assemblies use a flexible
cabl e contai ni ng fifty-two copper foi I conductors embedded
in a durable ribbon of Teflon approximately 3 inches wide.
Twenty-seven of the conductors are designated as ground
conductors whi Ie twenty-five can carry signa Is, {a Ithoug h
some are normally used as ground connectors also}. The
signal and ground conductors alternate across the width of
the ribbon, with ground conductors at both outside edges.
79
ZT45 Ribbon Cable
ZT46 Ribbon Cable
NOTES:
1. Coble conductor to be terminoted point to point.
Pins 0, 16, 32, 48 Com. and tied to ground conductors. Pins 49 and 51 not used.
I
PRINTED CIRCUIT
PATTERN DELETED
FOR CLARITY (TYP)
DIM."A"~
.75 MIN
TYP
2. Electrical Chorocteristics:
o. Characteristic impedance:
95 ohmSZoSll0 ohm
b.
Insulation resistance:
1000 megohms minimum between contocts
Dielectric withstanding voltage:
500 vdc
MODULE
COMPONENT
SIDE
A
A
t
t
CABLE (2 LAYERS) L _ _ _ _ _ _ _ _ _ _ _ _ _ _..
MODULE COMPONENT
SIDE SHOWN
SOLDER CONNECTION (TYP 104 PLACES)
PRINTED WIRING
BOARD (REF)
VIEW A-A
NO SCALE
Assembly Drawing, ZT45
80
RIBBON CABLE STANDARD LENGTHS, ZT45 (VERTICAL)
RIBBON CABLE STANDARD LENGTHS, ZT46 (HORIZONTAL)
length "A"
in Inches *
Length "A"
in Inches *
Tolerance,
in inches
Maximum dc resistance,
in ohms
1.80
±O.05
1.0
7.00
-t<:l.20
-0.00
1.0
12.70
-t<:l.20
-0.00
1.0
18.40
-t<:l.20
-0.00
1.0
23.70
-t<:l.20
-0.00
1.0
28.90
-t<:l.20
-0.00
1.2
29.90
-t<:l.20
-0.00
1.2
39.50
-t<:l.20
-0.00
1.5
Tolerance,
in inches
Maximum dc resistance,
in ohms
36
+1.0
- .0
1.4
44
+1.0
- .0
1.6
85
+1.0
- .0
2.7
100
+1.0
- .0
3.2
115
+1.0
- .0
3.5
Refer to Assembly Drawing, ZT46
Refer to Assembly Drawing, ZT45
PRINTED CIRCUIT
PATTERN DElETED
FOR CLARITY (TY P)
IDIM'''A''~
~-------------------------,
.~MIN· ~--~~o---~------=-~------------------'
o
(TYP)
MODULE ETCH
SIDE SHOWN
MODULE
COMPONENT
SIDE SHOWN
A
t
52-CONDUCTOR
CABLE (2 LAYERS)
NOTES:
1.
Cable conductor to be terminated point
to point. Pins 0, 16, 32, 48 common
an.d tied to ground conductors.
Pins 49 and 51 not used.
2.
Electrical Characteristics:
a. Characteristic impedance:
95 ohms :s Zo ::; 110 ohms
TAPE (BOTH ENDS)
SOLDER
CONNECTION
LAMINATED
MODULE
• 062 REF
ADHESIVE
b. Insulation resistance:
1000 megohms minimum between
between contacts
c. Dielectric withstanding voltage:
500 vdc
MODULE ETCH
SIDE (REF)
VIEW A-A
NO SCALE
Assembly Drawing, ZT46
81
Two ribbons are always run in parallel; their edges are
sewn together with nylon thread for handling convenience.
This provides a total of 104 conductors per cable: Fiftyfour ground conductors and fifty signal conductors.
is also present on the board. The ZTl5 is most useful for
low frequency work (under 1 Mhz) where the effects of
parasitics are not important.
The advantages of ribbon cable over coaxial are threefold.
First, impedance is 100 ohms rather than 33 ohms, eliminating the need for specia I cable drivers and receivers for
chassis interconnections up to 115 inches. Second, it results in a more compact installation with neater inter- and
intra-cabinet wiring connections. Third, user can wire and
test his mounting cases individually, then interconnect
them with ribbon cable, rather than wiring across several
adjacent mounting case back panels with logic wire.
Each cable assembly has a plug at both ends. The signal
and ground conductors are soldered to the plug at appropriate points. The plugs are etched-circuit cards with laminated ground planes, identical in size and shape to SDS
T Series and J Series modules. They plug into a slot in
any SDS MT model mounting case.
In the ZT45 assembly the cable is connected to the plug
at right angles to the plug's long axis, so that when plugged
into a mounting case, the cable enters the case vertically,
through a ventilating s'lot between modules. The ZT45 is
designed for connecting signals between mounting cases
stacked vertically in the same cabinet.
ZT23 Cable Plug Module (Pressure Contacts)
In the ZT46 assembly the cable is connected to the plug
parallel to the plug's long axis, so that when plugged into
a mounti ng case, the cab Ie enters the case from the front.
This assembly is most useful for routing signals between
mounting cases at front and rear of the same cabinet, or
between cabinets.
The cable may be folded for installation convenience. A
great advantage of ribbon cable is that it may be clamped
flat against the side of a cabinet and folded at 45 degrees
to form a right-angle turn.
The ZT45 and ZT46 assemblies are offered only in standard
lengths given in the tables on page 81. Lengths are measured from the edge of one plug to the edge of the other
(identified as dimension "A" in the figure on page 81).
When ordering specify length in inches. For example, a
ZT46 with an "A" dimension of 44 inches should be ordered
as ZT46-44.
ZTl5 and ZT23 Cable Plug Modules
Two cable-plug modules are available, the ZT15 and ZT23.
The ZT23 Cable Plug Module accepts either one or two 14conductor ETl2 cables, connecting through ETl1 connectors.
The contacts on the two sides of the module are independent. Each side has a straight-through etched circuit pattern to take the signals from the cables straight to back
panel pins.
The ZTl5 Cable Plug Module performs the same function
but does not have front-edge contacts. Instead, up to 44shielded conductors can be soldered directly to the module.
An etch pattern for adding passive decoupl ing components
82
ZTI5 Cable Plug Module (Soldered Connections)
WIRING COMPONENTS AND TOOLS
ZT52 Logic Wire
The wire required for connection to back panel wrap terminals is a special type, with high tensi Ie strength solid copper wire and a cut-proof insulation. The usual insulation,
made from polyethylene or teflon, tends to cold flow over
a period of time when placed under pressure such as exists
when a wire is pulled tight against a wrap post. Eventually
this causes intermittent short circuits which are extremely
hard to find. SDS provides a 1, 000 foot spool of wire,
Model ZT52, for making wrapped connections. The same
wire is suitable for soldered connections. In this case,
however, a softer copper can be used since the wire need
not grip the post.
VT10 Jumper Kit
TTl 1 and TT13 Wire Wrapping Tools
Model VTl 0 jumper kit contai ns an assortment of 500 sl ideon jumper wires, primari Iy for use in systems whose wiring
requires frequent change. This new approach offers significant improvements in reliability and convenience over
taper pin techniques. The terminals at the ends of each
wire slide on wire-wrap pins. Terminals may be stacked
two high on each pin. Wire is No. 24 AWG insulated
stranded copper. Wire lengths within each kit are:
The Model TT11 Cordless Power Wire Wrap Gun, with bit,
sleeve, and rechargeable battery is avai lable, together
with the Model TTl3 hand-operated unwrapping tool, which
is needed to remove improper wraps.
Length
Quantity
1.0"
2.0"
3.0"
4.0"
5.0"
6.5"
SO
SO
SO
SO
60
40
Length
S.O"
10.0"
12.0"
15.0"
lS.0"
27.0"
Quantity
20
20
15
10
10
5
VTll and VT12 Back-pane I Connectors
Model VTll Connector with wire-wrap pins and Model VTl2
Connector with solder-tails are provided for special module
installations. They are identical to those used in the MT
mounting cases.
Models TT1l and TT13 Wire Wrapping Tools
ZTll, ZT37, ZT53 and ZT60 Accessory Modules
The ZTll Blank Module has etched-circuit back-panel connectors. The remainder of the card is blank, for bui Iding
circuits as desired.
VT12 (Solder tail) and VT11 (Wire-wrap) Connectors
ZT65 Module Extractor
The ZT65 is a small plastic lever that mounts on any SDS
module. It provides the mechanical leverage and bearing
surface needed to make module removal simple and convenient.
Mounting
case (ref)
-----r--- --- :
Top front corner of module
ZT65
Module
Extractor
ZT65 Module Extractor
Model ZTll Blank Module
The ZT37 Breadboard Module (illustrated on next page) has
a versati Ie etch circui t pattern arranged for convenient
mounting of all standard components, including diodes,
capacitors, resistors, transistors or Ie's in TO-5 cans, flat
packs, or the 14-lead dual inline package. This module
permits custom bui Idi ng of special circuits whi Ie retaini ng
the advantages and mechanical compatibility of T Series
etch circuit construction.
The ZT53 Extender Module (illustrated on next page) has a
straight-through etched circuit pattern and a VTl2 connector mounted on its front edge. It permits the user to extend
S3
any module in front of the rack so that circuit operation
may be investigated whi Ie the modu Ie is plugged into the
rack. Contacts are Rhodium plated for long life.
SERVICES
AUTOMATED WIRING SERVICES
SDS uti lizes in-house computer programs to generate fully
documented wire lists from standard logic sheets completed
by the customer according to his logic design. Digitally
controlled machines wire the customer's mounting case back
panel according to the computer generated wire list. Ask
for Application Bulletin No.8 for details.
APPLICATION ENGINEERING
Application Engineers and technically oriented Sales Engineers are available at regional offices to aid in specification writing, system planning, and preliminary logic
design. These SDS engineers have considerable experience
in the design of both small and large scale digital and analog systems. Typical recent applications include: specialized data processors to compensate for earth curvature,
telemetry data converters, missile test sequencers, a digital
phase meter, a digital control for a large data display,
typesetting machine controllers, industrial process controls,
data reduction from linear accelerators, medical research
data processors, and interfacing units for SDS Sigma Computers.
Model ZT37 Breadboard Module
APPLICATION BULLETINS
The detai led design work is necessari Iy performed by the
module user. To familiarize the user and his assistants with
T Series design rules, and to provide specific product information, SDS has prepared a series .of fast-reading, selfteaching Application Bulletins, covering these topics:
Model ZT53 Extender Module
The ZT60 Blank Module is simi lar to the ZTl1, but has
copper foi I on both sides, for the production of custom
etched circuits. Connector contacts are provided, already
etched.
ZT39 INDICATOR LAMP
Model ZT39 miniature incandescent lamp mounts on a panel
through a 9/32 inch hole with mounting clip provided.
Wires can be soldered or wire-wrapped to the lamp. Any
T Series standard Ov/+4v logic level output can drive the
lamp, using the keep-alive circuit shown below to reduce
turn-on current, protecting both driver and lamp.
r-------:~'-+---a
ZT39
Buffer, Inverter,
or F. F. Output
84
--14 Unit Loads
Keep-alive
resistor
100 ohms
+4v
No.1:
Back Panel Wiring Design
(Pub. No. 64-51-04)
No.2:
Multifunction IC Logic Module, Model
FT19
(Pub. No. 64-51-05)
No. 3:
Logic Design
(Pub. No. 64-51-06)
No. 4:
Final Assembly and Wiring
(Pub. No. 64-51-07)
No. 5:
Wire Lists and Documentation
(Pub. No. 64-51-08)
No. 6:
Keyboard-Printer (Teletype) Interface
(Pub. No. 64-51-09)
No. 7:
T Series Module Testers
(Pub. No. 64-51-10)
No.8:
Automated Wiring Service
(Pub. No. 64-51-11)
These bu Ileti ns contai n tutoria I information, step-by-step
instructions, quantitative data, part numbers, pin numbers,
and a II other information that is necessary to get the job
done quickly. The series is being continuously extended
and other topics wi II be covered in future issues.
DATA SHEETS
Each customer is a Iso given a fu II set of up-to-date data
sheets covering all modules and accessories. Each sheet
describes a product in detail. For example, the following
data is given on each module:
1.
Functional description, and theory of operation
when necessary for a fu II understandi ng of the
module.
2.
Complete electrical specifications.
3.
Application data (circuit connections, etc.)
when necessary to fully utilize the module.
4.
Logic diagram (input-output diagram).
5.
Parts location diagram, with polarizing pins shown.
6.
Replacement parts list.
7.
Complete circuit schematic.
8.
Other data if required.
design engineer to delegate much of the wire-listing and
checking activity to other technical or clerical personnel.
Each logic sheet contains a logic diagram of the module,
printed on vellum, and annotated where necessary with
specific wiring hints.
SPECIAL MODULE DESIGN
The SDS Engineering Department will design and build modules with special configurations of standard T Series circuits,
or special supporting circuits, to customer specifications.
Sometimes this approach leads to lower total cost, particularly when a large number of similar modules are required.
WARRANTY
SDS provides a one year warranty from date of sale.
OTHER REFERENCES:
1.
"The Case For The Mi xed Approac h",
Computer Design magazi ne, Sept. 1966
2.
"The Ideal Logic Module Set",
EDN magazi ne, March 1968
3.
"Medicine For The Do-it-yourself Syndrome:
Digita! Modules", EEE magazine, April 1968
LOGIC SHEETS
For a nominal charge the user is provided with pads of logic
sheets for each module he buys. These sheets, which are
described in Application Bulletin No.5, can eliminate
many hours of drudgery and also make it possible for the
85
T SERIES PRODUCT INDEX AND PRICE II ST
Effective: 1 July 1969
QUANTITY DISCOUNTS
Order Exceeding
$ 5,000
10,000
20,000
Discount
Order Exceeding
$ 50,000
100,000
200,000
500,000
3%
5%
7%
Discount
10%
13%
16%
20%
Discounts apply to single purchase orders placed and not subsequently altered in
any manner by one customer specifying delivery and billing to single addresses.
SDS System Products Department
701 South Aviation Boulevard
EI Segundo, California 90245
Description
Page
Price
Price
Page
DTl2-1
38
4-bit D/A converters with buffers and reference
Cable receivers/drivers
200
DT12-2
38
4-bit D/A converters
45
25
Cable drivers
100
DTl3-1
38
6-bit D/A converters with buffers and reference
70
AT22
25
Schmitt triggers
100
DTl3-2
38
6-bit D/A converters
AT23
26
High current c lock driver
120
DT24
39
9-bit and siqn D/A converter
AT24
27
Medium current clock driver
110
ETlO-XX
78
14 conductor cable with connectors
AT47
28
8-volt interface cable drivers
165
ETll
78
Front-edge cable connectors
AT48
28
8-volt interface cable receivers
165
ETl2-XX
78
14 conductor cable (per foot)
AT52
29
Long line drivers
100
ET13
79
Cable dummy load
AT53
30
Long line receivers
150
ETl4-XX:Y
78
Cable assembly, sinqle connector
AT69
31
General purpose differential receivers
120
ET32-XXXX
79
Long line cable assembly
BTlO
33
Buffered AND/OR gates
72
BTl 1
33
Buffered AND gates
80
BT12
34
Binary - to - octal decoders
97
BTl3
34
Buffered matrix
BTl8
35
BT27
35
BT31
24
Cable Receivers
ATll
24
ATl2
S 60
55
160
4df:l
7
2
20
30CJ)
[email protected])
FTl0
40
Basic flip-flops
92
FTll
41
4-bit high speed cOL'olIer
76
FTl2
40
Gated flip-flops
100
FT19
42
Multipurpose counters/registers
140
Buffered AND gates
70
FT20
43
8-bit buffered latch registers
100
Buffered OR gates
75
FT26
44
Buffered latch multiplexing matrix
36
Buffered AND gates
48
FT27
45
Buffered latches
BT33
36
Dual-input 12-bit multiplexer
60
FT40
46
Fast access memory (128 bits)
480
CTlO
37
High frequency clock osci Ilator (1 MHz ta 10 MHz)
[email protected]
FT43
47
Standard flip-flops
115
CTl6
37
Medium frequency clock oscillator (7.8 KHz to 2 MHz)
[email protected]
FT56
47
Clocked flip-flops
120
CD Add
$25 for each crystal.
~ $40 for
cr> $30 for
Specify frequency.
basic assembly +$2 per faot of cable.
XX defines cable length in feet.
basic assembly +$2 per foot of cable. XX defines cable length in feet.
Define Y as C or E far connector mount on Component or Etch side of module.
@) $1000 for basic assembly +$1.50 per foot of cable. XXXX defines cable length in feet up to 2000 feet.
86
Description
Model
$150
Model
ATlO
95
80
99
Model
Description
Poge
Description
Price
Model
Page
67
Lamp drivers
Price
FT57
48
DC (RS) flip-flops
$ 55
QTl4
FT58
48
10-bit buffered latch registers
125
QTl6
68
BC D-decoder/dri vers
HT58
49
Universol operational amplifier
170
QT17
68
BCD-decoder/indi cators
120
100
5100
90
HT72
51
Valtage campara tors
79
RT14
69
Re lay drivers
HT73
52
Voltage comparators
120
ST14
69
Manual toggle switches
120
1Tl0
54
Inverted AND/OR gates (AND/NORs)
72
ST41
71
Read only memory
150
ITll
54
Inverted AND gates (NAND gates)
JT13
55
Inverter matrix
JT14
56
JT18
80
ST44
70
Read only memory (diodes in place)
160
100
TTl 1
83
Cordless power wire-wrap gun
130
Inverted AND/OR matrix (AND/NOR matrix)
70
TTl 3
83
Manual wire-unwrapping tool
57
Inverted AND gates (NAN D gates)
70
VTI0
83
Jumper kit (500 wire)
IT27
57
Inverted OR gates (NOR gates)
75
VTl1
83
Individual module connector, wire-wrap
JT31
58
Inverted AND gates (NAND gates)
48
VT12
83
Individual module connector, solder-tai I
KTI0
58
Mercury-wetted re lays
115
WT49
72
35v reference voltage regulator
190
LTI0
59
Lagic elements (ANDs, ORs, NANDs)
80
WT53
73
25v reference voltage regulator
80
LTll
59
Logic elements (AND/ORs, AND/NORs)
80
WT54
73
15v reference voltage regulator
80
LT26
60
Switch comparators
120
XTlO
74
Line terminators
30
15
125
5
5
LT50
61
Teletype send module (8-11 code)
350
YTl4
75
24-inch computer add-on cabinet
LT54
61
Teletype receive module (8-11 code)
350
YTl9
75
19-inch system cabinet
1200
150
YT24
75
24- inch system cabi net
900
75
YT30
75
Side panel
100
750
LT66
62
12-bi t comparator
LT67
63
Fast fu II-adder
MTlO
76
Fixed mount 32-module case, solder-tai I
220
YT31
76
Front door, blank
170
MTl2
76
Fixed mount 32-module case, wire-wrap
150
YT32
76
Front door with control panel
400
MTl3
76
Fixed mount 32-module case, w/o backplane, connectors
30
YT43
76
3-high swing frame
500
MT30
76
Hinge mount 32-module case, solder-tail
240
YT47
76
7-high swing frame
650
MT32
76
Hinge mount 32-module cose, wire-wrap
160
YT49
76
9-high swing frame
700
MT33
76
Hinge mount 32-module cose, w/o backplane, connectors
40
ZT11
83
Blank modu Ie
20
MT42
76
Two-high mounting case
300
ZT15
82
Cable plug module (solder connection)
30
MTD-l
76
Drawer type 90-module case, solder-tai I
700
ZT17
77
19" wide hinged door,
5-1/4 inches high
40
MTD-2
76
Drawer type 90-module case, wire-wrap
700
ZTl8
77
19" wide hinged door,
10-1/2 inches high
50
NTlO
64
8v interface buffers
100
ZT19
77
19" wide hinged door,
15 - 3/4 inches high
NTll
64
8v interface i nverlers
100
ZT20
77
Blower assembly
NT18
65
Negative logic to T Series interface (NORs)
NT19
65
Keyboard interface
60
80
55
ZT23
82
Cable plug module (pressure contacts)
25
100
ZT37
83
Breadboard module
20
NT33
66
T Series to negative logic interface
55
ZT39
84
Indicator lamp
OT14
66
Adjustable one-shats (medium delay)
190
ZT40-1
77
Push-on panel, 1 - 3/4 inches
35
OTl8
67
Adjustable one-shots (short delay)
120
ZT40-2
77
Push-on pane I, 3 - 1/2 inches
35
PTlO
77
Compact power supply
280
ZT40-3
77
Push-on pane I, 5 -1/4 inches
35
PTl2
77
High output power supply
980
ZT40-4
77
Push-on pane I, 7 inches
45
PTl6
77
Large system logic power supply
1350
ZT45
79
Ribbon cable assemblies (vertical)
100
PTl8
77
Large system peripheral and reference power supply
1000
ZT46
79
Ribbon cable assemblies (horizontal)
100
PTl9
77
60 Hz/2,000 Hz inverter
2500
ZT52
82
Logic wire (l, 000 ft.)
60
PT23
78
Logic and analog power supply (50v and ± 15v analog)
830
ZT53
83
Extender module
40
PT24
78
Logic and analog power supply (±25v analog)
830
ZT60
83
Copper-clad blank module
20
PT26
78
Analog power supply
48
ZT65
83
Module extractor
25
1.50
Xerox Data Systems
701 South Aviation Blvd./EI Segundo, California 90245 (213) 772-4511 /Cable SCIDATA/ Telex 674839/TWX 910-325-6908
SYSTEM PRODUCTS DEPT.
* *701 South Aviation Blvd.
EI Segundo, Calif. 90245
(213) 772-4511
SALES OFFICES
Western Region
Building Arts Bldg.
Suite G100
5045 N. 12th St.
Phoenix, Arizona 85014
(602) 264-9324
* 1360 So. Anaheim Blvd.
Anaheim, Calif. 92805
(714) 774-0461
*5250 West Century Blvd.
Los Angeles, Calif. 90045
(213) 772-4511
*Vista Del Lago Office Center
122 Saratoga Avenue
Santa Clara, Calif. 95050
(408) 246-8330
3333 South Bannock
Suite 400
Englewood, Colo. 80110
(303) 761 -2645
Fountain Professional Building
9004 Menaul Blvd., N.E.
Albuquerque, New Mexico 87112
(505) 298-7683
EI Paso Natural Gas Bldg.
Suite 201
315 E. 2nd South Street
Salt Lake City, Utah 84111
(801) 322-0501
Dravo Bldg., Suite 501
225 108th Street N.E.
Bellevue, Washington 98004
(206) 454-3991
Representatives:
*The Thorson Company
2505 East Thomas Road
Phoenix, Arizona 85016
(602) 956-5300
*The Thorson Company
300 East Hampden Avenue
Englewood, Colorado 80110
(303) 789-1841
Representatives:
*The Thorson Company
5921 Lomas Place Blvd., N.E.
Albuquerque, New Mexico 87110
(505) 265-5655
*The Thorson Company
909 N.E. 43rd Street
Seattle, Washington 98105
(206) 632-0710
Midwestern Region
*2720 Des Plaines Avenue
Des Plaines, Illinois 60018
(312) 824-8147
*Clausen Bldg., Suite 310
16000 W. Nine Mile Road
Southfield, Michigan 48075
(313) 353-7360
4410 Woodson Road
Suite 111
St. Louis, Missouri 63134
(314) 423-6200
Seven Parkway Center
Suite 238
Pittsburgh, Pennsylvania 15220
(412) 921-3640
Southern Region
State National Bank Bldg.
Suite 620
200 W. Court Square
Huntsville, Alabama 35801
(205) 539-5131
Orlando Executive Center
1080 Woodcock Road
Orlando, Florida 32803
(305) 841-6371
7000 North Atlantic Avenue
Cape Canaveral, Florida 32920
(305) 784-2181
2964 Peachtree Road, N.W.
Suite 350
Atlanta, Georgia 30305
(404) 261-5323
Jefferson Bank Bldg.
Suite 720
3525 N. Causeway Blvd.
Metairie, Louisiana 70002
(504) 837-1515
4920 S. Lewis Avenue
Suite 103
Tu Isa, Oklahoma 741 OS-(918) 743-7753
* 8383 Stem mons Freeway
Suite 233
Dallas, Texas 75247
(214) 637-4340
2300 West Loop South
Suite 150
Houston, Texas 77027
(713) 623-0510
280 Belfield Road
Rexdale 605, Ontario
(416) 677-8422
INTERNATIONAL OFFICES
& REPRESENTATIVES
European! African Headquarters
Scientific Data Systems
1.L.1. House, Olympic Way
Wembley Park (London)
Middlesex, England
(01) 903-2511, Telex 27992
Eastern Region
10227 Wincopin Circle
Suite 716
Columbia, Maryland 21043
(301) 730-4900
Sweden
*20 Walnut St.
Wellesley Hills, Mass. 02181
(617) 237-2300
*Brearley Office Building
190 Moore Street
Hackensack, New Jersey 07601
(201) 489-0100
*The Fortune Building
280 North Central Avenue
Hartsdale, New York 10530
(914) 948-2929
673 Panorama Trail West
Rochester, New York 14625
(716) 586-1500
*P.O. Box 168
535 Pennsylvania Ave.
Fort Washington Industrial Park
Fort Washington, Pa. 19034
(215) 643-4250
Kogerama Building
Suite 212
No.1 Tidewater Executive Center
Norfolk, Virginia 23502
(703) 497-6811
Washington (D.C.) Operations
Canada
* 864 Lady Ellen Place
Ottawa 3, Ontario
(613) 722-8387
Denmark
A/S Nordisk Elektronik
Danasvej 2
Copenhagen V
EVA 8285/EVA 8238
Norway
1301 Avenue of the Americas
New York City, New York 10019
(212) 765-1230
*2351 Research Blvd.
Rockville, Maryland 20850
(301) 948-8190
Nordisk Elektronik AB
Stureplan 3
Stockholm 7
(08) 248340
Nordisk Elektronik (Norge) A/S
Middelthunsgt. 27
Oslo 3
(2) 602590
France
Compagnie Internationale
pour l'lnformatique, C.1.1.
Executive and
Sales Offices
·66, Route de Versailles
78-Louveciennes
Yvelines
951 86 00 (Paris area)
Manufacturing
and Engineering
Rue Jean Jaures
78-Les Clayes-sous-Bois
Yvelines
Israel
Elbit Computers Ltd.
Subsidiary of Elron
Electronic Industries Ltd.
88 Hagiborim Street
Haifa
6 4613
Oil Exchange Building
1009 7th Avenue, S.W.
Calgary 2, Alberta
(403) 265-8134
·System products applications staff personnel are stationed at these offices .
•• Please address purchase orders to this office.
Printed in U.S.A.
64-51-03 (Rev. 5)
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