Z-100 LifeLine
IDE Interface and NVsRAM Board Design Description
-----------------------------------------------------------------------------------------------------------------------------------Z100 IDE Interface and NVSRAM Board Design
an onboard real time clock and an internal
Description – Large Scale Design 3.0
battery for memory retention. Therefore, no
By Charles Hett, Lenexa Kansas
special programming voltage is required and
programming is greatly simplified with no
special timing routines required. Other
Introduction
models are available; see the schematic for a
listing of devices thought to be compatible.
The Z-100 LifeLine IDE Interface and NVSRAM
Programming the real time clock is
design, hereafter referred to as the Z100 IDE
described in the software section.
Interface is a multifunction S-100 board designed
for the Heath/Zenith Z-100 Series computer. It
• A breakout switch to enable program
provides the following features:
analysis using the Z-100's enhanced Monitor
ROM utilities from the hand prompt or the
• An interface from the Z-100 S-100
DEBUG utility.
computer bus to the industry standard IDE
hard drive interface. This allows you to
• A prototype area for adding your own
connect to up to four standard IDE drives
options. One idea is to add a second
which are now much more available than
NVsRAM chip selected by means of a
the old MFM hard drives originally
toggle switch.
supported
on
the
Z-100.
DMA
capabilities, however, are not supported.
Solid state memory devices, such as
Theory of Operation
compact flash cards, that use the IDE
interface are also usable.
Main Schematic
The circuit design described here utilizes a
complex programmable logic device
(CPLD) from Altera for all of the control
circuitry.
Design Note: This programmable device
was chosen because it would make
development easier and the design
hopefully more reliable and require less
power. Altera was chosen because the
development tools were readily available
from their web site.
•
A bootable NVsRAM device. This
nonvolatile memory storage device, based
on the Texas Instruments bq4850
programmable
NVsRAM,
can
be
programmed at any time without removing
it from the board. The NVsRAM device is
fully bootable and can contain up to 512k
of user selectable programs or files,
making it an excellent choice for holding
the Z-DOS bootup files. The bq4850 has
Input Buffers
U1, 74LS245, provides buffering for the Data lines
(DO0 through DO7) from the S-100 bus to the
Interface board. U1 is enabled by the signal
/IO_Write.
U2, 74LS244, provides buffering for the Data lines
(DI0 through DI7) from the Interface board to the
S-100 bus. U2 is enabled by the signal /IO_Read.
Address Decoding
The board is uniquely decoded at address 0080h
through 008Fh by the Altera chip. S100 bus address
lines A00 through A15 are routed to the Altera chip
and these address lines are then decoded to only
allow addresses 0080h through 008Fh to affect card
operation.
This decoding could be changed but Altera chip
reprogramming would be required.
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Z-100 LifeLine
IDE Interface and NVsRAM Board Design Description
-----------------------------------------------------------------------------------------------------------------------------------31
INTRQ
32
Not Used
Output Buffers
U9 and U12, both 74LS245s, buffer control and
address signals to the IDE drive.
33
(Not
Used)
A1
34
U7 and U8, both 74LS245s, buffer data to/from
IDE J1.
U10 and U11, both 74LS245s, buffer data to/from
IDE J2.
These buffers turned out to be very important to
obtain reliable operation by providing the
capability of turning the individual IDE
connectors on and off under the Altera chip's
control. The long IDE cables caused ringing and
interaction without the buffers. Also note that all
Control and Data lines have series termination
resistors which help reduce ringing and improve
overall bus transient response.
IDE Connector
J1 and J2 are the IDE connectors.
The following signal names are the IDE interface
standard names for these signals and not
necessarily the signal names on our card:
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Name
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Gnd
DMARQ
(Not
Used)
WR/
RD/
IORDY
(Not
Used)
DMACK
(Not
Used)
Pin
2
4
6
8
10
12
14
16
18
20
22
Name
Gnd
D8
D9
D10
D11
D12
D13
D14
D15
keypin
Gnd
24
26
28
Gnd
Gnd
CSEL (Gnd)
30
Gnd
35
37
39
A0
CS0
Drive
LED (Not
Used)
36
38
40
PDIAG
(used
for
detection
between
Master and
Slave drives.
No connect
to
IDE
card.)
A2
CS1
Gnd
A note about CSEL, Cable Select. Cable Select is a
feature that most IDE drives have which allows two
drives to be connected to a connector and not worry
about which drive is connected as master and which
as slave. This pin is grounded on the IDE card. It is
pulled up by each IDE drive that supports CSEL.
The selection is done on the IDE cable instead.
CSEL is left unconnected on the connector farthest
out from the computer. That makes that far end
drive the Slave (Drive 1). The Master (Drive 0) is
at the mid cable connector as it is pulled down to
ground by the card. To use the CSEL feature you
would have to either buy a special cable that
supports it (may be difficult to find) or make your
own by carefully finding and cutting the correct
wire in the ribbon cable (also may be fairly
difficult). This feature is seldom used but it is there
for you to use if you wish.
Low and High Byte Data Latch U3
The S-100 bus data bus is 8 bits wide. The IDE
drive data bus is 16 bits wide. The drive does not
require 16 bit wide data for control so it could be
used without the upper 8 bits of data but that would
be wasteful of drive space. Scott Christiansen
documented a method for converting the bus from 8
to 16 bits and his method was adapted for this
design
with
his
XTIDE
interface
(http://mylinuxisp.com/~jdbaker/oldsite/SmallSys/8
bitIDE.html#XTIDE). Others have used this as
well, including Robert Doerr, a Heathkit Robot
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Z-100 LifeLine
IDE Interface and NVsRAM Board Design Description
-----------------------------------------------------------------------------------------------------------------------------------/RAM_CE
NVsRAM Chip enable
enthusiast in his H2KIDE Robot drive interface
(http://www.theoldrobots.com/hero2k.html), and
/RAM_RE
NVsRAM Output enable (for
Jim Hathaway for the Color Computer
reading)
(CoCoIDE)
(http://mylinuxisp.com/~jdbaker/oldsite/SmallSys
W1 is used to configure for a 32-pin or 36-pin
/8bitIDE.html#CoCo_IDE).
NVsRAM. The card comes with the trace in place
for a 32-pin NVsRAM. For a 36 pin NVsRAM, cut
The control for doing this is done in the Altera
the trace for 32-pin, install a three pin header and
chip, U13, an EPM7064SLC84. When reading
install a jumper on the 36-pin position.
data from the drive, read from the drive at address
008Ch which will give you the low byte, then
U4, a CD4040 Johnson counter, provides the
read the hi byte from the latch, U3, 74LS573, at
address counter. The address counter is reset by
address 008Dh. Note: Addresses are consecutive
writing to the Sector Latch 8Eh. The address
so that word-wide computer instructions can be
counter is incremented by reading address 8Fh. The
used for higher performance. Data is latched by
counter is clocked with the INCR/ signal and
the signal LATCH_LE. The output is enabled by
Cleared with the CLR signal.
the signal /LATCH_OE/, feeding hi byte data to
buffer U2 and the S100 data bus.
Write data to NVsRAM at address 8Fh.
Read data from NVsRAM at address 8Eh.
For Write, write the Lo Byte first to the latch at
address 0088h, then write the Hi Byte at 0089h.
U5, 74LS573, provides the sector latch. It is loaded
This writes both the Lo Byte and Hi Byte to the
by writing the sector value (0 to FFh) to address
drive. Again addresses are consecutive for word8Eh. Each sector is 1024 bytes long. The sector
wide instructions. As before, the data is latched
latch is also latched with the CLR signal at the same
with the LATCH_LE signal and the output is
time the counter is cleared.
enabled by the /LATCH_OE signal. The
destination for the latched lo byte data this time
The sector latch outputs are always enabled.
though is the IDE data bus.
You could also read the low byte or write the low
byte from/to address 80h if you only want 8 bit
transfer. This is not recommended as most IDE
drives do not support it. You would have to find a
really old drive.
NVsRAM (sheet 3 of schematic)
The NVsRAM (U6, BQ4850) is controlled with
the following signals:
/RAM_WE NVsRAM write enable. Note: W2
can be used to provide a hard write DISABLE by
cutting the trace between the two pads. Then to
re-enable write, install a two pin header and
install a jumper. We feel that the software is
reliable enough that accidental NVsRAM write is
unlikely.
The following equates summarize the above:
SECTOR_PORT
NVSRAM sector
equ
08Eh; port to specify
READ_PORT
equ
08Eh; read data port
WRITE_PORT
equ
08Fh; write data port
BUMP_PORT
equ
08Fh; reading from
this port increments the flash NVSRAM board
offset pointer
Note: these equates do not necessarily relate to any
specific software. They are examples only.
U6 is the BQ4850 NVsRAM and was described
earlier.
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Z-100 LifeLine
IDE Interface and NVsRAM Board Design Description
-----------------------------------------------------------------------------------------------------------------------------------CAUTION – the Altera chip can be damaged doing
this under some circumstances. Use care that I/O
Power Regulator (Sheet 3 of schematic)
pin definition is compatible with the programming
change being contemplated. A separate article
U20, LM7805, provides the 5v regulated power
describing programming in more detail will be
for the board. The S-100 bus provides
available.
approximately 8 volts to the board, from pins 1
and 51, which must be regulated. This is the only
operating voltage provided by the board.
Breakout Switch
Altera Controller
The Altera Controller, U13, EPM7064SLC84, is
the heart of the system. It performs the following
functions:
1. As previously mentioned, decodes the
address lines into the appropriate
address located at 008xH. Sixteen
address lines are decoded.
2. Controls the NVsRAM for reading and
writing.
3. Controls the Byte read/write latch.
4. Controls the IDE Drives
5. Controls all board buffers
6. Debounces the breakout switch and
generates the NMI signal for breakout.
7. Ensures that at least two wait states are
generated with IDE control for ports
81h – 87h and 8ah. Normally, one or
two wait states are selected by a
jumper on the Z100 motherboard. The
wait states generated here override any
jumper there unless more than two are
selected.
8. Selects the desired IDE connector J1,
J2. Controlled by B0 and B1 at
address 008Ch. B0=0 and B1=1 for
J1, B0=1 and B1=0 for J2.
9. Drives the two NVsRAM and four
IDE drive activity LEDs.
A breakout switch is located in the extreme upper
right corner of the IDE Controller Board to generate
an NMI interrupt signal for breakout. The switch
can be pressed at any time to exit to the monitorROM hand prompt. To return to the application in
progress, at the hand prompt, press {Go and
{RETURN} {RETURN}. The right-most pins on
the LED connector can also be connected to
another, optional breakout switch that you may
locate anywhere in the Z-100 case.
LEDs
The IDE Controller Board comes standard with an
LED assembly mounted on the LED connector to
provide indications for NVsRAM and IDE drive
activity. This assembly can be removed and
replaced by your own assembly to mount a bank of
LED’s somewhere on the front panel. These are
very handy for software debugging and discerning
proper IDE card activity.
The Altera chip can be programmed while
installed on the IDE card via the W3 IDE
programming connector. This can be connected to
an Altera Byte Blaster compatible programmer.
Charles made one using commonly available parts
per Altera website instructions.
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Z-100 LifeLine
IDE Interface and NVsRAM Board Design Description
-----------------------------------------------------------------------------------------------------------------------------------Altera Chip to IDE Schematic Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Altera Pin
Name/Usage
RESET/_75
pSYNC_76
VCCINT
pWR/_77
pDBIN_78
A[5]
GND
A[0]
A[4]
A[3]
A[1]
A[2]
VCCIO
TDI
A[15]
A[12]
A[6]
A[7]
GND
A[8]
A[9]
A[13]
TMS
A[10]
A[14]
VCCIO
A[11]
sINP_46
sOUT_45
I/O_Write_OE/
I/O_Read_OE/
GND
CLR
LATCH_OE/
J2_38_DS1/
INCR4040_CLK
J2_37_DS0/
VCCIO
J2_35_A0
J2_36_A2
J2_33_A1
GND
Schematic Name
RESET/_75
pSYNC_76
VCCINT
pWR/_77
pDBIN_78
A[5]_29
GND
A[0] _79
A[4]_30
A[3] _31
A[1]_80
A[2]_81
VCCIO
#TDI
A[15] _32
A[12]_33
A[6]_82
A[7]_83
GND
A[8]_84
A[9]_34
A[13_85
#TMS
A[10]_37
A[14]_86
VCCIO
A[11]_87
sINP_46
sOUT_45
I/O_Write_OE/
I/O_Read_OE/
GND
CLR_RST_LE
/LATCH_OE
J2_38_DS1/
INCR4040CLK
J2_37_DS0/
VCCIO
J2_35_A0
J2_36_A2
J2_33_A1
GND
Dir.
input
input
power
input
input
input
gnd
input
input
input
input
input
power
input
input
input
input
input
gnd
input
input
input
input
input
input
power
input
input
input
output
output
gnd
output
output
output
output
output
power
output
output
output
gnd
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Altera Pin
Name/Usage
VCCINT
J2_25_IOR/
J1_38_DS1/
J2_23_IOW/
GND
J1_37_DS0/
J1_35_A0
J1_36_A2
J1_25_IOR/
J1_33_A1
VCCIO
D[2]
J1_23_IOW/
D[1]
[D4]
D[0]
GND
DIR
J1_OE/
TCK
NVsRAM_CE/
NVsRAM_OE/
NVsRAM_WE/
VCCIO
J2_OE/
IDE_RESET_1/
LATCH_LE
LED_J2_SLAVE
TDO
GND
LED_J2_MASTER
LED_J1_MASTER
NVsRAM_RD_LED
LED_J1_SLAVE
BREAKOUT
VCCIO
NMI_12
NVsRAM_WR_LED
RDY_72
GND
PHI_24
pSTVAL/_25
Schematic Name
VCCINT
J2_25_IOR/
J1_38_DS1/
J2_23_IOW/
GND
J1_37_DS0/
J1_35_A0/
J1_36_A2
J1_25_IOR/
J1_33_A1
VCCIO
D[2]/DD10
J1_23_IOW/
D[1]/DD9
[D4]/DD12
D[0]/ DD8
GND
DIR
J1_OE/
#TCK
NVsRAM_CE/
NVsRAM_OE/
NVsRAM_WE/
VCCIO
J2_OE/
IDE_RESET_1/
LATCH_LE
LED_J2_SLAVE
#TDO
GND
LED_J2_MASTER
LED_J1_MASTER
NVsRAM_RD_LED
LED_J1_SLAVE
BREAKOUT
VCCIO
NMI_12
NVsRAM_WR_LED
RDY_72
GND
PHI_24
pSTVAL/_25
Dir.
power
output
output
output
gnd
output
output
output
output
output
power
input
output
input
input
input
gnd
output
output
input
output
output
output
power
output
output
output
output
output
gnd
output
output
output
output
input
power
output
output
bidir
gnd
input
input
Note:
• A “/” character in the signal name indicates the signal is active when low.
• A “#” character in the signal name indicates the signal is used for programming
the Altera chip and has no function in the IDE interface.
It is suggested that you obtain a copy of the FPGA socket diagram which will show the
pinout translation from the IDE Controller chip to the PC board. It is rather tricky.
One source for this drawing would be at Mill-Max:
http://www.mill-max.com/images/products/application_notes/940FP.pdf
Go to the 84 pin socket. It will be very helpful if you need to troubleshoot the card.
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