Product Manual ELS - MB1500A (Xilinx FPGA XC6SLX150-FG484 EVM 보드)

Product Manual ELS - MB1500A  (Xilinx FPGA XC6SLX150-FG484 EVM  보드)
Product Manual
ELS - MB1500A
(Xilinx FPGA XC6SLX150-FG484 EVM 보드)
Embedded and Logic Solution
eLogics
RM607-1,
이로직스
Digital
Empire,
#685,Gasan-dong,
Geumcheon-gu Seoul, Korea. (Zip: 150-023)
Phone: (02) 2624-2573
서울 특별시 금천구 가산동 568번지
디지털엠파이어
607-1호 (우: 152-050)
전화: (02) 2624-2573
Fax: (02)2624-2575
팩스: (02)2624-2575
[email protected]
[email protected]
www.eLogics.co.kr
© 2011 eLogics All rights reserved
www.eLogics.co.kr
ELS-MB1500A Manual V. 1.0 [2014-03-08]
ELS-1500A Manual Version
Version
Description
Date
Who
0.9
Initial Create
2013-03-08
Elogics
0.99
버그 수정
2013-08-08
Elogics
1.0
CHIP 교체
2014-03-08
Embedded and Logic Solution: eLogics
2
Elogics
ELS-MB1500A Manual V. 1.0 [2014-03-08]
목차
1.
제품 설명 ........................................................................................................................................................... 5
2.
제품 사양 ........................................................................................................................................................... 5
2.1.
하드웨어 사양 .......................................................................................................................................... 5
2.2.
소프트웨어 사양 ..................................................................................................................................... 5
2.3.
전기적 사양............................................................................................................................................... 5
3.
제품 구성 ........................................................................................................................................................... 6
4.
보드 사진 및 구성도 .................................................................................................................................... 7
4.1.
보드 사진 ................................................................................................................................................... 7
4.2.
보드 BLOCK DIAGRAM ........................................................................................................................ 7
5.
기능 설명 ........................................................................................................................................................... 8
6.
The overview of MicroBlaze is as follows: ............................................................................................ 8
6.1.
소프트 프로세서 (마이크로브레이즈) ...................................................................................... 8
6.2.
Bus 구조 ..................................................................................................................................................... 8
6.3.
HDMI 출력 설명 ..................................................................................................................................... 8
6.4.
응용 및 실습 분야 ................................................................................................................................. 9
6.5. ............................................................................................................................................................................. 9
7.
ELS-MB1500A 회로도 ................................................................................................................................ 9
7.1.
USB 회로도 : USB1.1 FT232RL CHIP 을 사용했다. .................................................................. 9
7.2.
FPGA DDR2 회로도 16Bit 128Mbyte DDR2 메모리............................................................. 10
7.3.
1Gbps 이더넷 회로도........................................................................................................................ 10
10/100 이더넷 회로도 .................................................................................................................................. 11
7.4.
업보드 확장 콘넥터 회로도............................................................................................................ 11
7.5.
업보드 확장 콘넥터 회로도............................................................................................................ 12
Embedded and Logic Solution: eLogics
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
7.6.
DVI OUT 회로도................................................................................................................................... 12
7.7.
System Clock generation 회로도 ................................................................................................. 13
 3.3V 50Mhz OSC ...................................................................................................................................... 13
 2.5V 200MhZ LVDS OSC 기본 장착(clock+, clock-) ................................................................ 13
7.8.
Reset 회로 .............................................................................................................................................. 13
7.9.
전원 회로 ................................................................................................................................................ 13
7.10.
8.
콘넥터 설명 ................................................................................................................................................... 14
8.1.
USB1 – Console 포트로 사용됨.................................................................................................... 14
8.2.
CN6 RJ 45 JACK 1Gbps 이더넷 콘넥터 .................................................................................... 14
8.3.
J9
8.4.
J1,CN7 DC Jack 5V (DC 입력) ........................................................................................................ 15
8.5.
J10. Xilinx Jtag....................................................................................................................................... 15
8.6.
J8 UP Board 콘넥터( 3.3V I/O) ...................................................................................................... 16
8.7.
J7 (1.8V , 3.3V I/O 선택) UP Board 콘넥터 – B2: 1.8V , B9: 3.3V(디폴트).............. 17
8.8.
BEAD : BANK0 전원 선택 스위치(2 개중 1 개만 선택한다.) 디폴트 3.3V ................ 18
8.9.
P1. MINI HDMI 콘넥터( TMDS 3.3V I/O) ............................................................................... 18
8.10.
9.
Configuration Prom 회로 ............................................................................................................ 13
RJ 45 JACK 10/100 bps 이더넷 콘넥터 ............................................................................ 14
Xilinx Tool 을 이용한 FPGA 내용 변경 하기...................................................................... 19
Example Project ........................................................................................................................................... 25
9.1.
4 개의 LED 와 DIP Switch 사용 예제 ......................................................................................... 25
9.2. .......................................................................................................................................................................... 26
Embedded and Logic Solution: eLogics
4
ELS-MB1500A Manual V. 1.0 [2014-03-08]
1. 제품 설명
ELS-1500A은 Xilinx사의 스파르탄 시리즈 중 XC6S25,45,75,150-FG484패키지로 제작된 FPGA
EVM보드 입니다. 보드 내에 On chip PHY 10/100/1000bps, Local Bus 10/100Mbps 이더넷,
128Mbyte DDR2(16Bit)메모리 , LVDS 200Mhz OSC, MINI HDMI TX, USB2SERIAL등이 내장되어
있다. 또한 사용자가 포트를 확장 할 수 있도록 80핀 IO포트가 2개 있습니다. 구동 전원은
5V 2A 전원으로 동작하며, 보드 동작을 표시하기 위한 LED등이 있습니다. 기존에 스파르탄 3
용으로 제작된 MB1500 업그레이드 버전이기 때문에 I/O 포트를 호환 되도록 설계 하였으며,
최대 XC6S150-FG456 칩으로 구매 시 최대 1500만 게이트 용량까지 사용할 수 있는 장점이
있습니다.
2. 제품 사양
2.1.
하드웨어 사양
 FPGA : Xilinx XC6SLX25,45,75,150-FG484(250~1500)만게이트 사용할 수 있음
 DDR2-16Bit 128Mbyte
 M88E1111-Gbps 이더넷
 LAN9220 10/100Mbps 이더넷
 Single USB2Serial Port
 FPGA Configuration EEPROM(SPI PROM)
 DC Power 5V 입력
 4 bit dip switch
 4 bit LED, 전원 표시 LED
 업보드 확장 콘넥터(2x40x2x2.0MM)
 보드 사이즈: 115mm x 90mm
 2.5V LVDS 200Mhz, 50Mhz OSC
 전원 스위치
2.2.
소프트웨어 사양

ISE 12.4 , EDK (예제 코드), ISE 11.5 이상 지원됨

제공 소스: 마이크로 브레이즈 예제 기본, SP601를 수정한 소스

DVI OUT 소스

마이크로 브레이즈 LWIP 테스트 소스 코드

Serial Uart Source 코드

2.3.
전기적 사양

5V 2A DC 아답터(메인전원)

1.2V FPGA CORE 전원

1.8V DDR2 메모리 전원

2.5V 이덧넷 I/O 전원

3.3V 주변 I/O 전원
Embedded and Logic Solution: eLogics
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
3. 제품 구성
구분
수량
비고
ELS-MB1500A, USB Cable
1
판매
제품 설명서
1
이로직스
회로도 PDF, ORCAD 원본(이메일 발송)
1
Webhard
1
Webhard
제공 소스
-
영상처리 필터 소스(SB601)
-
마이크로브레이즈 예제코드
Embedded and Logic Solution: eLogics
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
보드 사진 및 구성도
4.1.
보드 사진
4.2.
보드 BLOCK DIAGRAM
PWR SW
1.2V
JTAG
2.5V
DCJACK
1.8V
array res
2
USB
1
1
0
88E1111
RJ-45
DDR 2SDRAM
3
LAN
9220
RJ-45
XC6S-25/45/100/150
FG456
CY22393
4.
CFG FLASH
XCS08F
105mm
Embedded and Logic Solution: eLogics
7
90mm
ELS-MB1500A Manual V. 1.0 [2014-03-08]
5. 기능 설명
본 제품은 Xilinx 사에서 제공되는 ISE Tool를 이용한 VHDL,Velog H/W 개발
언어를 이용한 여러가지 IP(UART, HDMI, DSP BLOCK, MAC)를 실습 할 수 있
으며,
또한 EDK Tool을 사용하여 FPGA내부에 마이크로 브레이즈 마이컴을
내장하는 방법과 예제 프로그램을 테스트 할 수 있는 EVM 보드 입니다. 단
지 교육용만 아니라 여러 가지 용도로 응용 할 수 있도록 확장 I/O 포트가
내장되어 있습니다. .
6.
The overview of MicroBlaze is as follows:
6.1. 소프트 프로세서 (마이크로브레이즈)
・32-bit, RISC Processor
・32-bit, fixed length instruction
・32 generic 32bit registers
・3-Stage Pipeline
・Instruction cache and data cache
・Hardware multiplier
・Hardware debug logic supported
6.2. Bus 구조
The bus consists of the following three bus types.
FPGA Internal LMB
A dedicated bus used to connect the Micro Blaze and BRAM (FPGA internal memory).
FPGA Internal OPB
A bus used to connect multiple peripheral IP cores.
When customizing, peripheral cores are added to this bus.
FPGA External Bus
A bus used to connect external memory devices through OPB EMC and
OPB DDR2 SDRAM. ,AXI BUS지원
6.3. HDMI 출력 설명
HDMI(DVI) 출력은 MB1500A에서 영상 처리된 데이터를 DVI 포트로 모니터에 표시하기
위해서 사용되며, MB1500A보드 내에 FRAME BUFFER가 있으며, 메모리에 저장된 내용을
1280x1024x70Hz로 모니터에 디스플레이 됩니다.

지원 해상도 1280x1024x70Hz DVI 모니터

DUAL 12BIT RGB 출력

R/A 콘넥터 전기적 사양

12BIT DUAL RGB DATA( 3.3V)

HSYNC, DISPLAY EN, PCLK (3.3V)

DDC 데이터는 지원 하지 않음
Embedded and Logic Solution: eLogics
8
ELS-MB1500A Manual V. 1.0 [2014-03-08]
6.4.
응용 및 실습 분야

네트워크 JPG DID 광고용 모니터

영상처리 실습 등

이더넷 MAC 코딩 실습

UART 코딩 실습

기타 등등…
6.5.
7. ELS-MB1500A 회로도
USB 회로도 : USB1.1 FT232RL CHIP을 사용했다.
D10
19
26
20
VCC
VCCIO
3V3OUT
U13
RTS
CTS
DTR
DSR
DCD
RI
USBDM
USBDP
CBUS4
CBUS2
CBUS3
CBUS1
CBUS0
RESET
TEST
TXD
RXD
1
5
FT_TXD
FT_RXD
ST_RXD
ST_TXD
3
11
2
9
10
6
12
13
14
22
23
GND
GND
GND
15
4
17
16
USB_D+
NC
NC
AGND
D9
USB_D-
PGB0010603MR
C395
PGB0010603MR
USB1
10uF/10V
VB
DD+
ID
G1
24
8
1
2
3
4
5
OSCO
OSCI
25
7
USB_5V
G2
G3
6
C4
28
27
USB_5V
FT232RL
18
7
21
10uF/10V
VCC2V5
UX60-MB-5ST, miniUSB Type AB
7.1.
Embedded and Logic Solution: eLogics
9
ST_RXD
ST_TXD
2
2
ELS-MB1500A Manual V. 1.0 [2014-03-08]
7.2.
FPGA DDR2회로도 16Bit 128Mbyte DDR2 메모리
LENGTH SAME
DDR2_VREF
네트 길이 조정
VCC1.8V
org
R389
VCC1.8V
R322
R323
1
1
2
2
TERM_P
47
47 x TERM_N
R413
R414
1
1
2
2
1K
1K
CLK_DDRA
CLK_DDRA#
1
J2
DDR_A13
DDR_WE
DDR_RAS
DDR_BA2
RA17A1
RA17B3
RA17C5
RA17D7
0.1uF
C344
0.1uF
C345
0.1uF
C346
0.1uF
C347
2
4
6
8
47R
47R
47R
47R
2
4
6
8
47R
47R
47R
47R
0.1uF
DDRVREF
C348
0.1uF
R3
R7
RFU2
RFU3
C350
C349
0.1uF
0.1uF
C351
DDR_OPT
0.1uF
C352
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
0.1uF
VCC1.8V
C355
C356
X7R
X7R
C357
C358
X7R
X7R
C359
X7R
C360
C361
X7R
X7R
22uF/16V
VSS1
VSS2
VSS3
VSS4
VSS5
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSDL
1
K9
ODT
C362
X7R
+
VREF
R388
20K
K4T1G164QQ-HC(L)E6-667
1
+
RA16A1
RA16B3
RA16C5
RA16D7
47R
47R
47R
47R
CT49
BA0
BA1
BA2
DDR_A12
DDR_BA1
DDR_BA0
DDR_CAS
C343
2
4
6
8
1
L2
L3
L1
LDM
UDM
RA15A1
RA15B3
RA15C5
RA15D7
DDRVREF
2
4
6
8
47R
47R
47R
47R
2
0.001uF
DDR_BA0
DDR_BA1
DDR_BA2
DDR_VREFM
2
CT51 22uF/16V
XC6S25-FG484
SPARTAN-6 FG484
F3
B3
DDR_A8
DDR_A9
DDR_A7
DDR_A11
2
4
6
8
47R
47R
47R
47R
1
R387
20K
DDR_DQM0
DDR_DQM1
CK
CK#
CKE
CS#
RAS#
CAS#
WE#
RA14A1
RA14B3
RA14C5
RA14D7
2
0.1uF
VCC1.8V
2
2
4
4
J8
K8
K2
L8
K7
L7
K3
DDR_DQS0_M
DDR_DQS0_P
DDR_DQS1_M
DDR_DQS1_P
RA13A1
RA13B3
RA13C5
RA13D7
DDR_A1
DDR_A2
DDR_A0
DDR_A10
1
I2C3_SCL
I2C3_SDA
XEINT3
XEINT4
CLK_DDRA
CLK_DDRA#
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
A8
B7
E8
F7
DDR_A4
DDR_A3
DDR_A6
DDR_A5
2
0.1uF
P17
N16
P18
R19
T19
T20
4
4
UDQS#
UDQS
LDQS#
LDQS
DDR_DB0
DDR_DB1
DDR_DB2
DDR_DB3
DDR_DB4
DDR_DB5
DDR_DB6
DDR_DB7
DDR_DB8
DDR_DB9
DDR_DB10
DDR_DB11
DDR_DB12
DDR_DB13
DDR_DB14
DDR_DB15
1
XEINT1
XEINT2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13/RFU4
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
2
0.1uF
TERM_P
TERM_N
USER_SW1
USER_SW0
1
IO_L38N_A4_M1CLKN_1
IO_L72P_1
IO_L39P_M1A3_1
IO_L72N_1
IO_L39N_M1ODT_1
IO_L73P_1
IO_L40P_GCLK11_M1A5_1
IO_L73N_1
IO_L40N_GCLK10_M1A6_1
IO_L74P_AWAKE_1
IO_L41P_GCLK9_M1RASN_1 IO_L74N_DOUT_BUSY _1
IO_L41N_GCLK8_M1CASN_1
IO_L42P_GCLK7_M1UDM_1
IO_L42N_GCLK6_M1LDM_1
M16
L15
P19
P20
W20
W22
L17
K18
U19
V20
M17
M18
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
1
J19
G20
G22
K20
K19
H21
H22
M20
L19
IO_L58P_1
IO_L58N_1
IO_L59P_1
IO_L59N_1
IO_L60P_1
IO_L60N_1
IO_L61P_1
IO_L61N_1
IO_L70P_1
IO_L70N_1
IO_L71P_1
IO_L71N_1
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
NC1
NC2
VDDL
VDD1
VDD2
VDD3
VDD4
VDDL
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
2
0.1uF
CLK_DDRA#
DDR_A3
DDR_OPT
DDR_A5
DDR_A6
DDR_RAS
DDR_CAS
DDR_DQM1
DDR_DQM0
IO_L32N_A16_M1A9_1
IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1
IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1
IO_L35P_A11_M1A7_1
IO_L35N_A10_M1A2_1
IO_L36P_A9_M1BA0_1
IO_L36N_A8_M1BA1_1
IO_L37P_A7_M1A0_1
IO_L37N_A6_M1A1_1
IO_L38P_A5_M1CLK_1
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
1
C22
G19
F20
H19
H18
E20
E22
J17
K17
F21
F22
H20
DDR_DB4
DDR_DB5
DDR_DB6
DDR_DB7
DDR_DQS0_P
DDR_DQS0_M
DDR_DB2
DDR_DB3
DDR_DB0
DDR_DB1
DDR_DB8
DDR_DB9
DDR_DB10
DDR_DB11
DDR_DQS1_P
DDR_DQS1_M
DDR_DB12
DDR_DB13
DDR_DB14
DDR_DB15
USER_SW2
J20
J22
K21
K22
L20
L22
M21
M22
N20
N22
P21
P22
R20
R22
T21
T22
U20
U22
V21
V22
M19
N19
2
0.1uF
DDR_A9
DDR_A10
DDR_A4
DDR_WE
DDR_BA2
DDR_A7
DDR_A2
DDR_BA0
DDR_BA1
DDR_A0
DDR_A1
CLK_DDRA
18V_IO19P
18V_IO19N
18V_IO20P
18V_IO20N
IO_L43P_GCLK5_M1DQ4_4
IO_L43N_GCLK4_M1DQ5_1
IO_L44P_A3_M1DQ6_1
IO_L9P_1
IO_L44N_A2_M1DQ7_1
IO_L9N_1
IO_L45P_A1_M1DQS_1
IO_L10P_1
IO_L45N_A0_M1DQSN_1
IO_L10N_1
IO_L46P_FCB_B_M1_DQ2_1
IO_L19P_1
IO_L46N_FOE_B_M1_DQ3_1
IO_L19N_1
IO_L47P_FWE_B_M1DQ1_1
IO_L20P_1
IO_L47N_LDC_M1DQ1_1
IO_L20N_1
IO_L48P_HDC_M1DQ8_1
IO_L21P_1
IO_L48N_M1DQ9_1
IO_L21N_1
IO_L49P_M1DQ10_1
IO_L28P_1
IO_L49N_M1DQ11_1
IO_L28N_VREF_1
IO_L50P_M1UDQS1_1
IO_L29P_A23_M1A13_1
IO_L50N_M1UDQSN1_1
IO_L29N_A22_M1A14_1
IO_L51P_M1DQ12_1
IO_L30P_A21_M1RESET_1
IO_L51N_M1DQ13_1
IO_L30N_A20_M1A11_1
IO_L52P_M1DQ14_1
IO_L31P_A19_M1CKE_1
IO_L52N_M1DQ15_1
IO_L31N_A18_M1A12_1
IO_L53P_1
IO_L32P_A17_M1A8_1
IO_L53N__VREF_1
1
DDR_A13
FPGA_SCL
FPGA_SDA
DDR_A11
DDR_CKE
DDR_A12
DDR_A8
G16
G17
F16
F17
B21
B22
A20
A21
K16
J16
H16
H17
D19
D20
F18
F19
D21
D22
C20
U10 A2E2
IO_L1P_A25_1
IO_L1N_A24_VREF_1
2
0.1uF
C19
B20
2
USER_SW3
2
0.1uF
U6C
R324 1
R325 1
R390 1
2
100
2
2
2
DDR_CS
DDR_CKE
DDR_OPT
47
47
47
FPGA_SCL
FPGA_SDA
3.3V
VCC1.8V
C78
CT52 +
0.01uF
4
AVIN
PVIN
VSENSE
VREF
C367
X7R
VDDQ
VTT
5
7
B7
VTT_DDRV
3
[email protected] BEAD
8
1
9
LP2996/7MR xCT53
+
4.7uF
SW/SMD-4/SM_1
CT12
+
+
1Gbps 이더넷 회로도
VCC2V5
4.7K
4.7K
4.7K
4.7K
4.7K
R74
R75
R76
R77
R78
18
19
20
24
25
26
28
29
67
69
68
72
70
50
VCC2V5
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VCC1.1V
C98
C99
C100
C101
22uF/16V
C94
C95
C96
C97
CT21
+
0.1uF
0.1uF
0.1uF
0.1uF
VCC2V5
0.1uF
0.1uF
0.1uF
0.1uF
CT22
+
22uF/16V
C110
C111
C112
C113
에러 수정
71
34
122
30
11
5
94
93
84
83
66
65
63
60
58
55
51
48
45
43
40
38
22
21
15
9
1
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TDI
TMS
TRST_B
TDO
TCK
XTAL1
XTAL2
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DPLX
LED_RX
LED_TX
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
NC_50
VDDOX_71
VDDOX_34
VDD_122
VDDO_30
VDD_11
VDD_5
VSS94
VSS93
VSS84
VSS83
VSS66
VSS65
VSS63
VSS60
VSS58
VSS55
VSS51
VSS48
VSS45
VSS43
VSS40
VSS38
VSS22
VSS21
VSS15
VSS9
VSS1
25MHz
Y1
77
AVDD_104
AVCC_64
AVDD_59
AVDD_52
AVDD_49
AVDD_44
VDDOH_89
VDDOH_97
VDDOH_73
DVDD_118
DVDD_117
DVDD_96
DVDD_90
DVDD_85
DVDD_78
DVDD_27
DVDD_23
DVDD_17
DVDD_12
DVDD_6
DVDD_2
76
75
22pF
C93
22pF
100
99
98
PHY _LED_LINK10
PHY _LED_LINK100
PHY _LED_LINK1000
PHY _LED_DUPLEX
PHY _LED_RX
PHY _LED_TX
95
92
91
PHY _CFG0
88
87
86
82
81
80
79
0.01uF
0.01uF
1
SMD_LED(1608)
2
1
SMD_LED(1608)
LED12
2
1
SMD_LED(1608)
LED13
2
1
SMD_LED(1608)
LED14
2
1
SMD_LED(1608)
LED15
2
1
SMD_LED(1608)
1K
R67
1K
R68
1K
R69
1K
R70
1K
R72
1K
R73
PHY _LED_RX
89
97
73
VCC2V5
PHY _AVDD0
VCC2V5
PHY _CFG0
118
117
96
90
85
78
27
23
17
12
6
2
127
119
116
111
108
106
103
102
101
74
VCC1.1V
에러 수정
B1
PHY _AVDD0
BEAD
C380
+
22uF/16V
SMD-CT(3225)
M88E1111 X
Embedded and Logic Solution: eLogics
10
47
47
47
R65
R66
9
10
TD0_P
TD0_N
TD1_P
TD1_N
TD3_P
TD3_N
VCC
TCGND
SHIELD
HFJ11-1G01E/
2
0.01uF
RJ-45
TD2_P
TD2_N
C92
BOTTOM PLACE
2
LED11
VCC2V5
104
64
59
52
49
44
R64
47
R63
C91
VCC2V5
LED10
VCC2V5
VSS_127
VSS_119
VSS_116
VSS_111
VSS_108
VSS_106
VSS_103
VSS_102
VSS_101
VSS_74
2
C90
1
C88
4
2
47
47
C89
107
105
R62
R61
47
113
112
1
SOUT_P
SOUT_N
SEL_OSC
TOP ROUTING
110
109
2
SIN_P
SIN_N
53
54
1
PHY _TXD0
PHY _TXD1
PHY _TXD2
PHY _TXD3
PHY _TXD4
PHY _TXD5
PHY _TXD6
PHY _TXD7
GTXCLK
TXCLK
TXER
TXEN
SCLK_P
SCLK_N
47
2
2
2
2
2
2
2
2
14
10
13
16
HSDAC_P
HSDAC_N
R60
PHY _GTXCLK
PHY _TXCLK
PHY _TXER
PHY _TXEN
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
7
8
R59
2
2
2
2
RXCLK
RXER
RXDV
61
62
2
PHY _RXD0
PHY _RXD1
PHY _RXD2
PHY _RXD3
PHY _RXD4
PHY _RXD5
PHY _RXD6
PHY _RXD7
4
5
1
3
128
126
125
124
123
121
120
2
2
2
2
2
2
2
2
MDI3_P
MDI3_N
56
57
4.7K
7
8
4
2
PHY _RXCLK
2
PHY _RXER
2 PHY _RXCTL_RXDV
MDI2_P
MDI2_N
3
6
R71
4.99K
R58
MDI1_P
MDI1_N
1
2
46
47
NA
PHY _CRS
PHY _COL
CLK125
INIT_B
COMA
RESET_B
RSET
CRS
COL
CN6
MDIO_P
MDIO_N
R79
PHY _RESET_B
2
2
4.7K
R57
PHY _INT
MDIO
MDC
0.1uF
0.1uF
0.1uF
0.1uF
2
31
32
37
36
39
115
114
41
42
C376
C377
C378
C379
2
33
35
PHY _MDIO
PHY _MDC
PHY _AVDD0
U27
3
2
2
* Routing Length Same
* LVDS SIGNAL( Pair
SIGNAL) -> P/N
4.7K
R56
1
4.7K
R55
C106
C107
C108
C109
7.3.
CT10
22uF/16V
1
C81
USER_SW3
USER_SW2
USER_SW1
USER_SW0
8
7
6
5
SD
22uF/16V
6
SW3
1
2
3
4
R386
20K
VCC1.8V
U12
2
GND0
GND1
VCC1.8V
22uF/16V
2
2 1
org
10K
1
CT50 22uF/16V
+
8
7
6
5
22uF/16V
B6
RP11
2
3
4
R385
20K
BEAD
DDR2_VREF
2
0.001uF
VCC1.8V
0.01uF
B3
BEAD
13
ELS-MB1500A Manual V. 1.0 [2014-03-08]
10/100 이더넷 회로도
3.3V
VCC2V5
ETN_3.3V
BOE
15
BWE
16
ETH_CS 17
1K
R343
4.7K
52
R344
22
13
R404
10K INT_ETH
43
R345
4.7K
14
C363
0.1uF
0.1uF
C364
45
ETXD+
44
ETXD-
48
ERXD+
47
ERXD-
+
C370
0.1uF
C371
0.1uF
53
C369
37
2
22uF/16V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
LAN9220 / LAN9221
TPO+
TPOTPI+
TPIEXRES
GPIO0/nLED1
GPIO1/nLED2
GPIO2/nLED3
nRD
nWR
nCS
PME
AMDIX_EN
FIFO_SEL
XTAL1/CLKIN
IRQ
TEST
57
7.4.
46
VDD33A 49
VDD33A 51
VDD33A
1
VDD18A
VSS(PAD)
R326
VDD_18CORE
VDD18CORE
VDD18CORE
XTAL2
50
3
4
5
41
R329
R393
R394
R405
7
ETXD-
7
ERXD+
7
ERXD-
7
LED_A
LED_B
VCC2V5
1K
1K
R392
55
54
ETXD+
12.4K
1K
3
BA11
VCC2V5
36
35
34
33
32
31
29
28
27
26
25
23
22
21
20
19
3.3V
BEAD
25MHz
Y6
VCC2V5
C411
4
2
22pF
nRESET
EECLK
42
40
SY S_RST
C412
22pF
R397
R417
10K
1K
VCC2V5
VCC2V5
업보드 확장 콘넥터 회로도
U6D
2
DSS_PCLK+
2
2
2
2
2
2
2
2
DSS_D2
DSS_D3
DSS_D0
DSS_D1
DSS_D9
DSS_D10
DSS_VSY NC
DSS_HSY NC
LVDS_P5
LVDS_N5
LVDS_P6
LVDS_N6
T18
T17
Y 19
AB19
W18
Y 18
T16
T15
U17
U16
V19
V18
R16
R15
V17
W17
LVDS_N13 V15
LVDS_P14 AA18
LVDS_N14 AB18
LVDS_P15 Y 17
LVDS_N15 AB17
LVDS_P16 AA14
LVDS_N16 AB14
LVDS_P17 Y 16
LVDS_N17 W15
LVDS_P18 V13
LVDS_N18 W13
LVDS_P19 AA16
LVDS_N19 AB16
2
2
2
DSS_ACBIAS
DSS_D6
DSS_D11
LVDS_P20 W14
LVDS_N20 Y 14
LVDS_P21 Y 15
LVDS_N21 AB15
T12
U12
T14
R13
EXT_CLK1
W12
FPGA_CLK1
Y 12
IO_L30P_GCLK1_2
IO_L30N_GCLK0_2
IO_L31P_GCLK31_2
IO_L31N_GCLK30_2
IO_L2P_CMPCLK_2
IO_L2N_CMPMOSI_2
IO_L4P_2
IO_L4N_VREF_2
IO_L5P_2
IO_L5N_2
IO_L6P_2
IO_L6N_2
IO_L7P_2
IO_L7N_2
IO_L8P_2
IO_L8N_2
IO_L9P_2
IO_L9N_2
IO_L10P_2
IO_L10N_2
IO_L11P_2
IO_L11N_2
IO_L13N_D10_2
IO_L14P_D11_2
IO_L14N_D12_2
IO_L15P_2
IO_L15N_2
IO_L16P_2
IO_L16N_VREF_2
IO_L32P_GCLK29_2
IO_L32N_GCLK28_2
IO_L40P_2
IO_L40N_2
IO_L41P_2
IO_L41N_2
IO_L42P_2
IO_L42N_2
IO_L43P_2
IO_43N_2
IO_L44P_2
IO_L44N_2
IO_L45P_2
IO_L45N_2
IO_L46P_2
IO_L46N_2
IO_L47P_2
IO_L47N_2
IO_L48P_D7_2
IO_L48N_RDWR_B_VREF2
IO_L49P_D3_2
IO_L49N_D4_2
IO_L50P_2
IO_L50N_2
IO_L51P_2
IO_L51N_2
IP_L52P_2
IO_L52N_2
IO_L53P_2
IO_L53N_2
IO_L54P_2
IO_L54N_2
IO_L57P_2
IO_L57N_2
IO_L19P_2
IO_L58P_2
IO_L19N_2
IO_L58N_2
IO_L59P_2
XC6S25-FG484
IO_L20P_2
IO_L59N_2
IO_L20N_2
IO_L60P_2
IO_L21P_2
IO_L60N_2
IO_L21N_2
IO_L62P_D5_2
IO_L22P_2
IO_L62N_D6_2
IO_L22N_2
IO_L63P_2
IO_L23P_2
IO_L63N_2
IO_L23N_2
IO_L64P_D8_2
IO_L29P_GCLK3_2
IO_L64N_D8_2
IO_L29N_GCLK2_2
IO_L65P_INIT_B_2
IO_L17P_2
IO_L17N_2
IO_L18P_2
IO_L18N_2
Y 13
AB13
AA12
AB12
LVDS_P30
LVDS_N30
LVDS_P31
LVDS_N31
Y 11
AB11
R11
T11
AA10
AB10
V11
W11
LVDS_P32
LVDS_N32
LVDS_P40
LVDS_N40
LVDS_P41
LVDS_N41
LVDS_P42
LVDS_N42
Y9
AB9
W10
Y 10
AA8
AB8
W8
V7
W9
Y8
Y7
AB7
AA6
AB6
U9
V9
T8
U8
T10
U10
LVDS_P43
LVDS_N43
LVDS_P44
LVDS_N44
LVDS_P45
LVDS_N45
LVDS_P46
LVDS_N46
LVDS_P47
LVDS_N47
LVDS_P48
LVDS_N48
LVDS_P49
LVDS_N49
LVDS_P50
LVDS_N50
W6
Y6
Y5
AB5
AA4
AB4
Y3
AB3
R9
R8
T7
R7
W4
Y4
U6
V5
AA2
AB2
T6
LVDS_P53
LVDS_N53
LVDS_P54
LVDS_N54
LVDS_P57
LVDS_N57
LVDS_P58
LVDS_N58
LVDS_P59
LVDS_N59
LVDS_P60
LVDS_N60
LVDS_P62
LVDS_N62
LVDS_P63
LVDS_N63
LVDS_P64
LVDS_N64
INIT_65P
VCC3.3 BANK2
J8
LVDS_P2
LVDS_P5
LVDS_P14
LVDS_P6
LVDS_P15
LVDS_P19
LVDS_P17
LVDS_P21
IO_L13P_2
LENGTH SAME
DSS_D8
DSS_D5
DSS_D7
DSS_D4
2
2
2
2
3.3V
LVDS_P13
LVDS_P16
LVDS_P20
LVDS_P30
LVDS_P18
LVDS_P31
EXT_CLK1
LVDS_P40
LVDS_P42
LVDS_P32
LVDS_P44
LVDS_P41
LVDS_P50
LVDS_P43
LVDS_P59
LVDS_P47
LVDS_P45
LVDS_P60
LVDS_P46
LVDS_P48
LVDS_P53
LVDS_P49
LVDS_P63
LVDS_P54
LVDS_P62
LVDS_P57
LVDS_P58
LVDS_P64
R437
LENGTH SAME
AA21
AB21
10K
LVDS_P2
LVDS_N2
BUG FIX
SPARTAN-6 FG484
3.3V
Y4
50.000MHz
1
2
NC VCC
GND CLK
4
3
R398
22
FPGA_CLK1
SMD& DIP 겸용
Embedded and Logic Solution: eLogics
11
7
7
1
VCC2V5
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
A1
A2
A3
A4
A5
A6
A7
38
39 EEDIO/GPO3/TX_EN/TX_CLK
EECS
VCC2V5
12
11
10
9
8
7
6
VDD33REG
U8
BA1
BA2
BA3
BA4
BA5
BA6
BA7
18
VDDVARIO 24
VDDVARIO 30
VDDVARIO 56
VDDVARIO
+
C368
22uF/16V
B4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
CON80A
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
LVDS_N2
LVDS_N5
LVDS_N14
LVDS_N6
LVDS_N15
LVDS_N19
LVDS_N17
LVDS_N21
LVDS_N13
LVDS_N16
LVDS_N20
LVDS_N30
LVDS_N18
LVDS_N31
INIT_65P
LVDS_N40
LVDS_N42
LVDS_N32
LVDS_N44
LVDS_N41
LVDS_N50
LVDS_N43
LVDS_N59
LVDS_N47
LVDS_N45
LVDS_N60
LVDS_N46
LVDS_N48
LVDS_N53
LVDS_N49
LVDS_N63
LVDS_N54
LVDS_N62
LVDS_N57
LVDS_N58
LVDS_N64
ELS-MB1500A Manual V. 1.0 [2014-03-08]
7.5.
업보드 확장 콘넥터 회로도
bug
5V
VCC3.3 & 1.8V SELECT BLOCK
R418
330
J7
U6A
VCC1.8V
LVDS0_P1
LVDS0_N1
LVDS0_P2
LVDS0_N2
LVDS0_P3
LVDS0_N3
LVDS0_P4
LVDS0_N4
LVDS0_P5
A3
A4
C5
A5
D6
C6
B6
A6
C7
LVDS0_N5
LVDS0_P6
LVDS0_N6
LVDS0_P7
LVDS0_N7
LVDS0_P8
LVDS0_N8
LVDS0_NP14
LVDS0_NN14
LVDS0_NP15
A7
B8
A8
D9
C8
C9
A9
E8
F8
G8
LVDS0_NN15
LVDS0_NP16
LVDS0_NN16
LVDS0_NP17
LVDS0_NN17
LVDS0_NP18
LVDS0_NN18
LVDS0_P32
LVDS0_N32
LVDS0_P33
LVDS0_N33
LVDS0_P34
LVDS0_N34
F9
G9
H10
E10
F10
G11
H11
D7
D8
D10
C10
B10
A10
LVDS0_P35
LVDS0_N35
LVDS0_P36
LVDS0_N36
C11
A11
D11
C12
LVDS0_P37 B12
LVDS0_N37 A12
LVDS0_P38 C13
LVDS0_N38 A13
IO_L1P_HSWAPEN_0
IO_L1N_VREF_0
IO_L2P_0
IO_L2N_0
IO_L3P_0
IO_L3N_0
IO_L4P_0
IO_L4N_0
IO_L5P_0
IO_L5N_0
IO_L6P_0
IO_L6N_0
IO_L7P_0
IO_L7N_0
IO_L8P_0
IO_L8N_VREF_0
IO_L14P_0
IO_L14N_0
IO_L15P_0
IO_L15N_0
IO_L16P_0
IO_L16N_0
IO_L17P_0
IO_L17N_0
IO_L18P_0
IO_L18N_0
IO_L32P_0
IO_L32N_0
IO_L33P_0
IO_L33N_0
IO_L34P_GCLK19_0
IO_L34N_GCLK18_0
IO_L43P_0
IO_L43N_0
IO_L44P_0
IO_L44N_0
IO_L45P_0
IO_L45N_0
IO_L46P_0
IO_L46N_0
IO_L47P_0
IO_L47N_0
IO_L48P_0
IO_L48N_0
IO_L49P_0
IO_L49N_0
IO_L50P_0
IO_L50N_0
IO_L51P_0
IO_L51N_0
IO_L62P_0
IO_L62N_VREF_0
IO_L63P_SCP7_0
IO_L63N_SCP6_0
IO_L64P_SCP5_0
IO_L64N_SCP4_0
IO_L65P_SCP3_0
IO_L65N_SCP2_0
IO_L66P_SCP1_0
IO_L66N_SCP0_0
E12
D12
H12
F12
F13
D13
H13
G13
E14
F15
F14
H14
D14
C14
B14
A14
C15
A15
D15
C16
B16
LVDS0_P43
LVDS0_N43
LVDS0_P44
LVDS0_N44
LVDS0_P45
LVDS0_N45
LVDS0_P46
LVDS0_N46
LVDS0_P47
LVDS0_N47
LVDS0_P48
LVDS0_N48
LVDS0_P49
LVDS0_N49
LVDS0_P50
LVDS0_N50
LVDS0_P51
LVDS0_N51
LVDS0_P62
LVDS0_N62
LVDS0_P63
A16
C17
A17
B18
A18
E16
D17
LVDS0_N63
LVDS0_P64
LVDS0_N64
LVDS0_P65
LVDS0_N65
LVDS0_P66
LVDS0_N66
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
LVDS0_P1
LVDS0_P2
LVDS0_P3
LVDS0_P4
LVDS0_P32
LVDS0_P5
LVDS0_P7
LVDS0_P6
LVDS0_P8
LVDS0_NP14
LVDS0_NP15
LVDS0_NP16
LVDS0_NP17
LVDS0_NP18
LVDS0_P33
LVDS0_P36
18V_IO19P
LVDS0_P34
LVDS0_P37
LVDS0_P35
LVDS0_P44
LVDS0_P43
LVDS0_P38
LVDS0_P45
LVDS0_P46
LVDS0_P50
LVDS0_P49
LVDS0_P47
LVDS0_P48
LVDS0_P51
18V_IO20P
LVDS0_P63
LVDS0_P62
LVDS0_P64
LVDS0_P66
LVDS0_P65
IO_L35P_GCLK17_0
IO_L35N_GCLK16_0
IO_L36P_GCLK15_0
IO_L36N_GCLK14_0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
IO_L37P_GCLK13_0
IO_L37N_GCLK12_0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
LVDS0_N1
LVDS0_N2
LVDS0_N3
LVDS0_N4
LVDS0_N32
LVDS0_N5
LVDS0_N7
LVDS0_N6
LVDS0_N8
LVDS0_NN14
LVDS0_NN15
LVDS0_NN16
SW4
1
1
XEINT1
3
KEY _F1
R409
10K
LVDS0_NN17
LVDS0_NN18
LVDS0_N33
LVDS0_N36
VCC1.8V
18V_IO19N
LVDS0_N34
LVDS0_N37
LVDS0_N35
LVDS0_N44
LVDS0_N43
LVDS0_N38
LVDS0_N45
SW5
1
1
XEINT2
3
KEY _F1
R410
10K
LVDS0_N46
LVDS0_N50
LVDS0_N49
LVDS0_N47
LVDS0_N48
LVDS0_N51
18V_IO20N
LVDS0_N63
LVDS0_N62
LVDS0_N64
LVDS0_N66
LVDS0_N65
VCC1.8V
SW6
1
1
XEINT3
3
KEY _F1
R411
10K
CON80A
IO_L38P_0
IO_L38N_VREF_0
SPARTAN-6 FG484
XC6S25-FG484
VCC1.8V
SW7
1
1
XEINT4
3
KEY _F1
R412
10K
7.6.
DVI OUT 회로도
3.3V
L8
DVI_PVDD
C414
10V
L9
TVDD
L10
DVI_DVDD
C415
10V
C416
10V
C417
10V
C418
10V
C419
10V
BEAD
BEAD
BEAD
3.3V
Place Close to
the OMAP
Processor.
R420
22
3.3V
DVI_DEN
DVI_VSY NC
DVI_HSY NC
R429
R430
4.7K
4.7K
ISEL
10
13
R432
R433
4.7K
4.7K
BSEL
DVI_DSEL
15
14
0.1uF
DK3
DK2
DK1
4.7K
4.7K
4.7K
6
7
8
1
33
12
29
23
18
TXD1TXD1+
TXD2TXD2+
30
31
TXD1TXD1+
27
28
TXCTXC+
HTPLG
9
24
25
R422
4.7K
TXD0TXD0+
18
7
19
9
8
10
13
12
11
TXCTXC+
21
22
3.3V
TVDD
DAT2DAT2+
DAT2_S
SCL
SDA
20
21
22
23
DAT1DAT1+
DAT1_S
+5V
DDC/CEC GND
HPLG
DAT0DAT0+
DAT0_S
14
CBL_CEC
17
NC
CLK_S
CLKCLK+
MINI_HDMI
3.3V
4.7K 4.7K
Mini HDMI Interface
510
TFADJ
DKEN
RSVD2
NC
BSEL/SCL
DSEL/SDA
MSEN
TFADJ
19
35
34
49
DKEN
R431
410_NC
4.7K
MSEN
11
tq64-10x10-0.5
QFP64/0.5M
C420
10V
0.1uF
U32
3
5
4
6
T1
T2
T3
T4
R426R427R428
0.1uF 10V
I2C3_SCL
I2C3_SDA
6
5
4
DVI_+5v
HTPLG/EDGE
TXD0TXD0+
VCC1.8V
2
2
3
2
1
3.3V
PD
ISEL/RESET
DK3
DK2
DK1
P1
TXD2TXD2+
C421
I2C3_SCL
I2C3_SDA
RT1
15
16
26
32
20
16
48
64
R434
R435
R436
5V
0.1uF
PGND
R425
DVI_CLK+
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
IDCK+
IDCKDE
VSY NC
HSY NC
VREF
17
DSS_ACBIAS
DSS_VSY NC
DSS_HSY NC
22
22
63
62
61
60
59
58
55
54
53
52
51
50
47
46
45
44
43
42
41
40
39
38
37
36
57
56
2
5
4
3
TGND
TGND
TGND
DGND
DGND
DGND
2
2
2
R423
R424
0.1uF
100Ma
tFUSE-LITTEL_451
DVDD
DVDD
DVDD
TVDD
TVDD
PVDD
U31
TFP410
DVI_DATA0
DVI_DATA1
DVI_DATA2
DVI_DATA3
DVI_DATA4
DVI_DATA5
DVI_DATA6
DVI_DATA7
DVI_DATA8
DVI_DATA9
DVI_DATA10
DVI_DATA11
DSS_D0
DSS_D1
DSS_D2
DSS_D3
DSS_D4
DSS_D5
DSS_D6
DSS_D7
DSS_D8
DSS_D9
DSS_D10
DSS_D11
DSS_PCLK+
0.1uF
RXEF010 x
DVI_VREF
R421
10K,0603 x
2
0.1uF
4.7K
Adjusted for .9V
2
2
2
2
2
2
2
2
2
2
2
2
0.1uF
VCCA
A1
A2
OE
VCCB
B1
B2
GND
7
8
1
2
Internal 10K Pullups.
DDC_I2C3_SCL
DDC_I2C3_SDA
TXS0102 (DCU) x
DDC I2C Interface
Embedded and Logic Solution: eLogics
12
ELS-MB1500A Manual V. 1.0 [2014-03-08]
7.7.
System Clock generation 회로도

3.3V 50Mhz OSC

2.5V 200MhZ LVDS OSC 기본 장착(clock+, clock-)
7.8.
Reset 회로

Positive Level reset 입력( H: Reset, L: Normal)
VCC2V5
2
SW9
KEY _F1
C120
0.1uF
1
1
2 22
1
R403
PWR_nRST 2
2
R321
1K
BUG
7.9.
전원 회로

1.2V FPGA CORE 공급회로 : 1.2V 6A 전원공급

2.5V 이더넷 공급회로 : Gbps 이더넷 및 2.5V I/O 전원 공급

3.3V I/O 공급회로 : 3.3V I/O 전원 공급
7.10. Configuration Prom 회로

ST사의 MP25P64 Serial Prom을 사용했다.
Embedded and Logic Solution: eLogics
13
ELS-MB1500A Manual V. 1.0 [2014-03-08]
8. 콘넥터 설명
8.1.
USB1 – Console 포트로 사용됨
Pin
Pin
설 명
Name
Number
8.2.
1
VCC
USB 전원 5V 500mA
2
USB -
USB Negative Signal
3
USB +
USB Positive Signal
4
GND
Ground
CN6 RJ 45 JACK 1Gbps 이더넷 콘넥터
Pin
Pin
설
Name
명
Number
8.3.
1
TD0_P
1G TX0 Positive Transmit
2
TD0_N
1G TX0 Negative Transmit
3
TD1_P
1G TX1 Positive Transmit
4
TD1_N
1G TX1 Negative Transmit
5
TD2_P
1G TX2 Positive Transmit
6
TD2_N
1G TX2 Negative Transmit
7
TD3_P
1G TX3 Positive Transmit
8
TD3_N
1G TX3 Negative Transmit
J9 RJ 45 JACK 10/100 bps 이더넷 콘넥터
Pin
Pin
설
Name
명
Number
1
TD0_P
TX0 Positive Transmit
2
TD0_N
TX0 Negative Transmit
3
TD TAB
4
5
6
RXD TAB
7
RD0_N
RX0 Negative Transmit
Embedded and Logic Solution: eLogics
14
ELS-MB1500A Manual V. 1.0 [2014-03-08]
8
8.4.
RD0_P
RX0 Negative Transmit
J
1,CN7 DC Jack 5V (DC 입력)

8.5.
본 제품은
[email protected] 아답터 전원으로 사용한다.
J10. Xilinx Jtag
Pin Number
Pin Name
설 명
1
VCC
3.3 V
2
GND
Ground
3
TCK
JTAG Clock
4
TDO
JTAG Data Out
5
TDI
JTAG Data In
6
TMS
JTAG Mode Set
Embedded and Logic Solution: eLogics
15
ELS-MB1500A Manual V. 1.0 [2014-03-08]
8.6.
J8 UP Board 콘넥터( 3.3V I/O)
Num
I/O
BANK
1
LVDS_N2
3
5
FPGA NC P
Num
I/O
BANK
BANK2
2
LVDS_P2
BANK2
LVDS_N5
BANK2
4
LVDS_P5
BANK2
LVDS_N14
BANK2
6
LVDS_P14
BANK2
7
LVDS_N6
BANK2
8
LVDS_P6
BANK2
9
LVDS_N15
BANK2
10
LVDS_P15
BANK2
11
LVDS_N19
BANK2
12
LVDS_P19
BANK2
13
LVDS_N17
BANK2
14
LVDS_P17
BANK2
15
LVDS_N21
BANK2
16
LVDS_P21
BANK2
17
GND
18
GND
19
LVDS_N13
BANK2
20
LVDS_P13
BANK2
21
LVDS_N16
BANK2
22
LVDS_P16
BANK2
23
LVDS_N20
BANK2
24
LVDS_P20
BANK2
25
LVDS_N30
BANK2
26
LVDS_P30
BANK2
27
LVDS_N18
BANK2
28
LVDS_P18
BANK2
29
LVDS_N31
BANK2
30
LVDS_P31
BANK2
31
INIT_65P
BANK2
32
EXT_CLK1
BANK2
33
LVDS_N40
BANK2
34
LVDS_P40
BANK2
35
LVDS_N42
BANK2
36
LVDS_P42
BANK2
37
LVDS_N32
BANK2
38
LVDS_P32
BANK2
39
GND
40
GND
41
LVDS_N44
BANK2
42
LVDS_P44
BANK2
43
LVDS_N41
BANK2
44
LVDS_P41
BANK2
45
LVDS_N50
BANK2
46
LVDS_P50
BANK2
47
LVDS_N43
BANK2
48
LVDS_P43
BANK2
49
LVDS_N59
BANK2
LX75
50
LVDS_P59
BANK2
LX75
51
LVDS_N47
BANK2
LX75
52
LVDS_P47
BANK2
LX75
53
LVDS_N45
BANK2
54
LVDS_P45
BANK2
55
LVDS_N60
BANK2
LX75
56
LVDS_P60
BANK2
LX75
57
LVDS_N46
BANK2
LX75
58
LVDS_P46
BANK2
LX75
59
LVDS_N48
BANK2
60
LVDS_P48
BANK2
61
LVDS_N53
BANK2
62
LVDS_P53
BANK2
63
GND
64
GND
65
LVDS_N49
BANK2
66
LVDS_P49
BANK2
67
LVDS_N63
BANK2
68
LVDS_P63
BANK2
69
LVDS_N54
BANK2
70
LVDS_P54
BANK2
71
LVDS_N62
BANK2
72
LVDS_P62
BANK2
73
LVDS_N57
BANK2
74
LVDS_P57
BANK2
75
LVDS_N58
BANK2
76
LVDS_P58
BANK2
77
LVDS_N64
BANK2
78
LVDS_P64
BANK2
79
GND
80
GND
LX75,LX100
LX75
LX75
LX75
LX75
LX75
LX75
LX75
Embedded and Logic Solution: eLogics
16
FPGA NC P
LX75,LX100
LX75
LX75
LX75
LX75
LX75
LX75
LX75
ELS-MB1500A Manual V. 1.0 [2014-03-08]
8.7.
J7 (1.8V , 3.3V I/O 선택) UP Board 콘넥터 – B2: 1.8V
FPGA NC
, B9: 3.3V(디폴트)
Num
I/O
BANK
Num
I/O
BANK
1
VCC5
BANK0
2
VCC5
BANK0
3
LVDS0_N1
BANK0
4
LVDS0_P1
BANK0
5
LVDS0_N2
BANK0
6
LVDS0_P2
BANK0
7
LVDS0_N3
BANK0
8
LVDS0_P3
BANK0
9
LVDS0_N4
BANK0
10
LVDS0_P4
BANK0
11
LVDS0_N32
BANK0
12
LVDS0_P32
BANK0
13
LVDS0_N5
BANK0
14
LVDS0_P5
BANK0
15
LVDS0_N7
BANK0
16
LVDS0_P7
BANK0
17
LVDS0_N6
BANK0
18
LVDS0_P6
BANK0
19
LVDS0_N8
BANK0
20
LVDS0_P8
BANK0
21
LVDS0_N14
BANK0
22
LVDS0_P14
BANK0
23
LVDS0_N15
BANK0
24
LVDS0_P15
BANK0
25
LVDS0_N16
BANK0
26
LVDS0_P16
BANK0
27
GND
28
GND
29
LVDS0_N17
BANK0
30
LVDS0_P17
BANK0
31
LVDS0_N18
BANK0
32
LVDS0_P18
BANK0
33
LVDS0_N33
BANK0
34
LVDS0_P33
BANK0
35
LVDS0_N36
BANK0
36
LVDS0_P36
BANK0
37
LVDS1_N19_1.8
BANK1
38
LVDS1_P19_V1.8
BANK1
39
LVDS0_N34
BANK0
40
LVDS0_P34
BANK0
41
LVDS0_N37
BANK0
42
LVDS0_P37
BANK0
43
LVDS0_N35
BANK0
44
LVDS0_P35
BANK0
45
LVDS0_N44
BANK0
LX45,LX75
46
LVDS0_P44
BANK0
LX45,LX75
47
LVDS0_N43
BANK0
LX45
48
LVDS0_P43
BANK0
LX45
49
LVDS0_N38
BANK0
50
LVDS0_P38
BANK0
51
LVDS0_N45
BANK0
LX45
52
LVDS0_P45
BANK0
LX45
53
GND
54
GND
55
LVDS0_N46
BANK0
LX45
56
LVDS0_P46
BANK0
LX45
57
LVDS0_N50
BANK0
58
LVDS0_P50
BANK0
59
LVDS0_N49
BANK0
60
LVDS0_P49
BANK0
61
LVDS0_N47
BANK0
LX45
62
LVDS0_P47
BANK0
LX45
63
LVDS0_N48
BANK0
LX45
64
LVDS0_P48
BANK0
LX45
65
LVDS0_N51
BANK0
66
LVDS0_P51
BANK0
67
LVDS1_N20_1.8
BANK1
68
LVDS1_P20_1.8V
BANK1
69
LVDS0_N63
BANK0
70
LVDS0_P63
BANK0
71
LVDS0_N62
BANK0
72
LVDS0_P62
BANK0
73
LVDS0_N64
BANK0
74
LVDS0_P64
BANK0
75
LVDS0_N66
BANK0
76
LVDS0_P66
BANK0
77
LVDS0_N65
BANK0
78
LVDS0_P65
BANK0
79
GND
80
GND
1.8V IO
1.8V IO
Embedded and Logic Solution: eLogics
17
FPGA NC
1.8V IO
1.8V IO
ELS-MB1500A Manual V. 1.0 [2014-03-08]
8.8.
BEAD : BANK0 전원 선택 스위치(2개중 1개만 선택한다.) 디폴트 3.3V
Num
I/O
BANK
1
VCC 3.3V
+3.3V
1.8V
+1.8V
2
3
8.9.
P1. MINI HDMI 콘넥터( TMDS 3.3V I/O)
Pin
Pin
설
Name
명
Number
1
DATA2 Ground
TMDS GROUND
2
DATA2+
TMDS DATA2 PLUS
3
DATA2-
TMDS DATA2 MINUS
4
DATA1 Ground
TMDS GROUND
5
DATA1+
TMDS DATA1 PLUS
6
DATA1-
TMDS DATA1 MINUS
7
DDC/CEC GROUND
DDC RETURN GROUND
8
DATA0+
TMDS DATA0 PLUS
9
DATA0-
TMDS DATA0 MINUS
10
DATA0 GROUND
TMDS GROUND
11
CLK+
TMDS CLOCK PLUS
12
CLK-
TMDS CLOCK MINUS
13
CLK GROUND
TMDS CLOCK GROUND
14
CBL/CEC
CEC
15
DDC SCL
DDC CLOCK
16
DDC SDA
DDC DATA
17
NC
NC
18
DVI +5V
DVI OUT 5V
19
HPLG
HOT PLUG
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
8.10. Xilinx Tool을 이용한 FPGA 내용 변경 하기
jtag tool을 이용하여 FPGA 내용을 사용자 logic으로
변경 할 수 있다
8.10.1. Bit File을 만들기
아래그림에서 Generate Programming File를 더블 클릭하면
Synthesis -> Implement -> Bitfile 생성이 되며, 개발 시 필요한 bit file이 생성된다.
8.10.2. PROM FILE 만들기
Configure Taget Device -> Generate Target PROM/ACE File 을 클릭한다.
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
ISE IMPACT 프로그램이 실행된다. 여기서 Create PROM File Formatter를 클릭한다.
Configure Single FPGA ->
-> Auto Select PROM -> 순으로 클릭한다.
Output File Name : 생성될 file 이름
Output File Location : bit file 위치한 디렉토리
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
하단에 OK을 클릭한다.
OK을 누르면 Bitfile에서 생성된 file을 load한다.
또 다른 device Add을 할 창이 띄면 No 한다 -> 다음은 OK 을 누른다.
Geneare File…을 실행한다. 여기서 사용자 mcs파일이 생성되었다.
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
8.10.3. 생성된 Bit,mcs File 다운로드 하기
J1 콘넥터 순서: VCC,
GND , TCK ,TDI .TDO, TMS
Flashlink보드와 usb jtag ,제공된 프린터 jtag tool 을 연결한다.
Usb cable을 연결한다.
Boundary Scan을 클릭한다.
마우스 우측 button을 누른 후 Initialize Chain을 클릭한다.
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
클릭하면 우측에 XILINX IC 모양과 SPI/BPI 창이 뜬다.
SPI/BPI을 클릭한다. 클릭하면 위에서 생성된 *.MCS파일을 LOAD한다.
MB1500A 보드에 MP25P16, MP25P64가 실장 되어있어서 이것을 선택한다.
녹색으로 표시된 FLASH ICON을 클릭한다.
다음에 Program을 선택하여 Write을 진행하며 Wirte가 완료 시 성공 메시지가 표시된다.
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
9. Example Project
9.1.
4개의 LED와 DIP Switch 사용 예제

상태 표시 LED1,LED2,LED3,LED4

Option를 설정하기 위한 DIP SWICH SW1,SW2,SW3,SW4

예제 소스 : 제공된 프로젝트를 led blink open 한다.
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
9.2.
9.3.
module ledTest_top
9.4.
(
9.5.
sys_clk_pin,
9.6.
sys_rst_pin_i,
9.7.
leds
9.8.
);
9.9.
//
9.10. parameter
CLOCK_FREQ
= 50000000;
ONE_SECOND
= CLOCK_FREQ;
//
HALF_SECOND
= ONE_SECOND / 2;
//
// 50 Mhz
9.11.
9.12. parameter
1 second
9.13. parameter
1/2 second
9.14. parameter
ONE_MILLI_SECOND
= ONE_SECOND / 1000;
// One msec
9.15.
9.16. // port
9.17. input
sys_clk_pin;
9.18. input
sys_rst_pin_i;
9.19. output
[3:0]
leds;
9.20.
9.21.
9.22. wire
sys_rst_pin;
9.23.
9.24. assign sys_rst_pin = sys_rst_pin_i;
9.25. // DCM Clock Generating
9.26. wire
dcm_clk_w;
//
buffered clk
9.27. wire
dcm_clk_half_w;
//
buffered clk
9.28.
9.29. clk_dcm Inst_clk_dcm
9.30. (
9.31.
.clkin_in
9.32.
.rst_in
9.33.
.clkdv_out
(sys_clk_pin) ,
(sys_rst_pin) ,
(dcm_clk_half_w) ,
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
9.34.
.clkin_ibufg_out (CLKIN_IBUFG_OUT) ,
9.35.
.clk0_out
9.36.
.locked_out
(dcm_clk_w) ,
(LOCKED_OUT)
9.37. );
9.38.
9.39.
9.40. // Led
9.41. //assign
dcm_clk_out = dcm_clk_w;
9.42. reg
dir_r;
//
0 : left, 1 : right
9.43. reg [7:0]
leds_r;
9.44. reg [3:0]
led_count_r;
9.45.
9.46. reg [31:0]
count_r;
9.47. /*
9.48. [email protected](posedge sys_clk_pin ) begin
9.49.
if (sys_rst_pin) begin
9.50.
count_r <= 0;
9.51.
end
9.52.
else
9.53.
count_r <= count_r + 1;
9.54.
9.55. end
9.56.
9.57. */
9.58.
9.59. [email protected](posedge sys_rst_pin or posedge dcm_clk_w) begin
9.60. //[email protected](posedge sys_clk_pin ) begin
9.61.
if (sys_rst_pin) begin
9.62.
dir_r
<= 0;
9.63.
leds_r
<= 8'b00000001;
9.64.
led_count_r <= 1;
9.65.
count_r <= 0;
9.66.
end
9.67.
else begin
9.68.
//count_r <= count_r + 1;
9.69.
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ELS-MB1500A Manual V. 1.0 [2014-03-08]
9.70.
if ( count_r >= ONE_MILLI_SECOND * 3'b111)begin //dip_sw[6:0] ) begin
9.71.
led_count_r <= led_count_r + 1;
9.72.
9.73.
if (dir_r == 1'b0)
9.74.
leds_r <= leds_r << 1;
9.75.
else
9.76.
leds_r <= leds_r >> 1;
9.77.
9.78.
count_r <= 0;
9.79.
end
9.80.
else count_r <= count_r + 1;
9.81.
9.82.
if (led_count_r == 4'b1000)
9.83.
dir_r <= ~dir_r;
9.84.
led_count_r <= 1;
9.85.
9.86.
begin
end
end
9.87. end
9.88.
9.89. // 0 : On, 1 : Off
9.90. assign leds[3:0] = ~leds_r[3:0];
9.91. //assign leds[3:0] = ~count_r[15:12];
9.92. //assign leds[3:0] = {sys_clk_pin,sys_rst_pin_i,sys_clk_pin,sys_rst_pin_i};
NET sys_clk_pin
LOC="Y12"|IOSTANDARD=LVCMOS33;
# 50Mhz
//NET sys_rst_pin_i
LOC="H8" |SLEW=SLOW |IOSTANDARD=LVCMOS25;
NET sys_rst_pin_i
LOC="L17" |SLEW=SLOW |IOSTANDARD=LVCMOS18;
NET leds<0>
LOC="AB20";
NET leds<1>
LOC="AA20";
NET leds<2>
LOC="U14";
NET leds<3>
LOC="U13";
#NET dip_sw<0>
LOC=M1;
#NET dip_sw<1>
LOC=M2;
#NET dip_sw<2>
LOC=M3;
#NET dip_sw<3>
LOC=M4;
#NET dip_sw<4>
LOC=L1;
#NET dip_sw<5>
LOC=L4;
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#NET dip_sw<6>
LOC=L3;
#NET dip_sw<7>
LOC=L6;
#NET dcm_clk_out
LOC=C22;
;
위 프로젝트를 임플리먼트를 실행 후 bit File을 다운로드 한다.
그러면 LED가 깜박이는 것을 볼 수 있다.
9.93. SB601프로젝트 실습하기
9.93.1. Windows응용프로그램 설치하기(아래 프로그램은 XP에서만 지원됨 WIN7은 지원 되지 않
음)

d: \project\MB1500A\SP601_BRD_Application\BaseRefDISetup2_0_6.msi 이 파일을 설
치한다. 설치 후 실행하면 아래와 같다.
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9.93.2. SP601 프로젝트 컴파일 및 bit 파일 만들기

d:\project\MB1500A\DSP48A\DSP48A.xise를 더블 클릭한다.

임플리먼트를 실행하고 bit, MCS파일을 생성한다.

생성된 BIT파일을 다운로드 한다.

1G BIT 이더넷 통신모드로 동작을 한다. 위에 빨강색으로 표시된 Not connected FPGA
메시지가 connected FPGA로 바뀐다.

Select Image에서 영상 처리해야 할 이미지 파일을 선택한다.

아래 메뉴에 show display를
클릭한다. 설치된 os에 따라 이미지가 표시 되지 않을 수
있다. 이 경우에는 영문 windows XP를 설치하여 테스트 하면 된다.

이미지 실행 모두가
AUTO 와 Manual를 선택하면서 실행하면 된다.
9.93.3. DVI 모니터로 출력하기(SUB BOARD )

단) DVI서브 보드를 구입한 보드에 한함(SB1600),또는 MB1500A

MB1500A보드에 HDMI 케이블을 연결한다.

연결 시 영상처리 결과를 모니터로 통해서 볼 수 있다.
10. EDK 활용
10.1.
EDK사용법은 CD에 제공된 Xilinx_Embedded_Processor.pdf 파일을 참조 합니다.
제공된C/D에서 D:\sale_project\LOGIC_PROGRAM\edk_LWIP_142_45\system.xmp를 더
블 클릭하면 위와 같이 프로젝트가 OPEN 됩니다.
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ELS-MB1500A Manual V. 1.0 [2014-03-08]

위 예제는 메모리 테스트 프로젝트 입니다. 여기에 사용자 로직 및 응용 프로그램을 코
딩하여 사용 하면 됩니다.
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