A25L032 Series 32Mbit Low Voltage, Dual-I/O Serial Flash Memory

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A25L032 Series

32Mbit Low Voltage, Dual-I/O Serial Flash Memory with 100MHz Uniform 4KB Sectors

Document Title

32Mbit, Low Voltage, Dual-I/O Serial Flash Memory with 100MHz Uniform 4KB Sectors

Revision History

0.0

0.1

0.2

0.3

0.4

0.5

Initial issue

Spec. change for new commands

Add packing description in Part Numbering Scheme

P31: Modify Read Device Identification

P40: Remove the min. value of I

CC1

and I

CC2

P32: ID code error correction

P39: Change Data Retention and Endurance value from Max. to

August 18, 2008

July 13, 2009

May 3, 2010

July 27, 2010

September 21, 2010

October 7, 2010

Min.

1.0 Change

1.1

, t

BE

and t by request)” in Features

CE

data values May 26, 2011

Final version release

P1: Add “Provide 64Bytes Security ID (application note is available September 19, 2011

November 15, 2011

1.3

Add 8-pin WSON (6*5mm) package type

P40: Change I

CC6

& I

CC7

(max.) from 15mA to 25mA March 29, 2012

Preliminary

Final

(March, 2012, Version 1.3)

AMIC Technology Corp.

A25L032 Series

32Mbit Low Voltage, Dual-I/O Serial Flash Memory with 100MHz Uniform 4KB Sectors

FEATURES

„ Family of Serial Flash Memories

- A25L032: 32M-bit /4M-byte

„ Flexible Sector Architecture with 4KB sectors

- Sector Erase (4K-bytes) in 80ms (typical)

- Block Erase (64K-bytes) in 0.5s (typical)

„ Page Program (up to 256 Bytes) in 1.5ms (typical)

„ 2.7 to 3.6V Single Supply Voltage

„ Dual input / output instructions resulting in an equivalent clock frequency of 200MHz:

- FAST_READ_DUAL_OUTPUT Instruction

- FAST_READ_DUAL_INPUT_OUTPUT Instruction

- Dual Input Fast Program (DIFP) Instruction

„ SPI Bus Compatible Serial Interface

„ 100MHz Clock Rate (maximum)

„ Deep Power-down Mode 15µA (Max.)

„ Advanced Protection Features

- Software and Hardware Write-Protect

- Top/Bottom, 4KB Complement Array Protection

„ Additional 64-byte user-lockable, one-time programmable

(OTP) area

„ 32Mbit Flash memory

- Uniform 4-Kbyte Sectors

- Uniform 64-Kbyte Blocks

„ Electronic Signatures

- JEDEC Standard Two-Byte Signature

A25L032: (3016h)

RES Instruction, One-Byte, Signature, for backward compatibility

A25L032: (15h)

„ Package options

- 8-pin SOP (209mil), 8-pin DIP (300mil), 16-pin SOP

(300mil) or 8-pin WSON (6*5mm)

- All Pb-free (Lead-free) products are RoHS compliant

„ Provide 64Bytes Security ID (application note is available by request)

GENERAL DESCRIPTION

The A25L032 is 32M bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed

SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.

The memory is organized as 64 blocks, each containing 16

Pin Configurations

„

SOP8 / DIP8 Connections

„ sectors. Each sector is composed of 16 pages. Each page is

256 bytes wide. Thus, the whole memory can be viewed as consisting of 16,384 pages, or 4,194,304 bytes.

The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction, or a sector at a time, using the Sector Erase instruction.

SOP16 Connections

„

WSON8 Connections

A25L032

S

DO (IO

1

)

V

W

SS

1 8

2 7

3 6

4 5

V

CC

HOLD

C

DI (IO

0

)

HOLD

V

CC

DU

DU

DU

DU

S

DO (IO

1

)

A25L032

1 16

2 15

3 14

4 13

5 12

6 11

7 10

8 9

C

DI (IO

0

)

DU

DU

DU

DU

V

W

SS

S

DO (IO

1

)

V

W

SS

1

2

3

4

A25L032

8

7

6

5

V

CC

HOLD

C

DI (IO

0

)

Note:

DU = Do not Use

(March, 2012, Version 1.3) 1

AMIC Technology Corp.

Pin DescriptionsSOP8, DIP8, WSON8

Pin No.

1

Pin Name

S

3

W

4 V

SS

I/O

I

I/O

I

Description

Chip Select Input

Data Output (Data Input Output 1)

(1)

Write Protect Input

Ground

I/O Data Input (Data Input Output 0)

(1)

I Serial Clock Input 6 C

7

HOLD

8 V

CC

Notes:

(1) IO

0

and IO

1

are used for Dual Instruction.

Pin DescriptionsSOP16

Pin No. Pin Name

1 HOLD

2 V

CC

3 DU

I/O Description

4 DU

5 DU

6 DU

7

S

I

I/O

Chip Select Input

Data Output (Data Input Output 1)

(1)

9

W

I Write Protect Input

10 V

SS

Ground

11 DU

12 DU

13 DU

14 DU

16 C

I/O Data Input (Data Input Output 0)

(1)

I Serial Clock Input

Notes:

(1) IO

0

and IO

1

are used for Dual Instruction.

(March, 2012, Version 1.3) 2

A25L032 Series

AMIC Technology Corp.

Block Diagram

HOLD

W

S

C

DI (IO

0

)

DO (IO

1

)

Control Logic

Address register and Counter

A25L032 Series

High Voltage

Generator

64 OTP bytes

I/O Shift Register

256 Byte

Data Buffer

3FFFFF (32M)

Status

Register

Size of the memory area

00000h 000FFh

256 Byte (Page Size)

X Decoder

(March, 2012, Version 1.3) 3

AMIC Technology Corp.

PIN DESCRIPTION

Chip Select ( S )

The SPI Chip Select ( S ) pin enables and disables device operation. When Chip Select ( S ) is high the device is deselected and the Serial Data Output (DO, or IO

0

, IO

1

) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress.

When Chip Select ( S ) is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, Chip Select (

S

) must transition from high to low before a new instruction will be accepted.

Serial Data Input, Output and IOs (DI, DO and IO

0

, IO

1

)

The A25L032 support standard SPI and Dual SPI operation.

Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (C) input pin. Standard

SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of Serial Clock (C).

Dual SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of Serial clock (C) and read data or status from the device on the falling edge of Serial Clock (C).

A25L032 Series

Write Protect ( W )

The Write Protect (

W

) pin can be used to prevent the Status

Register from being written. Used in conjunction with the

Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP1, SRP0) bits, a portion or the entire memory array can be hardware protected. The Write Protect ( W ) pin is active low.

Hold ( HOLD )

The Hold (

HOLD

) pin allows the device to be paused while it is actively selected. When Hold ( HOLD ) pin is brought low, while Chip Select ( S ) pin is low, the DO pin will be at high impedance and signals on the DI and Serial Clock (C) pins will be ignored (don’t care). When Hold ( HOLD ) pin is brought high, device operation can resume. The Hold function can be useful when multiple devices are sharing the same SPI signals. The Hold ( HOLD ) pin is active low.

Serial Clock (C)

The SPI Serial Clock Input (C) pin provides the timing for serial input and output operations.

(March, 2012, Version 1.3) 4

AMIC Technology Corp.

SPI MODES

These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the

Figure 1. SPI Modes Supported

A25L032 Series

falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 1, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

CPOL CPHA

0

1

0

1

DI

DO

C

C

MSB

MSB

(March, 2012, Version 1.3) 5

AMIC Technology Corp.

SPI OPERATIONS

Standard SPI Instructions

The A25L032 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (C), Chip Select ( S ),

Serial Data Input (DI), and Serial Data Output (DO). Standard

SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of Serial Clock (C). The DO output pin is used to read data or status from the device on the falling edge of Serial

Clock (C).

Dual SPI Instructions

The A25L032 supports Dual SPI operation when using the

“FAST_READ_DUAL_OUTPUT and FAST_READ_DUAL_

INPUT_OUTPUT” (3B and BB hex) instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices.

The Dual Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus

(XIP). When using Dual SPI instructions the DI and DO pins become bidirectional I/O pins; IO

0

and IO

1

.

Hold Condition

The Hold (

HOLD

) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. The

HOLD

function is only available for standard SPI and Dual SPI operation, not during

Quad SPI.

Figure 2. Hold Condition Activation

C

A25L032 Series

To enter the Hold condition, the device must be selected, with

Chip Select (

S

) Low.

The Hold condition starts on the falling edge of the Hold

(

HOLD

) signal, provided that this coincides with Serial Clock

(C) being Low (as shown in Figure 2.).

The Hold condition ends on the rising edge of the Hold

(

HOLD

) signal, provided that this coincides with Serial Clock

(C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after

Serial Clock (C) next goes Low. This is shown in Figure 2.

During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip Select (

S

) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition.

If Chip Select (

S

) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (

HOLD

) High, and then to drive Chip

Select (

S

) Low. This prevents the device from going back to the Hold condition.

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

(March, 2012, Version 1.3) 6

AMIC Technology Corp.

OPERATING FEATURES

Page Programming

To program one data byte, two instructions are required: Write

Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t

PP

).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory.

Dual Input Fast Program

The Dual Input Fast Program (DIFP) instruction makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from 1 to 0).

For optimized timings, it is recommended to use the Dual

Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Dual Input Fast Program (DIFP) sequences each containing only a few bytes.

Sector Erase, Block Erase, and Chip Erase

The Page Program (PP) instruction and Dual Input Fast

Program (DIFP) instruction allow bits to be reset from 1 to 0.

Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved, a sector at a time, using the Sector Erase (SE) instruction, a block at a time, using the Block Erase (BE) instruction, or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration t

SE,

t

BE,

or t

CE

).

The Erase instruction must be preceded by a Write Enable

(WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register

(WRSR), Program OTP (POTP), Program (PP, DIFP), or

Erase (SE, BE, or CE) can be achieved by not waiting for the worst case delay (t

W

, t

PP

, t

SE

, t

BE

, t

CE

). The Write In Progress

(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or

Erase cycle is complete.

Active Power, Stand-by Power and Deep Power-Down

Modes

When Chip Select (

S

) is Low, the device is enabled, and in the Active Power mode.

When Chip Select ( S ) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to I

CC1

.

The Deep Power-down mode is entered when the specific instruction (the Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to I

CC2

. The device remains in this mode until another specific instruction

A25L032 Series

(the Release from Deep Power-down Mode and Read

Electronic Signature (RES) instruction) is executed.

All other instructions are ignored while the device is in the

Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write,

Program or Erase instructions.

Status Register

The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Read Status Register (RDSR) for a detailed description of the Status Register bits.

Protection Modes

The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the

A25L032 boasts the following data protection mechanisms:

„ Power-On Reset and an internal timer (t

PUW

) can provide protection against inadvertent changes while the power supply is outside the operating specification.

„ Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.

„ All instructions that modify data must be preceded by a

Write Enable (WREN) instruction to set the Write Enable

Latch (WEL) bit. This bit is returned to its reset state by the following events:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Program OTP (POTP) instruction completion

- Page Program (PP) instruction completion

- Dual Input Fast Program (DIFP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

„

The Block Protect (BP2, BP1, BP0) bits conjunction with

Sector Protect (SEC) bit , Top/Bottom (TB) bit and

Complement Protect (CMP) bit allow part of the memory to be configured as read-only. This is the Software Protected

Mode (SPM).

„ The Write Protect ( W ) signal allows the Block Protect

(BP2, BP1, BP0) bits, Sector Protect (SEC) bit,

Top/Bottom (TB) bit, All Protect (APT), Complement

Protect (CMP) bit and Status Register Protect (SRP1,

SRP0) bits to be protected. This is the Hardware

Protected Mode (HPM).

„ In addition to the low power consumption feature, the

Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction

(the Release from Deep Power-down instruction).

(March, 2012, Version 1.3) 7

AMIC Technology Corp.

Table 1-1. Protected Area Sizes (CMP=0)

A25L032

Status Register Content

SEC Block(s)

X None

A25L032 Series

(32M-Bit) Memory Protection

Addresses

None

Density(Byte)

None

Portion

None

1

X

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

X

1

1

1

0

0

0

0

1

1

1

1

1

0

0

1

1

1

1

0

0

0

1

1

0

0

0

1

1

1

1

0

0

1

1

0

1

1

0

1

0

1

1

0

1

0

1

0

1

0

1

1

0

1

X

0

1

0

1

X

0

0 00FFFFh

0 – 1 000000h – 01FFFFh

0 – 3

0 – 7

0 – 15

0 – 31

0 – 63

63

63

63

63

63

0

0

0

0

0

000000h – 03FFFFh

000000h – 07FFFFh

000000h – 0FFFFFh

000000h – 1FFFFFh

000000h – 3FFFFFh

3FF000h – 3FFFFFh

3FE000h – 3FFFFFh

3FC000h – 3FFFFFh

3F8000h – 3FFFFFh

3F0000h – 3FFFFFh

000000h – 000FFFh

000000h – 001FFFh

000000h – 003FFFh

000000h – 007FFFh

000000h – 00FFFFh

128KB

256KB

512KB

1MB

2MB

64KB

128KB

256KB

512KB

1MB

2MB

4MB

4KB

8KB

16KB

32KB

64KB

4KB

8KB

16KB

32KB

64KB

Upper 1/32

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

Lower 1/32

Lower 1/16

Lower 1/8

Lower 1/4

Lower 1/2

ALL

Top Block

Top Block

Top Block

Top Block

Top Block

Bottom Block

Bottom Block

Bottom Block

Bottom Block

Bottom Block

Note:

1. X = don’t care

2. When CMP is 0, the device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.

(March, 2012, Version 1.3) 8

AMIC Technology Corp.

Table 1-2. Protected Area Sizes (CMP=1)

A25L032 Series

A25L032

Status Register Content (32M-Bit) Memory Protection

SEC Block(s)

X

0

0

0

0

0

0

X

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

0 - 63

0 - 62

0 – 61

0 – 59

0 – 55

0 – 47

0 – 31

0 1

0 2

0 4

0 8

Addresses

000000h – 3FFFFFh

000000h – 3EFFFFh

000000h – 3DFFFFh

000000h – 3BFFFFh

000000h – 37FFFFh

000000h – 2FFFFFh

000000h – 1FFFFFh

Density(Byte)

4MB

4032KB

3968KB

3840KB

3584KB

3MB

2MB

4032KB

3968KB

3840KB

3584KB

3MB

2MB

None

4092KB

4088KB

4080KB

Portion

All

Lower 63/64

Lower 31/32

Lower 15/16

Lower 7/8

Lower 3/4

Lower 1/2

Upper 63/64

Upper 31/32

Upper 15/16

Upper 7/8

Upper 3/4

Upper 1/2

None

Lower 1023/1024

Lower 511/512

Lower 255/256

1

1

1

1

1

1

1

X None

1 0 0 0 1 0 - 62

None

000000h – 3FEFFFh

0

0

0

0

0

0

1

1

1

1

0

1

0

1

X

0

0 - 62

0 - 62

0 - 62

0 - 62

000000h – 3FDFFFh

000000h – 3FBFFFh

000000h – 3F7FFFh

000000h – 3EFFFFh

1

1

1

0

0

0

0

1

1

1

0

1

1 – 63

1 – 63

1 – 63

1 1 1 0 X 1 – 63

1 -

001000h – 3FFFFFh

002000h – 3FFFFFh

004000h – 3FFFFFh

008000h – 3FFFFFh

4032KB Lower 63/64

4032KB Upper 63/64

Note:

1. X = don’t care

2. When CMP is 1, the device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) bits are 1.

(March, 2012, Version 1.3) 9

AMIC Technology Corp.

22

21

24

23

26

25

28

27

MEMORY ORGANIZATION

The memory is organized as:

„ 4,194,304 bytes (8 bits each)

„ 64 blocks (64 Kbytes each)

„ 1024 sectors (4 Kbytes each)

„ 16384 pages (256 bytes each)

„ 64 bytes OTP located outside the main memory array

Table 2. Memory Organization

A25L032 Address Table

Block Sector

1023

Address range

3FF000h 3FFFFFh

63

1008 3F0000h 3F0FFFh

62

992 3E0000h 3E0FFFh

400

399

384

383

368

367

463

448

447

432

431

416

415

352

351

336

1CF000h 1CFFFFh

1C0000h 1C0FFFh

1BF000h 1BFFFFh

1B0000h 1B0FFFh

1AF000h 1AFFFFh

1A0000h 1A0FFFh

19F000h 19FFFFh

190000h 190FFFh

18F000h 18FFFFh

180000h 180FFFh

17F000h 17FFFFh

170000h 170FFFh

16F000h 16FFFFh

160000h 160FFFh

15F000h 15FFFFh

150000h 150FFFh

A25L032 Series

Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block, or Chip

Erasable (bits are erased from 0 to 1) but not Page Erasable.

Block

20

Sector

335

320

319

304

303

288

287

272

271

256

255

240

239

224

223

208

207

192

191

176

175

160

19

12

11

14

13

10

16

15

18

17

Address range

14F000h 14FFFFh

140000h 140FFFh

13F000h 13FFFFh

130000h 130FFFh

12F000h 12FFFFh

120000h 120FFFh

11F000h 11FFFFh

110000h 110FFFh

10F000h 10FFFFh

100000h

FF000h

100FFFh

FFFFFh

F0000h

EF000h

F0FFFh

EFFFFh

E0000h

DF000h

E0FFFh

DFFFFh

D0000h

CF000h

D0FFFh

CFFFFh

C0000h

BF000h

C0FFFh

BFFFFh

B0000h

AF000h

B0FFFh

AFFFFh

A0000h A0FFFh

(March, 2012, Version 1.3) 10

AMIC Technology Corp.

7

6

5

Memory Organization (continued)

Block Sector

159

Address range

9F000h 9FFFFh

9

144

143

90000h

8F000h

90FFFh

8FFFFh

8

128

127

80000h

7F000h

80FFFh

7FFFFh

4

112

111

96

95

80

79

64

70000h

6F000h

60000h

5F000h

50000h

4F000h

40000h

70FFFh

6FFFFh

60FFFh

5FFFFh

50FFFh

4FFFFh

40FFFh

A25L032 Series

Block

3

2

1

0

Sector

63

48

47

32

31

16

15

4

3

2

1

0

Address range

3F000h 3FFFFh

30000h

2F000h

30FFFh

2FFFFh

20000h

1F000h

10000h

0F000h

04000h

03000h

02000h

01000h

00000h

20FFFh

1FFFFh

10FFFh

0FFFFh

04FFFh

03FFFh

02FFFh

01FFFh

00FFFh

(March, 2012, Version 1.3) 11

AMIC Technology Corp.

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of the device, most significant bit first.

Serial Data Input(s) IO

0

(IO

1

) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select ( S ) is driven

Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input(s) IO

0

(IO

1

), each bit being latched on the rising edges of Serial

Clock (C).

The instruction set is listed in Table 3.

Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by dummy bytes (don’t care), or by a combination or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at

Higher Speed (Fast_Read), Read Data Bytes at Higher Speed by Dual Output (FAST_READ_DUAL_OUTPUT), Read Data

Bytes at Higher Speed by Dual Input and Dual Output

(FAST_READ_DUAL_INPUT_OUTPUT), Read OTP (ROTP),

Read Identification (RDID), Read Electronic Manufacturer and

Device Identification (REMS), Read Status Register (RDSR) or Release from Deep Power-down, Read Device

A25L032 Series

Identification and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select ( S ) can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Program OTP (POTP),

Dual Input Fast Program (DIFP), Sector Erase (SE), Block

Erase (BE), Chip Erase (CE), Write Status Register (WRSR),

Write Enable (WREN), Write Disable (WRDI) or Deep

Power-down (DP) instruction, Chip Select (

S

) must be driven

High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select ( S ) must driven High when the number of clock pulses after Chip Select

( S ) being driven Low is an exact multiple of eight.

All attempts to access the memory array during a Write Status

Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or

Erase cycle continues unaffected.

(March, 2012, Version 1.3) 12

AMIC Technology Corp.

A25L032 Series

Table 3. Instruction Set

PP

DIFP

SE

BE

CE

DP

RDID

WREN

WRDI

RDSR-1

RDSR-2

WRSR

READ

FAST_READ

FAST_READ_DUAL

_OUTPUT

FAST_READ_DUAL

_INPUT_OUTPUT

RES

Instruction

ROTP

POTP

REMS

Description

Write Enable

Write Disable

Read Status Register-1

Read Status Register-2

Write Status Register

Read Data Bytes

Read Data Bytes at Higher Speed

Read Data Bytes at Higher Speed by

Dual Output

(1)

Read Data Bytes at Higher Speed by

Dual Input and Dual Output

(1)(2)

Read OTP (Read 64 bytes of OTP area)

Program OTP (Program 64 bytes of

OTP area)

Page Program

Dual Input Fast Program

Sector Erase

Block Erase

Chip Erase

Deep Power-down

Read Device Identification

Read Electronic Manufacturer & Device

Identification

Release from Deep Power-down, and

Read Electronic Signature

1010 1011

Release from Deep Power-down

High Performance Mode 1010 0011

Reset Mode Bit M<4> to 1

One-byte

Instruction Code

0000 0110

0000 0100

0000 0101

0011 0101

0000 0001

0000 0011

0000 1011

0011 1011

1011 1011

0100 1011

0100 0010

0000 0010

1010 0010

0010 0000

1101 1000

1100 0111

1011 1001

1001 1111

1001 0000

1111 1111

1111 1111

06h

04h

05h

35h

01h

03h

0Bh

3Bh

BBh

4Bh or 48h

42h

02h

A2h

20h

D8h or 52h

C7h or 60h

B9h

9Fh

90h

ABh

A3h

FFFFh

Address

Bytes

0

0

0

0

0

3

3

3

1

3

(2)

3

3

0

0

0

3

3

3

3

(4)

Dummy

Bytes

1

0

0

0

0

0

0

1

(2)

0

0

0

0

0

0

0

Data

Bytes

0

0

1 to ∞

1 to ∞

2

1 to ∞

1 to ∞

1 to ∞

(1)

1

1 to 256

1 to 256

0

0

0

0

1 to ∞

(3)

0 0 0

0

0

1

1

0

3

0

1 to ∞

1 to 64

0

0

HPM

Continuous Read

Mode Reset

(5)

Note: (1) Dual Output Data

IO

0

= (D

6

, D

4

, D

2

, D

0

)

IO

1

= (D

7

, D

5

, D

3

, D

1

)

(2) Dual Input Address

IO

0

= (A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0)

IO

1

= (A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1)

(3) Dual Input Fast Program Input Data

IO

0

= (D

6

, D

4

, D

2

, D

0

)

IO

1

= (D

7

, D

5

, D

3

, D

1

)

(4) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first

(5) This instruction is recommended when using the Dual “Continuous Read Mode” features. See page 22 for

more information.

(March, 2012, Version 1.3) 13

AMIC Technology Corp.

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 3.) sets the

Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every

Page Program (PP), Dual Input Fast Program (DIFP),

Program OTP (POTP), Sector Erase (SE), Block Erase (BE), and Chip Erase (CE) and Write Status Register (WRSR)

Figure 3. Write Enable (WREN) Instruction Sequence

S

A25L032 Series

instruction.

The Write Enable (WREN) instruction is entered by driving

Chip Select ( S ) Low, sending the instruction code, and then driving Chip Select ( S ) High.

0 1 2 3 4 5 6 7

C

Instruction (06h)

DI

High Impedance

DO

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 4.) resets the

Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip

Select (

S

) Low, sending the instruction code, and then driving

Chip The Write Enable Latch (WEL) bit is reset under the following conditions:

Figure 4. Write Disable (WRDI) Instruction Sequence

S

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Page Program (PP) instruction completion

Dual Input Fast Program (DIFP) instruction completion

Program OTP (POTP) in struction completion

Sector Erase (SE) instruction completion

Block Erase (BE) instruction completion

Chip Erase (CE) instruction completion

C

0 1 2 3 4 5 6 7

Instruction (04h)

DI

High Impedance

DO

(March, 2012, Version 1.3) 14

AMIC Technology Corp.

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the

Status Register to be read. The instruction code of “05h” is for Status Register-1 and “35h” is for Status Register-2. The

Status Register may be read at any time, even while a

Program, Erase or Write Status Register cycle is in progress.

When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the

Status Register continuously, as shown in Figure 5.

Table 4-a Status Register-1 Format

b7 b6

SRP0 SEC b5

TB b4 b3 b2 b1 b0

BP2 BP1 BP0 WEL WIP

Status Register Protect 0

(Non-volatile)

Sector Protect

(Non-volatile)

Top/Bottom Bit

(Non-volatile)

Block Protect Bits

(Non-volatile)

Write Enable Latch Bit

Write In Progress Bit

Table 4-b Status Register-2 Format

b15

0 b14 b13 b12 b11 b10 b9

CMP 0 0 0 APT 0

Reserved

Complement Protect

(Non-volatile)

Reserved

All Protect (Non-volatile) b8

SRP1

Reserved

Status Register Protect 1

(Non-volatile)

The status and control bits of the Status Register are as follows:

WIP bit.

The Write In Progress (WIP) bit is a read only bit in the status register (b0) that is set to a 1 state when the device is busy with a Write Status Register, Program or

Erase cycle. During this time the device will ignore further instructions except for the Read Status Register instruction

(see t

W

, t

PP

, t

SE

, t

BE

, and t

CE

in AC Characteristics). When the program, erase, or write status register instruction has completed, the WIP bit will be cleared to a 0 state indicating the device is ready for further instructions.

WEL bit.

The Write Enable Latch (WEL) bit is a read only bit in the status register (b1) that is set to a 1 after executing a

Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Dual Input Fast

Program, Quad Input Fast Program, Sector Erase, Block

A25L032 Series

Erase, Chip Erase, and Write Status Register.

BP2, BP1, BP0 bits.

The Block Protect (BP2, BP1, and BP0) bits are non-volatile read/write bits in the status register (b4, b3, and b2) that provide Write Protection control and status.

Block Protect bits can be set using the Write Status Register

Instruction (see t in AC characteristics). All, none or a

W portion of the memory array can be protected from Program and Erase instructions (see Table 1. Protected Area Sizes).

These bits can be set with the Write Status Register

Instruction depending on the state of the SRP1, SRP0, and

WEL bit. The factory default setting for the Block Protect Bits is 0 which means none of the array protected. For value of

BP2, BP1, BP0 after power-on, see note please.

TB bit.

The non-volatile Top/Bottom (TB) bit controls if the

Block Protect Bits (BP2, BP1, BP0) protect from the Top

(TB=0) or the Bottom (TB=1) of the array as shown in Table 1.

Protected Area Sizes. The factory default setting is TB=0.

The TB bit can be set with the Write Status Register

Instruction depending on the state of the SRP1, SRP0, and

WEL bit.

SEC bit.

The non-volatile Sector Protect (SEC) bit in the status register (b6) controls if the Block Protect Bits (BP2,

BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks

(SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in Table 1. Protected Area Sizes. This bit can be set with the Write Status Register Instruction depending on the state of the SRP1, SRP0, and WEL bit. The factory default setting for SEC is 0.

SRP1, SRP0 bits.

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (b8 and b7). The SRP bits control the method of write protection: software protection, hardware protection, or one time programmable protection.

APT bit.

The All Protect (APT) bit is a non-volatile read/write bit in the status register (b10). Whole chip will be kept in write-protect state after power-on if this bit is set to 1. This bit can be set with the Write Status Register Instruction depending on the state of the SRP1, SRP0, and WEL bit.

The factory default setting for APT is 0.

CMP bit.

The Complement Protect (CMP) bit is a non-volatile read/write bit in the status register (b14). It’s used in conjunction with SEC, TB, BP2, BP1, BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. Please refer to table 1 for more details. The factory default setting for CMP is 0.

Note

:

1. When APT is 0, BP2, BP1, BP0 won’t be changed after power-on.

2. When APT is 1 and CMP is 0, all BP2, BP1, BP0 will be set to 1 after power-on.

3. When APT is 1 and CMP is 1, all BP2, BP1, BP0 will be set to 0 after power-on.

(March, 2012, Version 1.3) 15

AMIC Technology Corp.

Figure 5. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

A25L032 Series

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

C

Instruction (05h or 35h)

DI

DO

High Impedance

Status Register 1 or 2 Out Status Register 1 or 2 Out

7

MSB

6 5 4 3 2 1 0 7

MSB

6 5 4 3 2 1 0 7

(March, 2012, Version 1.3) 16

AMIC Technology Corp.

A25L032 Series

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (

S

) Low, followed by the instruction code and the data byte on Serial Data Input (DI).

The instruction sequence is shown in Figure 6. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1,

BP0 (bits 7, 6, 5, 4, 3, 2 of Status Register-1) and CMP,

APT, SRP1 (bits 14, 10 and 8 of Status Register-2) can be written. All other Status Register bits are always read as ‘0’ and will not be affected by the Write Status Register instruction.

Chip Select (

S

) must be driven High after the eighth or sixteenth bit of the data byte has been latched in. If not, the

Write Status Register (WRSR) instruction is not executed.

If Chip Select ( S ) is driven high after the eighth clock the

Figure 6. Write Status Register (WRSR) Instruction Sequence

CMP, QE and SRP1 bits will be cleared to 0.

As soon as Chip Select (

S

) is driven High, the self-timed

Write Status Register cycle (whose duration is t

W

) is initiated.

While the Write Status Register cycle is in progress, the

Status Register may still be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is

0 when it is completed. When the cycle is completed, the

Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (APT, CMP,

SEC, TB, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1. The

Write Status Register (WRSR) instruction also allows the user to set the Status Register Protect (SRP1, SRP0) bits.

Those bits are used in conjunction with the Write Protect

( W ) pin to disable writes to the Status Register. Factory default for all Status Register bits are 0.

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

C

DI

Instruction (01h)

7

MSB

6

Status Register In

5

4 3 2 1

High Impedance

DO

Table 5. Protection Modes

0

15 14 13 12 11 10

9 8

SRP1 SRP0

W

1 1 X

Status Register Description

Status Register is Writable (if the WREN instruction has set the WEL bit). The values in the CMP, APT, SRP1, SRP0, SEC, TB, BP2,

BP1, BP0 bits can be changed.

Status Register is hardware write protected. The values in the CMP,

APT, SRP1, SRP0, SEC, TB, BP2, BP1, BP0 bits cannot be changed.

When

Protection

W pin is high. Status Register is Writable (if the WREN

SRP1, SRP0, SEC, TB, BP2, BP1, BP0 bits can be changed.

One Time Program

Status Register is permanently protected. The values in the CMP,

APT, SRP1, SRP0, SEC, TB, BP2, BP1, BP0 bits cannot be changed.

(March, 2012, Version 1.3) 17

AMIC Technology Corp.

A25L032 Series

Read Data Bytes (READ)

The device is first selected by driving Chip Select (

S

) Low.

The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on

Serial Data Output (DO), each bit being shifted out, at a maximum frequency f

R

, during the falling edge of Serial Clock

(C).

The instruction sequence is shown in Figure 7. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (

S

) High. Chip Select (

S

) can be driven

High at any time during data output. Any Read Data Bytes

(READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 7. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

C

DI

DO

Instruction (03h) 24-Bit Address

23 22 21 3 2 1 0

MSB

High Impedance

7

MSB

Data Out 1

6 5 4 3 2 1 0

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

7

Data Out 2

(March, 2012, Version 1.3) 18

AMIC Technology Corp.

Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (

S

) Low.

The instruction code for the Read Data Bytes at Higher

Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial

Data Output (DO), each bit being shifted out, at a maximum frequency f

C

, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 8. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher

A25L032 Series

Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (

S

) High.

Chip Select (

S

) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 8. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

DI

Instruction (0Bh) 24-Bit Address

23 22 21

MSB

DO

High Impedance

S

C

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy Byte

7 6 5 4 3 2 1 0

DI

DO

Data Out 1

Data Out 2

7 6 5 4 3 2 1

MSB

0

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

7 6 5 4 3 2 1 0

MSB

7

MSB

(March, 2012, Version 1.3) 19

AMIC Technology Corp.

A25L032 Series

Read Data Bytes at Higher Speed by Dual Output (FAST_READ_DUAL_OUTPUT)

The FAST_READ_DUAL_OUTPUT (3Bh) instruction is similar to the FAST_READ (0Bh) instruction except the data is output on two pins, IO

0

and IO

1

, instead of just DO. This allows data to be transferred from the A25L032 at twice the rate of standard SPI devices.

Similar to the FAST_READ instruction, the

FAST_READ_DUAL_OUTPUT instruction can operate at the highest possible frequency of f

C

(See AC Characteristics).

This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in figure 9. The dummy clocks allow the device’s internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO

0

and IO

1

pins should be high-impedance prior to the falling edge of the first data out clock.

Figure 9. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

IO

0

Instruction (3Bh) 24-Bit Address

23 22 21

MSB

High Impedance

IO

1

S

C

IO

0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy Byte

DIO switches from input to output

7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

IO

1

7 5 3 1 7 5 3

MSB

Data Out 1 Data Out 2

1

7 5 3 1 7 5 3 1

MSB

Data Out 3 Data Out 4

7

MSB

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

(March, 2012, Version 1.3) 20

AMIC Technology Corp.

A25L032 Series

Read Data Bytes at Higher Speed by Dual Input and Dual Output (FAST_READ_DUAL_INPUT_OUTPUT)

The FAST_READ_DUAL_INPUT_OUTPUT (BBh) instruction is similar to the FAST_READ (0Bh) instruction except the data is input and output on two pins, IO

0

and IO

1

, instead of just DO. This allows data to be transferred from the A25L032 at twice the rate of standard SPI devices.

Similar to the FAST_READ instruction, the

FAST_READ_DUAL_INPUT_OUTPUT instruction can operate at the highest possible frequency of f

C

(See AC

Characteristics). The FAST_READ_DUAL_INPUT_OUTPUT instruction can further reduce instruction overhead through setting the Mode bits (M7-0) after the input Address bits

(A23-0), as shown in Figure 10-a. The upper nibble of the

Mode (M7-4) bits controls the length of the next

FAST_READ_DUAL_INPUT_OUTPUT instruction through the inclusion or exclusion of the first byte instruction code.

The lower nibble bits of the Mode (M3-0) bits are don’t care

(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the Mode bits (M5-4) equal “10” hex, then the chip is into

“Continuous Read” Mode and the next

FAST_READ_DUAL_INPUT_OUTPUT instruction (after

S is raised and then lowered) does not require the BBh instruction code, as shown in figure 10-b. This reduces the instruction sequence by eight clocks and allows the address to be immediately entered after S is asserted low. If the

Mode bits (M5-4) are any value other than “10” hex, the next instruction (after S is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.

Figure 10-a. FAST_READ_DUAL_INPUT_OUTPUT Instruction Sequence and Data-Out Sequence

(M5-410h)

S

0 1 2 3 4 5 6 7 8 9 10 16 17 18 19

C

IO

0

IO

1

Instruction (BBh)

High Impedance

24-Bit Address

22 20 18

MSB

23 21 19 7 5 3 1

S

C

IO

0

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

M7-0

DIO switches from input to output

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

IO

1

7 5 3 1

7 5 3 1

MSB

Data Out 1

7 5 3 1 7 5 3

MSB

Data Out 2 Data Out 3

1

7 5 3 1 7 5 3 1

MSB

Data Out 4 Data Out 5

7

MSB

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

(March, 2012, Version 1.3) 21

AMIC Technology Corp.

A25L032 Series

Figure 10-b. FAST_READ_DUAL_INPUT_OUTPUT Instruction Sequence and Data-Out Sequence

Continuous Read Mode, (M5-4=10h)

S

C

IO

0

0 1 2 3 4 … 7 8 9 10 11

22 20 18

24-Bit Address

IO

1

23

21 19

7 5 3 1

S

C

IO

0

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

M7-0

DIO switches from input to output

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

IO

1

7 5 3 1

7 5 3 1

MSB

Data Out 1

7 5 3 1 7 5 3

MSB

Data Out 2 Data Out 3

1

7 5 3 1 7 5 3 1

MSB

Data Out 4 Data Out 5

7

MSB

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

(March, 2012, Version 1.3) 22

AMIC Technology Corp.

Read OTP (ROTP)

The device is first selected by driving Chip Select (

S

) Low.

The instruction code for the Read OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte.

Each bit is latched in on the rising edge of Serial Clock (C).

Then the memory contents at that address are shifted out on

Serial Data output (DO).

Each bit is shifted out at the maximum frequency, f

C

(Max.) on the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 11.

The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to

A25L032 Series

000000h, allowing the read sequence to be continued indefinitely.

The Read OTP (ROTP) instruction is terminated by driving

Chip Select (

S

) High. Chip Select (

S

) can be driven High at any time during data output. Any Read OTP (ROTP) instruction issued while an Erase, Program or Write Status

Register cycle is in progress, is rejected without having any effect on the cycle that is in progress.

Figure 11. Read OTP (ROTP) instruction and data-out sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

DI

Instruction

(4Bh or 48h)

24-Bit Address

23 22 21

MSB

High Impedance

DO

S

C

DI

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy Byte

7 6 5 4 3 2

1

0

DO

7 6 5 4 3 2 1

MSB

Data Out 1

0

7 6 5 4 3 2 1 0

MSB

7

MSB

Data Out n

Note: A23 to A6 are don’t care. (1

≤ n ≤ 64)

(March, 2012, Version 1.3) 23

AMIC Technology Corp.

Program OTP (POTP)

The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.

The Program OTP instruction is entered by driving Chip

Select (

S

) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input

(DI).

Chip Select (

S

) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the

Program OTP instruction is not executed.

The instruction sequence is shown in Figure 12.

As soon as Chip Select (

S

) is driven High, the self-timed

Page Program cycle (whose duration is t

PP

) is initiated. While the Program OTP cycle is in progress, the Status Register may be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is

Figure 12. Program OTP (POTP) instruction sequence

S

A25L032 Series

completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.

To lock the OTP memory:

Bit 0 of the OTP control byte, that is byte 63, (see Figure 12) is used to permanently lock the OTP memory array.

• When bit 0 of byte 63 = ’1’, the OTP memory array can be programmed.

• When bit 0 of byte 63 = ‘0’, the OTP memory array are read-only and cannot be programmed anymore.

Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’.

Therefore, as soon as bit 0 of address 63h (control byte) is set to ‘0’, the 64 bytes of the OTP memory array become read-only in a permanent way.

Any Program OTP (POTP) instruction issued while an Erase,

Program or Write Status Register cycle is in progress is rejected without having any effect on the cycle that is in progress.

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

C

DI

Instruction (42h) 24-Bit Address

23 22 21

MSB

7

MSB

Data Byte 1

6 5 04 3 2 1 00

S

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

C

Data Byte 2 Data Byte 3 Data Byte n

DI

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1

MSB

0

7 6 5 4 3 2 1 0

MSB

7

MSB

Note: A23 to A6 are don’t care. (1

≤ n ≤ 64)

Figure 13. How to permanently lock the 64 OTP bytes

64 Data Byte OTP Control Byte

Byte

0

Byte

1

Byte

2

Byte

62

Byte

63

(March, 2012, Version 1.3)

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

When bit 0 =0 the OTP bytes become READ only

24

AMIC Technology Corp.

Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0).

Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the

Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip

Select (

S

) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input

(DI). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits

(A7-A0) are all zero). Chip Select (

S the entire duration of the sequence.

) must be driven Low for

The instruction sequence is shown in Figure 14. If more than

256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be

A25L032 Series

programmed correctly within the same page. If less than 256

Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.

Chip Select (

S

) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page

Program (PP) instruction is not executed.

As soon as Chip Select (

S

) is driven High, the self-timed

Page Program cycle (whose duration is t

PP

) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed

Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write

Enable Latch (WEL) bit is reset.

A Page Program (PP) instruction applied to a page which is protected by the Block Protect (CMP, SEC, TB, BP2, BP1,

BP0) bits (see table 1) is not executed.

Figure 14. Page Program (PP) Instruction Sequence

S

0 1 2 3 4 5 6 7 8 9 10

C

Instruction (02h)

28 29 30 31 32 33 34 35 36 37 38 39

24-Bit Address Data Byte 1

DI

23 22 21

MSB

7 6 5 4 3 2 1 0

MSB

S

C

DI

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Data Byte 2 Data Byte 3 Data Byte 256

7 6 5 4 3 2 1

MSB

0

7 6 5 4 3 2 1 0

MSB

7 6 5 4 3 2 1 0

MSB

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

(March, 2012, Version 1.3) 25

AMIC Technology Corp.

A25L032 Series

Dual Input Fast Program (DIFP)

The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins IO

0

and IO

1

instead of only one.

Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Page Program (PP) instruction.

The Dual Input Fast Program (DIFP) instruction is entered by having any effects on the other bytes in the same page.

For optimized timings, it is recommended to use the Dual

Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Dual Input Fast Program (DIFP) sequences each containing only a few bytes.

Chip Select (

S

) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Dual

Input Fast Program (DIFP) instruction is not executed. driving Chip Select (

S

) Low, followed by the instruction code, three address bytes and at least one data byte on Serial

Data Output (IO

0

and IO

1

).

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (

S

) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without

As soon as Chip Select (

S

) is driven High, the self-timed

Page Program cycle (whose duration is t

PP

) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress, the

Status Register may be read to check the value of the Write

In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the Block Protect (CMP, SEC, TB,

BP2, BP1, BP0) bits (see Table 1) is not executed.

Figure 15. Dual Input Fast Program (DIFP) instruction sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

IO

0

Instruction (A2h)

23 22 21

MSB

24-Bit Address

3 2 1 00

High Impedance

IO

1

S

C

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

IO

0

IO

1

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Data In 1 Data In 2 Data In 3 Data In 4 Data In 5

7

MSB

5 3 1 7 5

MSB

3 1 7 5 3 1 7 5 3 1 7 5 3 1

MSB MSB MSB

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

6 4 2 0

Data In 256

7 5 3 1

MSB

(March, 2012, Version 1.3) 26

AMIC Technology Corp.

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write

Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip

Select (

S

) Low, followed by the instruction code on Serial

Data Input (DI). Chip Select (

S

) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 16. Chip Select

(

S

) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Sector Erase

Figure 16. Sector Erase (SE) Instruction Sequence

S

A25L032 Series

instruction is not executed. As soon as Chip Select (

S

) is driven High, the self-timed Sector Erase cycle (whose duration is t

SE

) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Sector Erase cycle, and is

0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (CMP, SEC, TB, BP2, BP1,

BP0) bits (see table 1) is not executed.

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

DI

Instruction (20h)

22 21

MSB

24-Bit Address

3 2 1 00

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

(March, 2012, Version 1.3) 27

AMIC Technology Corp.

Block Erase (BE)

The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Block Erase (BE) instruction is entered by driving Chip

Select (

S

) Low, followed by the instruction code on Serial

Data Input (DI). Chip Select (

S

) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 17. Chip Select

(

S

) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Block Erase

Figure 17. Block Erase (BE) Instruction Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

A25L032 Series

instruction is not executed. As soon as Chip Select (

S

) is driven High, the self-timed Block Erase cycle (whose duration is t

BE

) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Block Erase (BE) instruction applied to a page which is protected by the Block Protect (CMP, SEC, TB, BP2, BP1,

BP0) bits (see table 1) is not executed.

C

DI

24-Bit Address

Instruction (D8h or 52h)

22 21

MSB

3 2 1 00

Note: Address bits A23 to A22 are Don’t Care, for A25L032.

(March, 2012, Version 1.3) 28

AMIC Technology Corp.

Chip Erase (CE)

The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the

Write Enable Latch (WEL).

The Chip Erase (CE) instruction is entered by driving Chip

Select (

S

) Low, followed by the instruction code on Serial

Data Input (DI). Chip Select (

S

) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 18. Chip Select

(

S

) must be driven High after the eighth bit of the instruction

Figure 18. Chip Erase (CE) Instruction Sequence

S

0 1 2 3 4 5 6 7

A25L032 Series

code has been latched in, otherwise the Chip Erase instruction is not executed. As soon as Chip Select (

S

) is driven High, the self-timed Chip Erase cycle (whose duration is t

CE

) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is

1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Chip Erase (CE) instruction is ignored if one, or more, sectors/blocks are protected.

C

Instruction

(C7h or 60h)

DI

(March, 2012, Version 1.3) 29

AMIC Technology Corp.

A25L032 Series

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the

Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write,

Program and Erase instructions.

Driving Chip Select (

S

) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep

Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from I

CC1

DC Characteristics Table.).

to I

CC2

, as specified in

The Deep Power-down mode automatically stops at

Power-down, and the device always Powers-up in the

Standby mode.

The Deep Power-down (DP) instruction is entered by driving

Chip Select (

S

) Low, followed by the instruction code on

Serial Data Input (DI). Chip Select (

S

) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 19.

Chip Select (

S

) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep

Power-down (DP) instruction is not executed. As soon as

Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep

Power-down and Read Electronic Signature (RES) instruction.

This releases the device from this mode. The Release from

Deep Power-down and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the device to be output on Serial Data Output (DO).

Figure 19. Deep Power-down (DP) Instruction Sequence

Chip Select (

S

) is driven High, it requires a delay of t

DP before the supply current is reduced to I

CC2

Power-down mode is entered.

and the Deep

Any Deep Power-down (DP) instruction, while an Erase,

Program or Write Status Register cycle is in progress, is rejected without having any effects on the cycle that is in progress.

S t

DP

0

1 2 3 4 5 6 7

C

Instruction (B9h)

DI

Stand-by Mode Deep Power-down Mode

(March, 2012, Version 1.3) 30

AMIC Technology Corp.

A25L032 Series

Read Device Identification (RDID)

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 37h. The device identification is assigned by the device manufacturer, and indicates the memory in the first byte (30h), and the memory capacity of the device in the second byte (16h for A25L032).

Any Read Identification (RDID) instruction while an Erase, or

Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.

This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (DO), each bit being shifted out during the falling edge of Serial

Clock (C).

The instruction sequence is shown in Figure 20. The Read

Identification (RDID) instruction is terminated by driving Chip

Select (

S

) High at any time during data output.

The device is first selected by driving Chip Select (

S

) Low.

Then, the 8-bit instruction code for the instruction is shifted in.

Table 6. Read Identification (READ_ID) Data-Out Sequence

When Chip Select (

S

) is driven High, the device is put in the

Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

Manufacture Identification

Manufacture ID Memory Type

Device Identification

37h 30h

Memory Capacity

Figure 20. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

S

0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 21 22 23 24 25 26 29 30 31

C

Instruction (9Fh)

DI

DO

High Impedance

23 22 21 18 17 16 15 14 13

Manufacture ID

10

9

8 7 6 5

Memory Type

2 1 0

Memory Capacity

(March, 2012, Version 1.3) 31

AMIC Technology Corp.

A25L032 Series

Read Electronic Manufacturer ID & Device ID (REMS)

The Read Electronic Manufacturer ID & Device ID (REMS) instruction allows the 8-bit manufacturer identification code to be read, followed by one byte of device identification. The manufacturer identification is assigned by JEDEC, and has the value 37h for AMIC. The device identification is assigned by the device manufacturer, and has the value 15h for

A25L032.

Any Read Electronic Manufacturer ID & Device ID (REMS) instruction while an Erase, or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.

The device is first selected by driving Chip Select (

S

) Low.

The 8-bit instruction code is followed by 2 dummy bytes and one byte address (A7~A0), each bit being latched-in on Serial

Data Input (DI) during the rising edge of Serial Clock (C).

If the one-byte address is set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. On the other hand, if the one-byte address is set to 00h, then the

Manufacturer ID will be read first and then followed by the device ID.

The instruction sequence is shown in Figure 21. The Read

Electronic Manufacturer ID & Device ID (REMS) instruction is terminated by driving Chip Select ( data output.

S

) High at any time during

When Chip Select (

S

) is driven High, the device is put in the

Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

Table 7. Read Electronic Manufacturer ID & Device ID (REMS) Data-Out Sequence

Manufacture Identification Device Identification

Figure 21. Read Electronic Manufacturer ID & Device ID (REMS) Instruction Sequence and Data-Out Sequence

S

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23

C

DI

Instruction (90h) 2 Dummy Bytes

15 14 13

MSB

DO

High Impedance

S

C

DI

DO

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

ADD

(1)

7 6 5 4 3 2

1

0

Manufacturer ID

7 6 5 4 3 2 1

MSB

Device ID

0

7 6 5 4 3 2 1 0

MSB MSB

Notes:

(1) ADD=00h will output the manufacturer ID first and ADD=01h will output device ID first

(March, 2012, Version 1.3) 32

AMIC Technology Corp.

Release from Deep Power-down and Read Electronic Signature (RES)

A25L032 Series

Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep

Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode.

The instruction can also be used to read, on Serial Data

Output (DO), the 8-bit Electronic Signature, whose value for

A25L032 is 15h.

Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and

Read Electronic Signature (RES) instruction always provides access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered.

Any Release from Deep Power-down and Read Electronic

Signature (RES) instruction while an Erase, Program or Write

Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. stored in the memory, is shifted out on Serial Data Output

(DO), each bit being shifted out during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 22.

The Release from Deep Power-down and Read Electronic

Signature (RES) instruction is terminated by driving Chip

Select (

S

) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial Clock

(C), while Chip Select (

S

) is driven Low, cause the

Electronic Signature to be output repeatedly.

When Chip Select (

S

) is driven High, the device is put in the

Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by

Power mode is immediate. If the device was previously in the

Deep Power-down mode, though, the transition to the Standby Power mode is delayed by t

RES2

, and Chip Select (

S

) must remain High for at least t

RES2

(max), as specified in AC

Characteristics Table . Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

The device is first selected by driving Chip Select (

S

) Low.

The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (DI) during the rising edge of Serial Clock (C). Then, the 8-bit Electronic Signature,

Figure 22. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and

Data-Out Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38

C

DI

DO

Instruction (ABh)

23 22 21

MSB

3 Dummy Bytes

3 2 1 0

High Impedance

7 6 5 4 3 2 1 0

MSB

Deep Power-down Mode

Note: The value of the 8-bit Electronic Signature, for A25L032 is 15h. t

RES2

Stand-by Mode

(March, 2012, Version 1.3) 33

AMIC Technology Corp.

Figure 23. Release from Deep Power-down (RES) Instruction Sequence

S t

RES1

0 1 2 3 4 5 6 7

C

Instruction (ABh)

DI

A25L032 Series

High Impedance

DO

Deep Power-down Mode Stand-by Mode

Driving Chip Select (

S

) High after the 8-bit instruction byte has been received by the device, but before the whole of the

8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 23.), still insures that the device is put into Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the

Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by t

RES1

, and Chip Select (

S

) must remain High for at least t

RES1

(max), as specified in AC Characteristics Table. Once in the

Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

(March, 2012, Version 1.3) 34

AMIC Technology Corp.

High Performance Mode (A3h)

A25L032 Series

The High Performance Mode (HPM) instruction can be executed prior to Dual instructions if chip is operated at high frequencies. This instruction allows pre-charging of internal charge pumps so the voltages required for accessing the

Flash memory array are readily available. The instruction sequence includes the A3h instruction code followed by three dummy byte clocks shown in Fig.28. After the HPM

Figure 24. High Performance Mode Instruction Sequence

S instruction is executed, the device will maintain a slightly higher standby current than standard SPI operation. The

Release from Power-down (ABh) can be used to return to standard SPI standby current (I

CC1

). In addition, Write Enable instruction (06h) and Power Down instruction (B9h) will also release the device from HPM mode back to standard SPI standby state.

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

DIO

Instruction (A3) 3 Dummy Bytes

23 22 21

MSB

3 2 1 00 t

RES2

DO

High Performance

Current

(March, 2012, Version 1.3) 35

AMIC Technology Corp.

A25L032 Series

Continuous Read Mode Reset (FFFFh)

Continuous Read Mode Reset instruction can be used to set mode bit M4 to 1, thus the device will release the Continuous

Read Mode and return to normal SPI operation, as shown in

Fig.29.

If user wants to issue a new command after A25L032 is set to Continuous Mode Read, it is recommended to issue a

Continuous Read Mode Reset instruction before any command. Doing so will release the device from the

Continuous Read Mode and allow Standard SPI instructions to be recognized.

To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh”.

Mode bit M5, M4 will be reset to 0 after power-on, so it’s unnecessary to issue Continuous Read Mode Reset instruction even the controller resets while A25L032 is set to

Continuous Mode Read.

Figure 25. Continuous Read Mode Reset for Fast Read Dual I/O

Mode Bit Reset for Dual I/O

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

C

FFh FFh

I/O

0

I/O

1

I/O

2

I/O

3

Do not care

Do not care

Do not care

(March, 2012, Version 1.3) 36

AMIC Technology Corp.

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must not be selected (that is Chip Select (

S

) must follow the voltage applied on V

CC

) until V

CC

reaches the correct value:

­

V

CC

(min) at Power-up, and then for a further delay of t

VSL

­

V

SS

at Power-down

Usually a simple pull-up resistor on Chip Select (

S

) can be used to insure safe and proper Power-up and Power-down.

To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included.

The logic inside the device is held reset while V the POR threshold value, V

WI

CC

is less than

– all operations are disabled, and the device does not respond to any instruction.

Moreover, the device ignores all Write Enable (WREN),

Program OTP (POTP), Page Program (PP), Dual Input Fast

Program (DIFP), Sector Erase (SE), Block Erase (BE), Chip

Erase (CE) and Write Status Register (WRSR) instructions until a time delay of t

PUW

has elapsed after the moment that

V

CC

rises above the V

WI

threshold. However, the correct operation of the device is not guaranteed if, by this time, V

CC is still below V

CC

(min). No Write Status Register, Program or

Erase instructions should be sent until the later of:

Figure 26. Power-up Timing

V

CC

A25L032 Series

­ t

PUW

- t

VSL

after V

afterV

CC

passed the V

CC

passed the V

WI

threshold

These values are specified in Table 8.

If the delay, t

VSL

CC

(min) level

, has elapsed, after V

CC

has risen above

V

CC

(min), the device can be selected for Read instructions even if the t

PUW

delay is not yet fully elapsed.

At Power-up, the device is in the following state:

­

The device is in the Standby mode (not the Deep

Power-down mode).

­

The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the V

CC

feed. Each device in a system should have the V

CC

rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of

0.1µF).

At Power-down, when V

CC

drops from the operating voltage, to below the POR threshold value, V , all operations are

WI disabled and the device does not respond to any instruction.

(The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)

V

CC

(max)

V

CC

(min)

Reset

State

V

WI t

VSL

Read

Access allowed t

PUW

Full Device Access time

(March, 2012, Version 1.3) 37

AMIC Technology Corp.

Table 8. Power-Up Timing

A25L032 Series

Symbol

t

VSL

t

PUW

V

WI

Parameter

V

CC(min)

to S Low

Time Delay Before Write Instruction

Write Inhibit Threshold Voltage

Min.

10

3

2.3

Max.

2.5

Unit

μ s ms

V

Note: These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains

00h (all Status Register bits are 0).

(March, 2012, Version 1.3) 38

AMIC Technology Corp.

Absolute Maximum Ratings*

Storage Temperature (TSTG) . . . . . . . . . . -65

°C to + 150°C

Lead Temperature during Soldering (Note 1)

D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to V

CC

+0.6V

Transient Voltage (<20ns) on Any Pin to Ground Potential . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V

CC

+2.0V

Supply Voltage (V

CC

) . . . . . . . . . . . . . . . . . . -0.6V to +4.0V

Electrostatic Discharge Voltage (Human Body model)

(VESD) (Note 2) . . . . . . . . . . . . . . . . . . . -2000V to 2000V

Notes:

1. Compliant with JEDEC Std J-STD-020B (for small body,

Sn-Pb or Pb assembly).

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500Ω ,

R2=500Ω)

DC AND AC PARAMETERS

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device.

The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the

Table 9. Operating Conditions

Symbol Parameter

A25L032 Series

*Comments

Stressing the device above the rating listed in the Absolute

Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the AMIC SURE Program and other relevant quality documents.

Measurement Conditions summarized in the relevant tables.

Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.

V

CC

T

A

Ambient Operating Temperature

Table 10. Data Retention and Endurance

Parameter

Erase/Program Cycles At 85°C

Condition Min.

100,000

Data Retention

Table 11. Capacitance

At 85°C 20

Symbol Parameter Test Condition

C

OUT

Output Capacitance (DO) V

OUT

= 0V

C

IN

Input Capacitance (other pins) V

IN

= 0V

Note: Sampled only, not 100% tested, at T

A

=25°C and a frequency of 33 MHz.

Min.

2.7

–40

Min.

Max.

Max.

3.6

85

Max.

8

6

Unit

V

°C

Unit

Cycles

Years

Unit

pF pF

(March, 2012, Version 1.3) 39

AMIC Technology Corp.

A25L032 Series

Table 12. DC Characteristics

Symbol Parameter Test Condition Min.

Max.

Unit

I

CC4

I

CC5

I

CC6

I

CC7

V

IL

V

IH

I

LI

Input Leakage Current

I

LO

Output Leakage Current

I

I

CC1

Standby

CC2

Deep Power-down Current

I

CC3

Operating Current (Read)

S

= V

CC

, V

IN

= V

SS

or V

CC

S

= V

CC

, V

IN

= V

SS

or V

CC

C= 0.1V

CC

/ 0.9.V

CC

at 100MHz, DO = open

C= 0.1V

CC

/ 0.9.V

CC

at 50MHz, DO = open

C= 0.1V

CC

/ 0.9.V

CC

at 33MHz, DO = open

Operating Current (Dual Read) C= 0.1V

CC

/ 0.9.V

CC

at 100MHz, IO

0

, IO

1

= open

Operating Current (PP)

Operating Current (WRSR)

Operating Current (SE)

Operating Current (BE)

Input Low Voltage

S

= V

S

= V

CC

S

= V

CC

S

= V

CC

CC

Input High Voltage

V

OL

Output Low Voltage

V

OH

Output High Voltage

Note: 1. This is preliminary data at 85°C

Table 13. AC Measurement Conditions

I

OL

= 1.6mA

I

OH

= –100µA

Symbol Parameter Min.

C

L

Input Rise and Fall Times

± 2

± 2

24

21

17

26

µA

µA mA mA mA mA

–0.5 0.3V

CC

0.7V

CC

V

CC

+0.4

V

V

0.4 V

V

CC

–0.2 V

Max.

30

5

Unit

pF ns

Input Pulse Voltages 0.2V

CC

to 0.8V

CC

V

Input Timing Reference Voltages

Output Timing Reference Voltages

0.3V

CC

to 0.7V

CC

V

V

CC

/ 2

Note: Output Hi-Z is defined as the point where data out is no longer driven.

Figure 27. AC Measurement I/O Waveform

Input Levels Input and Output

Timing Reference Levels

V

0.8V

CC

0.2V

CC

0.7V

CC

0.5V

CC

0.3V

CC

(March, 2012, Version 1.3) 40

AMIC Technology Corp.

A25L032 Series

Table 14. AC Characteristics

Symbol

f

C f

R t

CH

1

t

CL

1

t

CLCH

2

t

CHCL

2

t

SLCH t

CHSL t

DVCH t

CHDX t

CHSH t

SHCH t

SHSL

Alt.

f

C t

CLH t

CLL t

CSS t

DSU t

DH t

CSH

Parameter

Clock Frequency for all instructions, except READ (03h)

Clock Frequency for READ (03h) instruction

Clock High Time

Clock Low Time

Clock Rise Time

3

(peak to peak)

Clock Fall Time

3

(peak to peak)

S

Active Setup Time (relative to C)

S

Not Active Hold Time (relative to C)

Data In Setup Time

Data In Hold Time

S

Active Hold Time (relative to C)

S

Not Active Setup Time (relative to C)

S

Deselect Time

Min.

Typ.

Max.

Unit

D.C.

D.C.

100

65

MHz

MHz

5

5 ns ns

0.1 V/ns

0.1 V/ns

5 ns

5 ns

3

3 ns ns

5 ns

5 ns

30 ns t

SHQZ

2

t

CLQV t

CLQX t

HLCH t

CHHH t

HHCH t

CHHL t

HHQX

2

t

HLQZ

2

t

WHSL

4

t

SHWL

4

t

DP

2

t

RES1

2

t

RES2

2

t t

W pp t

SE t

BE t

CE t

LZ t

HZ t

DIS t

V t

HO

Clock Low to Output Valid

Output Hold Time

HOLD Setup Time (relative to C)

HOLD

Hold Time (relative to C)

HOLD Setup Time (relative to C)

HOLD Hold Time (relative to C)

HOLD to Output Low-Z

HOLD to Output High-Z

Write Protect Setup Time

Write Protect Hold Time

S

High to Deep Power-down Mode

S

High to Standby Mode without Electronic Signature Read

S

High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

Page Program Cycle Time

Program OTP Cycle Time

Sector Erase Cycle Time

Block Erase Cycle Time

Chip Erase Cycle Time of A25L032

0

7

7 ns ns ns

5 ns

5 ns

5

5

20

100

5

2

2

80

0.5

32

7 ns ns ns ns ns

1 µs

20

6

3

200

2

64

Note: 1. t

CH

+ t

CL

must be greater than or equal to 1/ f

C

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for WRSR instruction when Status Register Protect bits (SRP1, SRP0) = (0, 1) ms ms ms ms s s

(March, 2012, Version 1.3) 41

AMIC Technology Corp.

Figure 28. Serial Input Timing

A25L032 Series

S tCHSL

C tDVCH

DI tSLCH

MSB IN tCHDX tCHSH tCLCH

LSB IN tSHSL tSHCH tCHCL

High Impedance

DO

Figure 29. Write Protect Setup and Hold Timing during WRSR when (SRP1, SRP0) = (0, 1)

W tWHSL tSHWL

S

C

DI

DO

High Impedance

(March, 2012, Version 1.3) 42

AMIC Technology Corp.

Figure 30.

Hold Timing

S

C

DI

DO

HOLD

Figure 31. Output Timing

S

C

DI

ADDR.LSB IN tCLQV tCLQX

DO tCLQX tCLQV tCHHL tHLQZ tHLCH tCHHH tHHCH tHHQX tCH

A25L032 Series

tCL tQLQH tQHQL

LSB OUT tSHQZ

(March, 2012, Version 1.3) 43

AMIC Technology Corp.

Part Numbering Scheme

A25 X X

XXX

X

X X X

/ X

A25L032 Series

Packing

Blank: for DIP8

G: for SOP8 In Tube

Q: for Tape & Reel

Package Material

Blank: normal

F: PB free

Temperature*

Package Type

Blank = DIP8

M = 209 mil SOP 8

N = 300 mil SOP 16

Q4 = WSON 8 (6*5mm)

Device Version*

Device Density

512 = 512 Kbit (4KB uniform sectors)

010 = 1 Mbit (4KB uniform sectors)

020 = 2 Mbit (4KB uniform sectors)

040 = 4 Mbit (4KB uniform sectors)

080 = 8 Mbit (4KB uniform sectors)

016 = 16 Mbit (4KB uniform sectors)

032 = 32 Mbit (4KB uniform sectors)

Quad SPI Operation

Q = Support Quad SPI Operation

Blank = Do not support Quad SPI Operation

Device Voltage

L = 2.7-3.6V

Device Type

A25 = AMIC Serial Flash

* Optional

(March, 2012, Version 1.3) 44

AMIC Technology Corp.

Ordering Information

Part No. Speed (MHz) Active Read

Current

Max. (mA)

Program/Erase

Current

Max. (mA)

Standby

Current

Max. (μA)

A25L032-F

A25L032-UF

A25L032M-F

A25L032M-UF

A25L032N-F

A25L032N-UF

100 24 15

A25L032Q4-F

A25L032 Series

Package

8 Pin Pb-Free DIP (300 mil)

8 Pin Pb-Free DIP (300 mil)

8 Pin Pb-Free SOP (209mil)

8 Pin Pb-Free SOP (209mil)

16 Pin Pb-Free SOP (300mil)

8 Pin Pb-Free WSON (6*5mm)

Operating temperature range:

-40°C ~ +85°C

-U is for industrial operating temperature range: -40°C ~ +85°C

(March, 2012, Version 1.3) 45

AMIC Technology Corp.

Package Information

P-DIP 8L Outline Dimensions

A25L032 Series

unit: inches/mm

Symbol

Dimensions in inches

Min Nom

Dimensions in mm

Max Min Nom Max

A

1

0.015

A

2

0.128

0.130

0.136

B 0.014

B

1

0.050

B

2

0.032

C 0.008

D 0.350

0.018

0.060

0.039

0.010

0.360

0.022

0.070

0.046

0.013

0.370

E 0.290

E

1

0.254

0.300

0.260

e

1

- 0.100

L 0.125

E

A

0.345

S 0.016

0.315

0.266

- - 2.54 -

- 0.385

0.021

0.026

8.76 - 9.78

Notes:

1. Dimension D and E

1

do not include mold flash or protrusions.

2. Dimension B

1

does not include dambar protrusion.

3. Tolerance: ±0.010” (0.25mm) unless otherwise specified.

(March, 2012, Version 1.3) 46

AMIC Technology Corp.

Package Information

SOP 8L (209mil) Outline Dimensions

8 5

1

4

C

D e b

GAGE PLANE

SEATING PLANE

θ

L

Symbol

Dimensions in mm

Min Nom Max

A

1.75 1.95 2.16

A

1

0.05 0.15 0.25

A

2

1.70 1.80 1.91

C 0.19 0.20 0.25

D

5.13

5.23 5.33

E

1

5.18 5.28 5.38

θ 0° - 8°

Notes:

Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads

A25L032 Series

unit: mm

(March, 2012, Version 1.3) 47

AMIC Technology Corp.

Package Information

SOP 16L (300mil) Outline Dimensions

D

16

9

C o

1 b e

8

0.10

C

SEATING PLANE

θ

L

Symbol

A

A

1

b

C

Dimensions in inch Dimensions in mm

Min Max Min Max

0.093

0.104 2.36 2.65

0.004 0.012 0.10 0.30

0.016 Typ.

0.008 Typ.

0.41 Typ.

0.20 Typ. e 0.050 Typ. 1.27 Typ.

θ 0° 8° 0° 8°

Notes:

1. Dimensions “D” does not include mold flash, protrusions or gate burrs.

2. Dimensions “E” does not include interlead flash, or protrusions.

A25L032 Series

unit: inches/mm

(March, 2012, Version 1.3) 48

AMIC Technology Corp.

Package Information

WSON 8L (6 X 5 X 0.8mm) Outline Dimensions

4 1

0.25 C

A25L032 Series

unit: mm/mil

1 e

2 3 b

4

C0.30

Pin1 ID Area

5

E

8

8 7

E

2

6 5

// 0.10

C y C

Seating Plane

Symbol

Dimensions in mm

Min Nom Max

A 0.700

0.750

0.800

A

1

0.000

0.020

0.050

A

3

0.203 REF

Dimensions in mil

Min Nom

27.6

29.5

31.5

0.0 0.8 2.0

8.0 REF

Max b 0.350

0.400

0.480

13.8

15.8

18.9

D 5.900

6.000

6.100

232.3

236.2

240.2

D

2

3.200

3.400

3.600

126.0

133.9

141.7

E 4.900

5.000

5.100

192.9

196.9

200.8

E

2

3.800

4.000

4.200

149.6

157.5

165.4

L 0.500

0.600

0.750

19.7

23.6

29.5

e

1.270 BSC 50.0 BSC

0 - 3.2

Note:

1. Controlling dimension: millimeters

2. Leadframe thickness is 0.203mm (8mil)

(March, 2012, Version 1.3) 49

AMIC Technology Corp.

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