Specification BT45213 BTHQ128064AVD1-SRE-12-COG Doc. No.: COG-BTD12864-40

Specification BT45213 BTHQ128064AVD1-SRE-12-COG Doc. No.: COG-BTD12864-40

Specification

BT45213

BTHQ128064AVD1-SRE-12-COG

Doc. No.: COG-BTD12864-40

Version October 2010

Data Modul AG - www.data-modul.com

DOCUMENT REVISION HISTORY:

DOCUMENT

REVISION

FROM TO

A

DATE DESCRIPTION

2010.10.11

First Release.

Based on: a.) VL-QUA-012B REV.Y

2010.12.10

According to VL-QUA-012B,

LCD size is small because Unit

Per Laminate=24 which is more than 6pcs/Laminate.

CHANGED

BY

CHECKED

BY

LI WEI CHI SHAO

BO

2

5.4

5.5

6.

6.1

6.2

4.2

5.

5.1

5.2

5.3

1.

2.

3.

4.

4.1

7.

8.

CONTENTS

GENERAL DESCRIPTION

MECHANICAL SPECIFICATIONS

INTERFACE SIGNALS

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL MAXIMUM RATINGS – FOR IC ONLY

ENVIRONMENTAL CONDITION

ELECTRICAL SPECIFICATIONS

TYPICAL ELECTRICAL CHARACTERISTICS

TIMING SPECIFICATIONS

COMMAND TABLE

INITIAL CODE SETTING (FOR REFERENCE ONLY)

REFERENCE CIRCUIT

ELECTRO-OPTICAL CHARACTERISTICS

ISO PLOT

OPTICAL CHARACTERISTICS DEFINITION

LCD COSMETIC CONDITIONS

REMARK

16

16

17

17

18

10

11

11

12

15

Page No.

4

4

7

9

9

19

19

3

Specification of

LCD Module Type

Model No.: COG-BTD12864-40

1. General Description

128 x 64 Dots STN Positive Yellow Reflective Dot Matrix LCD Module.

Viewing Angle: 12 o’clock direction.

Driving duty: 1/65 Duty, 1/7 bias.

‘SITRONIX’ ST7565P (COG) LCD controller/Driver or equivalent.

Logic voltage: 3.3V.

FPC connection.

“RoHS” compliance.

2. Mechanical Specifications

The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.

Parameter

Outline dimensions

Viewing area

Active area

Display format

Dot size

Dot spacing

Dot pitch

Weight

Table 1

Specifications

55.6(W) x 70.2(H) x 4.48(D) (Included FPC. Exclude terminals of backlight)

50.60(W) x 31.0(H)

46.577(W) x 27.697(H)

128(W) x 64(H)

0.349(W) x 0.418(H)

0.015(W) x 0.015(H)

0.364(W) x 0.433(H)

Approx: 9

Unit mm mm mm dots mm mm mm grams

4

Figure 1: Module Specification

5

32

COG-BTD12864-40

LCD GRAPHIC DISPLAY

128X64 DOTS

32

RES

CS1

D/C

R/W(WR)

E(RD)

D7~D0

VDD

VSS

VOUT

C3+

C1+

C1-

C2-

C2+

V0

V1

V2

V3

V4

C86

P/S

8

LCD DRIVER &

CONTROLLER

"SITIRONIX"

ST7565P

Figure2: Block Diagram.

6

3. Interface signals

Table 2(a): Pin Assignment

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Symbol

P/S

C86

V0

V1

V2

V3

V4

Description

This pin configures the interface to be parallel mode or serial mode.

P/S = “H”: Parallel data input/output.

P/S = “L”: Serial data input.

The following applies depending on the P/S status:

P/S Data/Command

“H” D/C

Data

D0 to D7

Read/Write

_____ _____

RD , WR

Serial Clock

X

“L” D/C D7 Write only D6

When P/S = “L”, D0 to D5 must be fixed to “H”.

_____ _______

RD (E) and WR (R/W) are fixed to either “H” or “L”.

The serial access mode does NOT support read operation.

This is the MPU interface selection pin.

C86 = “H”: 6800 Series MPU interface.

C86 = “L”: 8080 Series MPU interface.

This is a multi-level power supply for the liquid crystal drive. The voltage supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VSS, and must maintain the relative magnitudes shown below.

V0≧V1≧V2≧V3≧V4≧VSS

When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command.

For 1/7 bias: V1= 6/7 * V0, V2=5/7 * V0, V3=2/7 *V0, V4=1/7 * V0.

C2-

C2+

C1+

C1-

DC/DC voltage converter. Connect a capacitor between this terminal and the

CAP2P terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the

CAP2N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the

CAP1N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and the

CAP1P terminal.

C3+

VOUT

DC/DC voltage converter. Connect a capacitor between this terminal and the

CAP1N terminal.

DC/DC voltage converter. Connect a capacitor between this terminal and VSS or VDD.

VSS Ground.

VDD Power supply pins for logic.

7

Table 2(b): Pin Assignment

Description Pin No.

Symbol

16

17

D7

D6

18

19

D5

D4

20

21

22

23

D3

D2

D1

D0

24

25

26

27

28

This is an 8-bit bi-directional data bus that connects to an 8-bit standard MPU data bus.

When the serial interface is selected (P/S = LOW), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL).

At this time, D0 to D5 are set to high impedance.

When the chip select is inactive, D0 to D7 are set to high impedance.

_____

E(RD )

_____

R/W(WR )

D/C

_______

CS1

_______

RES

______

When connected to 8080 series MPU, this pin is treated as the “RD ” signal of the 8080 MPU and is LOW-active.

The data bus is in an output status when this signal is “L”.

When connected to 6800 series MPU, this pin is treated as the “E” signal of the

6800 MPU and is HIGH-active.

This is the enable clock input terminal of the 6800 Series MPU.

______

When connected to 8080 series MPU, this pin is treated as the “WR ” signal of the 8080 MPU and is LOW-active.

______

The signals on the data bus are latched at the rising edge of the WR signal.

When connected to 6800 series MPU, this pin is treated as the “R/W” signal of the 6800 MPU and decides the access type :

When R/W = “H”: Read.

When R/W = “L”: Write.

This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or command.

D/C = “H”: Indicates that D0 to D7 are display data.

D/C= “L”: Indicates that D0 to D7 are control data.

This is the chip select signal. When /CS1 = “L”, then the chip select becomes active, and data/command I/O is enabled.

________

When RES is set to “L”, the register settings are initialized (cleared).

The reset operation is performed by the /RES signal level.

8

4. Absolute Maximum Ratings

4.1 Electrical Maximum Ratings – for IC Only

Table 3

Parameter

Power Supply voltage (Logic)

Power Supply voltage (VDD2)

Power Supply voltage (V0, VOUT)

Power Supply voltage (V1, V2, V3, V4)

Note:

Symbol

VDD

VDD2

V0, VOUT

V1, V2, V3, V4

Min.

+0.3

+0.3

Max.

+3.6

+3.6

+0.3 +14.5

V0 +0.3

1. The VDD2, V0 to V4 and VOUT are relative to the VSS = 0V reference.

2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that

VOUT ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4.

3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum

Unit

V

V

V

V ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well.

Figure 3

9

4.2 Environmental Condition

Table 4

Humidity

Item

Ambient Temperature

(Note 1)

Vibration (IEC 68 -2-6) cells must be mounted on a suitable connector

Shock (IEC 68

Half

-2-27)

-sine pulse shape

Operating

Temperature

(Topr)

Storage

Temperature

(Tstg)

(Note 1)

Remark

Min. Max. Min. Max.

0

°

C +50

°

C

90% max. RH for Ta

40

°

C

-20

°

C +65

°

< 50% RH for 40

°

C < Ta

Maximum operating

C

Dry

No condensation temperature

Frequency: 10

55 Hz

Amplitude: 0.75 mm

Duration: 20 cycles in each direction.

3 directions

Pulse duration: 11 ms

Peak acceleration: 981 m/s

2

= 100g

Number of shocks: 3 shocks in 3 mutually perpendicular axes.

3 directions

Note 1: Product cannot sustain at extreme storage conditions for long time.

10

5. Electrical Specifications

5.1 Typical Electrical Characteristics

At Ta = +25

°°°°

C, VDD = +3.3

±±±±

5%, VSS = 0V.

Table 5

Parameter

Supply voltage

(Logic)

Supply voltage

(LCD) (built-in)

Symbol

VDD-VSS

VLCD

=V0-VSS

Conditions

Ta = 0

°

C,

Character mode

VDD = +3.3V, Note 1

Ta = 25

°

C,

Character mode

VDD = +3.3V, Note 1

Ta = 50

°

C,

Character mode

VDD = +3.3V, Note 1

Note 2

Min.

3.14

-

8.6

-

Typ.

3.3

8.9

8.8

8.6

Max.

3.47

-

9.0

-

Unit

V

V

V

V

Low-level input signal voltage

High-level input signal voltage

Supply Current

(Logic & LCD)

V

V

ILC

IHC

IDD

Note 2

VDD = +3.3V,Note 1,

Character mode

VDD = +3.3V,Note 1,

Checker board mode

VSS

0.8xVDD

-

-

-

-

0.46

0.78

0.2xVDD

VDD

0.69

1.2

Note 1: There is tolerance in optimum LCD driving voltage during production and it will be

V

V mA mA within the specified range.

______

Note 2: D/C, D0 to D5, D6, D7, E(RD

_______ ______ _______

),R/W(WR ),CS1 ,C86,P/S,RES terminals.

Note 3: Do not display a fixed pattern for more than 30 min. because it may cause image sticking due to

LCD characteristics. It is recommended to change display pattern frequently. If customer must fix display pattern on the screen, please consider to activate screen saver.

11

5.2 Timing Specifications

System Bus read/Write Characteristics 1 (For the 8080 Series MPU)

At Ta = 0

°°°°

C to +50

°°°°

C, VDD = +3.3V

±±±±

5%, VSS = 0V.

Table 6

Figure 4: The timing diagram of system bus read/write (For the 8080 Series MPU)

12

System Bus read/Write Characteristics 2 (For the 6800 Series MPU)

At Ta =0

°°°°

C to +50

°°°°

C, VDD = +3.3V

±±±±

5%, VSS = 0V.

Table 7

Figure 5: The timing diagram of system bus read/write (For the 6800 Series MPU)

13

Reset Timing

At Ta =0

°°°°

C to +50

°°°°

C, VDD = +3.3V

±±±±

5%, VSS = 0V.

Table 8

Figure 6: Reset Timing

14

5.3. Command Table

Table 9

15

5.4 Initial code setting (for reference only)

Table 10

Description

Reset

LCD bias set

ADC select

Common output mode select

V5 voltage regulator internal resistor ratio set

Electronic volume mode set

Electronic volume

Power control set

Display start line set

Page address set

Column address upper bit set

Column address lower bit set

Display all point ON/OFF

Display normal or reverse

5.5 Reference circuit

Figure 7: Reference Circuit Diagram

Setting data

0xe2

0xa3

0xa0

0xc8

0x25

0x81

0x13

0x25

0x40

0xb0

0x10

0x04

0xa4

0xa6

16

6. Electro-Optical Characteristics

Item

Driving voltage

Symbol

Vop

Table 11

Temp.

Value

°

C Min.

Typ. Max.

+25 - 8.8 -

Unit Condition

V Vop= optimum voltage

Ton - 5737 7458

Response time +25 msec

Vop= Optimum voltage

θ

= 0

°

,

φ

= 0

°

Toff - 5371 6982

Optimum viewing area

Cr

2

θ

1(6 o’clock)

θ

φ

2(12 o’clock)

1(3 o’clock)

φ

2(9 o’clock)

+25

27

30

31

30

38

44

45

44

-

-

-

-

DEG

φ

θ

= 0

= 0

°

°

Vop= Optimum voltage

(Remark 1)

Contrast ratio Cr +25 5 7 -

-

Vop = Optimum voltage

θ

= 0

°

,

φ

= 0

°

Remark 1: Due to hardware limitation, the maximum measurable angle is 50

O

6.1 ISO plot

17

6. 2 Optical Characteristics Definition a.) Viewing Angle b.) Contrast Ratio

B1 = segments luminance in case of non-selected waveform

B2 = segments luminance in case of selected waveform

Non-selected dot

Contrast Ratio is defined by Cr = B2/B1

100%

B2

Select waveform

Non -select waveform

B1

Vop c.) Response Time

Non -selecected condition

Selected

Condition

Selected dot

Non -selecected condition

Ton rise time

Toff fall time

18

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