1024MB DDR3 – SDRAM ECC SO-UDIMM

1024MB DDR3  – SDRAM ECC SO-UDIMM
Data Sheet
Rev.1.2
22.03.2013
1024MB DDR3 – SDRAM ECC SO-UDIMM
Features:
204 Pin ECC SO-UDIMM
SGN01G72F1BG1MT-xxRT

1GByte in FBGA Technology





RoHS compliant
Options:

Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1600 MT/s CL11

Module density
1024MB with 9 dies and 1 rank

Standard Grade
Grade E
Grade W
(TA)
(TC)
(TA)
(TC)
(TA)
(TC)
Marking
-CC
-DC
0°C to 70°C
0°C to 85°C
0°C to 85°C
0°C to 95°C
-40°C to 85°C
-40°C to 95°C




*) The refresh rate has to be doubled when 85°C<TC<95°C



Environmental Requirements:







Operating temperature (ambient)
Standard Grade
0°C to 70°C
Grade E
0°C to 85°C
Grade W
-40°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C



204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double
Data Rate Synchronous DRAM Module
Module organization: single rank 128M x 72
VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V
1.5V I/O ( SSTL_15 compatible)
Fly-by-bus with termination for C/A & CLK bus
2
On-board I C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
Gold-contact pad
This module is fully pin and functional compatible to the
JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM
design spec. and JEDEC- Standard MO-268. (see
www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR3 - SDRAM component based Micron
MT41J128M8JP-XXX DIE-Rev. G
128Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit prefetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
Refresh, Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
Figure: mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 1
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Data Sheet
Rev.1.2
22.03.2013
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line
Memory Module (SO-DIMM) which is organized as x72 high speed CMOS memory arrays. The module uses
internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to
achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ
and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. The burst length is either four or
eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated
at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent
operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “powerdown” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
DDR3 SDRAMs used
Row
Addr.
Device Bank
Addr.
128M x 72bit
9 x 128M x 8bit (1024Mbit)
14
BA0, BA1, BA2
Column
Refresh
Addr.
10
Module
Bank Select
8k
S0#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SGN01G72F1BG1MT-CCRT
1024 MB
10.6 GB/s
1.5ns/1333MT/s
9-9-9
SGN01G72F1BG1MT-DCRT
1024 MB
12.8 GB/s
1.25ns/1600MT/s
11-11-11
Pin Name
A0 – A9, A11 – A13
Address Inputs
A10/AP
Address Input / Autoprecharge Bit
BA0 – BA2
Bank Address Inputs
DQ0 – DQ63
Data Input / Output
CB0 – CB07
ECC check bits
DM0 – DM8
Input Data Mask
DQS0 – DQS8
Data Strobe, positive line
DQS0# - DQS8#
Data Strobe, negative line (only used when differential data strobe mode is enabled)
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
CKE0
Clock Enable
S0#
Chip Select
CK0
Clock Inputs, positive line
CK0#
Clock Inputs, negative line
Swissbit AG
Industriestrasse 4
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Fax: +41 (0) 71 913 03 15
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Page 2
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Data Sheet
Rev.1.2
22.03.2013
Event#
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
VDD
Supply Voltage (1.5V± 0.075V)
VREFDQ
Reference voltage: DQ, DM (VDD/2)
VREFCA
Reference voltage: Control, command, and address (VDD/2)
VSS
Ground
VTT
Termination voltage: Used for control, command, and address (V DD/2).
VDDSPD
Serial EEPROM Positive Power Supply
SCL
Serial Clock for Presence Detect
SDA
Serial Data Out for Presence Detect
SA0 – SA1
Presence Detect Address Inputs
ODT0
On-Die Termination
NC
No Connection
Pin Configuration
Frontside
Symbol
PIN
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
VREFDQ
53
VSS
103
A3
155
VSS
3
VSS
55
DQ24
105
A1
157
DM5
5
DQ0
57
DQ25
107
A0
159
DQ42
7
DQ1
59
DM3
109
VDD
161
DQ43
9
VSS
61
VSS
111
CK0
163
VSS
11
DM0
63
DQ26
113
CK0#
165
DQ48
13
DQ2
65
DQ27
115
VDD
167
DQ49
15
DQ3
67
VSS
117
A10/AP
169
VSS
17
VSS
69
CB0
119
BA0
171
DQS6#
19
DQ8
71
CB1
121
WE#
173
DQS6
21
DQ9
123
VDD
175
VSS
Key
23
VSS
73
VSS
125
CAS#
177
DQ50
25
DQS1#
75
DQS8#
127
S0#
179
DQ51
27
DQS1
77
DQS8
129
NC(S1#)
181
VSS
29
VSS
79
VSS
131
VDD
183
DQ56
31
DQ10
81
CB2
133
DQ32
185
DQ57
33
DQ11
83
CB3
135
DQ33
187
VSS
35
VSS
85
VDD
137
VSS
189
DM7
37
DQ16
87
CKE0
139
DQS4#
191
DQ58
39
DQ17
89
NC(CKE1)
141
DQS4
193
DQ59
41
VSS
91
BA2
143
VSS
195
VSS
43
DQS2#
93
VDD
145
DQ34
197
SA0
45
DQS2
95
A12/BC#
147
DQ35
199
VDDSPD
47
VSS
97
A8
149
VSS
201
SA1
49
DQ18
99
A5
151
DQ40
203
VTT
51
DQ19
101
VDD
153
DQ41
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 3
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Data Sheet
Rev.1.2
22.03.2013
Backside
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
2
VSS
54
DQ28
104
A4
156
DQS5
4
DQ4
56
DQ29
106
A2
158
VSS
6
DQ5
58
VSS
108
BA1
160
DQ46
8
VSS
60
DQS3#
110
VDD
162
DQ47
10
DQS0#
62
DQS3
112
NC(CK1)
164
VSS
12
DQS0
64
VSS
114
NC(CK1#)
166
DQ52
14
VSS
66
DQ30
116
VDD
168
DQ53
16
DQ6
68
DQ31
118
NC(S3#)
170
VSS
18
DQ7
70
VSS
120
NC(S2#)
172
DM6
20
VSS
72
CB4
122
RAS#
174
DQ54
22
DQ12
124
VDD
176
DQ55
24
DQ13
74
CB5
126
ODT0
178
VSS
26
VSS
76
DM8
128
NC(ODT1)
180
DQ60
28
DM1
78
VSS
130
A13
182
DQ61
30
NC (Reset#)
80
CB6
132
VDD
184
VSS
32
VSS
82
CB7
134
DQ36
186
DQS7#
34
DQ14
84
VREFCA
136
DQ37
188
DQS7
36
DQ15
86
VDD
138
VSS
190
VSS
38
VSS
88
NC(A15)
140
DM4
192
DQ62
40
DQ20
90
NC(A14)
142
DQ38
194
DQ63
42
DQ21
92
A9
144
DQ39
196
VSS
44
DM2
94
VDD
146
VSS
198
EVENT#
46
VSS
96
A11
148
DQ44
200
SDA
48
DQ22
98
A7
150
DQ45
202
SCL
50
DQ23
100
A6
152
VSS
204
VTT
52
VSS
102
VDD
154
DQS5#
Key
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 4
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Data Sheet
Rev.1.2
22.03.2013
FUNCTIONAL BLOCK DIAGRAMM 1024MB DDR3 SDRAM SO-UDIMM,
1 RANK AND 9 COMPONENTS
S0
DQS4
DQS4
DM4
DQS0
DQS0
DM0
DM
DQ0
DQ1
DQ2
I/O 0
I/O 1
I/O 2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
D0
ZQ
DQ32
DQ33
DQ34
I/O 0
I/O 1
I/O 2
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D4
ZQ
DQS5
DQS5
DM5
DQS1
DQS1
DM1
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
CS
DM
DQS DQS
D1
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
CS
DQS DQS
D5
ZQ
DQS6
DQS6
DM6
DQS2
DQS2
DM2
DM
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
D2
ZQ
CS
DQS DQS
D6
ZQ
DQS7
DQS7
DM7
DQS3
DQS3
DM3
DM
DQ24
DQ25
DQ26
I/O 0
I/O 1
I/O 2
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
I/O 0
I/O 1
I/O 2
CB3
CB4
CB5
CB6
CB7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
D3
ZQ
DQ59
DQ60
DQ61
DQ62
DQ63
CS
DQS DQS
D7
ZQ
DQS8
DQS8
DM8
DM
BA0-BA2
A0-A13
RAS
CAS
WE
ODT0
CKE0
CK0
CK0
RESET
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
CS
DQS DQS
D8
ZQ
BA0-BA2: SDRAM D0-D8
A0-A13: SDRAM D0-D8
RAS: SDRAM D0-D8
CAS: SDRAM D0-D8
WE: SDRAM D0-D8
ODT: SDRAM D0-D8
CKE: SDRAM D0-D8
CK: SDRAM D0-D8
CK: SDRAM D0-D8
RESET: SDRAM D0-D8
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
VDDSPD
SPD
VDD/VDDQ
D0-D8
VREFDQ
D0-D8
VREFCA
D0-D8
VSS
D0-D8
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of the JEDED document.
5. For each DRAM, a unique ZQ resistor is connected to
GND. The ZQ resistor is 240O±1%.
6. Refer to associated figure for SPD details.
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Page 5
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Data Sheet
Rev.1.2
22.03.2013
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
INPUT LEAKAGE CURRENT
SYMBOL
VDD
VDDQ
VDDL
VIN, VOUT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
MIN
-0.4
-0.4
-0.4
-0.4
MAX
1.975
1.975
1.975
1.975
II
UNITS
V
V
V
V
µA
Command/Address
-16
16
IOZ
-16
-2
-5
16
2
5
µA
IVREF
-8
8
µA
RAS#, CAS#, WE#, S#, CKE
CK, CK#
DM
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
MIN
VDD
1.425
VDDQ
1.425
VDDL
1.425
VREF
0.49 x VDDQ
VTT
0.49 x VDDQ-20mV
VIH (DC)
VREF + 0.1
VIL (DC)
-0.3
NOM
1.5
1.5
1.5
0.50 x VDDQ
0.50 x VDDQ
MAX
1.575
1.575
1.575
0.51x VDDQ
0.51x VDDQ+20mV
VDDQ + 0.3
VREF – 0.1
UNITS
V
V
V
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.175
-
MAX
VREF - 0.175
UNITS
V
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: [email protected]
Page 6
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Data Sheet
Rev.1.2
22.03.2013
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
Fast Exit
PRECHARGE POWER-DOWN
CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and Slow Exit
Address bus inputs are not changing; DQ’s
are floating at VREF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN CURRENT:
All device banks open; tCK = tCK (IDD); CKE is LOW; All
Control and Address bus inputs are not changing; DQ’s
are floating at VREF (always fast exit)
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
Symbol
max.
Unit
12800-11-11-11
10600-9-9-9
IDD0
630
585
mA
IDD1
810
765
mA
IDD2P
270
270
mA
108
108
IDD2Q
360
315
mA
IDD2N
405
360
mA
IDD3P
315
270
mA
IDD3N
405
360
mA
IDD4R
1260
1125
mA
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Page 7
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Data Sheet
Parameter
& Test Condition
OPERATING WRITE CURRENT:
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
tCK = tCK (IDD); refresh command at every tRFC (IDD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are
floating at VREF
OPERATING CURRENT *) :
Four device bank interleaving READs, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
Rev.1.2
Symbol
22.03.2013
max.
Unit
12800-11-11-11
10600-9-9-9
IDD4W
1305
1125
mA
IDD5
1530
1485
mA
IDD6
72
72
mA
IDD7
2205
2115
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
12800-11-11-11
11
CL (IDD)
13.75
tRCD (IDD)
48.75
tRC (IDD)
6.25
tRRD (IDD)
1.25
tCK (IDD)
35
tRAS MIN (IDD)
70’200
tRAS MAX (IDD)
13.75
tRP (IDD)
110
tRFC (IDD)
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
10600-9-9-9
9
13.5
49.5
6
1.5
36
70’200
13.5
110
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 8
of 17
Data Sheet
Rev.1.2
22.03.2013
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
Clock cycle time
CL = 11
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
CK high-level width
CK low-level width
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
DQ and DM input setup time
relative to DQS
SYMBOL
tCK (11)
tCK (10)
tCK (9)
tCK (8)
tCK (7)
tCK (6)
tCK (5)
tCH (avg)
tCL (avg)
tHZ
tLZ
tDS(Base)
12800-11-11-11
MIN
MAX
1.25
1.5
1.5
<1.875
1.5
<1.875
1.875
<2.5
1.875
<2.5
2.5
3.3
3.0
3.3
0.47
0.53
0.47
0.53
225
-
250
ps
-450
225
-500
250
ps
-
-
30
-
ps
-
-
65
-
ps
160
-
180
-
ps
-
165
-
ps
400
-
ps
-
125
ps
tDH(Base)
DQ and DM input hold time
relative to DQS VREF=1V/ns
DQ and DM input pulse width
( for each input )
DQS, DQS# to DQ skew, per
access
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
DQS input high pulse width
DQS input low pulse width
DQS, DQS# rising to/from CK,
CK#
DQS, DQS# rising to/from CK,
CK# when DLL disabled
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
Positive DQS latching edge to
associated clock edge
Address and control input pulse
width ( for each input )
CTRL, CMD, Addr setup to CK,
CK#
CTRL, CMD, Addr setup to CK,
CK#
VREF @ 1V/ns
tDH1V
145
tDIPW
360
tDQSQ
-
100
0.38
-
1
2
tQH
Unit
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
-
DQ and DM input hold time
relative to DQS
DQ and DM input setup time
relative to DQS VREF=1V/ns
tDS1V
10600-9-9-9
MIN
MAX
1.5
<1.875
1.5
<1.875
1.875
<2.5
1.875
<2.5
2.5
3.3
3.0
3.3
0.47
0.53
0.47
0.53
0.38
-
tCK
(AVG)
tDQSH
tDQSL
tDQSCK
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
-225
225
-255
255
ps
tDQSCK
1
10
1
10
ns
tDSS
0.18
-
0.2
-
tCK
tDSH
0.18
-
0.2
-
tCK
0.9
0.3
0.9
0.3
Note1
Note2
0.9
0.3
0.9
0.3
Note1
Note2
-
tCK
tCK
tCK
tCK
- 0.27
+ 0.27
- 0.25
+ 0.25
tCK
tIPW
560
-
620
-
ps
tIS(Base)
45
-
65
-
ps
tIS(1V)
220
-
240
-
ps
DLL_DIS
tRPRE
tRPST
tWPRE
tWPST
tDQSS
The maximum preamble is bound by tLZDQS (MAX)
The maximum postamble is bound by tHZDQS (MAX)
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 9
of 17
Data Sheet
Rev.1.2
22.03.2013
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
SYMBOL
CTRL, CMD, Addr hold to CK,
tIH(Base)
CK#
CTRL, CMD, Addr hold to CK,
tIH(1V)
CK#
VREF @ 1V/ns
CAS# to CAS# command delay
tCCD
ACTIVE to ACTIVE (same bank)
tRC
command period
ACTIVE bank a to ACTIVE bank
tRRD
b command
ACTIVE to READ or WRITE
tRCD
delay
Four bank
1K Page size
30
Activate period
40
2K Page size
ACTIVE to PRECHARGE
tRAS
command
Internal READ to precharge
tRTP
command delay
Write recovery time
tWR
Auto precharge write recovery +
tDAL
precharge time
Internal WRITE to READ
tWTR
command delay
PRECHARGE command period
tRP
LOAD MODE command cycle
tMRD
time
REFRESH to ACTIVE or
REFRESH to REFRESH
tRFC
command interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
RTT turn-on from ODTL on
reference
RTT turn-on from ODTL off
reference
Asynchronous RTT turn-on
delay (power Down with DLL off)
Asynchronous RTT turn-off
delay (power Down with DLL off)
RTT dynamic change skew
Exit self refresh to commands
not requiring a locked DLL
Write levelling setup from rising
CK, CK# crossing to rising DQS,
DQS# crossing
Write levelling setup from rising
DQS, DQS# crossing to rising
CK, CK# crossing
First DQS, DQS# rising edge
DQS, DQS# delay
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
12800-11-11-11
MIN
MAX
10600-9-9-9
MIN
MAX
120
-
140
-
ps
220
-
240
-
ps
4
-
4
-
tCK
48.75
-
49.5
-
ns
max
max
4nCK,6ns
4nCK,10ns
-
ns
13.5
-
ns
30
45
-
ns
36
70’200
ns
max
-
ns
-
ns
-
ns
-
ns
13.75
-
35
70’200
max
-
4nCK,7.5ns
15
tWR +
tRP/tCK
max
-
4nCK,7.5ns
4nCK,7.5ns
15
tWR +
tRP/tCK
max
4nCK,7.5ns
Unit
13.75
-
15
-
ns
4
-
4
-
tCK
110
70’200
110
70’200
ns
tREFI
-
7.8
-
7.8
tREFI (IT)
-
3.9
-
3.9
tAON
-225
225
-250
250
ps
tAOF
0.3
0.7
0.3
0.7
tCK
tAONPD
2
8,5
2
8,5
ns
tAOFPD
2
8,5
2
8,5
ns
tADC
0.3
max
0.7
0.3
max
0.7
tCK
µs
tXS
5nCK,tR
FC + 10ns
-
5nCK,tR
FC + 10ns
-
ns
tWLS
165
-
195
-
ps
tWLH
165
-
195
-
ps
tWLMRD
tWLDQSEN
40
25
-
40
25
-
tCK
tCK
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 10
of 17
Data Sheet
Rev.1.2
22.03.2013
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
Exit reset from CKE HIGH to a
valid command
Begin power supply ramp to
power supplies stable
RESET# LOW to power supplies
stable
RESET# LOW to I/O and RTT
High-Z
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
12800-11-11-11
MIN
MAX
max
5nCK,
SYMBOL
tXPR
tRFC + 10ns
10600-9-9-9
MIN
MAX
max
5nCK,
-
200
tRPS
0
200
tIOz
-
20
max
-
3nCK,6ns
max
tCKE
tCK
tRFC + 10ns
tVDDPR
tXP
Unit
max
ms
200
ms
20
ns
-
tCK
3nCK,6ns
max
-
3nCK,
5ns
-
200
-
tCK
3nCK,
5.625ns
Temperature Sensor with Serial Presence-Detect EEPROM
SCL
SDA
WP/ EVENT
EVENT
R1
0Ω
SA0
SA1
SA0
SA1
SA2
Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions
Parameter / Condition
Supply voltage
Supply current: VDD = 3.3V
Input high voltage: Logic 1; SCL, SDA
Input low voltage: Logic 0; SCL, SDA
Output low voltage: IOUT = 2.1mA
Input current
Temperature sensing range
Temperature sensor accuracy
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Symbol
VDDSPD
IDD
VIH
VIL
VOL
IIN
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
MIN
+3
MAX
+3.6
+2.0
+1.45
-5.0
TBD
TBD
VDDSPD +1
550
400
5.0
TBD
TBD
www.swissbit.com
eMail: [email protected]
Unit
V
mA
V
mV
mV
µA
°C
°C
Page 11
of 17
Data Sheet
Rev.1.2
22.03.2013
A.C. Characteristics of Temperature Sensor
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Symbol
fSCL
tBUF
tF
tR
tHD:DAT
tH:STA
tHIGH
tLOW
tSU:DAT
tSU:STA
tSU:STO
tTIMEOUT
tI
tWR
tPU
Parameter / Condition
SCL clock frequency
Bus Free Time Between STOP and START
SDA fall time
SDA rise time
Data hold time (accepted for Input Data)
Data Hold Time (guaranteed for Output Data)
Start condition hold time
High Period of SCL
Low Period of SCL
Data setup time
Start condition setup time
Stop condition setup time
SMBus SCL Clock Low Timeout
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
Power-up Delay to Valid Temperature Recording
MIN
10
1300
MAX
400
300
300
0
300
600
600
1300
100
600
600
25
900
35
100
5
100
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ms
ms
Temperature Characteristics of Temperature Sensor
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Parameter
Test Conditions/Comments
+75°C ≤ TA ≤ +95°C, active range
+40°C ≤ TA ≤ +125°C, monitor range
-40°C ≤ TA ≤ +125°C, sensing range
Temperature Reading Error
Class B, JC42.4 compliant
ADC Resolution
Temperature Resolution
Conversion Time
1
Thermal Resistance θJA
Junction-to-Ambient (Still Air)
MAX
±1.0
±2.0
±3.0
12
0.0625
100
92
Unit
°C
°C
°C
Bits
°C
Ms
°C/W
1
Power Dissipation is defined as PJ = (TJ − TA)/θJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2-layer PCB.
Slave Address Bits of Temperature Sensor
Device
EEPROM
Temp. Sensor
1
Device Type Identifier
1
b7
b6
b5
b4
1
0
1
0
0
0
1
1
Select Address Signals
b3
b2
b1
A2
A1
A0
A2
A1
A0
R/W#
b0
R/W#
R/W#
The most significant bit, b7, is sent first.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 12
of 17
Data Sheet
Rev.1.2
22.03.2013
SERIAL PRESENCE-DETECT MATRIX
Byte
Byte Description
12800-11-11-11
10600-9-9-9
0
CRC RANGE, EEPROM BYTES, BYTES USED
1
SPD REVISON
2
DRAM DEVICE TYPE
0x0B
3
MODULE TYPE (FORM FACTOR)
0x08
4
SDRAM DEVICE DENSITY & BANKS
0x02
5
SDRAM DEVICE ROW & COLUMN COUNT
0x11
6
BYTE 6 RESERVED
0x00
7
MODULE RANKS & DEVICE DQ COUNT
0x01
8
ECC TAG & MODULE MEMORY BUS WIDTH
0x0B
9
FINE TIMEBASE DIVIDEND/DIVISOR
10
MEDIUM TIMEBASE DIVIDEND
0x01
11
MEDIUM TIMEBASE DIVISOR
0x08
12
MIN SDRAM CYCLE TIME (tCK MIN)
13
BYTE 13 RESERVED
14
CAS LATENCIES SUPPORTED (CL4 => CL11)
15
CAS LATENCIES SUPPORTED (CL12 => CL18)
0x00
16
MIN CAS LATENCY TIME (tAA MIN)
0x69
17
MIN WRITE RECOVERY TIME (tWR MIN)
0x78
18
MIN RAS# TO CAS# DELAY (tRCD MIN)
0x69
19
MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN)
0x30
20
MIN ROW PRECHARGE DELAY (tRP MIN)
0x69
21
UPPER NIBBLE FOR tRAS & tRC
0x11
22
MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN)
0x18
0x20
23
MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN)
0x81
0x89
24
MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB
0x70
25
MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB
0x03
26
MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN)
0x3C
27
MIN INTERNAL READ TO PRECHARGE CMD DELAY
(tRTP MIN)
0x3C
28
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB
0x00
29
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB
0xF0
30
SDRAM DEVICE OUTPUT DRIVERS SUPPORTED
31
SDRAM DEVICE THERMAL & REFRESH OPTIONS
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
0x92
0x11
0x10
0x11
0x52
0x0A
0x0C
0x00
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
0xFE
0x7E
0x83
0x82
0x05
www.swissbit.com
eMail: [email protected]
Page 13
of 17
Data Sheet
Byte
32
Rev.1.2
Byte Description
12800-11-11-11
22.03.2013
10600-9-9-9
Module Thermal Sensor
0x80
BYTES 32-59 RESERVED
0x00
60
MODULE HEIGHT (NOMINAL)
0x0F
61
MODULE THICKNESS (MAX)
0x11
62
REFERENCE RAW CARD ID
63
ADDRESS MAPPING EDGE CONECTOR TO DRAM
0x00
BYTES 64-116 RESEVED
0x00
117
MODULE MFR ID (LSB)
0x83
118
MODULE MFR ID (MSB)
0Xda
119
MODULE MFR LOCATION ID
0x01 (Switzerland)
0x02 (Germany)
0x03 (USA)
120
MODULE MFR YEAR
X
121
MODULE MFR WEEK
X
122-125
MODULE SERIAL NUMBER
X
126-127
CRC
128-145
MODULE PART NUMBER
33-59
64-116
0x02
0x1F
0x27A8
0x6A49
"SGN01G72F1BG1MT-xx"
146
MODULE DIE REV
X
147
MODULE PCB REV
0x54
148
DRAM DEVICE MFR ID (LSB)
0x80
149
DRAM DEVICE MFR (MSB)
0x2C
150-175
MFR RESERVED BYTES 150-175
0x00
176-255
CUSTOMER RESERVED BYTES 176-255
0xff
Part Number Code
S
G
N
01G
72
F1
B
G
1
MT
1
2
3
4
5
6
7
8
9
10
-
DC
*
R
**
11
12
13
14
*RoHs compl.
DDR3-1600MT/s
Swissbit AG
SDRAM DDR3
204 Pin SO-UDIMM 1.5V
capacity (1GByte)
Width
PCB-Type (B83S781 1.00)
Chip Vendor (Micron)
1 Module Rank
Chip Rev. G
Chip organisation x8
* optional / additional information
**T=Thermal Sensor
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 14
of 17
Data Sheet
Rev.1.2
22.03.2013
Revision History
Revision
Changes
Date
1.0
Initial Revision
21.01.2011
1.1
Industrial Temperatur Grades added (E-/W-Grade)
01.06.2011
1.2
new Speed-grade (1600MT/s) added
22.03.2013
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 15
of 17
Data Sheet
Rev.1.2
22.03.2013
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
+41 (0)71 913 03 03
Fax:
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
+49 (0)30 93 69 54 – 0
Fax:
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
1117 E Plaza Drive Unit E Suites 105/205
Eagle, ID 83616
USA
Phone:
+1 208 258-6254
Fax:
+1 208 938-4525
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
+81 3 5356 3511
Fax:
+81 3 5356 3512
________________________________
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 16
of 17
Data Sheet
Rev.1.2
22.03.2013
Declaration of Conformity
We
Manufacturer:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
declare under our sole responsibility that the product
Product Type:
Brand Name:
Product Series:
Part Number:
1GB DDR3 SO-UDIMM
SWISSMEMORY™
DDR3 SO-UDIMM
SGN01G72F1BG1MT-xxxRT
to which this declaration relates is in conformity with the following directives:
2002/96/EC Category 3 (WEEE)
following the provisions of Directive
Restriction of the use of certain hazardous substances
2011/65/EU
Swissbit AG, März 2013
Manuela Kögel
Head of Quality Management
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 17
of 17
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Swissbit:
SGN01G72F1BG1MT-CCWRT
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