STM32F103x6 STM32F103x8 STM32F103xB

STM32F103x6 STM32F103x8 STM32F103xB
STM32F103x6
STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,
seven 16-bit timers, two ADCs and nine communication interfaces
Preliminary Data
Features
■
Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz
– Single-cycle multiplication and hardware
division
■
■
Dead time generation and emergency
stop
– 2 watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
■
■
DMA
■
■
Packages are ECOPACK® (RoHS compliant)
Table 1.
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
Up to 9 communication interfaces
– Up to 2 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
2 x 12-bit, 1 µs A/D converters (16-channel)
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
Up to 7 timers
up to 6 channels for PWM output
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Temperature sensor
■
Device summary
Reference
October 2007
Root part number
STM32F103x6
STM32F103C6, STM32F103R6,
STM32F103T6
STM32F103x8
STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103xB
STM32F103RB STM32F103VB,
STM32F103CB
Up to 80 fast I/O ports
– 26/36/51/80 I/Os, all mappable on 16
external interrupt vectors, all 5 V-tolerant
except for analog inputs
BGA100
10 x 10 mm
– Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 16-bit, 6-channel advanced control timer:
Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
■
VFQFPN36
6 × 6 mm
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz quartz oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
■
LQFP64
10 x 10 mm
Memories
– 32-to-128 Kbytes of Flash memory
– 6-to-20 Kbytes of SRAM
■
LQFP100
14 x 14 mm
LQFP48
7 x 7 mm
Rev 3
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/79
www.st.com
1
Contents
STM32F103xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
2/79
Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 29
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 30
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.11
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 50
5.3.12
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.13
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STM32F103xx
6
5.3.14
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.15
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.16
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.17
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.18
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1
7
Contents
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.1
Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Appendix A Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8
A.1
PD0 and PD1 use in output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
A.2
ADC auto-injection channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
A.3
ADC combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . 76
A.4
Voltage glitch on ADC input 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3/79
List of tables
STM32F103xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
4/79
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device features and peripheral counts (STM32F103xx performance line). . . . . . . . . . . . . . 8
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 34
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 34
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Typical current consumption in Sleep mode, code with data processing
code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Typical current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
High-speed external (HSE) user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
USB: Full speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STM32F103xx
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
List of tables
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 68
LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 69
LQFP100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 71
LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 72
LQFP48 – 48 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 73
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5/79
List of figures
STM32F103xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
6/79
STM32F103xx performance line block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32F103xx VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM32F103xx performance line BGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 33
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 33
Current consumption in Stop mode with regulator in Run mode at VDD = 3.3 V to 3.6 V
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current consumption in Standby mode versus temperature at VDD = 3.3 V to 3.6 V . . . . . 35
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typical application with a 8-MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SPI timing diagram - slave mode and CPHA = 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 66
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 66
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 69
Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 70
LQFP100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 71
LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LQFP48 – 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
STM32F103xx
1
Introduction
Introduction
This datasheet provides the STM32F103xx performance line ordering information and
mechanical device characteristics.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming reference manual, PM0042, available
from www.st.com.
For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference
Manual.
2
Description
The STM32F103xx performance line family incorporates the high-performance ARM
Cortex-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded
memories (Flash memory up to 128Kbytes and SRAM up to 20 Kbytes), and an extensive
range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two
12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard
and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB
and a CAN.
The STM32F103xx performance line family operates in the −40 to +105 °C temperature
range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows
to design low-power applications.
The complete STM32F103xx performance line family includes devices in 5 different
package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F103xx performance line microcontroller family suitable for
a wide range of applications:
●
Motor drive and application control
●
Medical and handheld equipment
●
PC peripherals gaming and GPS platforms
●
Industrial applications: PLC, inverters, printers, and scanners
●
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
7/79
Description
2.1
STM32F103xx
Device overview
Table 2.
Device features and peripheral counts (STM32F103xx performance line)
Peripheral
STM32F103Tx
STM32F103Cx
STM32F103Rx
32
64
32
64
128
32
SRAM - Kbytes
10
20
10
20
20
10
20
20
2
3
2
3
3
2
3
3
Communication
Timers
Flash - Kbytes
General purpose
Advanced control
1
1
128
64
1
128
1
SPI
1
2
1
2
2
1
2
2
I2C
1
2
1
2
2
1
2
2
USART
2
3
2
3
3
2
3
3
USB
1
1
1
1
1
1
1
1
CAN
1
1
1
1
1
1
1
1
GPIOs
12-bit synchronized ADC
Number of channels
26
36
51
2
10 channels
2
10 channels
CPU frequency
2
16 channels
2.0 to 3.6 V
Operating temperature
Packages
80
72 MHz
Operating voltage
8/79
64
STM32F103Vx
-40 to +85 °C / -40 to +105 °C
VFQFPN36
LQFP48
LQFP64
LQFP100,
BGA100
STM32F103xx
2.2
Description
Overview
ARM® CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
●
Up to 128 Kbytes of embedded Flash is available for storing programs and data.
Embedded SRAM
Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a Nested Vectored Interrupt Controller able to
handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexM3) and 16 priority levels.
●
Closely coupled NVIC gives low latency interrupt processing
●
Interrupt entry vector table address passed directly to the core
●
Closely coupled NVIC core interface
●
Allows early processing of interrupts
●
Processing of late arriving higher priority interrupts
●
Support for tail-chaining
●
Processor state automatically saved
●
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16
external interrupt lines.
9/79
Description
STM32F103xx
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is
monitored for failure. During such a scenario, it is disabled and software interrupt
management follows. Similarly, full interrupt management of the PLL clock entry is available
when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the High Speed APB domains is 72 MHz. The maximum allowed frequency of the Low
Speed APB domain is 36 MHz.
Boot modes
At startup, boot pins are used to select one of three boot options:
●
Boot from User Flash
●
Boot from System Memory
●
Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using the USART.
Power supply schemes
●
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●
VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. In VDD range (ADC is limited at 2.4 V).
●
VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated Power On Reset (POR)/Power Down Reset (PDR) circuitry. It
is always active, and ensures proper operation starting from/down to 2 V. The device
remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need
for an external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to Table 9: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
10/79
STM32F103xx
Description
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
MR is used in the nominal regulation mode (Run)
●
LPR is used in the Stop modes.
●
Power down is used in Standby Mode: the regulator output is in high impedance: the
kernel circuitry is powered-down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby Mode, providing high
impedance output.
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode allows to achieve the lowest power consumption while retaining the content
of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI
and the HSE RC oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
●
Standby mode
The Standby mode allows to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby
mode, SRAM and registers content are lost except for registers in the Backup domain
and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose and
advanced control timers TIMx and ADC.
11/79
Description
STM32F103xx
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit
registers) can be used to store data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low power
RC oscillator or the high speed external clock divided by 128. The internal low-power RC
has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation. The RTC features a 32-bit
programmable counter for long term measurement using the Compare register to generate
an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application time out
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
●
A 24-bit down counter
●
Autoreload capability
●
Maskable system interrupt generation when the counter reaches 0.
●
Programmable clock source
General purpose timers (TIMx)
There are up to 3 synchronizable standard timers embedded in the STM32F103xx
performance line devices. These timers are based on a 16-bit auto-reload up/down counter,
a 16-bit prescaler and feature 4 independent channels each for input capture/output
compare, PWM or one pulse mode output. This gives up to 12 input captures / output
compares / PWMs on the largest packages. They can work together with the Advanced
Control Timer via the Timer Link feature for synchronization or event chaining.
The counter can be frozen in debug mode.
Any of the standard timers can be used to generate PWM outputs. Each of the timers has
independent DMA request generations.
12/79
STM32F103xx
Description
Advanced control timer (TIM1)
The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It can also be seen as a complete general-purpose timer. The 4 independent
channels can be used for
●
Input Capture
●
Output Compare
●
PWM generation (edge or center-aligned modes)
●
One Pulse Mode output
●
Complementary PWM outputs with programmable inserted dead-times.
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.
I²C bus
Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The
other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816
compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
13/79
Description
STM32F103xx
Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the
USB Full-speed 12 Mbs. The USB interface implements a full speed (12 Mbit/s) function
interface. It has software configurable endpoint setting and suspend/resume support. The
dedicated 48 MHz clock source is generated from the internal main PLL.
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
ADC (analog to digital converter)
Two 12-bit Analog to Digital Converters are embedded into STM32F103xx performance line
devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group
of analog inputs.
Additional logic functions embedded in the ADC interface allow:
●
Simultaneous sample and hold
●
Interleaved sample and hold
●
Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the standard timers (TIMx) and the Advanced Control timer (TIM1)
can be internally connected to the ADC start trigger, injection trigger, and DMA trigger
respectively, to allow the application to synchronize A/D conversion and timers.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature.
The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC12_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
14/79
STM32F103xx
Description
STM32F103xx performance line block diagram
TPIU
SW/JTAG
Ibus
Cortex-M3 CPU
Fmax : 72 MHz
NVIC
Trace
Controlle r
pbu s
Trace/trig
Dbus
Syst em
AHB:F max =48/72 MHz
@VDDA
SUPPLY
SUPERVISION
NRST
VDDA
VSSA
Rst
PVD
Int
PCLK1
PCLK2
HCLK
FCLK
AHB2
APB2
@VDD
PLL &
CLOCK
MANAGT
XTAL OSC
4-16 MHz
GPIOA
GPIOB
PC[15:0]
GPIOC
PD[15:0]
GPIOD
PE[15:0]
GPIOE
4 Chann els
3 co mpl. Chann els
Brk i npu t
TIM1
MOSI,MISO,
SCK,NSS as AF
SPI1
IWDG
Stand by
in terface
@VDDA
AHB2
APB 1
RTC
AWU
Back up
reg
12bit ADC1 IF
TAMPER-RTC
TIM2
4 Chann els
TIM3
4 Chann els
TIM 4
4 Chann els
USART2
RX,TX, CTS, RTS,
CK, SmartCard as AF
USART3
RX,TX, CTS, RTS,
CK, SmartCard as AF
2x(8x16bit)SPI2
MOSI,MISO,SCK,NSS
as AF
I2C1
SCL,SDA,SMBA L
as AF
I2C2
SCL,SDA
as AF
bx CAN
USB 2.0 FS
12bi t ADC2 IF
OSC32_IN
OSC32_OUT
Backu p i nterf ace
@VDDA
VREF-
VBAT
@VBAT
USART1
16AF
VREF+
OSC_IN
OSC_OUT
RC 8 MHz
RC 40 kHz
EXTI
WAKEUP
PA[ 15:0]
VDD = 2 to 3.6V
VSS
@VDD
64 bit
XTAL 32 kHz
PB[ 15:0]
RX,TX, CTS, RTS,
Smart Card as AF
Flash 128 KB
APB2 : F max =48 / 72 MHz
80AF
POR / PDR
VOLT. REG.
3.3V TO 1.8V
SRAM
20 KB
GP DMA
7 ch annels
POWER
APB1 : Fmax =24 / 36 MHz
JNTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
flash obl
Inte rfac e
TRACECLK
TRACED[0:3]
as AS
BusM atrix
Figure 1.
USBDP/CANTX
USBDM/CANRX
SRAM 512B
WWDG
Temp sensor
ai14390b
1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
15/79
Pin descriptions
Pin descriptions
PB6
PB5
PB4
PB3
PA15
PA14
36
PB7
STM32F103xx VFQFPN36 pinout
VSS_3
35
34
33
32
31
30
29
28
VDD_3
1
27
VDD_2
OSC_IN/PD0
2
26
VSS_2
OSC_OUT/PD1
3
25
PA13
NRST
4
24
PA12
23
PA11
VSSA
5
VDDA
6
22
PA10
PA0-WKUP
7
21
PA9
PA1
8
20
PA8
PA2
9
10
11
12
13
14
15
PA3
PA4
PA5
PA6
PA7
PB0
QFN36
19
18
VDD_1
VSS_1
17
PB2
16
PB1
Figure 2.
BOOT0
3
STM32F103xx
ai14654
16/79
STM32F103xx
Pin descriptions
STM32F103xx performance line LQFP100 pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 3.
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
ai14391
17/79
Pin descriptions
STM32F103xx performance line LQFP64 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 4.
STM32F103xx
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14392
STM32F103xx performance line LQFP48 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
Figure 5.
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
LQFP48
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14393
18/79
STM32F103xx
Figure 6.
Pin descriptions
STM32F103xx performance line BGA100 ballout
1
A
2
PC14PC13OSC32_IN TAMPER-RTC
3
4
5
6
7
8
9
10
PE2
PB9
PB7
PB4
PB3
PA15
PA14
APA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
OSC_IN
VSS_5
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
OSC_OUT
VDD_5
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PCD
PE6
VSS_4
VSS_3
VSS_2
VSS_1
PD1
PC9
PC7
F
PC0
PC1
PC3
VDD_4
VDD_3
VDD_2
VDD_1
NC
PC8
PC6
G
VSSA
PA0-WKUP
PA4
PC4
PB2
PE10
PE14
PB15
PD11
PD15
H
VREF–
PA1
PA5
PC5
PE7
PE11
PE15
PB14
PD10
PD14
J
VREF+
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDDA
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
AI16001
19/79
Pin descriptions
Table 3.
STM32F103xx
Pin definitions
BGA100
LQFP48
LQFP64
LQFP100
VFQFPN36
Type(1)
I / O Level(2)
Pins
Main function(3)
(after reset)
A3
-
-
1
-
PE2
I/O
FT
PE2
TRACECK
B3
-
-
2
-
PE3
I/O
FT
PE3
TRACED0
C3
-
-
3
-
PE4
I/O
FT
PE4
TRACED1
D3
-
-
4
-
PE5
I/O
FT
PE5
TRACED2
E3
-
-
5
-
PE6
I/O
FT
PE6
TRACED3
B2
1
1
6
-
VBAT
S
A2
2
2
7
-
A1
3
3
8
Pin name
PC13-TAMPER-RTC(4) I/O
Default alternate functions
VBAT
PC13
-
PC14-OSC32_IN(4)
I/O
PC14-OSC32_IN
I/O
PC15-OSC32_OUT
TAMPER-RTC
B1
4
4
9
-
PC15-OSC32_OUT(4)
C2
-
-
10
-
VSS_5
S
VSS_5
D2
-
-
11
-
VDD_5
S
VDD_5
C1
5
5
12
2
OSC_IN
I
OSC_IN
D1
6
6
13
3
OSC_OUT
O
OSC_OUT
E1
7
7
14
4
NRST
I/O
NRST
F1
-
8
15
-
PC0
I/O
PC0
ADC12_IN10
F2
-
9
16
-
PC1
I/O
PC1
ADC12_IN11
E2
-
10
17
-
PC2
I/O
PC2
ADC12_IN12
F3
-
11
18
-
PC3
I/O
PC3
ADC12_IN13
G1
8
12
19
5
VSSA
S
VSSA
H1
-
-
20
-
VREF-
S
VREF-
J1
-
-
21
-
VREF+
S
VREF+
K1
9
13
22
6
VDDA
S
VDDA
G2
10
14
23
7
PA0-WKUP
I/O
PA0
WKUP/USART2_CTS(6)/
ADC12_IN0/
TIM2_CH1_ETR(6)
H2
11
15
24
8
PA1
I/O
PA1
USART2_RTS(6)/
ADC12_IN1/ TIM2_CH2(6)
J2
12
16
25
9
PA2
I/O
PA2
USART2_TX(6)/
ADC12_IN2/ TIM2_CH3(6)
K2
13
17
26
10
PA3
I/O
PA3
USART2_RX(6)/
ADC12_IN3/TIM2_CH4(6)
E4
-
18
27
-
VSS_4
S
VSS_4
F4
-
19
28
-
VDD_4
S
VDD_4
20/79
STM32F103xx
Pin definitions (continued)
BGA100
LQFP48
LQFP64
LQFP100
VFQFPN36
Pin name
Type(1)
Pins
I / O Level(2)
Table 3.
Pin descriptions
G3
14
20
29
11
PA4
I/O
PA4
SPI1_NSS(6)/
USART2_CK(6)/ ADC12_IN4
H3
15
21
30
12
PA5
I/O
PA5
SPI1_SCK(6)/ ADC12_IN5
J3
16
22
31
13
PA6
I/O
PA6
SPI1_MISO(6)/
ADC12_IN6/TIM3_CH1(6)
K3
17
23
32
14
PA7
I/O
PA7
SPI1_MOSI(6)/
ADC12_IN7/TIM3_CH2(6)
G4
-
24
33
PC4
I/O
PC4
ADC12_IN14
H4
-
25
34
PC5
I/O
PC5
ADC12_IN15
J4
18
26
35
15
PB0
I/O
PB0
ADC12_IN8/TIM3_CH3(6)
K4
19
27
36
16
PB1
I/O
PB1
ADC12_IN9/TIM3_CH4(6)
G5
20
28
37
17
PB2 / BOOT1
I/O
FT
PB2/BOOT1
H5
-
-
38
-
PE7
I/O
FT
PE7
J5
-
-
39
-
PE8
I/O
FT
PE8
K5
-
-
40
-
PE9
I/O
FT
PE9
G6
-
-
41
-
PE10
I/O
FT
PE10
H6
-
-
42
-
PE11
I/O
FT
PE11
J6
-
-
43
-
PE12
I/O
FT
PE12
K6
-
-
44
-
PE13
I/O
FT
PE13
G7
-
-
45
-
PE14
I/O
FT
PE14
H7
-
-
46
-
PE15
I/O
FT
PE15
J7
21
29
47
-
PB10
I/O
FT
PB10
I2C2_SCL/USART3_TX(5)(6)
K7
22
30
48
-
PB11
I/O
FT
PB11
I2C2_SDA/ USART3_RX(5)(6)
E7
23
31
49
18
VSS_1
S
VSS_1
F7
24
32
50
19
VDD_1
S
VDD_1
Main function(3)
(after reset)
Default alternate functions
K8
25
33
51
-
PB12
I/O
FT
PB12
SPI2_NSS(5)/I2C2_SMBAl(5)/
USART3_CK(5)(6)/
TIM1_BKIN(6)
J8
26
34
52
-
PB13
I/O
FT
PB13
SPI2_SCK(5)/
USART3_CTS(5)(6)/
TIM1_CH1N (6)
H8
27
35
53
-
PB14
I/O
FT
PB14
SPI2_MISO(5)/
USART3_RTS(5)(6)
TIM1_CH2N (6)
G8
28
36
54
-
PB15
I/O
FT
PB15
SPI2_MOSI(5)/TIM1_CH3N(6)
21/79
Pin descriptions
Table 3.
STM32F103xx
Pin definitions (continued)
BGA100
LQFP48
LQFP64
LQFP100
VFQFPN36
Type(1)
I / O Level(2)
Pins
Main function(3)
(after reset)
K9
-
-
55
-
PD8
I/O
FT
PD8
J9
-
-
56
-
PD9
I/O
FT
PD9
H9
-
-
57
-
PD10
I/O
FT
PD10
G9
-
-
58
-
PD11
I/O
FT
PD11
K10
-
-
59
-
PD12
I/O
FT
PD12
J10
-
-
60
-
PD13
I/O
FT
PD13
H10
-
-
61
-
PD14
I/O
FT
PD14
G10
-
-
62
-
PD15
I/O
FT
PD15
F10
-
37
63
-
PC6
I/O
FT
PC6
E10
38
64
-
PC7
I/O
FT
PC7
F9
39
65
-
PC8
I/O
FT
PC8
Pin name
Default alternate functions
E9
-
40
66
-
PC9
I/O
FT
PC9
D9
29
41
67
20
PA8
I/O
FT
PA8
USART1_CK/
TIM1_CH1(6)/MCO
C9
30
42
68
21
PA9
I/O
FT
PA9
USART1_TX(6)/ TIM1_CH2(6)
D10 31
43
69
22
PA10
I/O
FT
PA10
USART1_RX(6)/ TIM1_CH3(6)
C10 32
44
70
23
PA11
I/O
FT
PA11
USART1_CTS/ CANRX(6)/
TIM1_CH4(6) / USBDM
B10 33
45
71
24
PA12
I/O
FT
PA12
USART1_RTS/ CANTX(6) /
TIM1_ETR(6) / USBDP
A10 34
46
72
25
PA13/JTMS/SWDIO
I/O
FT
JTMS/SWDIO
PA13
F8
-
-
73
-
E6
35
47
74
26
VSS_2
S
VSS_2
F6
36
48
75
27
VDD_2
S
VDD_2
A9
37
49
76
28
PA14/JTCK/SWCLK
I/O
FT
JTCK/SWCLK
PA14
A8
38
50
77
29
PA15/JTDI
I/O
FT
JTDI
PA15
B9
-
51
78
PC10
I/O
FT
PC10
B8
-
52
79
PC11
I/O
FT
PC11
C8
-
53
80
PC12
I/O
FT
PC12
D8
5
5
81
2
PD0
I/O
FT
OSC_IN(7)
E8
6
6
82
3
PD1
I/O
FT
OSC_OUT(7)
54
83
-
PD2
I/O
FT
PD2
-
84
-
PD3
I/O
FT
PD3
B7
C7
22/79
-
Not connected
TIM3_ETR
STM32F103xx
Table 3.
Pin descriptions
Pin definitions (continued)
BGA100
LQFP48
LQFP64
LQFP100
VFQFPN36
Type(1)
I / O Level(2)
Pins
Main function(3)
(after reset)
D7
-
-
85
-
PD4
I/O
FT
PD4
B6
-
-
86
-
PD5
I/O
FT
PD5
C6
-
-
87
-
PD6
I/O
FT
PD6
D6
-
-
88
-
PD7
I/O
FT
PD7
A7
39
55
89
30
PB3/JTDO
I/O
FT
JTDO
PB3/TRACESWO
A6
40
56
90
31
PB4/JNTRST
I/O
FT
JNTRST
PB4
C5
41
57
91
32
PB5
I/O
PB5
I2C1_SMBAl
B5
42
58
92
33
PB6
I/O
FT
PB6
I2C1_SCL(6)/
TIM4_CH1(5)(6)
A5
43
59
93
34
PB7
I/O
FT
PB7
I2C1_SDA(6)/TIM4_CH2(5) (6)
D5
44
60
94
35
BOOT0
I
B4
45
61
95
-
PB8
I/O
FT
PB8
TIM4_CH3(5) (6)
A4
46
62
96
-
PB9
I/O
FT
PB9
TIM4_CH4(5) (6)
D4
-
-
97
-
PE0
I/O
FT
PE0
TIM4_ETR(5)
C4
-
-
98
-
PE1
I/O
FT
PE1
E5
47
63
99
36
VSS_3
S
VSS_3
F5
48
64
100
1
VDD_3
S
VDD_3
Pin name
Default alternate functions
BOOT0
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. Refer to Table 2 on page 8.
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to
the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
23/79
Memory mapping
4
STM32F103xx
Memory mapping
The memory map is shown in Figure 7.
Figure 7.
Memory map
APB memory space
0xFFFF FFFF
reserved
0xE010 0000
reserved
0x6000 0000
reserved
4 Kbits
reserved
1 Kbit
reserved
3 Kbits
0x4002 3400
0x4002 3000
0xFFFF FFFF
0x4002 2400
0xFFFF F000
Flash Interface
0x4002 2000
7
0xE010 0000
0xE000 0000
0x4002 1400
0x4002 1000
Cortex-M3 Internal
Peripherals
1 Kbit
3 Kbits
reserved
1 Kbit
RCC
3 Kbits
reserved
0x4002 0400
1 Kbit
DMA
0x4002 0000
6
reserved
1 Kbit
USART1
1 Kbit
reserved
1 Kbit
0x4001 3C00
0x4001 3800
0xC000 0000
0x4001 3400
SPI1
1 Kbit
TIM1
1 Kbit
ADC2
1 Kbit
ADC1
1 Kbit
0x4001 3000
0x4001 2C00
5
0x4001 2800
0x4001 2400
0xA000 0000
2 Kbits
reserved
0x4001 1C00
4
1 Kbit
Port D
1 Kbit
Port C
1 Kbit
Port B
1 Kbit
Port A
1 Kbit
EXTI
1 Kbit
AFIO
1 Kbit
0x4001 1800
0x1FFF FFFF
reserved
0x4001 1400
0x1FFF F80F
0x8000 0000
Port E
Option Bytes
0x1FFF F800
0x4001 1000
0x4001 0C00
0x4001 0800
3
System memory
0x4001 0400
0x4001 0000
0x1FFF F000
0x6000 0000
reserved
0x4000 7400
35 Kbits
PWR
1 Kbit
BKP
1 Kbit
reserved
1 Kbit
0x4000 7000
2
0x4000 6C00
reserved
0x4000 0000
Peripherals
0x4000 6800
0x4000 6400
0x4000 6000
bxCAN
1 Kbit
shared 512 byte
USB/CAN SRAM
1 Kbit
USB Registers
1 Kbit
I2C2
1 Kbit
I2C1
1 Kbit
0x4000 5C00
1
0x4000 5800
0x2000 0000
0x4000 5400
SRAM
0x0801 FFFF
reserved
2 Kbits
USART3
1 Kbit
USART2
1 Kbit
reserved
2 Kbits
0x4000 4C00
0
Flash memory
0x4000 4800
0x4000 4400
0x0000 0000
Code
0x0800 0000
0x4000 3C00
SPI2
1 Kbit
reserved
1 Kbit
IWDG
1 Kbit
WWDG
1 Kbit
RTC
1 Kbit
0x4000 3800
0x4000 3400
0x4000 3000
Reserved
0x4000 2C00
0x4000 2800
reserved
7 Kbits
0x4000 0C00
TIM4
1 Kbit
TIM3
1 Kbit
TIM2
1 Kbit
0x4000 0800
0x4000 0400
0x4000 0000
ai14394b
24/79
STM32F103xx
5
Electrical characteristics
5.1
Test conditions
Electrical characteristics
Unless otherwise specified, all voltages are referred to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25 °C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
25/79
Electrical characteristics
Figure 8.
STM32F103xx
Pin loading conditions
Figure 9.
Pin input voltage
STM32F103xx pin
STM32F103xx pin
C = 50 pF
VIN
ai14141
5.1.6
ai14142
Power supply scheme
Figure 10. Power supply scheme
VBAT
3.3 V
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Backup registers)
OUT
GP I/Os
IN
Level shifter
Po wer swi tch
1.8-3.6 V
IO
Logic
Kernel logic
(CPU,
Digital
& Memories)
VDD
VDD
1/2/3/4/5
5 × 100 nF
+ 1 × 10 µF
Regulator
VSS
1/2/3/4/5
3.3V
VDD
VDDA
VREF
10 nF
+ 1 µF
10 nF
+ 1 µF
VREF+
VREF-
ADC
Analog:
RCs, PLL,
...
VSSA
ai14125
26/79
STM32F103xx
5.1.7
Electrical characteristics
Current consumption measurement
Figure 11. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
27/79
Electrical characteristics
5.2
STM32F103xx
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics,
Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 4.
Voltage characteristics
Symbol
Ratings
Min
Max
–0.3
4.0
Input voltage on five volt tolerant pin(2)
VSS −0.3
+5.5
Input voltage on any other pin(2)
VSS − 0.3
VDD+0.3
Variations between different power pins
50
50
Variations between all the different ground pins
50
50
External 3.3 V supply voltage (including VDDA
and VDD)(1)
VDD–VSS
VIN
|∆VDDx|
Unit
V
mV
|VSSX − VSS|
Electrostatic discharge voltage (human body
model)
VESD(HBM)
see Section 5.3.11:
Absolute maximum ratings
(electrical sensitivity)
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
2. IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is
induced by VIN < VSS.
Table 5.
Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into VDD power lines (source)(1)
150
IVSS
Total current out of VSS ground lines (sink)(1)
150
Output current sunk by any I/O and control pin
25
Output current source by any I/Os and control pin
−25
Injected current on NRST pin
±5
Injected current on HSE OSC_IN and LSE OSC_IN pins
±5
Injected current on any other pin(4)
±5
IIO
IINJ(PIN) (2)(3)
ΣIINJ(PIN)
(2)
Total injected current (sum of all I/O and control
pins)(4)
Unit
mA
± 25
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
28/79
STM32F103xx
Electrical characteristics
Table 6.
Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
–65 to +150
°C
Maximum junction temperature (see Thermal characteristics)
TJ
5.3
Operating conditions
5.3.1
General operating conditions
Table 7.
Symbol
Parameter
Min
Max
fHCLK
Internal AHB clock frequency
0
72
fPCLK1
Internal APB1 clock frequency
0
36
fPCLK2
Internal APB2 clock frequency
0
72
VDD
Standard operating voltage
2
3.6
V
VBAT
Backup operating voltage
1.8
3.6
V
Ambient temperature range
–40
105
°C
TA
5.3.2
General operating conditions
Conditions
Unit
MHz
Operating conditions at power-up / power-down
The parameters given in Table 8 are derived from tests performed under the ambient
temperature condition summarized in Table 7.
Table 8.
Symbol
tVDD
Operating conditions at power-up / power-down
Parameter
Conditions
Min
VDD rise time rate
0
VDD fall time rate
20
Max
Unit
∞
∞
µs/V
29/79
Electrical characteristics
5.3.3
STM32F103xx
Embedded reset and power control block characteristics
The parameters given in Table 9 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 9.
Symbol
VPVD
Embedded reset and power control block characteristics
Parameter
Programmable voltage
detector level selection
VPVDhyst
PVD hysteresis
VPOR/PDR
Power on/power down reset
threshold
VPDRhyst
PDR hysteresis
TRSTTEMPO Reset temporization
30/79
Conditions
Min Typ Max
Unit
PLS[2:0]=000 (rising edge)
2.1
2.18 2.26
V
PLS[2:0]=000 (falling edge)
2
2.08 2.16
V
PLS[2:0]=001 (rising edge)
2.19 2.28 2.37
V
PLS[2:0]=001 (falling edge)
2.09 2.18 2.27
V
PLS[2:0]=010 (rising edge)
2.28 2.38 2.48
V
PLS[2:0]=010 (falling edge)
2.18 2.28 2.38
V
PLS[2:0]=011 (rising edge)
2.38 2.48 2.58
V
PLS[2:0]=011 (falling edge)
2.28 2.38 2.48
V
PLS[2:0]=100 (rising edge)
2.47 2.58 2.69
V
PLS[2:0]=100 (falling edge)
2.37 2.48 2.59
V
PLS[2:0]=101 (rising edge)
2.57 2.68 2.79
V
PLS[2:0]=101 (falling edge)
2.47 2.58 2.69
V
PLS[2:0]=110 (rising edge)
2.66 2.78
2.9
V
PLS[2:0]=110 (falling edge)
2.56 2.68
2.8
V
PLS[2:0]=111 (rising edge)
2.76 2.88
3
V
PLS[2:0]=111 (falling edge)
2.66 2.78
2.9
V
100
Falling edge
1.8
Rising edge
1.84 1.92
mV
1.88 1.96
2.0
40
1
2.5
V
V
mV
4.5
mS
STM32F103xx
5.3.4
Electrical characteristics
Embedded reference voltage
The parameters given in Table 10 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 10.
Symbol
VREFINT
Embedded internal reference voltage
Parameter
Internal reference voltage
Conditions
Min
Typ
Max
Unit
−40 °C < TA < +105 °C
1.16
1.20
1.26
V
−40 °C < TA < +85 °C
1.16
1.20
1.24
V
5.1
17.1
µs
ADC sampling time when
TS_vrefint(1) reading the internal reference
voltage
1. Shortest sampling time can be determined in the application by multiple iterations.
5.3.5
Supply current characteristics
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except when explicitly mentioned
●
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
●
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
●
When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 11, Table 12 and Table 13 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Table 7.
31/79
Electrical characteristics
Table 11.
STM32F103xx
Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
Unit
TA = 85 °C
TA = 105 °C
72 MHz
50
50.3
48 MHz
36.1
36.2
36 MHz
28.6
28.7
24 MHz
19.9
20.1
16 MHz
14.7
14.9
8 MHz
8.6
8.9
72 MHz
32.8
32.9
48 MHz
24.4
24.5
External clock(2), all 36 MHz
peripherals disabled 24 MHz
19.8
19.9
13.9
14.2
16 MHz
10.7
11
8 MHz
6.8
7.1
External clock(2), all
peripherals enabled
IDD
fHCLK
Supply current in
Run mode
mA
1. Data based on characterization results, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz.
Table 12.
Maximum current consumption in Run mode, code with data processing
running from RAM
Max
Symbol
Parameter
Conditions
fHCLK
72 MHz(2)
IDD
45
47
31.5
32
(3)
24
25.5
24 MHz(3)
17.5
18
16 MHz(3)
12.5
13
8 MHz
7.5
8
72 MHz
29
29.5
48 MHz
20.5
21
36 MHz
16
16.5
24 MHz
11.5
12
16 MHz
8.5
9
8 MHz
5.5
6
36 MHz
(3)
Supply current
in Run mode
TA = 105 °C
(3)
48 MHz
External clock(1), all
peripherals enabled
Unit
TA = 85 °C
mA
clock(1),
External
peripherals
disabled(3)
all
1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz.
2. Data based on characterization results, tested in production at VDD max, fHCLK max. and TA max, and code
executed from RAM.
3. Based on characterization, not tested in production.
32/79
STM32F103xx
Electrical characteristics
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
45
40
Consumption (mA)
35
30
72MHz
36MHz
16MHz
8MHz
25
20
15
10
5
0
-40
0
25
70
85
105
Temperature (°C)
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
30
Consumption (mA)
25
20
72 MHz
36MHz
16MHz
8MHz
15
10
5
0
-40
0
25
70
85
105
Temperature (°C)
33/79
Electrical characteristics
Table 13.
STM32F103xx
Maximum current consumption in Sleep mode, code running from Flash or RAM
Max
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz(2)
28
29
(3)
20
20.5
36 MHz(3)
15.5
16
MHz(3)
11.5
12
8.5
9
5.5
6
72 MHz
7.5
8
48 MHz
6
6.5
36 MHz
5
5.5
24 MHz
4.5
5
16 MHz
4
4.5
8 MHz
3
4
48 MHz
External clock(1), all
peripherals enabled
24
(3)
16 MHz
IDD
8 MHz
Supply current in
Sleep mode
(3)
mA
External clock(1), all
peripherals disabled(3)
1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz.
2. Data based on characterization results, tested in production at VDD max, fHCLK max. and TA max.
3. Based on characterization, not tested in production.
Table 14.
Typical and maximum current consumptions in Stop and Standby modes(1)
Typ(2)
Symbol
Parameter
Conditions
Regulator in Run mode, low-speed and
high-speed internal RC oscillators and
high-speed oscillator OFF (no
Supply current in independent watchdog)
Stop mode
Regulator in Low Power mode, lowIDD
speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
Low-speed internal RC oscillator and
Supply current in
independent watchdog OFF, low-speed
(4)
Standby mode
oscillator and RTC OFF
IDD_VBAT
Backup domain
supply current
Low-speed oscillator and RTC ON
Max
VDD/VBAT VDD/VBAT TA =
TA =
= 2.4 V
= 3.3 V 85 °C 105 °C
23.5
24
TBD(3) TBD(3)
13.5
14
TBD(3) TBD(3)
1.7
2
1
1.4
4(5)
Unit
µA
5(5)
TBD(5) TBD(5)
1. TBD stands for to be determined.
2. Typical values are measured at TA = 25 °C, VDD = 3.3 V, unless otherwise specified.
3. Data based on characterization results, tested in production at VDDmax and fHCLK max.
4. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
VDD is present the Backup Domain is powered by VDD supply).
5. Data based on characterization results, not tested in production.
34/79
STM32F103xx
Electrical characteristics
Figure 14. Current consumption in Stop mode with regulator in Run mode at VDD = 3.3 V to 3.6 V
versus temperature
Stop regulator ON
300
Consumption (µA)
250
200
3.3 V
150
3.6 V
100
50
0
-45
25
70
90
110
Temperature (°C)
Figure 15. Current consumption in Standby mode versus temperature at VDD = 3.3 V to 3.6 V
Standby mode
3.5
Consumption (µA)
3
2.5
2
3.3 V
1.5
3.6 V
1
0.5
0
-45
25
70
90
110
Temperature (°C)
35/79
Electrical characteristics
STM32F103xx
Typical current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load).
●
All peripherals are disabled except if it is explicitly mentioned.
●
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHZ and 2 wait states above).
●
Ambient temperature and VDD supply voltage conditions summarized in Table 7.
●
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
●
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2
Table 15.
Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Symbol
Parameter
External clock(2)
IDD
All
peripherals
enabled
All
peripherals
disabled
72 MHz
36
27
48 MHz
24.2
18.6
36 MHz
19
14.8
24 MHz
12.9
10.1
16 MHz
9.3
7.4
8 MHz
5.5
4.6
4 MHz
3.3
2.8
2 MHz
2.2
1.9
1 MHz
1.6
1.45
500 kHz
1.3
1.25
125 kHz
1.08
1.06
64 MHz
31.4
23.9
48 MHz
23.5
17.9
36 MHz
18.3
14.1
24 MHz
12.2
9.5
16 MHz
8.5
6.8
8 MHz
4.9
4
4 MHz
2.7
2.2
2 MHz
1.6
1.4
1 MHz
1.02
0.9
500 kHz
0.73
0.67
125 kHz
0.5
0.48
Conditions
Supply
current in
Run mode
fHCLK
mA
Running on high speed
internal RC (HSI), AHB
prescaler used to
reduce the frequency
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
36/79
Unit
STM32F103xx
Table 16.
Electrical characteristics
Typical current consumption in Sleep mode, code with data processing
code running from Flash or RAM
Typ(1)
Symbol Parameter
Conditions
External clock
IDD
Supply
current in
Sleep mode
(2)
Fhclk
All peripherals All peripherals
enabled
disabled
72 MHz
14.4
5.5
48 MHz
9.9
3.9
36 MHz
7.6
3.1
24 MHz
5.3
2.3
16 MHz
3.8
1.8
8 MHz
2.1
1.2
4 MHz
1.6
1.1
2 MHz
1.3
1
1 MHz
1.11
0.98
500 kHz
1.04
0.96
125 kHz
0.98
0.95
64 MHz
12.3
4.4
48 MHz
9.3
3.3
36 MHz
7
2.5
4.8
1.8
3.2
1.2
1.6
0.6
1
0.5
0.72
0.47
1 MHz
0.56
0.44
500 kHz
0.49
0.42
125 kHz
0.43
0.41
Unit
mA
24 MHz
Running on high
16 MHz
speed internal RC
(HSI), AHB prescaler 8 MHz
used to reduce the
4 MHz
frequency
2 MHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
37/79
Electrical characteristics
Table 17.
Symbol
IDD
IDD_VBAT
STM32F103xx
Typical current consumption in Standby mode
VDD
Typ(1)
Low-speed internal RC oscillator and
independent watchdog OFF
3.3 V
2
2.4 V
1.5
Supply current in Low-speed internal RC oscillator and
Standby mode(2) independent watchdog ON
3.3 V
3.4
2.4 V
2.6
Low-speed internal RC oscillator ON,
independent watchdog OFF
3.3 V
3.2
2.4 V
2.4
3.3 V
1.4
2.4 V
1.1
Parameter
Backup domain
supply current
Conditions
Unit
µA
Low-speed oscillator and RTC ON
µA
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. To obtain Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator, RTC ON) to IDD
Standby.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed
under the following conditions:
●
all I/O pins are in input mode with a static value at VDD or VSS (no load)
●
all peripherals are disabled unless otherwise mentioned
●
the given value is calculated by measuring the current consumption
●
38/79
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 4
STM32F103xx
Table 18.
Electrical characteristics
Peripheral current consumption(1)
Peripheral
Typical consumption at 25°C
TIM2
1.2
TIM3
1.2
TIM4
0.9
SPI2
0.2
USART2
0.35
USART3
0.35
I2C1
0.39
I2C2
0.39
USB
0.65
CAN
0.715
GPIO A
0.47
GPIO B
0.47
GPIO C
0.47
GPIO D
0.47
GPIO E
0.47
ADC1
1.4
ADC2
1.3
TIM1
1.6
SPI1
0.43
USART1
0.85
Unit
APB1
mA
APB2
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
5.3.6
External clock source characteristics
High-speed external user clock
The characteristics given in Table 19 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 7.
39/79
Electrical characteristics
Table 19.
STM32F103xx
High-speed external (HSE) user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHSE_ext
User external clock source
frequency(1)
8
25
MHz
VHSEH
OSC_IN input pin high level
voltage
0.7VDD
VDD
VHSEL
OSC_IN input pin low level
voltage
VSS
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
16
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1)
V
IL
ns
OSC_IN Input leakage
current
5
VSS ≤VIN ≤VDD
±1
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
40/79
µA
STM32F103xx
Electrical characteristics
Low-speed external user clock
The characteristics given in Table 20 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 7.
Table 20.
Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
fLSE_ext
User External clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
VSS
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
Typ
Max
Unit
32.768
1000
kHz
0.7VDD
VDD
V
tr(LSE)
tf(LSE)
IL
0.3VDD
ns
OSC32_IN rise or fall
time(1)
OSC32_IN Input leakage
current
5
VSS ≤VIN ≤VDD
±1
µA
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
Figure 16. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE)
t
tW(HSE)
THSE
EXTER NAL
CLOCK SOURC E
fHSE_ext
OSC _IN
IL
STM32F103xx
ai14143
41/79
Electrical characteristics
STM32F103xx
Figure 17. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE)
t
TLSE
EXTER NAL
CLOCK SOURC E
fLSE_ext
STM32F103xx
ai14144b
42/79
STM32F103xx
Electrical characteristics
High-speed external clock
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 21. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 21.
Symbol
fOSC_IN
RF
CL1
CL2(2)
i2
gm(4)
HSE 4-16 MHz oscillator characteristics(1)
Parameter
Conditions
Oscillator frequency
Min
Typ
Max
Unit
4
8
16
MHz
Feedback resistor
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
HSE driving current
RS = 30 Ω
200
kΩ
30
pF
VDD= 3.3 V
VIN = VSS with 30 pF
load
Oscillator transconductance
Startup
tSU(HSE)(5) startup time
1
25
mA
mA/V
VSS is stabilized
2
ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board
capacitance).
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. Based on characterization results, not tested in production.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Figure 18. Typical application with a 8-MHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC_IN
8 MH z
resonator
CL2
REXT(1)
RF
OSC_OU T
Bias
controlled
gain
STM32F103xx
ai14145
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
43/79
Electrical characteristics
STM32F103xx
Low-speed external clock
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 22.
LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
CL1
CL2
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(1)
RS = 30 kΩ
15
pF
I2
LSE driving current
VDD = 3.3 V
VIN = VSS
1.4
µA
gm
Oscillator Transconductance
tSU(LSE)(2)
5
5
startup time
VSS is stabilized
MΩ
µA/V
3
s
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details
2.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768
kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Figure 19. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 kH z
resonator
CL2
RF
OSC32_OU T
Bias
controlled
gain
STM32F103xx
ai14146
44/79
STM32F103xx
5.3.7
Electrical characteristics
Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
High-speed internal (HSI) RC oscillator
Table 23.
Symbol
fHSI
HSI oscillator characteristics(1)
Parameter
Conditions
Min
Frequency
ACCHSI Accuracy of HSI oscillator
tsu(HSI)
HSI oscillator start up time
IDD(HSI)
HSI oscillator power
consumption
Typ
Max
8
Unit
MHz
±3(2)
%
±2
%
2
µs
80
100
µA
Min(2)
Typ
Max
Unit
30
40
60
kHz
85
µs
1.2
µA
TA = –40 to 105 °C
±1
at TA = 25°C
1
1. VDD = 3.3 V, TA = −40 to 105 °C unless otherwise specified.
2. Values based on device characterization, not tested in production.
LSI Low Speed Internal RC Oscillator
Table 24.
Symbol
fLSI
LSI oscillator characteristics (1)
Parameter
Conditions
Frequency
tsu(LSI)
LSI oscillator startup time
IDD(LSI)
LSI oscillator power
consumption
0.65
1. VDD = 3 V, TA = −40 to 105 °C unless otherwise specified.
2. Value based on device characterization, not tested in production.
45/79
Electrical characteristics
STM32F103xx
Wakeup time from low power mode
The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 7.
Table 25.
Symbol
Low-power mode wakeup timings(1)
Parameter
Typ
Max
Unit
Wakeup on HSI RC clock
1.8
TBD
µs
Wakeup from Stop mode
(regulator in run mode)
HSI RC wakeup time = 2 µs
3.6
TBD
Wakeup from Stop mode
(regulator in low power mode)
HSI RC wakeup time = 2 µs,
Regulator wakeup from LP
mode time = 5 µs
5.4
9
HSI RC wakeup time = 2 µs,
Regulator wakeup from power
down time = 38 µs
50
150
tWUSLEEP(2) Wakeup from Sleep mode
tWUSTOP(2)
tWUSTDBY(2) Wakeup from Standby mode
Conditions
µs
µs
1. TBD stands for to be determined.
2. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 26.
PLL characteristics
Value
Symbol
Parameter
Test conditions
Min
PLL input clock
fPLL_IN
Max(1)
8.0
Unit
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
72
MHz
tLOCK
PLL lock time
200
µs
1. Data based on device characterization, not tested in production.
46/79
Typ
STM32F103xx
5.3.9
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = −40 to 105 °C unless otherwise specified.
Table 27.
Flash memory characteristics
Max(1)
Unit
20
40
µs
TA = −40 to +105 °C
20
40
ms
TA = −40 to +105 °C
20
40
ms
Read mode
fHCLK = 72 MHz with 2 wait
states, VDD = 3.3 V
20
mA
Write / Erase modes
fHCLK = 72 MHz, VDD = 3.3 V
5
mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
50
µA
3.6
V
Symbol
Parameter
tprog
Word programming time
TA = −40 to +105 °C
Page (1kB) erase time
Mass erase time
tERASE
tME
IDD
Vprog
Supply current
Conditions
Min
Programming voltage
Typ
2
1. Values based on characterization and not tested in production.
Table 28.
Flash memory endurance and data retention
Value
Symbol
Parameter
NEND
Endurance
tRET
Data retention
Conditions
Min(1)
10
TA = 85 °C
30
TA = 105 °C
10
Unit
Typ
Max
kcycles
Years
1. Values based on characterization not tested in production.
47/79
Electrical characteristics
5.3.10
STM32F103xx
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 29. They are based on the EMS levels and classes
defined in application note AN1709.
Table 29.
EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK=48 MHz
induce a functional disturbance
conforms to IEC 1000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
VDD = 3.3 V, TA = +25 °C,
applied through 100pF on VDD and VSS pins fHCLK = 48 MHz
to induce a functional disturbance
conforms to IEC 1000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
48/79
STM32F103xx
Electrical characteristics
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.
Table 30.
Symbol
SEMI
EMI characteristics
Parameter
Peak level
Conditions
Monitored
Frequency Band
0.1 to 30 MHz
VDD = 3.3 V, TA = 2 5 °C,
30 to 130 MHz
LQFP100 package
compliant with SAE J
130 MHz to 1GHz
1752/3
SAE EMI Level
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz 8/72 MHz
12
12
22
19
23
29
4
4
dBµV
-
49/79
Electrical characteristics
5.3.11
STM32F103xx
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 31.
ESD absolute maximum ratings(1)
Symbol
Ratings
Conditions
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C
conforming to
JESD22-A114
TA = +25 °C
conforming to
JESD22-C101
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
Class
Maximum value(2)
2
Unit
2000
V
II
500
1. TBD stands for to be determined.
2. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 32.
Symbol
LU
50/79
Electrical sensitivities
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
Class
II level A
STM32F103xx
5.3.12
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under the conditions summarized in Table 7. All I/Os are CMOS and TTL
compliant.
All unused pins must be configured in either of the three modes below:
●
as outputs with an external pull-up or pull-down resistor and held at a fixed voltage (see
Figure 20)
●
as push-pull outputs with 0 written into the data register
●
or as analog inputs
Table 33.
Symbol
VIL
I/O static characteristics
Parameter
Conditions
Input low level voltage(1)
Standard IO input high level
voltage(1)
VIH
Input low level voltage(1)
VIH
Input high level voltage(1)
Ilkg
2
VDD+0.5
2
5.5V
–0.5
0.35 VDD
0.65 VDD
VDD+0.5
Unit
V
CMOS ports
IO FT Schmitt trigger voltage
hysteresis(3)
Input leakage current
Max
0.8
TTL ports
Standard IO Schmitt trigger
voltage hysteresis(3)
(5)
Typ
–0.5
IO FT(2) input high level
voltage(1)
VIL
Vhys
Min
V
200
mV
5% VDD(4)
mV
VSS ≤VIN ≤VDD
Standard I/Os
±1
VIN= 5 V
I/O FT
3
µA
RPU
Weak pull-up equivalent
resistor(6)
VIN = VSS
30
40
50
kΩ
RPD
Weak pull-down equivalent
resistor(6)
VIN = VDD
30
40
50
kΩ
CIO
I/O pin capacitance
5
pF
1. Values based on characterization results, and not tested in production.
2. FT = Five-volt tolerant.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. With a minimum of 100 mV.
5. Leakage could be higher than max. if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
51/79
Electrical characteristics
STM32F103xx
Figure 20. Unused I/O pin connection
VDD
1 0 kΩ
STM32F103xx
UNU SED I/O PORT
STM32F103xx
UNU SED I/O PORT
1 0 kΩ
ai14147b
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed VOL).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
52/79
●
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 5).
●
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 5).
STM32F103xx
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7. All I/Os are CMOS and TTL compliant.
Table 34.
Symbol
Output voltage characteristics
Parameter
VOL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
VOL (1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH (2)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
VOL(1)(3)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
VOL(1)(3)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Conditions
TTL port
IIO = +8 mA
2.7 V < VDD < 3.6 V
CMOS port
IIO =+ 8mA
2.7 V < VDD < 3.6 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
IIO = +6 mA
2 V < VDD < 2.7 V
Min
Max
Unit
0.4
V
VDD–0.4
0.4
V
2.4
1.3
V
VDD–1.3
0.4
V
VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 5
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
3. Based on characterization data, not tested in production.
53/79
Electrical characteristics
STM32F103xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 21 and
Table 35, respectively.
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
Table 35.
MODEx[1:0]
bit value(1)
I/O AC characteristics(1)
Symbol
Parameter
Conditions
Min
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
10
tf(IO)out
Output high to low
level fall time
tr(IO)out
Output low to high
level rise time
tf(IO)out
Output high to low
level fall time
tr(IO)out
Output low to high
level rise time
Fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
-
tEXTIpw
frequency(2)
Output high to low
level fall time
Output low to high
level rise time
Unit
2
MHz
125(3)
CL = 50 pF, VDD = 2 V to 3.6 V
ns
125(3)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
01
Max
10
MHz
25(3)
CL = 50 pF, VDD = 2 V to 3.6 V
ns
25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
50
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
30
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
20
MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
Pulse width of
external signals
detected by the EXTI
controller
10
ns
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 21.
3. Values based on design simulation and validated on silicon, not tested in production.
54/79
STM32F103xx
Electrical characteristics
Figure 21. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXT ERNAL
OUTPUT
ON 50pF
tr(I O)out
tr(I O)out
T
Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 33).
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
Table 36.
Symbol
NRST pin characteristics
Parameter
Conditions
Min
Typ
Max
VIL(NRST)
NRST Input low level voltage
–0.5
0.8
VIH(NRST)
NRST Input high level voltage
2
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
RPU
Unit
V
Weak pull-up equivalent resistor(1)
200
VIN = VSS
30
(2)
VF(NRST)
NRST Input filtered pulse
VNF(NRST)
NRST Input not filtered pulse(2)
300
40
50
kΩ
100
ns
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Values guaranteed by design, not tested in production.
55/79
Electrical characteristics
STM32F103xx
Figure 22. Recommended NRST pin protection
VDD
External
reset circuit(1)
NRST(2)
RPU
Internal Reset
FILTER
0.1 µF
STM32F10xxx
ai14132b
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 36. Otherwise the reset will not be taken into account by the device.
5.3.14
TIM timer characteristics
The parameters given in Table 37 are guaranteed by fabrication.
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 37.
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
TIMx(1) characteristics
Parameter
Conditions
Min
Max
1
tTIMxCLK
13.9
ns
Timer resolution time
fTIMxCLK = 72 MHz
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz
0
fTIMxCLK/2
MHz
0
36
MHz
16
bit
65536
tTIMxCLK
910
µs
65536 × 65536
tTIMxCLK
59.6
s
Timer resolution
16-bit counter clock period
1
when internal clock is
fTIMxCLK = 72 MHz 0.0139
selected
tMAX_COUNT Maximum possible count
fTIMxCLK = 72 MHz
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
56/79
Unit
STM32F103xx
5.3.15
Electrical characteristics
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 38 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
summarized in Table 7.
The STM32F103xx performance line I2C interface meets the requirements of the standard
I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. In addition, there is a protection
diode between the I/O pin and VDD. As a consequence, when multiple master devices are
connected to the I2C bus, it is not possible to power off the STM32F103xx while another I2C
master node remains powered on. Otherwise, the STM32F103xx would be powered by the
protection diode.
The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 38.
I2C characteristics
Standard mode I2C(1)
Symbol
Fast mode I2C(1)(2)
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(3)
0(4)
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb
300
th(STA)
Start condition hold time
4.0
0.6
tsu(STA)
Repeated Start condition
setup time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
µs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
1.3
µs
Cb
Capacitive load for each bus
line
µs
ns
µs
400
400
pF
1. Values based on standard I2C protocol requirement, not tested in production.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
57/79
Electrical characteristics
STM32F103xx
Figure 23. I2C bus AC waveforms and measurement circuit
VDD
VDD
4 .7 kΩ
4 .7 kΩ
100Ω
STM32F103xx
SDA
I2C bus
100Ω
SCL
S TART REPEATED
S TART
S TART
tsu(STA)
SDA
tf(SDA)
tr(SDA)
tw(SCKL)
th(STA)
SCL
tw(SCKH)
tsu(SDA)
tr(SCK)
th(SDA)
tsu(STA:STO)
S TOP
tsu(STO)
tf(SCK)
ai14149b
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 39.
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)(3)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
TBD
300
TBD
200
TBD
100
TBD
50
TBD
20
TBD
1. TBD = to be determined.
2. RP = External pull-up resistance, fSCL = I2C speed,
3. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
58/79
STM32F103xx
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 7.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40.
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
SPI characteristics(1)
Parameter
Conditions
Min
Max
Master mode
TBD
TBD
Slave mode
0
TBD
SPI clock frequency
SPI clock rise and fall
time
MHz
Capacitive load: C=50 pF
TBD
tsu(NSS)(2)
NSS setup time
Slave mode
0
th(NSS)(2)
NSS hold time
Slave mode
0
Master mode, fPCLK= TBD,
presc = TBD
TBD
Master mode
TBD
Slave mode
TBD
Master mode
TBD
Slave mode
TBD
Master mode, fPCLK= TBD
TBD(3)
Slave mode, fPCLK= TBD
TBD(3)
Slave mode
TBD
TBD
Slave mode, fPCLK= TBD
TBD
TBD
Slave mode
TBD
TBD
(2)
SCK high and low
tw(SCKH)
tw(SCKL)(2) time
tsu(MI) (2)
tsu(SI)(2)
th(MI) (2)
th(SI)(2)
Data input setup time
Data input hold time
ta(SO)(2)(4)
Data output access
time
tdis(SO)(2)(5)
Data output disable
time
tv(SO) (2)(1) Data output valid time
tv(MO)
(2)(1)
Data output valid time
th(SO)(2)
th(MO)(2)
Unit
Data output hold time
ns
Slave mode (after enable edge)
TBD
fPCLK= TBD
TBD
Master mode (after enable
edge)
TBD
fPCLK= TBD
TBD
Slave mode (after enable edge)
TBD
Master mode (after enable
edge)
TBD
TBD
1. TBD = to be determined.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
59/79
Electrical characteristics
STM32F103xx
Figure 24. SPI timing diagram - slave mode and CPHA = 0
NSS input
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
LSB IN
B I T1 IN
th(SI)
ai14134
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Figure 25. SPI timing diagram - slave mode and CPHA = 11)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
M SB IN
B I T1 IN
LSB IN
ai14135
60/79
STM32F103xx
Electrical characteristics
Figure 26. SPI timing diagram - master mode
High
NSS input
SCK Input
CPHA= 0
CPOL=0
SCK Input
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tsu(MI)
MISO
INP UT
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 41.
USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1)
Unit
Input levels
VDI
Differential input sensitivity
I(USBDP, USBDM)
0.2
VCM
Differential common mode
range
Includes VDI range
0.8
2.5
VSE
Single ended receiver
threshold
1.3
2.0
V
Output levels
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(2)
RL of 15 kΩ to
VSS(2)
0.3
V
2.8
3.6
1. All the voltages are measured from the local ground potential.
2. RL is the load connected on the USB drivers
61/79
Electrical characteristics
STM32F103xx
Figure 27. USB timings: definition of data signal rise and fall time
Crossover
points
Differen tial
data lines
VCRS
VS S
Table 42.
tf
tr
ai14137
USB: Full speed electrical characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(1)
CL = 50 pF
4
20
ns
tf
Time(1)
CL = 50 pF
4
20
ns
tr/tf
90
110
%
1.3
2.0
V
Driver characteristics
Fall
trfm
Rise/ fall time matching
VCRS
Output signal crossover voltage
1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
5.3.16
CAN (controller area network) interface
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (CANTX and CANRX).
62/79
STM32F103xx
5.3.17
Electrical characteristics
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 7.
Note:
It is recommended to perform a calibration after each power-up.
Table 43.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
ADC power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
ADC clock frequency
0.6
14
MHz
0.05
1
MHz
823
kHz
17
1/fADC
VDDA or
VREF+
V
fADC
fS
Sampling rate
fTRIG
External trigger frequency
VAIN
Conversion voltage range(1)
RAIN
External input impedance
Ilkg
TBD
fADC = 14 MHz
0 (VSSA or VREFtied to ground)
See Equation 1 and Table 44
Negative input leakage current VIN < VSS, | IIN | < 400 µA
on analog pins
on adjacent analog pin
5
kΩ
6
µA
RADC
Sampling switch resistance
1
kΩ
CADC
Internal sample and hold
capacitor
5
pF
tCAL
Calibration time
fADC = 14MHz
tlat
Injection trigger conversion
latency
fADC = 14 MHz
tlatr
Regular trigger conversion
latency
fADC = 14 MHz
tS
Sampling time
fADC = 14 MHz
tSTAB
Power-up time
tCONV
Total conversion time
(including sampling time)
µs
83
1/fADC
0.228
µs
3(2)
fADC
0.228
µs
(2)
fADC
2
0.107
17.1
µs
1.5
239.5
1/fADC
1
µs
18
µs
0
1
fADC = 14 MHz
5.9
0
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pin descriptions for further details.
2. For internal triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 43.
63/79
Electrical characteristics
STM32F103xx
Equation 1: RAIN max formula:
t
S
R AIN < --------------------------------------------------------------- – R ADC
N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 44.
RAIN max for fADC = 14 MHz
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.11
1.2
7.5
0.54
10
13.5
0.96
19
28.5
2.04
41
41.5
2.96
60
55.5
3.96
80
71.5
5.11
104
239.5
17.1
350
Table 45.
ADC accuracy(1)
Symbol
ET
Parameter
Total unadjusted error(3)
error(3)
EO
Offset
EG
Gain error(3)
ED
EL
Differential linearity
Integral linearity
error(3)
error(3)
Test conditions
fPCLK2 = 28 MHz,
fADC = 14 MHz,
RAIN <10 kΩ,
VDDA = 2.4 V to 3.6 V)
Measurements made
after ADC calibration
Typ(2)
Max(2)
3
5
1
3
1
±2
3
3
2
4
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Data based on characterization, not tested in production.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
64/79
STM32F103xx
Electrical characteristics
Figure 28. ADC accuracy characteristics
V
V
[1LSBIDEAL = REF+ (or DDA depending on package)]
4096
4096
EG
4095
4094
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4093
(2)
ET
(3)
7
(1)
6
5
4
EO
EL
3
ED
2
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
ai14395b
Figure 29. Typical connection diagram using the ADC
VDD
RAIN(1)
VAIN
STM32F103xx
VT
0.6 V
AINx
CAIN
VT
0.6 V
RADC(1)
IL±1 µA
12-bit A/D
conversion
CADC(1)
ai14150b
1. Refer to Table 43 for the values of CAIN, RAIN, RADC and CADC.
2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 30 or Figure 31,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
65/79
Electrical characteristics
STM32F103xx
Figure 30. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+
(see note 1)
1 µF // 10 nF
VDDA
1 µF // 10 nF
VSSA /VREF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Figure 31. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F103xx
VREF+/VDDA
(See note 1)
1 µF // 10 nF
VREF–/VSSA
(See note 1)
ai14389
1. VREF+ and VREF– inputs are available only on 100-pin packages.
66/79
STM32F103xx
5.3.18
Electrical characteristics
Temperature sensor characteristics
Table 46.
TS characteristics
Symbol
Parameter
TL
VSENSE linearity with temperature
±1.5
°C
Average slope
4.478
mV/°C
1.4
V
Avg_Slope
V25
tSTART
TS_temp(1)
Conditions
Min
Voltage at 25 °C
Startup time
ADC sampling time when reading
the temperature
Typ
4
2.2
Max
Unit
10
µs
17.1
µs
1. Shortest sampling time can be determined in the application by multiple iterations.
67/79
Package characteristics
6
STM32F103xx
Package characteristics
In order to meet environmental requirements, ST offers the STM32F103xx in ECOPACK®
packages. These packages have a lead-free second-level interconnect. The category of
second-level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 32. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline
Seating plane
C
ddd
C
A2 A
A1
A3
D
Pin # 1 ID
R = 0.20
e
36
28
27
E2
1
b
E
9
19
18
10
D2
L
ZR_ME
1. Drawing is not to scale.
Table 47.
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
0.800
0.900
1.000
0.0315
0.0354
0.0394
A1
0.020
0.050
0.0008
0.0020
A2
0.650
1.000
0.0256
0.0394
A3
0.250
A
0.0098
b
0.180
0.230
0.300
0.0071
0.0091
0.0118
D
5.875
6.000
6.125
0.2313
0.2362
0.2411
D2
1.750
3.700
4.250
0.0689
0.1457
0.1673
E
5.875
6.000
6.125
0.2313
0.2362
0.2411
E2
1.750
3.700
4.250
0.0689
0.1457
0.1673
e
0.450
0.500
0.550
0.0177
0.0197
0.0217
L
0.350
0.550
0.750
0.0138
0.0217
0.0295
ddd
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
68/79
0.0031
STM32F103xx
Package characteristics
Figure 33. LFBGA100 - low profile fine pitch ball grid array package outline
C
Seating plane
ddd C
A2 A4 A3
A1
A
D
B
D1
F
e
A
K
J
H
G
F
E
D
C
B
A
F
E1
E
e
1 2 3 4 5 6 7 8 9 10
A1 corner index area
(see note 5)
∅b (100
balls)
∅eee
M C A B
∅ fff M C
Bottom view
ai14396
1. Drawing is not to scale.
Table 48.
LFBGA100 - low profile fine pitch ball grid array package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
A1
Max
Min
Typ
1.700
Max
0.0669
0.270
0.0106
A2
1.085
0.0427
A3
0.30
0.0118
A4
0.80
0.0315
b
0.45
0.50
0.55
0.0177
0.0197
0.0217
D
9.85
10.00
10.15
0.3878
0.3937
0.3996
D1
E
7.20
9.85
10.00
0.2835
10.15
0.3878
0.3937
E1
7.20
0.2835
e
0.80
0.0315
F
1.40
0.0551
0.3996
ddd
0.12
0.0047
eee
0.15
0.0059
fff
0.08
0.0031
N (number of balls)
100
1. Values in inches are converted from mm and rounded to 4 decimal digits.
69/79
Package characteristics
STM32F103xx
Figure 34. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Dpad
0.37 mm
0.52 mm typ. (depends on solder
Dsm
mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
70/79
STM32F103xx
Package characteristics
Figure 35. LQFP100 – 100-pin low-profile quad flat package outline
A
D
D1
A2
A1
b
e
E1
E
c
L1
L
h
ai14397
1. Drawing is not to scale.
Table 49.
LQFP100 – 100-pin low-profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
C
0.09
Max
0.0025
0.15
0.0001
0.0002
1.40
1.45
0.0021
0.0022
0.0022
0.22
0.27
0.0003
0.0004
0.0004
0.20
0.0002
0.0003
D
16.00
0.0248
D1
14.00
0.0217
E
16.00
0.0248
E1
14.00
0.0217
e
0.50
0.0008
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0007
0.0009
0.0012
L1
1.00
0.0015
Number of pins
N
100
1. Values in inches are converted from mm and rounded to 4 decimal digits.
71/79
Package characteristics
STM32F103xx
Figure 36. LQFP64 – 64 pin low-profile quad flat package outline
D
A
D1
A2
A1
b
E1
E
e
c
L1
L
ai14398
1. Drawing is not to scale.
Table 50.
LQFP64 – 64 pin low-profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
Max
0.0025
0.15
0.0001
0.0002
1.40
1.45
0.0021
0.0022
0.0022
0.22
0.27
0.0003
0.0004
0.0004
0.20
0.0002
0.0003
D
12.00
0.0186
D1
10.00
0.0155
E
12.00
0.0186
E1
10.00
0.0155
e
0.50
0.0008
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0007
0.0009
0.0012
L1
1.00
0.0015
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
72/79
Typ
STM32F103xx
Package characteristics
Figure 37. LQFP48 – 48 pin low-profile quad flat package outline
D
A
D1
A2
A1
b
E1
e
E
c
L1
L
ai14399
1. Drawing is not to scale.
Table 51.
LQFP48 – 48 pin low-profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
C
0.09
Max
0.0025
0.15
0.0001
0.0002
1.40
1.45
0.0021
0.0022
0.0022
0.22
0.27
0.0003
0.0004
0.0004
0.20
0.0002
0.0003
D
9.00
0.0139
D1
7.00
0.0109
E
9.00
0.0139
E1
7.00
0.0109
e
0.50
0.0008
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0007
0.0009
0.0012
L1
1.00
0.0015
Number of pins
N
48
1. Values in inches are converted from mm and rounded to 4 decimal digits.
73/79
Package characteristics
6.1
STM32F103xx
Thermal characteristics
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the
following equation:
TJ = TA + (PD x ΘJA)
(1)
Where:
●
TA is the Ambient Temperature in ° C,
●
ΘJA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
●
PD is the sum of PINT and PI/O (PD = PINT + PI/O),
●
PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power.
PI/O represents the Power Dissipation on Input and Output Pins;
Most of the time for the application PI/O < PINT and can be neglected. On the other hand, PI/O
may be significant if the device is configured to drive continuously external modules and/or
memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
(2)
Therefore (solving equations 1 and 2):
K = PD x (TA + 273°C) + ΘJA x PD2
(3)
where:
K is a constant for the particular part, which may be determined from equation (3) by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
may be obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 52.
Symbol
ΘJA
74/79
Thermal characteristics
Parameter
Value
Thermal resistance junction-ambient
LFBGA100 - 10 x 10 mm / 0.5 mm pitch
41
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
46
Thermal Resistance Junction-Ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
55
Unit
°C/W
STM32F103xx
7
Order codes
Order codes
Table 53.
Order codes
Part number
Flash program
memory
(Kbytes)
SRAM
memory
(Kbytes)
STM32F103C6T6
32
10
STM32F103C8T6
64
20
STM32F103CBT6
128
20
STM32F103R6T6
32
10
STM32F103R8T6
64
20
STM32F103RBT6
128
20
STM32F103V8T6
64
20
STM32F103VBT6
128
20
STM32F103V8H6
64
20
STM32F103VBH6
128
20
STM32F103T6U6
32
6
STM32F103T8U6
64
10
Package
LQFP48
LQFP64
LQFP100
LFBGA100
VFQFPN36
7.1
Future family enhancements
Further developments of the STM32F103xx performance line will see an expansion of the
current options. Larger packages will soon be available with up to 512KB Flash, 64KB
SRAM and with extended features such as EMI support, SDIO, I2S, DAC and additional
timers and USARTS.
75/79
Important notes
Appendix A
STM32F103xx
Important notes
The notes listed below apply to STM32F103xx devices Revision Z. For more details on how
to identify the device Revision, please refer to section 20.6.1 MCU device ID code in the
STM32F10xxx reference manual.
A.1
PD0 and PD1 use in output mode
The use of PD0 and PD1 in output mode is limited as in this mode, PD0 and PD1 can only
be used at 50 MHz.
A.2
ADC auto-injection channel
When the ADC clock prescaler ranges from 4 to 8, a delay of 1 ADC clock period is
automatically inserted when switching from regular to injected conversion (and conversely,
from injected to regular). When the ADC clock prescaler is set to 2, the delay is 2 ADC clock
periods.
A.3
ADC combined injected simultaneous + interleaved
When the ADC clock prescaler is set to 4, the interleaved mode does not recover with
evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6
ADC clock periods, instead of 7 clock periods followed by 7 clock periods.
A.4
Voltage glitch on ADC input 0
A low-amplitude voltage glitch can be generated on ADC input 0, when the ADC is
converting with injection trigger, in very specific cases.
It is generated by internal coupling and synchronized to the beginning and the end of the
injection sequence, whatever the channel(s) to be converted.
It has an amplitude of less than 150 mV and a typical duration of 10 ns (measured with the
I/O left unconnected). This has no influence on the digital output signals or the digital inputs,
providing that they are driven with a reasonably low impedance.
76/79
STM32F103xx
8
Revision history
Revision history
Table 54.
Document revision history
Date
Revision
01-jun-2007
1
Initial release.
2
Flash memory size modified in Note 5, Note 4, Note 6, Note 7 and
BGA100 pins added to Table 3: Pin definitions. Figure 6:
STM32F103xx performance line BGA100 ballout added.
THSE changed to TLSE in Figure 17: Low-speed external clock source
AC timing diagram. VBAT ranged modified in Power supply schemes.
tSU(LSE) changed to tSU(HSE) in Table 21: HSE 4-16 MHz oscillator
characteristics. IDD(HSI) max value added to Table 23: HSI oscillator
characteristics.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 °C and 85 °C conditions removed and class name modified
in Table 32: Electrical sensitivities. RPU and RPD min and max values
added to Table 33: I/O static characteristics. RPU min and max values
added to Table 36: NRST pin characteristics.
Figure 23: I2C bus AC waveforms and measurement circuit and
Figure 22: Recommended NRST pin protection corrected.
Notes removed below Table 7, Table 36, Table 41.
IDD typical values changed in Table 11: Maximum current consumption
in Run and Sleep modes. Table 37: TIMx characteristics modified.
tSTAB, VREF+ value, tlat and fTRIG added to Table 43: ADC
characteristics.
In Table 28: Flash memory endurance and data retention, typical
endurance and data retention for TA = 85 °C added, data retention for
TA = 25 °C removed.
VBG changed to VREFINT in Table 10: Embedded internal reference
voltage. Document title changed. Controller area network (CAN)
section modified.
Figure 10: Power supply scheme modified.
Features on page 1 list optimized. Small text changes.
20-Jul-2007
Changes
77/79
Revision history
STM32F103xx
Table 54.
Document revision history
Date
18-Oct-2007
78/79
Revision
Changes
3
STM32F103CBT6, STM32F103T6 and STM32F103T8 root part
numbers added (see Table 2: Device features and peripheral counts
(STM32F103xx performance line))
VFQFPN36 package added (see Section 6: Package characteristics).
All packages are ECOPACK® compliant. Package mechanical data
inch values are calculated from mm and rounded to 4 decimal digits
(see Section 6: Package characteristics).
Table 3: Pin definitions updated and clarified.
Table 25: Low-power mode wakeup timings updated.
TA min corrected in Table 10: Embedded internal reference voltage.
Note 4 added below Table 21: HSE 4-16 MHz oscillator characteristics.
VESD(CDM) value added to Table 31: ESD absolute maximum ratings.
Note 3 added and VOH parameter description modified in Table 34:
Output voltage characteristics.
Note 1 modified under Table 35: I/O AC characteristics.
Equation 1 and Table 44: RAIN max for fADC = 14 MHz added to
Section 5.3.17: 12-bit ADC characteristics.
VAIN, tS max, tCONV, VREF+ min and tlat max modified, notes modified
and tlatr added in Table 43: ADC characteristics.
Figure 28: ADC accuracy characteristics updated. Note 1 modified
below Figure 29: Typical connection diagram using the ADC.
Electrostatic discharge (ESD) on page 50 modified.
Number of TIM4 channels modified in Figure 1: STM32F103xx
performance line block diagram.
Maximum current consumption Table 11, Table 12 and Table 13
updated. Vhysmodified in Table 33: I/O static characteristics.
Table 45: ADC accuracy updated. tVDD modified in Table 8: Operating
conditions at power-up / power-down. VFESD value added in Table 29:
EMS characteristics.
Values corrected, note 2 modified and note 3 removed in Table 25:
Low-power mode wakeup timings.
Table 14: Typical and maximum current consumptions in Stop and
Standby modes: Typical values added for VDD/VBAT = 2.4 V, Note 5
modified, Note 3 added.
Table 17: Typical current consumption in Standby mode added. On-chip
peripheral current consumption on page 38 added.
ACCHSI values updated in Table 23: HSI oscillator characteristics.
Vprog added to Table 27: Flash memory characteristics.
Upper option byte address modified in Figure 7: Memory map.
Typical fLSI value added in Table 24: LSI oscillator characteristics and
internal RC value corrected from 32 to 40 kHz in entire document.
TS_temp added to Table 46: TS characteristics. NEND modified in
Table 28: Flash memory endurance and data retention.
TS_vrefint added to Table 10: Embedded internal reference voltage.
Handling of unused pins specified in General input/output
characteristics on page 51. All I/Os are CMOS and TTL compliant.
Figure 30: Power supply and reference decoupling (VREF+ not
connected to VDDA) modified.
tJITTER and fVCO removed from Table 26: PLL characteristics.
Appendix A: Important notes on page 76 added.
Added Figure 12, Figure 13, Figure 14 and Figure 15.
STM32F103xx
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
79/79
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement