APPLICATION BULLETIN
®
Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (602) 746-1111 • Twx: 910-952-111 • Telex: 066-6491 • FAX (602) 889-1510 • Immediate Product Info: (800) 548-6132
BURR-BROWN
SPICE BASED MACROMODELS, REV. F
By Hubert Biagi, R. Mark Stitt, Bonnie Baker, and Stephan Baier
INTRODUCTION
Computer based simulation has an importance because it can
significantly reduce the development time and therefore
speed up the time-to-market process. The increased use of
SPICE based simulation software has created a rising demand for accurate models. Such models, or macromodels,
should reflect the actual performance of the component, but
without carrying the burden of too many circuit details,
which can lead to convergence problems. BURR-BROWN
has responded to this need and provides macromodels for a
broad range of semiconductor products. This Application
Bulletin, and the accompanying disk is a collection of
SPICE models of BURR-BROWN op amps, difference
amps, instrumentation amps, isolation amps, and analog
function circuits. There are four different levels of model
topologies used, which are:
Level I:
simplified circuit models produce the most accurate simulation results, but because of the complexity, require longer
simulation time. See Section D for a detailed discussion on
these models.
For a complete overview of all available macromodels on
the disk see Table XI on the last page.
DISKETTE INFORMATION
The disk has four different subdirectories, in which the
models are organized according to their topology level:
A:\
CIR_MOD
ENH_MOD
MPZ_MOD
STD_MOD
Standard Macromodel
Level II: Enhanced Macromodel
Level III: Multi-Pole/Zero Macromodel
Level IV: Simplified Circuit Model
• The standard op amp macromodels were derived using the
MicroSim Corporation PSpice® Parts™ simulation software.
A detailed description on this macromodel type is given in
Section A.
• The second level of macromodel is an enhanced version of
the standard model, which is indicated by the suffix “E” in
the model’s name. This model type is included to offer the
circuit designer a model with a higher level of accuracy. See
Section B for details.
• The Multiple-Pole/Zero macromodel uses the same input
stage as the standard or enhanced op amp macromodel, but
has multiple poles and pole/zero pairs in the mid-section.
This model has the designation “M”, and was used for
wide bandwidth op amps and function circuits where this
topology showed an advantage over the standard topology.
For a detailed description see Section C.
• In some instances, a fourth type of model is available,
which are designated by either an “X”, “X1”, or an “X2”
suffix. The model of this level is not a macromodel, but
rather a simplified circuit model at the transistor level. The
Here, the Standard macromodels (Level I) are found in the
STD_MOD subdirectory. The Enhanced macromodels
(Level II) are found in the ENH_MOD subdirectory. The
Multi-Pole/Zero macromodels (Level III) are found in the
MPZ_MOD subdirectory, and the Simplified circuit models
(Level IV) are found in the CIR_MOD subdirectory. Examples of model files are shown in Table I. This application
bulletin and the macromodel disk are being revised frequently. To obtain the latest revision please contact your
nearest sales office. Each model net-list starts with a header
containing the part number, revision information, and the
license statement. It should be noted that the disk contains
only the net-lists of the macromodels, and does not provide
the simulation software that allows the user to run the
models. The structure of the net-lists conforms to the standard SPICE format, which most SPICE based simulators
will accept. Please refer to the individual software manual if
conflicts are encountered. Burr-Brown also welcomes any
comments, which may be sent to the Applications Department at the address given above.
FILE NAME
DESCRIPTION
OPA111.MOD
OPA111E.MOD
OPA671M.MOD
OPA603X.MOD
OPA111
OPA111
OPA671
OPA603
Standard Op Amp Macromodel
Enhanced Op Amp Macromodel
Multiple Pole/Zero Macromodel
Simplified Circuit Model
TABLE I. Examples of Files on Macromodel Disk.
PSpice® PartsTM, MicroSim Corp.
©
1990 Burr-Brown Corporation
SBFA009
AB-020F
Printed in U.S.A. January, 1995
GENERAL INFORMATION
PREFIX
C
D
E
F
G
H
I
J
Q
R
S
V
Throughout this application bulletin and the net-lists of the
macromodels, standard definitions and designators are used.
As a reference they are listed in the following tables. Table
II and Table III specifically refer to the Standard and the
Enhanced macromodel only. Listed in Table IV are the
definitions for all used component prefixes.
COMPONENT
DESCRIPTION
C1
C2
CEE, CSS
DP
EGND
FB
Phase-Control Capacitor
Compensation Capacitor
Slew-Rate Limiting Capacitor
Substrate Junction
Voltage-Controlled Voltage Source
Output Device (Controlled by the Current Through VB,
VC, VE, and VLP, VLN)
Input Bias Current Correction
Interstage Transconductance (Controlled by Differential
Voltage at the Input Device Loads)
Common-Mode Transconductance (Controlled by the
Common-Mode Voltage at the Input Device Emitters
or Sources)
Input Stage Current
Voltage-Limiting Device
JFET Input Transistors
Bipolar Input Transistors
Interstage Resistance
Input-Stage Load Resistance
Input-Stage Load Resistance
Input-Stage Emitter Resistance
Input-Stage Current-Source Output Resistance
Output Resistors
Power Dissipation Resistor
Independent Voltage Source
Output Offset Limiter (to V+)
Output Offset Limiter (to V–)
Output Current Limiting Sensor
Negative Supply Limit
Positive Supply Limit
G11,G21
GA
GCM
IEE, ISS
HLIM
J1, J2
Q1, Q2
R2
RC1, RC2
RD1, RD2
RE1, RE2
REE, RSS
RO1, RO2
RP
VB
VC, DC
VE, DE
VLIM
VLN, DLN
VLP, DLP
DEFINITION
Capacitor
Diode
Voltage-Controlled Voltage Source
Current-Controlled Current Source
Voltage-Controlled Current Source
Current-Controlled Voltage Source
Independent Current Source or Stimulus
JFET Transistor
Bipolar Transistor
Resistor
Voltage-Controlled Switch
Independent Voltage Source or Stimulus
TABLE IV. Macromodel Component Prefix Definitions.
LIMITATIONS
These macromodels are intended to help designers simulate
typical amplifier performance. The macromodels were compiled using data sheet typical specifications. Where data
sheet specifications were not available, typical measured
values or design values were used. Macromodels were
verified with several standard simulations such as gainphase and large- and small-signal transient response. In
some cases, adjustments were made to the macromodels so
simulations with the macromodel more closely agreed with
actual measured typical performance.
Since these macromodels only simulate the typical performance of certain selected specifications, they will not predict actual device performance under all conditions. Good
design practice dictates that, in addition to simulation with
macromodels, circuit verification must include:
1) worst case analysis with data sheet minimum and maximum room temperature specifications
2) worst case analysis with variation of specifications over
the operating temperature range
TABLE II. Op Amp Macromodel Components for the
Standard and Enhanced Macromodels.
3) thorough breadboard evaluation
4) complete prototype characterization
BURR-BROWN
SYMBOL
MACROMODEL
DESIGNATION
V+, V–
+VPWR, –VPWR
+VOUT, –VOUT
SR+
SR–
+SR
–SR
Pd
IB
Av–dc
F–0dB
CMRR
Phi
Ro-dc
Ro-ac
Ios
Cc
IB
AOL
UGBW
CMRR
øM
rO
zO
ISC
CC
DEFINITION
DUAL AND QUAD OP AMPS
All op amps are modeled as single devices. To model duals
or quads, use two or four models. Quiescent current for the
dual or quad op amp macromodel is the dual or quad op amp
quiescent current divided by two or four.
Positive, Negative Power Supply
Max Positive, Negative Output
Swing
Positive-Going Slew Rate
Negative-Going Slew Rate
Quiescent Power Dissipation
Input Bias Current
DC Open-Loop Voltage Gain
Unity-Gain Frequency
Common-Mode Rejection Ratio
Phase Margin at F-0dB (°)
DC Output Resistance
AC Output Resistance
Short-Circuit Output Current
Compensation Capacitance
INSTRUMENTATION AMPLIFIERS
AND DIFFERENCE AMPLIFIERS
Instrumentation amplifier and difference amplifier
macromodels use standard op amp macromodels plus additional components as shown in Figures 1 and 2. There are
two types of models used for difference amplifiers. They are
the four-resistor difference amplifier and the five-resistor
difference amplifier.
TABLE III. PSpice Parts Inputs for Standard and
Enhanced Marcomodels.
FOUR-RESISTOR DIFFERENCE AMPLIFIER
The four-resistor difference amplifier macromodel, used for
the INA105, INA106, and the difference amplifier section in
all instrumentation amplifier macromodels, is shown in
2
Figure 1a. The circuit uses an op amp and four matched
resistors. If R2/R1 = R4/R3, GAIN = R2/R1 and CMR = ∞. To
simulate DC CMR error, R2 is set 0.01% low. CMR for a
four resistor difference amplifier is:
CMR = –20 LOG10 [(%/100) • R1/(R1 + R2)]
V+
2
3
Ref B
1
3
2
–In
A1
3
C2
A3
R1
R G1
9
4
R4
C2
5
VO
14
Ref
8
R4
FIGURE 1b. INA117 High Voltage Difference Amplifier
Macromodel and Node Assignments.
Sense
R3
Ref A
V–
9
–In
1
14
R3
VO
5
V+
R2
13
A3
9
4
+In
V+
+In
C2
R5
With a 0.01% resistor error, DC CMR for the INA105 unity
gain difference amplifier is 86dB, and DC CMR for the
INA106 gain-of-ten difference amplifier is 100.8dB.
To simulate AC CMR error, a small value capacitor, C2, is
placed in parallel with R2 to roll-off of CMR with increasing
frequency.
2
R2
13
–In
Where:
% = % error in any resistor.
R1
R1
8
R FB1
13
11
R2
Ref
C C1
RG
V–
A3
C C2
FIGURE 1a. Difference Amp Macromodel and Node Assignments.
10
R FB2
R G2
FIVE-RESISTOR DIFFERENCE AMPLIFIER
The five-resistor difference amplifier macromodel used for
the INA117 is shown in Figure 4b. The advantage of the
five-resistor difference amplifier configuration is a boost in
input common-mode-voltage range for a given op amp
common-mode range. The circuit uses an op amp and five
matched resistors. If (R2 || R5)/R1 = R4/R3, GAIN = R2/R1 and
CMR = ∞. To simulate DC CMR error, R4 is set 0.005%
low. For errors in R4, the CMR for a five-resistor difference
amplifier is;
CMR = –20 LOG10 [(%/100) • R1/(R1 + R4)]
Where:
% = % error in R4
R2 || R5 = R2 • R5/(R2 + R5)
5
VO
12
R3
14
R4
8
Ref
A2
+In
1
4
V–
FIGURE 2. Standard Instrumentation Amplifier Macromodel
and Node Assignments.
FIGURE
1a
1b
2
3
4
5
6
With a 0.005% resistor error, DC CMR for the INA117 high
common-mode-voltage unity-gain difference amplifier is
86.5dB. Note that unlike the four resistor difference amplifier, the sensitivity of DC CMR to errors in resistor value is
different for different resistors.
DESCRIPTION
Difference Amp Macromodel Node Assignments
INA117 Difference Amplifier Macromodel
Instrumentation Amp Macromodel Node Assignments
INA103 Macromodel and Node Assignments
INA118 Macromodel and Node Assignments
INA110 Macromodel and Node Assignments
INA120 Internal Gain Setting Resistor Connections
TABLE V. Figure Reference.
To simulate AC CMR error, a small value capacitor, C2, is
placed in parallel with R2 to roll-off of CMR with increasing
frequency.
3
V+
3
+
I1
I2
V1
15
D1
17
+In
2
A1
16
R1
–In
11
CC1
R CE
1
Q1
Q2
R2
13
C2
R FB1
R G1
9
5
A3
RG
VO
R FB2
R G2
10
I3
12
I4
R3
14
R4
Ref
8
CC2
D2
A2
4
V–
FIGURE 3. INA103 Current-Feedback Instrumentation Amplifier Macromodel and Node Assignments.
V+
3
+
I1
I2
V1
15
IB1
17
+In
2
D1
A1
16
R1
CC1
R CE
1
–In
I B2
Q1
Q2
13
11
C2
R FB1
R G1
9
A3
RG
R G2
R2
5
VO
R FB2
10
12
R3
14
CC2
CG1
CG2
D2
0
A2
4
IBAL
(V–) GND
FIGURE 4. INA118 Instrumentation Amplifier Macromodel and Node Assignments.
4
R4
8
Ref
V+
3
+
I5
I6
I1
V1
I2
15
A1
D1
17
21
16
22
2
+In
R1
R CE
–In
1
J1
Q1
J2
CC1
Q2
R G1
13
11
R FB1
9
R2
C2
5
A3
VO
RG
R FB2
10
R G2
C G1
12
8
14
R3
C G2
CC2
I3
Ref
R4
C4
I4
D2
A2
4
V–
FIGURE 5. INA110 Current-Feedback FET-Input Instrumentation Amplifier Macromodel and Node Assignments.
V+
–In
A1
G4
G5
R FB
INA120 INTERNAL GAIN CONNECTIONS(1)
GAIN
1
10
100
1000
2kΩ
CONNECT
G4-G5
G4-G5
G4-G8
G4-G8
G14-G15
G11-G14-G15
G11-G14
G11-G14
R1
20kΩ
R2
G8
44Ω
G10-G15
G9-G15
A3
G9
NOTE: (1) "G" numbers are also package pin numbers.
VO
400Ω
G10
R FB
2kΩ
Ref
20kΩ
G14
G11
G15
A2
+In
V–
FIGURE 6. INA120 Internal Gain-Setting Resistor Connections.
5
R3
R4
SECTION A:
STANDARD MACROMODELS
V+
3
2
The standard op amp macromodels were created by running
the PSpice® Parts™ Simulation software on an IBM-compatible PC. This software uses the standard Boyle op amp
model(1). The PSpice manual available from Microsim(2)
contains a detailed discussion of each of the elements used
in the macromodels.
–In
5
VO
+In
1
4
V–
FIGURE A1. Node Assignments for Standard and Enhanced
Op Amp Macromodels.
Op amp macromodels use the node assignments shown in
Figures A1 to A6. The FET-input amplifiers using the standard PSpice Parts topology are shown in Figures A3 and A4.
The node assignments for the standard PSpice Part op amp
macromodels with bipolar-inputs are shown in Figures A5
and A6. Figure A1 shows the external op amp node assignments. Tables II, III and IV list component prefix designations, macromodel component descriptions, and PSpice INPUT designations used for the standard and enhanced models. The parameters that are modelled by the standard
macromodels are listed in Table X.
FIGURE
DESCRIPTION
A1
A2
A3
A4
A5
A6
Op Amp Node Assignments
OPTxxx Node Assignments
N-Channel JFET-Input Op Amp
P-Channel JFET-Input Op Amp
NPN Bipolar-Input Op Amp
PNP Bipolar-Input Op Amp
TABLE VI. Standard Macromodels Figure Reference.
R FB
4
CFB
V+
1
2
ROUT
DPHOTO
RPHOTO
A1(1)
CPHOTO
5
VO
8
3
V–
NOTE: (1) Use Boyle model illustrated in Figure A4.
FIGURE A2. OPT–Standard Macromodel.
3
V+
DLN
RD1
RD2
RP
+
C1
11
92
HLIM
DP
90
J2
53
FB
VLIM
+
See Table II, for a
more detailed
description of the
components.
CSS
8
5
6
99
RSS
DC
GCM
DE
GA
54
9 +
+
VO
RO1
C2
R2
10
VC
VLP
7
RO2
J1
+
91
DLP
1
2
+
+
12
+In
–In
VLN
EGND
VB
+
VE
ISS
V–
4
FIGURE A3. N-Channel JFET-Input Op Amp Standard PSpice Parts Macromodel.
(1) For more information, see: G.R. Boyle, B.M. Cohn, D.O. Pederson, and J.E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
(2) MicroSim Corporation, 20 Fairbanks, Irvine, CA 92718 USA, (714) 770-3022, (800) 245-3022.
6
3
V+
RP
ISS
DLN
DP
92
HLIM
90
+
VLN
+
+
VC
91
53
+
DLP
10
VLP
7
+In
1
J1
–In
2
CSS
RSS
J2
FB
See Table II, for a
more detailed
description of the
components.
99
RD1
5
GCM
R2
DE
GA
54
9
+
+
EGND
RD2
VO
RO1
6
C1
12
8
+
C2
RO2
11
DC
VLIM
+
VB
VE
V–
4
FIGURE A4. N-Channel JFET-Input Op Amp Standard PSpice Parts Macromodel.
3
V+
DLN
RC1
RC2
RP
C1
90
+
11
92
HLIM
DP
VLN
+
+
VC
91
53
+
12
DLP
+In
VLP
DC
1
7
–In
Q1
2
Q2
13
RO2
14
RE1
FB
6
CEE
DE
GA
+
EGND
10
VO
54
9
+
See Table II, for a
more detailed
description of the
components.
GCM
R2
REE
5
RO1
VLIM
99
RE2
8
+
C2
+
VB
VE
IEE
V–
4
FIGURE A5. NPN-Input Op Amp Standard PSpice Parts Macromodel.
3
V+
DLN
RP
92
HLIM
DP
IEE
+
+
VC
90
+
VLN
91
+
DLP
10
RE1
RE2
13
+In
14
1
Q1
–In
2
7
REE
CEE
11
RC2
FB
EGND
DC
8
5
VO
RO1
6
GCM
9
+
12
+
R2
99
C1
VLIM
C2
RO2
Q2
53
VLP
DE
GA
54
+
VB
+
VE
RC2
V–
4
See Table II, for a more detailed
description of the components.
FIGURE A6. PNP-Input Op Amp Standard PSpice Parts Macromodel.
7
SECTION B:
ENHANCED MACROMODELS
Input Current Correction
One feature that Burr-Brown offers with the enhanced model
type is accurate simulation of input bias current for N-Channel
JFET and P-Channel JFET operational amplifiers. Mathematically, the input bias current for JFET op amps should
equal twice the IS of the JFET model. However, simulation
will show that the gate current from J1 and J2 in Figures A3
through B2 is between 10 to 20pA larger than expected,
depending on the common-mode voltage of the input stage
and the magnitude of the supply voltages, if G11 and G21 are
not included in the model. This additional current is generated from the drain-to-gate and source-to-gate nodes of the
input FETs of the operational amplifier, which manifests
itself as the bias current of the amplifier. The additional
current is caused by the Spice default value, GMIN. In this
case, 1/GMIN is the impedance between the drain and gate
and the source and gate. This is done by Spice to keep the
gate node of each FET from floating. The default value, or
GMIN is 1E-12 . The voltage dependent current sources,
G11 and G21 remove this error current from the model, hence
the macromodel models input bias current correctly. This
technique is used in all of the FET-enhanced and multiple
pole/zero macromodels. To improve simulation accuracy the .OPTIONS statement should include
ABSTOL = 100fA or 10fA.
The enhanced version, “E”, of the standard PSpice Parts
model contains several additional performance features. All
of the macromodels using this topology are in the ENH_MOD
subdirectory on the disk. The FET-input amplifiers using the
standard PSpice Parts topology plus enhancements are shown
in Figures B1 and B2. The node assignments for the enhanced op amp macromodels with bipolar-inputs are shown
in Figures B3 and B4. Figure A1 shows the external op amp
node assignments. Tables II, III, and IV list component
prefix designations, macromodel component descriptions,
and PSpice INPUT designations used for the standard and
enhanced models. The parameters that are modelled by the
enhanced macromodels are listed in Table X. Additions and
changes to the standard PSpice Parts macromodel to the
enhanced version are discussed in the following text.
Ω
FIGURE
DESCRIPTION
B1
B2
B3
B4
B5
B6
B7
N-Channel JFET-Input Op Amp
P-Channel JFET-Input Op Amp
NPN Bipolar-Input Op Amp
PNP Bipolar-Input Op Amp
OPA27/37 Input Protection
OPA77/177 Input Protection
INA114/118 Input Protection Circuitry
Noise
Most of the enhanced JFET-input macromodels model device current noise and voltage noise. The current noise is
modeled using RN1, RN2, RN3, RN4, RN5 and RN6 to create the
noise source and the voltage-dependent current sources, G11
and G21, to model the noise on the inverting and non-
TABLE VII. Enhanced Macromodels Figure Reference.
3
V+
RD1
RD2
DP
DLN
FQ1
RQ
HLIM
C1
11
+In
EN
DLP
7
64
J1
2
RO2
J2
10
C1CM
G21
53
VLIM
+
FB
CSS
5
6
99
RSS
DC
8
GCM
VB
ISS
DE
GA
54
9 +
+
VO
RO1
C2
EGND
G11
VC
VLP
R2
C2CM
+
91
– +
1
+
+
12
CDIF
–In
90
+
VLN
92
+
VE
FQ2
DQ2
FQ3
20
See Table II, for a more detailed
description of the components.
22 +
VQ2
21 +
DQ1
VQ1
FIGURE B1. N-Channel JFET-Input Op Amp Enhanced PSpice Parts Macromodel.
8
4
V–
inverting inputs of the amplifiers. The voltage noise is
modelled using DN1, DN2, VN1 and VN2 to create the noise
source and EN to model the noise on the non-inverting input
of the amplifiers.
Input Protection Diodes
If an op amp contains input protection diodes, its enhanced
op amp macromodel also contains diodes connected between the input pins as shown in Figures B5 and B6, for
example.
Input Capacitance
Differential and common-mode input capacitors, CDIF, C1CM,
and C2CM have been added to the enhanced macromodels.
Input capacitance could also be modeled by including capacitor coefficients in the transistor models. Instead, discrete
capacitors were used so the comparison to the standard
model would be more obvious.
Quiescent Power
RP was replaced by RQ. The value of RQ is higher. It models
only the resistive portion of quiescent current. The current
sources described below model the constant portion of the
quiescent current. This technique provides a more accurate
model of quiescent current vs power-supply voltage.
3
DLN
DP
ISS
FQ1
RQ
92
HLIM
+
+
VC
90
+
V+
VLN
91
+
DLP
10
1
+In
–
CDIF
+
–In
J1
2
C2CM
RSS
J2
FB
6
99
12
R
G21
GCM
VO
DE
GA
54
9
+
+
+
VB
EGND
RD2
D1
5
RO1
R2
C1
C1CM
8
+
C2
RO2
11
G11
CSS
DC
VLIM
7
64
EN
53
VLP
VE
FQ2
V–
DQ2
FQ3
See Table II, for a more detailed
description of the components.
22 +
20
4
VQ2
21 +
DQ1
VQ1
FIGURE B2. P-Channel JFET-Input Op Amp Enhanced PSpice Parts Macromodel.
3
DLN
RC1
RC2
DP
RQ
FQ1
91
+
12
DLP
1
+In
7
Q1
2
C2CM
C1CM
Q2
13
RO2
14
RE1
RE2
VLIM
+
GCM
R2
+
CEE
5
6
99
REE
DC
8
EGND
9
DE
GA
54
+
VB
10
IEE
VO
RO1
C2
FB
53
VLP
CDIF
–In
+
+
VC
90
+
C1
11
92
HLIM
V+
VLN
+
VE
FQ2
V–
DQ2
FQ3
See Table II, for a more detailed
description of the components.
20
22 +
VQ2
21
+
DQ1
VQ1
FIGURE B3. NPN-Input Op Amp Enhanced PSpice Parts Macromodel.
9
4
3
DLN
DP
IEE
92
HLIM
FQ1
RQ
+
+
VC
90
+
V+
VLN
91
+
DLP
10
RE1
1
+In
14
CEE
REE
CDIF
–In
Q1
2
C2CM
11
99
FB
DC
8
5
6
GCM
9
EGND
DE
GA
54
+
+
VB
RC2
VO
RO1
R2
+
12
RC1
+
C2
RO2
Q2
C1
C1CM
VLIM
7
RE2
13
53
VLP
VE
FQ2
V–
DQ2
FQ3
20
See Table II, for a more detailed
description of the components.
22 +
4
VQ2
21
+
DQ1
VQ1
FIGURE B4. PNP-Input Op Amp Enhanced PSpice Parts Macromodel.
NOTE: The enhanced op amp macromodels are more complicated and require more simulation time than the
standard macromodels, but will provide more accuracy in simulations in some applications.
Output Current Flowing
from the Power-Supply Nodes
A number of components were added so that both load and
quiescent current flow from the power supply nodes.
FQ3 mirrors the current flowing from VLIM.
Positive current from FQ3 flows through DQ1 into VQ1.
Negative current from FQ3 flows through DQ2 into VQ2.
FQ1 supplies constant portion of IQ plus mirrors positive
output current, which is measured by VQ1.
FQ2 supplies constant portion of IQ plus mirrors negative
output current, which is measured by VQ2.
3
V+
X1.VS11
X1.FS22
X1.FS11
X1.S11
Protection circuitry
for the inverting
input.
2
–In
V+
X1.S21
2
3
–In
D1N1
D1N2
+In
X1.FS12
X1.FS21
X1.VS21
5
VO
4
V–
3
4
1
V–
V+
X2.VS11
FIGURE B5. Input Protection Diode Circuitry Used on
OPA27/37 Enhanced Macromodels.
X2.FS22
X2.FS11
X2.S11
IN N
V+
R 2IN
2
–In
D2A
VD1
X2.S21
5
VD2
D1A
+In
+In
3
D1B
VO
X2.FS12
D2B
R 1IN
X2.FS21
X2.VS21
4
IN P
Protection circuitry
for the non-inverting
input.
1
4
1
V–
V–
FIGURE B7. Input Protection Circuitry Used on INA114/118
Enhanced Macromodel.
FIGURE B6. Input Protection Circuitry Used on OPA77/177
Enhanced Macromodels.
10
SECTION C:
MULTIPLE-POLE/ZERO
MACROMODELS
improvements in current steering from the supply voltages.
This model type is typically used to model high-speed
amplifiers; however, it has come in useful when modelling
function circuits that require special considerations.
The multiple pole/zero (“M”) macromodel allows modeling
of more than two poles and any additional zeros in the op
amp macromodel. All of the macromodels using this topology are in the MPZ_MOD subdirectory on the disk. The
input stage of this model is similar to the standard and
enhanced op amp macromodels; however, after the input
stage that similarity disappears. By using various circuit
topologies the gain stages, pole stages, zero stages and pole/
zero stages are constructed. The number of each of these
stage types is dependent on the performance characteristics
of the amplifier being modelled. An effort is made to match
the macromodel performance as closely as possible to the
tested gain/phase of the op amp. The output stage also offers
FIGURE
DESCRIPTION
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
N-Channel JFET–Input Op Amp
P-Channel JFET–Input Op Amp
NPN Bipolar–Input Op Amp
PNP Bipolar–Input Op Amp
Gain-, Pole/Zero, and Output Stages
ACF2101M–Op Amp Section
ACF2101M–Node Assignments
OPA675M/676M–Input Stage
OPA675M/676M–Package and Pad Parasitics
VCA610M–Macromodel
TABLE VIII. Multi Pole/Zero Macromodels Figure Reference.
V+
7
R13
+
15
R14
–
16
C12
2
–In
VA
J11
J12
13
R11
IOS
CDIFF
+
1
14
G11
EOS
–
R12
+In
3
ISS
G12
4
V–
FIGURE C1. Input Stage to the N-Channel JFET-Input Op Amp Multiple Pole/Zero Macromodel.
V+
7
ISS
14
R15
R16
17
18
2
J1
–In
R11
IOS
15
+
1
CDIFF
J2
–
VA
R13
13
C12
R13
–
16
R14
+
+In
G11
G21
3
EOS
4
V–
FIGURE C2. Input Stage to the P-Channel JFET-Input Op Amp Multiple Pole/Zero Macromodel.
11
V+
7
R3
R4
VA
+ –
10
11
C1
–In
Q1
Q2
R6
R5
R1
EOS
4
IOS
IEE
CDIFF
R2
+In
10
V–
FIGURE C3. Input Stage to the NPN–Input Op Amp Multiple Pole/Zero Macromodel.
V+
7
ICC
12
+In
3
–
EOS
R5
R1
CDIFF
IOS
R6
+
15
16
10
R2
–In
Q1
2
Q2
11
VA
+ –
13
14
C1
R3
R4
4
V–
FIGURE C4. Input Stage to the PNP–Input Op Amp Multiple Pole/Zero Macromodel.
The accuracy of this model topology compared to the standard and enhanced model topologies is improved for high
speed amplifiers primarily because of the improved gain/
phase performance. Assuming no convergence problem exists with the macromodels discussed so far, the time taken
for Spice to produce the dc operating point calculation of the
multiple pole/zero model is about twice the time required for
the standard model. For transient analysis using this model,
simulation time can be reduced by using the .OPTION
statement to increase the number of transient iterations from
10 to 40. The proper Spice command is:
The basic topology of input stages of this op amp model are
shown in Figures C1, C2, C3, and C4. The input stage is the
only section in the macromodels that differ between the four
types of op amps (N-Channel FET, P-Channel FET, NPN
Bipolar, and PNP Bipolar). The remainder of the macromodel
circuit (gain stages, phase stages, CMRR stage, and output
stage) is shown in a generic form in Figure C5. A summary
of the parameters modelled is listed in Table X.
.OPTIONS ITL4=40
12
7
V1
G1
VA
+
R7
R9
C2
D1
23
9
D2
G2
VA
+
R8
R10
C3
V2
4
Gain Stage
VH
Reference
7
+
G3 (V11 – V16)
V12
+
V15
R20
G6 (V12 – V16)
G8 (V17 – V16)
G10 (V13 – V16)
L2
R18
C6
V14
R17
C5
R21
R19
V13
R13
+
G9 (V13 – V16)
R16
R12
R14
L3
G7 (V17 – V16)
G5 (V12 – V16)
R11
G4 (V11 – V16)
L1
R15
C4
R22
C7
+
L4
4
Pole/Zero
Stage
fp < fz
Common-Mode
Gain Stage
with Zero
Zero/Pole
Stage
fz < fp
Pole Stage
V+
7
7
D5
G11 (V7 – V15)
D6
D3
R23
V3
L5
Output
VO
(From Previous
Stage)
D7
V15
D4
Intermediate
Output Node
V4
G14 (VO – V15)
G13 (V15 – VO)
D8
R24
G12 (V15 – Vp)
4
4
V–
Output Stage
Correction Current
Sources
FIGURE C5. Multiple Pole/Zero Macromodel without Input Stage. Refer to Figures C1 Through C4 for Input Stage Topology.
13
V+
7
R13
R14
IPS
RPS
R9
C12
16
15
3
V21
13
2
C22
R27
30
22
J12
J11
–In
G22
D21
21
30
71
VOS
14
D22
3
+In
23
ISS
V22
G22
C23
R28
R10
30
V–
4
7
R91
G91
D91
D93
D94
6
21
6
94
D92
G92
R92
D95
95
G95
G96
D96
4
FIGURE C6. Op Amp Section of the ACF2101 Using the Multiple Pole/Zero Macromodel Topology.
CINT
37
Cap
31
SR
SH1
32
2
Sw In
6
SH2
Sw Out
3
33
Com
Sw Com
FIGURE C7. Node Assignments for ACF2101 Macromodel.
accurate emulation of the effect of the 200ns switching
speed of the actual switching transistors in the ACF2101.
This is easily implemented with the PULSE command in
Spice. Also, to insure proper operation, always establish the
initial bias point for the transient analysis with RESET and
HOLD equal to the potential of COMMON (node 3).
The multiple pole/zero topology is used to model the op amp
section of the ACF2101 switched integrator. The node
assignments for this model are shown in Figure C6 and C7.
The transient time of the switches (HOLD, RESET, and
SELECT) should be programmed to have a slew of 6V/µs.
Complying with this requirement will give the user greater
success in convergence during transient analysis, and a more
14
7
+V
R4
R3
C1
110
–InA
102
113
Q2
Q1
114
111
202
+InA –InB
Q1-2
+InB
214
115
216
116
C11
13
213
Q2-2
C12
RSW1
RSW2
Q11
997
Q12
996
998
999
CSW2
CSW1
VTTL1
VTTL2
12
Cha
IEE
11
–V
10
FIGURE C8. Input Stage of the OPA675 and OPA676 Switched-Input Op Amp Using the Multiple Pole/Zero Macromodel
Topology.
2
(15)
–In
LM
CM1
CM2
108
(201)
Ideal
OPA
675/676
1
(16)
+In
102
(202)
LP
CP1
3
LOUT
Out
COUT1
19
8
COUT2
CCPP1
CP2
LCPP
CCPP2
5
Comp Cap
FIGURE C9. Package and Pad Parasitics Modelled by the OPA675 and OPA676 Macromodel.
The OPA675 and OPA676 are wideband op amps with two
independent differential inputs (Figure C8). The multiple
pole/zero topology is used to model the op amp portion of
these switched-input amplifiers. Both amplifiers are identical except for the switch logic. The OPA675 is an ECL-
switched device and the OPA676 is a TTL-switched device.
Both files will model the device characteristics and package
parasitics. If the user is using the product in its die form, the
package parasitics no longer apply (Figure C9).
15
6
I1
Gain Control
R2
10
13
12
2
Q2
Q1
3
11
Q3
G3
C1
R3
C3
E1
7
6
D03
44
D04
29
E41
24
D01
R41
D02
27
C41
G41
E43
43
28
41
31
R01
R02
20
1
D42
R31
21
Q01
G31
R42
Q02
C42
G42
E44
8
C01
6
D41
42
G1
G2
E42
C02
45
7
26
Gain Stage
Quiescent Current
IS
6
7
Input Stage
D55
D56
G51
R53
D53
51
V53
55
5
D54
52
E51
V54
53
D57
G54
R54
54
G53
D58
G52
7
Output Stage
FIGURE C10. VCA610M Voltage Controlled Amplifier using the Multiple Pole/Zero Macromodel Topology.
16
The OPA660 wideband amplifier offers the user an “ideal
transistor” and a buffer. The “ideal transistor” has three
terminals available to the user—a high-impedance input
(base), a low-impedance input/output (emitter) and the current output (collector). This “ideal transistor”, otherwise
called an Operational Transconductance Amplifier (OTA),
is constructed using several discrete real transistors on the
chip to give the user superior gain and temperature performance, hence, the comparison to an “ideal transistor”.
SECTION D:
SIMPLIFIED CIRCUIT MODELS
As already mentioned the simplified circuit models provide
a much different simulation approach, because they do not
follow a standard model design. They are micromodels at
the transistor level, therefore each model has its individual
circuit schematic, which are shown on the following pages.
Almost all of the devices of this model level (Level IV) are
wideband/high-speed components with bandwidth capabilities of up to 1GHz. Some models have only one simplified
circuit model available, and are labeled with the suffix “X”.
Other models offer two simplified circuit models. In general,
the models with an “X1” suffix are of equivalent complexity
as the “X” models. They are simpler implementations of the
macromodel and will simulate faster; however, the accuracy
is not as good as with the macromodels with an “X2” suffix
for the same product.
Although these transistor level models are more accurate
than the other three topology levels used for macromodels
on this disk, the user is cautioned that all models are an aid
to circuit design and not a suggested replacement for breadboarding. Simulation should be used as a forerunner or a
supplement to traditional lab testing. The parameters that are
modelled by the transistor level circuit macromodels are
listed in Table X.
All of these models are found in the CIR_MOD subdirectory
on the disk. These models are designed using different
topologies than mentioned above and several non-linear
elements. Because of the increased number of non-linear
elements in these models, the simulation time is longer, but
the accuracy is improved.
FIGURE
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
The wideband operational amplifiers that have simplified
circuit macromodels were designed using several subcircuits
that allow the user to implement a variety of configurations.
The OPA622 is a monolithic amplifier that can be configured as a current-feedback amplifier or a voltage-feedback
amplifier. Like typical current-feedback amplifier, the
OPA622 has a constant large-signal bandwidth of 280MHz.
One would expect that when the OPA622 is configured in a
voltage-feedback configuration the bandwidth would change
with gain. This is not the case. When the OPA622 is
configured as a voltage-feedback amplifier, it will again
have a constant bandwidth over a wide gain and output
voltage range. In the voltage-feedback mode, the OPA622
offers the speed advantages of current-feedback amplifiers
and matched input impedance advantage of the voltagefeedback op amp. The OPA623 is strictly configured as a
current-feedback amplifier, using the same internal design
as the OPA622.
DESCRIPTION
BUF600/601X1 Circuit Model
BUF600/602X2 Complex Circuit Model
BUF634X Circuit Model
ISO120/121X Circuit Model
ISO130 Circuit Model
MPC100X1 Circuit Model
MPC100X2 Complex Circuit Model
OPA603X Circuit Model
OPA620/621X Circuit Model
OPA622X1 Circuit Model
OPA622X2 Complex Circuit Model
OPA623X1 Circuit Model
OPA623X2 Complex Circuit Model
OPA640X/OPA641X Circuit Model
OPA642X/OPA643X Circuit Model
OPA644X Circuit Model
OPA646X Circuit Model
OPA648X Circuit Model
OPA64x Package and Pad Parasitics
OPA658X Circuit Model
OPA660X1 Circuit Model
OPA660X2 Complex Circuit Model
TABLE VIIII. Simplified Circuit Models Figure Reference.
17
VIN
4
Q21
1
Q23
21
V+
V41
Q29
41
R34
C33
I21
Q41
39
16X
C39
Q33
33
8
Q34
VOUT
C208
R33
C40
Q16X
40
42
24
Q22
V42
Q30
12X
Q24
RQC
5
V–
22
FIGURE D1. BUF600X1 and BUF601X1 Simplified Circuit Macromodel. Compared to Figure D2, this macromodel is less
complex with faster simulation times.
VIN
4
1
V+
Q27
Q21
1.4X
Q23
21
Q25
Q29
27
1.4X
Q37
6X
Q31
2X
I21
6X
34
Q34
Q40
6X
40
36
8
41
Q36
C204
16X
Q39
Q35
Q33
Q41
39
35
C208
VOUT
Q42
6X
Q32
2X
Q38
32
24
Q22
12X
RQC
Q24
Q26
28
6X
Q30
1.4X
Q28
1.4X
5
V–
22
FIGURE D2. BUF600X2 and BUF601X2 Complex Macromodel. Compared to Figure D1, this macromodel is more complex
and requires more simulation time.
18
+VCC
80
D9
R9
24
Q11
13
Q6
D2
IB
22
R10
85
86
C1
Q4
Q12
12
Q8
R1
15
Iss
6
R24
5
D4
Q13
D6
R1
14
7
2
102
Q2
VIN
VOS
CP
73
16
11
C0
D11
Q1
3
21
D8
R25
D10
RIN
1
Q9
CIN
Q10
18
4
20
R27
8
Q3
R5
C2
R2
10
Q7
98
94
9
R7
R2
17
D3
23
R6
Q14
D5
D1
VOUT
R26
Q5
R8
90
–VCC
FIGURE D3. BUF634X Simplified Circuit Macromodel.
3(3)(1)
15(23)
+VS1
+VS2
I1
24(40)
GND1
I3
R6
V1
I3
12(20)
52
GND2
R3
13(21)
R4
11(19)
C2
VIN
23(39)
C1
E2
VOS
R1
60
50
R2
14(22)
51
VOUT
57
C2V
55
Q3
Q1
C2L
E3
R5
R7
10(18)
E1
COM1
VOUT
54
21(37)
E4
56
Q2
Q4
58
COM2
9(17)
I2
–VS1
4(4)
I4
16(24)
NOTE: (1) First node number is for ISO120. Second node number is for ISO121.
FIGURE D4. ISO120/121X Isolation Amplifiers Simplified-Circuit Macromodel.
19
V2
I6
–VS2
1
VS1
VINP
D1
R1
2
GVS1
9
VIN+
R5
R3
D3
I1
D2
VIN
R2
3
10
VIN–
D4
R4
I2
GND1
4
R10
V2
13
VOUT+
C3
11
7
17
Q1
Q2
14
TDELAY
12
RE1
23
6
VOUT–
22
R6
16
R11
18
R7
19
R8
R9
21
20
RE2
V3
15
C1
9
C2
C4
E2
E3
+
–
E1
I3
5
10
GND2
GVS2
R12
8
VS2
FIGURE D5. ISO130X Simplified-Circuit Model.
20
In
12
R24
C25
Q21
V27
14
27
25
R21
Q 25
25
SEL
C23
Q23
23
G21
Q24
C24
11
26
V22
V+
R22
VOUT
Q26
26
28
Q22
C26
R23
V28
10
V–
FIGURE D6. MPC100X1 Simplified-Circuit Macromodel. Compared to Figure D7, this macromodel is less complex with faster
simulation times. Shown here is only one out of four inputs of the MPC100. However, the same circuit schematic
applies to the MPC102X1 and MPC104X1 model.
1
Q24
23
C24
29
25
33
Q33
26
42
D26
21
C33
Q31
Q43
Q35
45
Q37
35
11
R45
Q36
Q38
36
39
Q39
41
Q40
40
34
Q28
Q41
11
VOUT
Q42
28
Q44
Q32
Q21
22
43
Q45
34
Q27
D25
24
SEL
V+
R43
R34
Q29
27
R23
R24
12
R29
Q23
14
In
Q30
32
30
Q22
C28
R30
R32
46
Q46
44
R46
10
V–
FIGURE D7. MPC100X2 Complex-Circuit Macromodel. Compared to Figure D6, this macromodel is more complex and requires
more simulation time. Shown here is only one out of four inputs of the MPC100.
21
1
Q9A
V6A
FB
Q8A
30
IS
R PS
R 5A
34
R 8A
CB
32
Q5A
36
26
28
RB
Q6A
R 2AT
2
18
Q2A
16
R 1A
GC
Q1A
10
R 0EA
14
Q4A
20
24
Q3A
8
R 0A
+In
V+
+
6
Q0A
3
7
R 4A
QSCA
R 1EA
22
5
R3
Q0B
R 0B
VO
23
QSCB
4
–In
9
R 1EB
R 0EB
R 8B
Q8B
Q4B
Q2B
C 2B
17
R 2BT
33
35
21
Q1B
13
Q5B
25
15
R 1B
11
37
R 4B
Q3B
19
R 5B
Q6B
31
27
+
Q9B
V6B
2
FIGURE D8. OPA603X High Speed Current-Feedback Op Amp Simplified-Circuit Macromodel.
22
V–
3
V+
R7
R1
R2
17
5X
Q5
I3
10
9
+In
–In
1
2
25
Q2
Q1
2X
2X
11
18
Q6
Q13
40X
Q7
20X
Q11
20
12
5
Q12
VO
20X
R3
R4
I1
40X
19
13
Q8
24
Q14
2X
15
Q3
Q4
4X
14
R5
16
R6
I2
21
Q9
C1
Q10
2X
2X
22
23
R8
R9
V–
4
NOTE: OPA620 and OPA621 simplified-circuit macromodels
are the same with the following exceptions.
MODEL
C1
(pF)
I1
(mA)
I2
(mA)
I3
(mA)
OPA620
OPA621
10
2
1.1
1.3
4
3.5
2
3.5
FIGURE D9. OPA620X and OPA621X High Speed Op Amp Simplified-Circuit Macromodel.
23
24
IQ Adjust
2
R123
R122
141
V–
5
X1
Q124
Q123
12
–In
3
R63
63
C63
Q63
61
Q61
62
Q62
Q64
Diamond Buffer
(DB)
C62
C61
6X
Q66
6X
Q65
X4
Buffer –
8
VOUT
+In
4
R23
23
C23
Q23
21
Q21
Q22
22
Q24
28
C22
C21
27
Q27
Q28
6X
Q26
C10
6X
Q25
Diamond Transistor
(DT)
C28
C27
Q30
121
X2
Buffer +
Q34
34
Q32
13
33 OTA
Q33
10
Q31
111
Q29
V+
V O–
6
VO+ 11
FIGURE D10. OPA622X1 Simplified Circuit Macromodel. Compared to Figure D11, this macromodel is less complex with faster simulation times.
122
10X
Q122
131
Q121
Biasing Circuit
(BC)
Q36
Q38
38
Q37
37
Q35
9
2.2X
Q40
X3
Voltage
Out
2.2X
Q39
Current Buffer
(CB)
Diamond Transistor
(DT)
V+
Current Buffer
(CB)
11
12
Q23
131
10X
Q21
VO+
Q33
8X
Q25
23
Q35
33
10X
8X
111
111
Q43
4X
29
Q37
Q31
37
Q39
Q47
45
5X
5X
48X
6X
Q45
Q29
+In
Q28
4
10
6X
28
Q27
C213
Q30
6X
30
Q32
Q38
6X
5X
38
12X
OTA
9
47
Q46
C210
12X
Q40
Q48
46
5X
VOUT
C209
48X
125
125
Q44
4X
141
V–
24
Q22
34
Q26
Q36
8X
10X
Q24
Q34
10X
8X
6
5
13
X2
X3
VO –
Buffer +
Diamond Buffer
(DB)
V+
Biasing Circuit
(BC)
12
12
Q63
131
10X
Q61
63
Q73
Q121
4X
Q65
C121
Q123
10X
121
Q125
E13
11X
V+
131
73
69
I121
Q71
6X
Q69
+In
Q68
3
8
68
Q67
Buffer –
C208
Q70
Q72
70
6X
124
Q122
74
6X
V–
Q62
64
122
Q66
10X
Q64
Q74
10X
4X
141
Q124
R122
141
E14
R123
C124
5
V–
C202
5
2
X4
X1
IQ Adjust
FIGURE D11. OPA622X2 Complex Macromodel. Compared to Figure D10, this macromodel is more complex and requires
more simulation time.
25
Biasing Circuit
(BC)
Diamond Transistor
(DT)
Current Buffer
(CB)
Q27
Q121
Q123
131
Q21
27
Q29
C27
21
111
Q25
Q35
6X
Q31
C21
37
33
Q33
3
R23
23
Q23
–In
C35
22
Q26
6X
141
Q22
28
Q124
RQC
122
35
Q34
39
34
Q32
38
6
VOUT
Q38
Q40
2.2X
Q36
121
C22
10X
2.2X
Q37
2
Q24
C23
Q122
Q39
Q30
Q28
C28
4
X2
X1
X3
V–
FIGURE D12. OPA623X1 Simplified-Circuit Macromodel. Compared to Figure D13, this macromodel is less complex with
faster simulation times.
26
Diamond Transistor
(DT)
V+
Current Buffer
(CB)
7
7
Q23
131
10X
Q21
23
V+
Q33
10X
Q25
Q35
33
10X
10X
111
111
Q43
4X
29
Q37
Q31
37
Q39
6X
Q29
+In
Q28
3
C39
6X
28
Q27
C203
30
12X
39
Q32
Q38
6X
5X
38
12X
Q40
46
5X
V–
34
Q26
VOUT
C206
Q48
48X
123
Q44
4X
C202
24
6
47
123
Q22
48X
Q45
Q46
Q30
6X
141
Q47
45
5X
5X
Q36
8X
10X
Q24
Q34
10X
10X
4
4
2
X2
V–
X3
–In
Biasing Circuit
(BC)
7
Q121
C121
Q123
124
Q122
6X
E13
E14
11X
V+
131
141
Q124
RQC
122
121
Q125
C124
4
V–
X1
FIGURE D13. OPA623X2 Complex Macromodel. Compared to Figure D12, this macromodel is less complex with faster
simulation time.
27
28
4
2
R22
R21
Q1
R2
8X
R4
23
Q3
22
24
R5
R3
20
19
12X
Q2
16
21
18
12X
17
R1
C2
C3
Q7
27
R9
25
ISOUR
Q11
Q8
26
44
Q20
45
R8
17
R11
4X
Q14
R13
31
Q15
29
V1
28
4X
R12
Q20
Q19
Q18
R15
32
4X
30
4X
4X
R14
to C1P
16
C8
15
C6
Q22
33
Q21
R16
34
2X
2X
Q24
39
36
Q23
Q28
Q27
Q26
Q25
35
R18
R19
38
2X
24X
24X
2X
FIGURE D14. OPA640X, OPA641X, Wide Bandwidth Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics.
7
6
3
1
40
37
20X
Q31
Q30
Q32
36X
41
36X
20X
Q29
R20
43
42
5
Q34
Q33
10X
10X
29
6
7
17
16
35
4
2
R26
R27
R24
Q2
4X
40
R25
Q3
12X
R3
24
Q5
20
8X
R2
18
12X
Q1
R1
21
22
23
R5
19
Q4
4X
41
R4
2
CA1
C1
2
CA2
C2
2
CA3
2X
C3
Q9
Q13
Q12
28
R11
27
26
17
R9
25
ISOUR
Q8
29
R8
Q15
Q14
2X
34
30
R12
4X
Q17
37
Q16
R14
44
Q18
42
4X
3X
R15
31
R13
35
Q21
38
3X
32
R18
45
4X
43
4X
4X
Q23
Q22
R18
Q20
R17
C8
2X
Q24
Q25
36
33
R19
C6
15
16
C7
Q27
48
47
Q28
Q31
Q30
Q29
Q28
R22
49
2X
51
20X
20X
50
2X
46
R21
FIGURE D15. OPA642X, OPA643X, Low Distortion, High-Speed Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics.
3
1
20X
Q34
Q33
Q35
36X
53
36X
20X
Q32
R23
54
52
Q37
2
CA4
5
Q38
20X
20X
30
R34
R33
2
2
17
R2
C2PP
C1PP
R1
C1
18
C2
R4
58
R3
F1
59
2
C4PP
19
C4
2
27
C3PP
20
25
C3
R7
Q6
22
ISOUR
Q8
Q3
R5
Q10
Q09
21
R27
Q14
R28
24
7
Q11
R9
R10
28
Q13
Q12
26
30
6
29
R6
Q17
54
Q16
32
V2
31
V1
33
F2
59
F1
V3
59
F3
59
RB32
59
RB29
R18
RE31
R19
R32
R21
45
44
RBB34
RE30
38
37
RBB33
RE29
39
59
46
RB34
40
R20
59
RB33
CE32
59
35
59
43
RE34
CU32
CE29
CU29
RE33
G1
C7
G3
CE34
R032
CU34
R029
CU33
CE33
C6
34
2
2
36
C032
G2
C029
G2
FIGURE 16. OPA644x, High-Speed Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics.
4
2
3
1
R034
R033
2
C034
18
2
2
C12PP
C12
2
C8PP
C8
15
CS33
Q39
Q38
49
48
IOUT1
Q42
16
Q41
Q45
Q44
Q46
50
52
51
Q43
Q48
Q47
R26
5
31
4
2
R19
R19
Q1
R2
2X
R4
23
Q3
22
24
R5
R3
20
19
4X
Q2
16
21
18
4X
17
R1
C2
C3
Q7
27
R3
25
ISOUR
Q6
28
R8
Q10
26
17
Q11
R12
31
Q15
V1
29
3X
R11
32
30
Q18
Q17
Q18
R14
33
3X
R13
16
C8
C7
15
17
Q24
4X
Q22
Q21
34
R16
37
2X
38
Q23
45
2X
39
36
2X
Q20
2X
4X
Q19
R15
Q26
35
Q25
2X
2X
FIGURE D17. OPA646X, Low Power, High-Speed Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics.
7
6
3
1
20X
Q29
Q27
Q28
Q30
43
40
42
20X
Q32
Q31
36X
41
36X
R17
5
32
C3
R19
R18
R5
ISOUR
13
R7
21
B14
19
17
14
B11
12
4
16
B15
B18
B13
B12
R8
22
20
23
B2
B4
R3
29
B8
28
3
31
6
B9
B10
CCOMP
R4
30
32
B24
B22
B3
B7
25
B1
26
B6
R2
33
27
24
B5
R1
18
15
R8
FIGURE D18. OPA648X, High-Speed Op Amp Simplified-Circuit Macromodel.
2
1
B25
B23
34
B29
38
36
I2
B27
B30
B32
B31
B28
R23
39
40
37
35
R22
B38
B37
B35
B33
B41
43
B39
42
41
B42
B???
R24
5
FIGURE D19. Schematic to Model the Pad Parasitics Used for the OPA64X High-Speed Op Amp Series.
33
11
14
13
2
L13P
R12P
R7P
R2P
67
66
63
60
R18P
L10P
L6P
L2P
68
C10P
64
C4P
61
R11P
R5P
C15P
C9P
C3P
R1P
69
65
62
L9P
L5P
L1P
C14P
C8P
C2P
C1P
2
7
6
15
4
5
3
1
C35P
L27P
C29P
L22P
C22P
L18P
C16P
L14P
79
76
73
70
R33P
R27P
R22P
R17P
C38P
80
C30P
77
C23P
74
C17P
71
C31P
C24P
C18P
R38P
L28P
L23P
L19P
L15P
82
81
78
75
72
L31P
R37P
R31P
R26P
R21P
9
12
10
8
FIGURE D20. OPA658X, OPA2658X and OPA4658 Current-Feedback Wideband Op Amp Simplified-Circuit Macromodel.
34
7
9
8
2
2
1
R17
R16
L11P
R6P
R4P
R2P
12
C1
11
50
49
46
43
R11P
L8P
L4P
L2P
R5
48
C4
4
C3
C4P
45
C2P
42
Q2
Q1
47
44
41
ISOUR2
14
13
ISOUR1
C5P
R5P
C3P
R3P
C1P
R1P
Q4
Q3
R1
Q9
19
R8
R7
37
20
R2
R4
23
Q10
26
25
24
Q7
Q6
L9P
L7P
R3
R6
R12
5
1
21
3
17
2
4
3
Q8
22
16
Q5
L5P
L3P
L1P
54
51
C2
R9P
R7P
55
52
C8P
C6P
Q16
Q12
Q11
27
R9
R10
32
Q14
30
28
Q13
L10P
Q15
C7P
L8P
56
53
31
29
R10P
R8P
2
1
Q18
Q20
33
35
34
Q17
Q19
10
6
Q22
Q21
36
R11
5
35
IQ Adjust
1
R123
R122
Q121
V–
4
X3
Q124
14
Q123 13
7
Buffer
In
R73
5
73
C73
Q73
71
Q71
72
Q72
Q74
Diamond Buffer
(MDB)
C72
C71
Q76
Q75
X1
C206
6
Buffer
Out
Base
3
R23
23
C23
Q23
21
Q21
Q22
22
Q24
26
C22
C21
25
Diamond Transistor
(MDT)
Q28
Q26
Q25
Q27
C26
C25
FIGURE D21. OPA660X1 Simplified-Circuit Macromodel. Compared to Figure D22, this macromodel is less complex with faster simulation times.
C201
Q122
122
V+
Biasing Circuit
(MBC)
Q30
Q29
X2
C202
2
C208
8
Emitter
Collector
36
R122
C201
R123
Q122
122
I121
C121
121
Q121
C124
124
E13
Biasing Circuit
(MBC)
Q124
E14
Q123
X3
Q125
5
13
14
C205
Buffer In
14
13
Q74
Q71
74
Q77
79
Q75
77
80
Q76
Q78
73
Diamond Buffer
(MDB)
Q80
Q72
X1
78
Q79
Q73
Q82
Q81
6
C203
R27
Q21
Q24
Buffer
Out 24
C206
14
Base
3
13
Q26
Q28
Q22
Q23
23
27
Q27
30
29
Q30
28
Q29
Q25
Diamond Transistor
(MDT)
2
R33
33
R34
34
Q34
32
Q32
Q31
31
Q33
FIGURE D22. OPA660X2 Complex Macromodel. Compared to Figure D21, this macromodel is more complex and requires more simulation time.
V–
4
IQ Adjust
1
V+
7
C38
X2
R36
36
Q36
C208
C202
Q35
35
R35
4
Collector
8
Emitter
2
7
X
X
X
X
X
OPA124
OPA124E
OPA128
OPA128E
OPA129
X
X
X
X
X
OPA129E
OPA131
OPA131E
OPA177
OPA177E
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NA
NA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
10, 14
10, 14
10, 14
10, 14
C6,7
D1
D2
D1
D2
X
X
X
X
X
X
X
X
X
1
1
1
1
1
D3
2
2
2
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
2
2
2
3
3
1a
1a
1a
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
1
1
1
1
1a
5
5
2
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
2
2
2
2
16
X
X
X
X
X
X
X
X
X
X
X
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B4
A4
B2
A4
B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
B2
A4
B2
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PSRR
X
X
X
X
X
X
X
X
X
X
X
X
2
16
4
4
6
6
1
1
2
2
D4
D4
D5
4
4
X
X
X
X
X
X
X
TABLE X. Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel.
37
NO GROUND REFERENCE
X
X
X
X
PAD PARASITICS
X
X
X
X
X
X
SLEW RATE
X
X
X
X
X
X
X
PSRR vs FREQUENCY
X
X
X
X
X
X
CMRR vs FREQUENCY
X
X
X
X
X
X
PHASE RESPONSE
X
X
X
X
X
FIGURE
X
OPA1013E
OPA111
OPA111E
OPA121
OPA121E
X
X
X
X
X
X
X
X
COMMENTS
MPC100X1
MPC100X2
MPC102X1
MPC104X1
OPA1013
X
X
X
X
X
X
X
GAIN vs TEMPERATURE
X
X
NA
NA
X
X
X
X
X
X
X
X
X
X
X
GAIN vs FREQUENCY
INA131
INA131E
ISO120X
ISO121X
ISO130X
X
X
X
X
X
X
X
X
X
QUIESCENT CURRENT vs TEMPERATURE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
QUIESCENT CURRENT vs POWER SUPPLY
INA117E
INA118
INA118E
INA120
INA120E
X
X
QUIESCENT CURRENT
X
X
X
X
X
X
X
X
X
X
OUTPUT VOLTAGE SWING
INA114
INA114E
INA115
INA115E
INA117
X
X
NA
NA
NA
NA
OUTPUT FLOWING FROM POWER SUPPLIES
X
X
X
X
X
X
X
X
X
X
X
OUTPUT CURRENT LIMIT
INA106E
INA110
INA110E
INA111
INA111E
X
OUTPUT RESISTANCE
X
X
X
X
X
X
INPUT BIAS CURRENT CORRECTION
INA103
INA103E
INA105
INA105E
INA106
X
INPUT IMPEDANCE
X
X
X
X
X
X
INPUT PROTECTION
BUF634X
INA101
INA101E
INA102
INA102E
INPUT CURRENT NOISE
NA
NA
NA
NA
NA
INPUT VOLTAGE NOISE
INPUT OFFSET CURRENT
X
X
X
X
X
OFFSET VOLTAGE
INPUT BIAS CURRENT
DEVICE
CHARACTERISTICS
MODELED
ACF2101M
BUF600X1
BUF600X2
BUF601X1
BUF601X2
MODEL
14,
14,
14,
14,
10
10
10
10
D6
D7
D6
D6
A6
A5
B6
OPA2604M
OPA2658X
OPA27
OPA27E
OPA27M
X
X
X
X
X
OPA37
OPA37E
OPA404
OPA404E
OPA445
X
X
X
X
X
OPA445E
OPA4131
OPA4131E
OPA4658X
OPA501
X
X
X
X
X
OPA501E
OPA502
OPA502E
OPA511
OPA511E
X
X
X
X
X
OPA512
OPA512E
OPA541
OPA541E
OPA602
X
X
X
X
X
OPA602E
OPA603X
OPA604
OPA604E
OPA604M
X
X
X
X
X
OPA606
OPA606E
OPA620
OPA620E
OPA620X
X
X
X
X
X
OPA621
OPA621E
OPA621X
OPA622X1
OPA622X2
X
X
X
X
X
OPA623X1
OPA623X2
OPA627
OPA627E
OPA628M
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NA
NA
NA
NA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FIGURE
X
X
X
X
X
X
X
X
X
X
X
X
X
COMMENTS
COMMENTS
X
X
X
X
X
X
X
X
X
X
X
NO GROUND REFERENCE
X
X
X
X
X
X
X
X
X
X
X
X
X
PAD PARASITICS
X
X
X
X
SLEW RATE
X
X
X
X
X
X
X
X
X
X
X
X
PSRR vs FREQUENCY
X
X
X
X
X
X
X
X
X
X
X
X
PSRR
X
X
X
X
X
X
X
CMRR vs FREQUENCY
X
X
X
X
X
X
X
X
X
PHASE RESPONSE
X
X
X
X
X
X
X
X
X
X
X
X
GAIN vs TEMPERATURE
X
X
X
X
X
X
X
X
X
X
GAIN vs FREQUENCY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NA
NA
X
X
X
X
NA
NA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
QUIESCENT CURRENT vs TEMPERATURE
X
X
QUIESCENT CURRENT vs POWER SUPPLY
X
X
X
X
X
QUIESCENT CURRENT
X
X
X
X
X
X
OUTPUT VOLTAGE SWING
X
X
OUTPUT FLOWING FROM POWER SUPPLIES
X
X
X
X
X
X
OUTPUT CURRENT LIMIT
X
INPUT IMPEDANCE
X
INPUT PROTECTION
OFFSET VOLTAGE
X
OUTPUT RESISTANCE
X
X
X
X
X
X
INPUT BIAS CURRENT CORRECTION
OPA2131E
OPA2541
OPA2541E
OPA2604
OPA2604E
INPUT CURRENT NOISE
X
X
X
X
X
INPUT VOLTAGE NOISE
OPA2107
OPA2107E
OPA2111
OPA2111E
OPA2131
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
DEVICE
CHARACTERISTICS
MODELED
MODEL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A5
B4
A4
B2
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B4
A3
B4
A4
B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
B2
A4
B2
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
B2
A4
B2
A4
B2
A4
B2
X
X
X
C2, 5
D20
A5
B4
C3, 5
X
X
X
D20
A5
X
B2
D8
A4
B2
C2, 5
X
8
A4
B2
A5
B4
D9
8
10, 14
10, 14
A5
B4
D9
D10
D11
X
X
9
10, 14
10, 14
X
TABLE X (cont). Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel.
38
D12
D13
A4
B2
C3
X
X
X
X
X
NA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NO GROUND REFERENCE
X
INPUT PROTECTION
X
X
X
X
X
X
X
X
X
X
X
X
PAD PARASITICS
X
X
X
X
X
X
X
X
X
X
X
X
X
PSRR
X
X
X
X
X
X
X
NA
CMRR vs FREQUENCY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PHASE RESPONSE
X
X
X
X
X
X
X
X
X
GAIN vs TEMPERATURE
X
X
X
X
X
X
GAIN vs FREQUENCY
X
X
X
X
X
X
X
X
X
QUIESCENT CURRENT vs TEMPERATURE
X
X
X
X
X
X
X
X
X
X
QUIESCENT CURRENT vs POWER SUPPLY
X
X
X
X
X
X
X
X
X
FIGURE
X
X
X
X
X
X
X
X
X
X
X
X
COMMENTS
COMMENTS
UAF42
UAF42E
VCA610M
X
X
X
X
X
X
X
X
X
SLEW RATE
X
X
X
X
X
X
X
X
X
X
X
X
X
PSRR vs FREQUENCY
OPA77E
OPT101
OPT201
OPT202
OPT209
QUIESCENT CURRENT
NA
X
X
X
OUTPUT VOLTAGE SWING
X
X
X
X
X
OUTPUT FLOWING FROM POWER SUPPLIES
OPA660X2
OPA671M
OPA675M
OPA676M
OPA77
OUTPUT CURRENT LIMIT
X
X
X
X
NA
X
X
X
X
X
OUTPUT RESISTANCE
X
X
X
X
X
X
X
X
X
X
INPUT BIAS CURRENT CORRECTION
OPA643X
OPA644X
OPA646X
OPA648X
OPA660X1
X
X
X
X
INPUT IMPEDANCE
X
X
X
X
X
X
X
X
INPUT CURRENT NOISE
X
X
X
X
X
INPUT VOLTAGE NOISE
OPA637
OPA637E
OPA640X
OPA641X
OPA642X
OFFSET VOLTAGE
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
DEVICE
CHARACTERISTICS
MODELED
MODEL
X
X
X
X
X
X
8, 12
8, 12
8, 12
A4
B2
D14
D14
D15
X
X
X
X
X
X
X
X
8,
8,
8,
8,
X
X
X
X
X
X
12
12
12
12
10, 14, 5 D22
C2, 5
6
C8, C9
6, 11 C8, C9
A5
B6
A2
A2
A2
A2
X
3
3
13
COMMENTS: 1. Instrumentation Amplifier. 2. Difference Amplifier. 3. All four op amps in the UAF42 chip are identical. This model only contains one op amp. 4.
Also models isolation barrier impedance. 5. Also models enable transient response and the quiescent resistor transient response. 6. Also has the input control switch
and models its transient response. 7. Model includes HOLD, RESET and SELECT switches and internal capacitor. 8. Also models total harmonic distortion. 9. Also
models bias current vs power supply and bias current vs common-mode. 10. Also models group delay time. 11. Also models TTL switching times. 12. Also models
output recovery time. 13. Also models gain control vs frequency. 14. Contact the factory for a more detailed description of this macromodel 800 548-6132 or FAX
(602) 746-7852.
TABLE X (cont). Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel.
39
D15
D16
D17
D18
D21
A4
B2
C10
PRODUCT NOTES
RGI = One of the three internal gain-setting resistors shown
in the table (Ω)
RGE = external gain-setting resistor (Ω)
For more information please refer to the individual
data sheet.
ACF2101
SWITCHED INTEGRATOR
The integrator output voltage range is from +0.5V to –10V.
The output voltage (VOUT) can be calculated as:
V OUT = −
1
C
INT
INA103
INSTRUMENTATION AMPLIFIER
The INA103 contains internal gain-setting and feedback
resistors:
RFB = 3kΩ
RG = 60.606Ω (Gain = 100)
∫ i IN dt
The internal gain-setting feedback resistors may be used, or
external feedback resistors may be used.
VOUT = the output voltage of the ACF2101
CINT = the integration capacitor (in farads)
iIN = the input current (in amperes)
dt = the integration time (in seconds)
If the internal resistors are used:
GAIN = 1 + (6k/RG)
If external feedback resistors are used:
GAIN = 1 + (2 • RFB/RG)
Where:
RG = Optional external gain-setting resistor (Ω)
RFB = Optional external feedback resistor (Ω)
INA101
INSTRUMENTATION AMPLIFIER
The INA101 contains internal gain-setting feedback resistors;
RFB = 20kΩ
INA110
INSTRUMENTATION AMPLIFIER
When using the metal package (TO-100), these resistors
must be used. When using the ceramic or plastic packages,
the internal gain-setting feedback resistors may be used, or
external feedback resistors may be used.
INA110 INTERNAL GAIN-SETTING RESISTORS
If the internal resistors are used:
GAIN = 1 + (40k/RG)
If external feedback resistors are used:
GAIN = 1 + (2 • RFB/RG)
Where:
RG = external gain-setting resistor (Ω)
RFB = optional external feedback resistor (Ω)
RG
(w)
GAIN
(V/V)
4.444K
404.04
201.0
80.16
10
100
200
500
The INA110 contains internal gain-setting and feedback
resistors;
RFB = 20kΩ
The internal resistors are ratio trimmed to high accuracy and
have excellent tracking with temperature for low gain drift.
If the internal resistors are used:
INA102
INSTRUMENTATION AMPLIFIER
The INA102 contains internal gain-setting and feedback
resistors;
GAIN = 1 + (40k/RG)
External gain-setting resistors can be used in series with one
of the internal gain-setting resistors. If external gain-setting
resistors are used:
RFB = 20kΩ
INA102 INTERNAL GAIN-SETTING RESISTORS
RG
(Ω)
GAIN
(V/V)
GAIN = 1 + (40k/RGI + RGE])
4.444k
404
40.4
10
100
1000
RGI =one of the four above internal gain-setting resistors (Ω)
RGE = external gain-setting resistor (Ω)
INA111
INSTRUMENTATION AMPLIFIER
The INA111 contains internal gain-setting feedback resistors;
RFB = 25kΩ
The internal resistors are ratio trimmed to high accuracy and
have excellent tracking with temperature for low gain drift.
If the internal resistors are used:
GAIN = 1 + (40k/RG)
External gain-setting resistors can be used in series with one
of the internal gain-setting resistors. If external gain-setting
resistors are used:
GAIN = 1 + (40k/[RGI + RGE])
External gain-setting resistors are used to set the gain at:
GAIN = 1 + (50k/RG)
RG = external gain resistor (Ω)
40
INA120
INSTRUMENTATION AMPLIFIER
The INA120 contains an internal gain-setting and feedback
resistor string;
OPA660
OPERATIONAL TRANSCONDUCTANCE
AMPLIFIER AND BUFFER
This device includes a voltage-controlled current source and
a voltage buffer. The voltage-controlled current source or
Operational Transconductance Amplifier can be viewed as
an “ideal transistor”. The transconductance of the OTA can
be adjusted with an external resistor, allowing bandwidth,
quiescent current and gain tradeoffs to be optimized. Demo
boards are available.
RFB = 20kΩ
INA120 INTERNAL GAIN-SETTING RESISTORS
RG
[Ω]
GAIN
[V/V]
4000
400
44
10
100
1000
OPA675
SWITCHED-INPUT OPERATIONAL AMPLIFIER
The OPA675 is a “classical” high-speed amplifier that has
two differential input stages. Each stage is selectable with
ECL logic.
The internal resistors are ratio-trimmed to high accuracy and
have excellent tracking with temperature for low gain drift.
If the internal gain-setting resistor string is used, it can be
connected to the amplifier input terminals to give accurate
gains of 1, 10, 100, and 1000. The gain equation is the same
as for external gain-setting resistors, but in higher gains, part
of the lower gain-setting resistor is added to the feedback
resistor so the values shown for RG can not be inserted
directly in the equation—see Figure 10.
OPA676
SWITCHED-INPUT OPERATIONAL AMPLIFIER
The OPA676 is a “clasical” high-speed amplifier that has
two differential input stages. Each stage is selectable with
TTL logic.
The internal feedback resistors can be used with external
feedback resistors. If the internal feedback resistors are used
with external gain-setting resistors:
OPA2111
DUAL OPERATIONAL AMPLIFIER
The OPA2111 slew rate is asymmetric with the positivegoing slope faster than the negative-going slope (4V/µs
vs 2V/µs). Since the PSpice macromodel only allows asymmetric slew rate in the opposite direction, a conservative
symmetrical slew rate of 2V/µs was used in the macromodel.
GAIN = 1 + (40k/RG)
Where:
RG = optional gain-setting resistor (Ω) connected between
G5 and G14 with G11 open
External gain-setting and feedback resistors can be used. If
external feedback resistors are used:
GAIN = 1 + (2 • RFB/RG)
Where:
RG = Optional external gain-setting resistor (Ω)
RFB = Optional external feedback resistor (Ω)
OPA111
OPERATIONAL AMPLIFIER
The OPA111 slew rate is asymmetric with the positivegoing slope faster than the negative-going slope (4V/µs vs
2V/µs). Since the PSpice macromodel only allows asymmetric slew rate in the opposite direction, a conservative symmetrical slew rate of 2V/µs was used in the macromodel.
OPA121
OPERATIONAL AMPLIFIER
The OPA121 slew rate is asymmetric with the positivegoing slope faster than the negative-going slope (4V/µs vs
2V/µs). Since the PSpice macromodel only allows asymmetric slew rate in the opposite direction, a conservative symmetrical slew rate of 2V/µs was used in the macromodel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
41
TABLE XI. Content of the Macromodel Disk, Revision F, Listed by Topology Level and Directory. New models in bold.
42
OPA27
OPA37
OPA77
OPA111
OPA121
OPA124
OPA128
OPA129
OPA131
OPA177
INA101
INA102
INA103
INA105
INA106
INA110
INA111
INA114
INA115
INA117
INA118
INA120
INA131
UAF42
OPT101
OPT201
OPT202
OPT209
OPT211
OPA404
OPA445
OPA501
OPA502
OPA511
OPA512
OPA541
OPA602
OPA604
OPA606
OPA620
OPA621
OPA627
OPA637
OPA1013
OPA2107
OPA2111
OPA2131
OPA2541
OPA2604
OPA4131
LEVEL I
STD_MOD
OPA27E
OPA37E
OPA77E
OPA111E
OPA121E
OPA124E
OPA128E
OPA129E
OPA131E
OPA177E
INA101E
INA102E
INA103E
INA105E
INA106E
INA110E
INA111E
INA114E
INA115E
INA117E
INA118E
INA120E
INA131E
UAF42E
OPA404E
OPA445E
OPA501E
OPA502E
OPA511E
OPA512E
OPA541E
OPA602E
OPA604E
OPA606E
OPA620E
OPA621E
OPA627E
OPA637E
OPA1013E
OPA2107E
OPA2111E
OPA2131E
OPA2541E
OPA2604E
OPA4131E
LEVEL II
STD_MOD
VCA610M
OPA27M
OPA604M
OPA628M
OPA671M
OPA675M
OPA676M
OPA2604M
ACF2101M
LEVEL III
STD_MOD
CONTENT OF MACROMODEL DISK
OPA603X
OPA620X
OPA621X
OPA622X1
OPA622X2
OPA623X1
OPA623X2
OPA640X
OPA641X
OPA642X
OPA643X
OPA644X
MPC100X1
MPC100X2
MPC102X1
MPC104X1
ISO120X
ISO121X
ISO130X
BUF600X1
BUF600X2
BUF601X1
BUF601X2
BUF634X
OPA646X
OPA648X
OPA650X
OPA658X
OPA2658X
OPA4658X
OPA660X1
OPA660X2
LEVEL IV
STD_MOD
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated