256-Kbit (32 K × 8) nvSRAM CY14B256LA Features Functional Description

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256-Kbit (32 K × 8) nvSRAM CY14B256LA Features Functional Description | Manualzz

CY14B256LA

256-Kbit (32 K × 8) nvSRAM

256-Kbit (32 K × 8) nvSRAM

Features

25 ns and 45 ns access times

Internally organized as 32 K × 8 (CY14B256LA)

Hands off automatic STORE on power-down with only a small capacitor

STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or AutoStore on power-down

RECALL to SRAM initiated by software or power-up

Infinite read, write, and recall cycles

1 million STORE cycles to QuantumTrap

20-year data retention

Single 3 V +20% to –10% operation

Industrial temperature

44-pin thin small outline package (TSOP) Type II, 48-pin shrunk small outline package (SSOP), and 32-pin small-outline integrated circuit (SOIC) packages

Pb-free and restriction of hazardous substances (RoHS) compliance

Functional Description

The Cypress CY14B256LA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 32 K bytes of 8 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The

SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell.

Data transfers from the SRAM to the nonvolatile elements (the

STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.

For a complete list of related documentation, click here .

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

A

5

A

6

A

7

A

8

A

9

A

11

A

12

A

13

A

14

STATIC RAM

ARRAY

512 X 512

Quantum Trap

512 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

A

0

A

1

A

2

A

3

A

4

A

10

V

CC

V

CAP

POWER

CONTROL

STORE/

RECALL

CONTROL

SOFTWARE

DETECT

HSB

A

13

-

A

0

OE

CE

WE

Cypress Semiconductor Corporation

• 198 Champion Court

Document Number: 001-54707 Rev. *K

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised November 14, 2014

CY14B256LA

Contents

Pinouts .............................................................................. 3

Pin Definitions .................................................................. 4

Device Operation .............................................................. 5

SRAM Read ................................................................ 5

SRAM Write ................................................................. 5

AutoStore Operation .................................................... 5

Hardware STORE Operation ....................................... 5

Hardware RECALL (Power-Up) .................................. 6

Software STORE ......................................................... 6

Software RECALL ....................................................... 6

Preventing AutoStore .................................................. 7

Data Protection ............................................................ 7

Maximum Ratings ............................................................. 8

Operating Range ............................................................... 8

DC Electrical Characteristics .......................................... 8

Data Retention and Endurance ....................................... 9

Capacitance ...................................................................... 9

Thermal Resistance .......................................................... 9

AC Test Loads ................................................................ 10

AC Test Conditions ........................................................ 10

AC Switching Characteristics ....................................... 11

Switching Waveforms .................................................... 11

AutoStore/Power-Up RECALL ....................................... 13

Switching Waveforms .................................................... 13

Software Controlled STORE/RECALL Cycle ................ 14

Switching Waveforms .................................................... 14

Hardware STORE Cycle ................................................. 15

Switching Waveforms .................................................... 15

Truth Table For SRAM Operations ................................ 16

Ordering Information ...................................................... 16

Ordering Code Definitions ......................................... 16

Package Diagrams .......................................................... 17

Acronyms ........................................................................ 20

Document Conventions ................................................. 20

Units of Measure ....................................................... 20

Document History Page ................................................. 21

Sales, Solutions, and Legal Information ...................... 22

Worldwide Sales and Design Support ....................... 22

Products .................................................................... 22

PSoC Solutions ......................................................... 22

Document Number: 001-54707 Rev. *K Page 2 of 22

CY14B256LA

Pinouts

Figure 1. 44-pin TSOP II / 48-pin SSOP pinout

NC

NC

[5]

A

4

CE

DQ

0

DQ

1

V

CC

V

SS

DQ

2

DQ

3

WE

A

5

A

0

A

1

A

2

A

3

A

6

A

7

A

8

A

9

NC

NC

15

16

17

18

19

20

21

22

1

2

7

8

9

10

11

12

13

14

5

6

3

4

44-pin TSOP II

(x 8)

Top View

(not to scale)

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

V

CAP

A

14

A

13

A

12

A

11

A

10

NC

NC

OE

DQ

7

DQ

6

V

SS

V

CC

DQ

5

DQ

4

HSB

NC

NC

[4]

[3]

NC

NC

[2]

NC

[1]

NC

[1]

V

CAP

NC

A

14

A

12

A

7

A

6

A

5

NC

A

4

NC

NC

NC

V

SS

NC

NC

DQ0

A

3

A

2

A

1

A

0

DQ1

DQ2

NC

NC

1

2

11

12

13

14

7

8

9

10

15

16

5

6

3

4

17

18

19

20

21

22

23

24

48-pin SSOP

(x 8)

Top View

(not to scale)

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

V

CC

NC

HSB

WE

A

A

A

13

8

9

NC

A

11

NC

NC

NC

V

SS

NC

NC

DQ6

OE

A

10

CE

DQ7

DQ5

DQ4

DQ3

V

CC

Figure 2. 32-pin SOIC pinout

V

CAP

A

14

NC

A

2

A

1

A

0

DQ

0

DQ

1

DQ

2

V

SS

A

12

A

7

A

6

A

5

A

A

4

3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32 - SOIC

(x8)

Top View

(not to scale)

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

CC

HSB

WE

A

13

A

8

A

9

A

11

OE

NC

A

10

CE

DQ

7

DQ

6

DQ

5

DQ

4

DQ

3

Notes

1. Address expansion for 1-Mbit. NC pin not connected to die.

2. Address expansion for 2-Mbit. NC pin not connected to die.

3. Address expansion for 4-Mbit. NC pin not connected to die.

4. Address expansion for 8-Mbit. NC pin not connected to die.

5. Address expansion for 16-Mbit. NC pin not connected to die.

Document Number: 001-54707 Rev. *K Page 3 of 22

CY14B256LA

Pin Definitions

Pin Name

A

0

–A

14

DQ

0

–DQ

7

WE

CE

OE

V

SS

V

CC

HSB

V

CAP

NC

I/O Type

Input

Description

Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.

Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation.

Input Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location.

Input

Input

Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.

I/O pins are tristated on deasserting OE HIGH.

Ground Ground for the device. Must be connected to the ground of the system.

Power supply Power supply inputs to the device. 3.0 V +20%, –10%

Input/Output Hardware STORE busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.

When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (t optional).

HHHD

) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection

Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements.

No connect No connect. This pin is not connected to the die.

Document Number: 001-54707 Rev. *K Page 4 of 22

CY14B256LA

Device Operation

The CY14B256LA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the

SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations,

SRAM read and write operations are inhibited. The

CY14B256LA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations.

Refer to the

Truth Table For SRAM Operations on page 16

for a complete description of read and write modes.

SRAM Read

The CY14B256LA performs a read cycle when CE and OE are

LOW and WE and HSB are HIGH. The address specified on pins

A

0-14 determines which of the 32,768 data bytes each are accessed. When the read is initiated by an address transition, the outputs are valid after a delay of t

AA

(read cycle 1). If the read is initiated by CE or OE, the outputs are valid at t

ACE

or at t

DOE

, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the t

AA

access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought

HIGH, or WE or HSB is brought LOW.

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ written into the memory if the data is valid t

SD

0–7

are

before the end of a WE-controlled write or before the end of a CE-controlled write.

Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers t

HZWE after WE goes LOW.

AutoStore Operation

The CY14B256LA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by HSB; Software STORE activated by an address sequence;

AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B256LA.

During a normal operation, the device draws current from V charge a capacitor connected to the V charge is used by the chip to perform a single STORE operation.

If the voltage on the V

CC

CAP

pin. This stored

pin drops below V automatically disconnects the V

CAP

SWITCH

pin from V

CC

CC

to

, the part operation is initiated with power provided by the V

. A STORE

CAP

capacitor.

Note If the capacitor is not connected to V

CAP

pin, AutoStore must be disabled using the soft sequence specified in

Preventing

AutoStore on page 7

. In case AutoStore is enabled without a capacitor on V

CAP

pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This will corrupt the data stored in nvSRAM.

Figure 3

shows the proper connection of the storage capacitor

(V

CAP

) for automatic STORE operation. Refer to DC Electrical

Characteristics on page 8

the V

CAP

for the size of V

pin is driven to V

CC

CAP

. The voltage on by a regulator on the chip. Place a pull-up on WE to hold it inactive during power-up. This pull-up is only effective if the WE signal is tristate during power-up. Many

MPUs tristate their controls on power-up. This must be verified when using the pull-up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or

RECALL cycle. Software-initiated STORE cycles are performed regardless of whether a write operation has taken place. The

HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.

Figure 3. AutoStore Mode

V

CC

WE

V

CC

V

SS

V

CAP

0.1 uF

V

CAP

Hardware STORE Operation

The CY14B256LA provides the HSB pin to control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven

LOW, the CY14B256LA conditionally initiates a STORE operation after t

DELAY

. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or

RECALL cycle. The HSB pin also acts as an open drain driver

(internal 100 k

 weak pull-up resistor) that is internally driven

LOW to indicate a busy condition when the STORE (initiated by any means) is in progress.

Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (t

HHHD

) with standard output high current and then remains HIGH by internal 100 k

 pull-up resistor.

SRAM write operations that are in progress when HSB is driven

LOW by any means are given time (t

DELAY

) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven

LOW by the CY14B256LA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source.

Document Number: 001-54707 Rev. *K Page 5 of 22

CY14B256LA

During any STORE operation, regardless of how it is initiated, the CY14B256LA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the

STORE operation, the nvSRAM memory access is inhibited for t

LZHSB

time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used.

Hardware RECALL (Power-Up)

During power-up or after any low-power condition

(V

CC

V

CC

< V

SWITCH

), an internal RECALL request is latched. When

again exceeds the sense voltage of V

SWITCH cycle is automatically initiated and takes t

HRECALL

, a RECALL

to complete.

During this time, HSB is driven low by the HSB driver.

Software STORE

Data is transferred from SRAM to the nonvolatile memory by a software address sequence. The CY14B256LA Software

STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place.

To initiate the Software STORE cycle, the following read sequence must be performed:

1. Read address 0x0E38 valid READ

2. Read address 0x31C7 valid READ

3. Read address 0x03E0 valid READ

4. Read address 0x3C1F valid READ

5. Read address 0x303F valid READ

6. Read address 0x0FC0 initiate STORE cycle

The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW.

After the t

STORE

cycle time is fulfilled, the SRAM is activated again for the read and write operation.

Software RECALL

Data is transferred from nonvolatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed:

1. Read address 0x0E38 valid READ

2. Read address 0x31C7 valid READ

3. Read address 0x03E0 valid READ

4. Read address 0x3C1F valid READ

5. Read address 0x303F valid READ

6. Read address 0x0C63 initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the

SRAM cells. After the t

RECALL

cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.

Table 1. Mode Selection

CE

H

L

L

L

WE

X

H

L

H

OE

X

L

X

L

A

14

–A

0

[6]

X

X

X

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0B45

Mode

Not selected

Read SRAM

Write SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

AutoStore

Disable

I/O

Output high Z

Output data

Input data

Output data

Output data

Output data

Output data

Output data

Output data

Power

Standby

Active

Active

Active

[7]

Notes

6. While there are 15 address lines on the CY14B256LA, only the lower 14 are used to control software modes.

7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.

Document Number: 001-54707 Rev. *K Page 6 of 22

CY14B256LA

Table 1. Mode Selection (continued)

CE

L

L

L

WE

H

H

H

OE

L

L

L

Preventing AutoStore

The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed:

1. Read address 0x0E38 valid READ

2. Read address 0x31C7 valid READ

3. Read address 0x03E0 valid READ

4. Read address 0x3C1F valid READ

5. Read address 0x303F valid READ

6. Read address 0x0B45 AutoStore disable

The AutoStore is reenabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the

A

14

–A

0

[6]

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0B46

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0FC0

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0C63

Mode

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

AutoStore Enable

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile

STORE

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile

Recall

I/O

Output data

Output data

Output data

Output data

Output data

Output data

Output data

Output data

Output data

Output data

Output data

Output high Z

Output data

Output data

Output data

Output data

Output data

Output high Z

Power

Active

[8]

Active I

CC2

[8]

Active

[8]

AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed:

1. Read address 0x0E38 valid READ

2. Read address 0x31C7 valid READ

3. Read address 0x03E0 valid READ

4. Read address 0x3C1F valid READ

5. Read address 0x303F valid READ

6. Read address 0x0B46 AutoStore enable

If the AutoStore function is disabled or reenabled, a manual

STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled and 0x00 written in all cells.

Data Protection

The CY14B256LA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when

V

CC

is less than V

SWITCH

. If the CY14B256LA is in a write mode

(both CE and WE are LOW) at power-up, after a RECALL or

STORE, the write is inhibited until the SRAM is enabled after t

LZHSB

(HSB to output active). This protects against inadvertent writes during power-up or brown out conditions.

Note

8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.

Document Number: 001-54707 Rev. *K Page 7 of 22

CY14B256LA

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage temperature ................................–65

C to +150 C

Maximum accumulated storage time:

At 150

C ambient temperature .......................1000 h

At 85

C ambient temperature ..................... 20 years

Maximum junction temperature ..................................150

C

Supply voltage on V

CC

relative to V ss

........... –0.5 V to 4.1 V

Voltage applied to outputs in high Z state ......................................–0.5 V to V

CC

+ 0.5 V

Input voltage ....................................... –0.5 V to V

CC

+ 0.5 V

Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to V

CC

+ 2.0 V

Package power dissipation capability (T

A

= 25 °C) ..................................................1.0 W

Surface mount Pb soldering temperature (3 seconds) ..........................................+260

C

DC output current (1 output at a time, 1s duration) .....15 mA

Static discharge voltage

(per MIL-STD-883, Method 3015) .......................... > 2001 V

Latch-up current ................................................... > 200 mA

Operating Range

Range

Industrial

Ambient Temperature

–40

C to +85 C

V

CC

2.7 V to 3.6 V

DC Electrical Characteristics

Over the

Operating Range

I

I

I

I

I

I

Parameter

V

CC

I

CC1

CC2

CC3

CC4

SB

IX

[10]

OZ

V

IH

V

IL

V

OH

V

OL

Description

Power supply

Test Conditions

Average V

CC

current

Average V

CC

current during STORE All inputs don’t care, V

CC

= Max

Average current for duration t

STORE

Average V t

RC

CC

current at

= 200 ns, V

CC(Typ)

, 25 °C

All inputs cycling at CMOS levels.

Values obtained without output loads

(I

OUT

= 0 mA).

Average V

CAP

current during

AutoStore cycle t t

(I

RC

RC

= 25 ns

= 45 ns

Values obtained without output loads

OUT

= 0 mA)

V

CC

standby current

All inputs don’t Care. Average current for duration t

STORE

CE > (V

V

IN

CC

– 0.2 V).

< 0.2 V or > (V

CC

– 0.2 V).

Standby current level after nonvolatile cycle is complete.

Inputs are static. f = 0 MHz.

Input leakage current (except HSB) V

CC

= Max, V

SS

< V

IN

< V

CC

Input leakage current (for HSB) V

CC

= Max, V

SS

< V

IN

< V

CC

Off-state output leakage current V

CC

= Max, V

SS

CE or OE > V

IH

< V

OUT

< V or WE < V

IL

CC

,

Input HIGH voltage

Input LOW voltage

Output HIGH voltage

Output LOW voltage I

I

OUT

OUT

= –2 mA

= 4 mA

Min

2.7

–1

–100

–1

2.0

V ss

– 0.5

2.4

Typ

[9]

3.0

35

Max

3.6

70

52

10

5

5

+1

+1

+1

Unit

V mA mA mA mA mA mA

V

CC

+ 0.5

V

0.8

V

V

0.4

V

A

A

A

Notes

9. Typical values are at 25 °C, V

10. The HSB pin has I

OUT

CC

= V

CC(Typ)

. Not 100% tested.

= –2 µA for V

OH

of 2.4 V when both active high and low drivers are disabled. When they are enabled standard V

OH

and V

OL

are valid. This parameter is characterized but not tested.

Document Number: 001-54707 Rev. *K Page 8 of 22

CY14B256LA

DC Electrical Characteristics

(continued)

Over the Operating Range

Parameter

V

CAP

[11]

V

VCAP

[12, 13]

Description Test Conditions

Storage capacitor

Maximum voltage driven on V

CAP by the device

pin

Between V

CAP

pin and V

SS

V

CC

= Max

Data Retention and Endurance

Over the Operating Range

Parameter

DATA

R

NV

C

Data retention

Nonvolatile STORE operations

Description

Capacitance

Parameter

[13]

C

IN

C

OUT

Description Test Conditions

Input capacitance (except HSB) T

A

= 25

C, f = 1 MHz, V

CC

= V

CC(Typ)

Input capacitance (for HSB)

Output capacitance (except HSB)

Output capacitance (for HSB)

Thermal Resistance

Parameter

[13]

JA

JC

Description

Thermal resistance

(Junction to ambient)

Thermal resistance

(Junction to case)

Min

61

Typ

[9]

68

Max

180

V

CC

Unit

F

V

Min

20

1,000

Unit

Years

K

Max

7

8

7

8

Unit

pF pF pF pF

Test Conditions

Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with

EIA/JESD51.

48-pin

SSOP

37.47

24.71

44-pin

TSOP II

41.74

11.9

32-pin

SOIC

Unit

41.55

C/W

24.43

C/W

Notes

11. Min V

V

CAP

CAP

value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V

CAP

value guarantees that the capacitor on

is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V

12. Maximum voltage on V

CAP

pin (V

VCAP

) is provided for guidance when choosing the V temperature range should be higher than the V

VCAP

voltage.

13. These parameters are guaranteed by design and are not tested.

CAP

capacitor. The voltage rating of the V

CAP

CAP

options.

capacitor across the operating

Document Number: 001-54707 Rev. *K Page 9 of 22

CY14B256LA

AC Test Loads

Figure 4. AC Test Loads

3.0 V

OUTPUT

30 pF

577

R1

R2

789

3.0 V

OUTPUT

5 pF

577

R1

For tristate specs

R2

789

AC Test Conditions

Input Pulse Levels .................................................0 V to 3 V

Input Rise and Fall Times (10%–90%) ....................... < 3 ns

Input and Output Timing Reference Levels .................. 1.5 V

Document Number: 001-54707 Rev. *K Page 10 of 22

CY14B256LA

AC Switching Characteristics

Over the Operating Range

Parameters

[14]

Cypress

Parameters

Alt

Parameters

SRAM Read Cycle

t t

ACE

RC

[15]

t

AA

[16]

t t t

ACS

RC

AA t

DOE t t

OHA

[16]

LZCE

[17, 18]

t t t

OE

OH

LZ t

HZCE

[17, 18]

t

LZOE

[17, 18]

t t

HZ

OLZ t

HZOE

[17, 18]

t t

PU

[17]

PD

[17]

t t t

OHZ

PA

PS

SRAM Write Cycle

t

WC t

PWE t

SCE t

SD t

HD t

AW t

SA t

HA t t

HZWE

[17, 18, 19]

LZWE

[17, 18]

t

OW t

WC t

WP t

CW t

DW t

DH t

AW t

AS t

WR t

WZ

Description

Chip enable access time

Read cycle time

Address access time

Output enable to data valid

Output hold after address change

Chip enable to output active

Chip disable to output inactive

Output enable to output active

Output disable to output inactive

Chip enable to power active

Chip disable to power standby

Write cycle time

Write pulse width

Chip enable to end of write

Data setup to end of write

Data hold after end of write

Address setup to end of write

Address setup to start of write

Address hold after end of write

Write enable to output disable

Output active after end of write

Min

25 ns

Max

0

3

3

0

25

25

20

20

10

0

20

0

0

3

10

10

25

25

25

12

10

Min

45 ns

Max

0

3

3

0

45

45

30

30

15

0

30

0

0

3

15

15

45

45

45

20

15

Unit

Switching Waveforms

Figure 5. SRAM Read Cycle #1 (Address Controlled)

[15, 16, 20]

t

RC

Address

Address Valid t

AA

Data Output

Previous Data Valid t

OHA

Output Data Valid

Notes

14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V

CC

/2, input pulse levels of 0 to V

I

OL

/I

OH

and load capacitance shown in

Figure

.

15. WE must be HIGH during SRAM read cycles.

16. Device is continuously selected with CE and OE LOW.

17. These parameters are guaranteed by design and are not tested.

18. Measured ±200 mV from steady state output voltage.

19. If WE is low when CE goes low, the outputs remain in the high impedance state.

20. HSB must remain HIGH during READ and WRITE cycles.

CC(typ)

, and output loading of the specified ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Document Number: 001-54707 Rev. *K Page 11 of 22

CY14B256LA

Switching Waveforms

(continued)

Figure 6. SRAM Read Cycle #2 (CE and OE Controlled)

[21, 22]

Address Address Valid t

RC t

ACE t

HZCE

CE

OE

Data Output

I

CC

Address t

LZCE t

AA t

HZOE t

DOE t

LZOE

High Impedance t

PU

Output Data Valid t

PD

Standby

Active

Figure 7. SRAM Write Cycle #1 (WE Controlled)

[22, 23, 24]

t

WC

Address Valid t

SCE t

HA

CE t

AW t

PWE

WE

Data Input

Data Output

Address t

SA t

SD t

HD t

HZWE

Input Data Valid t

LZWE

High Impedance

Previous Data

Figure 8. SRAM Write Cycle #2 (CE Controlled)

[22, 23, 24]

t

WC t

SA

Address Valid t

SCE t

HA

CE t

PWE

WE t

SD

Data Input Input Data Valid

High Impedance

Data Output

Notes

21. WE must be HIGH during SRAM read cycles.

22. HSB must remain HIGH during READ and WRITE cycles.

23. If WE is low when CE goes low, the outputs remain in the high impedance state.

24. CE or WE must be > V

IH

during address transitions.

t

HD

Document Number: 001-54707 Rev. *K Page 12 of 22

CY14B256LA

AutoStore/Power-Up RECALL

Over the Operating Range

Parameters Description

t

HRECALL

[25]

t

STORE

[26]

t

DELAY

[27]

V

SWITCH t

VCCRISE

[28]

t t

V

HDIS

[28]

LZHSB

[28]

HHHD

[28]

Power-up RECALL duration

STORE cycle duration

Time allowed to complete SRAM write cycle

Low voltage trigger level

V

CC

rise time

HSB output disable voltage

HSB to output active time

HSB high active time

Switching Waveforms

Figure 9. AutoStore or Power-Up RECALL

[29]

V

CC

V

SWITCH

V

HDIS

Note

26

t

STORE t

VCCRISE

Note

30

t

HHHD t

HHHD

HSB OUT t

DELAY t

LZHSB

AutoStore t

LZHSB t

DELAY

POWER-

UP

RECALL

Read & Write

Inhibited

(RWI) t

HRECALL t

HRECALL

POWER-UP

RECALL

Read & Write

BROWN

OUT

AutoStore

POWER-UP

RECALL

Read & Write

POWER

DOWN

AutoStore

150

CY14B256LA

Min Max

– 20

8

25

2.65

1.9

5

500

Note

26

t

STORE

Note

30

Unit

µs

V

µs ns ms ms ns

V

Notes

25. t

HRECALL starts from the time V

CC

rises above V

SWITCH

.

26. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

27. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time t

DELAY

.

28. These parameters are guaranteed by design and are not tested.

29. Read and Write cycles are ignored during STORE, RECALL, and while V

CC

is below V

SWITCH

.

30. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.

Document Number: 001-54707 Rev. *K Page 13 of 22

CY14B256LA

Software Controlled STORE/RECALL Cycle

Over the Operating Range

Parameters

[31, 32]

t

RC t

SA t

CW t

HA t

RECALL

Description

STORE/RECALL initiation cycle time

Address setup time

Clock pulse width

Address hold time

RECALL duration

Min

25

0

20

0

25 ns

Max

200

Min

45

0

30

0

45 ns

Max

200

Switching Waveforms

Figure 10. CE and OE Controlled Software STORE/RECALL Cycle

[32]

t

RC t

RC

Address t

SA

Address #1 t

CW

Address #6 t

CW

CE t

SA t

HA t

HA t

HA t

HA

OE

HSB (STORE only)

DQ (DATA) t

LZCE t

HZCE t

DELAY

33

Note

High Impedance t

STORE

/t

RECALL

RWI

Address t

SA

Figure 11. Autostore Enable / Disable Cycle

[32]

t

RC t

RC

Address #1 Address #6 t

CW t

CW

CE t

SA t t

HA

HA t

HA t

HA

OE t

LZCE t

HZCE

Note

33

t

SS t

DELAY

DQ (DATA)

RWI

Notes

31. The software sequence is clocked with CE controlled or OE controlled reads.

32. The six consecutive addresses must be read in the order listed in

Table 1 on page 6

. WE must be HIGH during all six consecutive cycles.

33. DQ output data at the sixth read may be invalid since the output is disabled at t

DELAY

time.

t

HHHD t

LZHSB

Document Number: 001-54707 Rev. *K Page 14 of 22

Unit

ns ns ns ns

µs

CY14B256LA

Hardware STORE Cycle

Over the Operating Range

Parameters

t

DHSB t t

PHSB

SS

[34, 35]

Description

HSB to output active time when write latch is not set

Hardware STORE pulse width

Soft sequence processing time

CY14B256LA

Min Max

15

25

100

Unit

ns ns

s

Switching Waveforms

Write latch set

t

PHSB

HSB (IN) t

DELAY

HSB (OUT)

DQ (Data Out)

RWI

Write latch not set

t

PHSB

HSB (IN)

Figure 12. Hardware STORE Cycle

[36]

t

STORE t

HHHD t

LZHSB

HSB pin is driven high to V

C

only by Internal

100 kOhm resistor,

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

HSB (OUT)

RWI t

DELAY t

DHSB t

DHSB

Address

Figure 13. Soft Sequence Processing

[34, 35]

Address #1 t

SA

Soft Sequence

Command

Address #6 t

CW

t

SS

Soft Sequence

Command

Address #1 Address #6 t

CW t

SS

CE

V

CC

Notes

34. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

35. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

36. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

Document Number: 001-54707 Rev. *K Page 15 of 22

CY14B256LA

Truth Table For SRAM Operations

HSB must remain HIGH for SRAM operations.

Table 2. Truth Table

CE WE

H

L

X

H

L

L

H

L

OE

X

L

H

X

Inputs/Outputs

High Z

Data out (DQ

0

–DQ

7

);

High Z

Data in (DQ

0

–DQ

7

);

Ordering Information

Speed

(ns)

25

45

Ordering Code

CY14B256LA-ZS25XIT

CY14B256LA-ZS25XI

CY14B256LA-SP25XIT

CY14B256LA-SP25XI

CY14B256LA-SZ25XIT

CY14B256LA-SZ25XI

CY14B256LA-SP45XIT

CY14B256LA-SP45XI

CY14B256LA-SZ45XIT

CY14B256LA-SZ45XI

All the above parts are Pb-free.

Ordering Code Definitions

CY 14 B 256 L A - ZS 25 X I T

Mode

Deselect/power-down

Read

Output disabled

Write

Package Diagram

51-85087

51-85087

51-85061

51-85061

51-85127

51-85127

51-85061

51-85061

51-85127

51-85127

Package Type

44-pin TSOP II

44-pin TSOP II

48-pin SSOP

48-pin SSOP

32-pin SOIC

32-pin SOIC

48-pin SSOP

48-pin SSOP

32-pin SOIC

32-pin SOIC

Option:

T - Tape and Reel

Blank – Std.

Temperature:

I - Industrial (–40 to 85 °C)

Pb-free

Die revision:

Blank – No Rev

A – 1 st

Rev

Voltage:

B – 3.0 V

Package:

ZS - 44-pin TSOP II

SP - 48-pin SSOP

SZ - 32-pin SOIC

Density:

256 – 256 Kb

Data Bus:

L – × 8

14 – nvSRAM

Power

Standby

Active

Active

Active

Operating Range

Industrial

Speed:

25 – 25 ns

45 – 45 ns

Cypress

Document Number: 001-54707 Rev. *K Page 16 of 22

Package Diagrams

Figure 14. 44-pin TSOP II Package Outline, 51-85087

CY14B256LA

Document Number: 001-54707 Rev. *K

51-85087 *E

Page 17 of 22

Package Diagrams

(continued)

Figure 15. 48-pin SSOP (300 Mils) Package Outline, 51-85061

CY14B256LA

51-85061 *F

Document Number: 001-54707 Rev. *K Page 18 of 22

Package Diagrams

(continued)

Figure 16. 32-pin SOIC (300 Mil) Package Outline, 51-85127

CY14B256LA

51-85127 *C

Document Number: 001-54707 Rev. *K Page 19 of 22

Acronyms

Acronym

CE

CMOS chip enable

Description

complementary metal oxide semiconductor

EIA

HSB

I/O electronic industries alliance hardware store busy input/output nvSRAM non-volatile static random access memory

OE

RoHS

RWI

SRAM output enable restriction of hazardous substances read and write inhibited static random access memory

SSOP

SOIC

TSOP

WE shrink small outline package small outline integrated circuit thin small outline package write enable

CY14B256LA

Document Conventions

Units of Measure

pF

V

W ms ns

%

Symbol

°C k

MHz

A

F

s mA degree Celsius kilohm megahertz microampere microfarad microsecond milliampere millisecond nanosecond ohm percent picofarad volt watt

Unit of Measure

Document Number: 001-54707 Rev. *K Page 20 of 22

CY14B256LA

Document History Page

Document Title: CY14B256LA, 256-Kbit (32 K × 8) nvSRAM

Document Number: 001-54707

Revision ECN

Orig. of

Change

Submission

Date

** 2746918 07/31/2009 New data sheet.

*A

*B

2772059

2829117

GVCH /

AESA

GVCH /

PYRS

GVCH

Description of Change

09/30/2009 Updated Software STORE, RECALL and Autostore Enable, Disable soft sequence

12/16/09 Updated STORE cycles to QuantumTrap from 200K to 1 Million

Updated 48-pin SSOP package diagram

Added

Contents . Moved to external web

*C 2894560 GVCH

*D

*E

*F

*G

2995066

3074570

3143330

3315247

GVCH

GVCH

GVCH

GVCH

03/18/10 Added more clarity on HSB pin operation

Updated HSB pin operation in Figure 9 and updated footnote 21

Removed from ordering information table.

CY14B256LA-ZS25XIT, CY14B256LA-ZS25XI, CY14B256LA-ZS45XIT,

CY14B256LA-ZS45XI

Updated

Package Diagrams for spec 51-85061 and 51-85087.

Updated copyright section.

Updated links under section sales, solutions, and legal information.

07/28/2010 Added CY14B256LA-ZS25XI part to ordering information table.

10/29/10 Added CY14B256LA-ZS25XIT part to ordering information table.

Added

Units of Measure table

01/17/2011 Fixed typo in Figure 9 .

*H

*I

*J

3430452

3660776

3759425

GVCH

GVCH

GVCH

07/15/2011 Updated DC Electrical Characteristics (Added Note

11 and referred the same

note in V

CAP

parameter).

Updated

Capacitance

(Included Input capacitance (for HSB) and Output capacitance (for HSB)).

Updated

Thermal Resistance

packages).

(

JA and

JC

values for 44-pin TSOP II

Updated AC Switching Characteristics (Added Note 14

and referred the same note in Parameters).

11/04/2011 Corrected alignment of footnote

24.

Updated

Package Diagrams .

06/29/2012 Updated DC Electrical Characteristics

(Added V

added Note

Note 13

in V

12

and referred the same note in V

VCAP

parameter).

VCAP

VCAP

parameter and its details,

parameter, also referred

09/28/2012 Updated

Maximum Ratings (Removed “Ambient temperature with power

applied” and included “Maximum junction temperature”).

Updated Package Diagrams

(spec 51-85087 (Changed revision from *D to *E), spec 51-85061 (Changed revision from *E to *F)).

*K 4568935 GVCH 11/14/2014 Added documentation related hyperlink in page 1

Document Number: 001-54707 Rev. *K Page 21 of 22

CY14B256LA

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations .

Products

Automotive

Clocks & Buffers

Interface

Lighting & Power Control

Memory

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless

PSoC Solutions

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

© Cypress Semiconductor Corporation, 2009-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-54707 Rev. *K Revised November 14, 2014

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 22 of 22

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Cypress Semiconductor

:

CY14B256LA-SP25XIT CY14B256LA-SP45XI CY14B256LA-SP45XIT CY14B256LA-SZ25XIT CY14B256LA-

SZ45XIT CY14B256LA-SZ45XI CY14B256LA-SP25XI CY14B256LA-SZ25XI CY14B256LA-ZS25XIT

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