NJU3730 I C to PARALLEL CONVERTER PRELIMINARY

NJU3730 I C to PARALLEL CONVERTER PRELIMINARY
NJU3730
PRELIMINARY
2
I C to PARALLEL CONVERTER
! PACKAGE OUTLINE
! GENERAL DESCRIPTION
The NJU3730 is a serial-to-parallel converter IC,
2
which converts I C serial data into 3 bits parallel data.
The NJU3730 incorporates selectable three kinds of
2
I C-slave-address, which are used to distinguish one of
three NJU3730s. Thus, maximum three of the NJU3730
2
can be connected onto the same I C-bus and each
2
NJU3730 operates as a controller for non-I C device or
extensive ports.
2
The NJU3730 is suitable for I C-BUS applications
such as TV, AV amplifier, mini Stereo component,
speaker system and others.
NJU3730R
NJU3730D
! PIN CONFIGURATION
! FEATURES
#
#
#
#
#
#
NJU3730M
2
Converts I C data to parallel data
3 bits parallel output port
Selectable 3 slave addresses
Operating Voltage
2.4 to 5.5V
C-MOS Technology
Package Outline
DIP8, DMP8, VSP8
VDD
SCL
1
8
SDA
2
7
DO2
SEL
3
6
DO1
VSS
4
5
DO0
! BLOCK DIAGRAM
VDD
VSS
SCL
Output
DO0
Output
DO1
Output
DO2
2
2
I C BUS
Interface
SDA
I C to
Parallel
Converter
SEL
2006/04/06
-1-
NJU3730
! TERMINAL DESCRIPTION
NO.
1
2
3
4
5
6
7
8
-2-
SYMBOL
SCL
SDA
SEL
VSS
DO0
DO1
DO2
VDD
I/O
I
I/O
I
O
O
O
-
FUNCTION
2
I C-bus Serial Clock Input Terminal
2
I C-bus Serial Data Input/Output Terminal
Slave-address Select Terminal
GND: VSS=0V
Output Terminal
Output Terminal
Output Terminal
Power Supply: VDD=3V / 5V
2006/04/06
NJU3730
NJU3555
! FUNCTIONAL DESCRIPTION
(1) Data Transmission
2
NJU3730 is controlled by I C-bus using the SCL and the SDA terminals. NJU3730 is a receive-only slave, and
doesn’t correspond to the general call address (“0000 0000”).
The data transfer is available, when the following timing is executed. When the data transferred exactly, NJU3730
outputs “L” level signal from the SDA terminal as acknowledge signal just after each 8 bits.
Slave-address
S
SCL
1
2
SDA
0
1
A
7
8
Output data
9
1
2
7
A
8
P
S: Start condition
A: Acknowledge bit
P: Stop condition
9
0
LSB
MSB
LSB
MSB
DO2,1,0
Fig.1 Data Transfer Timing
(1-1) Start Condition
A falling edge of the SDA terminal while the SCL terminal is “H” level is defined as the Start condition. After
the Start condition, NJU3730 starts reading the data.
(1-2) Slave-address
The first byte defines the slave-address. When NJU3730 acknowledges a coincidence its own address with
th
the address information, it outputs the Acknowledge at 9 bit timing.
(1-3) Output Data
th
The second byte defines the output data. NJU3730 outputs the Acknowledge at 9 bit timing.
(1-4) Stop Condition
A rising edge of the SDA terminal while the SCL terminal is “H” level is defined as the Stop condition. After the
Stop condition, NJU3730 finishes reading the data.
(2) Slave-address
The slave-address is selected by the condition of the SEL terminal.
SEL
Low Level
Open
High Level
Slave-address
0100 0000
0100 0010
0100 0100
(3) Output Terminal (DO0-2) Settings
Output level of the DO0 to DO2 terminals is selected by the condition of the LSB 3 bits of the output data.
DO2
L
L
L
L
H
H
H
H
2006/04/06
DO1
L
L
H
H
L
L
H
H
DO0
L
H
L
H
L
H
L
H
Output Data
XXXX X000
XXXX X001
XXXX X010
XXXX X011
XXXX X100
XXXX X101
XXXX X110
XXXX X111
Initial Value
$
-3-
NJU3730
! ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
PARAMETER
RATING
UNIT
-0.3 to +7.0
V
-0.3 to VDD+0.3
V
500 (DIP)
Power Dissipation
PD
300 (DMP)
mW
320 (VSP)
Operating Temperature
Topr
-40 to +85
°C
Storage Temperature
Tstg
-40 to +125
°C
Note 1) All voltage values are specified as VSS=0V.
Note 2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed.
Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond
the electrical characteristics conditions will cause malfunction and poor reliability.
Note 3) Decoupling capacitors should be connected between VDD-VSS due to the stabilized operation.
Supply Voltage
Input Voltage
SYMBOL
VDD
VI
! ELECTRICAL CHARACTERISTICS
# DC Characteristics
PARAMETER
Operating Voltage
SYMBOL
VDD
Operating Current
IDD
Low level Input Voltage
High level Input Voltage
Low level Output Voltage
High level Output Voltage
Input Leakage Current
VIL
VIH
VOL
VOH
ILI
(Ta=25°C, VDD=2.4 to 3.6V, VSS=0.0V, unless otherwise noted)
CONDITION
MIN.
TYP.
MAX.
UNIT
2.4
3.6
V
VDD=3.0V
150
200
µA
No signal, without pull up resistor
0
0.2VDD
V
0.8VDD
VDD
V
VDD=3.0V , IOL=1mA
0
0.6
V
VDD=3.0V ,IOH=-1mA
VDD-0.4
VDD
V
VI=VDD or VSS
-1
1
uA
# DC Characteristics
PARAMETER
Operating Voltage
Operating Current
Low level Input Voltage
High level Input Voltage
Low level Output Voltage
High level Output Voltage
Input Leakage Current
-4-
(Ta=25°C, VDD=4.5 to 5.5V, VSS=0.0V, unless otherwise noted)
SYMBOL
CONDITION
MIN.
TYP.
MAX.
UNIT
VDD
4.5
5.5
V
VDD=5.0V
250
300
ΜA
IDD
No signal, without pull up resistor
VIL
0
0.2VDD
V
VIH
0.8VDD
VDD
V
VOL
VDD=5.0V , IOL=1mA
0
0.4
V
VOH
VDD=5.0V , IOH=-1mA
VDD-0.4
VDD
V
ILI
VI=VDD or VSS
-1
1
uA
2006/04/06
NJU3730
NJU3555
# AC Characteristics
(Ta=25°C, VDD=2.4 to 5.5V, VSS=0.0V, unless otherwise noted)
SYMBOL
MIN.
TYP.
MAX.
UNIT
PARAMETER
Maximum Clock Frequency
fSCL
Data Change Minimum Waiting Time
tBUF
4.7
Data Transfer Start Minimum Waiting Time
tHD:STA
4.0
Low Level Clock Pulse Width
tLOW
4.7
High Level Clock Pulse Width
tHIGH
4.0
Minimum Start Preparation Waiting Time
tSU:STA
4.7
Minimum Data Hold Time
tHD:DAT
5.0
Minimum Data Preparation Time
tSU:DAT
250
Rise Time
tR
Fall Time
tF
Minimum Stop Preparation Waiting Time
tSU:STO
4.0
2
Note 4) I C-bus Load Condition: Pull up resistance 4kΩ (Connected to +5V),
Load capacitance 200pF (Connected to GND).
100
1.0
300
-
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
SDA
tR
tBUF
tF
tHD:STA
SCL
tHD:STA tLOW
P
tHD:DAT
tHIGH
tSU:STA
tSU:DAT
S
tSU:STO
Sr
P
# OUTPUT DELAY TIME
PARAMETER
Output Delay Time 1 (VDD=3.0V)
Output Delay Time 2 (VDD=5.0V)
Note 5) DOx terminal, CL=50pF
SYMBOL
MIN.
tDO1
tDO2
-
(Ta=25°C, VSS=0.0V)
TYP.
MAX.
UNIT
-
200
100
ns
ns
SCL
tDO1,2
DO2,1,0
2006/04/06
-5-
NJU3730
•
Power Supply Startup
(Ta=25°C, VDD=2.4 to 5.5V, VSS=0.0V, unless otherwise noted)
Parameter
SYMBOL
MIN.
TYP.
MAX.
UNIT
Startup time of power supply
trDD
0.1
5
ms
Time for Power supply off
tOFF
1
ms
If the above conditions cannot be met, the internal reset circuit will malfunction.
trDD
VDD
tOFF
tOFF is the period when VDD is
below than 0.2V during power
temporarily blackout or power
cycle on/off.
2.2V
0.2V
! APPLICATION CIRCUIT
+5V
2
MCU
I C-bus
0.1µF
SCL
VDD 8
2 SDA
DO2 7
3
SEL
DO1 6
4
VSS
DO0 5
1
+5V
47µF
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
-6-
2006/04/06
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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NJU3730M NJU3730D NJU3730R-TE1
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