PT7C4302

PT7C4302
PT7C4302
Real-time Clock Module (3-wire Interface)
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Description
Features

Using external 32.768kHz quartz crystal

Real-time clock (RTC) counts seconds, minutes
hours, date of the month, month, day of the week,
and year with leap-year compensation valid up to
2099


31-byte, nonvolatile (NV) RAM for data storage
Time keeping voltage: 1.5V to 5.5V

Uses less than 300nA at 2.0V

Simple 3-wire interface


Serial I/O for minimum pin count
Burst mode for reading/writing successive addresses
in clock/RAM


TTL-compatible (VCC = 5V)
Optional industrial temperature range: -40°C to
+85°C
Battery backup


The PT7C4302 serial real-time clock is a lowpower clock/calendar with a programmable square-wave
output and 31 bytes of nonvolatile RAM.
Address and data are transferred serially via a 3wire bus. The clock/calendar provides seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections
for leap year. The clock operates in either the 24-hour or
12-hour format with AM/PM indicator.
Table 1 shows the basic functions of PT7C4302.
More details are shown in section: overview of functions.
Pin Assignment
PT7C4302
1
Trickle charger on chip for rechargeable energy
source backup
VCC2
VCC1
8
2
X1
SCLK
7
3
X2
I/O
6
4
GND
RST
5
DIP-8
SOIC-8
Pin Description
Pin no.
Pin
Type
Description
1
VCC
2
P
Primary power. When VCC2 is greater than VCC1 + 0.2V, VCC2 will power the IC. While VCC2<VCC1, VCC1
will power the IC.*1
2
3
4
X1
X2
GND
I
O
P
5
RST
I
6
I/O
I/
O
Serial Data Input/Output. I/O is the input/output pin for the 3-wire serial interface. The pin has a 40k
internal pull-down resistor.
7
SCL
K
I
Serial Clock Input. SCLK is used to synchronize data movement on the 3-wire serial interface. The pin
has a 40k internal pull-down resistor.
8
VCC
1
P
Backup power. When VCC2 is greater than VCC1 + 0.2V, VCC2 will power the IC. While VCC2<VCC1, VCC1
will power the IC. *1
Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them.
Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.
Ground.
Reset. The reset signal must be asserted high during a read or a write. This pin has a 40kΩ internal pulldown resistor.
Note*1: If VCC1 connects to battery, the battery voltage VCC1 has to be lower than VCC2 - 0.2Vwhen IC is read and written.
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PT7C4302
Real-time Clock Module (3-wire Interface)
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Function Block
PT7C4302
X1
CD
32.768
kHz
X2
OSC
Counter
Chain
31 x 8
RAM
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
CG
Address
Decoder
Address
Register
SCLK
I /O
Interface
(3-wires)
Power Manager
VCC2
RST
Shift Registers
VCC1
I/O
Note: CD=CG=11pF
Maximum Ratings
Storage Temperature…………………………………...-65℃ to +150℃
Ambient Temperature with Power Applied......................-40℃ to +85℃
Supply Voltage to Ground Potential (Vcc to GND) ……………..-0.3V to +6.5V
DC Input (All Other Inputs except Vcc & GND)………………..-0.3V to +6.5V
DC Output Voltage (SDA, /INTA, /INTB pins)………………...-0.3V to +6.5V
Power Dissipation ........................................320mW (Depend on package)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Recommended Operating Conditions
Symbol
VCC1
VCC2
Description
Min
Type
Max
Backup power voltage
Timing data and RAM data maintaining voltage
1.5
-
5.5
1.2
-
5.5
Timing data writing voltage
1.5
-
5.5
Timing data reading voltage
1.5
-
5.5
RAM data writing voltage
3.0
-
5.5
RAM data reading voltage
1.5
-
5.5
Unit
V
VIH
Input high level
2
-
VCC+0.3
VIL
Input low level
-0.3
-
0.3
TA
Operating temperature
-40
-
85
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PT7C4302
Real-time Clock Module (3-wire Interface)
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DC Electrical Characteristics
Unless otherwise specified, GND =0V, T A = 25 °C, Oscillation frequency = 32.768 kHz.
Sym
VCC1
Item
Backup power voltage
Pin
Conditions
VCC1
Timing and RAM data maintaining
VCC2
Timing data writing voltage
Timing data reading voltage
RAM data writing voltage
RAM data reading voltage
VCC2
Min
Typ
Max
Unit
-
1.5
-
5.5
V
-
1.2
-
5.5
-
1.5
1.5
3.0
1.5
2.0
1.4
2.0
1.4
1.6
2.4
0.5
1
100
100
1.1
0.6
1.3
0.9
1.9
0.9
1.9
0.9
0.08
0.11
1.9
4.9
5.5
5.5
5.5
5.5
0.4
1.2
0.425
1.28
25.3
81
25
80
0.8
0.4
0.8
0.6
0.4
0.4
-
OSC on, Note 2, 5
ICC1
Current consumption
VCC1
OSC on, Note 1, 5
OSC off, Note 4,
5, 7
OSC on, Note 2, 6
ICC2
Current consumption
VCC2
OSC on, Note 1, 6
OSC off, Note 4, 6
VCC1: 2V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 2V
VCC1: 5V
VCC1: 2V
IOH = 1.5mA, VCC = 2V
IOH = 4.0mA, VCC = 5V
IOH = -0.4mA, VCC = 2V
IOH = -1.0mA, VCC = 5V
V
mA
A
nA
mA
A
A
VIL1
Low-level input voltage
SCL, /RST
VIH1
High-level input voltage
SCL, /RST
VIL2
Low-level input voltage
X1
VIH2
High-level input voltage
X1
VOL
Low-level output voltage
I/O
VOH
High-level output voltage
I/O
IIL
Input leakage current
/RST,SCLK
Note 3
-
-
500
A
IOZ
Output current when OFF
I/O
Note 3
-
-
500
A
VTD
Trickle Charge Diode Voltage Drop
-
-
-
0.7
-
V
Trickle charge resistors
-
-
-
2
4
8
-
k
R1
R2
R3
V
V
V
V
V
V
Note:1. I/O open, /RST set to a logic 0, and /EOSC bit = 0 (oscillator enabled).
2. I/O pin open, /RST high, SCLK=2MHz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V, and /EOSC bit = 0 (oscillator
enabled).
3. /RST, SCLK, and I/O all have 40k pull-down resistors to ground.
4. /RST, I/O, and SCLK open. The /EOSC bit = 1 (oscillator disabled).
5. VCC2 = 0V.
6. VCC1 = 0V.
7. Typical values are at 25C.
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Real-time Clock Module (3-wire Interface)
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AC Electrical Characteristics
Figure 6 a Timing diagram: Read data transfer
Figure 6 b Timing diagram: Write data transfer
TA = -40 °C to +85 °C. Unless otherwise specified.
Parameter
Data to CLK Setup
tDC
CLK to Data Hold
tCDH
CLK to Data Delay
tCDD
CLK Low Time
tCL
CLK High Time
tCH
CLK Frequency
tCLK
CLK Rise and Fall
tR ,tF
RST to CLK Setup
tCC
CLK to RST Hold
tCCH
RST Inactive Time
tCWH
RST to I/O High-Z
tCDZ
SCLK to I/O High-Z
tCCZ
Sym
Min
Typ
Max
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
200
50
280
70
1000
250
-
800
200
-
VCC=2.0V
1000
-
-
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
VCC=2.0V
VCC=5.0V
250
0
4
1
240
60
4
1
-
-
0.5
2.0
2000
500
280
70
280
70
Unit
Notes
ns
1
ns
1
ns
1,2,3
ns
1
ns
1
MHz
1
ns
1
s
1
ns
1
s
1
ns
1
ns
1
Note:
1. Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time.
2. Measured at VOH = 2.4V or VOL = 0.4V.
3. Load capacitance = 50pF.
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Real-time Clock Module (3-wire Interface)
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Recommended Layout for Crystal
Note: The crystal, traces and crystal input pins
should be isolated from RF generating signals.
Built-in Capacitors Specifications and Recommended External Capacitors
Parameter
Symbol
Typ
Unit
X1 to GND
CG
11
pF
Build-in capacitors
X2 to GND
CD
11
pF
X1 to GND
C1
12
pF
Recommended External capacitors for
crystal CL=12.5pF
X2 to GND
C2
12
pF
X1 to GND
C1
0
pF
Recommended External capacitors for
crystal CL=6pF
X2 to GND
C2
0
pF
Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768 KHz, C1 and C2 should
meet the equation as below:
Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL
Cpar is all parasitical capacitor between X1 and X2.
CL is crystal’s load capacitance.
Crystal Specifications
Parameter
Nominal Frequency
Series Resistance
Load Capacitance
Symbol
fO
ESR
CL
Min
-
Typ
32.768
6/12.5
2015-11-0004
Max
70
-
Unit
kHz
k
pF
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PT7C4302
Real-time Clock Module (3-wire Interface)
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Function Description
Overview of Functions
1.
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year
that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099.
2.
Interface with CPU
Simple 3-wire interface.
3.
Oscillator enable/disable
Oscillator can be enabled or disable by /EOSC bit. But time count chain does not shut down when the bit is logic 1.
4.
Charger function
The function is controlled by trickle charge register. Customer can select the charge current by select the number of diode and
resistor value through the register.
For example:
Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume that the trickle
charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum current IMAX would,
therefore, be calculated as follows:
IMAX = (5.0V - diode drop)/R1 _ (5.0V - 0.7V) / 2kΩ _ 2.2mA
As the super cap charges, the voltage drop between VCC1 and VCC2 will decrease and, therefore, the charge current will
decrease.
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Real-time Clock Module (3-wire Interface)
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Registers
1.
Allocation of registers
Addr.
(hex)
Function
*1
Register definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
Seconds (00-59)
/EOSC*2
S40
S20
S10
S8
S4
S2
S1
01
Minutes (00-59)
0
M40
M20
M10
M8
M4
M2
M1
02
Hours (00-23 / 01-12)
12, /24
0
H20 or
P /A
H10
H8
H4
H2
H1
03
Dates (01-31)
0
0
D20
D10
D8
D4
D2
D1
04
Months (01-12)
0
0
0
MO10
MO8
MO4
MO2
MO1
05
Days of the week (01-07)
0
0
0
0
0
W4
W2
W1
06
Years (00-99)
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
07
Control
WP*3
0
0
0
0
0
0
0
08
Trickle charger
TCS*4
TCS
TCS
TCS
DS*5
DS
RS*6
RS
1F
Clock burst*7
-
-
-
-
-
-
-
-
RAM*9
-
-
-
-
-
-
-
-
RAM burst*8
-
-
-
-
-
-
-
-
20~3E
3F
Caution points:
*1. PT7C4302 uses 5 bits for address. It’s address byte consists of 1 + RAM/Clock select bit +5-bit addr. + Read/Write select bit.
*2. Oscillator Enable bit. When this bit is set to 1, oscillator is stopped but time count chain is still active.
*3. WP: Write Protect bit. WP bit should be cleared before attempting to write to the device.
*4. TCS: Trickle Charger Select.
*5. DS: Diode Select.
*6. RS: Resistor Select.
*7. Clock burst register address is used as clock/calendar burst mode operation address for consecutively read/write 0~7H
registers. Clock/calendar burst mode operation can continuously read 0H to maximum 7H registers in order; write 0~7H registers
in order. Less or larger than 8 bytes in clock burst write mode are ignored.
*8. RAM burst register address is used as RAM burst mode operation address for consecutively read/write 20~3EH RAM. Less
than 31 bytes in RAM burst read/write mode are valid.
*9. PT7C4302 has 318 static RAM for customer use. It is volatile RAM.
*10.
All bits marked with "0" are read-only bits. Their value when read is always "0". All bits marked with "-" are customer
using space.
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Real-time Clock Module (3-wire Interface)
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2. Control and status register
Addr.
Description
D7
(hex)
Control
(default)
07
WP
0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WP: Write Protect bit.
WP
Data
Description
Default
0
Write operation is enabled.
1
Prevent a write operation to any other register.
Read / Write
3. Time Counter
Time digit display (in BCD code):
 Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
 Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
 Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to
12 a.m. or 23 to 00.
Addr.
(hex)
Description
D7
00
Seconds
(default)
/EOSC*
0
S40
S20
S10
S8
S4
S2
S1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
01
Minutes
(default)
0
0
M40
M20
M10
M8
M4
M2
M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
02
Hours
(default)
12, /24
Undefined
D6
0
0
D5
D4
D3
D2
D1
D0
H20 or P,/A
H10
H8
H4
H2
H1
Undefined Undefined Undefined Undefined Undefined Undefined
* Note: /EOSC bit must be written into 0 to start the time count.
a)
12 / 24 bit
This bit is used to select between 12-hour clock operation and 24-hour clock operation.
12, /24
Description
Hours register
0
24-hour time display
1
12-hour time display
24-hour clock
00
01
02
03
04
05
06
07
08
09
10
11
12-hour clock
92 ( AM 12)
81 ( AM 01 )
82 ( AM 02 )
83 ( AM 03 )
84 ( AM 04 )
85 ( AM 05 )
86 ( AM 06 )
87 ( AM 07 )
88 ( AM 08 )
89 ( AM 09 )
90 ( AM 10 )
91 ( AM 11 )
24-hour clock
12
13
14
15
16
17
18
19
20
21
22
23
12-hour clock
B2 ( PM 12 )
A1 ( PM 01 )
A2 ( PM 02 )
A3 ( PM 03 )
A4 ( PM 04 )
A5 ( PM 05 )
A6 ( PM 06 )
A7 ( PM 07 )
A8 ( PM 08 )
A9 ( PM 09 )
B0 ( PM 10 )
B1 ( PM 11 )
Be sure to select between 12-hour and 24-hour clock operation before writing the time data.
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PT7C4302
Real-time Clock Module (3-wire Interface)
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4. Days of the week Counter
The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that
correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on).
Illogical time and date entries result in undefined operation.
Addr.
(hex)
Description
D7
D6
D5
D4
D3
05
Days of the week
(default)
0
0
0
0
0
0
0
0
0
0
D2
D1
D0
W4
W2
W1
Undefined Undefined Undefined
5. Calendar Counter
The data format is BCD format.
 Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).
Range from 1 to 30 (for April, June, September and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
 Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
 Year digits: Range from 00 to 99 and 00, 04, 08, …, 92 and 96 are counted as leap years.
Addr.
(hex)
Description
D7
D6
03
Dates
(default)
0
0
0
0
04
Months
(default)
0
0
0
0
06
Years
(default)
D5
D4
D3
D2
D1
D0
D20
D10
D8
D4
D2
D1
Undefined Undefined Undefined Undefined Undefined Undefined
0
0
M10
M8
M4
M2
M1
Undefined Undefined Undefined Undefined Undefined
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
6.
Trickle Charger
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
8
Trickle charger
(default)
TCS
0
TCS
1
TCS
0
TCS
1
DS
1
DS
1
RS
0
RS
0
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PT7C4302
Real-time Clock Module (3-wire Interface)
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a) Trickle Charger Select
Control the selection of the trickle charger.
TCS
Data
Read/
Write
b)
Other patent
Disable the trickle charger
1010
Enable the trickle charger
* Default 0101
Diode Select
DS
Data
00 or 11
Read/
Write
c)
Description
Select whether one diode or two diodes are connected between VCC2 and VCC1.
Description
* Default
The trickle charger is disabled independently of TCS.
01
One diode is selected.
10
Two diodes are selected.
Resistor Select
RS
Read/
Write
Data
Select whether one diode or two diodes are connected between VCC2 and VCC1.
Description
00
No resistor.
01
R1 with typ. 2k
10
R2 with typ. 4k
11
R3 with typ. 8k
* Default
Communication
1.
3-wire Interface
a)
Command Byte
Figure 1 Command byte
The command byte is shown in Figure 1. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If
it is 0, writes to the PT7C4302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1
through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or
read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
b) RST and SCL Signal
All data transfers are initiated by driving the RST input high and terminated by driving the RST input low. A clock cycle is a
sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and
data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the SDA pin goes to a high
impedance state. Data transfer is illustrated in Figure 2 and Figure 3. At power-up, RST must be a logic 0 until VCC > 2.0V. Also
SCLK must be at a logic 0 when RST is driven to a logic 1 state.
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c)
Single Byte Read
Figure 2 Single byte read
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK
cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written.
Additional SCLK cycles will transmit the same data bytes by PT7C4302 so long as RST remains high. This operation permits
continuous burst mode read capability. Also, the SDA pin is tri-stated upon each rising edge of SCLK. Data is output starting with
bit 0.
d)
Single Byte Write
Figure 3 Signal byte write
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK
cycles. Additional SCLK cycles are ignored. Data is input starting with bit 0.
e) Burst Mode
Burst mode is specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (Address bits: A4 A3
A2 A1 A0 = 1 1 1 1 1 showed in Figure 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no
data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or
writes in burst mode start with bit 0 of address 0.
When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred.
If the number of transferred bytes is less than eight, the data will be ignored. However, when writing to RAM in burst mode, it is
not necessary to write all 31 bytes for the data to transfer. Each byte that is written will be transferred to RAM regardless of
whether all 31 bytes are written or not. Additional SCLK cycles are ignored.
 Clock/Calendar Burst Mode
The clock/calendar command byte specifies burst mode operation. In this mode the first eight clock/calendar registers can be
consecutively read or written starting with bit 0 of address 0.
If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the
eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode.
At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read
from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an
update of the main registers during a read.
 RAM Burst Mode
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written
starting with bit 0 of address 0.
Note: PT7C4302 use 94H, 96H as test mode address. Customer should not use the address.
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Real-time Clock Module (3-wire Interface)
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Mechanical Information
WE (8-Pin SOIC)
Symbol
A
A1
A2
b
c
D
E
E1
e
L
θ
Note:
1) Controlling dimensions in millimeters.
2) Ref : JEDEC MS-012E/AA
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Dimensions In Millimeters
Min
Max
1.350
1.750
0.100
0.250
1.350
1.550
0.330
0.510
0.170
4.700
3.800
5.800
0.400
0°
0.250
5.100
4.000
6.200
1.27 BSC
1.270
8°
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Real-time Clock Module (3-wire Interface)
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ZEE (Lead free and Green 8-Pin TDFN)
PKG.
DIMENSIONS(MM)
SYMBOL
MIN.
MAX
A
0.700
0.800
A1
0.000
0.500
0.203REF
A3
D
1.924
2.076
E
2.924
3.076
D1
1.400
1.600
E1
1.400
1.600
0.200MIN
k
b
0.200
0.300
0.500TYP
e
L
0.224
0.376
Note:
Ref: JEDEC MO-229
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Real-time Clock Module (3-wire Interface)
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Ordering Information
Part Number
Package Code
Package
PT7C4302WE
W
Lead Free and Green 8-Pin SOIC (W)
PT7C4302WEX
W
Lead Free and Green 8-Pin SOIC (W) Tape/Reel
PT7C4302ZEE
ZE
Lead free and Green 8-Pin TDFN (ZE)
PT7C4302ZEEX
ZE
Lead free and Green 8-Pin TDFN (ZE) Tape/Reel
Notes:

E = Pb-free and Green

Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation  1-800-435-2336  www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom
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