Low Input Voltage and High Efficiency Synchronous DATASHEET ISL9113

Low Input Voltage and High Efficiency Synchronous DATASHEET ISL9113

DATASHEET

Low Input Voltage and High Efficiency Synchronous

Boost Converter with 1.3A Switch

ISL9113

The ISL9113 provides a power supply solution for devices powered by three-cell alkaline, NiCd, NiMH or one-cell

Li-Ion/Li-Polymer batteries. It offers either a fixed 5V or an adjustable output option for USB-OTG or portable HDMI applications. The device is guaranteed to supply 500mA from a 3V input and 5V output and has a typical 1.3A peak current limit. High 1.8MHz switching frequency allows for the use of tiny, low-profile inductors and ceramic capacitors to minimize the size of the overall solution.

The ISL9113 is an internally compensated, fully integrated synchronous converter optimized for efficiency with minimal external components. At light load, the device enters skip mode and consumes only 20µA of quiescent current, resulting in higher efficiency at light loads and maximum battery life.

The device is available in an 8 Ld DFN package and a 6 bump

WLCSP.

Related Literature

• AN1816 , “ISL9113ERAZ-EVZ, ISL9113ER7Z-EVZ Evaluation

Board User Guide”

Features

• Up to 95% efficiency at typical operating conditions

• Input voltage range: 0.8V to 4.7V

• Output current: Up to 500mA (V

BAT

= 3.0V, V

OUT

= 5.0V)

• Low quiescent current: 20μA (typical)

• Logic control shutdown (I

Q

< 1µA)

• Fixed 5V, 5.1V or adjustable output

• 1.2V EN high logic

• Output disconnect during shutdown

• Skip mode under light load condition

• Undervoltage lockout

• Fault protection: OVP (ADJ version only), OTP, short circuit

• 8 Ld 2mmx2mm DFN package and 6 bump

0.8mmx1.36mm WLCSP

Applications

• Products including portable HDMI and USB-OTG

• Smartphones

• Tablet and mobile internet devices

2.2µH

V

BAT =

0.8V TO 4.7V

4.7µF

V

FAULT

7

V

BAT

5

EN

SW

8

1k

4

FAULT

V

OUT

NC

PGND

AGND

1

6

2

3

V

OUT

=

5V/500mA

4.7µF

FIGURE 1. TYPICAL APPLICATION (ISL9113ER7Z)

100

95

90

V

BAT

= 3.0V

V

BAT

= 4.2V

V

BAT

= 3.6V

85

80

75

70

65

V

BAT

= 1.2V

V

BAT

= 2.3V

60

55

V

OUT

= 5.0V

50

0.0001

0.001 0.01 0.1

LOAD CURRENT (A)

FIGURE 2. FIXED 5V EFFICIENCY (ISL9113ER7Z)

1

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FN8313.3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

|

Copyright Intersil Americas LLC 2012, 2013, 2015. All Rights Reserved

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL9113

Block Diagrams

ISL9113ER7Z

C1

FAULT

UVLO

V

BAT

7

V

INT

VOLTAGE

SELECTOR

4

V

OUT

START-UP

OVP

CONTROL LOGIC

ZCD

GATE

DRIVER

AND

ANTI-CROSS

CONDUCTION

SW

V

OUT

CURRENT

SENSE

V

OUT

2

C2

N-WELL

SWITCH

8

SW

L1

AND

FAULT

MONITORING

DIGITAL

SOFT-START

CURRENT

LIMIT

SLOPE COMP

V

OUT

EN

5

OFF ON g m

VOLTAGE

CLAMP

1.8MHz

OSCILLATOR

THERMAL

SHUTDOWN

REFERENCE

GENERATOR

1

6

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ISL9113

Block Diagrams

(Continued)

ISL9113ERAZ

C1

UVLO

V

BAT

7

V

INT

VOLTAGE

SELECTOR

EN

5

OFF ON

V

OUT

START-UP

OVP

CONTROL LOGIC

ZCD

GATE

DRIVER

AND

ANTI-CROSS

CONDUCTION

SW

V

OUT

CURRENT

SENSE

V

OUT

2

C2

N-WELL

SWITCH

8

SW

L1

AND

FAULT

MONITORING

DIGITAL

SOFT-START

CURRENT

LIMIT

SLOPE COMP

4

FB g m

VOLTAGE

CLAMP

1.8MHz

OSCILLATOR

THERMAL

SHUTDOWN

REFERENCE

GENERATOR

1 6

R1

R2

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ISL9113

Pin Configurations

FIXED OUTPUT

(8 LD DFN)

TOP VIEW

PGND

1

V

OUT

2

NC 3

FAULT

4

8

SW

7 V

BAT

6 AGND

5

EN

PGND

1

V

OUT

2

NC 3

FB

4

ADJUSTABLE OUTPUT

(8 LD DFN)

TOP VIEW

8

SW

7 V

BAT

6 AGND

5

EN

SW

FIXED OUTPUT

(6 BUMP WLCSP)

TOP VIEW

A1

A2 PGND

V

BAT

B1 B2

V

OUT

EN

C1

C2

FAULT

ADJUSTABLE OUTPUT

(6 BUMP WLCSP)

TOP VIEW

SW

A1

A2 PGND

V

BAT

B1 B2

V

OUT

EN

C1

C2

FB

Pin Descriptions

8 LD DFN

PIN NUMBERS

FIXED

OUTPUT

ADJUSTABLE

OUTPUT

3

4

1

2

1

2

3

-

6 BUMP WLCSP

PIN NUMBERS

FIXED

OUTPUT

ADJUSTABLE

OUTPUT

A2

B2

-

C2

A2

B2

-

-

SYMBOL

-

5

6

7

8

4

5

6

7

8

-

C1

-

B1

A1

-

C2

C1

-

B1

A1

-

PIN DESCRIPTIONS

PGND Power ground

V

OUT

NC

Device output

No connection

FAULT Fault output; outputs logic LOW under a number of fault conditions (see

Table 1 on page 9

).

FB

EN

Feedback pin of the converter. Connect voltage divider resistors between

V

OUT

, FB and GND for desired output.

The EN pin is an active-HIGH logic input for enabling the device. When asserted HIGH, the boost function begins. When asserted LOW, the device is completely disabled, and current is blocked from flowing from the SW pin to the output and vice versa. This pin should be tied either HIGH to enable the device, or LOW to disable the device.

AGND Analog ground

V

BAT

SW

EPAD

Device input supply from a battery. Connect a 4.7µF ceramic capacitor to the power ground.

The SW pin is the switching node of the power converter. Connect one terminal of the inductor to the SW pin and the other to power input.

The exposed pad (available only in the 8 Ld DFN package) must be connected to PGND pin for proper electrical performance. Place as many vias as possible under the pad connecting to the system GND plane for optimal thermal performance.

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ISL9113

Ordering Information

PART NUMBER

( Notes 1

ISL9113ER7Z-T (

ISL9113ERAZ-T (

ISL9113EI9Z-T (

ISL9113EIAZ-T (

ISL9113ER7Z-EVZ

ISL9113ERAZ-EVZ

,

Note 2

Note 3

Note 3

)

)

4

Note 2

)

)

)

137

13A

139

13A

PART

MARKING

V

OUT

(V)

5.0

Adjustable

5.1

Adjustable

Evaluation Board for ISL9113ER7Z

Evaluation Board for ISL9113ERAZ

TEMP RANGE

(°C)

-20 to +85

-20 to +85

-20 to +85

-20 to +85

PACKAGE

(RoHS Compliant)

8 Ld DFN

8 Ld DFN

6 Bump WLCSP

6 Bump WLCSP W3x2.6

PKG.

DWG. #

L8.2x2D

L8.2x2D

W3x2.6

ISL9113EI9Z-EVZ

ISL9113EIAZ-EVZ

Evaluation Board for ISL9113EI9Z

Evaluation Board for ISL9113EIAZ

NOTES:

1. Please refer to Tech Brief TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and

SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free

WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL9113 . For more information on MSL please see Tech Brief TB363 .

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ISL9113

Absolute Maximum Ratings

V

BAT

, EN, FAULT, V

OUT

, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

SW Voltage

DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V

Pulse < 10ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 8.0V

ESD Ratings

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV

*Other ESD Spec should meet Level 1 requirement

Latch-up (Tested per JESD78; Class 2, Level A) . . . . . . . . . . . . . . . . 100mA

Thermal Information

Thermal Resistance (Typical)

8 Ld DFN Package (

Notes 5 , 6

). . . . . . . . . .

JA

(°C/W)

80

JC

(°C/W)

15

6 Bump WLCSP ( Note 5

) . . . . . . . . . . . . . . . 116 -

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-20°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

Recommended Operating Conditions

V

BAT

(After Start-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 4.7V

V

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V

BAT

+ 0.2V) to 5.2V

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

5.

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379 .

6. For

JC the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications

V

BAT

= 3.0V, V across the operating temperature range, -20°C to +85°C.

OUT

= 5.0V, T

A

= +25°C (see

“Typical Application Circuit” on page 7

). Boldface limits apply

PARAMETER

Start-up Voltage

Input Undervoltage Lockout

Feedback Voltage

Output Voltage

Feedback Pin Input Current

Quiescent Current from V

OUT

Shutdown Current from V

BAT

Leakage Current at SW Pin

N-Channel MOSFET ON-resistance

P-Channel MOSFET ON-resistance

N-Channel MOSFET Peak Current Limit

Maximum Duty Cycle

PWM Switching Frequency

EN Logic High

EN Logic Low

Soft-Start-Up Time

SYMBOL

V

MIN

V

UVLO

V

FB

V

OUT

I

Q1

I

SD

I

PK

D

MAX

F

OSC

TEST CONDITIONS

V

EN

= 1.2V

,

R

LOAD

= 50Ω

V

EN

= V

BAT,

R

LOAD

= 50Ω, DFN versions only

ADJ version only

V

BAT

= 2.8V, ADJ version only

I

LOAD

= 50mA, 5V DFN Fixed version

I

LOAD

= 1mA or 50mA, 5.1V WLCSP

Fixed version

V

FB

= 0.8V, ADJ version only

V

BAT

= V

EN

= 1.2V, No Load (

Note 8 )

V

EN

= 0V, V

BAT

= 1.2V, V

O

= 0

V

EN

= 0V, V

BAT

= 4.7V, V

O

= 0

DFN version

WLCSP version

2.5V < V

BAT

< 4.7V

V

BAT

< 2.5V

2.5V < V

BAT

< 4.7V

V

BAT

< 2.5V

C

OUT

= 4.7μF, L = 2.2μH

MIN

(

Note 7

)

2.8

0.68

784

3.0

4.9

4.96

1.1

85

1.5

1.7

1.2

0.48*V

BAT

TYP

3.0

0.70

800

5

5.1

20

0.5

0.20

0.35

1.3

87.5

1.8

1.8

0.2

MAX

(

Note 7 )

0.76

100

45

2

1

816

5.2

5.1

5.2

1.5

2.0

2.2

0.35

0.14*V

BA

T

1

UNITS

V

V

V

V mV

V ms

MHz

MHz

V

V

V

V

A

%

Ω

Ω nA

μA

μA

μA

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ISL9113

Electrical Specifications

V

BAT

= 3.0V, V

OUT

= 5.0V, T

A

= +25°C (see “Typical Application Circuit” on page 7 ). Boldface limits apply across the operating temperature range, -20°C to +85°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

( Note 7 ) TYP

FAULT Pin Leakage Current when High

FAULT Pin Sink Current when Low

Load Regulation

Line Regulation

Output Overvoltage Protection Threshold

ΔV

OUT

/V

OUT

V

FAULT

= V

OUT

V

FAULT

= 0.5V

I

LOAD

= 0 to 100mA, DFN versions

I

LOAD

= 0 to 100mA, WLCSP versions

V

BAT

= 3.0V to 3.6V, I

LOAD

= 1mA

ADJ version only

10

-1.5

-1.0

±

1.5

Thermal Shutdown

Thermal Shutdown Hysteresis

T

SD

5.9

150

25

NOTES:

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

8. I

Q1

is measured at V

OUT

and multiplied by V

OUT

/V

BAT

; thus, the equivalent input quiescent current is calculated.

MAX

( Note 7 )

100

+1.5

+1.0

UNITS nA mA

%

V o

C o

C

%

%

Typical Application Circuit

2.2µH

V

BAT

=

0.8V TO 4.7V

4.7µF

7

V

BAT

8

SW

5

EN

V

OUT

2

FB

4

523k

100k

GND

1

V

OUT

=

5.0V/500mA

4.7µF

ISL9113ERAZ

FIGURE 3. POWER SUPPLY SOLUTION FOR V

OUT

= 5V

Detailed Description

Current Mode PWM Operation

The control scheme of the device is based on the peak current mode control and the control loop is compensated internally. The peak current of the N-channel MOSFET switch is sensed to limit the maximum current flowing through the switch and the inductor. The typical current limit is set to 1.3A.

The control circuit includes a ramp generator, slope

compensator, error amplifier and a PWM comparator (see “Block

Diagrams” on pages 2

and 3

). The ramp signal is derived from the inductor current. This ramp signal is then compared to the error amplifier output to generate the PWM gating signals for driving both N-channel and P-channel MOSFETs. The PWM operation is initialized by the clock from the internal oscillator

(typical 1.8MHz). The N-channel MOSFET is turned ON at the beginning of a PWM cycle, the P-channel MOSFET remains OFF and the current starts ramping up. When the sum of the ramp and the slope compensator output reaches the error amplifier output voltage, the PWM comparator outputs a signal to turn OFF the N-channel MOSFET. Here, both MOSFETs remain OFF during the dead-time interval. Next, the P-channel MOSFET is turned ON and remains ON until the end of this PWM cycle. During this time, the inductor current ramps down until the next clock. At this point, following a short dead time, the N-channel MOSFET is again turned ON, repeating as previously described.

Skip Mode Operation

The boost converter is capable of operating in two different modes. When the inductor current is sensed to cross zero for eight consecutive times, the converter enters skip mode. In skip mode, each pulse cycle is still synchronized by the PWM clock.

The N-channel MOSFET is turned ON at the rising edge of the clock and turned OFF when the inductor peak current reaches typically 25% of the current limit. Then, the P-channel MOSFET is turned ON, and it stays ON until its current goes to zero.

Subsequently, both N-channel and P-channel MOSFETs are turned OFF until the next clock cycle starts, at which time the

N-channel MOSFET is turned ON again. When V

OUT

is 1.5% higher than the nominal output voltage, the N-channel MOSFET is immediately turned OFF and the P-channel MOSFET is turned ON until the inductor current goes to zero. The N-channel MOSFET resumes operation when V

FB

falls back to its nominal value, repeating the previous operation. The converter returns to

1.8MHz PWM mode operation when V

FB nominal voltage.

drops 1.5% below its

Given the skip mode algorithm incorporated in the ISL9113, the average value of the output voltage is approximately 0.75% higher than the nominal output voltage under PWM operation.

This positive offset improves the load transient response when switching from skip mode to PWM mode operation. The ripple on the output voltage is typically 1.5%*V

OUT

(nominal) when input voltage is sufficiently lower than output voltage, and it increases as the input voltage approaches the output voltage.

Synchronous Rectifier

The ISL9113 integrates one N-channel MOSFET and one

P-channel MOSFET to realize a synchronous boost converter.

Because the commonly used discrete Schottky rectifier is replaced with the low r

DS(ON)

P-channel MOSFET, the power conversion efficiency reaches a value above 90%. Since a typical step-up converter has a conduction path from the input to the

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output via the body diode of the P-channel MOSFET, a special

circuit (see “Block Diagrams” on pages 2

and

3 ) is used to

reverse the polarity of the P-channel body diode when the device is shut down. Thus, this configuration completely disconnects the load from the input during shutdown of the converter. The benefit of this feature is that the battery will not be completely depleted during shutdown of the converter. No additional components are needed to disconnect the battery from the output of the converter.

Soft-Start

The soft start-up duration is the time between the device being enabled and V

OUT

rising to within 3% of target voltage. When the device is enabled, the start-up cycle starts with a linear phase.

During the linear phase, the rectifying switch is turned ON in a current limited configuration, delivering about 350mA, until the output capacitor is charged to approximately 90% of the input voltage. At this point, PWM operation begins in boost mode. If the output voltage is below 2.3V, PWM switching is done at a fixed duty-cycle of 75% until the output voltage reaches 2.3V.

When the output voltage exceeds 2.3V, the closed-loop current mode PWM loop overrides the duty cycle until the output voltage is regulated. Peak inductor current is ramped to the final value

(typically 1.3A) during the soft-start period to limit inrush current from the input source. Fault monitoring begins approximately

2ms after the device is enabled.

Over-temperature Protection (OTP)

The device offers over-temperature protection. A temperature sensor circuit is integrated and monitors the internal IC temperature. Once the temperature exceeds the preset threshold

(typically +150°C), the IC shuts down immediately. The OTP has a typical hysteresis of +25°C. When the device temperature decreases by this, the device starts operating.

Fault Monitoring and Reporting

Fault monitoring starts 2ms after start-up.

Table 1 shows the

response to different detected faults. Any fault condition shown

in Table 1 causes the FAULT pin to be taken LOW. The FAULT pin

will not release until V

BAT condition is removed.

and V

OUT

fully collapse or until the fault

Printed Circuit Board Layout

Recommendations

The ISL9113 is a high frequency switching boost converter.

Accordingly, the converter has fast voltage change and high switching current that may cause EMI and stability issues if the layout is not done properly. Therefore, careful layout is critical to minimize the trace inductance and reduce the area of the power loop.

Power components, such as input capacitor, inductor and output capacitor, should be placed close to the device. Board traces that carry high switching current should be routed wide and short. A solid power ground plane is important for EMI suppression.

The switching node (SW pin) of the converter and the traces connected to this pin are very noisy. Noise sensitive traces, such as the FB trace, should be kept away from SW node. The voltage

ISL9113 divider should be placed close to the FB pin to prevent noise pickup.

Figures 4 and 5 show the recommended PCB layout.

In the 8 Ld DFN package, the heat generated in the device is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. It is recommended to add at least 4 vias within the pad to the GND plane for the best thermal relief.

V

OUT

FIGURE 4. RECOMMENDED PCB LAYOUT (DFN VERSION)

GND

GND V

BAT

FIGURE 5. RECOMMENDED PCB LAYOUT (WLCSP VERSION)

Fixed and Adjustable Output Voltage

ISL9113 offers options for fixed output voltage of 5V, 5.1V or an adjustable output voltage.

For the fixed output voltage version (ISL9113ER7Z,

ISL9113EI9Z-T), an internal voltage divider is used (see “Block

Diagrams”, “ISL9113ER7Z” on page 2

). For the adjustable output voltage version (ISL9113ERAZ), the output voltage is programmed by connecting two external voltage divider resistors between V

OUT

FB and GND (see “Block Diagrams”, “ISL9113ERAZ” on page 3 ).

,

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ISL9113

FAULT CONDITION

Low Battery Voltage

V

OUT

out of Regulation

Short Circuit

Over-temperature Protection

TABLE 1. FAULT DETECTION AND RESPONSE

DETECTION DETAILS ACTION

V

BAT

< 0.7V

Shut down until V

EN

or V

BAT

is cycled.

V

OUT

is 10% below the target output voltage Shut down only if V

BAT

and V

OUT

fall below 2.1V. Device automatically restarts after 200ms.

FAULT signal switches ON and OFF when V

OUT out of regulation due to overload condition.

drops

V

OUT

falls below V

BAT

Die temperature is > +150°C

Shut down immediately. Device automatically restarts after 200ms.

Switching stops. Device automatically restarts when temperature decreases to +125°C.

Output Overvoltage Protection (ADJ version only) V

OUT

> 5.9V

Switching stops until EN pin is toggled or power is cycled.

Output Voltage Setting Resistor Selection

For the ISL9113 adjustable output version, resistors R

1

and R

2

,

shown in the Block Diagram “ISL9113ERAZ” on page 3

, set the desired output voltage values. The output voltage can be

calculated using Equation 1 :

V

OUT

= V

FB

1 +

R

-------

2

(EQ. 1) where V

FB

is the internal FB reference voltage (0.8V typical). The current flowing through the divider resistors is calculated as

V

OUT

/(R

1

+ R

2

). Large resistance is recommended to minimize current into the divider and thus improve the total efficiency of the converter. R

1

and R

2

should be placed close to the FB pin of the device to prevent noise pickup.

Inductor Selection

An inductor with core material suitable for high frequency applications (e.g., ferrite) is desirable to minimize core loss and improve efficiency. The inductor should have a low ESR to reduce copper loss. Moreover, the inductor saturation current should be higher than the maximum peak current of the device; i.e., 1.5A.

The device is designed to operate with an inductor value of 2.2µH to provide stable operation across the range of load, input and output voltages. Stable mode switching between PWM and skip mode operation is guaranteed at this inductor value.

Table 2

shows recommended inductors.

TABLE 2. INDUCTOR VENDOR INFORMATION

MANUFACTURER PART NUMBER DIMENSIONS- W x L x H (mm)

Murata

Toko

LQH32PN2R2NN0L

1239AS-H-2R2M

3.2 x 2.5 x 1.7(max)

2.5 x 2.0 x 1.2(max)

TDK

Cyntec

1286AS-H-2R2M

TFM201610A-2R2M

PSE25201B-2R2MS

2.0 x 1.6 x 1.2(max)

2.0 x 1.6 x 1.0(max)

2.0 x 1.6 x 1.2(max)

Capacitor Selection

INPUT CAPACITOR

A minimum of a 4.7µF ceramic capacitor is recommended to provide stable operation under typical operating conditions. For input voltage less than 1.0V application, an additional 4.7µF ceramic capacitor is recommended for better noise filtering and

EMI suppression. The input capacitor should be placed close to the input pin, GND pin and the non-switching terminal of the inductor.

OUTPUT CAPACITOR

For the output capacitor, a ceramic capacitor with small ESR is recommended to minimize output voltage ripple. A typical 4.7µF should be used to provide stable operation at different typical operating conditions. The output capacitor should be placed

close to the output pin and GND pin of the device. Table 3

shows the recommended capacitors.

TABLE 3. CAPACITOR VENDOR INFORMATION

MANUFACTURER SERIES WEBSITE

AVX

Murata

X5R

X5R www.avx.com

www.murata.com

Taiyo Yuden

TDK

X5R

X5R www.t-yuden.com

www.tdk.com

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ISL9113

Typical Characteristics

100

95

90

85

80

75

70

65

60

V

BAT

= 4.2V

V

BAT

= 3.0V

V

BAT

= 3.6V

V

BAT

= 1.2V

V

BAT

= 2.3V

55

V

OUT

= 5.1V

50

0.0001 0.001 0.01

LOAD CURRENT (A)

0.1

FIGURE 6. FIXED 5.1V EFFICIENCY (ISL9113EI9Z)

1

1.2

1.0

0.8

0.6

0.4

0.2

V

OUT

= 4.0V

V

OUT

= 5.0V

0

0.8 1.3 1.8 2.3 2.8

V

BAT

(V)

3.3 3.8 4.3

FIGURE 7. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE

(ISL9113ERAZ)

4.8

L = 2.2µH, C

OUT

= 4.7μF

V

IN

= 3.0V, V

OUT

= 5.0V, I

LOAD

= 20mA

5.16

5.14

5.12

5.10

5.08

5.06

5.04

I

LOAD

= 100mA (PWM)

I

LOAD

= 1mA (PFM)

5.02

0 1 2

V

BAT

(V)

3 4

FIGURE 8. LINE REGULATION, V

OUT

= 5V (ISL9113ER7Z)

5

L = 2.2µH, C

OUT

= 4.7μF

V

BAT

= 3.0V, V

OUT

= 5.0V, I

LOAD

= 250mA

V

OUT

WITH 5V OFFSET (200mV/DIV)

INDUCTOR CURRENT(500mA/DIV)

SW (5V/DIV)

TIME 10µs/DIV

FIGURE 9. PULSE SKIP MODE WAVEFORM

V

BAT

= 3.0V, V

OUT

= 5.0V, I

LOAD

= 250mA

EN

V

OUT

WITH 5.0V OFFSET (50mV/DIV)

V

OUT

(2V/DIV)

INDUCTOR CURRENT(500mA/DIV)

SW (2V/DIV)

FIGURE 10. PWM WAVEFORM

TIME 1µs/DIV

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INDUCTOR CURRENT(500mA/DIV)

SW(5V/DIV)

TIME 40ms/DIV

FIGURE 11. START-UP AFTER ENABLE (I

LOAD

= 250mA)

FN8313.3

February 23, 2015

Typical Characteristics

(Continued)

V

BAT

= 3.0V, V

OUT

= 5.0V, I

LOAD

= 50mA

EN (5V/DIV)

ISL9113

V

OUT

(100mV/DIV)

V

BAT

= 3.6V, V

OUT

= 5.0V

V

OUT

(2V/DIV)

INDUCTOR CURRENT(500mA/DIV)

SW(5V/DIV)

TIME 40ms/DIV

FIGURE 12. START-UP AFTER ENABLE (I

LOAD

= 50mA)

V

BAT

= 3.6V, V

OUT

= 5.0V

V

OUT

(200mV/DIV)

TBD

INDUCTOR CURRENT(500mA/DIV)

I

LOAD

AT 0.66Ω

(200mV/DIV)

TIME 400µs/DIV

FIGURE 14. LOAD TRANSIENT RESPONSE (20mA TO 250mA)

INDUCTOR CURRENT(500mA/DIV)

I

LOAD

AT 0.66Ω

(200mV/DIV)

TIME 400µs/DIV

FIGURE 13. LOAD TRANSIENT RESPONSE (100mA TO 500mA)

5.20

5.15

5.10

5.05

4.2V

3.0V

3.6V

5.00

0 0.2 0.4 0.6 0.8

I

LOAD

(A)

FIGURE 15. LOAD REGULATION (ISL9113ER7Z)

1.0

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ISL9113

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision.

DATE REVISION CHANGE

February 23, 2015 FN8313.3 Updated Datasheet with Intersil new standards.

On page 6, under the“Absolute Maximum Ratings” section added “FB” to the first line.

Replaced Figure 9 on page 10.

Updated the About Intersil verbiage.

February 18, 2013 FN8313.2 Page 1:

Added 5.1V or Adjustable Output options to “Features”

Removed "Coming Soon" from WLCSP package references

Updated Figure 2. Changed y axis scale

Page 5:

Added information for WLCSP package option.

Page 6:

Removed Machine Model from “ESD Ratings”.

Added “Thermal Information” for WLCSP.

“Electrical Specifications” on page 6:

“Input Undervoltage Lockout”, aded "DFN versions only" to test conditions.

Changed parameter name from “Output Voltage Accuracy” to “Output Voltage”. Added "5V DFN Fixed version" to test

conditions where I

LOAD

= 50mA. Changed MIN/MAX from -100/+100 mV to 4.9/5.1 V. Added TYP. Added lines for ADJ version only and WLCSP Fixed version.

Added "ADJ version only" to test conditions for “Feedback Voltage”.

Added test conditions for “Feedback Pin Input Current”.

Added WLCSP specs for “PWM Switching Frequency”.

“Electrical Specifications” on page 7:

Added "DFN versions" to test conditions for “Load Regulation” where I

LOAD versions.

= 0 to 100mA. Added line for WLCSP

Added test conditions for “Output Overvoltage Protection Threshold”.

Page 8:

Added Figure 5 “RECOMMENDED PCB LAYOUT (WLCSP VERSION)”.

Changed “Fixed and Adjustable Output Voltage” from:

“ISL9113 offers options for fixed output voltage of 5V or an adjustable output voltage. For fixed output voltage version

(ISL9113ER7Z)..” to:

“ISL9113 offers options for fixed output voltage of 5V, 5.1V, or an adjustable output voltage. For fixed output voltage version (ISL9113ER7Z, ISL9113EI9Z-T)..”

Revised Table 2. Added dimensions. Revised Manufacturers and Part Numbers.

Added new efficiency plot, Figure 6.

Added “W3x2.6” on page 15.

January 16, 2013 FN8313.1 Updated Related Literature on page 1.

Changed ESD Ratings in “Absolute Maximum Ratings” on page 6 as follows:

HBM from 2.5kV to 3kV

MM from 250V to 300V

July 12, 2012 FN8313.0 Initial Release.

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ISL9113

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com

.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask .

Reliability reports are also available from our website at www.intersil.com/support

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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FN8313.3

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ISL9113

Package Outline Drawing

L8.2x2D

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD

Rev 0, 3/11

2.00

A

6

PIN 1

INDEX AREA

B

8

6x 0.50

(4X) 0.15

TOP VIEW

0.10M

C A B 0.22

4

0.90±0.10

0±0.10

0±0.10

BOTTOM VIEW

6

PIN #1

INDEX AREA

1

1.55±0.10

( 8x0.30 )

0.90±0.10

SIDE VIEW

SEE DETAIL "X"

0.10

C

C

BASE PLANE

SEATING PLANE

0.08

C

PACKAGE

OUTLINE

( 6x0.50 )

( 8x0.20 )

( 8x0.30 )

1.55

2.00

( 8x0.22 )

0.90

2.00

TYPICAL RECOMMENDED LAND PATTERN

C 0 . 2 REF

0 . 00 MIN.

0 . 05 MAX.

DETAIL "X"

NOTES:

1.

2.

3.

Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance: Decimal ± 0.05

4.

Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

5.

Tiebar shown (if present) is a non-functional feature.

6.

The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

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FN8313.3

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ISL9113

Package Outline Drawing

W3x2.6

3X2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLSCP 0.4MM PITCH)

Rev 3, 1/13

1.360±0.03

X

Y

0.200

0.800±0.03

(4X) 0.10

PIN 1

(A1 CORNER)

TOP VIEW

0.400

0.280

0.800

2

C B A

6X 0.265±0.035

1

0.200

BOTTOM VIEW

0.240

0.290

6

NSMD

TYPICAL RECOMMENDED LAND PATTERN

0.400

PACKAGE

OUTLINE

SEATING PLANE

3

0.05 Z

2

0.265±0.035

4

0.10

0.05

Z X Y

Z

0.200±0.030

0.500±0.050

SIDE VIEW

NOTES:

1. Dimensions and tolerance per ASME Y 14.5M - 1994.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z .

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.

4. Bump position designation per JESD 95-1, SPP-010.

5. All dimensions are in millimeters.

6. NSMD refers to non-solder mask defined pad design per Intersil

Tech Brief www.intersil.com/data/tb/tb451.pdf

7. Ball height and post saw device size can vary by ±10µm depending on final selection of assembly vendor.

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15

FN8313.3

February 23, 2015

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Intersil

:

ISL9113ERAZ-T ISL9113EIAZ-T ISL9113EI9Z-T ISL9113ER7Z-T

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