ML620Q131/2/3/4/5/6 GENERAL DESCRIPTION

ML620Q131/2/3/4/5/6 GENERAL DESCRIPTION
FEDL620Q130-01
Issue Date: Nov 12, 2015
ML620Q131/2/3/4/5/6
16-bit micro controller
GENERAL DESCRIPTION
This LSI is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with rich
peripheral functions such as the timer, PWM, comparator, voltage level supervisor, UART, I2C, and successive approximation
type A/D converter.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipeline architecture
parallel processing. It has the data flash memory area which can be written by software.
In addition, the on-chip debug function that is installed enables software debugging and programming.
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system: 16-bit length instruction
‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒ On-chip debug function built in
‒ Minimum instruction execution time
30.5 μs (at 32.768 KHz system clock)
0.063 μs (at 16 MHz system clock)
• Internal memory
‒ Flash memory (program area)
Rewrite count 100 cycles
ML620Q131: 8 Kbyte (4K x 16 bits)
ML620Q132: 16 Kbyte (8K x 16 bits)
ML620Q133: 24 Kbyte (12K x 16 bits)
ML620Q134: 8 Kbyte (4K x 16 bits)
ML620Q135: 16 Kbyte (8K x 16 bits)
ML620Q136: 24 Kbyte (12K x 16 bits)
‒ Flash memory (data area)
Rewrite count 10,000 cycles
2 Kbyte (1K x 16 bits)
‒ SRAM
2 Kbyte (2K x 8 bits)
• Interrupt controller
− Non-maskable interrupt source: 2 (Internal sources: BACK-UP CLOCK, WDT)
− Maskable interrupt sources: 30 (Internal sources: 25, External sources: 5)
− Four interrupt levels and masking function
• Time base counter
− Low-speed time base counter × 1 channel
• Watchdog timer
‒ Non-maskable interrupt and reset
(The first overflow generates an interrupt, and the second overflow generates a reset)
‒ Free running
‒ Overflow period: 4 types selectable (125 ms, 500 ms, 2 s, and 8 s at 32.768 kHz)
1/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
• Timers
‒ 8 bits x 10 ch (16-bit configuration available)
‒ Continuous timer mode/one-shot timer mode
‒ Timer start/stop function by software/external trigger input
• PWM
‒ Resolution 16 bits x 1 ch
‒ Continuous PWM mode/one-shot PWM mode
‒ PWM start/stop function by software/external trigger input
• Synchronous serial port
‒ Master/slave selectable
‒ LSB first/MSB first selectable
‒ 8-bit length/16-bit length selectable
‒ Operation in the SPI mode 0/3
‒ Overflow detection function
• UART
‒ Full-duplex communication x 1 ch
‒ Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
‒ Positive logic/negative logic selectable
‒ Internal baud rate generator
• I2C bus interface
‒ Master x 1ch
Standard mode (100 kbit/s) and fast mode (400 kbit/s) are supported
‒ Slave x 1ch
Standard mode (100 kbit/s) and fast mode (400 kbit/s) are supported
• Successive approximation type A/D converter
‒ 10-bit A/D converter
‒ ML620Q131/ ML620Q132/ ML620Q133 : Input 6 ch
‒ ML620Q134/ ML620Q135/ML620Q136 : Input 8 ch
• Analog Comparator
‒ Operation voltage range: VDD = 1.8 to 5.5 V
‒ Hysteresis width (only comparator 0): 20 mV (Typ.)
‒ Interrupts allow edge selection and sampling selection
• DUTY measurement circuit
‒ DUTY ratio measurement by inputting PWM signals with frequencies from 2 KHz to 64 KHz
‒ DUTY measurement interrupt: 4 types selectable (64 µs, 0.51 ms, 1.09 ms, 2.18 ms)
• General-purpose ports (including secondary functions)
‒ Input-only port
1 ch (including secondary functions, also used by the on-chip debug pin)
‒ I/O port
ML620Q131/ML620Q132/ML620Q133: 10 ch (including secondary functions)
ML620Q134/ML620Q135/ML620Q136: 14 ch (including secondary functions)
2/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
• Reset
‒ RESET_N pin reset
‒ Reset by power-on detection
‒ Reset by the watchdog timer (WDT) overflow
‒ Reset by RAM parity error (enable/disable can be selected)
‒ Reset by voltage level detection 0 (VLS0) (enable/disable can be selected)
‒ Reset by voltage level detection 1 (VLS1) (enable/disable can be selected)
‒ Reset by prohibition program address change
• Voltage level detect function
‒ 2 ch
‒ Threshold voltage: 12 values selectable
‒ Interrupt generation or reset generation can be selected
• Clock
‒ Low-speed clock
Internal low-speed RC oscillation (32.768 KHz)
‒ High-speed clock
PLL oscillation @ internal high-speed RC oscillation (32 MHz*1)
High-speed crystal oscillation (4 MHz)
PLL oscillation @ high-speed crystal oscillation (32 MHz*1*2)
‒ Selection of high-speed clock mode by software
PLL oscillation @ internal high-speed RC oscillation mode (16 MHz)
High-speed crystal oscillation mode (4 MHz)
PLL oscillation @ high-speed crystal oscillation mode (16 MHz)
*1
) 32 MHz can be used only as the PWMC clock.
The maximum frequency of the system clock is 16 MHz.
*2) To use the high-speed crystal oscillation and PLL oscillation @ high-speed crystal oscillation, be sure to connect the
high-speed crystal (4 MHz).
• Power management
‒ HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states)
‒ STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
‒ Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, or 1/16 of the
oscillation clock)
‒ Block Control Function: Powers down (reset registers and stop clock supply) the circuits of unused function blocks
3/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
• Shipment
‒ 16-pin plastic SSOP
ML620Q131-xxxMB
ML620Q132-xxxMB
ML620Q133-xxxMB
xxx: ROM code number
(Works: ML620Q131-NNNMB)
(Works: ML620Q132-NNNMB)
(Works: ML620Q133-NNNMB)
‒ 16-pin WQFN
ML620Q131-xxxGD
ML620Q132-xxxGD
ML620Q133-xxxGD
xxx: ROM code number
(Works: ML620Q131-NNNGD)
(Works: ML620Q132-NNNGD)
(Works: ML620Q133-NNNGD)
‒ 20-pin plastic TSSOP
ML620Q134-xxxTD
ML620Q135-xxxTD
ML620Q136-xxxTD
xxx: ROM code number
(Works: ML620Q134-NNNTD)
(Works: ML620Q135-NNNTD)
(Works: ML620Q136-NNNTD)
• Guaranteed operating range
‒ Operating temperature: -40 to 105 °C
‒ Operating voltage: VDD = 1.6 to 5.5 V
The difference of ML620Q130 series is shown below.
Feature
ML620Q131
ML620Q133
ML620Q134
16-pin SSOP/
16-pin WQFN
Shipment
FLASH capacity
(Program area)
Number of input channels
for successive
approximation type A/D
converter
Number of input-only
ports
Number of I/O ports
ML620Q132
8 KB
16 KB
ML620Q135
ML620Q136
20-pin TSSOP
24 KB
8 KB
16 KB
24 KB
6 ch
8 ch
1
(also used by the on-chip debug pin)
10
1
(also used by the on-chip debug pin)
14
4/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
BLOCK DIAGRAM
ML620Q131/ML620Q132/ML620Q133 Block Diagram
“*” indicates the secondary, tertiary or quarternary function.
CPU (nX-U16/100)
EPSW1~3
GREG
0~15
PSW
Timing
Controller
ELR1~3
ECSR1~3
LR
DSR/CSR
EA
PC
Program
Memory
(FLASH)
8/16/24Kbyte
ALU
SP
Instruction
Decoder
On-Chip
ICE
Instruction
Register
BUS
Controller
Data-bus
VDD
INT
VSS
1
VDDL
RAM
2Kbyte
Power
INT
2
RESET N
TEST0
TEST1_N
Interrupt
Controller
RESET &
TEST
INT
OSC0*
OSC1*
SSIOx1
OSC
1
INT
1
UART
INT
2
I2C
Master/Slave
WDT
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
RXD1*
TXD1*
SDA0*
SCL0*
INT
10
INT
3
LSCLK*
OUTCLK*
INT
1
AIN0 to AIN5*
CMP1P*
Analog
Comparator
×2
2
INT
INT
2
1
VLS
SA-ADC
INT
CMP0P*
CMP0M*
8bit Timer
×10
TBC
PWM
PWMC*
GPIO
PA0 to PA2
PB0 to PB7
INT
1
DME
INT
5
Figure 1-1 ML620Q131/ML620Q132/ML620Q133 Block Diagram
5/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
ML620Q134/ML620Q135/ML620Q136 Block Diagram
“*” indicates the secondary, tertiary or quarternary function.
CPU (nX-U16/100)
EPSW1~3
GREG
0~15
PSW
Timing
Controller
ELR1~3
ECSR1~3
LR
DSR/CSR
EA
PC
Program
Memory
(FLASH)
8/16/24Kbyte
ALU
SP
Instruction
Decoder
On-Chip
ICE
Instruction
Register
BUS
Controller
Data-bus
VDD
VSS
INT
1
SSIOx1
RAM
2Kbyte
VDDL
Power
INT
2
RESET N
TEST0
TEST1_N
Interrupt
Controller
RESET &
TEST
INT
OSC0*
OSC1*
OSC
1
INT
1
UART
INT
2
I2C
Master/Slave
WDT
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
RXD1*
TXD1*
SDA0*
SCL0*
INT
10
INT
3
LSCLK*
OUTCLK*
INT
1
AIN0 to AIN7*
CMP1P*
Analog
Comparator
×2
2
TBC
INT
INT
2
1
VLS
SA-ADC
INT
CMP0P*
CMP0M*
8bit Timer
×10
PWM
PWMC*
GPIO
PA0 to PA6
PB0 to PB7
INT
1
DME
INT
5
Figure 1-2 ML620Q134/ML620Q135/ML620Q136 Block Diagram
6/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
PIN CONFIGURATION
Pin Layout of ML620Q131/ML620Q132/ML620Q133 16pin SSOP Package
PB2 /
OSC0 / CMP0POUT
1
16
PA0 / LED0 / EXI0 / AIN0 / RXD1 /
PWMC / OUTCLK / SDA
PB3 /
OSC1 / CMP0NOUT
2
15
PB7 / LED1 / AIN5 /
TXD1 / SCL / PWMC/DUTI
PB0 / EXI4 / AIN2 / RXD0 /
PWMC / SCL / CMP1OUT/DUTI
3
14
VDD
PB1 / EXI5 / AIN3 /
TXD1 / TXD0 / CMP0OUT
4
13
VSS
RESET_N
5
12
VDDL
TEST1_N
6
11
PB5 / RXD0 / CMP0M
OUTCLK / TMJOUT / SCK0
PA2 / EXI2 / TEST0
7
10
PB4 / CMP0P /
TXD1 / TXD0 / SIN0
8
9
PA1 / EXI1 / AIN1 / CMP1P /
LSCLK / SOUT0
PB6 / AIN4 / RXD1
LSCLK / TMFOUT / SDA
Figure 2 Pin Layout of ML620Q131/ML620Q132/ML620Q133 16pin SSOP Package
7/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
VDD
VSS
VDDL
PB5 / RXD0 / CMP0M /
OUTCLK / TMJOUT / SCK0
12
11
10
9
Pin Layout of ML620Q131/ML620Q132/ML620Q133 16pin WQFN Package
PA2 / EXI2 / TEST0
PB2 / 16
OSC0 / CMP0POUT
5
PB6 / AIN4 / RXD1
LSCLK / TMFOUT / SDA
4
6
TEST1_N
PB3 / 15
OSC1 / CMP0NOUT
3
PB4 / CMP0P /
TXD1 / TXD0 / SIN0
RESET_N
7
2
PB7 / LED1 / AIN5 /
14
TXD1 / SCL / PWMC / DUTI
PB1 / EXI5 / AIN3 /
TXD1 / TXD0 / CMP0OUT
PA1 / EXI1 / AIN1 / CMP1P /
LSCLK / SOUT0
1
8
PB0 / EXI4 / AIN2 / RXD0 /
PWMC / SCL / CMP1OUT/DUTI
PA0 / LED0 / EXI0 / AIN0 / RXD1 /
13
PWMC / OUTCLK / SDA
Figure 3 Pin Layout of ML620Q131/ML620Q132/ML620Q133 16pin WQFN Package
8/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Pin Layout of ML620Q134/ML620Q135/ML620Q136 20pin TSSOP Package
PB2 /
OSC0 / CMP0POUT
1
20
PA0 / LED0 / EXI0 / AIN0 / RXD1 /
PWMC / OUTCLK / SDA
PB3 /
OSC1 / CMP0NOUT
2
19
PB7 / LED1 / AIN5 /
TXD1 / SCL / PWMC/DUTI
PB0 / EXI4 / AIN2 / RXD0 /
PWMC / SCL / CMP1OUT / DUTI
3
18
VDD
PB1 / EXI5 / AIN3 /
TXD1 / TXD0 / CMP0OUT
4
17
VSS
PA3 / AIN6 /
SDA
5
16
VDDL
PA5 /
SCK0 / SCL
6
15
PA4 / AIN7 /
SIN0
RESET_N
7
14
PA6 /
SOUT0
TEST1_N
8
13
PB5 / RXD0 / CMP0M
OUTCLK / TMJOUT / SCK0
PA2 / EXI2 / TEST0
9
12
PB4 / CMP0P /
TXD1 / TXD0 / SIN0
PB6 / AIN4 / RXD1
LSCLK / TMFOUT / SDA
10
11
PA1 / EXI1 / AIN1 / CMP1P /
LSCLK / SOUT0
Figure 4 Pin Layout of ML620Q134/ML620Q135/ML620Q136 20pin TSSOP Package
9/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
PIN LIST
Table 1 Pin List
PAD
PAD
PAD
No.
No.
No.
(16pin
(16pin
(20pin
SSOP)
WQFN)
TSSOP)
Primary function
Secondary function
Pin name
I/O
Feature
VDD
I/O
power supply pin
Tertiary function
Quartic function
Pin name
I/O
Feature
Pin name
I/O
Feature
Pin name
I/O
Feature













































SDA
I/O
data
Positive
14
12
18
input/output
Power supply pin
12
10
16
VDDL
I/O
for internal logic
(Internal
generation)
Negative
13
11
17
Vss
I/O
power supply pin
input/output
5
6
3
4
7
8
RESET_N
TEST1_N
I
I
Reset input pin
Input pin for
testing
I/O port/
16
13
20
PA0/
LED drive
LED0/
External interrupt
EXI0/
I/O
0/
AIN0/
AD input 0/
RXD1
UART1
High-spe
PWMC
O
PWMC output
OUTCLK
O
ed
clock
2
IC
I/O
output
reception
I/O port/
External interrupt
PA1/
9
8
11
EXI1/
AIN1/
Low-spe
1/
I/O
AD input 1/



LSCLK
O
Comparator 1
CMP1P
ed
clock
SSIO
SOUT0
O















O
CMP1 output
O
CMP0 output
data output
output
Non-inverting
input
input port/
PA2/
7
6
9
EXI2/
External interrupt
I
TEST0
2/









SDA
I/O
data
Input pin for
testing
—
—
—
—
5
15
PA3/
AIN6
PA4/
AIN7
I/O
I/O
I/O port/
AD input 6
I/O port/
AD input 7
2
IC
I/O
SIN0
I
SSIO
data input



2
—
—
—
—
6
14
PA5
PA6
I/O
I/O
I/O port
I/O port
SCK0
SOUT0
I/O
O
SSIO
clock I/O
SSIO
data output
IC
SCL
I/O
clock
I/O



I/O port/
External interrupt
PB0/
4/
EXI4/
3
1
3
AIN2/
I/O
RXD0/
AD input 2/
UART0
PWMC
O
PWMC
output
I2C
SCL
I/O
I/O
reception/
DUTI
clock
CMP1
OUT
DUTY
measurement
I/O port/
PB1/
4
2
4
EXI5/
I/O
AIN3
External interrupt
5/
TXD1
O
UART1
transmission
UART0
TXD0
O
sion
AD input 3
1
16
1
PB2
I/O
I/O port
OSC0
I
2
15
2
PB3
I/O
I/O port
OSC1
O
High-speed
oscillation
High-speed
oscillation
transmis
CMP0
OUT



CMP0POUT
O
CMP0P output



CMP0NOUT
O
CMP0N output
10/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
PAD
PAD
PAD
No.
No.
No.
(16pin
(16pin
(20pin
SSOP)
WQFN)
TSSOP)
Primary function
Pin name
I/O
Secondary function
Feature
Pin name
I/O
TXD1
O
Feature
Tertiary function
Pin name
I/O
Feature
TXD0
O
transmis
I/O port/
10
7
12
PB4/
CMP0P
I/O
Comparator 0
Non-inverting
UART1
transmission
Quartic function
Pin name
I/O
SIN0
I
SCK0
I/O
SDA
I/O
UART0
sion
input
Feature
SSIO
data input
I/O port/
PB5/
11
9
13
RXD0/
UART0
I/O
CMP0M
reception/
High-speed
OUTCLK
O
Comparator 0
clock
output
TMJ
OUT
O
Timer J
output
SSIO
clock I/O
Inverting input
I/O port/
PB6/
8
5
10
AIN4/
I/O
RXD1
15
14
19
AIN5/
DUTI
UART1
Low-speed
LSCLK
O
clock
output
reception
TMF
OUT
O
Timer F
output
I2C
data
I/O
I/O port/
PB7/
LED1/
AD input 4/
LED drive
I/O
AD input 5/
DUTY
TXD1
O
UART1
transmission
I2C
SCL
I/O
clock
PWMC
O
PWMC output
I/O
measurement
11/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
PIN DESCRIPTION
Table 2 Pin Description (1/4)
Primary/
Pin name
I/O
Description
Secondary/
Tertiary/
Logic
Quartic
System
RESET_N
I
Reset input pin. When this pin is set to a "L" level, system reset mode is set and
the internal section is initialized. When this pin is set to a "H" level
subsequently, program execution starts.
—
Negative
The RESET_N pin does not have an internal pull-up resistor.
OSC0
I
Crystal connection pin for the high-speed clock.
Secondary
—
OSC1
O
A crystal oscillator is connected to this pin (4 MHz max.), and capacitors CDH
and CGH (see measurement circuit 1) are connected between this pin and VSS. Secondary
This pin is used as the secondary function of the PB2 and PB3 pins.
—
LSCLK
O
Low-speed clock output. This pin is used as the tertiary function of the PA1 pin Secondary/
or the secondary function of the PB6 pin.
Tertiary
—
OUTCLK
O
High-speed clock output pin. This pin is used as the tertiary function of the PA0
pin or the secondary function of the PB5 pin.
Tertiary
—
—
Positive
—
Positive
—
Positive
General-purpose input port
PA2
I
General-purpose input port.
General-purpose input/output port
PA0 to PA1
I/O General-purpose input/output port.
PB0∼PB7
PA3 to PA6
This cannot be used as the general input/output port when used as the
secondary to quartic functions.
I/O General-purpose input/output port.
This cannot be used as the general input/output port when used as the
secondary to quartic functions.
Not available in ML620Q131/ML620Q132/ML620Q133.
Serial (UART)
TXD0
O
UART0 transmit pin. This pin is used as the tertiary function of the PB1 and
PB4 pins.
Tertiary
Positive
TXD1
O
UART1 transmit pin. This pin is used as the secondary function of the PB1,
PB4, and PB7 pins.
Secondary
Positive
RXD0
I
UART0 receive pin. This pin is used as the primary function of the PB0 and
PB5 pins.
Primary
Positive
RXD1
I
UART1 receive pin. This pin is used as the primary function of the PA0 and
PB6 pins.
Primary
Positive
2
I C Bus Interface
SDA
2
I/O NMOS open drain pin for I C data input/output.
This pin is used as the quartic function of the PA0 pin, the tertiary function of
the PA3 pin, or the quartic function of the PB6 pin. A pull-up resistor is
connected externally.
SCL
Tertiary/
Quartic
Positive
2
I/O NMOS open drain pin for I C clock input/output.
This pin is used as the tertiary function of the PA5 pin, the tertiary function of
the PB0 pin, or the tertiary function of the PB7 pin. A pull-up resistor is
connected externally.
Tertiary
Positive
12/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Table 2 Pin Description (2/4)
Primary/
Pin name
I/O
Description
Secondary/
Tertiary/
Logic
Quartic
Synchronous serial (SSIO)
SIN
I
Synchronous serial data input pin.
This pin is used as the secondary function of the PA4 pin or the quartic function
of the PB4 pin.
SCK0
I/O High-speed clock input pin.
This pin is used as the secondary function of the PA5 pin or the quartic function
of the PB5 pin.
SOUT0
O
High-speed clock output pin.
This pin is used as the quartic function of the PA1 pin or the secondary function
of the PA6 pin.
Secondary/
Quartic
Secondary/
Quartic
Secondary/
Quartic
Positive
—
Positive
PWM
PWMC
O
PWMC output pin.
Secondary/
Positive/
This pin is used as the secondary function of the PA0 and PB0 pins or the
quartic function of the PB7 pin.
Quartic
negative
External maskable interrupt input pins. Interrupt enable and edge selection
can be performed for each bit by software. This pin is used as the primary
function of the PA0 to PA2 pins.
Primary
Positive/
External maskable interrupt input pins. Interrupt enable and edge selection
can be performed for each bit by software. This pin is used as the primary
function of the PB0 and PB1 pins.
Primary
External trigger input pin of the timer 0, timer 1, timer E, timer F, timer G, timer
H, timer I, timer J, timer K, or timer L.
Primary
External interrupt
EXI0 to 2
EXI4,5
I
I
negative
Positive/
negative
Timer
TnTG
I
—
This pin is used as the primary function of the PA0 to PA2 and PB0 to PB7
pins.
TMJOUT
O
Timer J output pin. This pin is used as the tertiary function of PB5.
Tertiary
Positive
TMFOUT
O
Timer F output pin. This pin is used as the tertiary function of PB6.
Tertiary
Positive
O
Pins for LED driving. Allocated to the primary function of the PA0 and PB7
pins.
Primary
LED drive
LED0, 1
Positive/
negative
13/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Table 2 Pin Description (3/4)
Primary/
Pin name
I/O
Description
Secondary/
Tertiary/
Logic
Quartic
Successive approximation type A/D converter
AIN0
I
Ch0 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PA0 pin.
Primary
—
AIN1
I
Ch1 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PA1 pin.
Primary
—
AIN2
I
Ch2 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB0 pin.
Primary
—
AIN3
I
Ch3 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB1 pin.
Primary
—
AIN4
I
Ch4 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB6 pin.
Primary
—
AIN5
I
Ch5 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB7 pin.
Primary
—
AIN6
I
Ch6 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PA3 pin. Not available in
ML620Q131/ML620Q132/ML620Q133.
Primary
—
AIN7
I
Ch7 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PA4 pin. Not available in
ML620Q131/ML620Q132/ML620Q133.
Primary
—
CMP0P
I
Comparator 0 non-inverting input. This pin is used as the primary function of the
PB4 pin.
Primary
—
CMP0M
I
Comparator 0 inverting input. This pin is used as the primary function of the PB5
pin.
Primary
—
CMP0OUT
O
Comparator 0 output pin. This pin is used as the quartic function of the PB1 pin.
Quartic
—
CMP0POUT
O
Comparator 0 output pin. This pin is used as the quartic function of the PB2 pin.
Quartic
—
CMP0NOUT
O
Comparator 0 output pin. This pin is used as the quartic function of the PB3 pin.
Quartic
—
CMP1P
I
Comparator 1 non-inverting input. This pin is used as the primary function of the
PA1 pin.
Primary
—
CMP1OUT
O
Comparator 1 output pin. This pin is used as the quartic function of the PB0 pin.
Quartic
—
Primary
—
Comparator
DUTY measurement circuit
DUTI
I
PWM waveform input for the DUTY measurement circuit. This pin is used as
the primary function of the PB0 and PB7 pins.
14/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Table 2 Pin Description (4/4)
Primary/
Pin name
I/O
Description
Secondary/
Tertiary/
Logic
Quartic
For testing
TEST0
I
Input pin for testing. This pin is used as the primary function of the PA2 pin.
—
Positive
TEST1_N
I
Input pin for testing. A pull-up resistor is internally connected.
—
Negative
Power supply
VSS
—
Negative power supply pin.
—
—
VDD
—
Positive power supply pin.
—
—
VDDL
—
Power supply pin for internal logic (internally generated). Capacitor CL (see
measurement circuit 1) is connected between this pin and VSS.
—
—
15/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
TERMINATION OF UNUSED PINS
Table 3 Termination of unused pins
Pin
RESET_N
TEST1_N
PA0 to PA1
PA2/TEST0
PA3 to PA6
PB0 to PB7
Recommended pin termination
VDD
open
open
VSS
open
open
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left
open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as either inputs with
a pull-down resistor/pull-up resistor or outputs.
16/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
Symbol
Condition
Rating
Unit
Power supply voltage 1
Parameter
VDD
Ta = 25°C
−0.3 to +6.5
V
Power supply voltage 2
VDDL
Ta = 25°C
−0.3 to +2.0
V
Input voltage
Output voltage
Output current 1
(PA0 to PA1)
(PA3 to PA6)*
(PB0 to PB7)
Output current 2
(PA0)
(PB7)
VIN
Ta = 25°C
−0.3 to VDD+0.3
V
VOUT
Ta = 25°C
−0.3 to VDD+0.3
V
IOUT1
Ta = 25°C
−12 to +11
mA
−12 to +20
mA
PD
Ta = 25°C
When N-channel open drain
output mode is selected
Ta = 25°C
TSTG
―
IOUT2
Power dissipation
Storage temperature
1
W
−55 to +150
°C
* : ML620Q131/ ML620Q132/ ML620Q133 do not have the peripherals.
Recommended Operating Conditions
(VSS = 0V)
Parameter
Symbol
Condition
Range
Unit
Operating temperature
TOP
―
−40 to +105
°C
Operating voltage
VDD
Operating frequency (CPU)
fOP
fXTH
1.6 to 5.5
30k to 32.768k
30k to 16M
4.0M
V
Hz
High-speed crystal oscillation frequency
―
VDD = 1.6 to 5.5V
VDD = 1.8 to 5.5V
VDD = 1.8 to 5.5V
High-speed crystal oscillation
external capacitor
CDH
16
CGH
Use NX8045GE (NIHON
DEMPA KOGYO CORP.)
CL
―
2.2±30%
Capacitor externally connected to VDDL pin
Hz
pF
16
µF
Flash Memory Operating Conditions
Parameter
Symbol
Operating temperature
TOP
Operating voltage
VDD
CEPD
CEPP
―
Maximum rewrite count
Erase unit
―
―
Erase time
Write unit
Write time (Max.)
Data retention period
―
―
―
YDR
Condition
Data flash memory, At write/erase
Flash ROM, At write/erase
At write/erase
Data Flash
Program Flash
Chip erase
Program Flash
Block erase
Data Flash
Sector erase (Data Flash only)
Chip erase, Block erase, Sector
erase
―
1 word (2 Bytes)
―
Range
-40 to +105
0 to +40
1.6 to 5.5
10,000
100
All area
4
2
1
(VSS = 0V)
Unit
°C
V
times
―
KB
KB
KB
100
ms
1 word (2 Bytes)
40
15
―
µs
years
17/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
DC Characteristics Conditions (1/5)
Parameter
Symbol
Low-speed RC oscillator
frequency
fRCL
1
PLL oscillation frequency*
fPLL
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measur
Condition
Min.
Typ.
Max.
Unit
ing
circuit
Typ
Typ
Ta= +25°C
32.768k
Hz
-1%
+1%
Typ
Typ
Ta= -40 to 85°C
32.768k
Hz
-2.5%
+2.5%
Typ
Typ
Hz
32.768k
Ta= -40 to 105°C
+3%
-3%
Typ
Ta= -20 to 85°C,
Typ
MHz
32
+1%
VDD = 1.8 to 5.5V
-1%
Typ
Ta= -40°C to +105°C,
Typ
32
MHz
VDD = 1.8 to 5.5V
-1.5%
+1.5%
1
Low-speed RC oscillation start
TRCL
―
―
1
time*
High-speed RC oscillation start
TRCH
VDD = 1.8 to 5.5V
―
1
time*
High-speed crystal oscillation
TXTH
VDD = 1.8 to 5.5V
―
1
start time*
PLL oscillation start time
TPLL
VDD = 1.8 to 5.5V
―
Reset pulse width
PRST
―
100
Reset noise rejection pulse width
―
―
PNRST
Power On Reset rising time
TPOR
―
―
1
* : 2048 clock average. The CPU clock is max. fPLL/2.
2
* : Use 4MHz Crystal Oscillator NX8045GE (NIHON DEMPA KOGYO CORP.)
VIL1
RESET_N
―
65
µs
―
5
µs
2
20
ms
―
―
―
―
2
―
0.4
10
ms
µs
ms
VIL1
PRST
Reset pulse width (PRST)
VDD
1.8V
0V
TPOR
Power On Reset VDD Rising Time (TPOR)
18/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
DC Characteristics Conditions (2/5)
Parameter
Symbol
VLS0 threshold
voltage
VVLS0
VLS1 threshold
voltage
VVLS1
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Condition
Min.
Typ.
Max.
Unit
uring
circuit
Rise
1.64
1.67
1.70
VLS03 to 0 = 00H
Fall
1.60
1.63
1.66
Rise
1.74
1.77
1.81
VLS03 to 0 = 01H
Fall
1.70
1.73
1.77
Rise
1.84
1.88
1.91
VLS03 to 0 = 02H
Fall
1.80
1.84
1.87
Rise
1.94
1.98
2.02
VLS03 to 0 = 03H
Fall
1.90
1.94
1.98
Rise
2.05
2.09
2.13
VLS03 to 0 = 04H
Fall
2.00
2.04
2.08
Rise
2.45
2.50
2.55
VLS03 to 0 = 05H
Fall
2.40
2.45
2.50
Rise
2.56
2.61
2.66
VLS03 to 0 = 06H
Fall
2.50
2.55
2.60
Rise
2.66
2.71
2.76
VLS03 to 0 = 07H
Fall
2.60
2.65
2.70
Rise
2.76
2.81
2.87
VLS03 to 0 = 08H
Fall
2.70
2.75
2.81
V
1
Rise
2.86
2.92
2.97
VLS03 to 0 = 09H
Fall
2.80
2.86
2.91
Rise
2.96
3.02
3.08
VLS03 to 0 = 0AH
Fall
2.90
2.96
3.02
Rise
4.01
4.09
4.17
VLS03 to 0 = 0BH
Fall
3.90
3.98
4.06
VLS13 to 0 = 00H
1.60
1.63
1.66
VLS13 to 0 = 01H
1.70
1.73
1.77
VLS13 to 0 = 02H
1.80
1.84
1.87
VLS13 to 0 = 03H
1.90
1.94
1.98
VLS13 to 0 = 04H
2.00
2.04
2.08
VLS13 to 0 = 05H
2.40
2.45
2.50
VLS13 to 0 = 06H
2.50
2.55
2.60
VLS13 to 0 = 07H
2.60
2.65
2.70
VLS13 to 0 = 08H
2.70
2.75
2.81
VLS13 to 0 = 09H
2.80
2.86
2.91
VLS13 to 0 = 0AH
2.90
2.96
3.02
VLS13 to 0 = 0BH
3.90
3.98
4.06
19/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
DC Characteristics Conditions (3/5)
Parameter
Comparator0 same
phase input voltage
range
Comparator0
Hysteresis
Comparator0 input
offset
Comparator
reference voltage
3
error *
Symbol
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Condition
Min.
Typ.
Max.
Unit
uring
circuit
VCMR
VDD = 1.8 to 5.5V
0.1
―
VDD
-1.5
VHYSP
Ta = 25℃, VDD = 5.0V
VDD = 5.0V
10
5
20
20
30
35
VCMOF
Ta = 25℃, VDD = 5.0V
―
―
7
VCMREF
Ta = 25℃
VDD = 1.8 to 5.5V
VDD = 1.8 to 5.5V
-25
―
25
-50
―
50
CPU is in STOP state*1.
Low-speed oscillation is
stopped.
VDD=5.0V
Ta = -40
to +105℃
Ta = -40
to +85℃
―
1
22
―
1
9
IDD2
Internal RC Oscillating.
CPU is in HALT state
(LTBC,WBC: Operating*1).
High-speed oscillation is
stopped.
VDD=3.0V
Ta = -40
to +105℃
―
3.5
26
Supply current 3
IDD3
CPU: Running at 32kHz*1
High-speed oscillation is
stopped.
VDD=3.0V
Supply current 4
IDD4
IDD5
Supply current 1
Supply current 2
Supply current 5
IDD1
V
4
mV
µA
1
Ta = -40
to +105℃
―
13
42
CPU: Running at 16MHz PLL oscillating
mode used High-speed crystal oscillation *2
VDD=5.0V
―
4.5
5.5
CPU: Running at 16MHz PLL oscillating
mode used High-speed RC oscillation *2
VDD=5.0V
―
mA
4.5
5.5
1
* : LTBC and WDT is operating, Significant bits of BLKCON0 to BLKCON4 registers are all “1”
2
* : CPU running rate is 100%, min. instruction execution time is approx. [email protected]
3
* : Including comparator input offset voltage
20/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
DC Characteristics Conditions (4/5)
Parameter
Output voltage 1
(PA0 to PA1)
(PA3 to PA6)*
(PB0 to PB7)
Output voltage 2
(PA0)
(PB7)
Output leakage
current
(PA0 to PA1)
(PA3 to PA6)*
(PB0 to PB7)
Symbol
VOH1
VOL1
VOL2
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
VDD
IOH1 = −0.5mA
―
―
−0.5
―
―
0.5
IOL2 = +10mA
VDD ≥ 5.0V
IOL2 = +8mA
VDD ≥ 3.0V
―
―
0.5
―
―
0.5
IOL3 = +3mA
VDD ≥ 2.0V
IOL3 = +2mA
2.0V > VDD ≥ 1.8V
―
―
0.4
―
―
VDD*
0.2
IOL1 = +0.5mA
When N-channel
open drain output
mode is selected
V
IOOH
VOH = VDD
(in high-impedance state)
―
―
1
IOOL
VOL = VSS
(in high-impedance state)
−1
―
―
Input current 1
(RESET_N)
IIH1
VIH1 = VDD
―
―
1
IIL1
VIL1 = VSS
−1
―
―
Input current 2
(TEST1_N)
IIH2
VIH2 = VDD
―
―
1
−1500
2
−250
−300
30
−30
−20
250
−2
―
―
1
-1
―
―
2
3
IIL2
IIH3
IIL3
VIL2 = VSS
VIH3 = VDD (when pulled down)
Input current 3
VIL3 = VSS (when pulled up)
(PA0 to PA1)
VIH3 = VDD
(PA2/TEST0)
IIH3Z
(in high-impedance state)
(PA3 to PA6)*
VIL3 = VSS
(PB0 to PB7)
IIL3Z
(in high-impedance state)
* : ML620Q131/ ML620Q132/ ML620Q133 do not have the peripherals.
µA
4
21/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
DC Characteristics Conditions (5/5)
Parameter
Symbol
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
Input voltage 1
(RESET_N)
VIH1
―
(TEST1_N)
(PA0 to PA1)
(PA2/TEST0)
VIL1
―
(PA3 to PA6)*
(PB0 to PB7)
Input pin capacitance
(RESET_N)
f = 10kHz
(TEST1_N)
CIN
Vrms = 50mV
(PA0 to PA1)
(PA2/TEST0)
Ta = 25°C
(PA3 to PA6)*
(PB0 to PB7)
* : ML620Q131/ ML620Q132/ ML620Q133 do not have the peripherals.
0.7×
VDD
―
VDD
0
―
0.3×
VDD
―
―
10
V
5
pF
―
22/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Measuring circuit 1
CGH
PB2/OSC0
CDH
PB3/OSC1
4MHz
crystal
VDD
VDDL
A
CV
CL
VSS
CV :2.2μF
CL :2.2μF
CGH:16pF
CDH:16pF
4MHz crystal:NX8045GE
( NIHON DEMPA KOGYO CORP.)
Measuring circuit 2
(*2)
VIL
VDD VDDL
Output pins
(*1)
Input pins
VIH
V
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
23/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Measuring circuit 3
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL
A
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
Measuring circuit 4
Input pins
Output pins
(*3)
A
VDD
VDDL
VSS
*3: Measured at the specified input pins.
VIL
Input pins
(*1)
Output pins
VIH
VDD
VDDL
Waveform monitoring
Measuring circuit 5
VSS
*1: Input logic circuit to determine the specified measuring conditions.
24/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
AC Characteristics (External Interrupt)
Parameter
External interrupt disable
period
Symbol
TNUL
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
2.5 ×
Interrupt: Enabled (MIE = 1),
3.5 ×
―
µs
CPU is executing NOP instruction
LSCLK
LSCLK
PA0 to PA2, PB0 to PB1
(Rising-edge interrupt)
tNUL
PA0 to PA2, PB0 to PB1
(Falling-edge interrupt)
tNUL
PA0 to PA2, PB0 to PB1
(Both-edge interrupt)
tNUL
25/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
AC Characteristics (Synchronous Serial Port)
Parameter
SCK input cycle
(slave mode)
SCK output cycle
(master mode)
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
Symbol
SCK input pulse width
(slave mode)
tSCYC
―
1
―
tSCYC
―
―
High-speed oscillation stopped
During high-speed oscillation
tSW
―
µs
SCK
―
sec
0.4
―
―
µs
200
―
―
ns
(*1)
SCK output pulse width
SCK
―
tSW
(master mode)
×0.4
SOUT output delay time
―
―
tSD
(slave mode)
SOUT output delay time
―
―
tSD
(master mode)
SIN input setup time
―
80
tSS
(slave mode)
SIN input setup time
―
180
tSS
(Master mode)
―
80
SIN input hold time
tSH
*1: Clock period selected by S0CK3–0 of the serial port n mode register (SIO0MOD1)
(*1)
(*1)
(*1)
SCK
×0.5
SCK
×0.6
sec
―
360
ns
―
160
ns
―
―
ns
―
―
ns
―
―
ns
tSCYC
tSW
tSW
SCK0*
tSD
tSD
SOUT0
tSS
tSH
SIN0*
*: Indicates the secondary function of the corresponding port.
26/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
AC Characteristics (I2C Bus Interface: Standard Mode 100kHz)
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
fSCL

0

100
kHz
tHD:STA

4.0


µs
tLOW
tHIGH


4.7
4.0




µs
µs
tSU:STA

4.7


µs
tHD:DAT
tSU:DAT


0
0.25




µs
µs
tSU:STO

4.0


µs
tBUF

4.7


µs
AC Characteristics (I2C Bus Interface: Fast Mode 400kHz)
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.

0

400
kHz
fSCL
tHD:STA

0.6


µs
tLOW
tHIGH


1.3
0.6




µs
µs
tSU:STA

0.6


µs
tHD:DAT
tSU:DAT


0
0.1




µs
µs
tSU:STO

0.6


µs
tBUF

1.3


µs
Start
condition
Restart
condition
Stop
condition
SDA
SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
Note:
Current drive ability of PA3, PA5, PB0 and PB6 in N-ch open drain mode is lower than that of PA0 and PB7.
Therefore, the fast mode (400kbps) cannot be available when PA5 or PB0 is set as SCL function and when PA3 or PB6 is set as
SDA function.
For more details, see the characteristics of VOL1 and VOL2 in DC Characteristics Conditions (4/5).
27/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Successive Approximation Type A/D Converter
Parameter
Resolution
Symbol
n
Integral non-linearity error
INL
Differential non-linearity error
DNL
Zero-scale error
Full-scale error
Input impedance
A/D operating voltage
VOFF
FSE
RI
VDD
Conversion time
tCONV
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
―
―
―
10
bits
2.7V ≤ VDD ≤ 5.5V
−4
―
+4
2.2V ≤ VDD < 2.7V
−6
―
+6
1.8V ≤ VDD < 2.2V
−10
―
+10
2.7V ≤ VDD ≤ 5.5V
−3
―
+3
LSB
2.2V ≤ VDD < 2.7V
−5
―
+5
1.8V ≤ VDD < 2.2V
−9
―
+9
RI ≤ 5kΩ
−6
―
+6
RI ≤ 5kΩ
−6
―
+6
―
―
―
5k
Ω
―
1.8
―
5.5
V
CPU works in PLL oscillation mode
SACK bit = 0
―
13.67
―
2.7V ≤ VDD ≤ 5.5V
μs
CPU works in PLL oscillation mode
SACK bit = 1
―
41.26
―
1.8V ≤ VDD ≤ 5.5V
VDD
VDDL
2.2μF
A
-
2.2μF
RI≤5kΩ
+
Analog input
0.1μF
AIN0
to
AIN7
VSS
28/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact LAPIS SEMICONDUCTOR’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
16pin SSOP
29/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
16pin WQFN
30/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
20pin TSSOP
31/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
REVISION HISTORY
Document
No.
FEDL620Q130-01
Date
Nov 12, 2015
Page
Previous Current
Edition
Edition
–
–
Description
st
Fromal 1 Revision
32/33
FEDL620Q130-01
ML620Q131/2/3/4/5/6
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,
please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention
designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages
arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate
the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing
circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights
or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document;
therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by
third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and
power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no
responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright 2015 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
33/33
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement