ML610Q178 GENERAL DESCRIPTION

ML610Q178  GENERAL DESCRIPTION
FEDL610Q178FULL-01
Issue Date: May 18, 2012
ML610Q178
The low power micro controller corresponding to 5v for household appliances
I
GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q178 is a high-performance 8-bit CMOS microcontroller
that integrates a wide variety of peripherals such as 10-bit A/D converter, timer, PWM, synchronous serial port,
UART, I2C bus interface (master), Battery level detect circuit, LCD driver. The nX-U8/100 CPU is capable of
executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the
3-stage pipelined architecture.
In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI
mounted on the board.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 μs (at 32.768kHz system clock)
Approx 0.122 μs (at 8.192MHz system clock)@VDD = 2.2 to 5.5V
• Internal memory
− Has 128-Kbyte flash ROM(64K × 16-bit) built in. (1K byte of test domain that it cannot be used is
included)
− Has 4-Kbyte RAM (4096 × 8 bits) built in.
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 23 maskable interrupt sources (Internal source: 19, External source: 4)
• Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 6ch (16-bit configuration available)
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FEDL610Q178FULL-01
ML610Q178
• PWM
− Resolution 16 bits × 2 channel(IGBT control)
• Synchronous serial port
− 2ch
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− Half-duplex
− TXD/RXD × 2 channels
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400kbit/[email protected]), Standard mode (100kbit/[email protected])
• Successive approximation type A/D converter
− 10-bit A/D converter
− Input: 16ch (Maximum)
− Conversion time: 12.75μs per channel
• General-purpose ports ×74(Maximum)
− Non-maskable interrupt input port × 1ch
− Input-only port × 6ch
− Output-only port × 8ch (including secondary functions)
− Input/output × 27ch (including secondary functions)
− Input/output × 32ch (including LCD driver functions)
• LCD driver
− 160 dots max. (40 seg × 4 com), 1/1 to 1/4 duty
− Frame frequency selecable (approx. 64Hz, 73Hz, 85Hz, 102Hz, 32Hz, 128Hz, 171Hz, and 256Hz)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
•
Power supply voltage detect function
− Judgment voltages:
One of 4 levels
− Judgment accuracy: ±2% (Typ.)
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FEDL610Q178FULL-01
ML610Q178
• Reset
− Reset through the RESET_N pin
− Reset by the watchdog timer (WDT) overflow
• Clock
− Low-speed clock (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.7kHz)
− High-speed clock
Built-in oscillation (8.192MHz), Crystal/Ceramic oscillation (8MHz), external clock
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral
circuits are stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock
stop)
• Shipment
− 100-pin QFP (QFP100-P-1420-0.65-BK)
− ML610Q178-xxxGA (blank product: ML610Q178-NNNGA)
xxx: ROM code number
• Guaranteed operating range
− Operating temperature: −40°C to 85°C
− Operating voltage: VDD = 2.2V to 5.5V, VREF = 4.5V to 5.5V
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FEDL610Q178FULL-01
ML610Q178
BLOCK DIAGRAM
Figure 1-1 is a block diagram of the ML610Q178.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.
CPU (nX-U8/100) Large Model
EPSW1~3
GREG
0~15
PSW
Timing
Controller
On-Chip
ICE
ALU
TEST0
TEST1_N
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
VDDL
AIN0 to AIN15*3
LR
DSR/CSR
EA
PC
Instruction
Decoder
Instruction
Register
Data-bus
RESET &
TEST
RAM
4096byte
INT
1
OSC
Interrupt
Controller
INT
4
POWER
VDD
VSS
VREF
ECSR1~3
SP
VDD
VSS
RESET_N
ELR1~3
INT
6
INT
1
10bit-ADC
Program
Memory
(Flash)
128Kbyte
BUS
Controller
INT
2
INT
2
INT
1
TBC
INT
2
8bit Timer
×6
INT
5
SSIO
SCK0*1, SCK1*1
SIN0*1, SIN1*1
SOUT0*1, SOUT1*1
UART
RXD0*1, RXD1*1
TXD0*1, TXD1*1
I2C
PWM
INT
WDT
VPP
GPIO
SDA*1
SCL*1
PWM4*1
PWM5*1
PW45EV0*1
PW45EV1*1
NMI
P00 to P03
P10 to P11
P20 to P23
P30 to P33*3
P34 to P36
BLD
P40 to P43
P44 to P47*3
P50 to P53
P60 to P67*3
P90 to P93
PC0 to PC7*2
PD0 to PD7*2
PE0 to PE7*2
PF0 to PF7*2
LCD
Driver
*1 Secondary or tertiary function
*2 Select I/O port or LCD driver
*3 Select I/O port or A/D converter input
LCD
Drive Voltage
COM0 to COM3
SEG0 to SEG7
SEG8 to SEG39*2
VL1, VL2, VL3
4/28
100pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P20/LED0
P21/LED1
P22/LED2
P23/LED3
VSS
P90/LED4
P91/LED5
P92/LED6
P93/LED7
P67/AIN15
P66/AIN14
P65/AIN13
P64/AIN12
P63/AIN11
P62/AIN10
P61/AIN9
P60/AIN8
P47/AIN7
P46/AIN6
P45/AIN5
1pin
P44/AIN4
P33/AIN3
P32/AIN2
P31/AIN1
P30/AIN0
VREF
P50/SIN1
P51/SCK1
P52/SOUT1
P53/TXD1
P34/PWM4
P35/PWM5
P36/LSCLK
TEST0
TEST1_N
P10/OSC0
P11/OSC1
VSS
VDD
VDDL
XT0
XT1
VPP
VL1
VL2
VL3
COM3
COM2
COM1
COM0
81pin
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80pin
NMI
P03/INT3
P02/INT2
P01/INT1
P00/INT0
P43/TXD0
P42/RXD0
P41/SCL
P40/SDA
RESET_N
PF7/SEG39
PF6/SEG38
PF5/SEG37
PF4/SEG36
PF3/SEG35
PF2/SEG34
PF1/SEG33
PF0/SEG32
PE7/SEG31
PE6/SEG30
PE5/SEG29
PE4/SEG28
PE3/SEG27
PE2/SEG26
PE1/SEG25
PE0/SEG24
PD7/SEG23
PD6/SEG22
PD5/SEG21
PD4/SEG20
FEDL610Q178FULL-01
ML610Q178
PIN CONFIGURATION
ML610Q178 QFP package product
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
51pin
50pin
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
PC7/SEG15
PC6/SEG14
PC5/SEG13
PC4/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG9
PC0/SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
31pin
30pin
NC: No Connection
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FEDL610Q178FULL-01
ML610Q178
LIST OF PINS
Pin
No.
Primary function
Pin
name
I/O
18,85
Vss
⎯
19
VDD
⎯
20
VDDL
⎯
23
VPP
⎯
Power supply for internal logic
(internally generated)
Power supply pin for Flash ROM
24
VL1
⎯
Power supply pin for LCD bias
25
VL2
26
VL3
14
Secondary function
Description
I/O
Description
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power supply pin for LCD bias
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power supply pin for LCD bias
⎯
⎯
⎯
⎯
⎯
⎯
TEST0
I/O
Input/output pin for testing
⎯
⎯
⎯
⎯
⎯
⎯
15
TEST1_N
I/O
Input/output pin for testing
⎯
⎯
⎯
⎯
⎯
⎯
71
21
RESET_N
I
Reset input pin
⎯
⎯
⎯
⎯
⎯
⎯
XT0
I
Low-speed clock oscillation pin
⎯
⎯
⎯
⎯
⎯
⎯
22
XT1
O
⎯
⎯
⎯
⎯
⎯
⎯
6
VREF
I
⎯
⎯
⎯
⎯
⎯
⎯
80
NMI
I
⎯
⎯
⎯
⎯
⎯
⎯
76
P00/EXI0/
PW45EV0
I
⎯
⎯
⎯
⎯
⎯
⎯
77
P01/EXI1
I
⎯
⎯
⎯
⎯
⎯
⎯
78
P02/EXI2/
RXD0
I
⎯
⎯
⎯
⎯
⎯
⎯
79
P03/EXI3/
RXD1
I
Low-speed clock oscillation pin
Reference power supply pin of
Successive-approximation type
ADC
Input port,
non-maskable interrupt
Input port /
External interrupt /
PW45EV0 input
Input port /
External interrupt
Input port /
External interrupt
UART0 data input
Input port /
External interrupt /
UART1 data input
⎯
⎯
⎯
⎯
⎯
⎯
16
P10
I
Input port
OSC0
I
⎯
⎯
⎯
17
P11
I
Input port
OSC1
O
⎯
⎯
⎯
O
Output port / LED drive
LSCLK
O
⎯
⎯
⎯
O
Output port / LED drive
OUTCLK
O
⎯
⎯
⎯
O
Output port / LED drive
⎯
⎯
⎯
TM9OUT
O
Timer9 output
O
Output port / LED drive
⎯
⎯
⎯
TMBOUT
O
TimerB output
82
83
84
P20/
LED0
P21/
LED1
P22/
LED2
P23/
LED3
I/O
Negative power supply pin
⎯
Positive power supply pin
Tertiary function
Pin
name
81
Pin
name
Description
High-speed clock
oscillation pin
High-speed clock
oscillation pin
Low-speed clock
output
Low-speed clock
output
6/28
FEDL610Q178FULL-01
ML610Q178
Pin
No.
Primary function
Pin
name
I/O
Description
Input/output port
/
PW45EV1 input
/
Successive
approximation
type ADC input
Input/output port
/
Successive
approximation
type ADC input
Input/output port
/
Successive
approximation
type ADC input
Input/output port
/
Successive
approximation
type ADC input
Secondary function
Pin
name
I/O
⎯
Tertiary function
Description
Pin
name
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Fourthly function
Description
Pin
name
I/O
Description
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
P30/
PW45EV1
/AIN0
I/O
4
P31/AIN1
I/O
3
P32/AIN2
I/O
2
P33/AIN3
I/O
11
P34
I/O
Input/output port
⎯
⎯
⎯
PWM4
O
PWM4
output
⎯
⎯
⎯
12
P35
I/O
Input/output port
⎯
⎯
⎯
PWM5
O
PWM5
output
⎯
⎯
⎯
13
P36
I/O
Input/output port
LSCLK
O
⎯
⎯
⎯
⎯
⎯
⎯
72
P40
I/O
Input/output port
SDA
I/O
SIN0
I
⎯
⎯
⎯
73
P41
I/O
Input/output port
SCL
I/O
SCK0
I/O
⎯
⎯
⎯
74
P42
I/O
Input/output port
RXD0
I
SOUT0
O
SSIO0 data
input
SSIO0
synchronous
clock
input/output
SSIO0 data
output
PWM4
output
⎯
⎯
⎯
TXD1
O
UAR1
data output
75
P43
I/O
1
P44/
T0P4CK/
AIN4
I/O
100
P45/
T1P5CK/
AIN5
I/O
99
P46/
T8ACK/
AIN6
I
98
P47/
T9BCK/
AIN7
I
Input/output port
Input port /
Timer0 /
PWM4 external
clock input/
Successive
approximation
type ADC input
Input port /
Timer1 /
PWM5 external
clock input/
Successive
approximation
type ADC input
Input port /
Timer8 /
TimerA external
clock input /
Successive
approximation
type ADC input
Input port /
Timer9 /
TimerB external
clock input /
Successive
approximation
type ADC input
TXD0
O
Low-speed
clock
output
I2C data
input/output
I2C clock
input/output
UART0
data input
UART0
data output
PWM4
O
SIN0
I
SSIO0 data
input
⎯
⎯
⎯
SCK0
I/O
SSIO0
synchronous
clock
input/output
⎯
⎯
⎯
SOUT0
O
SSIO0 data
output
⎯
⎯
⎯
PWM5
O
PWM5
output
⎯
⎯
⎯
7/28
FEDL610Q178FULL-01
ML610Q178
Pin
No.
Primary function
Pin
name
I/O
7
P50
8
Secondary function
Description
Pin
name
I/O
I/O
Input/output port
⎯
P51
I/O
Input/output port
9
P52
I/O
10
P53
I/O
97
P60/
AIN8
I/O
96
P61/
AIN9
I/O
95
P62/
AIN10
I/O
94
P63/
AIN11
I/O
93
P64/
AIN12
I/O
92
P65/
AIN13
I/O
91
P66/
AIN14
I/O
90
P67/
AIN15
I/O
86
87
88
89
P90/
LED4
P91/
LED5
P92/
LED6
P93/
LED7
O
O
O
O
30
COM0
O
29
COM1
O
28
COM2
O
27
COM3
O
31
SEG0
O
32
SEG1
O
Tertiary function
Description
Pin
name
I/O
⎯
⎯
SIN1
I
⎯
⎯
⎯
SCK1
I/O
Input/output port
RXD1
I
SOUT1
O
Input/output port
TXD1
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input/output
port/
Successive
approximation
type ADC input
Input/output
port/
Successive
approximation
type ADC input
Input/output
port/
Successive
approximation
type ADC input
Input/output
port/
Successive
approximation
type ADC input
Input/output
port/
Successive
approximation
type ADC input
Input/output
port/
Successive
approximation
type ADC input
Input/output
port/
Successive
approximation
type ADC input
Input/output
port/
Successive
approximation
type ADC input
Output port /
LED drive
Output port /
LED drive
Output port /
LED drive
Output port /
LED drive
LCD common
pin
LCD common
pin
LCD common
pin
LCD common
pin
LCD segment
pin
LCD segment
pin
Fourthly function
Pin
name
I/O
Description
SSIO1 data
input
SSIO1
synchronous
clock
input/output
SSIO1 data
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TXD0
O
UAR0
data output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
UART1
data input
UART1
data input
Description
8/28
FEDL610Q178FULL-01
ML610Q178
Pin
No.
Primary function
Pin
name
I/O
33
SEG2
O
34
SEG3
O
35
SEG4
O
36
SEG5
O
37
SEG6
O
38
SEG7
O
39
PC0
I/O
40
PC1
41
Secondary function
Description
Pin
name
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Fourthly function
Description
I/O
Description
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input/output port
SEG8
O
⎯
⎯
⎯
⎯
⎯
⎯
I/O
Input/output port
SEG9
O
⎯
⎯
⎯
⎯
⎯
⎯
PC2
I/O
Input/output port
SEG10
O
⎯
⎯
⎯
⎯
⎯
⎯
42
PC3
I/O
Input/output port
SEG11
O
⎯
⎯
⎯
⎯
⎯
⎯
43
PC4
I/O
Input/output port
SEG12
O
⎯
⎯
⎯
⎯
⎯
⎯
44
PC5
I/O
Input/output port
SEG13
O
⎯
⎯
⎯
⎯
⎯
⎯
45
PC6
I/O
Input/output port
SEG14
O
⎯
⎯
⎯
⎯
⎯
⎯
46
PC7
I/O
Input/output port
SEG15
O
⎯
⎯
⎯
⎯
⎯
⎯
47
PD0
I/O
Input/output port
SEG16
O
⎯
⎯
⎯
⎯
⎯
⎯
48
PD1
I/O
Input/output port
SEG17
O
⎯
⎯
⎯
⎯
⎯
⎯
49
PD2
I/O
Input/output port
SEG18
O
⎯
⎯
⎯
⎯
⎯
⎯
50
PD3
I/O
Input/output port
SEG19
O
⎯
⎯
⎯
⎯
⎯
⎯
51
PD4
I/O
Input/output port
SEG20
O
⎯
⎯
⎯
⎯
⎯
⎯
52
PD5
I/O
Input/output port
SEG21
O
⎯
⎯
⎯
⎯
⎯
⎯
53
PD6
I/O
Input/output port
SEG22
O
⎯
⎯
⎯
⎯
⎯
⎯
54
PD7
I/O
Input/output port
SEG23
O
⎯
⎯
⎯
⎯
⎯
⎯
55
PE0
I/O
Input/output port
SEG24
O
⎯
⎯
⎯
⎯
⎯
⎯
56
PE1
I/O
Input/output port
SEG25
O
⎯
⎯
⎯
⎯
⎯
⎯
57
PE2
I/O
Input/output port
SEG26
O
⎯
⎯
⎯
⎯
⎯
⎯
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
LCD segment
pin
I/O
Tertiary function
Pin
name
Description
Pin
name
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
9/28
FEDL610Q178FULL-01
ML610Q178
Pin
No.
Primary function
Pin
name
I/O
58
PE3
59
Secondary function
Description
Pin
name
I/O
I/O
Input/output port
SEG27
O
PE4
I/O
Input/output port
SEG28
O
60
PE5
I/O
Input/output port
SEG29
O
61
PE6
I/O
Input/output port
SEG30
O
62
PE7
I/O
Input/output port
SEG31
O
63
PF0
I/O
Input/output port
SEG32
O
64
PF1
I/O
Input/output port
SEG33
O
65
PF2
I/O
Input/output port
SEG34
O
66
PF3
I/O
Input/output port
SEG35
O
67
PF4
I/O
Input/output port
SEG36
O
68
PF5
I/O
Input/output port
SEG37
O
69
PF6
I/O
Input/output port
SEG38
O
70
PF7
I/O
Input/output port
SEG39
O
Description
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
LCD
segment
pin
Tertiary function
Pin
name
I/O
⎯
Fourthly function
Description
Pin
name
I/O
Description
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10/28
FEDL610Q178FULL-01
ML610Q178
PIN DESCRIPTION
Pin name
Primary/
Secondary
Logic
Negative power supply pin
—
—
I/O
Description
Power supply
VSS
—
VDD
—
Positive power supply pin
—
—
VDDL
—
Positive power supply pin for internal logic (internally generated). Connect
capacitors (CL) (see Measuring Circuit 1) between this pin and VSS .
—
—
VPP
—
Power supply pin for programming Flash ROM.
—
—
VL1
—
Power supply pins for LCD bias (external input)
—
—
VL2
—
Power supply pins for LCD bias (external input)
—
—
VL3
—
Power supply pins for LCD bias (external input)
—
—
Test
TEST0
I/O Input/output pin for testing. Has a pull-down resistor built in.
—
Positive
TEST1_N
I/O Input/output pin for testing. Has a pull-up resistor built in.
—
Negative
—
Negative
—
—
—
—
Secondary
—
Secondary
—
System
RESET_N
I
XT0
I
XT1
O
OSC0
I
OSC1
O
LSCLK
O
OUTCLK
O
Reset input pin. When this pin is set to a “L” level, the device is placed in
system reset mode and the internal circuit is initialized. If after that this pin
is set to a “H” level, program execution starts. This pin has a pull-up
resistor built in.
Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator
(see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL
are connected across this pin and VSS as required.
External input pin for high-speed clock. This function is allocated to the
secondary function of the P10 pin.
Low-speed clock output. This function is allocated to the secondary function
Secondary
of the P20/P36 pin.
High-speed clock output. This function is allocated to the secondary
Secondary
function of the P21 pin.
—
—
General-purpose input port
P00 to P03
I
P10 to P11
I
General-purpose input ports. Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used.
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
General-output input port
P20 to P23
O
P90 to P93
O
General-purpose output ports.Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used.
General-purpose output ports.Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used.
General-purpose input/output port
P30 to P36
General-purpose input/output ports.Provided with a secondary function for
each port. Cannot be used as ports if their secondary functions are used.
P40 to P47
P50 to P53
PC0 to PC7
PD0 to PD7
PE0 to PE7
I/O
General-purpose input/output ports.Provided with a LCD segment for each
port. Cannot be used as ports if LCD segment are used.
PF0 to PF7
11/28
FEDL610Q178FULL-01
ML610Q178
Pin name
I/O
Description
Primary/
Secondary
Logic
UART
TXD0
O
UART0 data output pin. Allocated to the secondary function of the P43 pin
and the fourthly function of the P53 pin.
RXD0
I
UART0 data input pin. Allocated to the primary function of the P02 pin and
the secondary function of the P42 pin.
TXD1
O
UART1 data output pin. Allocated to the secondary function of the P53 pin
and the fourthly function of the P43 pin.
RXD1
I
UART1 data input pin. Allocated to the primary function of the P03 pin and
the secondary function of the P52 pin.
Secondary
Fourthly
Positive
Secondary Positive
Secondary
Fourthly
Positive
Secondary Positive
2
I C bus interface
2
SDA
SCL
I C data input/output pin. This pin is used as the secondary function of the
I/O P40 pin. This pin has an NMOS open drain output. When using this pin as
2
a function of the I C, externally connect a pull-up resistor.
2
I C clock output pin. This pin is used as the secondary function of the P41
I/O pin. This pin has an NMOS open drain output. When using this pin as a
2
function of the I C, externally connect a pull-up resistor.
Secondary Positive
Secondary Positive
Synchronous serial (SSIO)
SIN0
SCK0
SOUT0
SIN1
SCK1
SOUT1
Synchronous serial data input pin. Allocated to the tertiary function of the
P40 pin and P44 pin.
Synchronous serial clock input/output pin. Allocated to the tertiary function
I/O
of the P41 pin and P45 pin.
Synchronous serial data output pin. Allocated to the tertiary function of the
O
P42 pin and P46 pin.
Synchronous serial data input pin. Allocated to the tertiary function of the
I
P50 pin .
Synchronous serial clock input/output pin. Allocated to the tertiary function
I/O
of the P51 pin.
Synchronous serial data output pin. Allocated to the tertiary function of the
O
P52 pin.
I
Tertiary
Positive
Tertiary
—
Tertiary
Positive
Tertiary
Positive
Tertiary
—
Tertiary
Positive
PWM
PWM4
O
PWM4 output pin. Allocated to the tertiary function of the P34 and P43 pins.
Tertiary
Positive
PWM5
O
PWM5 output pin. Allocated to the tertiary function of the P35and P47 pins.
Tertiary
Positive
T0P4CK
I
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin.
Primary
—
T1P5CK
I
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin.
Primary
—
I
Control start /stop pin for PWM4 and PWM5. Allocated to the primary
function of the P00 pin and P30 pin.
Primary
—
NMI
I
External non-maskable interrupt input pin. The interrupt occurs on both the
rising and falling edges.
Primary
Positive/
Negative
EXI0–EXI3
I
External maskable interrupt input pins. It is possible, for each bit, to specify
whether the interrupt is enabled and select the interrupt edge by software.
Allocated to the primary function of the P00–P03 pins.
Primary
Positive/
Negative
PW45EV0
PW45EV1
External interrupt
12/28
FEDL610Q178FULL-01
ML610Q178
Pin name
I/O
Description
Primary/
Secondary
Logic
Primary
—
Primary
—
Primary
—
Primary
—
Tertiary
Positive
Tertiary
Positive
Primary
Positive/
Negative
—
—
Primary
—
Timer
T0P4CK
I
T1P5CK
I
T8ACK
I
T9BCK
I
TM9OUT
O
TMBOUT
O
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin.
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin.
External clock input pin for timer 8 and timer A. Allocated to the primary
function of the P46 pin.
External clock input pin for timer 9 and timer B. Allocated to the primary
function of the P47 pin.
Timer9 overflow output pin. Allocated to the secondary function of the P22
pin.
TimerB overflow output pin. Allocated to the secondary function of the P23
pin.
LED drive
LED0-LED7
O
Pins for LED driving. Allocated to the primary function of the P20–P23 pins
and P90–P93 pins.
Successive-approximation type A/D converter
VREF
I
AIN0–AIN15
I
Reference power supply pin for successive approximation type A/D
converter.
Analog inputs to Ch0–Ch15 of the successive-approximation type A/D
converter. Allocated to the secondary function of the P30 to P33 and P44 to
P47 and P60 to P67 pins.
LCD driver
COM0 to
COM3
O
LCD common output pins.
Primary
—
SEG0 to
SEG7
O
LCD segment output pins.
Primary
—
SEG8 to
SEG39
O
LCD segment output pins. Allocated to the secondary function of the PC0
Secondary
to PC7 and PD0 to PD7 and PE0 to PE7 and PF0 to PF7 pins.
—
13/28
FEDL610Q178FULL-01
ML610Q178
TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin
VPP
RESET_N
TEST0
TEST1_N
VREF
P00 to P03
P10 to P11
P20 to P23
P30 to P33 (AIN0 to AIN3)
P34 to P36
P40 to P43
P44 to P47 (AIN4 to AIN7)
P50 to P53
P60 to P67 (AIN8 to AIN15)
P90 to P93
COM0 to COM3
SEG0 to SEG7
PC0 to PC7 (SEG8 to15)
PD0 to PD7 (SEG16 to 23)
PE0 to PE7 (SEG24 to 31)
PF0 to PF7 (SEG32 to 39)
Recommended pin termination
open
open
open
open
Connect to VDD
Connect VDD or VSS
Connect VDD or VSS
open
open
open
open
open
open
open
open
open
open
open
open
open
open
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs
and left open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as
either inputs with a pull-down resistor/pull-up resistor or outputs.
14/28
FEDL610Q178FULL-01
ML610Q178
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta = 25°C
−0.3 to +7.0
V
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Power supply voltage 5
VDDL
VPP
VL1
VL2
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
−0.3 to +3.6
−0.3 to +9.5
−0.3 to +2.33
−0.3 to +4.66
V
V
V
V
Power supply voltage 6
VL3
Ta = 25°C
−0.3 to +7.0
V
Reference voltage
VREF
Ta = 25°C
−0.3 to VDD+0.3
V
Analog input voltage
VAI
Ta = 25°C
−0.3 to VDD+0.3
V
Input voltage
VIN
Ta = 25°C
−0.3 to VDD+0.3
V
Output voltage
VOUT
−0.3 to VDD+0.3
V
Output current 1
IOUT1
−12 to +11
mA
Output current 2
IOUT2
Ta = 25°C
Port3,4,5,6,C,D,E,F
Ta = 25°C
Port2,9 Ta = 25°C
−12 to +20
mA
Power dissipation
PD
Ta = 25°C
1
W
Storage temperature
TSTG
―
−55 to +150
°C
Recommended Operating Conditions
(VSS =
Parameter
Operating temperature
0V)
Symbol
Condition
Range
Unit
TOP
―
−40 to +85
°C
Operating voltage
VDD
―
2.2 to 5.5
V
Reference voltage
VREF
―
4.5 to VDD
V
Analog input voltage
Operating frequency (CPU)
Low-speed crystal oscillation frequency
Capacitor externally connected to VDD pin
Capacitor externally connected to VPP pin
Capacitor externally connected to Vref pin
VAI
fOP
fXTL
CV
C1
CAV
VSS to VREF
30k to 8.4M
32.768k
10±30%
1±30%
1±30%
Hz
Hz
μF
μF
μF
Low-speed crystal oscillation
external capacitor
CDL
CGL
―
―
―
―
―
―
Use 32.768KHz Crystal
Oscillator DT-26
(DAISHINKU CORP.)
fXTH
―
8M/8.192M
Hz
CDH
CGH
―
―
47±30%
47±30%
pF
CL
―
10±30%
μF
High-speed crystal/ceramic oscillation
frequency
High-speed crystal oscillation
external capacitor*
Capacitor externally connected to VDDL pin
12 to 25
12 to 25
pF
* CGH and CDH are built into, external capacity is unnecessary for CSTLS8M00G56 (made by Murata Mfg.).
15/28
FEDL610Q178FULL-01
ML610Q178
Flash Memory Operating Conditions
(VSS = 0V)
Unit
°C
Parameter
Operating temperature
Symbol
Condition
Range
TOP
At write/erase
0 to +40
VDD
At write/erase
2.7 to 5.5
*1
Operating voltage
V
VDDL
At write/erase
2.5 to 2.75
1
At write/erase
7.7 to 8.3
VPP
Maximum rewrite count
CEP
―
80
times
Data retention period
―
10
years
YDR
1
* : At the writing of a flash ROM, it is necessary to supply voltage to VDDL pin within the limits of the above-mentioned
regulation. Pulldown resistance is built in the VPP pin.
DC Characteristics (1 of 5)
Parameter
High-speed crystal oscillation
start time
Low-speed crystal oscillation
2
start time*
Symbol
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
TXTH
―
―
2
20
ms
TXTL
―
―
0.6
2
s
Low-speed RC oscillator
frequency
fLCR
Ta= -10 to 60°C
Typ
-5%
32.7k
Typ
+5%
Hz
PLL oscillation frequency
fPLL
LSCLK=32.768kHz
100 clock average
Typ
-1%
8.192
Typ
+1%
MHz
Reset pulse width
PRST
―
100
―
Reset noise rejection pulse
―
―
―
PNRST
width
1
* : Use 32.768KHz Crystal Oscillator DT-26 (Daishinku) with capacitance CGL/CDL=12pF.
1
―
0.4
μs
Reset
RESET_N
VIL1
VIL1
PRST
Reset by RESET_N pin
16/28
FEDL610Q178FULL-01
ML610Q178
DC Characteristics (2 of 5)
Parameter
BLD threshold
voltage
Symbol
VBLD
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Meas
Condition
Min.
Typ.
Max.
Unit uring
circuit
LD3 to 0 = 0H
2.35
Typ.
Typ.
LD3 to 0 = 3H
2.80
Ta = 25°C
V
1
-2%
+2%
LD3 to 0 = 9H
3.70
LD3 to 0 = FH
4.60
DC Characteristics (3 of 5)
Parameter
Symbol
Supply current 1
IDD1
Supply current 2
IDD2
Supply current 3
IDD3
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Meas
Condition
Min. Typ. Max. Unit uring
circuit
CPU: In STOP state
-40 to +35℃
―
0.7
6
Low-speed/high-speed
oscillation: Stopped
―
-40 to +85℃
0.7
22
VDD=3.0V
CPU: In HALT state
-40 to +35℃
―
2.0
7
*2
(LTBC,WBC: Operating )
μA
High-speed oscillation: Stopped
―
-40 to +85℃
2.0
24
1
VDD=3.0V
1
CPU: Running at 32kHz*
-40 to +35℃
―
13
20
High-speed oscillation: Stopped
VDD=3.0V
-40 to +85℃
―
13
42
CPU: Running at 8.192MHz
2
Crystal/ceramic oscillating mode*
VDD = SPVDD = 5.0V
1
* : Case when the CPU operating rate is 100% (with no HALT state)
2
* : Significant bits of BLKCON0 to BLKCON4 registers are all “1”.
Supply current 4
IDD4
―
5
8
mA
17/28
FEDL610Q178FULL-01
ML610Q178
DC Characteristics (4 of 5)
Parameter
Output voltage 1
(P20 to P23)
(P30 to P36)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
Output voltage 2
(P20–P23)
(P90-P93)
Output voltage 3
(P40–P41)
Output leakage
current
(P20 to P23)
(P30 to P36)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
Symbol
VOH1
IOH1 = −0.5mA
VDD
−0.5
―
―
VOL1
IOL1 = +0.5mA
―
―
0.5
IOL2 = +10mA
VDD ≥ 4.5V
―
―
0.5
IOL3 = +3mA
―
―
0.4
―
―
1
VOL2
When LED drive
mode is selected
VOL3
When I C mode is
selected
IOOH
VOH = VDD
(in high-impedance state)
VOL = VSS
(in high-impedance state)
−1
―
―
VL3=3V、VOL=0.3V
15
40
―
VL3=5V、VOL=0.5V
100
200
―
VL3=3V、VOH=2.7V
―
-30
-15
VL3=5V、VOH=4.5V
―
-90
-45
VL3=3V、VOL=0.3V
15
30
―
VL3=5V、VOL=0.5V
70
150
―
VL3=3V、VOH=2.7V
―
-13
-6
VL3=5V、VOH=4.5V
―
-40
-20
IIH1
VIH1 = VDD
0
―
1
IIL1
VIL1 = VSS
−1500
−300
−20
IIH2
VIH2 = VDD (when pulled down)
2
30
250
IIL2
VIL2 = VSS (when pulled up)
−250
−30
−2
IIH2Z
VIH2 = VDD
(in high-impedance state)
―
―
1
IIL2Z
VIL2 = VSS
(in high-impedance state)
-1
―
―
IIH3
VIH3 = VDD
20
300
1500
IIL3
VIL3 = VSS
-1
―
―
IOOL
Output current 1
COM0 to COM3
IOH1
IOL2
Output current 2
SEG0 to SEG39
IOH2
Input current 3
(TEST0)
V
2
μA
3
μA
3
μA
4
2
IOL1
Input current 1
(RESET_N)
(TEST1_N)
Input current 2
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P36)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
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DC Characteristics (5 of 5)
Parameter
Input voltage 1
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P36)
(P40 to P43)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
Input pin capacitance
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P36)
(P40 to P43)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
Symbol
VIH1
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
―
0.7×
VDD
―
VDD
VIL1
―
0
―
0.3×
VDD
CIN
f = 10kHz
Vrms = 50mV
Ta = 25°C
―
―
10
V
5
pF
―
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Measuring Circuits
Measuring circuit 1
CGL
XT0
CDL
32.768kHz
crystal
CGH
V
Cc
V
Cb
XT1
OSC0
Ca
V
CDH
OSC1
VDD VREF
8MHz
crystal
VDDL
VSS
A
CV
CV
:10μF
:10μF
CL
CGL
:12pF
:12pF
CDL
CGH
:47pF
:47pF
CDH
CL1,C L2,C L3:0.22μF
32.768kHz Crystal oscillator
(DMX-26 DAISHINKU Corp.)
8MHz Crystal oscillator
CSTLS8M00G56(MURATA Corp.)
it has built-in CGH, and CDH
CL
Measuring circuit 2
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL VREF
VL1 VL2 VL3
V
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
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Measuring circuit 3
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL
VREF
A
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
Measuring circuit 4
Input pins
Output pins
(注3)
A
VDD
VDDL
VREF
VSS
*3: Measured at the specified input pins.
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL
VREF
Waveform monitoring
Measuring circuit 5
VSS
*1: Input logic circuit to determine the specified measuring conditions.
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AC Characteristics (External Interrupt)
Parameter
External interrupt disable
period
Symbol
TNUL
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
Interrupt: Enabled (MIE = 1),
2.5×
3.5×
―
μs
CPU: NOP operation
sysclk
sysclk
P00–P03
(Rising-edge interrupt)
tNUL
P00–P03
(Falling-edge interrupt)
tNUL
NMI, P00–P03
(Both-edge interrupt)
tNUL
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AC Characteristics (Synchronous Serial Port)
Parameter
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
High-speed oscillation stopped
10
―
―
μs
500
During high-speed oscillation
―
―
ns
Symbol
SCK input cycle
(slave mode)
tSCYC
SCK output cycle
(master mode)
tSCYC
SCK input pulse width
(slave mode)
―
tSW
―
SCK
High-speed oscillation stopped
4
During high-speed oscillation
200
(*1)
SCK output pulse width
SCK
―
tSW
×0.4
(master mode)
SOUT output delay time
―
―
tSD
(slave mode)
SOUT output delay time
―
―
tSD
(master mode)
SIN input setup time
―
50
tSS
(slave mode)
SIN input hold time
―
50
tSH
*1: Clock period selected by SnCK3–0 of the serial port n mode register (SIOnMOD1)
(*1)
―
sec
―
―
μs
―
―
ns
(*1)
SCK
×0.5
(*1)
SCK
×0.6
sec
―
180
ns
―
80
ns
―
―
ns
―
―
ns
tSCYC
tSW
tSW
SCKn*
tSD
tSD
SOUTn
tSS
tSH
SINn*
*: Indicates the secondary function of the corresponding port.
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AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
fSCL
⎯
0
⎯
100
kHz
tHD:STA
⎯
4.0
⎯
⎯
μs
tLOW
tHIGH
⎯
⎯
4.7
4.0
⎯
⎯
⎯
⎯
μs
μs
tSU:STA
⎯
4.7
⎯
⎯
μs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.25
⎯
⎯
⎯
⎯
μs
μs
tSU:STO
⎯
4.0
⎯
⎯
μs
tBUF
⎯
4.7
⎯
⎯
μs
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
fSCL
⎯
0
⎯
400
kHz
tHD:STA
⎯
0.6
⎯
⎯
μs
tLOW
tHIGH
⎯
⎯
1.3
0.6
⎯
⎯
⎯
⎯
μs
μs
tSU:STA
⎯
0.6
⎯
⎯
μs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.1
⎯
⎯
⎯
⎯
μs
μs
tSU:STO
⎯
0.6
⎯
⎯
μs
tBUF
⎯
1.3
⎯
⎯
μs
Start
condition
Restart
condition
Stop
condition
P40/SDA
P41/SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
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Electrical Characteristics of Successive Approximation Type A/D Converter
Parameter
Resolution
Integral non-linearity error
Differential non-linearity
error
Zero-scale error
Full-scale error
Input impedance
Reference voltage
Conversion time
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
―
―
―
10
bits
−4
―
+4
2.7V ≤ VREF ≤ 5.5V
Symbol
n
IDL
DNL
2.7V ≤ VREF ≤ 5.5V
−3
―
+3
VOFF
FSE
RI
VREF
―
―
―
−4
−4
―
4.5
―
―
―
―
+4
+4
5k
VDD
Ω
V
tCONV
HSCLK=3.0M to 8.4MHz
―
102
―
φ/CH
LSB
φ: Period of high-speed clock (HSCLK)
VDD
Reference
voltage
VREF
VDDL
1μF
10μF
A
-
10μF
Analog input
RI≤5kΩ
+
0.1μF
AIN0
~
AIN15
VSS
25/28
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PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact LAPIS SEMICONDUCTOR’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).
26/28
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REVISION HISTORY
Document No.
Date
FEDL610Q178FULL-01
May 18, 2012
Page
Previous
Current
Edition
Edition
–
–
Description
Formal edition 1
27/28
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ML610Q178
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor
shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
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While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
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The Products are not designed or manufactured to be used with any equipment, device or system which
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under the Law.
Copyright 2012 LAPIS Semiconductor Co., Ltd.
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