ML610Q438/ML610Q439 GENERAL DESCRIPTION

ML610Q438/ML610Q439  GENERAL DESCRIPTION
FEDL610Q439-3
Issue Date: Jun 7, 2011
ML610Q438/ML610Q439
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD
driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
 CPU
 8-bit RISC CPU (CPU name: nX-U8/100)
 Instruction system: 16-bit instructions
 Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division,
bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations,
arithmetic shift, and so on
 On-Chip debug function
 Minimum instruction execution time
30.5 s (@32.768 kHz system clock)
0.24 4s (@4.096 MHz system clock)
 Internal memory
 Internal 128KByte Flash ROM (64K16 bits) (including unusable 1KByte TEST area)
 Internal 6KByte Data RAM (61448 bits), 1KByte Display Allocation RAM (1024 x 8bit)
 Internal 192-byte RAM for display
 Interrupt controller
 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
 27 maskable interrupt sources (Internal sources: 19, External sources: 8)
 Time base counter
 Low-speed time base counter 1 channel
Frequency compensation (Compensation range: Approx. 488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
 High-speed time base counter 1 channel
 Watchdog timer
 Non-maskable interrupt and reset
 Free running
 Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
 Timers
 8 bits  4 channels (16-bit configuration available)
 1 kHz timer
 10 Hz/1 Hz interrupt function
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LAPIS Semiconductor
ML610Q438/ML610Q439
 Capture
 Time base capture  2 channels (4096 Hz to 32 Hz)
 PWM
 Resolution 16 bits  3 channel
 Synchronous serial port
 Master/slave selectable
 LSB first/MSB first selectable
 8-bit length/16-bit length selectable
 Timer interrupt is used as a serial clock and selection is possible
 UART
 TXD/RXD  1 channel
 Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
 Positive logic/negative logic selectable
 Built-in baud rate generator
 I2C bus interface
 Master function only
 Fast mode (400 [email protected]4MHz), standard mode (100 [email protected]z, [email protected])
 Melody driver
 Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
 Tone length: 63 types
 Tempo: 15 types
 Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
 RC oscillation type A/D converter
 24-bit counter
 Time division  2 channels
 Successive approximation type A/D converter
 12-bit A/D converter
 Input  2 channels
 General-purpose ports
 Non-maskable interrupt input port  1 channel
 Input-only port  10 channels (including secondary functions)
 Output-only port  3 channels (including secondary functions)
 Input/output port
20 channels (including secondary functions)
 LCD driver
 Dot matrix can be supported.
ML610Q438: 1344 dots max. (56 seg  24 com)
ML610Q439: 1024 dots max. (64 seg  16 com)
 1/1 to 1/24 duty
 1/3 or 1/4 bias (built-in bias generation circuit)
 Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)
 Bias voltage multiplying clock selectable (8 types)
 Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps)
 LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
 Programmable display allocation function (available only when 1/1~1/8 duty is selected)
 The metal option of only ML610Q439
Type B : 16com x 64seg (seg63 to seg0: segment port)
Type C : 16com x 56seg (seg63 to seg56: output port、seg55 to seg0: segment port)
Type D : 16com x 48seg (seg63 to seg48: output port、seg47 to seg0: segment port)
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ML610Q438/ML610Q439
Type E : 16com x 40seg (seg63 to seg40: output port、seg39 to seg0: segment port)
Type F : 16com x 32seg (seg63 to seg32: output port、seg31 to seg0: segment port)
 Reset
 Reset through the RESET_N pin
 Power-on reset generation when powered on
 Reset when oscillation stop of the low-speed clock is detected
 Reset by the watchdog timer (WDT) overflow
 Power supply voltage detect function
 Judgment voltages:
One of 16 levels
 Judgment accuracy:
2% (Typ.)
 Clock
 Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz)
 High-speed clock:
Built-in RC oscillation (2M/500kHz)
Built-in PLL oscillation (8.192 MHz 2.5%), crystal/ceramic oscillation (4.096 MHz), external clock
 Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock
 Power management
 HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
 STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
 Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
 Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
 Shipment
 Chip (Die)
ML610Q438-xxxWA (Blank product: ML610Q438-NNNWA)
ML610Q438P-xxxWA (Blank product: ML610Q438P-NNNWA)
ML610Q439-xxxWA (Blank product: ML610Q439-NNNWA)
ML610Q439P-xxxWA (Blank product: ML610Q439P-NNNWA)
 144-pin plastic LQFP
ML610Q438-xxxTCZ03A (Blank product: ML610Q438-NNNTCZ03A)
ML610Q438P-xxxTCZ03A (Blank product: ML610Q438P-NNNTCZ03A)
ML610Q439-xxxTCZ03A (Blank product: ML610Q439-NNNTCZ03A)
ML610Q439P-xxxTCZ03A (Blank product: ML610Q439P-NNNTCZ03A)
xxx: ROM code number
 Guaranteed operating range
 Operating temperature: 20C to 70C (P version : 40C to 85C)
 Operating voltage: VDD = 1.1V to 3.6V, AVDD = 2.2V to 3.6V
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FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
BLOCK DIAGRAM
ML610Q438 Block Diagram
Figure 1 show the block diagram of the ML610Q438.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1~3
GREG
0~15
PSW
Timing
Controller
On-Chip
ICE
TEST
ECSR1~3
LR
DSR/CSR
EA
PC
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
VDD
VSS
RESET_N
ELR1~3
RESET &
TEST
XT0
XT1
INT
1
OSC
INT
4
LSCLK*
OUTCLK*
VDDL
VDDX
INT
1
Power
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
TBC
SCK0*
SIN0*
SOUT0*
UART
RXD0*
TXD0*
I2C
SDA*
SCL*
INT
1
INT
1
INT
3
PWM
×3
1kHzTC
Capture
×2
INT
4
RC-ADC
×2
WDT
VPP
SSIO
PWM0* to PWM2*
INT
1
Melody
INT
1
INT
5
8bit Timer
×4
MD0*
NMI
P00 to P03
P10 to P11
GPIO
P20 to P22
P30 to P35
P40 to P47
AVDD
AVSS
VREF
INT
1
RAM
6144byte
Interrupt
Controller
OSC0*
OSC1*
Program
Memory
(Flash)
128Kbyte
BUS
Controller
INT
1
Display Allocation
RAM 1KByte
12bit-ADC
AIN0, AIN1
Display RAM
192Byte
BLD
LCD
Driver
COM0 to COM23
LCD
BIAS
VL1, VL2, VL3, VL4
SEG0 to SEG55
C1, C2, C3, C4
Figure 1 ML610Q438 Block Diagram
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FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
ML610Q439 Block Diagram
Figure 2 show the block diagram of the ML610Q439.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1~3
GREG
0~15
PSW
Timing
Controller
On-Chip
ICE
TEST
ECSR1~3
LR
DSR/CSR
EA
PC
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
VDD
VSS
RESET_N
ELR1~3
RESET &
TEST
XT0
XT1
INT
1
OSC
INT
4
LSCLK*
OUTCLK*
VDDL
VDDX
INT
1
Power
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
TBC
SCK0*
SIN0*
SOUT0*
UART
RXD0*
TXD0*
I2C
SDA*
SCL*
INT
1
INT
1
INT
3
PWM
×3
1kHzTC
Capture
×2
INT
4
RC-ADC
×2
WDT
VPP
SSIO
PWM0* to PWM2*
INT
1
Melody
INT
1
INT
5
8bit Timer
×4
MD0*
NMI
P00 to P03
P10 to P11
GPIO
P20 to P22
P30 to P35
P40 to P47
AVDD
AVSS
VREF
INT
1
RAM
6144byte
Interrupt
Controller
OSC0*
OSC1*
Program
Memory
(Flash)
128Kbyte
BUS
Controller
INT
1
Display Allocation
RAM 1KByte
12bit-ADC
AIN0, AIN1
Display RAM
192Byte
BLD
LCD
Driver
COM0 to COM15
LCD
BIAS
VL1, VL2, VL3, VL4
SEG0 to SEG63
C1, C2, C3, C4
Figure 2 ML610Q439 Block Diagram
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FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
PIN CONFIGURATION
AVDD
(NC)
AIN1
AIN0
VSS
P07
P06
P05
P04
PA5
PA4
PA3
PA2
PA1
PA0
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
SEG55
SEG54
SEG53
SEG52
SEG51
ML610Q438 LQFP144 Pin Layout
108pin
72pin
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
109pin
73pin
VREF
AVSS
VSS
P20
P21
P22
P40
P41
VPP
RESET_N
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
VSS
VDDX
XT0
(NC)
XT1
P42
P43
VL1
VL2
VL3
VL4
C1
C2
L610Q438
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
144pin
1pin
C3
C4
P00/EXI0
P01/EXI1
P02/EXI2
P03/EXI3
NMI
VSS
P10
(NC)
P11
VDD
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
(NC)
SEG16
37pin
36pin
(NC): No Connection
Figure 3 ML610Q438 LQFP144 Pin Configuration
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FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
AVDD
(NC)
AIN1
AIN0
VSS
P07
P06
P05
P04
PA5
PA4
PA3
PA2
PA1
PA0
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
ML610Q439 LQFP144 Pin Layout
108pin
72pin
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
109pin
73pin
VREF
AVSS
VSS
P20
P21
P22
P40
P41
VPP
RESET_N
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
VSS
VDDX
XT0
(NC)
XT1
P42
P43
VL1
VL2
VL3
VL4
C1
C2
L610Q439
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
144pin
1pin
C3
C4
P00/EXI0
P01/EXI1
P02/EXI2
P03/EXI3
NMI
VSS
P10
(NC)
P11
VDD
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
(NC)
SEG16
37pin
36pin
(NC): No Connection
Figure 4 ML610Q439 LQFP144 Pin Configuration
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FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
AVDD
AIN1
AIN0
VSS
P07
P06
P05
P04
PA5
PA4
PA3
PA2
PA1
PA0
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
SEG55
SEG54
SEG53
SEG52
SEG51
83
82
81
80
79
78
77
76
75
74
73
72
71
□□□□□□□□□□□□□□□□□□□□□□
□□□□□□□□
□□□□□
□□
□□□□□□□□□□□□□□□□□□□□□□□□
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
3.46m
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
□□□□□□□□□
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
P11 10
VDD 11
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
1
2
3
4
5
6
7
8
9
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
C3
C4
P00/EXI
P01/EXI
P02/EXI
P03/EXI
NMI
VSS
P10
VREF
AVSS
VSS
P20
P21
P22
P40
P41
VPP
RESET_N
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
VSS
VDDX
XT0
XT1
P42
P43
VL1
VL2
VL3
VL4
C1
C2
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
ML610Q438 Chip Pin Layout & Dimension
3.51mm
Chip size:
PAD count:
Minimum PAD pitch:
PAD aperture:
Chip thickness:
Voltage of the rear side of chip:
3.51 mm  3.46 mm
140 pins
80 m
80 m  80 m
350 m
VSS level
Figure 5 ML610Q438 Chip Layout & Dimension
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FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
AVDD
AIN1
AIN0
VSS
P07
P06
P05
P04
PA5
PA4
PA3
PA2
PA1
PA0
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
83
82
81
80
79
78
77
76
75
74
73
72
71
□□□□□□□□□□□□□□□□□□□□□□
□□□□□□□□
□□□□□
□□
□□□□□□□□□□□□□□□□□□□□□□□□
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
3.46mm
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
□□□□□□□□□
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
P11 10
VDD 11
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
1
2
3
4
5
6
7
8
9
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
C3
C4
P00/EXI
P01/EXI
P02/EXI
P03/EXI
NMI
VSS
P10
VREF
AVSS
VSS
P20
P21
P22
P40
P41
VPP
RESET_N
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
VSS
VDDX
XT0
XT1
P42
P43
VL1
VL2
VL3
VL4
C1
C2
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
ML610Q439 Chip Pin Layout & Dimension
3.51mm
Chip size:
PAD count:
Minimum PAD pitch:
PAD aperture:
Chip thickness:
Voltage of the rear side of chip:
3.51 mm  3.46 mm
140 pins
80 m
80 m  80 m
350 m
VSS level
Figure 6 ML610Q439 Chip Layout & Dimension
9/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
ML610Q438 Pad Coordinates
Table 1 ML610Q438 Pad Coordinates
Chip Center: X=0,Y=0
PAD
No.
Pad
Name
X
(μm)
Y
(μm)
PAD
No.
Pad
Name
X
(μm)
Y
(μm)
PAD
No.
Pad
Name
X
(μm)
Y
(μm)
1
C3
-1485
-1624
48
SEG28
1649
-400
95
PA3
-525
1624
2
C4
-1405
-1624
49
SEG29
1649
-320
96
PA4
-605
1624
3
P00/EXI0
-1315
-1624
50
SEG30
1649
-240
97
PA5
-685
1624
4
P01/EXI1
-1235
-1624
51
SEG31
1649
-160
98
P04
-765
1624
5
P02/EXI2
/RXD0/P2
CK
-1155
-1624
52
SEG32
1649
-80
99
P05
-845
1624
6
P03/EXI3
-1075
-1624
53
SEG33
1649
0
100
P06
-925
1624
7
NMI
-995
-1624
54
SEG34
1649
80
101
P07
-1005
1624
8
VSS
-865
-1624
55
SEG35
1649
160
102
VSS
-1106
1624
9
P10
-785
-1624
56
SEG36
1649
240
103
AIN0
-1186
1624
10
P11
-625
-1624
57
SEG37
1649
320
104
AIN1
-1366
1624
11
VDD
-545
-1624
58
SEG38
1649
400
105
AVDD
-1446
1624
12
COM0
-445
-1624
59
SEG39
1649
480
106
VREF
-1649
1430
13
COM1
-365
-1624
60
SEG40
1649
560
107
AVSS
-1649
1270
14
COM2
-285
-1624
61
SEG41
1649
640
108
VSS
-1649
1190
15
COM3
-205
-1624
62
SEG42
1649
720
109
P20
-1649
1095
16
COM4
-125
-1624
63
SEG43
1649
800
110
P21
-1649
1015
17
COM5
-45
-1624
64
SEG44
1649
880
111
P22
-1649
935
18
COM6
35
-1624
65
SEG45
1649
960
112
P40
-1649
855
19
COM7
115
-1624
66
SEG46
1649
1040
113
P41
-1649
775
20
SEG0
235
-1624
67
SEG47
1649
1120
114
VPP
-1649
695
21
SEG1
315
-1624
68
SEG48
1649
1200
115
RESET_N
-1649
615
22
SEG2
395
-1624
69
SEG49
1649
1280
116
P44
-1649
535
23
SEG3
475
-1624
70
SEG50
1649
1360
117
P45
-1649
455
24
SEG4
555
-1624
71
SEG51
1515
1624
118
P46
-1649
375
25
SEG5
635
-1624
72
SEG52
1435
1624
119
P47
-1649
295
26
SEG6
715
-1624
73
SEG53
1355
1624
120
P30
-1649
215
27
SEG7
795
-1624
74
SEG54
1275
1624
121
P31
-1649
135
28
SEG8
875
-1624
75
SEG55
1195
1624
122
P34
-1649
55
29
SEG9
955
-1624
76
COM23
1095
1624
123
P32
-1649
-25
30
SEG10
1035
-1624
77
COM22
1015
1624
124
P33
-1649
-105
31
SEG11
1115
-1624
78
COM21
935
1624
125
P35
-1649
-185
32
SEG12
1195
-1624
79
COM20
855
1624
126
TEST
-1649
-265
33
SEG13
1275
-1624
80
COM19
775
1624
127
VDD
-1649
-345
34
SEG14
1355
-1624
81
COM18
695
1624
128
VDDL
-1649
-425
35
SEG15
1435
-1624
82
COM17
615
1624
129
VSS
-1649
-505
36
SEG16
1649
-1360
83
COM16
535
1624
130
VDDX
-1649
-585
37
SEG17
1649
-1280
84
COM15
375
1624
131
XT0
-1649
-665
38
SEG18
1649
-1200
85
COM14
295
1624
132
XT1
-1649
-825
39
SEG19
1649
-1120
86
COM13
215
1624
133
P42
-1649
-905
40
SEG20
1649
-1040
87
COM12
135
1624
134
P43
-1649
-985
41
SEG21
1649
-960
88
COM11
55
1624
135
VL1
-1649
-1080
42
SEG22
1649
-880
89
COM10
-25
1624
136
VL2
-1649
-1160
43
SEG23
1649
-800
90
COM9
-105
1624
137
VL3
-1649
-1240
44
SEG24
1649
-720
91
COM8
-185
1624
138
VL4
-1649
-1320
45
SEG25
1649
-640
92
PA0
-285
1624
139
C1
-1649
-1400
46
SEG26
1649
-560
93
PA1
-365
1624
140
C2
-1649
-1480
47
SEG27
1649
-480
94
PA2
-445
1624
10/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
ML610Q439 Pad Coordinates
Table 2 ML610Q439 Pad Coordinates
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Pad
Name
C3
C4
P00/EXI0
P01/EXI1
P02/EXI2
/RXD0/P2
CK
P03/EXI3
NMI
VSS
P10
P11
VDD
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
Chip Center: X=0,Y=0
Pad
X
Y
Name
(μm)
(μm)
PA3
-525
1624
PA4
-605
1624
PA5
-685
1624
P04
-765
1624
X
(μm)
-1485
-1405
-1315
-1235
Y
(μm)
-1624
-1624
-1624
-1624
PAD
No.
48
49
50
51
Pad
Name
SEG28
SEG29
SEG30
SEG31
X
(μm)
1649
1649
1649
1649
Y
(μm)
-400
-320
-240
-160
PAD
No.
95
96
97
98
-1155
-1624
52
SEG32
1649
-80
99
P05
-845
1624
-1075
-995
-865
-785
-625
-545
-445
-365
-285
-205
-125
-45
35
115
235
315
395
475
555
635
715
795
875
955
1035
1115
1195
1275
1355
1435
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1624
-1360
-1280
-1200
-1120
-1040
-960
-880
-800
-720
-640
-560
-480
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
PA0
PA1
PA2
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1649
1515
1435
1355
1275
1195
1095
1015
935
855
775
695
615
535
375
295
215
135
55
-25
-105
-185
-285
-365
-445
0
80
160
240
320
400
480
560
640
720
800
880
960
1040
1120
1200
1280
1360
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
1624
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
P06
P07
VSS
AIN0
AIN1
AVDD
VREF
AVSS
VSS
P20
P21
P22
P40
P41
VPP
RESET_N
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
VSS
VDDX
XT0
XT1
P42
P43
VL1
VL2
VL3
VL4
C1
C2
-925
-1005
-1106
-1186
-1366
-1446
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
-1649
1624
1624
1624
1624
1624
1624
1430
1270
1190
1095
1015
935
855
775
695
615
535
455
375
295
215
135
55
-25
-105
-185
-265
-345
-425
-505
-585
-665
-825
-905
-985
-1080
-1160
-1240
-1320
-1400
-1480
11/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
PIN LIST
PAD No.
Q439 Q438
8,102,
108,129
Primary function
Pin name I/O
Function
Tertiary function
Pin name
I/O
Function
Vss

Negative power supply
pin






Positive power supply
pin
Power supply pin for
 internal logic (internally
generated)
Power supply pin for
 low-speed oscillation
(internally generated)
Power supply pin for

Flash ROM
Negative power supply
pin for successive

approximation type
ADC
Positive power supply
pin for successive

approximation type
ADC
Power supply pin for
 LCD bias (internally
generated)
Power supply pin for
 LCD bias (internally
generated)
Power supply pin for
 LCD bias (internally
generated)
Power supply pin for
 LCD bias (internally
generated)
Capacitor connection
 pin for LCD bias
generation
Capacitor connection
 pin for LCD bias
generation
Capacitor connection
 pin for LCD bias
generation
Capacitor connection
 pin for LCD bias
generation
Input/output pin for
I/O
testing


























































































Reset input pin






Low-speed clock
oscillation pin
Low-speed clock
oscillation pin
Reference power
supply pin for
successive
approximation type
ADC
Successive
approximation type
ADC input
























8,102,
108,12
Secondary function
Pin name I/O
Function
9
11,127 11,127
VDD

128
128
VDDL
130
130
VDDX
114
114
VPP
107
107
AVSS
105
105
AVDD
135
135
VL1
136
136
VL2
137
137
VL3
138
138
VL4
139
139
C1
140
140
C2
1
1
C3
2
2
C4
126
126
TEST
115
115
RESET_
N
I
131
131
XT0
I
132
132
XT1
O
106
106
VREF

103
103
AIN0
I
12/36
FEDL610Q439-3
LAPIS Semiconductor
PAD No.
Q439 Q438
ML610Q438/ML610Q439
Primary function
Pin name
I/O
104
104
AIN1
I
7
7
NMI
I
3
3
P00/EXI0/C
AP0
I
4
4
P01/EXI1/C
AP1
I
5
5
P02/EXI2
/RXD0
/P2CK
I
6
6
P03/EXI3
I
98
98
P04/EXI4
I/O
99
99
P05/EXI5
I/O
100
100
P06/EXI6
I/O
101
101
P07/EXI7
I/O
9
9
P10
I
Secondary function
Function
Pin name
Successive
approximation type

ADC input
Non-maskable interrupt

pin
Input port, External
interrupt 0 input,

Capture 0 input
Input port, External

interrupt 1 input,
Capture 1 input
Input port, External
interrupt 2, UART0

receive, PWM2 external
clock input
Input port, External

interrupt 3
Input port, External

interrupt 4
Input port, External

interrupt 5
Input port, External

interrupt 6
Input port, External

interrupt 7
Input port
OSC0
Tertiary function
I/O
Function
Pin name I/O
Function


















































I
High-speed oscillation



High-speed oscillation
10
10
P11
I
Input port
OSC1
O



109
109
P20/LED0
O
Output port
LSCLK
O Low-speed clock output
PWM2
O
PWM2 output
110
110
P21/LED1
O
Output port
OUTCLK
O High-speed clock output



MD0
O


O
PWM2 output






O
PWM0 output
O
PWM1 output
I
SSIO data input
111
111
P22/LED2
O
Output port
120
120
P30
I/O
Input/output port
IN0
I
121
121
P31
I/O
Input/output port
CS0
O
123
123
P32
I/O
Input/output port
RS0
O
124
124
P33
I/O
Input/output port
RT0
O
122
122
P34
I/O
Input/output port
RCT0
O
125
125
P35
I/O
Input/output port
RCM
O
112
112
P40
I/O
Input/output port
SDA
I/O
113
113
P41
I/O
Input/output port
SCL
I/O
133
133
P42
I/O
Input/output port
RXD0
I/O
Input/output port
Input/output port, Timer
0/Timer 2/PWM0
external clock input
Input/output port, Timer
1/Timer 3/PWM1
external clock input
Input/output port,
PWM2 external clock
input
TXD0
IN1
I
CS1
O
RS1
O
134
134
P43
116
116
P44/T02P0
I/O
CK
117
117
P45/T13P1
I/O
CK
118
118
P46/T46P2
I/O
CK
Melody output

RC type ADC0
PWM2
oscillation input pin
RC type ADC0
reference capacitor

connection pin
RC type ADC0

reference resistor
connection pin
RC type ADC0 resistor

sensor connection pin
RC type ADC0
resistor/capacitor
PWM0
sensor connection pin
RC type ADC oscillation
PWM1
monitor
I2C data input/output
SIN0
I2C clock input/output
SCK0
I
UART data input
SOUT0
O
SSIO data output
O
UART data output
PWM0
O
PWM0 output
RC type ADC1
oscillation input pin
SIN0
I
SSIO0 data input
SCK0
I/O
SSIO0 synchronous
clock
SOUT0
O
SSIO0 data output
RC type ADC1
reference capacitor
connection pin
RC type ADC1
reference resistor
connection pin
I/O SSIO synchronous clock
13/36
FEDL610Q439-3
LAPIS Semiconductor
PAD No.
Q439 Q438
ML610Q438/ML610Q439
Primary function
Pin name
I/O
Function
Secondary function
Pin name I/O
Function
Tertiary function
Pin name I/O
Function
119
119
P47
I/O
Input/output port
RT1
O
RC type ADC1
resistor sensor
connection pin
92
92
PA0
I/O
Input/output port






93
93
PA1
I/O
Input/output port






94
94
PA2
I/O
Input/output port






95
95
PA3
I/O
Input/output port






96
96
PA4
I/O
Input/output port






97
97
PA5
I/O
Input/output port






12
12
COM0
O
LCD common pin






13
13
COM1
O
LCD common pin






14
14
COM2
O
LCD common pin






15
15
COM3
O
LCD common pin






16
16
COM4
O
LCD common pin






17
17
COM5
O
LCD common pin






18
18
COM6
O
LCD common pin






19
19
COM7
O
LCD common pin






91
91
COM8
O
LCD common pin






90
90
COM9
O
LCD common pin






89
89
COM10
O
LCD common pin






88
88
COM11
O
LCD common pin






87
87
COM12
O
LCD common pin






86
86
COM13
O
LCD common pin






85
85
COM14
O
LCD common pin






84
84
COM15
O
LCD common pin







83
COM16
O
LCD common pin







82
COM17
O
LCD common pin







81
COM18
O
LCD common pin







80
COM19
O
LCD common pin







79
COM20
O
LCD common pin







78
COM21
O
LCD common pin







77
COM22
O
LCD common pin







76
COM23
O
LCD common pin






20
20
SEG0
O
LCD segment pin






21
21
SEG1
O
LCD segment pin






22
22
SEG2
O
LCD segment pin






23
23
SEG3
O
LCD segment pin






24
24
SEG4
O
LCD segment pin






25
25
SEG5
O
LCD segment pin






26
26
SEG6
O
LCD segment pin






27
27
SEG7
O
LCD segment pin






28
28
SEG8
O
LCD segment pin






29
29
SEG9
O
LCD segment pin






30
30
SEG10
O
LCD segment pin






31
31
SEG11
O
LCD segment pin






32
32
SEG12
O
LCD segment pin






33
33
SEG13
O
LCD segment pin






34
34
SEG14
O
LCD segment pin






35
35
SEG15
O
LCD segment pin






36
36
SEG16
O
LCD segment pin






PWM1
O
PWM1 output
14/36
FEDL610Q439-3
LAPIS Semiconductor
PAD No.
Q439 Q438
ML610Q438/ML610Q439
Primary function
Secondary function
Pin name I/O
Function
Tertiary function
Pin name
I/O
Function
37
37
SEG17
O
LCD segment pin



Pin name I/O


Function

38
38
SEG18
O
LCD segment pin






39
39
SEG19
O
LCD segment pin






40
40
SEG20
O
LCD segment pin






41
41
SEG21
O
LCD segment pin






42
42
SEG22
O
LCD segment pin






43
43
SEG23
O
LCD segment pin






44
44
SEG24
O
LCD segment pin






45
45
SEG25
O
LCD segment pin






46
46
SEG26
O
LCD segment pin






47
47
SEG27
O
LCD segment pin






48
48
SEG28
O
LCD segment pin






49
49
SEG29
O
LCD segment pin






50
50
SEG30
O
LCD segment pin






51
51
SEG31
O
LCD segment pin






52
52
SEG32
O
LCD segment pin






53
53
SEG33
O
LCD segment pin






54
54
SEG34
O
LCD segment pin






55
55
SEG35
O
LCD segment pin






56
56
SEG36
O
LCD segment pin






57
57
SEG37
O
LCD segment pin






58
58
SEG38
O
LCD segment pin






59
59
SEG39
O
LCD segment pin






60
60
SEG40
O
LCD segment pin






61
61
SEG41
O
LCD segment pin






62
62
SEG42
O
LCD segment pin






63
63
SEG43
O
LCD segment pin






64
64
SEG44
O
LCD segment pin






65
65
SEG45
O
LCD segment pin






66
66
SEG46
O
LCD segment pin






67
67
SEG47
O
LCD segment pin






68
68
SEG48
O
LCD segment pin






69
69
SEG49
O
LCD segment pin






70
70
SEG50
O
LCD segment pin






71
71
SEG51
O
LCD segment pin






72
72
SEG52
O
LCD segment pin






73
73
SEG53
O
LCD segment pin






74
74
SEG54
O
LCD segment pin






75
75
SEG55
O
LCD segment pin






76

SEG56
O
LCD segment pin






77

SEG57
O
LCD segment pin






78

SEG58
O
LCD segment pin






79

SEG59
O
LCD segment pin






80

SEG60
O
LCD segment pin






81

SEG61
O
LCD segment pin






82

SEG62
O
LCD segment pin






83

SEG63
O
LCD segment pin






15/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
PIN DESCRIPTION
Pin name
I/O
Description
Primary/
Secondary/
Tertiary
Logic
—
Negative
—
—
—
—
Secondary
Secondary
—
—
Secondary
—
Secondary
—
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Secondary
Positive
Primary/Se
condary
Positive
System
Reset input pin. When this pin is set to a “L” level, system reset mode is
set and the internal section is initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up resistor is internally
connected.
XT0
I Crystal connection pin for low-speed clock.
XT1
O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to
this pin. Capacitors CDL and CGL are connected across this pin and VSS
as required.
OSC0
I Crystal/ceramic connection pin for high-speed clock.
OSC1
O A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors
CDH and CGH (see measuring circuit 1) are connected across this pin
and VSS.
This pin is used as the secondary function of the P10 pin(OSC0) and P11
pin(OSC1).
LSCLK
O Low-speed clock output pin. This pin is used as the secondary function of
the P20 pin.
OUTCLK
O High-speed clock output pin. This pin is used as the secondary function of
the P21 pin.
General-purpose input port
RESET_N
I
General-purpose input port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P10-P11
I General-purpose input port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose output port
P20-P22
O General-purpose output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port
P30-P35
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P40-P47
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
PA0-PA5
I/O General-purpose input/output port.
P00-P07
I
UART
TXD0
O
RXD0
I
UART data output pin. This pin is used as the secondary function of the
P43 pin.
UART data input pin. This pin is used as the secondary function of the
P42 or the primary function of the P02 pin.
16/36
FEDL610Q439-3
LAPIS Semiconductor
Pin name
I/O
ML610Q438/ML610Q439
Description
Primary/
Secondary/
Tertiary
Logic
Secondary
Positive
Secondary
Positive
Tertiary
—
Tertiary
Positive
Tertiary
Positive
Tertiary
Positive
Primary
—
Tertiary
Positive
Primary
—
Tertiary
Positive
Primary
—
Primary
Positive/
negative
Positive/
negative
2
I C bus interface
2
SDA
I/O I C data input/output pin. This pin is used as the secondary function of the
P40 pin. This pin has an NMOS open drain output. When using this pin as
2
a function of the I C, externally connect a pull-up resistor.
2
SCL
O I C clock output pin. This pin is used as the secondary function of the P41
pin. This pin has an NMOS open drain output. When using this pin as a
2
function of the I C, externally connect a pull-up resistor.
Synchronous serial (SSIO)
SCK0
SIN0
SOUT0
PWM
PWM0
I/O Synchronous serial clock input/output pin. This pin is used as the tertiary
function of the P41 or P45 pin.
I Synchronous serial data input pin. This pin is used as the tertiary function
of the P40 or P44 pin.
O Synchronous serial data output pin. This pin is used as the tertiary
function of the P42 or P46 pin.
O
T0P0CK
I
PWM1
O
T1P1CK
I
PWM2
O
P2CK
I
External interrupt
NMI
I
EXI0-7
I
PWM0 output pin. This pin is used as the tertiary function of the P43 or
P34 pin.
PWM0 external clock input pin. This pin is used as the primary function of
the P44 pin.
PWM1 output pin. This pin is used as the tertiary function of the P47 or
P35 pin.
PWM1 external clock input pin. This pin is used as the primary function of
the P45 pin.
PWM2 output pin. This pin is used as the tertiary function of the P20 or
P30 pin.
PWM2 external clock input pin. This pin is used as the primary function of
the P02 pin.
External non-maskable interrupt input pin. An interrupt is generated on
both edges.
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P00-P07 pins.
Primary
Capture
CAP0
I
CAP1
I
Capture trigger input pins. The value of the time base counter is captured
in the register synchronously with the interrupt edge selected by software.
These pins are used as the primary functions of the P00 pin(CAP0) and
P01 pin(CAP1).
Primary
Primary
Positive/
negative
Positive/
negative
Timer
T0P0CK
I
T1P1CK
I
External clock input pin used for Timer 0. This pin is used as the primary
function of the P44 pin.
External clock input pin used for Timer 1. This pin is used as the primary
function of the P45 pin.
Melody
MD0
O
Melody/buzzer signal output pin. This pin is used as the secondary
function of the P22 pin.
LED drive
LED0-2
O
Nch open drain output pins to drive LED.
Primary
Primary
—
—
Secondary Positive/
negative
Primary
Positive/
negative
17/36
FEDL610Q439-3
LAPIS Semiconductor
Pin name
I/O
ML610Q438/ML610Q439
Description
RC oscillation type A/D converter
IN0
I Channel 0 oscillation input pin. This pin is used as the secondary function
of the P30 pin.
CS0
O Channel 0 reference capacitor connection pin. This pin is used as the
secondary function of the P31 pin.
RS0
O This pin is used as the secondary function of the P32 pin which is the
reference resistor connection pin of Channel 0.
RT0
O Resistor sensor connection pin of Channel 0 for measurement. This pin is
used as the secondary function of the P34 pin.
CRT0
O Resistor/capacitor sensor connection pin of Channel 0 for measurement.
This pin is used as the secondary function of the P33 pin.
RCM
O RC oscillation monitor pin. This pin is used as the secondary function of
the P35 pin.
IN1
I Oscillation input pin of Channel 1. This pin is used as the secondary
function of the P44 pin.
CS1
O Reference capacitor connection pin of Channel 1. This pin is used as the
secondary function of the P45 pin.
RS1
O Reference resistor connection pin of Channel 1. This pin is used as the
secondary function of the P46 pin.
RT1
O Resistor sensor connection pin for measurement of Channel 1. This pin is
used as the secondary function of the P47 pin.
Successive approximation type A/D converter
AVSS
— Negative power supply pin for successive approximation type A/D
converter.
AVDD
— Positive power supply pin for successive approximation type A/D
converter.
VREF
— Reference power supply pin for successive approximation type A/D
converter.
AIN0
I Channel 0 analog input for successive approximation type A/D converter.
AIN1
I
Channel 1 analog input for successive approximation type A/D converter.
LCD drive signal
COM0-15
O
COM8-23
O
Common output pins.
Common output pins.
These pins are for the ML610Q438, but are not provided in the
ML610Q439.
SEG0-57
O Segment output pin.
SEG58-63
O Segment output pins.
These pins are for the ML610Q439, but are not provided in the
ML610Q438.
LCD driver power supply
VL1
— Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb,
VL2
— Cc, and Cd (see measuring circuit 1) are connected between VSS and VL1,
V
— VL2, VL3, and VL4, respectively.
L3
VL4
C1
C2
C3
C4
For testing
—
—
—
—
—
Power supply pins for LCD bias (internally generated). Capacitors C12
and C34 (see measuring circuit 1) are connected between C1 and C2 and
between C3 and C4, respectively.
TEST
I/O Input/output pin for testing. A pull-down resistor is internally connected.
Power supply
VSS
— Negative power supply pin.
Primary/
Secondary/
Tertiary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Logic
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/36
FEDL610Q439-3
LAPIS Semiconductor
VDD
VDDL
—
—
VDDX
—
VPP
—
Positive power supply pin.
Positive power supply pin (internally generated) for internal logic.
Capacitors CL0 and CL1 (see measuring circuit 1) are connected between
this pin and VSS.
Plus-side power supply pin (internally generated) for low-speed oscillation.
Capacitor Cx (see measuring circuit 1) is connected between this pin and
VSS.
Power supply pin for programming Flash ROM. A pull-up resistor is
internally connected.
ML610Q438/ML610Q439
—
—
—
—
—
—
—
—
19/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
TERMINATION OF UNUSED PINS
Table 3 shows methods of terminating the unused pins.
Table 3
Termination of Unused Pins
Pin
Recommended pin termination
Open
VPP
AVDD
VSS
AVSS
VSS
VREF
VSS
AIN0, AIN1
Open
VL1, VL2, VL3, VL4
Open
C1, C2, C3, C4
RESET_N
TEST
NMI
P00 to P07
P10 to P11
P20 to P22
P30 to P35
P40 to P47
PA0 to PA5
COM0 to 23
SEG0 to 63
Open
Open
Open
Open
VDD or VSS
VDD
Open
Open
Open
Open
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
The main difference points of ML610Q438 and ML610Q439
Table 4
The main difference points of ML610Q438 and ML610Q439.
Function
LCD COM
LCD SEG
ML610Q438
ML610Q439
COM23 to COM0
SEG55 to SEG0
COM15 to COM0
SEG63 to SEG0
20/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(VSS = AVSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta = 25C
0.3 to +4.6
V
Power supply voltage 2
AVDD
Ta = 25C
0.3 to +4.6
V
Power supply voltage 3
VPP
Ta = 25C
0.3 to +9.5
V
Power supply voltage 4
VDDL
Ta = 25C
0.3 to +3.6
V
Power supply voltage 5
Power supply voltage 6
Power supply voltage 7
VDDX
VL1
VL2
Ta = 25C
Ta = 25C
Ta = 25C
0.3 to +3.6
0.3 to +1.75
0.3 to +3.5
V
V
V
Power supply voltage 8
VL3
Ta = 25C
0.3 to +5.25
V
Power supply voltage 9
VL4
Ta = 25C
0.3 to +7.0
V
Input voltage
VIN
Ta = 25C
0.3 to VDD+0.3
V
Output voltage
VOUT
Ta = 25C
0.3 to VDD+0.3
V
Output current 1
IOUT1
Port3–A, Ta = 25C
12 to +11
mA
Output current 2
IOUT2
Port2, Ta = 25C
12 to +20
mA
Power dissipation
PD
Ta = 25C
122
mW
Storage temperature
TSTG

55 to +150
C
RECOMMENDED OPERATING CONDITIONS
(VSS = AVSS = 0V)
Parameter
Operating temperature
Operating voltage
Symbol
TOP
VDD
Condition
Range
Unit
ML610Q438/Q439
20 to +70
C
ML610Q438P/Q439P



1.1 to 3.6
V
AVDD

2.2 to 3.6
AVDD
fOP
VDD = 1.1 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.8 to 3.6V
30k to 36k
30k to 650k
30k to 4.2M
Hz
fXTL

32.768k
Hz
CDL
CGL


0 to 12
0 to 12
pF
fXTH

4.0M / 4.096M
Hz
CDH
CGH
CL0
CL1




24
24
1.030%
0.130%
CX

0.130%
F
Capacitors externally connected to
VL1, 2, 3, 4 pins
Ca, b, c, d

1.030%
F
Capacitors externally connected
across C1 and C2 pins and across
C3 and C4 pins
C12, C34

1.030%
F
Operating frequency (CPU)
Low-speed crystal oscillation
frequency
Low-speed crystal oscillation
external capacitor
High-speed crystal/ceramic
oscillation frequency
High-speed crystal oscillation
external capacitor
Capacitor externally connected to
VDDL pin
Capacitor externally connected to
VDDX pin
pF
F
21/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
OPERATING CONDITIONS OF FLASH ROM
Parameter
Operating temperature
Symbol
TOP
VDD
VDDL
VPP
CEP
YDR
Operating voltage
Write cycles
Data retention
(VSS = AVSS = 0V)
Range
Unit
0 to +40
C
2.75 to 3.6
V
2.5 to 2.75
7.7 to 8.3
80
cycles
years
10
Condition
At write/erase
*1
At write/erase
*1
At write/erase
*1
At write/erase


*1
: In addition the power supply to VDD pin and VPP pin, within the range 2.5V to 2.75V has to be supplied to VDDL
pin when programming and eraseing Flash ROM.
DC CHARACTERISTICS (1/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,unless otherwise
specified ) (1/5)
Measuring
Rating
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
500kHz RC oscillation frequency
4
fRC
PLL oscillation frequency*
fPLL
Low-speed crystal oscillation
2
start time*
TXTL
500kHz RC oscillation start time
High-speed crystal oscillation
3
start time*
PLL oscillation start time
Low-speed oscillation stop detect
*1
time
Reset pulse width
Reset noise elimination
pulse width
Power-on reset activation
power rise time
VDD =
1.3 to
3.6V
Ta = 25C
Ta = 20 to
+70C
LSCLK = 32.768kHz
VDD = 1.8 to 3.6V
Typ.
10%
Typ.
25%
500
500
Typ.
10%
Typ.
25%
kHz
kHz
-2.5%
8.192
+2.5%
MHz


0.3
2
s
TRC


50
500
s
TXTH
VDD = 1.8 to 3.6V
―
2
20
TPLL
VDD = 1.8 to 3.6V
―
1
10
TSTOP

0.2
3
20
PRST

200


PNRST



0.3
TPOR



10
1
ms
s
ms
*1: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is
reset to shift to system reset mode.
2
* : Use 32.768KHz Crystal Resonator DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.)
3
* : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
4
* : 1024 clock average.
RESET
VIL1
RESET_N
VIL1
PRST
RESET_N pin reset
0.9xVDD
VDD
0.1xVDD
TPOR
Power on reset
22/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
DC CHARACTERISTICS (2/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version, unless otherwise
specified) (2/5)
Measuring
Rating
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
CN4–0 = 00H
0.89
0.94
0.99
CN4–0 = 01H
0.91
0.96
1.01
CN4–0 = 02H
0.93
0.98
1.03
CN4–0 = 03H
0.95
1.00
1.05
CN4–0 = 04H
0.97
1.02
1.07
CN4–0 = 05H
0.99
1.04
1.09
CN4–0 = 06H
1.01
1.06
1.11
CN4–0 = 07H
1.03
1.08
1.13
CN4–0 = 08H
1.05
1.10
1.15
CN4–0 = 09H
1.07
1.12
1.17
CN4–0 = 0AH
1.09
1.14
1.19
CN4–0 = 0BH
1.11
1.16
1.21
CN4–0 = 0CH
1.13
1.18
1.23
CN4–0 = 0DH
1.15
1.20
1.25
CN4–0 = 0EH
1.17
1.22
1.27
VDD = 3.0V,
CN4–0 = 0FH
1.19
1.24
1.29
VL1 voltage
VL1
V
Tj = 25C
CN4–0 = 10H
1.21
1.26
1.31
CN4–0 = 11H
1.23
1.28
1.33
CN4–0 = 12H
1.25
1.30
1.35
CN4–0 = 13H
1.27
1.32
1.37
*1
CN4–0 = 14H
1.29
1.34
1.39
*1
CN4–0 = 15H
1.31
1.36
1.41
1
*1
CN4–0 = 16H
1.33
1.38
1.43
*1
CN4–0 = 17H
1.35
1.40
1.45
*1
CN4–0 = 18H
1.37
1.42
1.47
*1
CN4–0 = 19H
1.39
1.44
1.49
*1
CN4–0 = 1AH
1.41
1.46
1.51
*1
CN4–0 = 1BH
1.43
1.48
1.53
*1
CN4–0 = 1CH
1.45
1.50
1.55
*1
CN4–0 = 1DH
1.47
1.52
1.57
*1
CN4–0 = 1EH
1.49
1.54
1.59
*1
CN4–0 = 1FH
1.51
1.56
1.61
VL1 temperature
deviation
VL1
VL1 voltage
dependency
VL1
VL2 voltage
VL2
VL3 voltage
VL3
VL4 voltage
VL4
LCD bias voltage
generation time
TBIAS



mV/C
VDD = 1.3 to 3.6V

5
20
mV/V
VDD = 3.0V, Tj = 25C
300k load (VL4VSS)
1/3 bias
VDD = 3.0V,
Tj = 25C
1/4 bias
300k load
1/3 bias
(VL4VSS)
1/4 bias
Typ.
%
Typ.
10%
VL12
Typ.
10%
VL12
VL13
VL13
VL14
Typ.
+4%
Typ.
+4%



VDD = 3.0V
V
Typ.
+5%
600
ms
*1: When using 1/4 bias, the VL1 voltage is set to typ. 1.32 V (same voltage as in CN4–0 = 13H).
23/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
DC CHARACTERISTICS (3/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,unless otherwise
specified) (3/5)
Rating
Measuring
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
LD2–0 = 0H
1.35
LD2–0 = 1H
1.4
LD2–0 = 2H
1.45
LD2–0 = 3H
1.5
LD2–0 = 4H
1.6
LD2–0 = 5H
1.7
LD2–0 = 6H
1.8
BLD
LD2–0 = 7H
1.9
Typ.
Typ.
threshold
VDD = 1.35 to 3.6V
V
VBLD
2%
+2%
LD2–0 = 8H
2.0
voltage
LD2–0 = 9H
2.1
LD2–0 = 0AH
2.2
LD2–0 = 0BH
2.3
LD2–0 = 0CH
2.4
LD2–0 = 0DH
2.5
LD2–0 = 0EH
2.7
LD2–0 = 0FH
2.9
BLD
threshold
voltage
temperature
deviation
Supply current
1
Supply current
2
Supply current
3
Supply current
4
Supply current
5
VBLD
IDD1
IDD2
IDD3
IDD4
IDD5

0

Ta =
25C

0.15
0.50
Ta = -20
to +70C


2.50
Ta =
25C

0.5
1.3
Ta = -20
to +70C


3.5
Ta =
25C

5
7
Ta = -20
to +70C


12
Ta =
25C

70
85
Ta = -20
to +70C


100
Ta =
25C

0.8
1.0
Ta = -20
to +70C


1.2
VDD = 1.35 to 3.6V
CPU: In STOP state.
Low-speed/high-speed oscillation:
stopped.
CPU: In HALT state (LTBC, RTC:
Operating*3*5).
High-speed oscillation: Stopped.
LCD/BIAS circuits: Stopped.
CPU: In 32.768kHz operating state.*1*3
High-speed oscillation: Stopped.
LCD/BIAS circuits: Operating.*2
CPU: In 500kHz CR operating state.
LCD/BIAS circuits: Operating.*2*3
CPU: In 4.096MHz operating state.
PLL: In oscillating state.
LCD/BIAS circuits: Operating. *2*3
VDD = 1.8 to 3.6V
1
%/C
A
A
A
A
mA
1
* : CPU operating rate is 100% (No HALT state).
2
* : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz,
Bias voltage multiplying clock: 1/128 LSCLK (256Hz)
3
* : Use 32.768KHz Crystal Resonator DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.)
4
* : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
5
* : Significant bits of BLKCON0~BLKCON4 registers are all “1”.
24/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
DC CHARACTERISTICS (4/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,unless otherwise
specified) (4/5)
Measuring
Rating
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
VDD


IOH1 = 0.5mA, VDD = 1.8 to 3.6V
0.5
Output voltage 1
VDD
nd
VOH1


IOH1 = -0.1mA, VDD = 1.3 to 3.6V
(P20–P22/2
0.3
function is
VDD
IOH1 = -0.03mA, VDD = 1.1 to 3.6V


selected)
0.3
(P30–P36)
IOL1 = +0.5mA, VDD = 1.8 to 3.6V


0.5
(P40–P47)
IOL1
=
+0.1mA,
V
=
1.3
to
3.6V


0.5
DD
(PA0–PA5)
VOL1
IOL1 = +0.03mA, VDD = 1.1 to 3.6V


0.3
IOH1 = 0.5mA, VDD = 1.8 to 3.6V
Output voltage 2
nd
(P20–P22/2
function is Not
selected)
Output voltage 3
(P40–P41)
Output voltage 4
(COM0–23)
(SEG0–63)
Output leakage
(P20–P22)
(P30–P35)
(P40–P47)
(PA0–PA5)
VOH2
IOH1 = -0.03mA, VDD = 1.1 to 3.6V
Input current 1
(TEST)





IOL2 = +5mA, VDD = 1.8 to 3.6V


0.5
VOL3
IOL3 = +3mA, VDD = 2.0 to 3.6V
2
(when I C mode is selected)


0.4
VOH4
IOH4 = 0.2mA, VL1=1.2V
VL4
0.2


VOMH4
IOMH4 = +0.2mA, VL1=1.2V


VL3
+0.2
VOMH4S
IOMH4S = 0.2mA, VL1=1.2V
VL3
0.2


VOM4
IOM4 = +0.2mA, VL1=1.2V


VL2
+0.2
VOM4S
IOM4S = 0.2mA, VL1=1.2V
VL2
0.2


VOML4
IOML4 = +0.2mA, VL1=1.2V


VL1
+0.2
VOML4S
IOML4S = 0.2mA, VL1=1.2V
VL1
0.2


VOL4
IOL4 = +0.2mA, VL1=1.2V


0.2
IOOH
VOH = VDD (in high-impedance state)


1
IOOL
IIL1
IIH1
IIL1
Input current 2
(NMI)
(P00–P03)
(P04–P07)

VOL2
IIH1
Input current 1
(RESET_N)
IOH1 = -0.1mA, VDD = 1.3 to 3.6V
VDD
0.5
VDD
0.3
VDD
0.3
1


0
600
600
600
20
10
2
-1

300
300
300
300
300
300

1
20
-10
-2
600
600
600

VDD = 1.8 to 3.6V
2
30
200
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
0.2
0.01
200
30
30
30
200
200
2
VOL = VSS (in high-impedance state)
VIH1 = VDD
VDD = 1.8 to 3.6V
VIL1 = VSS
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
VIH1 = VDD
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VIL1 = Vss
IIH2
VIH2 = VDD
(when pulled-down)
IIL2
VIL2 = VSS
V
2
A
3
A
4
25/36
FEDL610Q439-3
LAPIS Semiconductor
(P10–P11)
(P30–P35)
(P40–P47)
(PA0–PA5)
ML610Q438/ML610Q439
(when pulled-up)
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
200
200
30
30
-0.2
-0.01
IIH2Z
VIH2 = VDD (in high-impedance state)


1
IIL2Z
VIL2 = VSS (in high-impedance state)
1


DC CHARACTERISTICS (5/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P
version,unless otherwise specified) (5/5)
Rating
Measuring
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
Input voltage 1
(RESET_N)
(TEST)
(NMI)
(P00–P03)
(P04–P07)
(P10–P11)
(P31–P35)
(P40–P43)
(P45–P47)
(PA0–PA5)
Hysteresis width
(RESET_N)
(TEST)
(NMI)
(P00–P03)
(P04–P07)
(P10–P11)
(P31–P35)
(P40–P43)
(P45–P47)
(PA0–PA5)
Input voltage 2
(P30, P44)
Input pin
capacitance
(NMI)
(P00–P03)
(P04–P07)
(P10–P11)
(P30–P35)
(P40–P47)
(PA0–PA5)
VDD = 1.3 to 3.6V
0.7
VDD

VDD
VDD = 1.1 to 3.6V
0.7
VDD

VDD
VDD = 1.3 to 3.6V
0

0.3
VDD
VDD = 1.1 to 3.6V
0

0.2
VDD
VDD = 2.0 to 3.6V
0.05
VDD
0.18
VDD
0.4
VDD
VDD = 1.1 to 3.6V
0.02
VDD
0.18
VDD
0.4
VDD
VIH2

0.7
VDD

VDD
VIL2

0

0.3
VDD
CIN
f = 10kHz
Vrms = 50mV
Ta = 25C


5
VIH1
VIL1
V
5
pF

VT
HYSTERESIS WIDTH
VT
Input signal
VDD
VSS
Internal signal
VDDL
VSS
26/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
MEASURING CIRCUITS
MEASURING CIRCUIT 1
XT0
C4
XT1
C3
C2
C34
32.768kHz crystal
CGH
P10/OSC0
C12
C1
CDH
CV:
CL0:
CL1:
CX:
Ca,Cb,Cc,Cd:
C12,C34:
CGH:
CDH:
P11/OSC1
4.096MHz
crystal
VDD AVDD VREFVDDL
VDDX VL1 VL2 VL3 VL4 VSS AVSS
A
CV
CL1 CL0 CX Ca Cb Cc Cd
1F
1F
0.1F
0.1F
1F
1F
24pF
24pF
32.768KHz Crystal Resonator :
DT-26 (Load capacitance 6pF)
(KDS: DAISHINKU CORP.)
4.096MHz crystal:
HC49SFWB (Kyocera)
MEASURING CIRCUIT 2
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL VDDX VL1
VL2
VL3
V
VL4 AVDDVREF VSSAVSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
27/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
MEASURING CIRCUIT 3
(*2)
VIL
Input pins
RS1
Output pins
VIH
VDD VDDL VDDX VL1
VL2
VL3
A
VL4 AVDDVREF VSSAVSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
MEASURING CIRCUIT 4
Input pins
Output pins
(*3)
A
VDD VDDL VDDX VL1
VL2
VL3
VL4 AVDD VREF VSSAVSS
*3: Measured at the specified output pins.
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL VDDX VL1
VL2
VL3
Waveform monitoring
MEASURING CIRCUIT 5
VL4 AVDDVREF VSSAVSS
*1: Input logic circuit to determine the specified measuring conditions.
28/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
AC CHARACTERISTICS (External Interrupt)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,
unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
External interrupt disable period
TNUL
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
System clock: 32.768kHz

76.8
106.8
s
P00–P07
(Rising-edge interrupt)
tNUL
P00–P07
(Falling-edge interrupt)
tNUL
NMI, P00–P07
(Both-edge interrupt)
tNUL
AC CHARACTERISTICS (UART)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,
unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Transmit baud rate

tTBRT

1
BRT*
1

s
1
BRT*
BRT*
1
BRT*
s
3%
+3%
*1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H)
and the UART mode register 0 (UA0MOD0).
Receive baud rate

tRBRT
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
29/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
AC CHARACTERISTICS (Synchronous Serial Port)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,
unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
When high-speed oscillation is
10


s
not active
SCLK input cycle
tSCYC
(slave mode)
When high-speed oscillation is
1


s
active (VDD = 1.8 to 3.6V)
SCLK output cycle
1


SCLK*

s
tSCYC
(master mode)
When high-speed oscillation is
4


s
not active
SCLK input pulse width
tSW
(slave mode)
When high-speed oscillation is
0.4


s
active (VDD = 1.8 to 3.6V)
1
1
1
SCLK*
SCLK*
SCLK*
SCLK output pulse width
s

tSW
(master mode)
0.5
0.4
0.6
SOUT output delay time
tSD



180
ns
(slave mode)
SOUT output delay time



80
ns
tSD
(master mode)
SIN input
setup time
tSS

80


ns
(slave mode)
SIN input
setup time

180


ns
tSS
(master mode)
SIN input
tSH

80


ns
hold time
*1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
tSCYC
tSW
tSW
SCLK0*
tSD
tSD
SOUT0*
tSS
tSH
SIN0*
*: Indicates the secondary function of the port.
30/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,
unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
SCL clock frequency
fSCL

0

100
kHz
SCL hold time

4.0


s
tHD:STA
(start/restart condition)
SCL ”L” level time
tLOW

4.7


s
SCL ”H” level time

4.0


s
tHIGH
SCL setup time
tSU:STA

4.7


s
(restart condition)
SDA hold time
tHD:DAT

0

3.45
s
SDA setup time

0.25


s
tSU:DAT
SDA setup time

4.0


s
tSU:STO
(stop condition)
Bus-free time
tBUF

4.7


s
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,
unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
SCL clock frequency
fSCL

0

400
kHz
SCL hold time
tHD:STA

0.6


s
(start/restart condition)
SCL ”L” level time

1.3


s
tLOW
SCL ”H” level time
tHIGH

0.6


s
SCL setup time
tSU:STA

0.6


s
(restart condition)
SDA hold time
tHD:DAT

0

0.9
s
SDA setup time
tSU:DAT

0.1


s
SDA setup time
tSU:STO

0.6


s
(stop condition)
Bus-free time

1.3


s
tBUF
Start
condition
Restart
condition
Stop
condition
P40/SDA
P41/SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
31/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
AC CHARACTERISTICS (RC Oscillation A/D Converter)
(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,
unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
RS0, RS1,
Resistors for oscillation
RT0,
CS0, CT0, CS1  740pF
1


k
RT0-1,RT1
fOSC1
Resistor for oscillation = 1k
209.4
330.6
435.1
kHz
Oscillation frequency
55.27
64.16
41.29
f
Resistor
for
oscillation
=
10k
kHz
OSC2
VDD = 1.5V
5.97
7.06
4.71
fOSC3
Resistor for oscillation = 100k
kHz
5.982
6.225
RT0,
RT0-1,
RT1
=
1kHz
5.567
Kf1

RS to RT oscillation frequency
1
1.01
ratio *1
RT0, RT0-1, RT1 = 10 kHz
0.99
Kf2

VDD = 1.5V
0.108
0.118
RT0, RT0-1, RT1 = 100 kHz
0.104
Kf3

fOSC1
fOSC2
fOSC3
Kf1
Kf2
Kf3
Oscillation frequency
VDD = 3.0V
RS to RT oscillation frequency
ratio *1
VDD = 3.0V
Resistor for oscillation = 1k
Resistor for oscillation = 10k
Resistor for oscillation = 100k
RT0, RT0-1, RT1 = 1kHz
RT0, RT0-1, RT1 = 10 kHz
RT0, RT0-1, RT1 = 100 kHz
407.3
49.76
5.04
8.006
0.99
0.100
486.7
59.28
5.993
8.210
1
0.108
594.6
72.76
7.04
8.416
1.01
0.115
kHz
kHz
kHz



*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same
conditions.
fOSCX(RT0-1CS0 oscillation)
fOSCX(RS0CS0 oscillation)
,
IN0 CS0 RCT0
(*1)
VIL
*1: Input logic circuit to
determine the specified
measuring conditions.
VDDL
fOSCX(RT1CS1 oscillation)
fOSCX(RS1CS1 oscillation)
VDDX
RT0, RT0-1, RT1: 1k /10k/100k
RS0, RS1: 10k
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN1 CS1 RS1 RT1
RCM
VDD
CV
RT1
RT0
RS0
RS0 RT0
Input pins
VIH
,
CVR1
RI0-1
CT0
CS0
CVR0
RS1
fOSCX(RT0CS0 oscillation)
fOSCX(RS0CS0 oscillation)
(x = 1, 2, 3)
CS1
Kfx =
Frequency measurement
(fOSCX)
VSS
CL1 CL0 CX
Note:
- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors
and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling
capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise
around the node.
- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to
the signal.
- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved
components may affect to the A/D conversion operation by noise the components itself may have.
32/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
Electrical Characteristics of Successive Approximation Type A/D Converter
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version,
unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Resolution
n



12
bit
2.7V  VREF  3.6V
4

+4
Integral non-linearity error
IDL
2.2V  VREF  2.7V
6

+6
2.7V  VREF  3.6V
3

+3
Differential non-linearity error
LSB
DNL
2.2V  VREF  2.7V
5

+5
Zero-scale error
VOFF

6

+6
Full-scale error
FSE

6

+6
Reference voltage

2.2

AVDD
V
VREF
SACK = 0

25

(HSCLK = 375kHz to 625kHz)
Conversion time
/CH
tCONV
SACK = 1

112

(HSCLK = 1.5MHz to 4.2MHz)
: Period of high-speed clock (HSCLK)
AVDD
Reference
voltage
VREF
VDD
VDDL
10F
1F
A
0.1F

1F
RI5k
+
Analog input
0.1F
VDDX
AIN0,
AIN1
0.1F
VSS
AVSS
33/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
Package Dimensions
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number,
package code and desired mounting conditions (reflow method, temperature and times).
34/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
Revision History
Document No.
FEDL610Q439-01
FEDL610Q439-02
FEDL610Q439-03
Date
Aug. 24,2010
Feb. 2,2011
Jun. 7,2011
Page
Previous Current
Edition
Edition
–
34
3
–
34
3
Description
Formally edition 1.0
Change of a Package Dimensions
Add the P persion
35/36
FEDL610Q439-3
LAPIS Semiconductor
ML610Q438/ML610Q439
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor
Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If
you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS
Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage
and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass
production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any
damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for
such damage.
The technical information specified herein is intended only to show the typical functions of and examples of application
circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise
intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no
responsibility whatsoever for any dispute arising from the use of such technical information.
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While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail
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Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of
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The Products are not designed or manufactured to be used with any equipment, device or system which requires an
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Copyright
2010 - 2011 LAPIS Semiconductor Co., Ltd.
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