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Freescale Semiconductor
Data Sheet: Technical Data
Document Number S9KEA128P80M48SF0
Rev 4, 09/2014
S9KEA128P80M48SF0
KEA128 Sub-Family Data
Sheet
Supports the following:
S9KEAZ64AMLK(R),
S9KEAZ128AMLK(R),
S9KEAZ64AVLK(R),
S9KEAZ128AVLK(R),
S9KEAZ64ACLK(R),
S9KEAZ128ACLK(R),
S9KEAZ64AMLH(R),
S9KEAZ128AMLH(R),
S9KEAZ64AVLH(R),
S9KEAZ128AVLH(R),
S9KEAZ64ACLH(R) and
S9KEAZ128ACLH(R)
Key features
• Operating characteristics
– Voltage range: 2.7 to 5.5 V
– Flash write voltage range: 2.7 to 5.5 V
– Temperature range (ambient): -40 to 125°C
• Performance
– Up to 48 MHz ARM® Cortex-M0+ core
– Single cycle 32-bit x 32-bit multiplier
– Single cycle I/O access port
• Memories and memory interfaces
– Up to 128 KB flash
– Up to 16 KB RAM
• Clocks
– Oscillator (OSC) - supports 32.768 kHz crystal or 4
MHz to 24 MHz crystal or ceramic resonator; choice of low power or high gain oscillators
– Internal clock source (ICS) - internal FLL with internal or external reference, 37.5 kHz pre-trimmed internal reference for 48 MHz system clock
– Internal 1 kHz low-power oscillator (LPO)
• System peripherals
– Power management module (PMC) with three power modes: Run, Wait, Stop
– Low-voltage detection (LVD) with reset or interrupt, selectable trip points
– Watchdog with independent clock source (WDOG)
– Programmable cyclic redundancy check module
(CRC)
– Serial wire debug interface (SWD)
– Aliased SRAM bitband region (BIT-BAND)
– Bit manipulation engine (BME)
• Security and integrity modules
– 80-bit unique identification (ID) number per chip
• Human-machine interface
– Up to 71 general-purpose input/output (GPIO)
– Two 32-bit keyboard interrupt modules (KBI)
– External interrupt (IRQ)
• Analog modules
– One up to 16-channel 12-bit SAR ADC, operation in
Stop mode, optional hardware trigger (ADC)
– Two analog comparators containing a 6-bit DAC and programmable reference input (ACMP)
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
© 2014 Freescale Semiconductor, Inc.
• Timers
– One 6-channel FlexTimer/PWM (FTM)
– Two 2-channel FlexTimer/PWM (FTM)
– One 2-channel periodic interrupt timer (PIT)
– One pulse width timer (PWT)
– One real-time clock (RTC)
• Communication interfaces
– Two SPI modules (SPI)
– Up to three UART modules (UART)
– Two I2C modules (I2C)
– One MSCAN module (MSCAN)
• Package options
– 80-pin LQFP
– 64-pin LQFP
2
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
Table of Contents
FTM module timing....................................................... 16
1.1 Determining valid orderable parts............................................... 4
2.1 Description...................................................................................4
2.4 Example....................................................................................... 5
3.1 Thermal handling ratings............................................................. 5
3.2 Moisture handling ratings............................................................ 5
3.3 ESD handling ratings................................................................... 6
3.4 Voltage and current operating ratings..........................................6
4.1 Nonswitching electrical specifications........................................ 7
DC characteristics.......................................................... 7
Supply current characteristics........................................ 13
EMC performance..........................................................15
4.2 Switching specifications.............................................................. 15
Control timing................................................................ 15
4.3 Thermal specifications.................................................................17
Thermal characteristics.................................................. 17
5 Peripheral operating requirements and behaviors................................ 19
5.1 Core modules............................................................................... 19
SWD electricals .............................................................19
5.2 External oscillator (OSC) and ICS characteristics.......................20
5.3 NVM specifications..................................................................... 22
ADC characteristics....................................................... 23
Analog comparator (ACMP) electricals.........................25
5.5 Communication interfaces........................................................... 26
SPI switching specifications.......................................... 26
MSCAN......................................................................... 29
6.1 Obtaining package dimensions.................................................... 29
7.1 Signal multiplexing and pin assignments.................................... 30
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to
freescale.com
and perform a part number search for the following device numbers: KEAZ128.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q B KEA A C FFF M T PP N
4
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid):
Field
Q
B
KEA
A
C
Description
Qualification status
Memory type
Kinetis Auto family
Key attribute
CAN availability
Values
• S = Automotive qualified
• P = Prequalification
• 9 = Flash
• KEA
• Z = M0+ core
• F = M4 W/ DSP & FPU
• C= M4 W/ AP + FPU
• N = CAN not available
• (Blank) = CAN available
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
Field
FFF
M
T
PP
N
Description
Program flash memory size
Maskset revision
Temperature range (°C)
Package identifier
Packaging type
Values
• 128 = 128 KB
• A = 1 st
Fab version
• B = Revision after 1 st
version
• C = –40 to 85
• V= –40 to 105
• M = –40 to 125
• LH = 64 LQFP (10 mm x 10 mm)
• LK = 80 LQFP (14 mm x 14 mm)
• R = Tape and reel
• (Blank) = Trays
Ratings
2.4 Example
This is an example part number:
S9KEAZ128AMLK
3 Ratings
3.1 Thermal handling ratings
Symbol Description
T
STG
T
SDR
Storage temperature
Solder temperature, lead-free
Min.
–55
—
Max.
150
260
Unit
°C
°C
Notes
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
3.2 Moisture handling ratings
Symbol Description
MSL Moisture sensitivity level
Min.
—
Max.
3
Unit
—
Notes
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
5
Ratings
3.3 ESD handling ratings
Symbol Description
V
HBM
V
CDM
I
LAT
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of °C
Min.
–6000
–500
–100
Max.
+6000
+500
+100
Unit
V
V mA
Notes
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test. The test produced the following results:
• Test was performed at 125 °C case temperature (Class II).
• I/O pins pass +100/-100 mA I-test with I
DD
• I/O pins pass +50/-100 mA I-test with I
DD
.
current limit at 400 mA (V
DD
collapsed during positive injection).
current limit at 1000 mA for V
DD
.
• Supply groups pass 1.5 V ccmax
• RESET_B pin was only tested with negative I-test due to product conditioning requirement.
6
3.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V
SS associated with the pin is enabled.
or V
DD
) or the programmable pullup resistor
Symbol
V
DD
I
DD
V
IN
I
D
V
DDA
Table 1. Voltage and current operating ratings
Description
Digital supply voltage
Maximum current into V
DD
Input voltage except true open drain pins
Input voltage of true open drain pins
Instantaneous maximum current single pin limit (applies to all port pins)
Analog supply voltage
Min.
–0.3
—
–0.3
–0.3
–25
V
DD
– 0.3
Max.
6.0
120
V
DD
6
25
V
DD
+ 0.3
Unit
V mA
V
V mA
V
1. Maximum rating of V
DD
also applies to V
IN
.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
General
4 General
4.1
Nonswitching electrical specifications
4.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Symbol
—
V
OH
I
OHT
V
OL
I
OLT
V
IH
V
IL
V hys
|I
In
|
Table 2. DC characteristics
Output high voltage
Descriptions
Operating voltage
All I/O pins, except PTA2 and PTA3, standard-drive strength
High current drive pins, high-drive strength
Output high current
Output low voltage
Output low current
Input high voltage
Input low voltage
Max total I
OH
for all ports
All I/O pins, standard-drive strength
High current drive pins, high-drive strength
Max total I
OL
for all ports
All digital inputs
All digital inputs
—
5 V, I load
= –5 mA
3 V, I load
= –2.5 mA
5 V, I load
= –20 mA
3 V, I load
= –10 mA
5 V
3 V
5 V, I load
= 5 mA
3 V, I load
= 2.5 mA
5 V, I load
=20 mA
3 V, I load
= 10 mA
5 V
3 V
4.5≤V
DD
<5.5 V
2.7≤V
DD
<4.5 V
4.5≤V
DD
<5.5 V
Min
2.7
V
DD
– 0.8
V
DD
– 0.8
V
DD
– 0.8
V
DD
– 0.8
—
—
—
—
—
—
—
—
0.65 × V
DD
0.70 × V
DD
—
2.7≤V
DD
<4.5 V —
Input hysteresis
Input leakage current
All digital inputs
Per pin (pins in high impedance input mode)
—
V
IN
= V
DD
or V
SS
0.06 × V
DD
—
Typical
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.1
Max
5.5
—
—
—
—
–100
–60
0.8
0.8
0.8
0.8
100
60
—
—
0.35 ×
V
DD
0.30 ×
V
DD
—
1
Table continues on the next page...
Unit
V
V
V
V
V mA
V
V
V
V mA mV
µA
V
V
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
7
Nonswitching electrical specifications
Table 2. DC characteristics (continued)
Symbol
|I
INTOT
|
R
PU
R
PU
I
IC
C
In
V
RAM
Total leakage combined for all port pins
Pullup resistors
Descriptions
Pullup resistors
DC injection
,
,
Pins in high impedance input mode
All digital inputs, when enabled (all I/O pins other than PTA2 and PTA3)
PTA2 and PTA3 pins
Single pin limit
Total MCU limit, includes sum of all stressed pins
Input capacitance, all pins
RAM retention voltage
V
IN
= V
DD
or V
SS
—
—
V
IN
< V
SS
, V
IN
> V
DD
—
—
Min
—
30.0
30.0
-2
-5
—
2.0
Typical
—
—
—
—
—
—
—
Max
2
50.0
60.0
2
25
7
—
Unit
µA kΩ kΩ mA pF
V
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support high current output.
3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin.
4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to V
SS open drain I/O pins that are internally clamped to V
SS
.
and V
DD
. PTA2 and PTA3 are true
5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger value.
6. Power supply must maintain regulation within operating V conditions. If the positive injection current (V
In
> V
DD
DD
range during instantaneous and operating maximum current
) is higher than I
DD
, the injection current may flow out of V result in external power supply going out of regulation. Ensure that external V
DD
DD
and could
load will shunt current higher than maximum injection current when the MCU is not consuming power, such as when no system clock is present, or clock rate is very low (which would reduce overall power consumption).
Symbol
V
POR
V
LVDH
V
LVW1H
V
LVW2H
V
LVW3H
V
LVW4H
V
HYSH
Table 3. LVD and POR specification
Description
Falling low-voltage detect threshold—high range (LVDV =
Falling lowvoltage warning threshold— high range
Level 1 falling
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
Level 4 falling
(LVWV = 11)
High range low-voltage detect/ warning hysteresis
Min
1.5
4.2
4.3
4.5
4.6
4.7
—
Typ
1.75
4.3
4.4
4.5
4.6
4.7
100
Table continues on the next page...
Max
2.0
4.4
4.5
4.6
4.7
4.8
—
Unit
V
V
V
V
V
V mV
8
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
Symbol
V
LVDL
V
LVW1L
V
LVW2L
V
LVW3L
V
LVW4L
V
HYSDL
V
HYSWL
V
BG
Nonswitching electrical specifications
Table 3. LVD and POR specification (continued)
Description
Falling low-voltage detect threshold—low range (LVDV = 0)
Falling lowvoltage warning threshold—low range
Level 1 falling
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
Level 4 falling
(LVWV = 11)
Low range low-voltage detect hysteresis
Low range low-voltage warning hysteresis
1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at V
DD
= 5.0 V, Temp = 125 °C
Min
2.56
2.62
2.72
2.82
2.92
—
—
1.14
Typ
2.61
2.7
2.8
2.9
3.0
40
80
1.16
Max
2.66
2.78
2.88
2.98
3.08
—
—
1.18
Unit
V
V
V
V
V mV mV
V
V
DD
-V
OH
(V)
I
OH
(mA)
Figure 1. Typical V
DD
-V
OH
Vs. I
OH
(standard drive strength) (V
DD
= 5 V)
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
9
Nonswitching electrical specifications
V
DD
-V
OH
(V)
I
OH
(mA)
Figure 2. Typical V
DD
-V
OH
Vs. I
OH
(standard drive strength) (V
DD
= 3 V)
V
DD
-V
OH
(V)
I
OH
(mA)
Figure 3. Typical V
DD
-V
OH
Vs. I
OH
(high drive strength) (V
DD
= 5 V)
10
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
V
DD
-V
OH
(V)
I
OH
(mA)
Figure 4. Typical V
DD
-V
OH
Vs. I
OH
(high drive strength) (V
DD
= 3 V)
V
OL
(V)
I
OL
(mA)
Figure 5. Typical V
OL
Vs. I
OL
(standard drive strength) (V
DD
= 5 V)
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
11
Nonswitching electrical specifications
V
OL
(V)
I
OL
(mA)
Figure 6. Typical V
OL
Vs. I
OL
(standard drive strength) (V
DD
= 3 V)
V
OL
(V)
12
I
OL
(mA)
Figure 7. Typical V
OL
Vs. I
OL
(high drive strength) (V
DD
= 5 V)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
V
OL
(V)
I
OL
(mA)
Figure 8. Typical V
OL
Vs. I
OL
(high drive strength) (V
DD
= 3 V)
4.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Parameter
Run supply current FEI mode, all modules clocks enabled; run from flash
Run supply current FEI mode, all modules clocks disabled and gated; run from flash
Table 4. Supply current characteristics
Symbol
RI
DD
RI
DD
Core/Bus
Freq
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
V
DD
(V)
5
3
5
7.9
4.9
2.3
7.8
5.5
3.8
2.3
11.1
8
5
2.4
11
Max
—
—
—
—
—
—
—
—
—
—
—
—
Table continues on the next page...
Unit
mA mA
Temp
-40 to 125 °C
-40 to 125 °C
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
13
Nonswitching electrical specifications
Table 4. Supply current characteristics (continued)
Parameter Symbol V
DD
(V)
Max
Run supply current FBE mode, all modules clocks enabled; run from RAM
Run supply current FBE mode, all modules clocks disabled and gated; run from
RAM
Wait mode current FEI mode, all modules clocks enabled
RI
DD
RI
DD
WI
DD
SI
DD
Core/Bus
Freq
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
—
—
3
5
3
5
3
5
3
5
3
Stop mode supply current no clocks active (except 1 kHz
ADC adder to Stop
ADLPC = 1
ADLSMP = 1
ADCO = 1
MODE = 10B
ADICLK = 11B
ACMP adder to Stop
—
—
— 5
3
2.4
8.3
6.4
4.2
2.2
8.4
6.5
4.3
2.3
11.4
7.7
4.7
2.3
11.3
7.6
4.6
2.3
2
1.9
7.7
5.4
3.7
2.2
14.7
9.8
6
2.4
14.6
9.6
5.9
86
82
— 5
3
12
12
Table continues on the next page...
—
—
—
—
—
—
—
—
—
12.5
—
—
—
—
—
—
—
—
—
14.9
—
—
—
12.8
—
—
—
—
—
Unit
mA mA mA
µA
µA
µA
Temp
-40 to 125 °C
-40 to 125 °C
-40 to 125 °C
-40 to 125 °C
-40 to 125 °C
-40 to 125 °C
-40 to 125 °C
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
14 Freescale Semiconductor, Inc.
Parameter
LVD adder to Stop
Table 4. Supply current characteristics (continued)
Switching specifications
Symbol
—
Core/Bus
Freq
—
V
DD
(V)
5
3
130
125
Max
—
—
Unit
µA
Temp
-40 to 125 °C
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. The high current is observed at high temperature.
3. RTC adder cause <1 µA I
DD
increase typically, RTC clock source is 1 kHz LPO clock.
4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
4.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation play a significant role in EMC performance. The system designer must consult the following Freescale applications notes, available on
freescale.com
for advice and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
4.2
Switching specifications
4.2.1 Control timing
Table 5. Control timing
Num Rating
1 System and core clock
2 Bus frequency (t cyc
= 1/f
Bus
)
3 Internal low power oscillator frequency
4
Symbol
f
Sys f
Bus f
LPO t extrst
Min
DC
DC
0.67
1.5 × t cyc
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
—
—
1.0
—
Max
48
24
1.25
—
Unit
MHz
MHz
KHz ns
15
Switching specifications
Num
5 Reset low drive
6 IRQ pulse width
Rating
7
8
Keyboard interrupt pulse width
Synchronous path
Synchronous path
— Port rise and fall time -
Normal drive strength (load
= 50 pF)
Port rise and fall time - high drive strength (load = 50 pF)
—
Symbol
t rstdrv t
ILIH t
IHIL t
ILIH t
IHIL t
Rise t
Fall t
Rise t
Fall
Min
34 × t cyc
100
1.5 × t cyc
100
1.5 × t cyc
—
—
—
—
—
—
—
—
—
10.2
9.5
5.4
4.6
1. Typical values are based on characterization data at V
DD
= 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
4. Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range -40 °C to 125 °C.
t extrst
RESET_b pin
Max
—
—
—
—
—
—
—
—
—
KBIPx
Figure 9. Reset timing
t
IHIL
Unit
ns ns ns ns ns ns ns ns ns
IRQ/KBIPx t
ILIH
Figure 10. KBIPx timing
4.2.2 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Function
Timer clock frequency
External clock frequency
Symbol
f
Timer f
TCLK
Table 6. FTM input timing
Min
f
Bus
0
Max
f
Sys f
Timer
/4
Unit
Hz
Hz
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
16 Freescale Semiconductor, Inc.
Function
External clock period
External clock high time
External clock low time
Input capture pulse width
Table 6. FTM input timing (continued)
Symbol
t
TCLK t clkh t clkl t
ICPW
Min
4
1.5
1.5
1.5
Max
—
—
—
—
Thermal specifications
Unit
t cyc t cyc t cyc t cyc t
TCLK t clkh
TCLK t clkl
Figure 11. Timer external clock
t
ICPW
FTMCHn
FTMCHn t
ICPW
Figure 12. Timer input capture pulse
4.3
Thermal specifications
4.3.1 Thermal characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To take P
I/O
into account in power calculations, determine the difference between actual pin voltage and V
SS
or V
DD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and V
SS small.
or V
DD
will be very
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
17
Thermal specifications
Board type
Single-layer (1S)
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
—
—
—
Table 7. Thermal attributes
Symbol
R
R
R
θJA
θJA
θJMA
Description
Thermal resistance, junction to ambient (natural convection)
Thermal resistance, junction to ambient (natural convection)
Thermal resistance, junction to ambient (200 ft./min. air speed)
R
θJMA
Thermal resistance, junction to ambient (200 ft./min. air speed)
R
θJB
Thermal resistance, junction to board
R
θJC
Ψ
JT
Thermal resistance, junction to case
Thermal characterization parameter, junction to package top outside center (natural convection)
64 LQFP 80 LQFP
71 57
53
59
46
35
20
5
44
47
38
28
15
3
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
The average chip-junction temperature (T
J
) in °C can be obtained from:
T
J
= T
A
+ (P
D
×
θ
JA
)
Where:
T
A
= Ambient temperature, °C
θ
JA
= Package thermal resistance, junction-to-ambient, °C/W
P
D
= P int
+ P
I/O
P int
= I
DD
× V
DD
, Watts - chip internal power
P
I/O
= Power dissipation on input and output pins - user determined
For most applications, P
I/O between P
D
and T
J
(if P
I/O
<< P int
and can be neglected. An approximate relationship
is neglected) is:
P
D
= K ÷ (T
J
+ 273 °C)
Solving the equations above for K gives:
K = P
D
× (T
A
+ 273 °C) +
θ
JA
× (P
D
)
2
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
18 Freescale Semiconductor, Inc.
Notes
,
,
,
,
Peripheral operating requirements and behaviors
where K is a constant pertaining to the particular part. K can be determined by measuring
P
D
(at equilibrium) for an known T
A
. Using this value of K, the values of P be obtained by solving the above equations iteratively for any value of T
A
.
D
and T
J
can
5 Peripheral operating requirements and behaviors
5.1 Core modules
5.1.1 SWD electricals
Table 8. SWD full voltage range electricals
Symbol
J1
Description
Operating voltage
SWD_CLK frequency of operation
• Serial wire debug
Min.
2.7
0
J2
J3
J4
J9
J10
J11
J12
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
SWD_CLK rise and fall times
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
1/J1
20
—
10
3
—
5
—
—
3
—
—
35
—
Max.
5.5
24
J2
J3 J3
SWD_CLK (input)
J4 J4
Figure 13. Serial wire clock input timing
ns ns ns ns ns ns ns
Unit
V
MHz
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
19
Peripheral operating requirements and behaviors
SWD_CLK
SWD_DIO
SWD_DIO
J11
J12
SWD_DIO
SWD_DIO
J11
J9
J10
Input data valid
Output data valid
Output data valid
Figure 14. Serial wire data timing
5.2 External oscillator (OSC) and ICS characteristics
Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient)
Num
1
2
3
4
5
Crystal or resonator frequency
Characteristic
Low range (RANGE = 0)
High range (RANGE = 1)
Feedback resistor
Series resistor -
Low Frequency
Series resistor -
High Frequency
Series resistor -
High Frequency,
High-Gain Mode
Load capacitors
Low Frequency, Low-Power
Low Frequency, High-Gain
Mode
High Frequency, Low-Power
Mode
High Frequency, High-Gain
Mode
Low-Power Mode
High-Gain Mode
Low-Power Mode
4 MHz
8 MHz
Symbol
f lo f hi
C1, C2
R
F
R
S
R
S
Min
31.25
4
—
—
—
—
—
—
—
—
—
Typical
32.768
—
—
10
1
1
0
200
0
0
0
Max
39.0625
24
—
—
—
—
—
—
—
—
—
Unit
kHz
MHz
MΩ
MΩ
MΩ
MΩ kΩ kΩ kΩ kΩ kΩ
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
20 Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient) (continued)
Num Characteristic
16 MHz
6
7
8
9
10
Crystal start-up time low range =
32.768 kHz crystal; High range = 20 MHz
Low range, low power
Low range, high gain
High range, low power
High range, high gain
Internal reference start-up time
Internal reference clock (IRC) frequency trim range
T = 125 °C, V
DD
= 5 V Internal reference clock frequency, factory trimmed
,
DCO output frequency range
FLL reference = fint_t, flo, or fhi/RDIV
11 Factory trimmed internal oscillator accuracy
12 Deviation of IRC over temperature when trimmed at
T = 25 °C, V
DD
=
5 V
13
14
15
T = 125 °C, V
Long term jitter of DCO output clock (averaged over 2 ms interval)
DD
= 5 V
Over temperature range from
-40 °C to 125°C
Frequency accuracy of DCO output using factory trim value
Over temperature range from
-40 °C to 125°C
FLL acquisition time
Symbol
t
CSTL t
CSTH t
IRST f int_t f int_ft f dco
Δf int_ft
Δf int_t
Δf dco_ft t
Acquire
C
Jitter
Min
—
—
—
—
—
—
31.25
—
40
-0.8
-1
-2.3
—
—
Typical
0
1000
800
3
1.5
20
—
37.5
—
—
—
—
—
0.02
Max
—
—
—
—
—
50
39.0625
—
50
0.8
0.8
0.8
2
0.2
Unit
kΩ ms ms ms ms
µs kHz kHz
MHz
%
%
% ms
%f dco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. See crystal or resonator manufacturer's recommendation.
3. Load capacitors (C
1
,C
2
), feedback resistor (R
F
) and series resistor (R
S
) are incorporated internally when RANGE = HGO =
0.
4. This parameter is characterized and not tested on each device.
5. Proper PC board layout procedures must be followed to achieve specifications.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V
DD for a given interval.
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
21
Peripheral operating requirements and behaviors
EXTAL
OSC
R
F
XTAL
R
S
Crystal or Resonator
C
1
C
2
Figure 15. Typical crystal or resonator circuit
5.3 NVM specifications
This section provides details about program/erase times and program/erase endurance for the flash memories.
Characteristic
Supply voltage for program/erase –40 °C to 125 °C
Supply voltage for read operation
NVM Bus frequency
NVM Operating frequency
Erase Verify All Blocks
Erase Verify Flash Block
Erase Verify Flash Section
Read Once
Program Flash (2 word)
Program Flash (4 word)
Program Once
Erase All Blocks
Erase Flash Block
Erase Flash Sector
Unsecure Flash
Verify Backdoor Access Key
Set User Margin Level
FLASH Program/erase endurance T
L
= -40 °C to 125 °C
to T
H
Table 10. Flash characteristics
Symbol
V prog/erase
2.7
—
V
Read f
NVMBUS f
NVMOP t
VFYALL t
RD1BLK t
RD1SEC t
RDONCE t
PGM2 t
PGM4 t
PGMONCE t
ERSALL t
ERSBLK t
ERSPG t
UNSECU t
VFYKEY t
MLOADU n
FLPE
0.12
0.21
0.20
95.42
95.42
19.10
95.42
—
—
10 k
—
—
—
—
2.7
1
0.8
0.13
0.21
0.21
100.18
100.18
20.05
100.19
—
—
100 k
—
—
—
—
—
—
1
Table continues on the next page...
Max
5.5
0.31
0.49
0.21
100.30
100.30
20.09
100.31
482
415
—
5.5
24
1.05
2605
2579
485
464
Unit
V
V
MHz
MHz t cyc t cyc t cyc t cyc ms ms ms ms ms ms ms t cyc t cyc
Cycles
22
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 10. Flash characteristics (continued)
Characteristic
Data retention at an average junction temperature of T
Javg
= 85°C after up to
10,000 program/erase cycles
Symbol
t
D_ret
15
100
Max
—
Unit
years
1. Minimum times are based on maximum f
NVMOP
and maximum f
NVMBUS
2. Typical times are based on typical f
NVMOP
and maximum f
NVMBUS
3. Maximum times are based on typical f
NVMOP
and typical f
NVMBUS
4. t cyc
= 1 / f
NVMBUS
plus aging
Program and erase operations do not require any special power sources other than the normal V
DD
supply. For more detailed information about program/erase operations, see the Flash Memory Module section in the reference manual.
5.4 Analog
5.4.1 ADC characteristics
Table 11. 5 V 12-bit ADC operating conditions
Conditions Symbol Min
Max Characteri stic
Reference potential
• Low
• High
Supply voltage
Absolute
Delta to V
DD
(V
DD
-V
DDA
)
V
REFL
V
REFH
V
DDA
ΔV
DDA
V
ADIN
V
SSA
V
DDA
/2
2.7
-100
V
REFL
—
—
—
0
—
V
DDA
/2
V
DDA
5.5
+100
V
REFH
Input voltage
Input capacitance
Input resistance
Analog source resistance
ADC conversion clock frequency
•
•
•
•
12-bit mode f
ADCK f
ADCK
> 4 MHz
< 4 MHz
10-bit mode f f
ADCK
> 4 MHz
ADCK
< 4 MHz
8-bit mode
(all valid f
ADCK
)
High speed (ADLPC=0)
Low power (ADLPC=1)
C
ADIN
R
ADIN
R
AS f
ADCK
—
—
—
—
—
—
—
0.4
0.4
4.5
3
—
—
—
—
—
—
—
5.5
5
5
10
10
2
5
8.0
4.0
MHz
Unit
V
V mV
V pF kΩ kΩ
Comment
—
—
—
—
—
—
External to
MCU
—
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
23
Peripheral operating requirements and behaviors
1. Typical values assume V
DDA
= 5.0 V, Temp = 25°C, f
ADCK
=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
R
AS
Z
AS v
ADIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad leakage due to input protection z
ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
R
ADIN
ADC SAR
ENGINE v
AS
C
AS
R
ADIN
INPUT PIN
R
ADIN
INPUT PIN
R
ADIN
INPUT PIN
C
ADIN
Figure 16. ADC input impedance equivalency diagram
Table 12. 12-bit ADC characteristics (V
REFH
= V
DDA
, V
REFL
= V
SSA
)
Characteristic Conditions Symbol Min
Max
I
DDA
— 133 — Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
Supply current Stop, reset, module off
I
DDA
I
DDA
I
DDA
I
DDA
—
—
—
—
218
327
582
0.011
—
—
990
1
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
24
Unit
µA
µA
µA
µA
µA
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. 12-bit ADC characteristics (V
REFH
= V
DDA
, V
REFL
= V
SSA
) (continued)
Characteristic
ADC asynchronous clock source
Conversion time
(including sample time)
Conditions
High speed (ADLPC =
0)
Low power (ADLPC =
1)
Short sample
(ADLSMP = 0)
Sample time
Long sample
(ADLSMP = 1)
Short sample
(ADLSMP = 0)
Total unadjusted Error
Long sample
(ADLSMP = 1)
12-bit mode
10-bit mode
8-bit mode
Differential Non-
Liniarity
12-bit mode
10-bit mode
8-bit mode
Integral Non-Linearity 12-bit mode
10-bit mode
8-bit mode
12-bit mode
10-bit mode
Quantization error
Input leakage error
Temp sensor slope
8-bit mode
12-bit mode
10-bit mode
8-bit mode
≤12 bit modes all modes
-40 °C–25 °C
25 °C–125 °C
Temp sensor voltage 25 °C
Symbol
f
ADACK t
ADC t
ADS
E
TUE
DNL
INL
E
ZS
E
FS
E
Q
E
IL m
V
TEMP25
Min
2
1.25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.3
2
20
40
3.5
23.5
±0.4
±0.15
±1.0
±0.2
±0.35
±2.5
±0.3
±0.25
±5.0
±1.5
±0.8
±1.5
±0.4
±0.15
±1.5
—
I
In
x R
AS
3.266
3.638
1.396
Max
5
3.3
—
—
—
—
—
—
—
—
—
—
—
—
±0.5
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ADCK cycles
ADCK cycles
LSB
LSB
LSB
LSB
LSB
LSB
mV mV/°C
V
1. Typical values assume V
DDA
= 5.0 V, Temp = 25 °C, f reference only and are not tested in production.
2. Includes quantization
3. 1 LSB = (V
REFH
- V
REFL
)/2
N
4. V
ADIN
= V
SSA
5. V
6. I
In
ADIN
= V
DDA
= leakage current (refer to DC characteristics)
ADCK
=1.0 MHz unless otherwise stated. Typical values are for
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
25
Peripheral operating requirements and behaviors
5.4.2 Analog comparator (ACMP) electricals
Table 13. Comparator electrical specifications
Characteristic
Supply voltage
Supply current (Operation mode)
Analog input voltage
Analog input offset voltage
Analog comparator hysteresis
(HYST=0)
Analog comparator hysteresis
(HYST=1)
Supply current (Off mode)
Propagation Delay
Symbol
V
DDA
I
DDA
V
AIN
V
AIO
V
H
V
H
I
DDAOFF t
D
Min
2.7
—
V
SS
- 0.3
—
—
—
—
—
Typical
—
10
—
—
15
20
60
0.4
Max
5.5
20
V
DDA
40
20
30
—
1
Unit
V
µA
V mV mV mV nA
µs
5.5 Communication interfaces
2
5
6
3
4
7
8
9
5.5.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20%
V
DD
and 80% V
DD
, unless noted, and 25 pF load on all SPI pins. All timing assumes slew rate control is disabled and high-drive strength is enabled for SPI output pins.
Symbol Description
Table 14. SPI master mode timing
Min.
Max.
Unit Comment Nu m.
1 f op
Frequency of operation f
Bus
/2048 f
Bus
/2 Hz t
SPSCK t
Lead t
Lag t
WSPSCK t
SU t
HI t v t
HO
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
2 x t
Bus
1/2
1/2 t
Bus
– 30
8
8
—
20
2048 x t
Bus
—
—
1024 x t
Bus
—
—
25
—
Table continues on the next page...
ns t
SPSCK t
SPSCK ns ns ns ns ns f
Bus
is the bus clock t
Bus
= 1/f
Bus
—
—
—
—
—
—
—
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
26 Freescale Semiconductor, Inc.
Nu m.
10
11
Peripheral operating requirements and behaviors
Table 14. SPI master mode timing (continued)
Symbol Description Min.
Max.
Unit Comment
t
RI t
FI t
RO t
FO
Rise time input
Fall time input
Rise time output
Fall time output
—
— t
Bus
– 25
25 ns ns
—
—
SS1
(OUTPUT)
3 2 10 11
SPSCK
(CPOL=0)
(OUTPUT)
5
5
10
11
SPSCK
(CPOL=1)
(OUTPUT)
6 7
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
9
4
SS1
(OUTPUT)
2
3 10 11 4
SPSCK
(CPOL=0)
(OUTPUT)
SPSCK
(CPOL=1)
(OUTPUT)
5 5
10 11
6 7
MISO
(INPUT)
MSB IN
2
BIT 6 . . . 1
MOSI
(OUTPUT)
8
PORT DATA MASTER MSB OUT
2
9
BIT 6 . . . 1
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
LSB IN
MASTER LSB OUT
Figure 18. SPI master mode timing (CPHA=1)
PORT DATA
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
27
38 <<CLASSIFICATION>>
<<NDA MESSAGE>>
Peripheral operating requirements and behaviors
Table 15. SPI slave mode timing
Nu m.
1
Symbol Description
f op
Frequency of operation
Min.
0
Max.
f
Bus
/4
9
10
11
12
6
7
8
4
5
2
3
13 t dis t v t
HO t
RI t
FI t
RO t
FO t
SPSCK t
Lead t
Lag t
WSPSCK t
SU t
HI t a
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
Fall time input
Rise time output
Fall time output
4 x t
Bus
1
1 t
Bus
- 30
15
25
—
—
—
0
—
— 25
—
— t
Bus
—
—
—
— t
Bus
25
— t
Bus
- 25
Unit
Hz ns ns ns ns t
Bus t
Bus ns ns ns ns ns ns
Comment
f
Bus
is the bus clock as
.
t
Bus
= 1/f
Bus
—
—
—
—
—
Time to data active from high-impedance state
Hold time to highimpedance state
—
—
—
—
SPSCK
(CPOL=0)
(INPUT)
SPSCK
(CPOL=1)
(INPUT)
MISO
(OUTPUT)
8
3
MOSI
(INPUT)
NOTE: Not defined see note
6
5
SLAVE MSB
MSB IN
7
2
5
10
BIT 6 . . . 1
BIT 6 . . . 1
12
12
11
LSB IN
13 4
13
11
SLAVE LSB OUT
Figure 19. SPI slave mode timing (CPHA = 0)
SEE
NOTE
9
28
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
Dimensions
2
SPSCK
(CPOL=0)
(INPUT)
SPSCK
(CPOL=1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
NOTE: Not defined see note
8
3
5 5
10
SLAVE MSB OUT
6
MSB IN
7
12
12
11
BIT 6 . . . 1
BIT 6 . . . 1
13
4
13
SLAVE LSB OUT
LSB IN
Figure 20. SPI slave mode timing (CPHA=1)
9
5.5.2 MSCAN
Table 16. MSCAN wake-up pulse characteristics
Parameter
MSCAN wakeup dominant pulse filtered
MSCAN wakeup dominant pulse pass
Symbol
t
WUP t
WUP
Min
-
5
Typ
-
-
Max
1.5
-
Unit
µs
µs
6 Dimensions
6.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to
freescale.com
and perform a keyword search for the drawing’s document number:
If you want the drawing for this package
64-pin LQFP
80-pin LQFP
Then use this document number
98ASS23234W
98ASS23237W
Freescale Semiconductor, Inc.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
29
Pinout
7 Pinout
7.1 Signal multiplexing and pin assignments
For the pin muxing details see section Signal Multiplexing and Signal Descriptions of
KEA128 Reference Manual.
8 Revision History
The following table provides a revision history for this document.
Rev. 1
Rev. 2
Rev. 3
Rev. 4
Rev. No.
Table 17. Revision History
Date
11 March 2014
18 June 2014
18 July 2014
03 Sept 2014
Substantial Changes
Initial Release
• Parameter Classification section is removed.
• Classification column is removed from all the tables in the document.
• New section added - Supply current characteristics
.
• Added supported part numbers.
•
section is updated.
• Figures in DC characteristics
section are updated.
• Specs updated in following tables:
•
.
• Data Sheet type changed to
"Technical Data".
30
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
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Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to any products herein.
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©2014 Freescale Semiconductor, Inc.
Document Number S9KEA128P80M48SF0
Revision 4, 09/2014
Mouser Electronics
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