AOZ8304A Low Capacitance 3.3 V TVS Diode General Description

AOZ8304A Low Capacitance 3.3 V TVS Diode  General Description
AOZ8304A
Low Capacitance 3.3 V TVS Diode
General Description
Features
The AOZ8304A is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
z ESD protection for high-speed data lines:
This AOZ8304A incorporates eight surge rated, low
capacitance steering diodes and a TVS in a single
package. During transient conditions, the steering
diodes direct the transient to either the positive side of
the power supply line or to ground. The AOZ8304A
may be used to meet the ESD immunity requirements of
IEC 61000-4-2, Level 4 and IEC 61000-4-5. The TVS
diodes provide effective suppression of ESD voltages:
±30 kV (air discharge) and ±30 kV (contact discharge).
The AOZ8304A comes in a Halogen Free and RoHS
compliant DFN-10 2.6 mm x 2.6 mm package and is
rated over a -40 °C to +85 °C ambient temperature
range. The AOZ8304A is compatible with both lead free
and SnPb assembly techniques. The small size,
low capacitance and high ESD protection makes the
AOZ8304A ideal for protecting high speed video and
data communication interfaces.
– IEC 61000-4-2, level 4 (ESD) immunity test
– ±30 kV (air discharge) and ±30 kV (contact discharge)
– IEC 61000-4-4 (EFT) 40 A (5/50 ns)
– IEC 61000-4-5 (Lightning) 25 A
– Human Body Model (HBM) ±30 kV
z Small package saves board space
z Low insertion loss
z Protects four I/O lines
z Low clamping voltage
z Low operating voltage: 3.3 V
z Green product
z Pb-free device
Applications
z 10/100/1000 Ethernet
z USB 2.0 power and data line protection
z Video graphics cards
z Monitors and flat panel displays
z Digital Video Interface (DVI)
z T1/E1 telecom ports
Typical Application
AOZ8304A
TRD0+
TRD0TRD1+
TRD1-
Gigabit
Ethernet
Controller TRD2+
AOZ8304A
RJ45
Connector
TRD2TRD3+
TRD3VCC
75Ω
75Ω
75Ω
75Ω
Figure 1. 10/100/1000 Ethernet Port Connection
Rev. 1.1 August 2011
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Page 1 of 8
AOZ8304A
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ8304ADI
-40 °C to +85 °C
2.6 mm x 2.6 mm DFN-10
Green Product
AOS Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
CH1
1
10
NC
NC
2
9
CH2
CH3
3
NC
VP
8
NC
4
7
CH4
5
6
NC
GND
Pin Number
Description
1, 3, 7, 9
Input/Output lines
2, 4, 6, 8, 10
No connection
5
VP
Center Tab
Ground
DFN-10
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
VP – GND
3.3 V
Peak Pulse Current (IPP), tP = 8/20 µs
25 A
Peak Power Dissipation (8 x 20 µ[email protected] 25 °C)
400 W
Storage Temperature (TS)
-65 °C to +150 °C
ESD Rating per IEC61000-4-2,
Contact(1)
±30 kV
ESD Rating per IEC61000-4-2,
Air(1)
±30 kV
ESD Rating per Human Body Model
(2)
±30 kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150 pF, RDischarge = 330 Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100 pF, RDischarge = 1.5 kΩ.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
Rev. 1.1 August 2011
-40 °C to +85 °C
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Page 2 of 8
AOZ8304A
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40 °C to +85 °C.
Symbol
Parameter
Conditions
Min.
VRWM
Reverse Working Voltage
Between pin 5 and GND(4)
IR
Reverse Leakage Current
VRWM = 3.3 V, between pins 5 and GND
VBR
Reverse Breakdown Voltage
VBR = 1 mA
VCL
Channel Clamp Voltage
IPP = 5 A, tp = 100 ns, any I/O pin to
Ground(3)(6)(8)
Positive Transients
Typ.
Positive Transients
IPP = 10 A, tp = 100 ns, any I/O pin to
Ground(3)(6)(8)
Negative Transient
Channel Clamp Voltage
Positive Transients
IPP = 25 A, tp = 100 ns, any I/O pin to
Ground(3)(6)(8)
Negative Transient
Cj
Junction Capacitance
VR = 0 V, f = 1 MHz, any I/O pin to Ground
VR = 0 V, f = 1 MHz, between I/O pins
VR = 0 V, f = 1 MHz, any I/O pin to
VR = 0 V, f = 1 MHz, between I/O
Units
3.3
V
5
µA
5.6
V
7.00
V
-3.00
V
8.00
V
-4.00
V
10.00
V
-5.00
V
5
pF
3.5
Negative Transient
Channel Clamp Voltage
Max.
(3)(7)
(3)(7)
Ground(3)(6)
pins(3)(6)
1.25
5
2.5
pF
6
pF
pF
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
5. VBR is measured at the pulse test current IT.
6. Measurements performed with no external capacitor on VP (pin 5 floating).
7. Measurements performed with VP biased to 3.3 Volts.
8. Measurements performed using a 100 ns Transmission Line Pulse (TLP) system.
Rev. 1.1 August 2011
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Page 3 of 8
AOZ8304A
Typical Performance Characteristics
Forward Voltage vs. Forward Current
Clamping Voltage vs. Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
(tperiod = 100ns, tr = 1ns)
6
5
Forward Voltage (V)
Clamping Voltage, VCL (V)
12
10
8
6
4
3
2
1
0
4
5
10
15
20
5
25
10
20
25
Forward Current (A)
Peak Pulse Current, IPP (A)
I/O – Gnd Insertion Loss (S21) vs. Frequency
Analog Crosstalk (I/O–I/O) vs. Frequency
5
0
0
-10
20
S41 (dB)
-5
S21 (dB)
15
-10
-15
-20
-30
-40
-50
-60
-25
-70
-30
-80
1
10
100
1,000
10,000
10
100
1,000
10,000
Frequency (MHz)
Frequency (MHz)
Rev. 1.1 August 2011
1
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Page 4 of 8
AOZ8304A
Application Information
The AOZ8304A TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping
the over-voltage to a reference. When the transient on a
protected data line exceeds the reference voltage, the
steering diode is forward bias and conducts harmful ESD
transients away from the sensitive circuitry under
protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8304A devices should be located as close as
possible to the noise source. The placement of the
AOZ8304A devices should be used on all data and
power lines that enter or exit the PCB at the I/O
connector. In most systems, surge pulses occur on data
and power lines that enter the PCB through the I/O
connector. Placing the AOZ8304A devices as close as
possible to the noise source ensures that a surge voltage
will be clamped before the pulse can be coupled into
adjacent PCB traces. In addition, the PCB should use the
shortest possible traces. A short trace length equates to
low impedance, which ensures that the surge energy will
be dissipated by the AOZ8304A device. Long signal
traces will act as antennas to receive energy from fields
that are produced by the ESD pulse. By keeping line
lengths as short as possible, the efficiency of the line to
act as an antenna for ESD related fields is reduced.
Minimize interconnecting line lengths by placing devices
with the most interconnect as close together as possible.
The protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8304A low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the I/O terminals or connectors
to restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4 mm.
10. Keep the chassis ground trace length-to-width ratio
< 5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
TPBIASx
1μF
56Ω
56Ω
IEEE 1394
Connector
TPAx+
IEEE 1394
TPAxPHY
TPBx+
TPBx56Ω
56Ω
GND
5.1kΩ
270pF
AOZ8304A
IEEE1394 Port Connection
Rev. 1.1 August 2011
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Page 5 of 8
AOZ8304A
Package Dimensions, DFN 2.6 x 2.6, 10L
A
D
D1
D1/2
B
D/2
e
L
K
E/2
E1/2
E
E1
Pin #1 ID
Chamfer 0.30x45°
Pin #1 Dot
by Marking
TOP VIEW
BOTTOM VIEW
Dimensions in millimeters
Symbols
A
A1
b
c
D
D1
E
E1
e
K
L
b
A
A1
SIDE VIEW
c
RECOMMENDED LAND PATTERN
Min.
0.50
0.00
0.20
Nom. Max.
0.55
0.60
—
0.05
0.25
0.30
0.152 REF.
2.55
2.60
2.65
2.10
2.15
2.20
2.55
2.60
2.65
1.21
1.26
1.31
0.50 BSC
0.32 REF
0.30
0.35
0.40
Dimensions in inches
Symbols
A
A1
b
c
D
D1
E
E1
e
K
L
Min.
Nom. Max.
0.020 0.022 0.024
0.000
—
0.002
0.008 0.010 0.012
0.006 REF.
0.100 0.102 0.104
0.083 0.085 0.087
0.100 0.102 0.104
0.048 0.050 0.052
0.050 BSC
0.013 BSC
0.012 0.014 0.016
2.35
1.75
0.50
0.45
0.32
1.175
0.63
1.26
2.35
Pin #1 ID
Chamfer 0.20x45°
UNIT: mm
0.25
Note:
1. Controlling dimension is millimeter. Coverted inch dimensions are not necessarily exact
Rev. 1.1 August 2011
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Page 6 of 8
AOZ8304A
Tape and Reel Dimensions, DFN 2.6 x 2.6, 10L
Carrier Tape
P1
D0
P2
D1
K0
E1
E2
R0.3
Max.
E
B0
A0
T
P0
R0.3 Typ.
Feeding Direction
UNIT: mm
Reel
Package
T
B0
A0
K0
D0
D1
E
E1
E2
P0
P1
P2
DFN
2.6x2.6
0.30
±0.05
2.80
±0.10
2.80
±0.10
1.10
±0.10
ø1.50
+0.1/-0.0
ø1.50
Min.
12.0
±0.3
1.75
±0.10
5.50
±0.05
4.00
±0.10
4.00
±0.10
2.00
±0.05
B
W1
S
60°
120°
M
K
N
H
Arbor Hole Detail A
Scale 2:1
2.24
B
W
2.84
Back View
Section B-B
Front View
UNIT: mm
Tape Size
12mm
Reel Size
ø180
M
ø179
±1.0
N
60
±0.5
W
13
±0.5
W1
17.0
H
ø13.0
±0.2
K
10.5
±0.25
S
2.0
±0.2
Leader / Trailer
& Orientation
Trailer Tape
300mm Min.
Rev. 1.1 August 2011
Components Tape
Orientation in Pocket
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Leader Tape
500mm Min.
Page 7 of 8
AOZ8304A
Part Marking
AOZ8304ADI
(DFN-10)
Assembly Location Code
PNOA
Part Number Code
Option Code
YWLT
Year & Week Code
Assembly Lot Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.1 August 2011
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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