LV25810PEB Car DSP Tuner Overview

LV25810PEB  Car DSP Tuner Overview
Ordering number : ENA2341
LV25810PEB
Bi-CMOS LSI
http://onsemi.com
Car DSP Tuner
Overview
LV25810PEB is a DSP tuner LSI which adopts Low-IF. This IC has realized not only the significant reduction of
external parts compare to the existing model by integration, but also the reconfiguration of specification according to
customers’ need by setting and controlling the software of microcontroller, in which constant is programmable.
Therefore, this IC curbs the total cost and realizes a tuner which corresponds to on-board type.
This LSI implements serial bus (I2C) I/F, which realizes reduction of communication line with microcontroller. In
mass production, it is effective to prevent troubles related to line layout, and to reduce area of the system main board.
In addition to radio basic functions, LV25810PEB integrates a new original CMA circuit to enhance multipath noise
rejection feature. Also, LV25810PEB includes an HD Radio decoder interface.
Features
• LOW-IF (AM=57.5/58.33/58.5/58.75/59.75/60.5kHz, FM=300kHz)
• Implementation area is reduced by part reduction.
• Standard AM/FM global tuner [AM (LW, MW, SW), FM (JAPAN, US, EU, E-EU, WB)]
• HD radio ready (I2S I/O port for external HD Radio decoder)
• The best multipath noise rejection of all the other ICs with new CMA.
Functions
FM/AM FE, PLL, IF, FM/AM detector, FM/AM-noise canceller, FM-multipath noise canceller, FM-MPX, switching
diversity, RDS demodulator/decoder, integrated HD Radio interface function (HD blend processing).
Function Overview
1) FM RF-LNA
2) FM IQ mixer
3) FM RF-AGC
4) AM RF-LNA
5) AM IQ mixer
6) AM RF-AGC
7) FM/AM IF-AGC
8) IF ADC
9) Variable IF band filter
10) Image canceller
11) IF block multipath noise rejection (CMA)
12) FM/AM pulse noise canceller
13) FM stereo decoder
14) Audio block multipath noise rejection (MRC)
15) RDS demodulator and decoder
16) IF data output for HD decoder
17) Digital I2S input for HD blend function
18) Stereo output (analog DAC/ digital I2S)
19) PLL synthesizer
20) Switching diversity
Package
QFP80 (14×14), 0.65mm pitch
(Required to solder the Exposed-Die-Pad to GND)
QFP80(14X14)
* I2C Bus is a trademark of Philips Corporation.
ORDERING INFORMATION
See detailed ordering and shipping information on page 28 of this data sheet.
Semiconductor Components Industries, LLC, 2014
June, 2014
61714NK 20140530-S00001 No.A2341-1/28
LV25810PEB
Absolute Maximum Ratings at Ta=25°C, VSS=0V
Parameter
Symbol
Supply voltage
Vcc1 max
VCC (5V)
Supply voltage
Supply voltage
Input voltage
Operating
temperature
Storage
temperature
Pin name
Conditions
Value
unit
For FE analog
−0.3 to 5.8
V
Vcc2 max
VDD33,
PLLVDD,
XVDD,
AVDD33,
DACVDD
(3.3V)
For FE logic, BE_ADC, and DAC
−0.3 to 3.9
V
Vcc3 max
VDD15
(1.5V)
BE logic power supply
w/ internal regulator and external
FET, external power supply is
unnecessary.
−0.3 to 1.8
V
VIN1max
*1
VSS−0.3 to VDD+0.3
V
VIN2max
*2
VSS−0.3 to 5.5
V
Topr
−40 to +85
°C
Tstg
−50 to +125
°C
*1) Please refer the “Pin Overview” list of Page5/Page6 for the details of each VDD name and the supply voltage to them.
*2) TEST, RSTB, BL_SEL, BL_LRCK, BL_BCLK, BL_DATA, I2C_SCL, I2C_SDA, TESTI1, TESTI2
Only when the power supplies are On, you can apply voltage to input pin up to 5.5V. When the power is OFF, you can only apply
voltage up to 3.6V.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable operating range at Ta=−40 to +85°C, VSS=0V
Parameter
Symbol
Pin name
Conditions
VCC_OSC
VCC_IF
VCC_AM
VCC_FM
VDD33,
PLLVDD, XVDD
AVDD33,
DACVDD
Min.
Typ.
Max.
unit
4.75
5.0
5.25
V
3.15
3.3
3.45
V
3.15
3.3
3.45
V
Supply voltage
Vcc1
Supply voltage
Vcc21
Supply voltage
Vcc22
Supply voltage
Vcc3
VDD15
1.42
1.5
1.58
V
Input ”H” level voltage
VIH
*4
2.0
–
–
V
Input ”L” level voltage
VIL
*4
–
–
0.8
V
–
–
1250
mW
146k
520k
2.28M
–
281k
1710k
26.1M
Hz
65
–
108
MHz
162.4
–
162.55
MHz
–
62.4
–
MHz
Allowable power
dissipation
*3
78mm×106mm×1.7mm PWB
(Glass epoxy, Double-sided)
Ta=85°C,
Exposed-Die-Pad is soldered to
GND.
LW
MW
SW
Pdmax
AM reception
frequency
FM reception
frequency
WB reception
frequency
X’tal oscillator
frequency
E-EU, EU, US, Japan
WB
XIN, XOUT
*5
*3) Required more than 90% of Exposed Die-Pad area to be soldered to GND.
*4) TEST, RSTB, MODE, BL_SEL, BL_LRCK, BL_BCLK, BL_DATA, SP_SSB, SP_CLK, SP_DI, SP_DO
*5) X’tal CI value ≤ 40Ω (X’tal oscillator)
In X’tal oscillation circuit, circuit constant fluctuates depends on X’tal oscillator and a pattern of a board. Therefore, it is
recommended that a manufactures of the X’tal oscillator performs an evaluation.
No.A2341-2/28
LV25810PEB
Recommended operating supply voltage at Ta=25°C
Parameter
Symbol
Pin name
Min.
Typ.
Max.
unit
Supply voltage
Vcc1
VCC_OSC, VCC_IF, VCC_AM ,VCC_FM
–
5.0
–
V
Supply voltage
Vcc2
VDD33, PLLVDD, XVDD, AVDD33, DACVDD
–
3.3
–
V
Supply voltage
Vcc3
VDD15
–
1.5
–
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical characteristics at Ta=25°C, FM fr=98.1MHz
Parameter
Current consumption
(5V FM)
Current consumption
(3.3V FM)
Current consumption
(1.5V FM)
rd
Local frequency 3
spurious rejection
ratio
Symbol
Pin name
Conditions
Min.
Typ.
Max.
unit
I5V_FM
No input signal, FM Mode
85
100
115
mA
I33V_FM
No input signal, FM Mode
68
80
92
mA
I15V_FM
No input signal, FM Mode
153
180
207
mA
Freq. Setting =90MHz,
Input Freq. =271.2MHz
Reference input level: 90MHz 20dBuV
70
80
–
dB
Impedance between pin 69 and 70
–
300
–
Ω
67
73
79
dBuV
53
59
65
dBuV
98
100
102
–
43
48
53
–
147
152
157
–
–
3
6
dBuV
FM_HRR3
Input impedance
Zi
RF AGC start point
F_RFAGC
IF AGC start point
F_IFAGC
S-Meter DC 1
SMDC_F1
S-Meter DC 2
SMDC_F2
S-Meter DC 3
SMDC_F3
Practical sensitivity
(FM)
US
Output level (FM)
VoFM
THD(MONO)
THDMONO
S/N(MONO)
S/N MONO
THD(STEREO)
THD ST
S/N(STEREO)
S/N ST
AMR
AMR
Separation
SEP
Image rejection rate
IRR
Interference
characteristic
(Sensitivity reduction)
2SIG
FM_IN+
FM_IN-
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
RF AGC operation sensitivity @RF_ATT
2→3
IF AGC operation start point
@IF_ATT 0→1
SMDC Value @30dBuV no-dev input
After calibration to SMDC=100
SMDC Value @10dBuV no-dev input
After calibration to SMDC_F1
SMDC Value @50dBuV no-dev input
After calibration to SMDC_F1
fm=1kHz, 22.5kHz dev. S/N=30dB ANT
input level
IF BW=60kHz, HCC ON
60dBuV, fm=1kHz, 75kHz dev.
200
mVrms
60dBuV, fm=1kHz, 75kHz dev.
–
0.1
0.7
%
60dBuV, fm=1kHz, 75kHz dev.
66
72
–
dB
–
0.4
1
%
61
67
–
dB
60
67
–
dB
35
45
–
dB
65
80
–
dB
–
35
41
dBuV
80dBuV, fm=1kHz,
L=R 90% mod., Pilot 10% mod.
60dBuV, fm=1kHz,
L=R 90% mod., Pilot 10% mod.
60dBuV, fm=1kHz, 75kHz dev.,
fm=1kHz 30%AM, CMA=OFF
60dBuV, fm=1kHz, 30%mod,
L-ch only
fr=98.7MHz, fm=400Hz, 22.5kHz dev.
(after adjustment by IQ correction circuit)
fud=98.5MHz, fm=400Hz, 110dBuV,
22.5kHz dev.
fd=98.1MHz, fm= 1kHz, 22.5kHz dev.
S/N=30dB ANT input level
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2341-3/28
LV25810PEB
AM fr=1MHz, After tuning AM RF Synchronization
Parameter
Current
consumption
(5V AM)
Current
consumption
(3.3V AM)
Current
consumption
(1.5V AM)
rd
Local frequency 3
th
and 5 spurious
rejection ratio
Symbol
Pin name
Conditions
Min.
Typ.
Max.
unit
I5V_AM
No input signal, AM Mode
72.25
85
97.75
mA
I33V_AM
No input signal, AM Mode
68
80
92
mA
I15V_AM
No input signal, AM Mode
93.5
110
126.5
mA
70
80
–
dB
78
84
90
dBuV
67
73
79
dBuV
138
140
142
–
83
88
93
–
187
192
197
–
–
22
25
dBuV
AM_HRR3
AM_HRR5
RF AGC start point
RF AGC
IF AGC start point
IF AGC
S-Meter DC 1
SMDC_A1
S-Meter DC 2
SMDC_A2
S-Meter DC 3
SMDC_A3
Practical sensitivity
(AM)
US
Output level(AM)
VoAM
S/N(AM)
S/N
THD(AM)
THD
Image rejection
ratio
IRR
Anti-interference
feature
CROSS
DACLOUT
DACROUT
DACLOUT
DACROUT)
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
DACLOUT
DACROUT
Freq. Setting = 1000kHz,
AM_HRR3: 3230kHz, with RF input,
AM_HRR5: 5230kHz, with RF input
RF AGC operation start point
@RF_ATT 0→1
IF AGC operation start point
@IF_ATT 0→1
SMDC Value @40dBuV no-dev input
After calibration to SMDC=140
SMDC Value @20dBuV no-dev input
After calibration to SMDC_A1
SMDC Value @60dBuV no-dev input
After calibration to SMDC_A1
fm=400Hz 30%, S/N20dB,
HCC=ON, Speech enhancer=ON
ANT input level
74dBuV, fm=400Hz30%, det. output level
( with LPF )
74dBuV
fm=400Hz 30%mod.
74dBuV
fm=400Hz 80%mod
fr=1115kHz, fm=400Hz, 30%mod
(after adjustment by IQ correction circuit)
fud=1.08MHz 100dBuV, fm= 1kHz,
80%mod,
fd=1MHz 65dBuV, fm=400Hz, 30%mod.
70
mVrms
56
62
–
dB
–
0.1
1.0
%
70
80
–
dB
32
38
–
dB
DC characteristics
Parameter
Output ”H” level
Voltage
Output ”L” level
Voltage
Symbol
VOH
VOL
Pin name
Conditions
Min.
Typ.
Max.
unit
*8
IOH=1mA
Vcc2−0.4
V
*6
IOH=2mA
Vcc2−0.4
V
*7
IOH=4mA
Vcc2−0.4
V
*8
IOL=1mA
0.4
V
*6
IOL=2mA
0.4
V
*7
IOL=4mA
0.4
V
10
μA
Input leak current
IL
*9
Hysteresis voltage
VHYS
*9
−10
0.25
V
*6) ANT1, ANT2, BUSY, SP_ERR, IB_BCLK
*7) I2C_SDA
*8) IB_WS, IB_IDATA, IB_QDATA, RDSC, RDSD, RDSID, AO_BCLK, AO_LRCK, AO_DATA,
*9) TEST, RSTB, BL_SEL, BL_LRCK, BL_BCLK, BL_DATA, I2C_SCL, I2C_SDA, TESTI1, TESTI2
Additional data :
1. Digital audio output (I2S) Fs=54.167kHz
2. HD decoder output (I2S) Fs=650kHz
3. DAC output : S/N=87dB typ. (−3dBFS Input)
No.A2341-4/28
LV25810PEB
Package Dimensions
unit : mm
PQFP80 14x14, 0.65P
CASE 122CG
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL BE 0.08 MAX. AT MMC. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07.
4. DIMENSIONS D1 AND E1 DO NO INCLUDE MOLD FLASH, GATE BURRS,
OR PROTRUSIONS. MOLD FLASH, GATE BURRS, OR PROTRUSIONS
SHALL NOT EXCEED 0.25 PER SIDE. DIMENSIONS D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE INCLUDING MOLD MISMATCH.
5. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM
PACKAGE SIZE BY AS MUCH AS 0.15.
6. DIMENSIONS D1 AND E1 TO BE DETERMINED AT DATUM PLANE H.
7. DATUMS A−B AND D ARE DETERMINED AT DATUM PLANE H.
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
9. DIMENSIONS D AND E TO BE DETERMINED AT DATUM PLANE C.
10. EXPOSED PAD TO BE COPLANAR WITH THE BOTTOM OF THE PACKAGE.
2X 20 TIPS
5
0.20 C A-B D
9
D
D
7
7
B
A
6
E1
5
E
7
4
9
2X
0.10 H A-B D
2X 20 TIPS
1
PIN ONE
INDICATOR
2X
0.10 H A-B D
4
D1
0.20 C A-B D
6
DIM
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
L2
M
TOP VIEW
0.05
0.10 C
DETAIL A
H
A2
c
L2
A
0.10 C
C
SIDE VIEW
SEATING
PLANE
8 A1
L
M
DETAIL A
D2
1
10
RECOMMENDED
SOLDERING FOOTPRINT*
21
80
17.76
10
80X
L
80X
1.58
6.90
E2
61
MILLIMETERS
MIN
MAX
2.95
0.05
0.15
2.70 REF
0.20
0.30
0.10
0.30
17.20 BSC
14.00 BSC
6.70
7.10
17.20 BSC
14.00 BSC
6.70
7.10
0.65 BSC
0.60
1.00
0.25 BSC
0°
10 °
3
41
e
e/2
BOTTOM VIEW
80X
b
0.13 C A-B D
6.90
17.76
0.65
PITCH
80X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
No.A2341-5/28
LV25810PEB
Pin overview
I : Input pin, O : Output Pin, B : Bi-Directional Pin, A : Analogue Pin, P : Power Supply
Output Level1: Initial condition (After finishing reset procedure), Output Level2 : During reset procedure
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
Pin name
I/O
GND_OSC
VT_out
CP_SW
VCC_OSC
GND_PLL
VDD33_FE
VDD33
DVSS
VDD15
ANT1
ANT2
P
A
A
P
P
P
P
P
P
O
O
12
TEST
I
13
14
15
16
BL_SEL
BL_LRCK
BL_BCLK
BL_DATA
I
I
I
I
17
IB_WS
O
L
L
18
19
20
21
22
23
24
IB_BCLK
IB_IDATA
IB_QDATA
RDSC
RDSD
RDSID
RSTB
O
O
O
O
O
O
I
L
L
L
L
L
L
L
L
L
L
L
L
25
BUSY
O
L
H
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
SP_ERR
I2C_SDA
TESTI1
I2C_SCL
TESTI2
AO_BCLK
AO_LRCK
AO_DATA
VDD33
REFV
DVSS
VDD15
PLLVDD
PLLVSS
DACVSS
DACROUT
DACREF
DACLOUT
DACVDD
XIN
XOUT
XVDD
XVSS
AVSSVREF
AVREFI
AVREFQ
O
B
I
I
I
O
O
O
P
O
P
P
P
P
P
A
A
A
P
I
O
P
P
P
A
A
L
Z
L
Z
52
AVDDVREF
P
Output
Level1
H
H
Output
Level2
L
L
Description
LoOSC GND
Tuning voltage output
PLL AM/FM time constant switching
LoOSC power supply (5V)
PLL GND
FE Digital power supply (3.3V)
BE Digital power supply (3.3V)
Digital GND
Digital power supply (1.5V)
Antenna switching 1
Antenna switching 2
Test pin L: normal operation
H: test mode
Connect to GND during normal
operation
VDD/
VCC
VSS/
GND
VCC_OSC
GND_OSC
Open
Open
To GND
IBOC blend input select
IBOC blend input LR clock
IBOC blend input bit clock
IBOC blend input data
L
L
L
L
L
L
To GND
To GND
To GND
To GND
IBOC signal output word
synchronization
IBOC signal output bit clock
IBOC signal output I data
IBOC signal output Q data
RDS output clock
RDS output data
RDS output data judgment
Reset input
CPU interface busy signal output
H: busy
CPU interface error output H : error
2
CPU interface I C data input / output
Test pin (connect to GND)
2
CPU interface I C clock input
Test pin (connect to GND)
Audio digital output bit clock
Audio digital output LR clock
Audio digital output data
Digital power supply (3.3V)
1.5V reference voltage output
Digital GND
Digital power supply (1.5V)
PLL power supply (3.3V)
PLL GND
Audio DAC GND
Audio DAC R channel output
Audio DAC reference voltage
Audio DAC L channel output
Audio DAC power supply (3.3V)
X’tal oscillation amplifier input
X’tal oscillation amplifier output
X’tal oscillation power supply(3.3V)
X’tal oscillation GND
IF ADC reference GND
IF ADC reference voltage(I)
IF ADC reference voltage(Q)
Unused
connection
Open
VDD33
DVSS
Open
Open
Open
Open
Open
Open
To GND
To GND
Open
Open
Open
DVDD33
DVSS
PLLVDD
PLLVSS
DACVDD
DACVSS
XVDD
XVSS
AVDD33
AVSS33
Open
Open
Open
Open
IF ADC reference power supply
(3.3V)
Continued on next page
No.A2341-6/28
LV25810PEB
Continued from preceding page.
Pin
No.
Pin name
I/O
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
TESTTEST+
AVDD33
AVSS33
Vref
VCC_IF
FE TEST
AM_RF_AGC1
AM_LNA_IN+
AM_LNA INVCC_AM
AM_LNA_out+
AM_LNA_outGND_AM
AM_CB_INAM_CB_IN+
FM_IN+
FM_INVCC_FM
A
A
P
P
A
P
A
A
A
A
P
A
A
P
A
A
A
A
P
72
WB_IN+
A
73
WB_IN-
A
74
75
76
GND_FM
PIN_DIODE
FM_RF_AGC0
P
A
A
Test pin TEST is normally open.
Test pin TEST is normally open.
IF ADC power supply (3.3V)
GND for IF ADC/ FE-IF
FE reference voltage (3.15V)
IF power supply (5V)
FE TEST pin
Rectifier pin for AM RF AGC
AM LNA input+
AM LNA inputAM power supply (5V)
AM LNA output+
AM LNA outputAM GND
AM Cap Bank inputAM Cap Bank input+
FM LNA input+
FM LNA inputFM power supply (5V)
Weather Band LNA input+/ FM ANT
buffer output+
Weather Band LNA input-/ FM ANT
buffer outputFM GND
Pin diode drive pin
Rectifier pin0 for FM RF AGC
77
FM_RF_AGC1
A
Rectifier pin1 for FM RF AGC
78
79
80
VCO1
VCO_BIAS
VCO2
A
A
A
VCO oscillation pin1
VCO bias
VCO oscillation pin2
Output
Level1
Output
Level2
Z
Z
Z
Z
Description
VDD/
VCC
VSS/
GND
Unused
connection
AVDD33
AVSS33
Open
Open
VCC_IF
AVSS33
Open
VCC_AM
GND_AM
VCC_AM
GND_AM
VCC_AM
GND_AM
VCC_FM
GND_FM
VCC_FM
GND_FM
VCC_FM
GND_FM
VCC_OSC
GND_OSC
Circuit Stricture
Pin
12
13
14
15
16
24
27
28
30
10
11
17
18
19
20
21
22
23
25
26
31
32
33
Function
TEST
BL_SEL
BL_LRCK
BL_BCLK,
BL_DATA
RSTB
I2C_SCL,
TESTI1
TESTI2
ANT1
ANT2
IB_WS
IB_BCLK
IB_IDATA
IB_QDATA
RDSC
RDSD
RDSID
BUSY
SP_ERR
AO_BCLK
AO_LRCK
AO_DATA
Equivalent circuit
Remarks
Digital Input
(5V tolerant)
Digital Output
Continued on next page
No.A2341-7/28
LV25810PEB
Continued from preceding page.
Pin
Equivalent circuit
Function
27
I2C_SDA
34
VDD33
35
REFV
Remarks
Digital Input/Output
(5V tolerant)
-
Digital Power Supply (3.3V)
Reference Voltage output
+
36
DVSS
-
Digital GND
37
VDD15
-
Digital Power Supply (1.5V)
38
PLLVDD
-
PLL Power Supply (3.3V)
39
PLLVSS
-
PLL GND
40
DACVSS
-
GND for Audio DAC
41
43
DACROUT
DACLOUT
DAC Output
+
42
DACREF
44
DACVDD
Reference Voltage Output
for AudioDAC
-
VDD for Audio DAC (3.3V)
Continued on next page
No.A2341-8/28
LV25810PEB
Continued from preceding page.
Pin
Equivalent circuit
Function
Remarks
45
46
XIN
XOUT
47
XVDD
-
VDD for Crystal OSC (3.3V)
48
XVSS
-
GND for Crystal GND
49
AVSSVREF
-
Reference GND for IF ADC
50
51
AVREFI
AVREFQ
Oscillator circuit
ADC
REF Output
+
52
AVDDVREF
53
54
TEST+
TEST-
1
GND_OSC
2
VT out
-
Reference VDD for IF ADC (3.3V)
TEST
• GND for LO_OSC
-
• PLL charge-pump output
• Control input for internal varactor
VT
VCC5V
Charge-pump output is transferred to
DC signal with external LPF.
P_CH
100Ω
P_CH
100Ω
4.25V
100Ω
0.25V
N_CH
N_CH
GND
Continued on next page
No.A2341-9/28
LV25810PEB
Continued from preceding page.
Pin
3
Equivalent circuit
Function
CP SW
Remarks
• Switch the constant value of
external LPF.
VCO_BIAS
P_CH
100Ω
100Ω
500Ω
4
VCC_OSC
-
• 5V supply for LO_OSC
5
6
GND_PLL
VDD33_FE
-
57
Vref
• Digital GND for PLL
• 3,3V supply for FE
• Capacitor for internal power supply
VCC5V
circuit.
500Ω
This capacitor stabilizes the internal
power supply circuit.
50Ω
Q
NPN
15k
15k
GND
58
59
60
VCC_IF
FE_TEST
AM RF AGC1
• 5V supplu for FE IF
• AM RF AGC output
-
P_CH
SIG
300Ω
N_CH
61
62
AM_INAM_IN+
RER_VBE
VCC5V
VCC5V
• AM LNA input
ÆInput RF signal.
100Ω
N_CH
N_CH
GND
63
VCC_AM
-
GND
• 5V supply for AM
Continued on next page
No.A2341-10/28
LV25810PEB
Continued from preceding page.
Pin
64
65
Equivalent circuit
Function
AM LNA out+
AM LNA out-
Remarks
• AM LNA output
VCC5V
Q
NPN
10Ω
10Ω
Q
PNP
66
67
68
GND_AM
AM_CB_INAM_CB_IN+
GND
• GND for AM
• AM capacitor-bank input
VCC5V
BIAS
Q
NPN
Q
NPN
70k
70k
200Ω
OUT+
OUT-
200Ω
130k
130k
2
GND
N CH
1
N CH
C
N CH
N CH
U
7405
N_OUT
GND
69
70
• FM LNA input
FM_IN+
FM_IN-
Î Input RF signal.
Q
Q
NPN
NPN
50Ω
GND
BIAS
VCC5V
50Ω
C
VR
VR2
50Ω
Q
PNP
Q
PNP
C
GND
71
VCC_FM
-
• 5V supply for FM
Continued on next page
No.A2341-11/28
LV25810PEB
Continued from preceding page.
Pin
72
73
Equivalent circuit
Function
WB_IN+
WB_IN-
Remarks
• LNA input for weatherband (WB)
• Buffered-Output for sub-tuner
VCC5V
Î Output RF signal
100Ω
These pins are use for WB input or
Buffered-Output for sub-tuner
Q
NPN
50Ω
VCC5V
Q
NPN
BIAS
650Ω
500Ω
GND
50Ω
Q
NPN
C
C
74
GND_FM
75
PIN_DIODE
−
• GND for FM
• PIN diode driver
VCC5V
P CH
P CH
GND
76
• Rectifier for FM RFAGC0
FM_RF_AGC0
Q
PNP
Q
PNP
Q
NPN
Q
NPN
P_CH
P_CH
R
R
N_CH
77
N_CH
• Rectifier for FM RFAGC1
FM_RF_AGC1
Q
NPN
Q
NPN
Q
NPN
R
R
R
R
P_CH
P_CH
P_CH
P_CH
R
R
N_CH
N_CH
N_CH
N_CH
R
R
Continued on next page
No.A2341-12/28
LV25810PEB
Continued from preceding page.
Pin
78
80
Equivalent circuit
Function
VCO1
VCO2
Remarks
• VCO oscillation
Vref
GND
C
C
GND
BIAS
BIAS
VCC5V
Î Do not connect any other
circuit.
C
BIAS
C
BIAS
C
C
NPN
NPN
Q
Q
GND
79
NPN
NPN
Q
Q
GND
GND
GND
• VCO BIAS pin
VCO_BIAS
Î For the stabilization of the
VCO bias voltage level
with external capacitor .
Q
NPN
Q
NPN
Q
NPN
C
C
GND
No.A2341-13/28
LV25810PEB
The Power Supply / Shut Down Procedure
The power supply / shutdown order to each Power pins and the specified pins are as follows.
These order and timings must be kept absolutely.
1) To start the system
5.0V System
tpup533
3.3V System
tpup3315
1.5V System
RSTB Pin
tRST
tXtal
Enable to supply
the 5.0V to each Pins
tINIT
BUSY Pin
RSTB pin must be kept the “L” level during 5ms after latter either the 1.5V System is activated or the waiting
time of the OSC being stable.
2) To Shut Down the System
5.0V System
tpdn335
3.3V System
tpdn1533
1.5V System
Parameter
Symbol
Power Supply Waiting Time
(5.0V Æ3.3V)
Condition
Min.
Typ.
Max.
tpup533
0
100
Power Supply Waiting Time
(3.3V Æ 1.5V)
tpup3315
0
100
Waiting time of the
OSC being stable
tXtal
5
Reset Pulse Width
tRST
5
LSI Initialization time *1
tINIT
Unit
ms
9
Shut Down Waiting Time (1.5V
Æ 3.3V)
tpdn1533
0
100
Shut Down Waiting Time (3.3V
Æ 5.0V)
tpdn335
0
100
*) In Digital Input pins (5V-Tolerant system), do not supply the “H (=5V)” level until all of power supply voltage
level does not reach a defined value.
*) The input / output direction of each I/O pins are not defined until the 1.5V system is activated.
The order of the power supplies to 5V, 3V, and 1.5V system must be adhered closely to the following order.
5V Æ 3.3V Æ 1.5V
If this order is met and the total elapsed time of “tput533” and “tpup3315” is less than 100ms, the order that each power
supply reaches the operation voltage can be ignored.
No.A2341-14/28
LV25810PEB
Host I/F
I2C I/F
The I2C interface supports 100kbs Standard mode and 400kbps High-Speed mode, and the unit of data transfer
is 8 bits. The details of data read and data write are written in software control manual.
I2C slave address is 0x1D.
Data Write
Data Write Sequence (6bytes)
: Signal from LV25810 to Master
I2C_SCL
I2C_SDA
W
A
C7 C 6 C 5 C4 C3 C 2 C 1 C 0
Slave Address
C 1 5 C 1 4 C 1 3 C 1 2 C 11 C 1 0
Data
D7 D 6 D 5 D4 D3 D 2 D 1 D 0
A
C8
A
C23 C22 C21 C20 C19 C18 C17 C16
D9
D8
A
Ack
D23 D22 D21 D20 D19 D18 D17 D16
Data
A
Data
Ack
D 1 5 D 1 4 D 1 3 D 1 2 D 11 D 1 0
Data
C9
Data
Write Ack
Start
A
Ack
A
Data
Ack
Ack Stop(or Repeated Start)
Ack
Data write can be accepted during the status of “BUSY” output level is “L”. The command and data during the status of
“BUSY” output level is “H” cannot be acceptable.
Data Read
Data Read Sequence
: Signal from LV25810 to Master
I2C_SCL
I2C_SDA
W
A
C7 C 6 C 5 C4 C3 C 2 C 1 C 0
Slave Address
C 1 5 C 1 4 C 1 3 C 1 2 C 11 C 1 0
Data
C9
C8
A
C23 C22 C21 C20 C19 C18 C17 C16
Data
Write Ack
Start
A
A
Data
Ack
Ack Stop
Ack
<Wait till the status of “BUSY” becomes “L”>
R
A
D7 D 6 D 5 D4 D3 D 2 D 1 D 0
Slave Address
Start
A
D 1 5 D 1 4 D 1 3 D 1 2 D 11 D 1 0
Data
D9
D8
A
D23 D22 D21 D20 D19 D18 D17 D16
Data
Read Ack
Data
Ack
D7 D 6 D 5 D4 D3 D 2 D 1 D 0
A
D 1 5 D 1 4 D 1 3 D 1 2 D 11 D 1 0
Data
Ack
Ack
D9
D8
A
D23 D22 D21 D20 D19 D18 D17 D16
Data
Ack
A
A
Data
Ack
Nak Stop(or Repeated Start)
No.A2341-15/28
LV25810PEB
Timing Specifications
①
⑧
⑦
④
①
⑪
⑨
I2C_SCL
②
③
⑩
I2C_SDA
⑧
⑤
⑥
Start
⑦
Repeated Start
Stop
Standard Mode
High-Speed Mode
(100kbps)
(400kbps)
Timing Parameters
Min.
Max.
①
Hold time of Start (Repeated-Start) condition
4000
600
ns
②
SCL “L” Level Pulse Width
4700
1300
ns
③
SCL “H” Level Pulse Width
4000
600
ns
④
Setup time of Start (Repeated-Start) condition
4700
600
ns
⑤
SDA Hold Time
0
⑥
SDA Setup Time
250
⑦
SCL, SDA rise time
1000
20 + 0.1Cb
300
ns
⑧
SCL, SDA fall time
300
20 + 0.1Cb
300
ns
⑨
Setup time of Stop conditrion
4000
600
ns
⑩
Bus acceptable time
4700
1300
ns
⑪
Allowed Spike pulse width
0
ns
3450
Min.
0
Max.
900
100
Unit
ns
ns
“Cb” in ⑦ and ⑧ means the total capacity of the bus line both I2C_SCL and I2C_SDA.
Details of each command are written in the “Software Control Manual.
No.A2341-16/28
LV25810PEB
WatchDog Timer
To detect the runaway of internal DSP, LV25810 has the WatchDog Timer (WDT) output pin.
When the DSP runaway, the WDT overflows and the DSP status can be confirmed by the output of BUSY and
SP_ERR pin
Pin
BUSY
0
1
0
1
Status
SP_ERR
0
0
1
1
Command Waiting
Commanad transfer finished
Communication Error
DSP Runaway (WDT Overflow)
When both of BUSY and SP_ERR output level are “H”, the operation state of the DSP is abnormal.
If this occurs, the host CPU must reset and reboot the LV25810.
Commands
Status
RESET
RUNAWAY
INITIALIZE
Command
(Normal)
Command
Command
(Communication Error) (Normal)
RESET INITIALIZE
WDT
Overfolw
No.A2341-17/28
LV25810PEB
IBOC I/F
IBOC Decoder output is ready.
Fs : 650kHz
BCLK : 10.4MHz
Data Length : 16 bits
IBOC I/F Timing Chart
MSB
LSB
LSB MSB
MSB
LSB MSB
LSB MSB
LSB
LSB
MSB
Timing Specifications
IB_BCLK
tWD
fBCLK
IB_WS
tWD
tDD
IB_QDATA
IB_IDATA
Parameter
IB_BCLK frequency
Symbol
Min.
fBCLK
Typ.
Max.
10.4
Unit
MHz
IB_WS Output Delay Time
tWD
0
10
ns
IB_QDATA, IB_IDATA Output Delay time
tDD
0
15
ns
No.A2341-18/28
LV25810PEB
Audio Output
Audio output (I2S format) is available.
fs : 54.167kHz
BCLK : 64fs
Data Length : 24 bits
Audio Output Timing Chart
Timing Specifications
AO_BCLK
tLD
tLD
fBCLK
AO_LRCK
tDD
AO_DATA
Parameter
AO_BCLK frequency
Symbol
Min.
fBCLK
Typ.
Max.
3.467
Unit
MHz
AO_LRCK Output Delay Time
tLD
-1
10
ns
AO_DATA Output Delay Time
tDD
0
50
ns
No.A2341-19/28
LV25810PEB
IBOC BLEND Input
Audio Input (I2S format) for IBOC BLEND is available.
fs : 44.1kHz
BCLK : 32fs to 64fs
Data Length : 16 bits
Timing Chart
Timing Specifications
fBCLK
BL_BCLK
tLS
tLS
BL_LRCK
tDS
tDH
BL_DATA
Parameter
BL_BCLK frequency
BL_LRCK Setup Time
Symbol
Min.
Max.
Unit
fBCLK
1411.2
Typ.
2822.4
kHz
tLS
10
100
ns
BL_DATA Setup Time
tDS
10
ns
BL_DATA Hold Time
tDH
100
ns
No.A2341-20/28
LV25810PEB
RDS Demodulation Function
The RDS (Radio Data System) for EBU (Europe Broadcasting Union) and the RBDS (Radio Broadcast Data
System) for NSRC (National Radio System Committee (US)) demodulator system is available.
This system includes both the RDS demodulator, which outputs the RDS data directly to the RDSC, RDSD,
RDSID pin and the RDS decoder, which contains the error corrector function and data transfer function to the
main microcontroller.
The setting method is written in the software control manual.
(1) Block Diagram of RDS demodulation function
RDS demodulation function has following 4 blocks.
57kHZ BPF for RDS carrier signal,
RDS demodulator for by-phase demodulation,
RDS decoder for the error correction and data synchronization,
DSP for whole RDS system control
The block diagram is as follows.
57kHz
BPF
RDS
Demodulator
RDSC (clock)
RDSD (Data)
RDSID
RDS Decoder
(Error Correction
&
Synchronization)
DSP
I2C
a) 57kHz BPF block
This block contains the band-path filter to get the 57kHz signal, which is the 3rd harmonics of RDS sub-carrier
signal (19kHz). The sufficient characteristics of the RDS demodulation is provided with the digital filter.
b) RDS Demodulator block
To demodulate the RDS signal, this block contains the comparator block, by-phase clock regeneration block,
and the criterion circuit for data reliability.
The comparator block has the zero cross linear complement function and zero cross detection function.
This block lets the most suitable comparison position for the carrier signal from BPF block with doing the
linear complementation.
The bi-phase clock regeneration block has digital PLL, DATA module, and ARI detector. The PLL regenerates
the carrier signal and ARI detector detects the ARI signal. The data latch timing is defined depending on the
state of the ARI and the RDS data is decoded in DATA module.
The DATA module generates the RDS clock (RDSC) , RDS output data (RDSD), and RDS output data
judgement (RDSID) signals.
c) RDS Decoder Block (Error correction block)
RDS decoder block has the syndrome-register, the offset word detection function, the synchronism detection
function, and the error detection function. The RDS data is processed the syndrome-register, and the offset
word is detected with the offset detector by the output signal from the syndrome-register. The synchronization
pull-in process is executed in synchronism detection function depending on the content of the off-set word. The
selection of whether RDS or RDIS is controlled from DSP.
The intersymbol distance about the RDS data which may be wrong is measured and the soft-detection error
correction is executed.
No.A2341-21/28
LV25810PEB
d) DSP
This DSP controls all of the RDS functions by the instructions from the main microcontroller.
The demodulation data and the error collection data is transferred to the main microcontroller via DSP.
(2) RDSC, RDSD output timing
421μs 421μs
RDSC
RDSD
17μs
17μs
(3) RDSID output timing
RDSID output indicates the reliability of the RDS data.
When the RDS data is reliable, the RDIS output level becomes “L”.
RDSID
RDSC
RDSD
Data reliability
Low
High
Controllable Items
The following items are controllable. Details are shown in the software control manual.
• IF-BPF (Band Pass Filter)
• Local OSC
• AM RF Synchronization (Correct the difference of the AM CAP BANK)
• Image (Correct the amplitude error and phase error of the IQ signal)
• IF Offset (Correct the frequency mismatch of the IF signal)
• S-meter DC
• Separations
No.A2341-22/28
LV25810PEB
Application circuit
LV25810PEB
No.A2341-23/28
LV25810PEB
Measurement circuit
LV25810PEB
No.A2341-24/28
LV25810PEB
FM LNA+ RF AGC, WB LNA+ RF AGC (Including the IF-AFC)
When there is a FM (WB) RF signal at the ANT input, the output of MIX amplifier is about 25 dB. It attenuates by 3dB
per steps by switching the LNA, a total of 22 steps in Attenuation. RF_AGC_1 operates when antenna input level is
bout 75dBuV. RF_AGC_0 is the AGC for the LNA to improve the sensitivity and operates when antenna input level is
about 60dBuV. A 65MHz~108MHz band pass filter in formed by the LC Antenna input.
(Details are shown in software control manual.)
Signal processing Image
FM IF out Level
IFAGC (6dB step×3)
6dB Hysteresis
120
110
ATT0 (3dB UP)
Output Signal Level [dBuV]
100
90
80
70
up
down
60
50
ATT2 (3dB down)
6dB Hysteresis
40
RFAGC (3dB step×22)
3dB Hysteresis
30
20
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Input Signal Level [dBuV]
No.A2341-25/28
LV25810PEB
AM LNA+RF AGC (Including the IF-AGC)
The AM RF signal of the ANT input approximately 23 dB is feed into to the MIX.
LNA gain is controlled by 3dB per step, a total of 21 steps attenuation. RF AGC operates when antenna input is about
80dBuV.
In case of receiving the LW (144kHz – 281kHz), the RF signal output from LNA is input into the mixer via LPF. In
case of receiving the MW (520kHz -1710kHz), the RF signal output from LNA is tuned by the capacitor bank and is
input into the mixer.
In case of receiving the SW (2MHz – 30MHz), the RF signal output from LNA is input into the mixer via HPF.
The input LC antenna circuit makes 144 kHz – 30 MHz BPF.
(Details are shown in the software control manual.)
Signal Processing image
AM IF out Level
120
110
Output Signal Level [dBuV]
100
90
80
up
down
70
60
IFAGC (6dB step x 5)
6dB Hysteresis
50
40
RFAGC (3dBstep x 19)
3dB Hysteresis
30
20
-10
0
10
20
30
40
50
60
70
80
90
100 110 120
130
Input Signal Level [dBuV]
No.A2341-26/28
LV25810PEB
PLL
The LO_OSC frequency divider (P_CTR) output is compared with the reference frequency (R_CTR) so that they will
have a zero phase difference. It makes output voltage of VT.
Local Oscillator
LO oscillator consists of the internal varactor and the internal inductor. The frequency of this oscillator is from
261.2MHz to 433.6MHz.
IF BPF ‚ AGC AMP block
[ Phase-Shift-Control, Level-Mismatch-Control ]
Detect level differences and phase differences of I/Q.
Details are shown in software control manual.
[ BPF, IF-AGC-Amp ]
Gain and band-change function is included in the IF-BPF.
FM : +18dB (Full-Gain) to 0dB, 6dB steps
AM : +18dB (Full-Gain) to -12dB, 6dB steps
Details are shown in software control manual.
AM IQ MIX
The AM RF signal, from 144 kHz to 26.1 MHz, is converted into approximately 60 kHz IF signal which generates the
I- and Q-signal. A +/− 45° phases down conversion output, which are added into the I-signal and Q-signal output,
removes the square wave component (3rd, 5th order undesired elements) at the MIX output. The image component is
removed in the IQ-mixer.
FM IQ MIX
The FM RF signal, from 65 MHz to 108 MHz, is converted into 300 kHz IF signal which generates the I- and Q-signal.
A +/− 45° phases down conversion output, which are added into I-signal and Q-signal outputs, removes the square
wave component (3rd, 5th order undesired elements) at the MIX output. The image component is removed in the
IQ-mixer.
No.A2341-27/28
LV25810PEB
ORDERING INFORMATION
Device
LV25810PEB-6156H
Package
QFP80(14X14)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
60 / Tray Foam
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warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
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harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
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PS No.A2341-28/28
Mouser Electronics
Authorized Distributor
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