FM25LX64 64Kb Serial 1.5V F-RAM Memory FEATURES

FM25LX64  64Kb Serial 1.5V F-RAM Memory FEATURES
Preliminary
FM25LX64
64Kb Serial 1.5V F-RAM Memory
FEATURES
64K bit Ferroelectric Nonvolatile RAM
 Organized as 8,192 x 8 bits
 High Endurance 1 Trillion (1012) Read/Writes
 36 Year Data Retention at +75ºC
 NoDelay™ Writes
 Advanced High-Reliability Ferroelectric Process
Fast SPI Interface
 Up to 20 MHz Frequency
 SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
 Software Write-Protection (BP bits)
 Hardware Write-Protect (/WP pin)
DESCRIPTION
The FM25LX64 is a 1.5V 64-kilobit nonvolatile
memory employing an advanced ferroelectric
process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes
like a RAM. It provides reliable data retention for 36
years while eliminating the complexities, overhead,
and system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM25LX64 performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after each byte has
been successfully transferred to the device. The next
bus cycle may commence immediately without the
need for data polling. In addition, the product offers
substantial write endurance compared with other
nonvolatile memories. The FM25LX64 is capable of
supporting 1012 read/write cycles, or 1 million times
more write cycles than EEPROM.
These capabilities make the FM25LX64 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25LX64 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25LX64 uses the high-speed
SPI bus, which enhances the high-speed write
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.1
Feb. 2012
Active-Low RESET Input
 Holds Device in Reset State While Power
Stabilizes
 Reduces Time to First F-RAM Access
 Allows Freedom of Power Supply Ramp Rates
Low Voltage/ Low Energy Consumption
 Low Voltage Operation 1.5V +0.15V, -0.1V
 20 A (typ.) Active Current at 1 MHz
 0.1 A (typ.) Standby Current
Industry Standard Configuration
 Industrial Temperature -40C to +85C
 8-pin “Green”/RoHS SOIC Package
capability
of
F-RAM
technology.
Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
PIN CONFIGURATION
CS
SO
WP
1
8
2
7
3
6
VDD
RST
SCK
VSS
4
5
SI
Pin Name
/CS
SCK
SI
SO
/RST
/WP
VDD
VSS
Function
Chip Select
Serial Clock
Serial Data Input
Serial Data Output
Reset Input
Write Protect Input
Supply Voltage
Ground
Ordering Information
FM25LX64-G
“Green” 8-pin SOIC
FM25LX64-GTR
“Green” 8-pin SOIC,
Tape & Reel
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
RST
Instruction Decode
Clock Generator
Control Logic
Write Protect
CS
SCK
1,024 x 64
FRAM Array
Instruction Register
Address Register
Counter
SI
13
8
Data I/O Register
SO
3
Nonvolatile Status
Register
Figure 1. Block Diagram
PIN DESCRIPTIONS
Pin Name
/RST
I/O
Input
/CS
Input
SCK
Input
SI
Input
SO
Output
/WP
Input
VDD
VSS
Supply
Supply
Rev. 1.1
Feb. 2012
Description
Reset Input: This active-low pin is used to hold the memory in a reset state while
power is being stabilized. When /RST is low, the interface is inactive and the SPI state
machine is reset. Once Vdd is within spec, the /RST pin may be driven high. The
memory is ready for commands within tPU.
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode and ignores other inputs. When low, the device internally
activates the SCK signal. A falling edge on /CS must occur prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the rising edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
Serial Output: This is the data output pin. It behaves differently from a standard SPI
SO pin. Data is driven during a read from the rising edge of SCK instead of the falling
edge. SO is driven at all times.
Write Protect: This active low pin prevents write operations to the status register only.
A complete explanation of write protection is provided on pages 7 and 8.
Power Supply (1.4V to 1.65V)
Ground
Page 2 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
OVERVIEW
The FM25LX64 is a 1.5V serial F-RAM memory. The memory array is logically organized as 8,192 x 8 and is
accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is
similar to serial EEPROMs. The major difference between the FM25LX64 and a serial EEPROM with the same
pinout is the F-RAM’s superior write performance.
MEMORY ARCHITECTURE
When accessing the FM25LX64, the user addresses 8,192 locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select, an op-code, and
a two-byte address. The upper 3 bits of the address range are ‘don’t care’ values. The complete address of 13-bits
specifies each byte address uniquely.
Most functions of the FM25LX64 either are controlled by the SPI interface or are handled automatically by onboard circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial
protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus
transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in
the interface section.
Users expect several obvious system benefits from the FM25LX64 due to its fast write cycle and high endurance
as compared to EEPROM. In applications that have a limited power budget, the fast-write and low-power
operation provides a much lower energy solution for nonvolatile store compared to EEPROM since the access is
completed quicker and at a very low voltage. By contrast, an EEPROM requires milliseconds to perform a write
operation and at much higher currents.
RESET
A reset input (/RST) is provided as a means to hold the memory interface in a reset state during power cycle
events. When /RST is driven low, the memory enters a reset condition. In this state, the interface is locked out
and the SO pin is high impedance. When /RST is driven high, the memory enters a normal operating mode after
the tPU time is satisfied. Driving /RST low during a read or write operation will abort the operation and data may
be lost.
Note: The FM25LX64 contains no power management circuits. To ensure proper operation, the user is
responsible for /RST being held active (low) while VDD voltage stabilizes and is within the specified DC
min/max limits. It is recommended that the part is not powered down with chip enable active.
SERIAL PERIPHERAL INTERFACE – SPI BUS
The FM25LX64 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 20
MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller.
Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate
the port using ordinary port pins for microcontrollers that do not. The FM25LX64 operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system
configuration uses a single FM25LX64 device with a microcontroller that has a dedicated SPI port, as Figure 2
illustrates. Note that there may be additional delay required in the SO path to account for proper data output hold
timing. A one-gate buffer ‘1G125 is shown.
For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. Figure 3 shows a
configuration that uses the MCU GPIO pins.
Rev. 1.1
Feb. 2012
Page 3 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
SCK
MOSI
MISO
‘1G125
SPI
Microcontroller
SO
SI
SCK
FM25LX64
CS RST
SS
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
System
Reset
Figure 2. System Configuration with SPI port
P1.0
P1.1
P1.2
Microcontroller
SO
SI SCK
FM25LX64
P1.3
CS
RST
System
Reset
Figure 3. System Configuration without SPI port
OPERATING VOLTAGE
It should be noted that the operating voltage range allow the use of 1.5V and 1.6V voltage regulators that are
spec’d to an output voltage of ±3%. A 1.5V regulator with a ±3% has a VOUT min of 1.455V and a max of
1.545V. A 1.6V regulator with a ±3% has a VOUT min of 1.552V and a max of 1.648V. The FM25LX64 is spec’d
to operate from VDD = 1.40V to 1.65V which meets both voltage rail tolerances.
Protocol Overview
The SPI interface is a synchronous serial interface using clock and data pins. Once chip select is activated by the
bus master, the FM25LX64 will begin monitoring the clock and data lines. The relationship between the falling
edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI
mode on the falling edge of each chip select. While there are four such modes, the FM25LX64 supports Modes 0
and 3. Figure 4 shows the required signal relationships for Modes 0 and 3. For both modes, data is clocked into
the FM25LX64 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If
the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising
edge.
The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is
activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and
data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data
transfer.
Rev. 1.1
Feb. 2012
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FM25LX64 - 64Kb 1.5V SPI F-RAM
Important: The /CS pin must go inactive after an operation is complete and before a new op-code can be
issued. There is one valid op-code only per active chip select.
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Power Up to First Access
The FM25LX64 is not accessible for a period of time (tPU) after power up. Users must comply with the timing
parameter tPU, which is the minimum time from /RST deasserted to the first /CS low.
Data Transfer
All data transfers to and from the FM25LX64 occur in 8-bit groups. They are synchronized to the clock signal
(SCK), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK.
Outputs are driven from the rising edge of SCK. This is different compared to a standard SPI device.
Command Structure
There are six commands called op-codes that can be issued by the bus master to the FM25LX64. They are listed
in the table below. These op-codes control the functions performed by the memory. They can be divided into
three categories. First, there are commands that have no subsequent operations. They perform a single function
such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate
on the Status Register. The third group includes commands for memory transactions followed by address and one
or more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE Write Memory Data
Rev. 1.1
Feb. 2012
Op-code
Hex
0000
0000
0000
0000
0000
0000
0x06
0x04
0x05
0x01
0x03
0x02
0110b
0100b
0101b
0001b
0011b
0010b
Page 5 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
WREN – Set Write Enable Latch
The FM25LX64 will power up with writes disabled. The WREN command must be issued prior to any write
operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations.
These include writing the Status Register (WRSR) and writing the memory (WRITE).
Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the Status Register,
called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the
WEL bit in the Status Register has no effect on the state of this bit – only the WREN op-code can set this bit.
The WEL bit will be automatically cleared on the rising edge of /CS following a WRDI, a WRSR, or a WRITE
operation. This prevents further writes to the Status Register or the F-RAM array without another WREN
command. Figure 5 below illustrates the WREN command bus configuration.
WRDI – Write Disable
The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that
writes are disabled by reading the WEL bit in the Status Register and verifying that WEL=0. Figure 6 illustrates
the WRDI command bus configuration.
CS
0
1
2
3
4
5
6
7
0
1
1
0
SCK
SI
0
0
0
0
SO
Figure 5. WREN Bus Timing
CS
0
1
2
3
4
5
6
7
0
1
0
0
SCK
SI
0
0
0
0
SO
Figure 6. WRDI Bus Timing
RDSR – Read Status Register
The RDSR command allows the bus master to verify the contents of the Status Register. Reading Status
provides information about the current state of the write protection features. Following the RDSR op-code, the
FM25LX64 will return one byte with the contents of the Status Register. The Status Register is described in
detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select certain write protection features by writing a byte to the Status
Register. Prior to issuing a WRSR command, the /WP pin must be high or inactive. Note that on the
FM25LX64, /WP only prevents writing to the Status Register, not the memory array. Prior to sending the
Rev. 1.1
Feb. 2012
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FM25LX64 - 64Kb 1.5V SPI F-RAM
WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR
command is a write operation and therefore clears the Write Enable Latch.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
1
7
SO
6
5
4
3
2
1
0
Figure 7. RDSR Bus Timing
CS
SCK
SI
SO
Figure 8. WRSR Bus Timing (WREN not shown)
STATUS REGISTER & WRITE PROTECTION
The write protection features of the FM25LX64 are multi-tiered. A WREN op-code must be issued prior to any
write operation. Assuming that writes are enabled using WREN, writes to memory are controlled by the Status
Register. As described above, writes to the Status Register are performed using the WRSR command and
subject to the /WP pin. The Status Register is organized as follows.
Table 2. Status Register
Bit
Name
7
WPEN
6
0
5
0
4
0
3
BP1
2
BP0
1
WEL
0
0
Bits 0 and 4-6 are fixed at 0 and cannot be modified. Note that bit 0 (“Ready” in EEPROMs) is unnecessary as
the F-RAM writes in real-time and is never busy. The WPEN, BP1 and BP0 control write protection features.
They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Latch. Attempting
to directly write the WEL bit in the Status Register has no effect on its state. This bit is internally set and
cleared via the WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected
as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0
Protected Address Range
0
0
None
0
1
1800h to 1FFFh (upper ¼)
1
0
1000h to 1FFFh (upper ½)
1
1
0000h to 1FFFh (all)
The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from
writes. The remaining write protection features protect inadvertent changes to the block protect bits.
Rev. 1.1
Feb. 2012
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FM25LX64 - 64Kb 1.5V SPI F-RAM
The WPEN bit controls the effect of the hardware /WP pin. When WPEN is low, the /WP pin is ignored. When
WPEN is high, the /WP pin controls write access to the Status Register. Thus the Status Register is write
protected if WPEN=1 and /WP=0.
This scheme provides a write protection mechanism, which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and BP0 are set to 1, the WPEN bit is set to 1, and /WP is set
to 0. This occurs because the block protect bits prevent writing memory and the /WP signal in hardware
prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be
involved in allowing a write operation. The following table summarizes the write protection conditions.
Table 4. Write Protection
WEL
WPEN
/WP
0
X
X
1
0
X
1
1
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
Unprotected
MEMORY OPERATION
The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the
F-RAM technology. Unlike SPI-bus EEPROMs, the FM25LX64 can perform sequential writes at bus speed. No
page register is needed and any number of sequential writes may be performed.
Write Operation
All writes to the memory begin with a WREN op-code with /CS being asserted and deasserted. The next op-code
is WRITE. The WRITE op-code is followed by a two-byte address value. The upper 3-bits of the address are
ignored. In total, the 13-bits specify the address of the first data byte of the write operation. This is the starting
address of the first data byte of the write operation. Subsequent bytes are data bytes, which are written
sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and keeps
/CS low. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is written MSB first.
The rising edge of /CS terminates a WRITE operation. A write operation is shown in Figure 9.
EEPROMs use page buffers to increase their write throughput. This compensates for the technology’s inherently
slow write operations. F-RAM memories do not have page buffers because each byte is written to the F-RAM
array immediately after it is clocked in (after the 8th clock). This allows any number of bytes to be written
without page buffer delays.
CS
0
1
2
3
4
5
6
7
0
1
2
X
X
X
3
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
9
8
3
2
1
0
7
6
Data
5 4
3
2
1
0
SCK
op-code
SI
0
0
0
0
0
13-bit Add ress
0
1
0
12
11 10
MSB
LSB MSB
LSB
SO
Figure 9. Memory Write (WREN not shown)
Read Operation
After the falling edge of /CS, the bus master can issue a READ op-code. Following the READ command is a twobyte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first
byte of the read operation. This is the starting address of the first byte of the read operation. After the op-code and
address are issued, the device drives out the read data on the next 8 clocks. The SI input is ignored during read
data bytes. Subsequent bytes are data bytes, which are read out sequentially. Addresses are incremented internally
Rev. 1.1
Feb. 2012
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FM25LX64 - 64Kb 1.5V SPI F-RAM
as long as the bus master continues to issue clocks and /CS is low. If the last address of 1FFFh is reached, the
counter will roll over to 0000h. Data is read MSB first. The rising edge of /CS terminates a READ operation. A
read operation is shown in Figure 10.
CS
0
1
2
3
4
5
6
7
0
1
X
X
2
3
4
5
6
7
4
9
8
3
5
6
7
1
0
0
1
2
3
4
5
6
7
SCK
14-bit Address
op-code
SI
0
0
0
0
0
0
1
1
13 12 11 10
MSB
2
LSB
SO
Data
MSB
7
6
5
4
3
LSB
2
1
0
Figure 10. Memory Read
ENDURANCE
The FM25LX64 devices are capable of being accessed at least 10 14 times, reads or writes. An F-RAM memory
operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each
access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns.
Rows are defined by A12-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array
as 1K rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are
read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential
64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and
write endurance is virtually unlimited even at 20MHz clock rate.
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq
Endurance
Endurance
Years to Reach
(MHz)
Cycles/sec.
Cycles/year
Limit
20
37,310
1.18 x 1012
85.1
10
18,660
5.88 x 1011
170.2
5
9,330
2.94 x 1011
340.3
Rev. 1.1
Feb. 2012
Page 9 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
Ratings
-1.0V to +2.4V
-1.0V to +2.4V
and VIN < VDD+0.7V
-55C to + 125C
260 C
TBD
TBD
TBD
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD = 1.4V to 1.65V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units
VDD
Power Supply Voltage
1.40
1.5
1.65
V
IDD
VDD Supply Current
@ SCK = 1.0 MHz
20
60
µA
@ SCK = 20.0 MHz
400
900
µA
ISB
Standby Current
/RST High
0.1
3
A
/RST Low
20
50
A
ILI
Input Leakage Current
1
A
ILO
Output Leakage Current
1
A
VIH
Input High Voltage
0.75 VDD
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.25 VDD
V
VOH
Output High Voltage
VDD – 0.3
V
@ IOH = -1 mA
VOL
Output Low Voltage
0.2
V
@ IOL = 1 mA
Notes
1. SCK toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V. SO=open.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD.
3. VSS  VIN  VDD and VSS  VOUT  VDD.
Rev. 1.1
Feb. 2012
Notes
1
2
3
3
Page 10 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
AC Parameters (TA = -40 C to + 85 C, CL = 30pF, VDD = 1.4V to 1.65V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
fCK
SCK Clock Frequency
0
20
MHz
tCH
Clock High Time
22
ns
1
tCL
Clock Low Time
22
ns
1
tCSU
Chip Select Setup
10
ns
tCSH
Chip Select Hold
10
ns
tOD
Output Disable Time
20
ns
2
tODV
Output Data Valid Time
20
ns
tOH
Output Hold Time
0
ns
tD
Deselect Time
60
ns
tR
Data In Rise Time
50
ns
2,3
tF
Data In Fall Time
50
ns
2,3
tSU
Data Setup Time
5
ns
tH
Data Hold Time
5
ns
Notes
1.
2.
3.
tCH + tCL = 1/fCK.
Characterized but not 100% tested in production.
Rise and fall times measured between 10% and 90% of waveform.
Capacitance (TA = 25 C, f=1.0 MHz, VDD = 1.5V)
Symbol Parameter
CO
Output Capacitance (SO)
CI
Input Capacitance
Notes
1.
Min
-
Max
8
6
Units
pF
pF
Notes
1
1
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
Data Retention
Symbol
Parameter
TDR
@ +85ºC
@ +80ºC
@ +75ºC
Rev. 1.1
Feb. 2012
10% and 90% of VDD
5 ns
0.5 VDD
30 pF
Min
10
18
36
Max
-
Units
Years
Years
Years
Notes
Page 11 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
Serial Data Bus Timing
tD
CS
tCSU
tF
1/tCK
tCL
tR
tCH
tCSH
SCK
tSU
tH
SI
tOH
tODV
tOD
SO
Power Cycle Timing
VDD
VDD min
tVF
tVR
tRS
tRH
RST
tPU
tPD
CS
Power Cycle Timing (TA = -40 C to + 85 C, VDD = 1.4V to 1.65V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
tPU
/RST High to First Access Start
15
s
tPD
Last Access Complete to VDD(min)
0.2
s
tVR
VDD Rise Time
1
s/V
tVF
VDD Fall Time
1
s/V
tRH
/RST Hold Time after VDD(min) at Power Up
0
s
tRS
/RST Setup Time to VDD(min) at Power Down
0
s
Notes
1. Slope measured at any point on VDD waveform.
Rev. 1.1
Feb. 2012
Notes
1
1
Page 12 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
MECHANICAL DRAWING
8-pin SOIC (JEDEC MS-012 variation AA)
Recommended PCB Footprint
7.70
3.90 ±0.10
3.70
6.00 ±0.20
2.00
Pin 1
0.65
1.27
4.90 ±0.10
1.27
0.33
0.51
0.25
0.50
1.35
1.75
0.10
0.25
0.10 mm
0- 8
0.19
0.25
45 
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXXP
RLLLLLLL
RICYYWW
Legend:
XXXXXXX= part number, P= package type (G=SOIC)
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM25LX64, “Green” SOIC package, Year 2011, Work Week 47
FM25LX64G
ESA00002G1
RIC1147
Rev. 1.1
Feb. 2012
Page 13 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
REVISION HISTORY
Revision
1.0
1.1
Rev. 1.1
Feb. 2012
Date
11/8/2011
12/5/2011
Summary
Initial Release
Updated DC specs and timing diagrams (SO never tri-states)
Page 14 of 14
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