LH28F128BFHT- PBTL75A Flash Memory 16Mbit (8Mbitx16)

LH28F128BFHT- PBTL75A Flash Memory 16Mbit (8Mbitx16)
PRELIMINARY PRODUCT SPECIFICATION
Integrated Circuits Group
LH28F128BFHTPBTL75A
Flash Memory
16Mbit (8Mbitx16)
(Model Number: LHF12F17)
Spec. Issue Date: June 7, 2004
LHF12F17
• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,
full or in part, of this material is prohibited without the express written permission of the company.
• When using the products covered herein, please observe the conditions written herein and the precautions outlined in
the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly
adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the
products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure
to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph
(3).
• Office electronics
• Instrumentation and measuring equipment
• Machine tools
• Audiovisual equipment
• Home appliance
• Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high
reliability, should first contact a sales representative of the company and then accept responsibility for
incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring
reliability and safety of the equipment and the overall system.
• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
• Mainframe computers
• Traffic control systems
• Gas leak detectors and automatic cutoff devices
• Rescue and security equipment
• Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely high performance
in terms of functionality, reliability, or accuracy.
• Aerospace equipment
• Communications equipment for trunk lines
• Control equipment for the nuclear power industry
• Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales
representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 0.04
LHF12F17
1
CONTENTS
PAGE
PAGE
56-Lead TSOP (Normal Bend) Pinout ....................... 3
1 Electrical Specifications ........................................ 19
Pin Descriptions.......................................................... 4
1.1 Absolute Maximum Ratings........................... 19
Simultaneous Operation Modes
Allowed with 6 Planes........................................ 5
1.2 Operating Conditions ..................................... 19
1.2.1 Capacitance.............................................. 20
Memory Map .............................................................. 6
1.2.2 AC Input/Output Test Conditions............ 20
Identifier Codes and OTP Address
for Read Operation ............................................. 9
OTP Block Address Map for OTP Program............. 10
1.2.3 DC Characteristics................................... 21
1.2.4 AC Characteristics
- Read-Only Operations............................ 23
Bus Operation............................................................ 11
Command Definitions .............................................. 12
1.2.5 AC Characteristics
- Write Operations .................................... 27
Functions of Block Lock and Block Lock-Down..... 14
1.2.6 Reset Operations...................................... 29
Block Locking State Transitions
upon Command Write....................................... 14
1.2.7 Block Erase, Full Chip Erase,
(Page Buffer) Program and
OTP Program Performance ...................... 30
Block Locking State Transitions
upon WP#/ACC Transition .............................. 15
Status Register Definition......................................... 16
Extended Status Register Definition ........................ 18
Rev. 0.04
LHF12F17
2
LH28F128BFHT-PBTL75A
128Mbit (8Mbit×16)
Page Mode Dual Work Flash MEMORY
„ 128-M density with 16-bit I/O Interface
„ High Performance Reads
• 75/25ns 8-Word Page Mode
„ 6-Plane Dual Work Operation
• Read operations are available during Block Erase or
(Page Buffer) Program between two different Planes
• Plane Architecture:
16M, 24M, 24M, 24M, 24M, 16M
„ Low Power Operation
• 2.7V Read and Write Operations
• VCCQ for Input/Output Power Supply Isolation
• Automatic Power Savings Mode reduces ICCR
in Static Mode
„ Enhanced Code + Data Storage
• 5µs Typical Erase/Program Suspends
„ OTP (One Time Program) Block
• 4-Word Factory-Programmed Area
• 4-Word User-Programmable Area
„ High Performance Program with Page Buffer
• 16-Word Page Buffer
• 5µs/Word (Typ.) at WP#/ACC=9.5V
„ Operating Temperature -40°C to +85°C
„ CMOS Process (P-type silicon substrate)
„ Flexible Blocking Architecture
• Eight 4-Kword Parameter Blocks
• Two-hundred and fifty-five 32-Kword Main Blocks
• Bottom Parameter Location
„ Enhanced Data Protection Features
• Individual Block Lock and Block Lock-Down with
Zero-Latency
• All blocks are locked at power-up or device reset.
• Block Erase, Full Chip Erase, (Page Buffer) Word
Program Lockout during Power Transitions
„ Automated Erase/Program Algorithms
• 3.0V Low-Power 11µs/Word (Typ.)
Programming
• 9.5V No Glue Logic 9µs/Word (Typ.)
Production Programming and 0.8s Erase (Typ.)
„ Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
„ Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
„ 56-Lead TSOP (Normal Bend)
„ ETOXTM* Flash Technology
„ Not designed or rated as radiation hardened
The product, which is 6-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low
power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can
operate at VCC=2.7V-3.3V. Its low voltage operation capability greatly extends battery life for portable applications.
The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus
eliminating time consuming wait states.
The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as an unique number.
* ETOX is a trademark of Intel Corporation.
Rev. 0.04
LHF12F17
NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-LEAD TSOP
STANDARD PINOUT
14mm x 20mm
TOP VIEW
3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
NC
NC
Figure 1. 56-Lead TSOP (Normal Bend) Pinout
Rev. 0.04
LHF12F17
4
Table 1. Pin Descriptions
Symbol
Type
A22-A0
INPUT
DQ15-DQ0
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code and
identifier code reads. Data pins float to high-impedance (High Z) when the chip or
outputs are deselected. Data is internally latched during an erase or program cycle.
CE#
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to
standby levels.
RST#
INPUT
RESET: When low (VIL), RST# resets internal automation and inhibits write operations
which provides data protection. RST#-high (VIH) enables normal operation. After
power-up or reset mode, the device is automatically set to read array mode. RST# must
be low during power-up/down.
OE#
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
INPUT/
SUPPLY
WRITE PROTECT: When WP#/ACC is VIL, locked-down blocks cannot be unlocked.
Erase or program operation can be executed to the blocks which are not locked and not
locked-down. When WP#/ACC is VIH, lock-down is disabled.
Applying 9.5V±0.5V to WP#/ACC provides fast erasing or fast programming mode. In
this mode, WP#/ACC is power supply pin. Applying 9.5V±0.5V to WP#/ACC during
erase/program can only be done for a maximum of 1,000 cycles on each block. WP#/
ACC may be connected to 9.5V±0.5V for a total of 80 hours maximum. Use of this pin
at 9.5V+0.5V beyond these limits may reduce block cycling capability or cause
permanent damage.
WE#
WP#/ACC
RY/BY#
Name and Function
ADDRESS INPUTS: Inputs for addresses.
READY/BUSY#: Indicates the status of the internal WSM (Write State Machine). When
low, WSM is performing an internal operation (block erase, full chip erase, (page buffer)
OPEN DRAIN
program or OTP program). RY/BY#-High Z indicates that the WSM is ready for new
OUTPUT
commands, block erase is suspended and (page buffer) program is inactive, (page buffer)
program is suspended, or the device is in reset mode.
VCC
SUPPLY
DEVICE POWER SUPPLY (2.7V-3.3V): With VCC≤VLKO, all write attempts to the
flash memory are inhibited. Device operations at invalid VCC voltage (see DC
Characteristics) produce spurious results and should not be attempted.
VCCQ
SUPPLY
INPUT/OUTPUT POWER SUPPLY (2.7V-3.3V): Power supply for all input/output
pins.
GND
SUPPLY
GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internally connected; it may be driven or floated.
Rev. 0.04
LHF12F17
5
Table 2. Simultaneous Operation Modes Allowed with 6 Planes (1, 2)
THEN THE MODES ALLOWED IN THE OTHER PLANE IS:
IF ONE
PLANE IS:
Read
Read Read
Array ID/OTP Status
Read
Word
Query Program
Block
Page
OTP
Block Full Chip Program
Erase
Buffer
Program Erase
Erase Suspend
Suspend
Program
Read Array
X
X
X
X
X
X
X
X
X
Read ID/OTP
X
X
X
X
X
X
X
X
X
Read Status
X
X
X
X
X
X
X
X
Read Query
X
X
X
X
X
X
X
X
Word Program
X
X
X
X
X
Page Buffer
Program
X
X
X
X
X
OTP Program
Block Erase
X
X
X
X
X
X
X
Full Chip Erase
X
X
X
Program
Suspend
X
X
X
X
Block Erase
Suspend
X
X
X
X
X
X
X
X
NOTES:
1. "X" denotes the operation available.
2. Dual Work Restrictions:
Status register reflects WSM (Write State Machine) state.
Only one plane can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
Rev. 0.04
LHF12F17
6
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
Block 86
Block 85
Block 84
Block 83
Block 82
Block 81
Block 80
Block 79
Block 78
Block 77
Block 76
Block 75
Block 74
Block 73
Block 72
Block 71
Block 70
Block 69
Block 68
Block 67
Block 66
Block 65
Block 64
Block 63
Block 62
Block 61
Block 60
Block 59
Block 58
Block 57
Block 56
Block 55
Block 54
Block 53
Block 52
Block 51
Block 50
Block 49
Block 48
Block 47
Block 46
Block 45
Block 44
Block 43
Block 42
Block 41
Block 40
Block 39
278000H - 27FFFFH
270000H - 277FFFH
268000H - 26FFFFH
260000H - 267FFFH
258000H - 25FFFFH
250000H - 257FFFH
248000H - 24FFFFH
240000H - 247FFFH
238000H - 23FFFFH
230000H - 237FFFH
228000H - 22FFFFH
220000H - 227FFFH
218000H - 21FFFFH
210000H - 217FFFH
208000H - 20FFFFH
200000H - 207FFFH
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
178000H - 17FFFFH
170000H - 177FFFH
168000H - 16FFFFH
160000H - 167FFFH
158000H - 15FFFFH
150000H - 157FFFH
148000H - 14FFFFH
140000H - 147FFFH
138000H - 13FFFFH
130000H - 137FFFH
128000H - 12FFFFH
120000H - 127FFFH
118000H - 11FFFFH
110000H - 117FFFH
108000H - 10FFFFH
100000H - 107FFFH
PLANE1 : 24 Mbit
[A22-A0]
PLANE0
PLANE1
[A22-A0]
32-Kword Block 38
32-Kword Block 37
32-Kword Block 36
32-Kword Block 35
32-Kword Block 34
32-Kword Block 33
32-Kword Block 32
32-Kword Block 31
32-Kword Block 30
32-Kword Block 29
32-Kword Block 28
32-Kword Block 27
32-Kword Block 26
32-Kword Block 25
32-Kword Block 24
32-Kword Block 23
32-Kword Block 22
32-Kword Block 21
32-Kword Block 20
32-Kword Block 19
32-Kword Block 18
32-Kword Block 17
32-Kword Block 16
32-Kword Block 15
32-Kword Block 14
32-Kword Block 13
32-Kword Block 12
32-Kword Block 11
32-Kword Block 10
32-Kword Block 9
32-Kword Block 8
4-Kword Block 7
4-Kword Block 6
4-Kword Block 5
4-Kword Block 4
4-Kword Block 3
4-Kword Block 2
4-Kword Block 1
4-Kword Block 0
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
078000H - 07FFFFH
070000H - 077FFFH
068000H - 06FFFFH
060000H - 067FFFH
058000H - 05FFFFH
050000H - 057FFFH
048000H - 04FFFFH
040000H - 047FFFH
038000H - 03FFFFH
030000H - 037FFFH
028000H - 02FFFFH
020000H - 027FFFH
018000H - 01FFFFH
010000H - 017FFFH
008000H - 00FFFFH
007000H - 007FFFH
006000H - 006FFFH
005000H - 005FFFH
004000H - 004FFFH
003000H - 003FFFH
002000H - 002FFFH
001000H - 001FFFH
000000H - 000FFFH
PLANE0 : 16 Mbit
Figure 2.1. Memory Map (Bottom Parameter, Plane 0 and Plane 1)
Rev. 0.04
LHF12F17
7
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
32-Kword
Block 182
Block 181
Block 180
Block 179
Block 178
Block 177
Block 176
Block 175
Block 174
Block 173
Block 172
Block 171
Block 170
Block 169
Block 168
Block 167
Block 166
Block 165
Block 164
Block 163
Block 162
Block 161
Block 160
Block 159
Block 158
Block 157
Block 156
Block 155
Block 154
Block 153
Block 152
Block 151
Block 150
Block 149
Block 148
Block 147
Block 146
Block 145
Block 144
Block 143
Block 142
Block 141
Block 140
Block 139
Block 138
Block 137
Block 136
Block 135
578000H - 57FFFFH
570000H - 577FFFH
568000H - 56FFFFH
560000H - 567FFFH
558000H - 55FFFFH
550000H - 557FFFH
548000H - 54FFFFH
540000H - 547FFFH
538000H - 53FFFFH
530000H - 537FFFH
528000H - 52FFFFH
520000H - 527FFFH
518000H - 51FFFFH
510000H - 517FFFH
508000H - 50FFFFH
500000H - 507FFFH
4F8000H - 4FFFFFH
4F0000H - 4F7FFFH
4E8000H - 4EFFFFH
4E0000H - 4E7FFFH
4D8000H - 4DFFFFH
4D0000H - 4D7FFFH
4C8000H - 4CFFFFH
4C0000H - 4C7FFFH
4B8000H - 4BFFFFH
4B0000H - 4B7FFFH
4A8000H - 4AFFFFH
4A0000H - 4A7FFFH
498000H - 49FFFFH
490000H - 497FFFH
488000H - 48FFFFH
480000H - 487FFFH
478000H - 47FFFFH
470000H - 477FFFH
468000H - 46FFFFH
460000H - 467FFFH
458000H - 45FFFFH
450000H - 457FFFH
448000H - 44FFFFH
440000H - 447FFFH
438000H - 43FFFFH
430000H - 437FFFH
428000H - 42FFFFH
420000H - 427FFFH
418000H - 41FFFFH
410000H - 417FFFH
408000H - 40FFFFH
400000H - 407FFFH
PLANE3 : 24 Mbit
[A22-A0]
PLANE2
PLANE3
[A22-A0]
32-Kword Block 134
32-Kword Block 133
32-Kword Block 132
32-Kword Block 131
32-Kword Block 130
32-Kword Block 129
32-Kword Block 128
32-Kword Block 127
32-Kword Block 126
32-Kword Block 125
32-Kword Block 124
32-Kword Block 123
32-Kword Block 122
32-Kword Block 121
32-Kword Block 120
32-Kword Block 119
32-Kword Block 118
32-Kword Block 117
32-Kword Block 116
32-Kword Block 115
32-Kword Block 114
32-Kword Block 113
32-Kword Block 112
32-Kword Block 111
32-Kword Block 110
32-Kword Block 109
32-Kword Block 108
32-Kword Block 107
32-Kword Block 106
32-Kword Block 105
32-Kword Block 104
32-Kword Block 103
32-Kword Block 102
32-Kword Block 101
32-Kword Block 100
32-Kword Block 99
32-Kword Block 98
32-Kword Block 97
32-Kword Block 96
32-Kword Block 95
32-Kword Block 94
32-Kword Block 93
32-Kword Block 92
32-Kword Block 91
32-Kword Block 90
32-Kword Block 89
32-Kword Block 88
32-Kword Block 87
3F8000H - 3FFFFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
378000H - 37FFFFH
370000H - 377FFFH
368000H - 36FFFFH
360000H - 367FFFH
358000H - 35FFFFH
350000H - 357FFFH
348000H - 34FFFFH
340000H - 347FFFH
338000H - 33FFFFH
330000H - 337FFFH
328000H - 32FFFFH
320000H - 327FFFH
318000H - 31FFFFH
310000H - 317FFFH
308000H - 30FFFFH
300000H - 307FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
PLANE2 : 24 Mbit
Figure 2.2. Memory Map (Bottom Parameter, Plane 2 and Plane 3)
Rev. 0.04
LHF12F17
8
!"#$
!"#$
Figure 2.3. Memory Map (Bottom Parameter, Plane 4 and Plane 5)
Rev. 0.04
LHF12F17
9
Table 3. Identifier Codes and OTP Address for Read Operation
Code
Address
[A15-A0]
Data
[DQ15-DQ0]
Notes
Manufacturer Code
Manufacturer Code
0000H
00B0H
1
Device Code
Device Code
0001H
0011H
1
Block Lock Configuration
Code
Block is Unlocked
DQ0 = 0
2, 3
DQ0 = 1
2, 3
DQ1 = 0
2, 3
DQ1 = 1
2, 3
0080H
OTP-LK
1, 4
0081-0088H
OTP
1, 5
Block is Locked
Block is not Locked-Down
Block
Address
+2
Block is Locked-Down
OTP
OTP Lock
OTP
NOTES:
1. A22-A16 must be the address within the plane to which the Read Identifier Codes/OTP command (90H) has been written.
2. Block Address = The beginning location of a block address within the plane to which the Read Identifier Codes/OTP
command (90H) has been written.
3. DQ15-DQ2 are reserved for future implementation.
4. OTP-LK=OTP Block Lock configuration.
5. OTP=OTP Block data.
Rev. 0.04
LHF12F17
10
[A22-A0]
000088H
Customer Programmable Area
000085H
000084H
Factory Programmed Area
000081H
000080H
Reserved for Future Implementation
(DQ15-DQ2)
Customer Programmable Area Lock Bit (DQ1)
Factory Programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program
(The area outside 80H~88H cannot be used.)
Rev. 0.04
LHF12F17
11
Table 4. Bus Operation(1, 2)
Mode
Notes
RST#
CE#
OE#
WE#
Address
DQ15-0
RY/BY# (8)
6
VIH
VIL
VIL
VIH
X
DOUT
High Z
Output Disable
VIH
VIL
VIH
VIH
X
High Z
X
Standby
VIH
VIH
X
X
X
High Z
X
Read Array
Reset
3
VIL
X
X
X
X
High Z
High Z
Read Identifier
Codes/OTP
6
VIH
VIL
VIL
VIH
See
Table 3
See
Table 3
High Z
Read Query
6,7
VIH
VIL
VIL
VIH
X
DOUT
High Z
Read Status
Register
6
VIH
VIL
VIL
VIH
X
DOUT
X
4,5,6
VIH
VIL
VIH
VIL
X
DIN
X
Write
NOTES:
1. Refer to DC Characteristics for VIL or VIH voltages.
2. X can be VIL or VIH for control pins and addresses.
3. RST# at GND±0.2V ensures the lowest power consumption.
4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably
executed when VCC=2.7V-3.3V.
5. Refer to Table 5 for valid DIN during a write operation.
6. Never hold OE# low and WE# low at the same timing.
7. Query code = Common Flash Interface (CFI) code.
8. RY/BY# is VOL when the WSM (Write State Machine) is executing internal block erase, full chip erase,
(page buffer) program or OTP program algorithms. It is High Z during when the WSM is not busy, in
block erase suspend mode (with program and page buffer program inactive), (page buffer) program suspend
mode, or reset mode.
Rev. 0.04
LHF12F17
12
Table 5. Command Definitions(11)
Command
Read Array
Bus
Cycles
Req’d
First Bus Cycle
Notes
1
Second Bus Cycle
Oper(1)
Addr(2)
Data
Write
PA
FFH
Oper(1)
Addr(2)
Data(3)
Read Identifier Codes/OTP
≥2
4
Write
PA
90H
Read
IA or OA
ID or OD
Read Query
≥2
4
Write
PA
98H
Read
QA
QD
Read
PA
SRD
Read Status Register
2
Write
PA
70H
Clear Status Register
1
Write
PA
50H
Block Erase
2
5
Write
BA
20H
Write
BA
D0H
Full Chip Erase
2
5,9
Write
X
30H
Write
X
D0H
2
5,6
Write
WA
40H or
10H
Write
WA
WD
≥4
5,7
Write
WA
E8H
Write
WA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
8,9
Write
PA
B0H
Block Erase and (Page Buffer)
Program Resume
1
8,9
Write
PA
D0H
Set Block Lock Bit
2
Write
BA
60H
Write
BA
01H
Clear Block Lock Bit
2
Write
BA
60H
Write
BA
D0H
Set Block Lock-down Bit
2
Write
BA
60H
Write
BA
2FH
OTP Program
2
Write
OA
C0H
Write
OA
OD
Program
Page Buffer Program
10
9
NOTES:
1. Bus operations are defined in Table 4.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
bus cycle.
X=Any valid address within the device.
PA=Address within the selected plane.
IA=Identifier codes address (See Table 3).
QA=Query codes address. Refer to Appendix of LH28F128BF series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
3. ID=Data read from identifier codes. (See Table 3).
QD=Data read from query database. Refer to Appendix of LH28F128BF series for details.
SRD=Data read from status register. See Table 9.1, Table 9.2 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever
goes high first) during command write cycles.
OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first)
during command write cycles.
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code and the data within OTP block (See Table 3).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
block can be erased or programmed when RST# is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
Rev. 0.04
LHF12F17
13
7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any
valid address within the target block to be programmed and the confirm command (D0H).
8. If the program operation in one plane is suspended and the erase operation in other plane is also suspended, the suspended
program operation will be resumed first.
9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted
while the block erase operation is being suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP#/ACC is VIL.
When WP#/ACC is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down
configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 0.04
LHF12F17
14
Table 6. Functions of Block Lock(5) and Block Lock-Down
Current State
Erase/Program Allowed (2)
WP#/ACC
DQ1(1)
DQ0(1)
[000]
0
0
0
Unlocked
Yes
[001](3)
0
0
1
Locked
No
[011]
0
1
1
Locked-down
No
[100]
1
0
0
Unlocked
Yes
[101](3)
1
0
1
Locked
No
[110](4)
1
1
0
Lock-down Disable
Yes
[111]
1
1
1
Lock-down Disable
No
State
State Name
NOTES:
1. DQ0=1: a block is locked; DQ0=0: a block is unlocked.
DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, full chip erase and
(page buffer) program operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,
[001] (WP#/ACC=0) or [101] (WP#/ACC=1), regardless of the states before power-off or reset
operation.
4. When WP#/ACC is driven to VIL in [110] state, the state changes to [011] and the blocks are
automatically locked.
5. OTP (One Time Program) block has the lock function which is different from those described
above.
Table 7. Block Locking State Transitions upon Command Write(4)
Current State
Result after Lock Command Written (Next State)
State
WP#/ACC
DQ1
DQ0
Set Lock(1)
Clear Lock(1)
Set Lock-down(1)
[000]
0
0
0
[001]
No Change
[011](2)
[001]
0
0
1
No Change(3)
[000]
[011]
[011]
0
1
1
No Change
No Change
No Change
[100]
1
0
0
[101]
No Change
[111](2)
[101]
1
0
1
No Change
[100]
[111]
[110]
1
1
0
[111]
No Change
[111](2)
[111]
1
1
1
No Change
[110]
No Change
NOTES:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit
command and "Set Lock-down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the
corresponding block is locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that WP#/ACC is not changed and fixed VIL or VIH.
Rev. 0.04
LHF12F17
15
Table 8. Block Locking State Transitions upon WP#/ACC Transition(4)
Current State
Result after WP#/ACC Transition (Next State)
Previous State
[110]
State
WP#/ACC
DQ1
DQ0
WP#/ACC=0→1(1)
WP#/ACC=1→0(1)
[000]
0
0
0
[100]
-
[001]
0
0
1
[101]
-
[110]
-
(2)
Other than
[110](2)
[011]
0
1
1
[111]
-
[100]
1
0
0
-
[000]
-
[101]
1
0
1
-
[001]
-
[110]
1
1
0
-
[011](3)
-
[111]
1
1
1
-
[011]
NOTES:
1. "WP#/ACC=0→1" means that WP#/ACC is driven to VIH and "WP#/ACC=1→0" means that
WP#/ACC is driven to VIL.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When WP#/ACC is driven to VIL in [110] state, the state changes to [011] and the blocks are
automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in
previous, current and next state.
Rev. 0.04
LHF12F17
16
Table 9.1. Status Register Definition
GWSMS
GBESS
GBEFCES
GPBPOPS
GWPACCS
GPBPSS
GDPS
R
15
14
13
12
11
10
9
8
PWSMS
GBESS
GBEFCES
GPBPOPS
GWPACCS
GPBPSS
GDPS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = PLANE WRITE STATE MACHINE STATUS
(PWSMS)
1 = Ready
0 = Busy
Status Register indicates the status of the WSM (Write State
Machine). However, SR.7 indicates the status of WSM in
each plane. Even if the SR.7 is "1", the WSM may be
occupied by the other plane.
SR.6 = GLOBAL BLOCK ERASE SUSPEND STATUS
(GBESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
In the plane to which the command is issued, Check SR.7 or
RY/BY# to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
SR.5 = GLOBAL BLOCK ERASE AND
FULL CHIP ERASE STATUS (GBEFCES)
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (page buffer) program, set/clear block lock bit, set
block lock-down bit attempt, an improper command
sequence was entered.
SR.4 = GLOBAL (PAGE BUFFER) PROGRAM AND
OTP PROGRAM STATUS (GPBPOPS)
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
SR.3 = GLOBAL WP#/ACC STATUS (GWPACCS)
1 = VCCQ+0.4V < WP#/ACC < 9.0V Detect,
Operation Abort
0 = WP#/ACC OK
SR.2 = GLOBAL (PAGE BUFFER) PROGRAM
SUSPEND STATUS (GPBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = GLOBAL DEVICE PROTECT STATUS (GDPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.3 does not provide a continuous indication of WP#/ACC
level. The WSM interrogates and indicates the WP#/ACC
level only after Block Erase, Full Chip Erase, (Page Buffer)
Program or OTP Program command sequences. SR.3 is not
guaranteed to report accurate feedback when WP#/
ACC≠VACCH.
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.0 is reserved for future use and should be masked out
when polling the status register.
Rev. 0.04
LHF12F17
17
Table 9.2. Status Register Definition (Continued)
NOTES:
SR.15 = GLOBAL WRITE STATE MACHINE STATUS
(GWSMS)
1 = Ready
0 = Busy
Status Register SR.15-SR.9 indicates the status of the WSM.
Check SR.15 or RY/BY# to determine block erase, full chip
erase, (page buffer) program or OTP program completion.
SR.14 - SR.9 are invalid while SR.15="0".
SR.14 = GLOBAL BLOCK ERASE SUSPEND STATUS
(GBESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.13 = GLOBAL BLOCK ERASE AND
FULL CHIP ERASE STATUS (GBEFCES)
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
If both SR.13 and SR.12 are "1"s after a block erase, full chip
erase, (page buffer) program, set/clear block lock bit, set
block lock-down bit attempt, an improper command
sequence was entered.
SR.12 = GLOBAL (PAGE BUFFER) PROGRAM AND
OTP PROGRAM STATUS (GPBPOPS)
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
SR.11 = GLOBAL WP#/ACC STATUS (GWPACCS)
1 = VCCQ+0.4V < WPP#/ACC < 9.0V Detect,
Operation Abort
0 = WP#/ACC OK
SR.10 = GLOBAL (PAGE BUFFER) PROGRAM
SUSPEND STATUS (GPBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.9 = GLOBAL DEVICE PROTECT STATUS (GDPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.11 does not provide a continuous indication of WP#/ACC
level. The WSM interrogates and indicates the WP#/ACC
level only after Block Erase, Full Chip Erase, (Page Buffer)
Program or OTP Program command sequences. SR.11 is not
guaranteed to report accurate feedback when WP#/
ACC≠VACCH.
SR.9 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.8 is reserved for future use and should be masked out
when polling the status register.
Rev. 0.04
LHF12F17
18
Table 10. Extended Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.15-8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
NOTES:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted.
If XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and
should be masked out when polling the extended status
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) register.
Rev. 0.04
LHF12F17
1 Electrical Specifications
1.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Erase and Program ...-40°C to +85°C (1)
Storage Temperature
During under Bias............................... -40°C to +85°C
During non Bias................................ -65°C to +125°C
Voltage On Any Pin (except VCC, VCCQ and WP#/ACC)
............................................... -0.5V to VCCQ+0.5V (2)
VCC and VCCQ Supply Voltage .......... -0.2V to +3.7V (2)
WP#/ACC Supply Voltage ......... -0.2V to +10.3V (2, 3, 4)
Output Short Circuit Current ........................... 100mA (5)
19
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device
reliability.
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins and
-0.2V on VCC, VCCQ and WP#/ACC pins. During
transitions, this level may undershoot to -2.0V for
periods <20ns. Maximum DC voltage on input/output
pins is VCC+0.5V which, during transitions, may
overshoot to VCC+2.0V for periods <20ns.
3. Maximum DC voltage on WP#/ACC may overshoot to
+11.0V for periods <20ns.
4. WP#/ACC erase/program voltage is normally 2.7V3.3V. Applying 9.0V-10.0V to WP#/ACC during erase/
program can be done for a maximum of 1,000 cycles
on the main blocks and 1,000 cycles on the parameter
blocks. WP#/ACC may be connected to 9.0V-10.0V for
a total of 80 hours maximum.
5. Output shorted for no more than one second. No more
than one output shorted at a time.
1.2 Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
TA
-40
+25
+85
°C
VCC Supply Voltage
VCC
2.7
3.0
3.3
V
1
I/O Supply Voltage
VCCQ
2.7
3.0
3.3
V
1
VIL
-0.2
0.4
V
VIH
2.4
VCCQ
+ 0.4
V
VACCH
9.0
10.0
V
Operating Temperature
WP#/ACC Voltage when Used as a Logic Control
WP#/ACC Supply Voltage
9.5
Main Block Erase Cycling: WP#/ACC=VIL or VIH
100,000
Cycles
Parameter Block Erase Cycling: WP#/ACC=VIL or VIH
100,000
Cycles
Main Block Erase Cycling: WP#/ACC=VACCH, 80 hrs.
1,000
Cycles
Parameter Block Erase Cycling: WP#/ACC=VACCH, 80 hrs.
1,000
Cycles
80
Hours
Maximum WP#/ACC hours at VACCH
Notes
1
1, 2
NOTES:
1. See DC Characteristics tables for voltage range-specific specification.
2. Applying WP#/ACC=9.0V-10.0V during a erase or program can be done for a maximum of 1,000 cycles on the main
blocks and 1,000 cycles on the parameter blocks. A permanent connection to WP#/ACC=9.0V-10.0V is not allowed and
can cause damage to the device.
Rev. 0.04
LHF12F17
20
1.2.1 Capacitance (1) (TA=+25°C, f=1MHz)
Parameter
Symbol
Condition
Input Capacitance
CIN
WP#/ACC Input Capacitance
Output Capacitance
Min.
Typ.
Max.
Unit
VIN=0.0V
4
7
pF
CIN
VIN=0.0V
18
22
pF
COUT
VOUT=0.0V
6
10
pF
NOTE:
1. Sampled, not 100% tested.
1.2.2 AC Input/Output Test Conditions
VCCQ
INPUT
VCCQ/2
TEST POINTS
VCCQ/2 OUTPUT
0.0
AC test inputs are driven at VCCQ(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Worst case speed conditions are when VCC=VCC(min).
Figure 4. Transient Input/Output Reference Waveform for VCC=2.7V-3.3V
Table 11. Test Configuration Capacitance Loading Value
VCCQ(min)/2
1N914
Test Configuration
CL (pF)
VCC=2.7V-3.3V
50
RL=3.3KΩ
DEVICE
UNDER
TEST
CL Includes Jig
Capacitances.
OUT
CL
Figure 5. Transient Equivalent Testing Load Circuit
Rev. 0.04
LHF12F17
21
1.2.3 DC Characteristics
VCC=2.7V-3.3V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
VCC=VCCMax.,
VCCQ=VCCQMax.,
VIN/VOUT=VCCQ or
GND
ILI
Input Load Current
1
-1.0
+1.0
µA
ILO
Output Leakage Current
1
-1.0
+1.0
µA
ICCS
VCC Standby Current
ICCAS
VCC Automatic
Current
ICCD
ICCR
1,7,8
9
40
µA
VCC=VCCMax.,
CE#=RST#=
VCCQ±0.2V,
WP#/ACC=VCCQ or
GND
1,3,7
9
40
µA
VCC=VCCMax.,
CE#=GND±0.2V,
WP#/ACC=VCCQ or
GND
VCC Reset Current
1,7
9
40
µA
RST#=GND±0.2V
Average VCC Read
Current
Normal Mode
1,6,7
20
30
mA
Average VCC Read
8 Word Read
Current
Page Mode
1,6,7
5
10
mA
VCC=VCCMax.,
CE#=VIL,
OE#=VIH,
f=5MHz
1,4,6,7
20
60
mA
WP#/ACC=VIL or VIH
1,4,6,7
10
20
mA
WP#/ACC=VACCH
1,4,6,7
10
30
mA
WP#/ACC=VIL or VIH
1,4,6,7
4
10
mA
WP#/ACC=VACCH
Power
Savings
ICCW
VCC (Page Buffer) Program Current
ICCE
VCC Block Erase,
Full Chip Erase Current
ICCWS
ICCES
VCC (Page Buffer) Program or
Block Erase Suspend Current
1,2,6,7
10
200
µA
CE#=VIH
IACCS
IACCR
WP#/ACC Standby or Read Current
1,5,6,7
2
5
µA
WP#/ACC≤VCC
IACCW
WP#/ACC (Page Buffer) Program 1,4,5,6,7
Current
1,4,5,6,7
2
5
µA
WP#/ACC=VIL or VIH
10
30
mA
WP#/ACC=VACCH
IACCE
WP#/ACC Block Erase,
Full Chip Erase Current
1,4,5,6,7
2
5
µA
WP#/ACC=VIL or VIH
1,4,5,6,7
5
15
mA
WP#/ACC=VACCH
IACCWS
WP#/ACC (Page Buffer) Program
Suspend Current
1,5,6,7
2
5
µA
WP#/ACC=VIL or VIH
1,5,6,7
10
200
µA
WP#/ACC=VACCH
IACCES
WP#/ACC
Current
Suspend 1,5,6,7
1,5,6,7
2
5
µA
WP#/ACC=VIL or VIH
10
200
µA
WP#/ACC=VACCH
Block
Erase
Rev. 0.04
LHF12F17
22
DC Characteristics (Continued)
VCC=2.7V-3.3V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
5
-0.4
0.4
V
VIH
Input High Voltage
4
2.4
VCCQ
+ 0.4
V
VOL
Output Low Voltage
4,8
0.2
VOH
Output High Voltage
4
VCCQ
-0.2
VACCH
WP#/ACC during Block Erase, Full
Chip Erase, (Page Buffer) Program or
OTP Program Operations
5
9.0
VLKO
VCC Lockout Voltage
1.5
9.5
10.0
Test Conditions
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOL=100µA
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOH=-100µA
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V, VCCQ=3.0V and
TA=+25°C unless VCC is specified.
2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block
erase suspend mode, the device’s current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page
buffer) program suspend mode, the device’s current draw is the sum of ICCWS and ICCR.
3. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (tAVQV) provide new data when addresses are changed.
4. Sampled, not 100% tested.
5. Applying 9.5V±0.5V to WP#/ACC provides fast erasing or fast programming mode. In this mode, WP#/ACC is power
supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power
supply trace widths and layout considerations given to the VCC power bus.
Applying 9.5V±0.5V to WP#/ACC during erase/program can only be done for a maximum of 1,000 cycles on each block.
WP#/ACC may be connected to 9.5V±0.5V for a total of 80 hours maximum.
6. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
7. For all pins other than those shown in test conditions, input level is VCCQ or GND.
8. Includes RY/BY#.
Rev. 0.04
LHF12F17
23
1.2.4 AC Characteristics - Read-Only Operations(1)
VCC=2.7V-3.3V, TA=-40°C to +85°C
Symbol
Parameter
Notes
Min.
Max.
Unit
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE# to Output Delay
tAPA
Page Address Access Time
tGLQV
OE# to Output Delay
tPHQV
RST# High to Output Delay
tEHQZ, tGHQZ
CE# or OE# to Output in High Z, Whichever Occurs First
2
tELQX
CE# to Output in Low Z
2
0
ns
tGLQX
OE# to Output in Low Z
2
0
ns
tOH
Output Hold from First Occurring Address, CE# or OE# change
2
0
ns
tAVEL, tAVGL
Address Setup to CE#, OE# Going Low
for Reading Status Register
4, 6
10
ns
tELAX, tGLAX
Address Hold from CE#, OE# Going Low
for Reading Status Register
5, 6
10
ns
tEHEL, tGHGL
CE#, OE# Pulse Width High for Reading
Status Register
6
20
ns
75
3
3
ns
75
ns
75
ns
25
ns
20
ns
150
ns
20
ns
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. OE# may be delayed up to tELQV ⎯ tGLQV after the falling edge of CE# without impact to tELQV.
4. Address setup time (tAVEL, tAVGL) is defined from the falling edge of CE# or OE# (whichever goes low last).
5. Address hold time (tELAX, tGLAX) is defined from the falling edge of CE# or OE# (whichever goes low last).
6. Specifications tAVEL, tAVGL, tELAX, tGLAX and tEHEL, tGHGL for read operations apply to only status register read
operations.
Rev. 0.04
LHF12F17
VIH
A22-0 (A)
24
VALID
ADDRESS
tAVAV
VIL
tAVQV
tEHEL
VIH
CE# (E)
VIL
tAVEL
tELAX
tAVGL
tGHGL
tGLAX
VIH
OE# (G)
VIL
tEHQZ
tGHQZ
tELQV
VIH
WE# (W)
VIL
tGLQV
tGLQX
tELQX
VOH
DQ15-0 (D/Q)
High Z
tOH
VALID
OUTPUT
VOL
tPHQV
RST# (P)
VIH
VIL
Figure 6. AC Waveform for Single Asynchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 0.04
LHF12F17
A22-3 (A)
VIH
25
VALID
ADDRESS
VIL
tAVAV
tAVQV
A2-0 (A)
CE# (E)
VIH
VALID
ADDRESS
VALID
ADDRESS
VIL
VALID
ADDRESS
VALID
ADDRESS
VIH
VIL
tELQV
OE# (G)
WE# (W)
tEHQZ
tGHQZ
VIH
VIL
VIH
tGLQV
VIL
tGLQX
tAPA
tELQX
DQ15-0 (D/Q)
VOH
High Z
VALID
OUTPUT
VOL
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
tPHQV
RST# (P)
VIH
VIL
Figure 7. AC Waveform for Asynchronous 4-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 0.04
LHF12F17
A22-3 (A)
VIH
26
VALID
ADDRESS
VIL
tAVAV
tAVQV
A2-0 (A)
CE# (E)
VIH
VIL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VIH
VIL
tEHQZ
tGHQZ
tELQV
OE# (G)
WE# (W)
VIH
VIL
VIH
tGLQV
VIL
tGLQX
tAPA
tELQX
DQ15-0 (D/Q)
VOH
High Z
VOL
VALID
OUTPUT
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tPHQV
RST# (P)
VIH
VIL
Figure 8. AC Waveform for Asynchronous 8-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 0.04
LHF12F17
27
1.2.5 AC Characteristics - Write Operations(1), (2)
VCC=2.7V-3.3V, TA=-40°C to +85°C
Symbol
Parameter
tAVAV
Write Cycle Time
tPHWL (tPHEL)
RST# High Recovery to WE# (CE#) Going Low
tELWL (tWLEL)
CE# (WE#) Setup to WE# (CE#) Going Low
tWLWH (tELEH)
WE# (CE#) Pulse Width
tDVWH (tDVEH)
Notes
Min.
Max.
Unit
75
ns
150
ns
0
ns
4
50
ns
Data Setup to WE# (CE#) Going High
7
40
ns
tAVWH (tAVEH)
Address Setup to WE# (CE#) Going High
7
40
ns
tWHEH (tEHWH)
CE# (WE#) Hold from WE# (CE#) High
0
ns
tWHDX (tEHDX)
Data Hold from WE# (CE#) High
0
ns
tWHAX (tEHAX)
Address Hold from WE# (CE#) High
0
ns
tWHWL (tEHEL)
WE# (CE#) Pulse Width High
5
25
ns
tSHWH (tSHEH)
WP#/ACC High Setup to WE# (CE#) WP#/ACC=VIH
Going High
WP#/ACC=VACCH
3
tWHGL (tEHGL)
Write Recovery before Read
tQVSL
WP#/ACC High Hold from Valid SRD, RY/BY# High Z
tWHR0 (tEHR0)
WE# (CE#) High to SR.7 Going "0"
tWHRL (tEHRL)
WE# (CE#) High to RY/BY# Going Low
3
0
3
ns
200
30
ns
0
ns
3, 6
tAVQV
+50
ns
3
100
ns
NOTES:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and
OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.
5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
6. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns.
7. Refer to Table 5 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
configuration.
Rev. 0.04
LHF12F17
NOTE 1
VIH
A22-0 (A)
VIL
28
NOTE 2
NOTE 3
VALID
ADDRESS
VALID
ADDRESS
tAVAV
tWHAX
(tEHAX)
NOTES 5, 6
VIL
tELWL (tWLEL)
tWHEH (tEHWH)
tWHGL (tEHGL)
NOTES 5, 6
VIH
OE# (G)
NOTE 5
VALID
ADDRESS
tAVWH (tAVEH)
VIH
CE# (E)
NOTE 4
VIL
tPHWL (tPHEL)
tWHWL (tEHEL)
VIH
WE# (W)
VIL
tWLWH
(tELEH )
tWHQV1,2,3 (tEHQV1,2,3)
tWHDX (tEHDX)
tDVWH (tDVEH)
VIH
DQ15-0 (D/Q)
VIL
DATA IN
VALID
SRD
DATA IN
tWHRL (tEHRL)
(tWHR0 (tEHR0))
High Z
RY/BY#
("1")
(R)
(SR.7)
VOL
("0")
VIH
RST# (P)
VIL
tSHWH (tSHEH)
tQVSL
VVIH
IH, VACCH
WP# (S)
WP#/ACC
(S)
VIL
NOTES:
1. VCC power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.
Figure 9. AC Waveform for Write Operations
Rev. 0.04
LHF12F17
29
1.2.6 Reset Operations
tPHQV
RST#
VIH
(P)
VIL
V
DQ15-0 (D/Q) OH
VOL
tPLPH
High Z
VALID
OUTPUT
(A) Reset during Read Array Mode
SR.7="1"
tPLRH
RST#
VIH
VIL
(P)
V
DQ15-0 (D/Q) OH
VOL
ABORT
COMPLETE
tPHQV
tPLPH
High Z
VALID
OUTPUT
(B) Reset during Erase or Program Mode
VCC(min)
VCC
tVHQV
GND
t2VPH
RST#
(P)
tPHQV
VIH
VIL
V
DQ15-0 (D/Q) OH
VOL
High Z
VALID
OUTPUT
(C) RST# rising timing
Figure 10. AC Waveform for Reset Operations
Reset AC Specifications (VCC=2.7V-3.3V, TA=-40°C to +85°C)
Symbol
Parameter
Notes
Min.
100
tPLPH
RST# Low to Reset during Read
(RST# should be low during power-up.)
1, 2, 3
tPLRH
RST# Low to Reset during Erase or Program
1, 3, 4
t2VPH
VCC 2.7V to RST# High
1, 3, 5
tVHQV
VCC 2.7V to Output Delay
3
Max.
Unit
ns
22
100
µs
ns
1
ms
NOTES:
1. A reset time, tPHQV, is required from the later of SR.7 (RY/BY#) going "1" (High Z) or RST# going high until outputs are
valid. Refer to AC Characteristics - Read-Only Operations for tPHQV.
2. tPLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and
also has been in stable there.
Rev. 0.04
LHF12F17
30
1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3)
VCC=2.7V-3.3V, TA=-40°C to +85°C
Symbol
Parameter
Page Buffer WP#/ACC=VIL or VIH WP#/ACC=VACCH
Command is
(In System)
(In Manufacturing)
Unit
Notes
Used or not
(1)
(2) Min.
(1)
(2)
Min.
Typ. Max.
Typ. Max.
Used
tWPB
4-Kword Parameter Block
Program Time
2
Not Used
0.05
0.3
0.04
0.12
s
2
Used
0.03
0.12
0.02
0.06
s
tWMB
32-Kword Main Block
Program Time
2
Not Used
0.38
2.4
0.31
1.0
s
2
Used
0.24
1.0
0.17
0.5
s
tWHQV1/
tEHQV1
Word Program Time
2
Not Used
11
200
9
185
µs
2
Used
7
100
5
90
µs
tWHOV1/
tEHOV1
OTP Program Time
2
Not Used
36
400
27
185
µs
tWHQV2/
tEHQV2
4-Kword Parameter Block
Erase Time
2
-
0.5
4
0.4
4
s
tWHQV3/
tEHQV3
32-Kword Main Block
Erase Time
2
-
0.9
5
0.8
5
s
Full Chip Erase Time
2
240
1400
200
1400
s
tWHRH1/
tEHRH1
(Page Buffer) Program Suspend
Latency Time to Read
4
-
5
10
5
10
µs
tWHRH2/
tEHRH2
Block Erase Suspend
Latency Time to Read
4
-
5
20
5
20
µs
tERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
5
-
500
500
µs
NOTES:
1. Typical values measured at VCC=3.0V, WP#/ACC=3.0V or 9.5V, and TA=+25°C. Assumes corresponding lock bits
are not set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1" or RY/BY#
going High Z.
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter
than tERES and its sequence is repeated, the block erase operation may not be finished.
Rev. 0.04
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tVR
t2VPH
tPHQV
VIH
RP# (P)
(RST#)
VIL
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tF
tR
tELQV
VIH
CE#
(E)
VIL
VIH
WE# (W)
VIL
tF
tR
tGLQV
VIH
OE#
(G)
VIL
DATA
(D/Q)
VOH
VOL
High Z
Valid
Output
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
Min.
Max.
Unit
1
0.5
30000
µs/V
tVR
VCC Rise Time
tR
Input Signal Rise Time
1, 2
1
µs/V
tF
Input Signal Fall Time
1, 2
1
µs/V
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
Input Signal
VIH (Min.)
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, VPP Electric Potential Switching Circuit
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
JAPAN
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Camas, WA 98607, U.S.A.
Phone: (1) 360-834-2500
Fax: (1) 360-834-8903
Fast Info: (1) 800-833-9437
www.sharpsma.com
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Division of Sharp Electronics (Europe) GmbH
Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
Fax: (49) 40-2376-2232
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SHARP Corporation
Electronic Components & Devices
22-22 Nagaike-cho, Abeno-Ku
Osaka 545-8522, Japan
Phone: (81) 6-6621-1221
Fax: (81) 6117-725300/6117-725301
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TAIWAN
SINGAPORE
KOREA
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(Taiwan) Corporation
8F-A, No. 16, Sec. 4, Nanking E. Rd.
Taipei, Taiwan, Republic of China
Phone: (886) 2-2577-7341
Fax: (886) 2-2577-7326/2-2577-7328
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438A, Alexandra Road, #05-01/02
Alexandra Technopark,
Singapore 119967
Phone: (65) 271-3566
Fax: (65) 271-3855
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(Korea) Corporation
RM 501 Geosung B/D, 541
Dohwa-dong, Mapo-ku
Seoul 121-701, Korea
Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
CHINA
HONG KONG
SHARP Microelectronics of China
(Shanghai) Co., Ltd.
28 Xin Jin Qiao Road King Tower 16F
Pudong Shanghai, 201206 P.R. China
Phone: (86) 21-5854-7710/21-5834-6056
Fax: (86) 21-5854-4340/21-5834-6057
Head Office:
No. 360, Bashen Road,
Xin Development Bldg. 22
Waigaoqiao Free Trade Zone Shanghai
200131 P.R. China
Email: [email protected]
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
Shenzhen Representative Office:
Room 13B1, Tower C,
Electronics Science & Technology Building
Shen Nan Zhong Road
Shenzhen, P.R. China
Phone: (86) 755-3273731
Fax: (86) 755-3273735
Mouser Electronics
Authorized Distributor
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LH28F128BFHT-PBTL75A
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