ENABLE

UVLO

Thermal Limit

Current Limit

Soft Start

(-)

PWM

(+)

Comp

Sawtooth

Generator

Logic

Compensation

Network

P-Drive

N-Drive

Error

Amp

(-)

(+)

V

IN

Switch

V

OUT

GND

V

SENSE

V

FB

DAC

VREF

Voltage

Select

Package Boundry

VS0 VS1 VS2

Product Highlights

• Revolutionary integrated inductor

• Very small solution foot print*

• Fully RoHS compliant; MSL 3 260°C reflow

• Only two low cost components required

• 5mm x 4mm x1.1mm QFN package

• Wide 2.4V to 5.5V input range

• 500, 600, 800 mA output current versions

• Less than 1 µA standby current

• 4 MHz switching frequency

• Fast transient response

• Very low ripple voltage; 5mV

p-p

typical

• 3 Pin VID Output Voltage select

• External divider option

• Dynamically adjustable output

• Designed for Low noise/EMI

• Short circuit, UVLO, and thermal protection

Enpirion

®

Power Datasheet

EP5352QI/EP5362QI/EP5382QI

500/600/800mA PowerSoC

Synchronous Buck Regulators

With Integrated Inductor

Product Overview

The Ultra-Low-Profile EP53X2QI product family is targeted to applications where board area and profile are critical. EP53X2QI is a complete power conversion solution requiring only two low cost ceramic MLCC caps. Inductor, MOSFETS,

PWM, and compensation are integrated into a tiny 5mm x 4mm x 1.1mm QFN package. The

EP53x2QI family is engineered to simplify design and to minimize layout constraints. High switching frequency and internal type III compensation provides superior transient response. With a 1.1 mm profile, the EP53x2 is perfect for space and height limited applications.

A 3-pin VID output voltage select scheme provides seven pre-programmed output voltages along with an option for external resistor divider.

Output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling.

Typical Application Circuit

V

IN

ENABLE

V in

V

Sense

V out

V

OUT

2.2uF

Voltage

Select

V

S0

V

S1

V

S2

GND

V

FB

10

µF

Figure 1. Typical application circuit.

Applications

• Area constrained applications

• Mobile multimedia, smartphone & PDA

• Mobile and Cellular platforms

• VoIP and Video phones

• Personal Media Players

• FPGA, DSP, IO & Peripherals

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03132 October 11, 2013 Rev H

Absolute Maximum Ratings

EP5382QI/EP5362QI/EP5352QI

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Input Supply Voltage

PARAMETER SYMBOL

V

IN

MIN

-0.3

MAX

7.0

UNITS

V

Voltages on: ENABLE, V

SENSE

, V

S0

-V

S2

Voltage on: V

FB

Storage Temperature Range

Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A

ESD Rating (based on Human Body Model)

T

STG

-0.3

-0.3

-65

V

IN

+ 0.3

2.7

150

260

2000

V

V

°C

°C

V

Recommended Operating Conditions

PARAMETER

Input Voltage Range

Output Voltage Range

Operating Ambient Temperature

Operating Junction Temperature

Thermal Characteristics

SYMBOL

V

IN

V

OUT

T

A

T

J

MIN

2.4

0.6

-40

-40

MAX

5.5

V

IN

-0.45

+85

+125

UNITS

V

V

°C

°C

PARAMETER

Thermal Resistance: Junction to Ambient (0 LFM)

Thermal Resistance: Junction to Case (0 LFM)

Thermal Shutdown

Thermal Shutdown Hysteresis

Electrical Characteristics

SYMBOL

θ

JA

θ

JC

T

J-TP

TYP

65

15

+150

15

UNITS

°C/W

°C/W

°C

°C

NOTE: T

A

= 25°C unless otherwise noted. Typical values are at VIN = 3.6V.

EP5352QI, EP5362QI: C

IN

EP5382QI: C

IN

= 2.2

µF, C

OUT

= 4.7

µF, C

OUT

=10uF.

=10uF.

V

V

OUT

OUT

PARAMETER

Operating Input Voltage

Under Voltage Lockout

UVLO Hysteresis

Initial Accuracy

Variation for all

Causes

Feedback Pin Voltage

Feedback Pin Input Current

Feedback Pin Voltage

SYMBOL TEST CONDITIONS

V

IN

V

UVLO

VIN going low to high

V

V

V

OUT

OUT

FB

2.4V ≤ V

IN

= 25C

≤ 5.5V, I

LOAD

= 100mA;

T

A

2.4V ≤ V

IN

800mA,

≤ 5.5V, I

LOAD

= 0 –

T

A

= -40°C to +85°C

2.4V ≤ V

IN

≤ 5.5V, I

LOAD

= 100mA

VSO=VS1=VS2=1

I

FB

V

FB

MIN

2.4

-2.0

-3.0

0.591

TYP

2.2

0.145

0.603

MAX

5.5

2.3

+2.0

+3.0

0.615

2.4V ≤ V

IN

1

≤ 5.5V, I

LOAD

= 0-800mA, 0.585 0.603 0.621

UNITS

V

V

V

%

%

V nA

V

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03132 October 11, 2013 Rev H

PARAMETER

Dynamic Voltage Slew Rate

Continuous Output Current

EP5352QI

Continuous Output Current

EP5362QI

Continuous Output Current

EP5382QI

Shut-Down Current

Quiescent Current

SYMBOL

V slew

I

OUT

TEST CONDITIONS

T

A

= -40°C to +85°C

VSO=VS1=VS2=1

EP5352QI

I

OUT

EP5362QI

PFET OCP Threshold

VS0-VS1 Voltage

Threshold

VS0-VS2 Pin Input Current

Enable Voltage Threshold

Enable Pin Input Current

Operating Frequency

PFET On Resistance

NFET On Resistance

Internal Inductor DCR

Soft-Start Operation

Soft-Start Slew Rate

VOUT Rise Time

VSS

TSS

I

OUT

EP5382QI

I

SD

Enable = Low

I

LIM

No switching

2.4V

≤ V

IN

0.6V

≤ V

OUT

≤ 5.5V,

≤ V

IN

– 0.6V

Pin = Low

Pin = High

I

VSX

I

EN

F

OSC

R

DS(ON)

R

DS(ON)

Logic Low

Logic High

V

IN

= 3.6V

VID programming mode

VFB programming mode

500

600

800

1.4

0.0

1.4

0.0

1.4

3

0.75

800

2

1

2

4

340

270

.110

EP5382QI/EP5362QI/EP5352QI

MIN TYP MAX UNITS

0.4

V

IN

0.2

V

IN

V/mS mA mA mA

µA

µA

A

V nA

V

µA

MHz m

Ω m

Ω

Ω

1.95

1.56

3

2.4

4.05 V/mS

3.24 mS

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03132 October 11, 2013 Rev H

Pin Description

V

IN

V

IN

GND

GND

1

2

3

4

16

15

14

13

V

FB

V

SENSE

NC

NC

V

OUT

V

OUT

5

6

12

11

NC

NC

Figure 2. Pin description, top view.

V

IN

(Pin 1,2): Input voltage pin. Supplies power to the IC. V

IN can range from 2.4V to 5.5V.

Input GND: (Pin 3): Input power ground.

Connect this pin to the ground terminal of the input capacitor. Refer to Layout

Recommendations for further details.

Output GND: (Pin 4): Power ground. The output filter capacitor should be connected to this pin. Refer to Layout recommendations for further detail.

V

OUT

(Pin 5,6,7): Regulated output voltage.

NC (Pin 8,9,10,11,12,13,14): These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally.

V

SENSE

(Pin 15): Sense pin for output voltage regulation. Connect V

SENSE

to the output voltage rail as close to the terminal of the output filter capacitor as possible.

V

FB

V

SENSE

16

15

NC

NC

NC

NC

14

13

12

11

EP5382QI/EP5362QI/EP5352QI

Thermal

Pad

1

2

6

3

4

5

V

IN

V

IN

GND

GND

V

OUT

V

OUT

Figure 3. Pin description, bottom view.

V

FB

(Pin 16): Feed back pin for external divider option. When using the external divider option

(VS0=VS1=VS2= high) connect this pin to the center of the external divider. Set the divider such that V

FB

= 0.603V.

VS0,VS1,VS2 (Pin 17,18,19): Output voltage select. VS0=pin19, VS1=pin18, VS2=pin17.

Selects one of seven preset output voltages or choose external divider by connecting pins to logic high or low. Logic low is defined as V

≤ 0.4V. Logic high is defined as V

LOW

HIGH

≥ 1.4V.

Any level between these two values is indeterminate. (refer to section on output voltage select for more detail).

ENABLE (Pin 20): Output enable. Enable = logic high, disable = logic low. Logic low is defined as V

LOW

≤ 0.2V. Logic high is defined as V

HIGH

≥ 1.4V. Any level between these two values is indeterminate.

Thermal Pad. Thermal pad to remove heat from package. Connect to surface ground pad and PCB internal ground plane.

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03132 October 11, 2013 Rev H

Functional Block Diagram

EP5382QI/EP5362QI/EP5352QI

V

IN

ENABLE

UVLO

Thermal Limit

Current Limit

Soft Start

(-)

(+)

PWM

Comp

Sawtooth

Generator

Logic

P-Drive

N-Drive

Compensation

Network

Error

Amp

(-)

(+)

Switch

DAC

VREF

Figure 4. Functional block diagram.

Voltage

Select

VS0 VS1 VS2

Package Boundry

V

FB

V

OUT

GND

V

SENSE

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03132 October 11, 2013 Rev H

Typical Performance Characteristics

EP5382QI/EP5362QI/EP5352QI

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03132 October 11, 2013 Rev H

EP5382QI/EP5362QI/EP5352QI

Detailed Description

Functional Overview

The EP53x2QI family is a complete DCDC converter solution requiring only two low cost

MLCC capacitors. MOSFET switches, PWM controller, Gate-drive, compensation, and inductor are integrated into the tiny 5mm x

4mm x 1.1mm package to provide the smallest footprint possible while maintaining high efficiency and high performance. The converter uses voltage mode control to provide the simplest implementation and high noise immunity. The device operates at a 4 MHz switching frequency. The high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. The 4 MHz switching frequency enables the use of very small components making possible this unprecedented level of integration.

Altera Enpirion’s proprietary power MOSFET technology provides very low switching loss at frequencies of 4 MHz and higher, allowing for the use of very small internal components, and very wide control loop bandwidth. Unique magnetic design allows for integration of the inductor into the very low profile 1.1mm package. Integration of the inductor virtually eliminates the design/layout issues normally associated with switch-mode DCDC converters. All of this enables much easier and faster integration into various applications to meet demanding EMI requirements.

Output voltage is chosen from seven preset values via a three pin VID voltage select scheme. An external divider option enables the selection of any voltage in the 0.6 to V

IN

-

V dropout

. This reduces the number of components that must be qualified and reduces inventory problems. The VID pins can be toggled on the fly to implement glitch free dynamic voltage scaling.

Protection features include under-voltage lockout (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection.

Integrated Inductor

Altera has introduced the world’s first product family featuring integrated inductors. The

EP53x2QI family utilizes a low loss, planar construction inductor. The use of an internal inductor localizes the noises associated with the output loop currents. The inherent shielding

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03132 October 11, 2013 Rev H

and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board.

Further, the package layout is optimized to reduce the electrical path length for the AC ripple currents that are a major source of radiated emissions from DCDC converters.

The integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple.

Soft Start

Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the “ENABLE” pin is asserted “high”. Digital control circuitry limits the V

OUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor.

The EP53x2QI have two soft start operating modes. When VOUT is programmed using a preset voltage in VID mode, the device has a constant slew rate. When the EP53x2QI is configured in external resistor divider mode, the device has a constant VOUT ramp time.

Output voltage slew rate and ramp time is given in the Electrical Characteristics Table.

Excess bulk capacitance on the output of the device can cause an over-current condition at startup.

When operating in VID mode, the maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as:

C

OUT_TOTAL_MAX

= C

OUT_Filter

+ C

OUT_BULK

= 350uF

When the EP53x2QI output voltage is programmed using and external resistor divider the maximum total capacitance on the output is given as:

C

OUT_TOTAL_MAX

= 6.253x10

-4

/V

OUT

Farads

Application Information

EP5382QI/EP5362QI/EP5352QI

The above number and formula assume a no load condition at startup.

Over Current/Short Circuit Protection

The current limit function is achieved by sensing the current flowing through a sense P-

MOSFET which is compared to a reference current. When this level is exceeded the P-

FET is turned off and the N-FET is turned on, pulling V

OUT

low. This condition is maintained for a period of 1mS and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat in a “hiccup” mode.

Under Voltage Lockout

During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states.

Enable

The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. In shutdown mode, the device quiescent current will be less than 1 uA. The ENABLE pin must not be left floating.

Thermal Shutdown

When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 15C

°, the device will go through the normal startup process.

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03132 October 11, 2013 Rev H

Output Voltage Select

1

1

1

VS2

0

0

0

0

1

To provide the highest degree of flexibility in choosing output voltage, the EP53x2QI family uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected.

Table 1 shows the various VS0-VS2 pin logic states and the associated output voltage levels. A logic “1” indicates a connection to V

IN or to a “high” logic voltage level. A logic “0” indicates a connection to ground or to a “low” logic voltage level. These pins can be either hardwired to V

IN

or GND or alternatively can be driven by standard logic levels. These pins must not be left floating.

0

1

1

VS1

0

0

1

1

0

1

0

1

VS0

0

1

0

1

0

V

OUT

3.3

2.5

2.8

1.2

3.0

1.8

2.7

External

External Voltage Divider

As described above, the external voltage divider option is chosen by connecting the

VS0, VS1, and VS2 pins to V

IN

or logic “high”.

The EP53x2QI uses a separate feedback pin,

V

FB

, when using the external divider. VSENSE must be connected to V

OUT as indicated in

Figure 5.

Table 1. Voltage select settings.

V

IN

2.2uF

4.7uF

EP5382QI/EP5362QI/EP5352QI

ENABLE

V in

V

S0

V

S1

V

S2

GND

V

Sense

V out

V

FB

Figure 5. External Divider.

The output voltage is selected by the following formula:

V

OUT

=

0 .

603

V

(

1

+

Ra

Rb

)

R a

must be chosen as 200K

Ω to maintain loop gain. Then R b

is given as:

R b

=

V

1 .

2

OUT

−

x

10

5

0 .

603

Ω

Dynamically Adjustable Output

The EP53x2QI are designed to allow for dynamic switching between the predefined VID voltage levels The inter-voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. The slew rate is identical to the softstart slew rate of 3V/mS.

Dynamic transitioning between internal VID settings and the external divider is not allowed.

Power-Up/Down Sequencing

Ra

Rb

10

µF

V

OUT

During power-up, ENABLE should not be asserted before VIN. During power down, the

VIN should not be powered down before the

ENABLE. Tying PVIN and ENABLE together

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03132 October 11, 2013 Rev H

EP5382QI/EP5362QI/EP5352QI during power-up or power-down meets this requirement

.

Pre-Bias Start-up

The EP53x2QI does not support startup into a pre-biased condition. Be sure the output capacitors are not charged or the output of the

EP53x2QI is not pre-biased when the

EP53x2QI is first enabled.

MLCC type capacitor be used. The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-DC converter input and output filter applications.

Cin

Manufacturer Part #

Murata GRM219R61A475KE19D

GRM319R61A475KA01D

GRM219R60J475KE01D

GRM31MR60J475KA01L

Value

4.7uF

WVDC Case Size

10V

6.3V

0805

1206

0805

1206

Input and Output Capacitors

The input capacitance requirement is as follows:

EP5352QI, EP5362QI = 2.2uF

EP5382QI = 4.7uF

Altera recommends that a low ESR MLCC capacitor be used. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input and output filter applications.

The output capacitance requirement is a minimum of 10uF. The control loop is designed to be stable with up to 60uF of total output capacitance without requiring modification of the control loop. Capacitance above the 10uF minimum should be added if the transient performance is not sufficient using the 10uF. Altera recommends a low ESR

LAYOUT CONSIDERATIONS*

Panasonic

Panasonic

ECJ-2FB1A475K

ECJ-3YB1A475K

ECJ-2FB0J475K

ECJ-3YB0J475K

Taiyo Yuden LMK212BJ475KG-T

LMK316BJ475KD-T

JMK212BJ475KD-T

Cin

Manufacturer

Murata

Part #

GRM21BR71A225KA01L

GRM31MR71A225KA01L

GRM21BR70J225KA01L

Taiyo Yuden LMK107BJ225KA-T

LMK212BJ225KG-T

Cout

Manufacturer

Murata

Part # Value

GRM219R60J106KE19D 10uF

GRM319R60J106KE01D

Panasonic

Taiyo Yuden

ECJ-2FB1A225K

ECJ-3YB1A225K

ECJ-2YB0J225K

ECJ-2FB0J106K

ECJ-3YB0J106K

JMK212BJ106KD-T

JMK316BJ106KF-T

Value

2.2uF

10V

6.3V

10V

6.3V

WVDC Case Size

10V

6.3V

0805

1206

0805

10V

6.3V

10V

WVDC Case Size

6.3V

0805

1206

6.3V

6.3V

0805

1206

0805

1206

0805

1206

0805

0805

1206

0805

0603

0805

0805

1206

0805

1206

*Optimized PCB Layout file downloadable from http://www.altera.com/enpirion to assure first pass design success.

Recommendation 1: Input and output filter capacitors should be placed as close to the EP53x2QI package as possible to reduce EMI from input and output loop AC currents. This reduces the physical area of the Input and Output AC current loops.

Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the

Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground pad for the input and output filter capacitors should be isolated ground islands and should be connected to system ground as indicated in recommendation 3 and recommendation 5.

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03132 October 11, 2013 Rev H

EP5382QI/EP5362QI/EP5352QI

Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect ground terminals of the Input capacitor and the output capacitor to the system ground plane. This provides a low inductance path for the high-frequency AC currents, thereby reducing ripple and suppressing EMI (see Fig. 5, Fig. 6, and Fig. 7).

Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for heat dissipation from the converter.

Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer (PCB layer 2). This ground plane should be continuous and un-interrupted below the converter and the input and output capacitors that carry large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the

EP53x2QI and its input and output capacitors. The vias that connect the input and output capacitor grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as well.

Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or control lines underneath the converter package.

Figure 6 shows an example schematic for the EP53x2QI using the internal voltage select. In this example, the device is set to a V

OUT

of 1.2V (VS2=0, VS1=1, VS0=1).

VS2

VS1

VS0

ENABLE

17

18

19

20

10

NC

9

NC

8

NC

7

V

OUT

V

IN

4.7uF/2.2uF

(see layout recommendation 3)

10

µF

V

OUT

Figure 6. Example application, Vout=1.2V.

Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The resistor values are chosen to give an output voltage of 2.6V.

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03132 October 11, 2013 Rev H

EP5382QI/EP5362QI/EP5352QI

VS2

VS1

VS0

ENABLE

17

18

19

20

10

NC

9

NC

8

NC

7

V

OUT

Rb=60K

Ra=200K

V

IN

V

OUT

4.7uF

10

µF

(see layout recommendation 3)

Figure 7. Schematic showing the use of external divider option, Vout = 2.6V.

Figure 8 shows two example board layouts. Note the placement of the input and output capacitors.

They are placed close to the device to minimize the physical area of the AC current loops. Note the placement of the vias per recommendation 3.

Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter capacitor local grounds, and thermal pad, to PCB system ground.

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03132 October 11, 2013 Rev H

Ordering Information

Part Number

EP5352QI

EP5362QI

EP5382QI

EVB-EP5352QI

EVB-EP5362QI

EVB-EP5382QI

Temp Range

-40°C to +85°C

Package

20-pin QFN T&R

-40°C to +85°C

-40°C to +85°C

20-pin QFN T&R

20-pin QFN T&R

EP5352QI Evaluation Board

EP5362QI Evaluation Board

EP5382QI Evaluation Board

EP5382QI/EP5362QI/EP5352QI

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03132 October 11, 2013 Rev H

EP5382QI/EP5362QI/EP5352QI

Design Considerations for Lead-Frame Based Modules

Exposed Metal on Bottom Of Package

Altera has developed a break-through in package technology that utilizes the lead frame as part of the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, it does require some special considerations.

As part of the package assembly process, lead frame construction requires that for mechanical support, some of the lead-frame metal be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package.

Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EP53x2QI should be clear of any metal except for the large thermal pad. The “grayed-out” area in Figure 9 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the PCB.

NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC

MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.

Thermal Pad.

Connect to

Ground plane

Figure 9. Exposed metal and mechanical dimensions of the package . The gray area represents the bottom metal no-connect area. This area should be clear of any traces, planes, or vias, on the top layer of the PCB.

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03132 October 11, 2013 Rev H

EP5382QI/EP5362QI/EP5352QI

Figure 10. Exposed pad clearances; the Altera Enpirion lead frame package complies with JEDEC requirements.

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03132 October 11, 2013 Rev H

EP5382QI/EP5362QI/EP5352QI

Figure 11. Recommended PCB Solder Mask Openings.

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Figure 12. Package mechanical dimensions.

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Contact Information

Altera Corporation

101 Innovation Drive

San Jose, CA 95134

Phone: 408-544-7000 www.altera.com

© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,

QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.

Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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