USBLC6-4SC6Y Automotive very low capacitance ESD protection Features 

USBLC6-4SC6Y Automotive very low capacitance ESD protection Features 
USBLC6-4SC6Y
Automotive very low capacitance ESD protection
Datasheet  production data
Features
■
4 data-line protection
■
Protects VBUS
■
Very low capacitance: 3 pF
■
Very low leakage current: 10 nA
■
SOT23-6L package
■
RoHS compliant
■
AEC Q101 qualified
SOT23-6L
USBLC6-4SC6Y(JEDEC MO178AB)
Figure 1.
Functional diagram
Benefits
■
Very low capacitance between lines to GND for
optimized data integrity and speed
■
Low PCB space consumption, 9 mm²
maximum foot print
■
Enhanced ESD protection: ISO10605 up to
25 kV guaranteed at device level
■
ESD protection of VBUS
■
High reliability offered by monolithic integration
■
Fast response time
■
Consistent D+ / D- signal balance:
– Very low capacitance matching tolerance
I/O to GND = 0.015 pF
– Compliant with USB 2.0 requirements
Complies with the following standards
■
ISO10605, C = 150 pF, R = 330 
– 25 kV (air discharge)
– 15 kV (contact discharge)
■
ISO10605, C = 330 pF, R = 330 
– 15 kV (air discharge)
– 15 kV (contact discharge)
■
ISO 7637-3
– Pulse 3a: Vs = -150 V
– Pulse 3b: Vs = +100 V
This is information on a product in full production.
1
1
6
I/O4
GND
2
5
VBUS
I/O2
3
4
I/O3
Applications
■
USB 2.0 ports up to 480 Mb/s (high speed)
■
Compatible with USB 1.1 low and full speed
■
High-speed data lines in smart junction boxes
■
Ethernet port: 10/100 Mb/s
■
Video line protection
Description
The USBLC6-4SC6Y is a monolithic device
dedicated to ESD protection of high speed
interfaces, such as USB 2.0, Ethernet links and
video lines.
TM: Transil is a trademark of STMicroelectronics
September 2012
I/O1
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
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www.st.com
10
Characteristics
1
USBLC6-4SC6Y
Characteristics
Table 1.
Absolute maximum ratings (tamb = 25 °C) - Generic parameters
Symbol
VPP
1
Value
ISO10605 (C = 330 pF, R = 330 ):
air discharge
contact discharge
ISO10605 (C = 150 pF, R = 330 :
air discharge
contact discharge
Peak pulse voltage
15
15
kV
25
15
-55 to +150
°C
Tj
Operating junction temperature range
-40 to +150
°C
TL
Lead solder temperature (10 seconds duration)
260
°C
For a surge greater than the maximum values, the diode will fail in short-circuit.
Figure 2.
Electrical characteristics (definitions)
I
IF
Symbol
VBR
IRM
VRM
IPP
Cline
=
=
=
=
=
Parameter
Breakdown voltage
Leakage current @ VRM
Stand-off voltage
Peak pulse current
Line capacitance
VF
VCL VBR VRM
IRM
IR
Slope:1/Rd
2/10
Unit
Storage temperature range
Tstg
Note:
Parameter
Doc ID 023199 Rev 2
IPP
V
USBLC6-4SC6Y
Table 2.
Characteristics
Electrical characteristics (Tamb = 25 °C)
Value
Symbol
Parameter
Test Conditions
Unit
Min.
IRM
Leakage current
VRM = 5.25 V
VBR
Breakdown voltage between VBUS and
GND
IR = 1 mA
Forward voltage
IF = 10 mA
VF
VCL
Typ.
Max.
10
150
nA
6
V
0.86
V
IPP = 1 A, 8/20 µs
Any I/O pin to GND
12
V
IPP = 5 A, 8/20 µs
Any I/O pin to GND
17
V
Clamping voltage
Ci/o-GND
Capacitance between I/O and GND
VR = 1.65 V
3
pF
Ci/o-GND
0.015
Capacitance between I/O
Ci/o-i/o
VR = 1.65 V
1.85
2.7
pF
Ci/o-i/o
Figure 3.
4
0.04
Capacitance versus voltage
(typical values)
Figure 4.
Line capacitance versus frequency
(typical values)
C(pF)
C(pF)
5.0
5.0
F=1MHz
VOSC=30mVRMS
Tj=25°C
4.5
4.0
VOSC=30mVRMS
Tj=25°C
4.5
VCC=0V
4.0
3.5
3.5
CO=I/O-GND
VCC=1.65V
3.0
3.0
2.5
2.5
Cj=I/O-I/O
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
Data line voltage (V)
0.0
F(MHz)
0.0
0.0
0.5
Figure 5.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Relative variation of leakage
current versus junction
temperature (typical values)
1
10
Figure 6.
IRM[Tj] / IRM[Tj=25°C]
0.00
100
100
1000
Frequency response
S21(dB)
VBUS=5V
-5.00
-10.00
10
-15.00
F(Hz)
Tj(°C)
1
-20.00
25
50
75
100
125
100.0k
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1.0M
10.0M
100.0M
1.0G
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Application and design guidelines
USBLC6-4SC6Y
Figure 7.
ESD response to ISO10605,
C= 150 pF, R = 330 (+15 kV air
discharge)
Figure 9.
Analog crosstalk results
Figure 8.
ESD response to ISO10605,
C = 150 pF, R = 330 (-15 kV air
discharge)
0.00
dB
- 30.00
- 60.00
- 90.00
F (Hz)
- 120.00
100.0k
2
1.0M
10.0M
f/Hz
100.0M
1.0G
Application and design guidelines
More information is available in the STMicroelectronics Application note AN2689,
“Protection of automotive electronics from electrical hazards, guidelines for design and
component selection”.
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USBLC6-4SC6Y
3
Ordering information scheme
Ordering information scheme
Figure 10. Ordering information scheme
USB
LC
6 - 4
SC6 Y
Product designation
Low capacitance
Breakdown voltage
6 = 6.1 V
Number of lines protected
4 = 4 lines
Package
SC6 = SOT23-6L
Automotive grade
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Package information
4
USBLC6-4SC6Y
Package information
●
Epoxy meets UL94, V0
●
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:www.st.com.
ECOPACK® is an ST trademark.
Table 3.
SOT23-6L dimensions
Dimensions
Ref.
Millimeters
Min.
c
A
Typ.
Min.
Typ.
Max.
A
0.90
H
A1
0
E
A2
0.90
1.30 0.035
0.051
b
0.30
0.50 0.012
0.02
C
0.09
0.20 0.004
0.008
D
2.80
3.05 0.110
0.120
E
1.50
1.75 0.059
0.069
A1
θ
L
e
D b
e
e
A2
0.15
0.006
0
0.037
2.60
3.00 0.102
0.118
L
0.30
0.60 0.012
0.024

0°
10°
1.20
2.30
0.057
H
0.60
3.50
1.45 0.035
0.95
Figure 11. SOT23-6L footprint (mm)
6/10
Max.
Inches
0.95
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0°
10°
USBLC6-4SC6Y
Recommendation on PCB assembly
5
Recommendation on PCB assembly
5.1
Solder paste
5.2
5.3
1.
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste recommended.
3.
Offers a high tack force to resist component displacement during PCB movement.
4.
Use solder paste with fine particles: powder particle size 20-45 µm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of  0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
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Recommendation on PCB assembly
5.4
USBLC6-4SC6Y
Reflow profile
Figure 12. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
8/10
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
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USBLC6-4SC6Y
6
Ordering information
Ordering information
Table 4.
7
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
USBLC6-4SC6Y
UL4Y
SOT23-6L
16.7 mg
3000
Tape and reel
Revision history
Table 5.
Document revision history
Date
Revision
Changes
14-May-2012
1
First issue.
06-Sep-2012
2
Updated dimensions A1 max, b min., and L min. in Table 3.
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USBLC6-4SC6Y
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