KSZ8893MQL/MBL General Description Integrated 3-Port 10/100 Managed

KSZ8893MQL/MBL General Description  Integrated 3-Port 10/100 Managed

KSZ8893MQL/MBL

Integrated 3-Port 10/100 Managed

Switch with PHYs

Rev. 1.6

General Description

The KSZ8893MQL/MBL, a highly integrated layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes rate limiting, with patented mixed-signal low-power technology, three media access control (MAC) units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. tag/port-based VLAN, QoS priority, management, management information base (MIB) counters,

RMII/MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast

Ethernet applications.

The KSZ8893MQL/MBL contains two 10/100 transceivers

Both PHY units support 10BASE-T and 100BASE-

TX. In addition, one PHY unit supports 100BASE-FX.

The KSZ8893MQL/MBL comes in a lead-free package, and is also available in industrial temperature-grade KS8893MQLI/MBLI and

Automotive-grade KSZ8893 MQL AM. (See Ordering

Information).

___________________________________________________________________________________________________

Functional Diagram

1K LOOK-UP

ENGINE

HP AUTO

MDIX

HP AUTO

MDIX

10/100

T/TX/FX

PHY 1

10/100

T/TX

PHY 2

10/100

MAC 1

10/100

MAC 2

QUEUE

MANAGEMENT

BUFFER

MANAGEMENT

RMII/MII/

SNI

10/100

MAC 3

FRAME

BUFFERS

SNI

SPI SPI

MIB

COUNTERS

MIIM

CONTROL

REGISTERS

EEPROM

INTERFACE

SMI

I2C

P1 LED[3:0]

P2 LED[3:0]

LED

DRIVERS

STRAP IN

CONFIGURATION

LinkMD is a registered trademark of Micrel, Inc.

Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.

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Micrel, Inc.

Features

Proven Integrated 3-Port 10/100 Ethernet Switch

– 3rd generation switch with three MACs and two

PHYs fully compliant with IEEE 802.3u standard

– Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture

– Full duplex IEEE 802.3x flow control (PAUSE) with force mode option

– Half-duplex back pressure flow control

– HP Auto MDI-X for reliable detection of and correction for straight-through and crossover cables with disable and enable option

– Micrel LinkMD

TM

TDR-based cable diagnostics permit identification of faulty copper cabling

– 100BASE-FX support on port 1

– MII interface supports both MAC mode and PHY mode

– RMII interface support with external 50MHz system clock

– 7-wire serial network interface (SNI) support for legacy MAC

– Comprehensive LED Indicator support for link, activity, full/half duplex and 10/100 speed

Comprehensive Configuration Register Access

– Serial management interface (SMI) to all internal registers

– MII management (MIIM) interface to PHY registers

– SPI and I

2

C Interface to all internal registers

– I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode

– Control registers configurable on the fly (port-priority,

802.1p/d/q, AN…)

QoS/CoS Packet Prioritization Support

– Per port, 802.1p and DiffServ-based

– Re-mapping of 802.1p priority field per port basis

– Four priority levels

Advanced Switch Features

– IEEE 802.1q VLAN support for up to 16 groups (fullrange of VLAN IDs)

– VLAN ID tag/untag options, per port basis

– IEEE 802.1p/q tag insertion or removal on a per port basis (egress)

– Programmable rate limiting at the ingress and egress on a per port basis

– Broadcast storm protection with % control (global and per port basis)

– IEEE 802.1d spanning tree protocol support

– Special tagging mode to inform the processor which ingress port receives the packet

– IGMP snooping (Ipv4) and MLD snooping (Ipv6) support for multicast packet filtering

– MAC filtering function to forward unknown unicast packets to specified port

– Double-tagging support

Support IEEE 802.1w, 802.1t spanning tree

Low Latency Support

KSZ8893MQL/MBL

Switch Monitoring Features

– Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII

– MIB counters for fully compliant statistics gathering,

34 MIB counters per port

– Loopback modes for remote diagnostic of failure

Low Power Dissipation:

– Full-chip hardware power-down (register configuration not saved)

– Per port based software power-save on PHY (idle link detection, register configuration preserved)

– Voltages: Single power supply: 3.3V

• Industrial Temperature Range: –40 o

C to +85 o

C

• Available in 128-Pin PQFP and 100-ball LFBGA,

Lead- free package

Applications

Typical

– Media Converter

– FTTx customer premises equipment

– VoIP Phone

– SOHO Residential Gateway

– Broadband Gateway / Firewall / VPN

– Integrated DSL/Cable Modem

– Wireless LAN access point + gateway

– Set-top/Game Box

– Standalone 10/100 switch

Upgradeable

(1)

– Unmanaged switch with future option to migrate to a managed solution

– Single PHY alternative with future expansion option for two ports

Industrial

– Applications requiring port redundancy and port monitoring

– Sensor devices in redundant ring topology

Note:

1. Reduces cost and time of PCB re-spin.

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Ordering Information

Part Number Operation Package Grade

Temp. Range

KSZ8893MQL 0 o

C to 70 o

C 128-Pin PQFP,

Lead-free

Commercial

KSZ8893MQLI –40 o

C to +85 o

C 128-Pin PQFP,

Lead-free

Industrial

KSZ8893MQL AM -40 o

C to +85 o

C 128-Pin PQFP,

Lead-free

Automotive grade

KSZ8893MBL 0 o

C to 70 o

C 100-Ball

KSZ8893MBLI –40 o

C to +85 o

LFBGA Industrial

KSZ8893MQL/MBL

Revision History

Revision Date Summary of Changes

1.1

1.2

1.3

1.4

11/17/05

02/08/07

06/19/07

10/16/07

Updated ordering information

Updated package information

Updated default register values

Updated current consumption description

Changed device reference in datasheet from KS8893M to KSZ8893MQL

Added repeater mode description

Modify Table 5. RMII Signal Connections

Add TLA-6T718 to Table 16. Qualified Single Port Magnetics

Add Thermal Resistance (θ

JC

) to Operating Rating

Recommend connecting a 100ohm resistor between VDDC and 3.3V power rail.

11/26/07

12/10/07

07/30/08

09/16/08

02/12/09

Modify the Hold time, Output valid in table 25, 26 and Figure 25,26 of MII interface timing.

Add the I2C timing diagram and parameters in Figure 24 to 27 and Table

28.

Add MBLI to order information

Modify the paragraph “Unicast MAC Address Filtering”

Modify the Table 5 (RMII Signal Connections)

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Contents

List of Figures ...................................................................................................................................... 8

List of Tables ....................................................................................................................................... 9

Pin Description and I/O Assignment of KSZ8893MQL .................................................................... 10

Ball Description and I/O Assignment of KSZ8893MBL ................................................................... 19

Pin Configuration............................................................................................................................... 26

Functional Overview: Physical Layer Transceiver .......................................................................... 28

100BASE-TX Transmit.........................................................................................................................................................28

100BASE-TX Receive ..........................................................................................................................................................28

PLL Clock Synthesizer........................................................................................................................................................28

Scrambler/De-scrambler (100BASE-TX Only) ...................................................................................................................29

100BASE-FX Operation.......................................................................................................................................................29

100BASE-FX Signal Detection............................................................................................................................................29

100BASE-FX Far-End Fault.................................................................................................................................................29

10BASE-T Transmit .............................................................................................................................................................29

10BASE-T Receive ..............................................................................................................................................................30

Power Management.............................................................................................................................................................30

MDI/MDI-X Auto Crossover.................................................................................................................................................30

Straight Cable ................................................................................................................................................................31

Crossover Cable ............................................................................................................................................................32

Auto-Negotiation .................................................................................................................................................................32

LinkMD Cable Diagnostics .................................................................................................................................................34

Access ...........................................................................................................................................................................34

Usage ............................................................................................................................................................................34

Functional Overview: MAC and Switch ............................................................................................ 35

Address Lookup ..................................................................................................................................................................35

Learning ...............................................................................................................................................................................35

Migration ..............................................................................................................................................................................35

Aging ....................................................................................................................................................................................35

Forwarding...........................................................................................................................................................................35

Switching Engine ................................................................................................................................................................38

MAC Operation ....................................................................................................................................................................38

Inter Packet Gap (IPG) ..................................................................................................................................................38

Back-Off Algorithm.........................................................................................................................................................38

Late Collision .................................................................................................................................................................38

Illegal Frames ................................................................................................................................................................38

Full Duplex Flow Control................................................................................................................................................38

Half-Duplex Backpressure .............................................................................................................................................38

Broadcast Storm Protection ...........................................................................................................................................39

MII Interface Operation........................................................................................................................................................39

RMII Interface Operation .....................................................................................................................................................40

SNI (7-Wire) Operation ........................................................................................................................................................41

MII Management (MIIM) Interface .......................................................................................................................................42

Serial Management Interface (SMI) ....................................................................................................................................43

Repeater Mode.....................................................................................................................................................................43

Advanced Switch Functions ............................................................................................................. 44

Spanning Tree Support.......................................................................................................................................................44

Special Tagging Mode.........................................................................................................................................................45

IGMP Support ......................................................................................................................................................................46

IGMP Snooping .............................................................................................................................................................46

Multicast Address Insertion in the Static MAC Table .....................................................................................................46

IPv6 MLD Snooping.............................................................................................................................................................46

Port Mirroring Support........................................................................................................................................................47

IEEE 802.1Q VLAN Support ................................................................................................................................................47

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QoS Priority Support...........................................................................................................................................................48

Port-Based Priority..............................................................................................................................................................48

802.1p-Based Priority..........................................................................................................................................................48

DiffServ-Based Priority .......................................................................................................................................................49

Rate Limiting Support .........................................................................................................................................................49

Unicast MAC Address Filtering..........................................................................................................................................49

Configuration Interface .......................................................................................................................................................50

I

2

I

2

C Master Serial Bus Configuration ..............................................................................................................................50

C Slave Serial Bus Configuration ................................................................................................................................51

SPI Slave Serial Bus Configuration ...............................................................................................................................51

Loopback Support...............................................................................................................................................................54

Far-end Loopback..........................................................................................................................................................54

Near-end (Remote) Loopback .......................................................................................................................................55

MII Management (MIIM) Registers..................................................................................................... 56

PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control.........................................................................57

PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control.........................................................................57

PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status...........................................................................58

PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status...........................................................................58

PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High ..................................................................................58

PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High ..................................................................................58

PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low ...................................................................................58

PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low ...................................................................................58

PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................59

PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................59

PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................59

PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................59

PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status ...........................................................60

PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status ...........................................................60

PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status ...................................................60

PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status ...................................................60

Register Map: Switch & PHY (8-bit registers) .................................................................................. 61

Global Registers ............................................................................................................................................................61

Port Registers ................................................................................................................................................................61

Advanced Control Registers ..........................................................................................................................................61

Global Registers..................................................................................................................................................................61

Register 0 (0x00): Chip ID0 ...........................................................................................................................................61

Register 1 (0x01): Chip ID1 / Start Switch .....................................................................................................................62

Register 2 (0x02): Global Control 0 ...............................................................................................................................62

Register 3 (0x03): Global Control 1 ...............................................................................................................................63

Register 4 (0x04): Global Control 2 ...............................................................................................................................63

Register 4 (0x04): Global Control 2 (continued).............................................................................................................64

Register 5 (0x05): Global Control 3 ...............................................................................................................................64

Register 5 (0x05): Global Control 3 (continued).............................................................................................................65

Register 6 (0x06): Global Control 4 ...............................................................................................................................65

Register 6 (0x06): Global Control 4 (continued).............................................................................................................66

Register 7 (0x07): Global Control 5 ...............................................................................................................................66

Register 8 (0x08): Global Control 6 ...............................................................................................................................66

Register 9 (0x09): Global Control 7 ...............................................................................................................................66

Register 10 (0x0A): Global Control 8 .............................................................................................................................66

Register 11 (0x0B): Global Control 9 .............................................................................................................................67

Register 12 (0x0C): Global Control 10...........................................................................................................................67

Register 13 (0x0D): Global Control 11...........................................................................................................................68

Register 14 (0x0E): Global Control 12 ...........................................................................................................................68

Register 15 (0x0F): Global Control 13 ...........................................................................................................................68

Port Registers......................................................................................................................................................................68

Register 16 (0x10): Port 1 Control 0 ..............................................................................................................................69

Register 32 (0x20): Port 2 Control 0 ..............................................................................................................................69

Register 48 (0x30): Port 3 Control 0 ..............................................................................................................................69

Register 17 (0x11): Port 1 Control 1 ..............................................................................................................................70

Register 33 (0x21): Port 2 Control 1 ..............................................................................................................................70

Register 49 (0x31): Port 3 Control 1 ..............................................................................................................................70

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Register 18 (0x12): Port 1 Control 2 ..............................................................................................................................71

Register 34 (0x22): Port 2 Control 2 ..............................................................................................................................71

Register 50 (0x32): Port 3 Control 2 ..............................................................................................................................71

Register 19 (0x13): Port 1 Control 3 ..............................................................................................................................72

Register 35 (0x23): Port 2 Control 3 ..............................................................................................................................72

Register 51 (0x33): Port 3 Control 3 ..............................................................................................................................72

Register 20 (0x14): Port 1 Control 4 ..............................................................................................................................72

Register 36 (0x24): Port 2 Control 4 ..............................................................................................................................72

Register 52 (0x34): Port 3 Control 4 ..............................................................................................................................72

Register 21 (0x15): Port 1 Control 5 ..............................................................................................................................72

Register 37 (0x25): Port 2 Control 5 ..............................................................................................................................72

Register 53 (0x35): Port 3 Control 5 ..............................................................................................................................72

Register 22 (0x16): Port 1 Control 6 ..............................................................................................................................73

Register 38 (0x26): Port 2 Control 6 ..............................................................................................................................73

Register 54 (0x36): Port 3 Control 6 ..............................................................................................................................73

Register 23 (0x17): Port 1 Control 7 ..............................................................................................................................74

Register 39 (0x27): Port 2 Control 7 ..............................................................................................................................74

Register 55 (0x37): Port 3 Control 7 ..............................................................................................................................74

Register 24 (0x18): Port 1 Control 8 ..............................................................................................................................75

Register 40 (0x28): Port 2 Control 8 ..............................................................................................................................75

Register 56 (0x38): Port 3 Control 8 ..............................................................................................................................75

Register 25 (0x19): Port 1 Control 9 ..............................................................................................................................76

Register 41 (0x29): Port 2 Control 9 ..............................................................................................................................76

Register 57 (0x39): Port 3 Control 9 ..............................................................................................................................76

Register 26 (0x1A): Port 1 PHY Special Control/Status.................................................................................................77

Register 42 (0x2A): Port 2 PHY Special Control/Status.................................................................................................77

Register 58 (0x3A): Reserved, not applied to port 3 ......................................................................................................77

Register 27 (0x1B): Port 1 LinkMD Result .....................................................................................................................77

Register 43 (0x2B): Port 2 LinkMD Result .....................................................................................................................77

Register 59 (0x3B): Reserved, not applied to port 3 ......................................................................................................77

Register 28 (0x1C): Port 1 Control 12............................................................................................................................78

Register 44 (0x2C): Port 2 Control 12............................................................................................................................78

Register 60 (0x3C): Reserved, not applied to port 3......................................................................................................78

Register 29 (0x1D): Port 1 Control 13............................................................................................................................79

Register 45 (0x2D): Port 2 Control 13............................................................................................................................79

Register 61 (0x3D): Reserved, not applied to port 3......................................................................................................79

Register 30 (0x1E): Port 1 Status 0 ...............................................................................................................................80

Register 46 (0x2E): Port 2 Status 0 ...............................................................................................................................80

Register 62 (0x3E): Reserved, not applied to port 3 ......................................................................................................80

Register 31 (0x1F): Port 1 Status 1 ...............................................................................................................................80

Register 47 (0x2F): Port 2 Status 1 ...............................................................................................................................80

Register 63 (0x3F): Port 3 Status 1 ...............................................................................................................................80

Register 31 (0x1F): Port 1 Status 1 (continued).............................................................................................................81

Register 47 (0x2F): Port 2 Status 1 (continued).............................................................................................................81

Register 63 (0x3F): Port 3 Status 1 (continued).............................................................................................................81

Register 96 (0x60): TOS Priority Control Register 0 ......................................................................................................81

Register 97 (0x61): TOS Priority Control Register 1 ......................................................................................................82

Register 98 (0x62): TOS Priority Control Register 2 ......................................................................................................82

Register 99 (0x63): TOS Priority Control Register 3 ......................................................................................................83

Register 100 (0x64): TOS Priority Control Register 4 ....................................................................................................83

Register 101 (0x65): TOS Priority Control Register 5 ....................................................................................................84

Register 102 (0x66): TOS Priority Control Register 6 ....................................................................................................84

Register 103 (0x67): TOS Priority Control Register 7 ....................................................................................................85

Register 104 (0x68): TOS Priority Control Register 8 ....................................................................................................85

Register 105 (0x69): TOS Priority Control Register 9 ....................................................................................................86

Register 106 (0x6A): TOS Priority Control Register 10..................................................................................................86

Register 107 (0x6B): TOS Priority Control Register 11..................................................................................................87

Register 108 (0x6C): TOS Priority Control Register 12 .................................................................................................87

Register 109 (0x6D): TOS Priority Control Register 13 .................................................................................................88

Register 110 (0x6E): TOS Priority Control Register 14..................................................................................................88

Register 111 (0x6F): TOS Priority Control Register 15..................................................................................................89

Register 112 (0x70): MAC Address Register 0 ..............................................................................................................89

Register 113 (0x71): MAC Address Register 1 ..............................................................................................................89

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Register 114 (0x72): MAC Address Register 2 ..............................................................................................................89

Register 115 (0x73): MAC Address Register 3 ..............................................................................................................89

Register 116 (0x74): MAC Address Register 4 ..............................................................................................................89

Register 117 (0x75): MAC Address Register 5 ..............................................................................................................89

Register 118 (0x76): User Defined Register 1 ...............................................................................................................90

Register 119 (0x77): User Defined Register 2 ...............................................................................................................90

Register 120 (0x78): User Defined Register 3 ...............................................................................................................90

Register 121 (0x79): Indirect Access Control 0..............................................................................................................90

Register 122 (0x7A): Indirect Access Control 1 .............................................................................................................90

Register 123 (0x7B): Indirect Data Register 8 ...............................................................................................................90

Register 124 (0x7C): Indirect Data Register 7 ...............................................................................................................91

Register 125 (0x7D): Indirect Data Register 6 ...............................................................................................................91

Register 126 (0x7E): Indirect Data Register 5 ...............................................................................................................91

Register 127 (0x7F): Indirect Data Register 4................................................................................................................91

Register 128 (0x80): Indirect Data Register 3................................................................................................................91

Register 129 (0x81): Indirect Data Register 2................................................................................................................91

Register 130 (0x82): Indirect Data Register 1................................................................................................................91

Register 131 (0x83): Indirect Data Register 0................................................................................................................91

Register 132 (0x84): Digital Testing Status 0.................................................................................................................91

Register 133 (0x85): Digital Testing Control 0 ...............................................................................................................92

Register 134 (0x86): Analog Testing Control 0 ..............................................................................................................92

Register 135 (0x87): Analog Testing Control 1 ..............................................................................................................92

Register 136 (0x88): Analog Testing Control 2 ..............................................................................................................92

Register 137 (0x89): Analog Testing Control 3 ..............................................................................................................92

Register 138 (0x8A): Analog Testing Status..................................................................................................................92

Register 139 (0x8B): Analog Testing Control 4..............................................................................................................92

Register 140 (0x8C): QM Debug 1 ................................................................................................................................92

Register 141 (0x8D): QM Debug 2 ................................................................................................................................92

Static MAC Address Table.............................................................................................................................................93

VLAN Table ...................................................................................................................................................................94

Dynamic MAC Address Table........................................................................................................................................95

MIB (Management Information Base) Counters.............................................................................................................96

Additional MIB Counter Information ...............................................................................................................................98

Absolute Maximum Ratings

(1)

........................................................................................................... 99

Operating Ratings

(2)

........................................................................................................................... 99

Electrical Characteristics

(1)

............................................................................................................. 100

EEPROM Timing ................................................................................................................................................................102

SNI Timing..........................................................................................................................................................................103

MII Timing...........................................................................................................................................................................104

MAC Mode MII Timing .................................................................................................................................................104

PHY Mode MII Timing..................................................................................................................................................105

RMII Timing ........................................................................................................................................................................106

I2C Slave Mode Timing .....................................................................................................................................................107

SPI Timing..........................................................................................................................................................................108

Input Timing .................................................................................................................................................................108

Output Timing ..............................................................................................................................................................109

Auto-Negotiation Timing...................................................................................................................................................110

Reset Timing .................................................................................................................................... 111

Reset Circuit .................................................................................................................................... 112

Selection of Isolation Transformers ............................................................................................... 113

Selection of Reference Crystal ....................................................................................................... 113

Package Information........................................................................................................................ 114

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List of Figures

Figure 1. Typical Straight Cable Connection................................................................................................................................... 31

Figure 2. Typical Crossover Cable Connection .............................................................................................................................. 32

Figure 3. Auto-Negotiation and Parallel Operation ......................................................................................................................... 33

Figure 4. Destination Address Lookup Flow Chart, Stage 1 .......................................................................................................... 36

Figure 5. Destination Address Resolution Flow Chart, Stage 2..................................................................................................... 37

Figure 6. 802.1p Priority Field Format.............................................................................................................................................. 48

Figure 7. KSZ8893MQL/MBL EEPROM Configuration Timing Diagram......................................................................................... 50

Figure 8. SPI Write Data Cycle.......................................................................................................................................................... 52

Figure 9. SPI Read Data Cycle.......................................................................................................................................................... 53

Figure 10. SPI Multiple Write ............................................................................................................................................................ 53

Figure 11. SPI Multiple Read............................................................................................................................................................. 53

Figure 12: Far-End Loopback Path .................................................................................................................................................. 54

Figure 13. Near-end (Remote) Loopback Path ................................................................................................................................ 55

Figure 14. EEPROM Interface Input Timing Diagram.................................................................................................................... 102

Figure 15. EEPROM Interface Output Timing Diagram ................................................................................................................. 102

Figure 16. SNI Input Timing Diagram .............................................................................................................................................. 103

Figure 17. SNI Output Timing Diagram .......................................................................................................................................... 103

Figure 18. MAC Mode MII Timing – Data Received from MII......................................................................................................... 104

Figure 19. MAC Mode MII Timing – Data Transmitted to MII ........................................................................................................ 104

Figure 20. PHY Mode MII Timing – Data Received from MII ......................................................................................................... 105

Figure 21. PHY Mode MII Timing – Data Transmitted to MII ......................................................................................................... 105

Figure 22: RMII Timing – Data Received from RMII....................................................................................................................... 106

Figure 23: RMII Timing – Data Input to RMII .................................................................................................................................. 106

Figure 24. I2C Input Timing.............................................................................................................................................................. 107

Figure 25. I2C Start Bit Timing ........................................................................................................................................................ 107

Figure 26. I2C Stop Bit Timing......................................................................................................................................................... 107

Figure 27. I2C Input Timing.............................................................................................................................................................. 107

Figure 28. SPI Input Timing ............................................................................................................................................................ 108

Figure 29. SPI Output Timing ......................................................................................................................................................... 109

Figure 30: Auto-Negotiation Timing............................................................................................................................................... 110

Figure 31. Reset Timing .................................................................................................................................................................. 111

Figure 32. Recommended Reset Circuit ........................................................................................................................................ 112

Figure 33. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output............................................................. 112

Figure 34. 128-Pin PQFP Package.................................................................................................................................................. 114

Figure 35. 100_Ball LFBGA Package .............................................................................................................................................. 115

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List of Tables

Table 1. FX and TX Mode Selection.................................................................................................................................................. 29

Table 2. MDI/MDI-X Pin Definitions................................................................................................................................................... 30

Table 3. MII Signals ........................................................................................................................................................................... 39

Table 4: RMII Signal Description ...................................................................................................................................................... 40

Table 5: RMII Signal Connections .................................................................................................................................................... 41

Table 6. SNI Signals .......................................................................................................................................................................... 41

Table 7. MII Management Interface Frame Format .......................................................................................................................... 42

Table 8. Serial Management Interface (SMI) Frame Format............................................................................................................ 43

Table 9: Spanning Tree States ......................................................................................................................................................... 44

Table 10. Special Tagging Mode Format.......................................................................................................................................... 45

Table 11. STPID Egress Rules (Processor to Switch Port 3).......................................................................................................... 45

Table 12. STPID Egress Rules (Switch Port 3 to Processor).......................................................................................................... 46

Table 13. FID+DA Lookup in VLAN Mode ........................................................................................................................................ 47

Table 14. FID+SA Lookup in VLAN Mode ........................................................................................................................................ 48

Table 15. KSZ8893MQL/MBL SPI Connections ............................................................................................................................... 52

Table 16. Format of Static MAC Table (8 Entries) ........................................................................................................................... 93

Table 17. Format of Static VLAN Table (16 Entries)........................................................................................................................ 94

Table 18. Format of Dynamic MAC Address Table (1K Entries)..................................................................................................... 95

Table 19. Format of “Per Port” MIB Counters ................................................................................................................................. 96

Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets ........................................................................................... 97

Table 21. Format of “All Port Dropped Packet” MIB Counters....................................................................................................... 97

Table 22. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets .............................................................................. 97

Table 23. EEPROM Timing Parameters.......................................................................................................................................... 102

Table 24. SNI Timing Parameters ................................................................................................................................................... 103

Table 25. MAC Mode MII Timing Parameters................................................................................................................................. 104

Table 26. PHY Mode MII Timing Parameters.................................................................................................................................. 105

Table 27: RMII Timing Parameters ................................................................................................................................................. 106

Table 28. I2C Timing Parameters..................................................................................................................................................... 107

Table 29. SPI Input Timing Parameters.......................................................................................................................................... 108

Table 30. SPI Output Timing Parameters....................................................................................................................................... 109

Table 31: Auto-Negotiation Timing Parameters ............................................................................................................................ 110

Table 32. Reset Timing Parameters ............................................................................................................................................... 111

Table 33. Transformer Selection Criteria....................................................................................................................................... 113

Table 34. Qualified Single Port Magnetics..................................................................................................................................... 113

Table 35. Typical Reference Crystal Characteristics .................................................................................................................... 113

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Pin Description and I/O Assignment of KSZ8893MQL

Pin Number

1

2

3

Pin Name

P1LED2

P1LED1

P1LED0

Type

(1)

Description

Ipu/O

Ipu/O

Ipu/O

Port 1 LED Indicators

(apply to all modes of operation, except Repeater Mode)

[0, 0]

P1LED3 —

[0, 1]

P1LED2 Link/Act 100Link/Act

[1, 0]

P1LED3 Act

P1LED2 Link

[1, 1]

P1LED0 Speed —

Link/Act, 100Link/Act, 10Link/Act

: Low (link), High (no link),

Toggle (transmit / receive activity)

Full duplex/Col

: Low (full duplex), High (half duplex), Toggles

(collision)

Speed

: Low (100BASE-TX), High (10BASE-T)

Full duplex

: Low (full duplex), High (half duplex)

Act

: Toggle (transmit / receive activity)

Link

: Low (link), High (no link)

Repeater Mode (only)

P1LED3

P1LED2

P1LED1

P1LED0

[LEDSEL1, LEDSEL0]

[0, 0]

RPT_COL

RPT_LINK3/RX

RPT_LINK2/RX

RPT_LINK1/RX

RPT_COL

: Low (collision)

RPT_LINK#/RX

(# = port) : Low (link), High (no link), Toggles

Notes:

LEDSEL0 is external strap-in pin 70.

LEDSEL1 is external strap-in pin 23.

P1LED3 is pin 25.

During reset, P1LED[2:0] are inputs for internal testing.

Note:

1. Ipu/O = Input with internal pull-up during reset, output pin otherwise.

February 2010 10 M9999-021110-1.6

Micrel, Inc.

Pin Number

4

5

6

Pin Name

P2LED2

P2LED1

P2LED0

KSZ8893MQL/MBL

Type

(1)

Description

Ipu/O

Ipu/O

Ipu/O

Port 2 LED Indicators

(apply to all modes of operation, except Repeater Mode)

[0, 0]

P2LED3 —

[0, 1]

P2LED2 Link/Act 100Link/Act

[1, 0]

P2LED3 Act

P2LED2 Link

[1, 1]

P2LED0 Speed —

Link/Act, 100Link/Act, 10Link/Act

: Low (link), High (no link),

Toggle (transmit / receive activity)

Full duplex/Col

: Low (full duplex), High (half duplex), Toggles

(collision)

Speed

: Low (100BASE-TX), High (10BASE-T)

Full duplex

: Low (full duplex), High (half duplex)

Act

: Toggle (transmit / receive activity)

Link

: Low (link), High (no link)

Repeater Mode (only)

[LEDSEL1, LEDSEL0]

[0, 0]

P2LED3

P2LED2

P2LED1

P2LED0

RPT_ACT

RPT_ERR3

RPT_ERR2

RPT_ERR1

RPT_ACT

: Low (activity)

RPT_ERR#

(# = port) : Low (error status due to either isolation, partition, jabber, or JK error)

Notes:

LEDSEL0 is external strap-in pin 70.

LEDSEL1 is external strap-in pin 23.

P2LED3 is pin 20.

During reset, P2LED[2:0] are inputs for internal testing.

8 VDDIO P 3.3V digital V

DD

Note:

1. P = Power supply.

Gnd = Ground.

Ipu/O = Input with internal pull-up during reset, output pin otherwise.

February 2010 11 M9999-021110-1.6

Micrel, Inc.

Pin Number Pin Name Type

(1)

Description

KSZ8893MQL/MBL

12

13

14

15

16

ADVFC Ipu

P2ANEN

P2SPD

P2DPX

Ipu

Ipd

Ipd

P2FFC Ipd

1 = advertise the switch’s flow control capability via auto- negotiation.

0 = will not advertise the switch’s flow control capability via auto-negotiation.

1 = enable auto-negotiation on port 2

0 = disable auto-negotiation on port 2

1 = force port 2 to 100BT if P2ANEN = 0

0 = force port 2 to 10BT if P2ANEN = 0

1 = port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in full duplex mode if

P2ANEN = 0.

0 = port 2 default to half duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half duplex mode if

P2ANEN = 0.

1 = always enable (force) port 2 flow control feature

0 = port 2 flow control feature enable is determined by auto- negotiation result.

20

22

23

25

P2LED3

VDDCO

Opd

P

LEDSEL1

P1LED3

Ipd

Opd

Port 2 LED indicator

Note: Internal pull-down is weak; it will not turn ON the LED.

See description in pin 4.

1.2V digital VDD

Provides V

OUT_1V2

to KSZ8893MQL’s input power pins: V

DDAP

(pin 63), V

DDC

(pins 91 and 123), and V

DDA

(pins 38, 43, and

57). It is recommended the pin should be connected to 3.3V power rail by a 100ohm resistor for the internal LDO application.

LED display mode select

See description in pins 1 and 4.

Port 1 LED indicator

Note: An external 1K pull-down is needed on this pin if it is connected to a LED. The 1K resistor will not turn ON the

LED.

See description in pin 1.

Note:

1. P = Power supply.

Gnd = Ground.

O = Output.

Ipu = Input w/ internal pull-up.

Ipd = Input w/ internal pull-down.

Opu = Output w/ internal pull-up.

Opd = Output w/ internal pull-down.

February 2010 12 M9999-021110-1.6

Micrel, Inc.

Pin Number

26

Pin Name

RMII_EN

27

28

29

30

31

32

33

HWPOVR

P2MDIXDIS

P2MDIX

P1ANEN

P1SPD

P1DPX

P1FFC

35

36

NC

PWRDN

38 VDDA

40

41

MUX1

MUX2

Note:

1. P = Power supply.

Gnd = Ground.

I = Input.

Ipu = Input w/ internal pull-up.

Ipd = Input w/ internal pull-down.

Opd = Output w/ internal pull-down.

Ipd

Ipu

P

I

I

KSZ8893MQL/MBL

Type

(1)

Description

Opd

Ipd

Ipd

Strap pin for RMII Mode

0 = Disable

1 = Enable

After reset, this pin has no meaning and is a no connect.

Hardware pin overwrite

0 = Disable. All strap-in pins configurations are overwritten by the EEPROM configuration data

1 = Enable. All strap-in pins configurations are overwritten by the EEPROM configuration data, except for register 0x2C bits

[7:5], (port 2: auto-negotiation enable, force speed, force duplex).

Port 2 Auto MDI/MDI-X

PD (default) = enable

PU = disable

Ipd

Ipu

Ipd

Ipd

Ipd

Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled.

PD (default) = MDI-X (transmit on TXP2 / TXM2 pins)

PU = MDI, (transmit on RXP2 / RXM2 pins)

1 = enable auto-negotiation on port 1

0 = disable auto-negotiation on port 1

1 = force port 1 to 100BT if P1ANEN = 0

0 = force port 1 to 10BT if P1ANEN = 0

1 = port 1 default to full duplex mode if P1ANEN = 1 and auto- negotiation fails. Force port 1 in full-duplex mode if P1ANEN

= 0.

0 = port 1 default to half duplex mode if P1ANEN = 1 and auto- negotiation fails. Force port 1 in half duplex mode if

P1ANEN = 0.

1 = always enable (force) port 1 flow control feature

0 = port 1 flow control feature enable is determined by auto negotiation result.

No connect

Chip power down input (active low)

1.2V analog V

DD

Factory test pin - float for normal operation

Factory test pin - float for normal operation

February 2010 13 M9999-021110-1.6

Micrel, Inc.

Pin Number

48

49

50

51

52

53

43

44

45

46

55

56

57

59

60

61

Pin Name

VDDA

FXSD1

RXP1

RXM1

TXP1

TXM1

VDDATX

VDDARX

RXM2

RXP2

TXM2

TXP2

VDDA

TEST1

TEST2

ISET

63

65

66

VDDAP

X1

X2

67

68

69

RST_N

UNUSED

UNUSED

Note:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

Ipu = Input w/ internal pull-up.

P

I

O

I

I

O

I/O

I/O

P

I/O

I/O

P

P

I/O

I/O

KSZ8893MQL/MBL

P

I

I/O

I/O

Type

(1)

Description

1.2V analog V

DD

Fiber signal detect / factory test pin

Physical receive or transmit signal (+ differential)

Physical receive or transmit signal (– differential)

Ipu

I

I

Physical transmit or receive signal (+ differential)

Physical transmit or receive signal (– differential)

3.3V analog V

DD

3.3V analog V

DD

Physical receive or transmit signal (– differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (– differential)

Physical transmit or receive signal (+ differential)

1.2V analog V

DD

Factory test pin - float for normal operation

Factory test pin - float for normal operation

Set physical transmit output current.

Pull-down this pin with a 3.01K 1% resistor to ground.

1.2V analog V

DD

for PLL

25MHz crystal/oscillator clock connections

Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect.

Note: Clock is +/- 50ppm for both crystal and oscillator.

Hardware reset pin (active low)

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

February 2010 14 M9999-021110-1.6

Micrel, Inc.

Pin Number

70

71

72

73

74

75

76

Pin Name

LEDSEL0

SMTXEN

SMTXD3

SMTXD2

SMTXD1

SMTXD0

SMTXER

REFCLK

KSZ8893MQL/MBL

I

I

I

I

I

I

Type

(1)

Description

I LED display mode select

See description in pins 1 and 4.

Switch MII transmit enable

Switch MII transmit data bit 3

Switch MII transmit data bit 2

Switch MII transmit data bit 1

Switch MII transmit data bit 0

Switch MII transmit error

Switch MII transmit clock (MII and SNI modes only)

Output in PHY MII mode and SNI mode

Input in MAC MII mode

Reference Clock (RMII mode only)

Input for 50MHz +/- 50ppm system clock

Note: In RMII mode, pin X1 is pulled up to VDDIO supply with a 10K resistor and pin X2 is a no connect.

79

80

81

82

83

84

85

VDDIO

SMRXC

SMRXDV

SMRXD3

SMRXD2

SMRXD1

SMRXD0

P

I/O

O

Ipd/O

Ipd/O

Ipd/O

I/O

86

87

SCOL

SCRS

I/O

I/O

Note:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.

I/O = Bi-directional.

3.3V digital V

DD

Switch MII receive clock.

Output in PHY MII mode

Input in MAC MII mode

Switch MII receive data valid

Switch MII receive data bit 3

Strap option: switch MII full-duplex flow control

PD (default) = disable

PU = enable

Switch MII receive data bit 2

Strap option: switch MII is in

PD (default) = full-duplex mode

PU = half-duplex mode

Switch MII receive data bit 1

Strap option: Switch MII is in

PD (default) = 100Mbps mode

PU = 10Mbps mode

Switch MII receive data bit 0

Strap option: switch will accept packet size up to

PD = 1536 bytes (inclusive)

PU = 1522 bytes (tagged), 1518 bytes (untagged)

Switch MII collision detect

Switch MII carrier sense

February 2010 15 M9999-021110-1.6

Micrel, Inc.

Pin Number

88

89

Pin Name

SCONF1

SCONF0

I

I

Type

(1)

Description

Switch MII interface configuration

(SCONF1, SCONF0) Description

KSZ8893MQL/MBL

91

92

93

94

95

96

98

99

VDDC

UNUSED

UNUSED

MDC

MDIO

SPIQ

I

I

P

I

I/O

O

SDA I/O

SPIS_N I

(1,1) PHY mode SNI

1.2V digital VDD

Unused pins – externally pull down for normal operation

MII management interface: clock input

MII management interface: data input/output

Note: an external pull-up is needed on this pin when it is in use.

SPI slave mode: serial data output

See description in pins 100 and 101.

Note: an external pull-up is needed on this pin when it is in use.

SPI slave mode / I

2

C slave mode: clock input

I

2

C master mode: clock output

See description in pins 100 and 101.

SPI slave mode: serial data input

I

2

C master/slave mode: serial data input/output

See description in pins 100 and 101.

Note: an external pull-up is needed on this pin when it is in use.

SPI slave mode: chip select (active low)

When SPIS_N is high, the KSZ8893MQL is deselected and

SPIQ is held in high impedance state.

A high-to-low transition is used to initiate SPI data transfer.

See description in pins 100 and 101.

Note: an external pull-up is needed on this pin when it is in use.

Note:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

February 2010 16 M9999-021110-1.6

Micrel, Inc.

Pin Number

100

101

Pin Name

PS1

PS0

KSZ8893MQL/MBL

I

I

Type

(1)

Description

Serial bus configuration pins to select mode of access to

KSZ8893MQL internal registers.

[PS1, PS0] = [0, 0] — I

2

C master (EEPROM) mode

(If EEPROM is not detected, the KSZ8893MQL will be configured with the default values of its internal registers and the values of its strap-in pins.)

Interface Signals Type Description

SPIQ O Not used (tri-stated)

[PS1, PS0] = [0, 1] — I

2

C slave mode

The external I

2

C master will drive the SCL clock.

The KSZ8893MQL device addresses are:

1011_1111 <read>

1011_1110 <write>

Interface Signals Type Description

SPIQ O Not used (tri-stated)

[PS1, PS0] = [1, 0] — SPI slave mode

Interface Signals Type Description

SPIQ O SPI data out

SDA

SPIS_N

I

I

SPI data In

SPI chip select

[PS1, PS0] = [1, 1]

– SMI-mode

In this mode, the KSZ8893MQL provides access to all its internal 8-bit registers through its MDC and MDIO pins.

Note:

When (PS1, PS0)

≠ (1,1), the KSZ8893MQL provides access to its 16-bit MIIM registers through its MDC and MDIO pins.

Unused pins – externally pull up for normal operation 102

103

Note:

1. I = Input.

UNUSED

UNUSED

I

I

February 2010 17 M9999-021110-1.6

Micrel, Inc.

Pin Number

104

105

Pin Name

UNUSED

UNUSED

117

118

119

120

121

108

109

110

111

112

113

114

115

116

124

125

126

127

128

UNUSED

UNUSED

UNUSED

TESTEN

SCANEN

Note:

1. P = Power supply.

Gnd = Ground.

I = Input.

Ipd = Input w/ internal pull-down.

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

KSZ8893MQL/MBL

I

I

Type

(1)

Description

Unused pins – externally pull up for normal operation

I

I

I

I

I

I

I

I

I

I

I

I

I

P 3.3V digital V

DD

I Unused pins – externally pull up for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

P 1.2V digital V

DD

I Unused pin – externally pull down for normal operation

I

I

Ipd

Ipd

Unused pin – externally pull down for normal operation

Unused pin – externally pull down for normal operation

Scan Test Enable

For normal operation, pull-down this pin to ground.

Scan Test Scan Mux Enable

For normal operation, pull-down this pin to ground.

February 2010 18 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

Ball Description and I/O Assignment of KSZ8893MBL

Ball Number

C10

B10

A10

Ball Name

P1LED2

P1LED1

P1LED0

Type

(1)

Ipu/O

Ipu/O

Ipu/O

Ball Function Description

Port 1 LED Indicators

(apply to all modes of operation, except Repeater Mode)

[0, 0]

P1LED3 —

[0, 1]

P1LED2 Link/Act 100Link/Act

[1, 0]

P1LED3 Act

P1LED2 Link

[1, 1]

P1LED0 Speed —

Link/Act, 100Link/Act, 10Link/Act

: Low (link), High (no link),

Toggle (transmit / receive activity)

Full duplex/Col

: Low (full duplex), High (half duplex), Toggles

(collision)

Speed

: Low (100BASE-TX), High (10BASE-T)

Full duplex

: Low (full duplex), High (half duplex)

Act

: Toggle (transmit / receive activity)

Link

: Low (link), High (no link)

Repeater Mode (only)

[LEDSEL1, LEDSEL0]

[0, 0]

P1LED3

P1LED2

P1LED1

P1LED0

RPT_COL

RPT_LINK3/RX

RPT_LINK2/RX

RPT_LINK1/RX

RPT_COL

: Low (collision)

RPT_LINK#/RX

(# = port) : Low (link), High (no link), Toggles

Notes:

LEDSEL0 is external strap-in pin 70.

LEDSEL1 is external strap-in pin 23.

P1LED3 is pin 25.

During reset, P1LED[2:0] are inputs for internal testing.

Note:

1. Ipu/O = Input with internal pull-up during reset, output pin otherwise.

February 2010 19 M9999-021110-1.6

Micrel, Inc.

Ball Number

C9

B9

A9

Ball Name

P2LED2

P2LED1

P2LED0

Type

(1)

Ipu/O

Ipu/O

Ipu/O

C8

B8

February 2010

ADVFC

P2ANEN

Ipu

Ipu

KSZ8893MQL/MBL

Ball Function Description

Port 2 LED Indicators

(apply to all modes of operation, except Repeater Mode)

[0, 0]

P2LED3 —

[0, 1]

P2LED2 Link/Act 100Link/Act

[1, 0]

P2LED3 Act

P2LED2 Link

[1, 1]

P2LED0 Speed —

Link/Act, 100Link/Act, 10Link/Act

: Low (link), High (no link),

Toggle (transmit / receive activity)

Full duplex/Col

: Low (full duplex), High (half duplex), Toggles

(collision)

Speed

: Low (100BASE-TX), High (10BASE-T)

Full duplex

: Low (full duplex), High (half duplex)

Act

: Toggle (transmit / receive activity)

Link

: Low (link), High (no link)

Repeater Mode (only)

P2LED3

P2LED2

P2LED1

P2LED0

[LEDSEL1, LEDSEL0]

[0, 0]

RPT_ACT

RPT_ERR3

RPT_ERR2

RPT_ERR1

RPT_ACT

: Low (activity)

RPT_ERR#

(# = port) : Low (error status due to either isolation, partition, jabber, or JK error)

Notes:

LEDSEL0 is external strap-in pin 70.

LEDSEL1 is external strap-in pin 23.

P2LED3 is pin 20.

During reset, P2LED[2:0] are inputs for internal testing.

1 = advertise the switch’s flow control capability via auto- negotiation.

0 = will not advertise the switch’s flow control capability via auto-negotiation.

1 = enable auto-negotiation on port 2

0 = disable auto-negotiation on port 2

20 M9999-021110-1.6

Micrel, Inc.

Ball Number

A8

B7

Ball Name

P2SPD

P2DPX

A7

B6

A6

B5

A5

B4

A4

B3

A3

B2

A2

February 2010

P2FFC

P2LED3

LEDSEL1

P1LED3

RMII_EN

HWPOVR

P2MDIXDIS Ipd

P2MDIX

P1ANEN

P1SPD

P1DPX

Ipu

Ipd

Ipd

Type

(1)

Ipd

Ipd

Ipd

Opd

Ipd

Opd

Opd

Ipd

Ipd

KSZ8893MQL/MBL

Ball Function Description

1 = force port 2 to 100BT if P2ANEN = 0

0 = force port 2 to 10BT if P2ANEN = 0

1 = port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in full duplex mode if

P2ANEN = 0.

0 = port 2 default to half duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half duplex mode if

P2ANEN = 0.

1 = always enable (force) port 2 flow control feature

0 = port 2 flow control feature enable is determined by auto- negotiation result.

Port 2 LED indicator

Note: Internal pull-down is weak; it will not turn ON the LED.

See description in pin 4.

LED display mode select

See description in pins 1 and 4.

Port 1 LED indicator

Note: An external 1K pull-down is needed on this pin if it is connected to a LED. The 1K resistor will not turn ON the

LED.

See description in pin 1.

Strap pin for RMII Mode

0 = Disable

1 = Enable

After reset, this pin has no meaning and is a no connect.

Hardware pin overwrite

0 = Disable. All strap-in pins configurations are overwritten by the EEPROM configuration data

1 = Enable. All strap-in pins configurations are overwritten by the EEPROM configuration data, except for register 0x2C bits

[7:5], (port 2: auto-negotiation enable, force speed, force duplex).

Port 2 Auto MDI/MDI-X

PD (default) = enable

PU = disable

Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled.

PD (default) = MDI-X (transmit on TXP2 / TXM2 pins)

PU = MDI, (transmit on RXP2 / RXM2 pins)

1 = enable auto-negotiation on port 1

0 = disable auto-negotiation on port 1

1 = force port 1 to 100BT if P1ANEN = 0

0 = force port 1 to 10BT if P1ANEN = 0

1 = port 1 default to full duplex mode if P1ANEN = 1 and auto- negotiation fails. Force port 1 in full-duplex mode if

P1ANEN = 0.

0 = port 1 default to half duplex mode if P1ANEN = 1 and auto- negotiation fails. Force port 1 in half duplex mode if

P1ANEN = 0.

21 M9999-021110-1.6

D1

D2

F2

F1

B1

C3

C1

C2

G2

G1

H2

H1

J1

K1

J2

K2

J3

K3

J4

K4

J5

Micrel, Inc.

Ball Number

A1

Ball Name

P1FFC

Type

(1)

Ipd

PWRDN

FXSD1

RXP1

RXM1

TXP1

TXM1

RXM2

RXP2

TXM2

TXP2

ISET

X1

X2

RST_N

LEDSEL0

Ipu

I

SMTXEN

SMTXD3

SMTXD2

SMTXD1

SMTXD0

SMTXER

I

I

REFCLK

I/O

I

I

I

I

I/O

I/O

I/O

I/O

Ipu

I

I/O

I/O

I/O

I/O

O

I

O

K6

J6

J7

SMRXC

SMRXDV

SMRXD3

I/O

O

Ipd/O

KSZ8893MQL/MBL

Ball Function Description

1 = always enable (force) port 1 flow control feature

0 = port 1 flow control feature enable is determined by auto negotiation result.

Chip power down input (active low)

Fiber signal detect / factory test pin

Physical receive or transmit signal (+ differential)

Physical receive or transmit signal (– differential)

Physical transmit or receive signal (+ differential)

Physical transmit or receive signal (– differential)

Physical receive or transmit signal (– differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (– differential)

Physical transmit or receive signal (+ differential)

Set physical transmit output current.

Pull-down this pin with a 3.01K 1% resistor to ground.

25MHz crystal/oscillator clock connections

Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect.

Note: Clock is +/- 50ppm for both crystal and oscillator.

Hardware reset pin (active low)

LED display mode select

See description in pins 1 and 4.

Switch MII transmit enable

Switch MII transmit data bit 3

Switch MII transmit data bit 2

Switch MII transmit data bit 1

Switch MII transmit data bit 0

Switch MII transmit error

Switch MII transmit clock (MII and SNI modes only)

Output in PHY MII mode and SNI mode

Input in MAC MII mode

Reference Clock (RMII mode only)

Input for 50MHz +/- 50ppm system clock

Note: In RMII mode, pin X1 is pulled up to VDDIO supply with a 10K resistor and pin X2 is a no connect.

Switch MII receive clock.

Output in PHY MII mode

Input in MAC MII mode

Switch MII receive data valid

Switch MII receive data bit 3

Strap option: switch MII full-duplex flow control

PD (default) = disable

PU = enable

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Ball Number

K7

Ball Name

SMRXD2

Type

(1)

Ipd/O

J8

K8

J9

K9

J10

K10

SMRXD1

SMRXD0

SCOL

SCRS

SCONF1

SCONF0

Ipd/O

I/O

I

I

I/O

I/O

KSZ8893MQL/MBL

Ball Function Description

Switch MII receive data bit 2

Strap option: switch MII is in

PD (default) = full-duplex mode

PU = half-duplex mode

Switch MII receive data bit 1

Strap option: Switch MII is in

PD (default) = 100Mbps mode

PU = 10Mbps mode

Switch MII receive data bit 0

Strap option: switch will accept packet size up to

PD = 1536 bytes (inclusive)

PU = 1522 bytes (tagged), 1518 bytes (untagged)

Switch MII collision detect

Switch MII carrier sense

Switch MII interface configuration

(SCONF1, SCONF0) Description

H10

H9

G9

F9

F10

MDC

MDIO

SPIQ

SDA

I

I/O

O

I/O

SPIS_N I

(1,1) PHY mode SNI

MII management interface: clock input

MII management interface: data input/output

Note: an external pull-up is needed on this pin when it is in use.

SPI slave mode: serial data output

See description in pins 100 and 101.

Note: an external pull-up is needed on this pin when it is in use.

SPI slave mode / I

2

C slave mode: clock input

I

2

C master mode: clock output

See description in pins 100 and 101.

SPI slave mode: serial data input

I

2

C master/slave mode: serial data input/output

See description in pins 100 and 101.

Note: an external pull-up is needed on this pin when it is in use.

SPI slave mode: chip select (active low)

When SPIS_N is high, the KSZ8893MBL is deselected and

SPIQ is held in high impedance state.

A high-to-low transition is used to initiate SPI data transfer.

See description in pins 100 and 101.

Note: an external pull-up is needed on this pin when it is in use.

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Micrel, Inc.

Ball Number

E9

E10

Ball Name

PS1

PS0

Type

(1)

I

I

KSZ8893MQL/MBL

Ball Function Description

Serial bus configuration pins to select mode of access to

KSZ8893MBL internal registers.

[PS1, PS0] = [0, 0] — I

2

C master (EEPROM) mode

(If EEPROM is not detected, the KSZ8893MBL will be configured with the default values of its internal registers and the values of its strap-in pins.)

Interface Signals Type Description

SPIQ O Not used (tri-stated)

[PS1, PS0] = [0, 1] — I

2

C slave mode

The external I

2

C master will drive the SCL clock.

The KSZ8893MBL device addresses are:

1011_1111 <read>

1011_1110 <write>

Interface Signals Type Description

SPIQ O Not used (tri-stated)

[PS1, PS0] = [1, 0] — SPI slave mode

Interface Signals Type Description

SPIQ O SPI data out

D9

D10

C5, D8, E8, H6,

H7

SDA

SPIS_N

I

I

SPI data In

SPI chip select

[PS1, PS0] = [1, 1]

– SMI-mode

In this mode, the KSZ8893MBL provides access to all its internal 8-bit registers through its MDC and MDIO pins.

TESTEN Ipd

Note:

When (PS1, PS0)

≠ (1,1), the KSZ8893MBL provides access to its 16-bit MIIM registers through its MDC and MDIO pins.

Scan Test Enable

For normal operation, pull-down this pin to ground.

SCANEN Ipd Scan Test Scan Mux Enable

For normal operation, pull-down this pin to ground.

VDDC P 1.2V digital V

DD

Ball Number Ball Name

P 1.2V digital V

DD

Provides V

OUT_1V2

to KSZ8893MBL’s input power pins: V

DDA

(pin E3, F3 and G3), V

DDC

(pins C5, D8, E8, H6 and H7). It is recommended the pin should be connected to 3.3V power rail by a 100ohm resistor for the internal LDO application.

Type

(1)

Ball Function Description

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Micrel, Inc.

E3, F3, G3

C6, C7, F8, G8,

H4, H5

E1

E2

D4, D5, D6, D7,

E4, E5, E6, E7,

F4, F5, F6, F7,

G4, G5, G6, G7

D3, H3, H8

VDDA

VDDATX

VDDARX

P

P

1.2V analog V

DD

VDDIO P

3.3V digital V

DD

NC

Note:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

Ipu = Input w/ internal pull-up.

P

NC

3.3V analog V

3.3V analog V

No connect

DD

DD

KSZ8893MQL/MBL

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Pin Configuration

KSZ8893MQL/MBL

February 2010

UNUSED

UNUSED

UNUSED

DGND

VDDIO

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

DGND

VDDC

UNUSED

UNUSED

UNUSED

TESTEN

SCANEN

111

112

113

114

115

116

117

118

103

104

105

106

107

108

109

110

119

120

121

122

123

124

125

126

127

128

101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

45

44

43

42

49

48

47

46

41

40

39

53

52

51

50

57

56

55

54

64

63

62

61

60

59

58

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

AGND

VDDAP

AGND

ISET

TEST2

TEST1

AGND

VDDA

TXP2

TXM2

AGND

RXP2

RXM2

VDDARX

VDDATX

TXM1

TXP1

AGND

RXM1

RXP1

FXSD1

VDDA

AGND

MUX2

MUX1

AGND

NC NC

DGND V

KSZ8893 128-Pin PQFP (Top View)

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Ball Configuration

1 2

A

P1

FFC

P1

DPX

3

P1AN

EN

4

P2MD

IXDIX

KSZ8893MQL/MBL

5

RMII

EN

6

LED

SEL1

7

P2

FFC

8

P2

SPD

9

P2

LED0

10

P1

LED0

B

C

D

E

F

G

H

J

K

PWR

DN

P1

SPD

P2

MDIX

RXP1 RXM1

FXSD

1

HW

POVR

P1

LED3

P2

LED3

VDD

CO

VDDC

VDD

IO

P2

DPX

P2AN

EN

VDD

IO

ADV

FC

P2

LED1

P1

LED1

P2

LED2

P1

LED2

TXP1 TXM1 NC GND GND GND GND VDDC

TEST

EN

SCAN

EN

VDDA

TX

VDDA

RX

VDDA GND GND GND GND VDDC PS1 PS0

RXP2 RXM2 VDDA GND GND GND GND

VDD

IO

SDA

SPIS

N

TXP2

X1

X2

TXM2 VDDA GND GND GND GND

VDD

IO

SPIQ SCL

ISET NC

VDD

IO

VDD

IO

VDDC VDDC NC MDIO MDC

LED

SEL0

SM

TXD3

SM

TXD1

SM

TXER

SM

RXDV

SM

RXD3

SM

RXD1

SCOL

SCON

F1

RSTN

SM

TXEN

SM

TXD2

SM

TXD0

SM

TXC

SM

RXC

SM

RXD2

SM

RXD0

SCRS

SCON

F0

KSZ8893MBL 100-Ball LFBGA (Top View)

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Micrel, Inc. KSZ8893MQL/MBL

Functional Description

The KSZ8893MQL/MBL contains two 10/100 physical layer transceivers and three MAC units with an integrated

Layer 2 managed switch.

The KSZ8893MQL/MBL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host processor has complete control of the KSZ8893MQL/MBL via the SMI interface, MIIM interface,

SPI bus, or I

2

C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.

On the media side, the KSZ8893MQL/MBL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and also 100BASE-FX on PHY port 1, which allows the KSZ8893MQL/MBL to be used as a media converter.

Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size.

Functional Overview: Physical Layer Transceiver

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-

NRZI conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external1% 3.01K

Ω resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the

100BASE-TX transmitter.

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.

PLL Clock Synthesizer

The KSZ8893MQL/MBL generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50MHz oscillator or system clock.

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Scrambler/De-scrambler (100BASE-TX Only)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming data stream using the same sequence as at the transmitter.

100BASE-FX Operation

100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is bypassed and auto MDI/MDI-X is disabled.

100BASE-FX Signal Detection

In 100BASE-FX operation, FXSD1 (fiber signal detect), input pin 44, is usually connected to the fiber transceiver

SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater than 1V.

When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a far-end fault (FEF) is generated. When

FXSD1 is over 2.2V, the fiber signal is detected.

Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied high to force 100BASE-FX mode.

100BASE-FX signal detection is summarized in the following table:

FXSD1 Input Voltage Mode

Less than 0.2V

Greater than 1V, but less than 1.8V

Greater than 2.2V

TX mode

FX mode

No signal detected.

Far-end fault generated

FX mode

Signal detected

Table 1. FX and TX Mode Selection

To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage swing to match the FXSD1 pin’s input voltage threshold.

100BASE-FX Far-End Fault

A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver.

The KSZ8893MQL/MBL detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the KSZ8893MQL/MBL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between frames.

By default, FEF is enabled. FEF can be disabled through register setting.

10BASE-T Transmit

The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental frequency when driven by an all-ones Manchesterencoded signal.

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10BASE-T Receive

On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8893MQL/MBL decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.

Power Management

The KSZ8893MQL/MBL features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via port control register, or MIIM PHY register.

In addition, there is a full chip power down mode. When activated, the entire chip is powered down.

MDI/MDI-X Auto Crossover

To eliminate the need for crossover cables between similar devices, the KSZ8893MQL/MBL supports HP Auto

MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.

The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the KSZ8893MQL/MBL device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers, or MIIM PHY registers.

The IEEE 802.3u standard MDI and MDI-X definitions are:

MDI MDI-X

RJ-45 Pins Signals RJ-45 Pins Signals

1 TD+ 1 RD+

2 TD- 2 RD-

3 RD+ 3 TD+

6 RD- 6 TD-

Table 2. MDI/MDI-X Pin Definitions

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Straight Cable

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).

10/100 Ethernet

Media Dependent Interface

Transmit Pair

Receive Pair

6

7

4

5

8

1

2

3

Modular Connector

(RJ-45)

NIC

Straight

Cable

10/100 Ethernet

Media Dependent Interface

6

7

4

5

8

1

2

3

Receive Pair

Transmit Pair

Modular Connector

(RJ-45)

HUB

(Repeater or Switch)

Figure 1. Typical Straight Cable Connection

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Crossover Cable

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.

The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

10/100 Ethernet

Media Dependent Interface

10/100 Ethernet

Media Dependent Interface

Receive Pair

Transmit Pair

5

6

7

8

1

2

3

4

Crossover

Cable

5

6

7

8

1

2

3

4

Receive Pair

Transmit Pair

Modular Connector (RJ-45)

HUB

(Repeater or Switch)

Modular Connector (RJ-45)

HUB

(Repeater or Switch)

Figure 2. Typical Crossover Cable Connection

Auto-Negotiation

The KSZ8893MQL/MBL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification.

Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation.

In auto-negotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not supported or the KSZ8893MQL/MBL link partner is forced to bypass auto-negotiation, the KSZ8893MQL/MBL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the

KSZ8893MQL/MBL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol.

The link up process is shown in the following flow diagram.

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Start Auto Negotiation

KSZ8893MQL/MBL

Force Link Setting

Yes

Bypass Auto Negotiation and Set Link Mode

N o

Parallel

Operation

Attempt Auto

Negotiation

Listen for 100BASE-TX

Idles

Listen for 10BASE-T

Link Pulses

No

Join

Flow

February 2010

Link Mode Set ?

Yes

Link Mode Set

Figure 3. Auto-Negotiation and Parallel Operation

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LinkMD Cable Diagnostics

The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of +/- 2m. Internal circuitry displays the TDR information in a user-readable digital format.

Note: Cable diagnostics are only valid for copper connections and do not support fiber optic operation.

Access

LinkMD is initiated by accessing registers {26,27} and {42,43}, the LinkMD Control/Status registers, for ports 1 and 2, respectively; and in conjunction with registers 29 and 45, Port Control Register 13, for ports 1 and 2, respectively.

Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD access.

Usage

The following is a sample procedure for using LinkMD with registers {26,27,29} on port 1.

1. Disable auto MDI/MDI-X by writing a ‘1’ to register 29, bit [2] to enable manual control over the differential pair used to transmit the LinkMD pulse.

2. Start cable diagnostic test by writing a ‘1’ to register 26, bit [4]. This enable bit is self-clearing.

3. Wait (poll) for register 26, bit [4] to return a ‘0’, indicating cable diagnostic test is completed.

4. Read cable diagnostic test results in register 26, bits [6:5]. The results are as follows:

00 = normal condition (valid test)

01 = open condition detected in cable (valid test)

10 = short condition detected in cable (valid test)

11 = cable diagnostic test failed (invalid test)

The ‘11’ case, invalid test, occurs when the KSZ8893MQL/MBL is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8893MQL/MBL to determine if the detected signal is a reflection of the signal generated or a signal from another source.

5. Get distance to fault by concatenating register 26, bit [0] and register 27, bits [7:0]; and multiplying the result by a constant of 0.4. The distance to the cable fault can be determined by the following formula:

D (distance to cable fault) = 0.4 x {(register 26, bit [0]),(register 27, bits [7:0])}

D (distance to cable fault) is expressed in meters.

Concatenated value of registers 26 and 27 is converted to decimal before multiplying by 0.4.

The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.

For port 2 and for the MIIM PHY registers, LinkMD usage is similar.

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Functional Overview: MAC and Switch

Address Lookup

The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information.

The KSZ8893MQL/MBL is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.

Learning

The internal lookup engine updates its table with a new entry if the following conditions are met:

1. The received packet's Source Address (SA) does not exist in the lookup table.

2. The received packet is good; the packet has no receiving errors, and is of legal length.

The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted to make room for the new entry.

Migration

The internal lookup engine also monitors whether a station has moved. If a station has moved, it will update the table accordingly. Migration happens when the following conditions are met:

1. The received packet's SA is in the table but the associated source port information is different.

2. The received packet is good; the packet has no receiving errors, and is of legal length.

The lookup engine will update the existing record in the table with the new source port information.

Aging

The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record from the table. The lookup engine constantly performs the aging process and will continuously remove aging records. The aging period is about 200 seconds. This feature can be enabled or disabled through register 3

(0x03) bit [2].

Forwarding

The KSZ8893MQL/MBL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in Figure 5. The packet is sent to PTF2.

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Start

KSZ8893MQL/MBL

PTF1= NULL

NO

VLAN ID

Valid?

- Search VLAN table

- Ingress VLAN filtering

- Discard NPVID check

YES

Search complete.

Get PTF1 from

Static MAC Table

FOUND

Search Static

Table

NOT

FOUND

This search is based on

DA or DA+FID

Search complete.

Get PTF1 from

Dynamic MAC

Table

FOUND

Dynamic Table

Search

NOT

FOUND

This search is based on

DA+FID

Search complete.

Get PTF1 from

VLAN Table

PTF1

Figure 4. Destination Address Lookup Flow Chart, Stage 1

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PTF1

Spanning Tree

Process

- Check receiving port's receive enable bit

- Check destination port's transmit enable bit

- Check whether packets are special (BPDU

or specified)

IGMP Process

- Applied to MAC #1 and MAC #2

- MAC #3 is reserved for

microprocessor

- IGMP will be forwarded to port 3

Port Mirror

Process

- RX Mirror

- TX Mirror

- RX or TX Mirror

- RX and TX Mirror

KSZ8893MQL/MBL

Port VLAN

Membership

Check

PTF2

Figure 5. Destination Address Resolution Flow Chart, Stage 2

The KSZ8893MQL/MBL will not forward the following packets: packets

These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size

PAUSE

KSZ8893MQL/MBL intercepts these packets and performs full duplex flow control accordingly.

3. "Local" packets

Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local."

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Switching Engine

The KSZ8893MQL/MBL features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.

The switching engine has a 32kB internal frame buffer. This buffer pool is shared between all three ports. There are a total of 256 buffers available. Each buffer is sized at 128 bytes.

MAC Operation

The KSZ8893MQL/MBL strictly abides by IEEE 802.3 standards to maximize compatibility.

Inter Packet Gap (IPG)

If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.

Back-Off Algorithm

The KSZ8893MQL/MBL implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and optional "aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending on the switch configuration for register 4 (0x04) bit [3].

Late Collision

If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.

Illegal Frames

The KSZ8893MQL/MBL discards frames less than 64 bytes, and can be programmed to accept frames up to1518 bytes, 1536 bytes or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since the KSZ8893MQL/MBL supports VLAN tags, the maximum sizing is adjusted when these tags are present.

Full Duplex Flow Control

The KSZ8893MQL/MBL supports standard IEEE 802.3x flow control frames on both transmit and receive sides.

On the receive side, if the KSZ8893MQL/MBL receives a pause control frame, the KSZ8893MQL/MBL will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it is flow controlled), only flow control packets from the KSZ8893MQL/MBL are transmitted.

On the transmit side, the KSZ8893MQL/MBL has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues.

The KSZ8893MQL/MBL will flow control a port that has just received a packet if the destination port resource is busy. The KSZ8893MQL/MBL issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802.3x standard. Once the resource is freed up, the KSZ8893MQL/MBL sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated.

The KSZ8893MQL/MBL flow controls all ports if the receive queue becomes full.

Half-Duplex Backpressure

A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as full duplex flow control. If backpressure is required, the KSZ8893MQL/MBL sends preambles to defer the other stations' transmission (carrier sense deference).

To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the

KSZ8893MQL/MBL discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense

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To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following:

1. Aggressive back-off (register 3 (0x03), bit [0])

2. No excessive collision drop (register 4 (0x04), bit [3])

Note: These bits are not set as defaults, as this is not the IEEE standard.

Broadcast Storm Protection

The KSZ8893MQL/MBL has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8893MQL/MBL has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting is 0x63 (99 decimal). This is equal to a rate of 1%, calculated as follows:

148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63

Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes of preamble between two packets.

MII Interface Operation

The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common interface between physical layer and MAC layer devices. The MII provided by the KSZ8893MQL/MBL is connected to the device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception. The following table describes the signals used by the MII bus.

PHY-Mode Connections

External MAC

Controller Signals

MTXEN

MTXER

MTXD3

MTXD2

MTXD1

MTXD0

MTXC

MCOL

MCRS

MRXDV

MRXER

MRXD3

MRXD2

MRXD1

MRXD0

MRXC

KSZ8893MQL/MBL

PHY Signals

SMTXD[3]

SMTXD[2]

SMTXD[1]

SMTXD[0]

(not used)

SMRXD[3]

SMRXD[2]

SMRXD[1]

SMRXD[0]

Pin

Descriptions

Transmit data bit 3

Transmit data bit 2

Transmit data bit 1

Transmit data bit 0

Receive error

Receive data bit 3

Receive data bit 2

Receive data bit 1

Receive data bit 0

Table 3. MII Signals

MAC-Mode Connections

External

PHY Signals

KSZ8893MQL/MBL

MAC Signals

MTXD3

MTXD2

MTXD1

MTXD0

MRXER

MRXD3

MRXD2

MRXD1

MRXD0

SMRXD[3]

SMRXD[2]

SMRXD[1]

SMRXD[0]

SMTXER

SMTXD[3]

SMTXD[2]

SMTXD[1]

SMTXD[0]

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The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors. For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission.

The KSZ8893MBL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the KSZ8893MBL. So, for PHY mode operation, if the device interfacing with the KSZ8893MBL has an MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the

KSZ8893MQL/MBL has an MTXER input pin, it also needs to be tied low.

RMII Interface Operation

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII).

RMII provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:

1. Supports 10Mbps and 100Mbps data rates.

2. Uses a single 50 MHz clock reference (provided externally).

3. Provides independent 2-bit wide (di-bit) transmit and receive data paths.

4. Contains two distinct groups of signals: one for transmission and the other for reception

The RMII provided by the KSZ8893MQL/MBL is connected to the device’s third MAC. It complies with the RMII

Specification. The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal description.

RMII

Signal Name

Direction

(with respect to the PHY)

Direction

(with respect to the MAC)

RMII

Signal Description

REF_CLK Input

Input or

Output

CRS_DV Output Input

RXD1

RXD0

Output

Output

Input

Input

Synchronous 50 MHz clock reference for receive, transmit and control interface

Carrier sense/

Receive data valid

Receive data bit 1

Receive data bit 0

TXD1

TXD0

Input

Input

Output

Output

Transmit data bit 1

Transmit data bit 0

KSZ8893MQL/MBL RMII

Signal (direction)

REFCLK (input)

SMRXDV (output)

SMRXD[1] (output)

SMRXD[0] (output)

SMTXEN (input)

SMTXD[1] (input)

SMTXD[0] (input)

Receive error (not used)

SMTXER* (input)

* Connects to RX_ER signal of RMII PHY device

Table 4: RMII Signal Description

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The KSZ8893MQL/MBL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from RMII PHY devices, the SMTXER input signal of the KSZ8893MQL/MBL is connected to the

RXER output signal of the RMII PHY device.

Collision detection is implemented in accordance with the RMII Specification.

In RMII mode, tie MII signals, SMTXD[3:2] and SMTXER, to ground if they are not used.

The KSZ8893MQL/MBL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two

KSZ8893MQL/MBL devices to be connected back-to-back. The following table shows the KSZ8893MQL/MBL

RMII pin connections with an external RMII PHY and an external RMII MAC, such as another KSZ8893MQL/MBL device.

KSZ8893MQL/MBL

PHY-MAC Connections

External

PHY Signals

KSZ8893MQL/M

BL

MAC Signals

REF_CLK

TX_EN SMRXDV

TXD1

TXD0

CRS_DV

RXD1

RXD0

RX_ER

SMRXD[1]

SMRXD[0]

SMTXD[1]

SMTXD[0]

Pin

Descriptions

Carrier sense/

Receive data valid

Receive data bit 1

Receive data bit 0

KSZ8893MQL/MBL

MAC-MAC Connections

KSZ8893MQL/M

BL

MAC Signals

External

MAC Signals

SMRXDV CRS_DV

SMRXD[1] RXD1

SMRXD[0] RXD0

Transmit data bit 1

Transmit data bit 0

Table 5: RMII Signal Connections

SMTXD[1] TXD1

SMTXD[0] TXD0

(not used) (not used)

SNI (7-Wire) Operation

The serial network interface (SNI) or 7-wire is compatible with some controllers used for network layer protocol processing. In SNI mode, the KSZ8893MQL/MBL acts like a PHY and the external controller functions as the

MAC. The KSZ8893MQL/MBL can interface directly with external controllers using the 7-wire interface. These signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in the following table.

Pin Descriptions

Transmit enable

Serial transmit data

Transmit clock

Collision detection

Carrier sense

Serial receive data

Receive clock

External MAC

Controller Signals

TXEN

TXD

TXC

COL

CRS

RXD

RXC

Table 6. SNI Signals

KSZ8893MQL/MBL

PHY Signals

SMTXEN

SMTXD[0]

SMTXC

SCOL

SMRXDV

SMRXD[0]

SMRXC

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The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys when the data is valid.

For half duplex operation, the SCOL signal is used to indicate that a collision has occurred during transmission.

MII Management (MIIM) Interface

The KSZ8893MQL/MBL supports the IEEE 802.3 MII Management Interface, also known as the Management

Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8893MQL/MBL. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u

Specification.

The MIIM interface consists of the following:

ƒ A physical connection that incorporates the data line (MDIO) and the clock line (MDC).

ƒ A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8893MQL/MBL device.

ƒ Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom

MIIM registers [29, 31].

The MIIM Interface can operate up to a maximum clock speed of 5 MHz.

The following table depicts the MII Management Interface frame format.

PHY REG

Frame

OP Code

Read

Write

32 1’s

32 1’s

01

01

10

01

Address

Bits [4:0]

AAAAA

AAAAA

Address

Bits [4:0]

RRRRR

RRRRR

TA Data

Bits [15:0]

Idle

Z0 DDDDDDDD_DDDDDDDD Z

10 DDDDDDDD_DDDDDDDD Z

Table 7. MII Management Interface Frame Format

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Serial Management Interface (SMI)

The SMI is the KSZ8893MQL/MBL non-standard MIIM interface that provides access to all KSZ8893MQL/MBL configuration registers. This interface allows an external device to completely monitor and control the states of the

KSZ8893MQL/MBL.

The SMI interface consists of the following:

ƒ A physical connection that incorporates the data line (MDIO) and the clock line (MDC).

ƒ

A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8893MQL/MBL device.

ƒ Access to all KSZ8893MQL/MBL configuration registers. Register access includes the Global, Port and

Advanced Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers

[0:5] and custom MIIM registers [29, 31].

The following table depicts the SMI frame format.

Read

32 1’s

Write

32 1’s

PHY REG TA Data Idle

Frame

OP Code Address

Bits [4:0]

Address

Bits [4:0]

Bits [15:0]

01

01

00

00 0xRRR RRRRR 10 xxxx_xxxx_DDDD_DDDD Z

Table 8. Serial Management Interface (SMI) Frame Format

SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations.

To access the KSZ8893MQL/MBL registers 0-141 (0x00 – 0x8D), the following applies:

ƒ PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address;

that is, {PHYAD[2:0], REGAD[4:0]} = bits [7:0] of the 8-bit address.

ƒ Registers are 8 data bits wide.

For read operation, data bits [15:8] are read back as 0’s.

For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.

SMI register access is the same as the MIIM register access, except for the register access requirements presented in this section.

Repeater Mode

The KSZ8893MQL/MBL supports repeater mode in 100BASE-TX Half Duplex mode. In repeater mode, all ingress packets are broadcast to the other two ports. MAC address checking and learning are disabled.

Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be configured to 100BASE-TX Half Duplex mode. Additionally, both PHY ports need to have auto-negotiation disabled.

The latency between the two PHY ports is 270 ns (minimum) and 310 ns (maximum). The 40 ns difference is one clock skew (one 25 MHz clock period) between reception and transmission. Latency is defined as the time from the first bit of the Destination Address (DA) entering the ingress port to the first bit of the DA exiting the egress port.

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Advanced Switch Functions

Spanning Tree Support

To support spanning tree, port 3 is designated as the processor port.

The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”,

“receive enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The following table shows the port setting and software actions taken for each of the five spanning tree states.

Software Action Disable State

The port should not forward or receive any packets. Learning is disabled.

Blocking State

Only packets to the processor are forwarded.

Learning is disabled.

Listening State

Only packets to and from the processor are forwarded.

Learning is disabled.

Learning State

Only packets to and from the processor are forwarded.

Learning is enabled.

Port Setting

“transmit enable = 0, receive enable = 0, learning disable =1”

Port Setting

“transmit enable = 0, receive enable = 0, learning disable =1”

Port Setting

“transmit enable = 0, receive enable = 0, learning disable =1”

Port Setting

“transmit enable = 0, receive enable = 0, learning disable = 0”

Forwarding

State

Port Setting

Packets are forwarded and received normally.

Learning is enabled.

“transmit enable = 1, receive enable = 1, learning disable = 0”

The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the “static MAC table” with “overriding bit” set) and the processor should discard those packets. Address learning is disabled on the port in this state.

Software Action

The processor should not send any packets to the port(s) in this state. The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state.

Software Action

The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. See

“Special Tagging Mode” for details. Address learning is disabled on the port in this state.

Software Action

The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. See

“Special Tagging Mode” for details. Address learning is enabled on the port in this state.

Software Action

The processor programs the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. See “Special

Tagging Mode” for details. Address learning is enabled on the port in this state.

Table 9: Spanning Tree States

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Special Tagging Mode

Special Tagging Mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications. Special Tagging, similar to 802.1Q Tagging, requires software to change network drivers to insert/modify/strip/interpret the special tag. This mode is enabled by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.

802.1Q Tag Format

TPID (tag protocol identifier, 0x8100) + TCI.

Special Tag Format

STPID (special tag identifier, 0x810 +

4 bit for “port mask”) + TCI

Table 10. Special Tagging Mode Format

The STPID is only seen and used by the port 3 interface, which should be connected to a processor. Packets from the processor to the switch’s port 3 should be tagged with the STPID and the port mask, defined as follows:

“0001”, forward packet to port 1 only

“0010”, forward packet to port 2 only

“0011”, broadcast packet to port 1 and port 2

Packets with normal tags (“0000” port masks) will use KSZ8893MQL/MBL internal MAC table lookup to determine the forwarding port(s). Also, if packets from the processor are not tagged, the KSZ8893MQL/MBL will treat them as normal packets and use internal MAC table lookup to determine the forwarding port(s).

The KSZ8893MQL/MBL uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override any port setting, regardless of port states (disable, blocking, listening, learning). The table below shows the processor to switch egress rules when dealing with STPID.

Ingress Tag Field

(0x810+ port mask)

(0x810+ port mask)

(0x810+ port mask)

(0x810+ port mask)

Not Tagged

TX port “tag insertion”

TX port “tag removal”

Egress Action to Tag Field

0

0

1

1

Don’t care

0

1

0

1

Don’t care

- Modify tag field to 0x8100

- Recalculate CRC

- No change to TCI if not null VID

- Replace VID with ingress (port 3) port

VID if null VID

- (STPID + TCI) will be removed

- Padding to 64 bytes if necessary

- Recalculate CRC

- Modify tag field to 0x8100

- Recalculate CRC

- No change to TCI if not null VID

- Replace VID with ingress (port 3) port

VID if null VID

- Modify tag field to 0x8100

- Recalculate CRC

- No change to TCI if not null VID

- Replace VID with ingress (port 3) port

VID if null VID

- Determined by the Dynamic MAC

Table

Table 11. STPID Egress Rules (Processor to Switch Port 3)

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For packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the packets were received on, defined as follows:

“0001”, packet from port 1

“0010”, packet from port 2

No port mask values, other than the previous two defined ones, should be received in this direction in Special

Tagging Mode. The switch to processor egress rules are defined as follows:

Ingress Packets

Tagged with 0x8100 + TCI

Not tagged.

Egress Action to Tag Field

- Modify TPID to 0x810 + “port mask”, which indicates source port.

- No change to TCI if VID is not null

- Replace null VID with ingress port VID

- Recalculate CRC

- Insert TPID to 0x810 + “port mask”, which indicates source port

- Insert TCI with ingress port VID

- Recalculate CRC

Table 12. STPID Egress Rules (Switch Port 3 to Processor)

IGMP Support

For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8893MQL/MBL provides two components:

IGMP Snooping

The KSZ8893MQL/MBL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2.

Multicast Address Insertion in the Static MAC Table

Once the multicast address is programmed in the Static MAC Table, the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports.

To enable IGMP support, set register 5 bit [6] to ‘1’. Also, Special Tagging Mode needs to be enabled, so that the processor knows which port the IGMP packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.

IPv6 MLD Snooping

The KSZ8893MQL/MBL traps IPv6 Multicast Listener Discovery (MLD) packets and forwards them only to processor (port 3). MLD snooping is controlled by register 5 bit 5 (MLD snooping enable) and register 5 bit 4

(MLD option).

With MLD snooping enabled, the KSZ8893MQL/MBL traps packets that meet all of the following conditions:

• IPv6 multicast packets

• Hop count limit = 1

• IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58)

If the MLD option bit is set to “1”, the KSZ8893MQL/MBL traps packets with the following additional condition:

• IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or

60)

For MLD snooping, Special Tagging Mode also needs to be enabled, so that the processor knows which port the

MLD packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.

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Port Mirroring Support

KSZ8893MQL/MBL supports “Port Mirroring” comprehensively as:

“receive only” mirror on a port

All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8893MQL/MBL forwards the packet to both port 2 and port 3.

The KSZ8893MQL/MBL can optionally even forward “bad” received packets to the “sniffer port”.

“transmit only” mirror on a port

All the packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1 after the internal lookup. The KSZ8893MQL/MBL forwards the packet to both port 1 and port 3.

“receive and transmit” mirror on two ports

All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port

2 is programmed to be “transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8893MQL/MBL forwards the packet to both port 2 and port 3.

Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the

“sniffer port”. All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively.

IEEE 802.1Q VLAN Support

The KSZ8893MQL/MBL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8893MQL/MBL provides a 16-entries VLAN Table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine whether the VID is valid. If the VID is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved for further lookup. The FID + Destination Address (FID+DA) are used to determine the destination port. The FID + Source Address (FID+SA) are used for address learning.

DA found in

Static MAC

Table?

No

No

Use FID flag? FID match?

Don’t care

Don’t care

Don’t care

Don’t care

DA+FID found in

Dynamic

MAC Table?

No

Yes

Action

Broadcast to the membership ports defined in the VLAN Table bits [18:16]

Send to the destination port defined in the

Dynamic MAC Address Table

bits [53:52]

Broadcast to the membership ports defined in the VLAN Table bits [18:16]

Yes

Send to the destination port defined in the

Dynamic MAC Address Table

bits [53:52]

Table 13. FID+DA Lookup in VLAN Mode

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FID+SA found in Dynamic

MAC Table?

No

Yes

Action

Learn and add FID+SA to the Dynamic MAC Address Table

Update time stamp

Table 14. FID+SA Lookup in VLAN Mode

Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KSZ8893MQL/MBL. These features can be set on a per port basis, and are defined in register 18, 34 and

50 for ports 1, 2 and 3, respectively.

QoS Priority Support

The KSZ8893MQL/MBL provides Quality of Service (QoS) for applications such as VoIP and video conferencing.

Offering four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the highest priority queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32 and 48 is used to enable split transmit queues for ports 1, 2 and 3, respectively. If a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue.

There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four priority queues. This global option is set and explained in bit [3] of register 5.

Port-Based Priority

With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received at the high priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. Bits [4:3] of registers 16, 32 and 48 are used to enable portbased priority for ports 1, 2 and 3, respectively.

802.1p-Based Priority

For 802.1p-based priority, the KSZ8893MQL/MBL examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as specified by the registers 12 and 13. The “priority mapping” value is programmable.

The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.

Bytes 8

Preamble

6

DA

6

SA

2

VPID

2

TCI

2 length LLC

46-1500

Data

4

FCS

Bits

802.1q VLAN Tag

16

Tagged Packet Type

(8100 for Ethernet)

3

802.1p

1 12

VLAN ID

Figure 6. 802.1p Priority Field Format

802.1p-based priority is enabled by bit [5] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively.

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The KSZ8893MQL/MBL provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control

Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag.

Tag Insertion

is enabled by bit [2] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets

{19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KSZ8893MQL/MBL will not add tags to already tagged packets.

Tag Removal

is enabled by bit [1] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8893MQL/MBL will not modify untagged packets.

The CRC is recalculated for both tag insertion and tag removal.

802.1p Priority Field Re-mapping

is a QoS feature that allows the KSZ8893MQL/MBL to set the “User Priority

Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User

Priority Ceiling” is enabled by bit [3] of registers 17, 33 and 49 for ports 1, 2 and 3, respectively.

DiffServ-Based Priority

DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section.

The ToS priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the

DSCP register to determine priority.

Rate Limiting Support

The KSZ8893MQL/MBL supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and on the “transmit side” on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up

Ingress Rate Control Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from packet DA to FCS).

For ingress rate limiting, KSZ8893MQL/MBL provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. The KSZ8893MQL/MBL counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.

For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified.

If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate.

To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.

Unknown Unicast MAC Address Filtering

The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in the static table, and also not learned in the dynamic MAC table, KSZ8893MQL/MBL is then configured with the option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register 14.

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This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in applications such as voice over Internet Protocol (VoIP).

Configuration Interface

The KSZ8893MQL/MBL can operate as both a managed switch and an unmanaged switch.

In unmanaged mode, the KSZ8893MQL/MBL is typically programmed using an EEPROM. If no EEPROM is present, the KSZ8893MQL/MBL is configured using its default register settings. Some default settings are configured via strap-in pin options. The strap-in pins are indicated in the “KSZ8893MQL/MBL Pin Description and

I/O Assignment” table.

I

2

C Master Serial Bus Configuration

With an additional I

2

C (“2-wire”) EEPROM, the KSZ8893MQL/MBL can perform more advanced switch features like “broadcast storm protection” and “rate control” without the need of an external processor.

For KSZ8893MQL/MBL I

2

C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as defined in the KSZ8893MQL/MBL register map) with the exception of the “Read Only” status registers. After the de-assertion of reset, the KSZ8893MQL/MBL sequentially reads in the configuration data for all 121 registers, starting from register 0. The configuration access time (t prgm the following figure.

) is less than 15 ms, as depicted in

RST_N

SCL

SDA

....

....

....

t prgm

<15 ms

Figure 7. KSZ8893MQL/MBL EEPROM Configuration Timing Diagram

The following is a sample procedure for programming the KSZ8893MQL/MBL with a pre-configured EEPROM:

1. Connect the KSZ8893MQL/MBL to the EEPROM by joining the SCL and SDA signals of the respective devices. For the KSZ8893MQL/MBL, SCL is pin 97 and SDA is pin 98.

2. Enable C master mode by setting the KSZ8893MQL/MBL strap-in pins, PS[1:0] (pins 100 and 101, respectively) to “00”.

3. Check to ensure that the KSZ8893MQL/MBL reset signal input, RST_N (pin 67), is properly connected to the external reset source at the board level.

4. Program the desired configuration data into the EEPROM.

5. Place the EEPROM on the board and power up the board.

6. Assert an active-low reset to the RST_N pin of the KSZ8893MQL/MBL. After reset is de-asserted, the

KSZ8893MQL/MBL begins reading the configuration data from the EEPROM. The KSZ8893MQL/MBL checks that the first byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues. If not, EEPROM configuration access is denied and all other data sent from the EEPROM is ignored by the

KSZ8893MQL/MBL. The configuration access time (t prgm

) is less than 15ms.

Note:

For proper operation, check to ensure that the KSZ8893MQL/MBL PWRDN input signal (pin 36) is not asserted during the reset operation. The PWRDN input is active low.

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I

2

C Slave Serial Bus Configuration

In managed mode, the KSZ8893MQL/MBL can be configured as an I

2

C slave device. In this mode, an I

2

C master device (external controller/CPU) has complete programming access to the KSZ8893MQL/MBL’s 142 registers.

Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly accessed via registers 121 to 131.

In I

2

C slave mode, the KSZ8893MQL/MBL operates like other I

KSZ8893MQL/MBL’s 8-bit registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations.

Details of I

2

2

C slave devices. Addressing the

C read/write operations and related timing information can be found in the AT24C02 Datasheet.

Two fixed 8-bit device addresses are used to address the KSZ8893MQL/MBL in I

2 the other is for write. The addresses are as follow:

C slave mode. One is for read;

1011_1111 <read>

1011_1110 <write>

The following is a sample procedure for programming the KSZ8893MQL/MBL using the I

2

C slave serial bus:

1. Enable C slave mode by setting the KSZ8893MQL/MBL strap-in pins PS[1:0] (pins 100 and 101, respectively) to “01”.

2. Power up the board and assert reset to the KSZ8893MQL/MBL. After reset, the “Start Switch” bit (register 1 bit [0]) is set to ‘0’.

3. Configure the desired register settings in the KSZ8893MQL/MBL, using the I

2

C write operation.

4. Read back and verify the register settings in the KSZ8893MQL/MBL, using the I

2

C read operation.

5. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893MQL/MBL with the programmed settings.

Note:

The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.

Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down” can be programmed after the switch has been started.

SPI Slave Serial Bus Configuration

In managed mode, the KSZ8893MQL/MBL can be configured as a SPI slave device. In this mode, a SPI master device (external controller/CPU) has complete programming access to the KSZ8893MQL/MBL’s 142 registers.

Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly accessed via registers 121 to 131.

The KSZ8893MQL/MBL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write. SPI multiple read and multiple write are also supported by the KSZ8893MQL/MBL to expedite register read back and register configuration, respectively.

SPI multiple read is initiated when the master device continues to drive the KSZ8893MQL/MBL SPIS_N input pin

(SPI Slave Select signal) low after a byte (a register) is read. The KSZ8893MQL/MBL internal address counter increments automatically to the next byte (next register) after the read. The next byte at the next register address is shifted out onto the KSZ8893MQL/MBL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by de-asserting the SPIS_N signal to the KSZ8893MQL/MBL.

Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8893MQL/MBL SPIS_N input pin low after a byte (a register) is written. The KSZ8893MQL/MBL internal address counter increments automatically to the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8893MQL/MBL SDA input pin is written to the next register address. SPI multiple write continues until the

SPI master device terminates it by de-asserting the SPIS_N signal to the KSZ8893MQL/MBL.

For both SPI multiple read and multiple write, the KSZ8893MQL/MBL internal address counter wraps back to register address zero once the highest register address is reached. This feature allows all 142

KSZ8893MQL/MBL registers to be read, or written with a single SPI command from any initial register address.

The KSZ8893MQL/MBL is capable of supporting a 5MHz SPI bus.

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The following is a sample procedure for programming the KSZ8893MQL/MBL using the SPI bus:

1. At the board level, connect the KSZ8893MQL/MBL pins as follows:

KSZ8893MQL/MBL Pin # KSZ8893MQL/MBL Signal Name External Processor Signal Description

99 SPI Slave Select

97

98

SPIS_N

SCL

(SPIC)

SDA

(SPID)

96 SPIQ

SPI Clock

SPI Data

(Master output; Slave input)

SPI Data

(Master input; Slave output)

Table 15. KSZ8893MQL/MBL SPI Connections

2. Enable SPI slave mode by setting the KSZ8893MQL/MBL strap-in pins PS[1:0] (pins 100 and 101, respectively) to “10”.

3. Power up the board and assert reset to the KSZ8893MQL/MBL.

After reset, the “Start Switch” bit (register 1 bit [0]) is set to ‘0’.

4. Configure the desired register settings in the KSZ8893MQL/MBL, using the SPI write or multiple write command.

5. Read back and verify the register settings in the KSZ8893MQL/MBL, using the SPI read or multiple read command.

6. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893MQL/MBL with the programmed settings.

Note:

The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.

Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down” can be programmed after the switch has been started.

The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”.

The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of SPIC.

SPIS_N

SPIC

SPID

SPIQ

X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

WRITE DATA WRITE COMMAND WRITE ADDRESS

Figure 8. SPI Write Data Cycle

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SPIS_N

SPIC

SPID

SPIQ

X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

READ COMMAND READ ADDRESS READ DATA

Figure 9. SPI Read Data Cycle

SPIS_N

SPIC

SPID

SPIQ

X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

WRITE COMMAND WRITE ADDRESS

SPIS_N

SPIC

SPID

SPIQ

D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Byte 1

D7 D6 D5 D4 D3 D2 D1 D0

Byte 2 Byte N Byte 3 ...

Figure 10. SPI Multiple Write

SPIS_N

SPIC

SPID

SPIQ

X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X

D7 D6 D5 D4 D3 D2 D1 D0

READ COMMAND READ ADDRESS Byte 1

SPIS_N

SPIC

SPID

SPIQ

X X X X X X X X X X X X X X X

X

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Byte 2 Byte 3

Figure 11. SPI Multiple Read

X X X X X X X X

D7 D6 D5 D4 D3 D2 D1 D0

Byte N

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Loopback Support

The KSZ8893MQL/MBL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near-end (Remote) Loopback.

Far-end Loopback

Far-end loopback is conducted between the KSZ8893MQL/MBL’s two PHY ports. The loopback path starts at the

“Originating.” PHY port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating” PHY port’s transmit outputs (TXP/TXM).

Bit [0] of registers 29 and 45 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, the

MII Management register 0, bit [14] can be used to enable far-end loopback.

The far-end loopback path is illustrated in the following figure.

R X P /

R X M

T X P /

T X M

O riginating

P H Y P o rt

PM D /PM A

PC S

M A C

S w itch

M A C

PC S

PM D /PM A

L o o p B ac k

P H Y P o rt

Figure 12: Far-End Loopback Path

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Near-end (Remote) Loopback

Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8893MQL/MBL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s

PMD/PMA, and ends at the PHY port’s transmit outputs (TXPx/TXMx).

Bit [1] of registers 26 and 42 is used to enable near-end loopback for ports 1 and 2, respectively. Alternatively, the MII Management register 31, bit [1] can be used to enable near-end loopback.

The near-end loopback paths are illustrated in the following figure.

RXP1 /

RXM 1

PHY

Port 1

TXP1 /

TXM 1

PMD/PMA

PCS

MAC

Switch

MAC

PCS

PMD/PMA

RXP2 /

RXM 2

PHY

Port 2

Figure 13. Near-end (Remote) Loopback Path

TXP2 /

TXM 2

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MII Management (MIIM) Registers

The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I mechanism than the MIIM interface.

2

C, and SMI interfaces can also be used to access some of these registers. The latter three interfaces use a different mapping

The “PHYADs” by defaults are assigned “0x1” for PHY1 (port 1) and “0x2” for PHY2 (port 2). Additionally, these

“PHYADs” can be programmed to the PHY addresses specified in bits[7:3] of Register 15 (0x0F): Global Control

13.

The “REGAD” supported are 0x0-0x5, 0x1D and 0x1F.

Register Number

PHYAD = 0x1, REGAD = 0x0

PHYAD = 0x1, REGAD = 0x1

PHYAD = 0x1, REGAD = 0x2

PHYAD = 0x1, REGAD = 0x3

PHYAD = 0x1, REGAD = 0x4

PHYAD = 0x1, REGAD = 0x5

PHYAD = 0x1, 0x6 – 0x1C

PHYAD = 0x1, 0x1D

PHYAD = 0x1, 0x1E

PHYAD = 0x1, 0x1F

PHYAD = 0x2, REGAD = 0x0

PHYAD = 0x2, REGAD = 0x1

PHYAD = 0x2, REGAD = 0x2

PHYAD = 0x2, REGAD = 0x3

PHYAD = 0x2, REGAD = 0x4

PHYAD = 0x2, REGAD = 0x5

PHYAD = 0x2, 0x6 – 0x1C

PHYAD = 0x2, 0x1D

PHYAD = 0x2, 0x1E

PHYAD = 0x2, 0x1F

Description

PHY1 Basic Control Register

PHY1 Basic Status Register

PHY1 Physical Identifier I

PHY1 Physical Identifier II

PHY1 Auto-Negotiation Advertisement Register

PHY1 Auto-Negotiation Link Partner Ability Register

PHY1 Not supported

PHY1 LinkMD Control/Status

PHY1 Not supported

PHY1 Special Control/Status

PHY2 Basic Control Register

PHY2 Basic Status Register

PHY2 Physical Identifier I

PHY2 Physical Identifier II

PHY2 Auto-Negotiation Advertisement Register

PHY2 Auto-Negotiation Link Partner Ability Register

PHY2 Not supported

PHY2 LinkMD Control/Status

PHY2 Not supported

PHY2 Special Control/Status

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PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control

PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control

Bit Name

15

14

13

12

11

Soft reset

Loopback

Force 100

AN enable

Power down

RO NOT SUPPORTED

R/W = 1, Perform loopback, as indicated:

Port 1 Loopback (reg. 29, bit 0 = ‘1’)

Start: RXP2/RXM2 (port 2)

Loopback: PMD/PMA of port 1’s PHY

End: TXP2/TXM2 (port 2)

Port 2 Loopback (reg. 45, bit 0 = ‘1’)

Start: RXP1/RXM1 (port 1)

Loopback: PMD/PMA of port 2’s PHY

End: TXP1/TXM1 (port 1)

=0, Normal operation

R/W =1, 100 Mbps

=0, 10 Mbps

R/W =1, Auto-negotiation enabled

=0, Auto-negotiation disabled

R/W =1, Power down

=0, Normal operation

10 Isolate

9 Restart AN R/W =1, Restart auto-negotiation

=0, Normal operation full duplex

R/W =1, Full duplex

=0, Half duplex

7 Collision test RO NOT SUPPORTED

6 Reserved RO

5 Hp_mdix R/W 1 = HP Auto MDI/MDI-X mode

0 = Micrel Auto MDI/MDI-X mode

4 Force MDI R/W =1, Force MDI (transmit on RXP / RXM pins)

=0, Normal operation (transmit on TXP / TXM pins)

3 Disable MDIX R/W =1, Disable auto MDI-X

=0, Enable auto MDI-X far-end =1, Disable far-end fault detection fault

1 Disable transmit

=0, Normal operation

R/W =1, Disable transmit

0 Disable LED

=0, Normal operation

R/W =1, Disable LED

=0, Normal operation

0

0

0

1

0

Reg. 28, bit 6

Reg. 44, bit 6

Reg. 28, bit 7

Reg. 44, bit 7

0 Reg. 29, bit 3

Reg. 45, bit 3

0

0 Reg. 29, bit 5

Reg. 45, bit 5

Reg. 28, bit 5

Reg. 44, bit 5

0

0

1 Reg. 31, bit 7

Reg. 47, bit 7

0 Reg. 29, bit 1

Reg. 45, bit 1

0

0

0

0

Reg. 29, bit 0

Reg. 45, bit 0

Reg. 29, bit 2

Reg. 45, bit 2

Reg. 29, bit 4

Reg. 29, bit 6

Reg. 45, bit 6

Reg. 29, bit 7

Reg. 45, bit 7

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PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status

PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status

Bit Name

15

14

T4 capable

100 Full capable capable

Full capable

Half capable

RO

RO

RO

RO

RO

=0, Not 100 BASE-T4 capable

=1, 100BASE-TX full duplex capable

=0, Not capable of 100BASE-TX full duplex

=1, 100BASE-TX half duplex capable

=0, Not 100BASE-TX half duplex capable

=1, 10BASE-T full duplex capable

=0, Not 10BASE-T full duplex capable

=1, 10BASE-T half duplex capable

=0, Not 10BASE-T half duplex capable

10-7 Reserved RO

6 Preamble suppressed

5 AN complete RO

4

3

2

1

Far-end fault

AN capable

Link status

Jabber test

RO

RO

RO

RO

=1, Auto-negotiation complete

=0, Auto-negotiation not completed

=1, Far-end fault detected

=0, No far-end fault detected

=1, Auto-negotiation capable

=0, Not auto-negotiation capable

=1, Link is up

=0, Link is down

NOT SUPPORTED

=0, Not extended register capable capable

PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High

PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High

Bit Name R/W

15-0 PHYID high RO High order PHYID bits

PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low

PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low

Bit Name R/W

15-0 PHYID low RO Low order PHYID bits

0

KSZ8893MQL/MBL

0

0

0000

0

0

0

1

0

Reg. 30, bit 6

Reg. 46, bit 6

Reg. 31, bit 0

Reg. 28, bit 7

Reg. 44, bit 7

Reg. 30, bit 5

Reg. 46, bit 5

Default

0x0022

Default

0x1430

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PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability

KSZ8893MQL/MBL

PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability

Bit Name R/W

15 Next page RO NOT SUPPORTED

14 Reserved RO

13 Remote fault RO NOT SUPPORTED

12-11 Reserved RO

10 Pause R/W =1, Advertise pause ability

=0, Do not advertise pause ability

9 Reserved R/W

8 Adv 100 Full R/W =1, Advertise 100 full duplex ability

7

=0, Do not advertise 100 full duplex ability

Adv 100 Half R/W =1, Advertise 100 half duplex ability

=0, Do not advertise 100 half duplex

ability

6 Adv 10 Full

5 Adv 10 Half

R/W =1, Advertise 10 full duplex ability

=0, Do not advertise 10 full duplex ability

R/W =1, Advertise 10 half duplex ability

=0, Do not advertise 10 half duplex ability

0

0

0

00

1 Reg. 28, bit 4

Reg. 44, bit 4

0

1 Reg. 28, bit 3

1

Reg. 44, bit 3

Reg. 28, bit 2

Reg. 44, bit 2

1

1

Reg. 28, bit 1

Reg. 44, bit 1

Reg. 28, bit 0

Reg. 44, bit 0

00001

PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability

PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability

Bit Name

15 Next page RO NOT SUPPORTED

14

13

LP ACK

Remote fault

RO

RO

NOT SUPPORTED

NOT SUPPORTED

12-11 Reserved RO

10 Pause RO Link partner pause capability

9 Reserved RO

8 Adv 100 Full RO Link partner 100 full capability

7

6

5

Adv 100 Half

Adv 10 Full

Adv 10 Half

RO

RO

RO

Link partner 100 half capability

Link partner 10 full capability

Link partner 10 half capability

4-0 Reserved RO

0

0

0

00

0

Reg. 46, bit 4

0

0 Reg. 30, bit 3

Reg. 46, bit 3

0

Reg. 30, bit 4

0

0

Reg. 30, bit 2

Reg. 46, bit 2

Reg. 30, bit 1

Reg. 46, bit 1

Reg. 30, bit 0

Reg. 46, bit 0

00000

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PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status

PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status

Bit Name

14-13 Vct_result

(SC)

RO completed, this bit will be self-cleared.

0 = indicate cable diagnostic test (if enabled) has completed and the status information is valid for read.

00 = normal condition

01 = open condition detected in cable

10 = short condition detected in cable

11 = cable diagnostic test has failed

1 = Less than 10 meter short

Default Reference

0 Reg. 26, bit 4

Reg. 42, bit 4

Reg 42, bit[6:5]

12 Vct 10M Short

11-9 Reserved

8-0 Vct_fault_count

RO

RO Reserved

RO Distance to the fault.

It’s approximately 0.4m*vct_fault_count[8:0]

0 Reg. 26, bit 7

Reg. 42, bit 7

000

{0, (0x00)} {(Reg. 26, bit

0), 27,

bit[7:0])}

{(Reg. 42, bit

(Reg.

bit[7:0])}

PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status

PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status

Bit Name R/W

15-6 Reserved RO Reserved

5 Polrvs RO 1 = polarity is reversed

0 = polarity is not reversed

4

3

MDI-X status

Force_lnk

RO 1 = MDI-X

0 = MDI

R/W 1 = Force link pass

0 = Normal Operation

2 Pwrsave R/W 0 = Enable power saving

1 = Disable power saving

1 Remote

Loopback

R/W 1 = Perform Remote loopback, as follows:

Port 1 (reg. 26, bit 1 = ‘1’)

Start: RXP1/RXM1 (port 1)

Loopback: PMD/PMA of port 1’s PHY

End: TXP1/TXM1 (port 1)

Port 2 (reg. 42, bit 1 = ‘1’)

Start: RXP2/RXM2 (port 2)

Loopback: PMD/PMA of port 2’s PHY

End: TXP2/TXM2 (port 2)

0 = Normal Operation

Default Reference

{(0x00),00}

0 Reg. 31, bit 5

Reg. 47, bit 5

0

0

1

0

Reg. 30, bit 7

Reg. 46, bit 7

Reg. 26, bit 3

Reg. 42, bit 3

Reg. 26, bit 2

Reg. 42, bit 2

Reg. 26, bit 1

Reg. 42, bit 1

0

Do not change the default value.

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Register Map: Switch & PHY (8-bit registers)

Global Registers

Register (Decimal) Register (Hex)

0-1 0x00-0x01

2-15 0x02-0x0F

Description

Chip ID Registers

Global Control Registers

Port Registers

Register (Decimal) Register (Hex)

16-29

30-31

32-45

46-47

48-57

0x10-0x1D

0x1E-0x1F

0x20-0x2D

0x2E-0x2F

0x30-0x39

63 0x3F

Description

Port 1 Control Registers, including MII PHY Registers

Port 1 Status Registers, including MII PHY Registers

Port 2 Control Registers, including MII PHY Registers

Port 2 Status Registers, including MII PHY Registers

Port 3 Control Registers

Port 3 Status Register

KSZ8893MQL/MBL

Advanced Control Registers

Register (Decimal) Register (Hex)

96-111 0x60-0x6F

118-120

121-122

123-131

132

133

134-137

138

139

140-141

0x76-0x78

0x79-0x7A

0x7B-0x83

0x84

0x85

0x86-0x89

0x8A

0x8B

0x8C-0x8D

Description

TOS Priority Control Registers

User Defined Registers

Indirect Access Control Registers

Indirect Data Registers

Digital Testing Status Register

Digital Testing Control Register

Analog Testing Control Registers

Analog Testing Status Register

Analog Testing Control Register

QM Debug Registers

Global Registers

Register 0 (0x00): Chip ID0

Bit Name R/W

7-0 Family ID RO Chip family

Default

0x88

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Register 1 (0x01): Chip ID1 / Start Switch

Bit Name R/W

7-4 Chip ID RO 0x2 is assigned to M series. (93M)

3-1

0

Revision ID

Start Switch

RO

RW

Revision ID

= 1, start the chip when external pins

(PS1, PS0) = (0,1) or (1,0) or (1,1).

Note:

In (PS1, PS0) = (0, 0) mode, the chip will start automatically after trying to read the external

EEPROM. If EEPROM does not exist, the chip will use pin strapping and default values for all internal registers. If EEPROM is present, the contents in the

EEPROM will be checked. The switch will check: (1)

Register 0 = 0x88, (2) Register 1 bits [7:4] = 0x2. If this check is OK, the contents in the EEPROM will override chip registers’ default values.

= 0, chip will not start when external pins

(PS1, PS0) = (0,1) or (1,0) or (1,1).

-

-

Default

0x2

Register 2 (0x02): Global Control 0

Bit Name R/W

Back-off New back-off algorithm designed for UNH

Enable 1 = Enable

0 = Disable

Default

0

100

Do not change the default value.

Flow = 1, switch will not filter 802.1x “flow control” packets 0

Control Packet

1

Do not change the default value.

0

Do not change the default value.

0 Link

Age

Change = 1, link change from “link” to “no link” will cause fast aging (<800us) to age address table faster. After an age cycle is complete, the age logic will return to normal aging (about 200 sec).

Note:

If any port is unplugged, all addresses will be automatically aged out.

0

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Register 3 (0x03): Global Control 1

Bit Name R/W

Frames

R/W = 1, switch all packets including bad ones. Used solely for debugging purposes. Works in conjunction with sniffer mode only.

6 Reserved R/W Reserved

Do not change the default value.

Transmit

R/W = 1, will enable transmit direction flow control feature.

= 0, will not enable transmit direction flow control

Direction Flow

Control Enable feature. Switch will not generate any flow control

(PAUSE) frame.

R/W = 1, will enable receive direction flow control feature.

Receive

Direction Flow

Control Enable

= 0, will not enable receive direction flow control feature. Switch will not react to any flow control

(PAUSE) frame it receives.

Length 1 = will check frame length field in the IEEE packets.

Field Check If the actual length does not match, the packet will be dropped (for Length/Type field < 1500).

2 Aging Enable R/W 1 = enable age function in the chip

0 = disable age function in the chip

Age R/W 1 = turn on fast age (800us)

Enable

0 Aggressive 1 = enable more aggressive back off algorithm in half

Back-off

Enable duplex mode to enhance performance. This is not an

IEEE standard.

Default

0

0

1

1

0

0

0

0

Register 4 (0x04): Global Control 2

Bit Name R/W

7 Unicast

Port-VLAN

Mismatch

Discard

R/W This feature is used with port-VLAN (described in reg.

17, reg. 33, …)

= 1, all packets can not cross VLAN boundary

= 0, unicast packets (excluding unkown/multicast/ broadcast) can cross VLAN boundary

Note: Port mirroring is not supported if this bit is set to

“0”.

6 Multicast

Storm

R/W = 1, “Broadcast Storm Protection” does not include multicast packets. Only DA = FF-FF-FF-FF-FF-FF

Protection

Disable packets will be regulated.

= 0, “Broadcast Storm Protection” includes

DA = FF-FF-FF-FF-FF-FF and DA[40] = 1 packets.

Pressure = 1, carrier sense based backpressure is selected

Mode = 0, collision based backpressure is selected

Default

1

1

1

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Register 4 (0x04): Global Control 2 (continued)

Bit Name R/W

and Back

Pressure Fair

Mode

R/W = 1, fair mode is selected. In this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time.

= 0, in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be

“fair” to the flow control port.

Excessive

Collision Drop

R/W = 1, the switch will not drop packets when 16 or more collisions occur.

= 0, the switch will drop packets when 16 or more collisions occur.

Packet = 1, will accept packet sizes up to 1916 bytes

Support (inclusive). This bit setting will override setting from bit 1 of this register.

= 0, the max packet size will be determined by bit 1 of this register.

1 Legal

Maximum

Packet Size

Check Enable

R/W = 0, will accept packet sizes up to 1536 bytes

(inclusive).

= 1, 1522 bytes for tagged packets, 1518 bytes for untagged packets. Any packets larger than the specified value will be dropped.

Reserve

R/W = 1, each port is pre-allocated 48 buffers for high priority (q3, q2, and q1) packets. This selection is effective only when the multiple queue feature is turned on. It is recommended to enable this bit for multiple queue.

= 0, no reserved buffers for high priority packets.

Each port is pre-allocated 48 buffers for all priority packets (q3, q2,q1, and q0).

Default

1

0

0

SMRXD0

(pin 85) value during reset

1

Register 5 (0x05): Global Control 3

Bit Name R/W

7 802.1Q

Enable

R/W = 1, 802.1Q VLAN mode is turned on. VLAN table needs to set up before the operation.

5

4

Enable on

Switch MII

Interface

IPv6 MLD

Snooping

Enable

IPv6 MLD

Snooping

Option

= 0, 802.1Q VLAN is disabled.

R/W =1, IGMP snoop is enabled. All IGMP packets will be forwarded to the Switch MII port.

=0, IGMP snoop is disabled.

R/W IPv6 MLD snooping

1 = enable

0 = disable

R/W IPv6 MLD snooping option

1 = enable

0 = disable

Default

0

0

0

0

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Register 5 (0x05): Global Control 3 (continued)

Bit Name R/W

3

2-1

0

Weighted

Fair Queue

Enable

Reserved

Sniff Mode

Select

R/W 0 = always transmit higher priority packets first

1 = Weighted Fair Queueing enabled. When all four queues have packets waiting to transmit, the bandwidth allocation is q3:q2:q1:q0 = 8:4:2:1.

If any queues are empty, the highest non-empty queue gets one more weighting. For example, if q2 is empty, q3:q2:q1:q0 becomes (8+1):0:2:1.

R/W Reserved

Do not change the default values.

R/W = 1, will do RX AND TX sniff (both source port and destination port need to match)

= 0, will do RX OR TX sniff (either source port or destination port needs to match). This is the mode used to implement RX only sniff.

Default

0

00

0

Register 6 (0x06): Global Control 4

Bit Name R/W

7 Repeater =1, enable repeater mode

Mode

=0, disable repeater mode

Note:

For repeater mode, all ports need to be set to

100BASE-TX and half duplex mode. PHY ports need to have auto-negotiation disabled.

6 Switch MII Half

Duplex Mode

R/W = 1, enable MII interface half-duplex mode.

= 0, enable MII interface full-duplex mode.

Flow Control

Enable

R/W = 1, enable full duplex flow control on Switch MII interface.

= 0, disable full duplex flow control on Switch MII interface.

Default

0

Pin SMRXD2 strap option.

Pull-down(0):

Full-duplex mode

Pull-up(1):

Half-duplex mode

Note:

SMRXD2 has internal pulldown.

Pin SMRXD3 strap option.

Pull-down(0):

Disable flow control

Pull- up(1):

Enable flow control

Note:

SMRXD3 has internal pulldown.

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Register 6 (0x06): Global Control 4 (continued)

Bit Name R/W

10BT

MII = 1, the switch interface is in 10Mbps mode

= 0, the switch interface is in 100Mbps mode

Default

Pin SMRXD1 strap option.

Pull-down(0):

Enable

100Mbps

Pull-up(1):

Enable

10Mbps

Note:

SMRXD1 has internal pulldown.

0 VID

Replacement

R/W = 1, will replace NULL VID with port VID (12 bits)

= 0, no replacement for NULL VID

2-0 Broadcast R/W This register along with the next register determines

Storm

Protection

Rate

(1)

Bit [10:8] how many “64 byte blocks” of packet data are allowed on an input port in a preset period. The period is 67ms for 100BT or 500ms for 10BT. The default is 1%.

000

Register 7 (0x07): Global Control 5

Bit Name R/W

7-0 Broadcast

Storm

Protection

Rate

(1)

Bit [7:0]

R/W This register along with the previous register determines how many “64 byte blocks” of packet data are allowed on an input port in a preset period. The period is 67ms for 100BT or 500ms for 10BT. The default is 1%.

Note:

(1)

100BT Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63

Register 8 (0x08): Global Control 6

Bit Name R/W

7-0 Factory

Testing

R/W Reserved

Do not change the default values.

Register 9 (0x09): Global Control 7

Bit Name R/W

7-0 Factory

Testing

R/W Reserved

Do not change the default values.

Register 10 (0x0A): Global Control 8

Bit Name R/W

7-0 Factory

Testing

R/W Reserved

Do not change the default values.

Default

0x63

Default

0x00

Default

0x24

Default

0x35

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Register 11 (0x0B): Global Control 9

7 LEDSEL1 R/W LED mode select

See description in bit 1 of this register.

Default

LEDSEL1

(pin 23) value during reset

00

Do not change the default values.

0

Set to ‘0’ for normal operation.

10

1

Do not change the default values.

LEDSEL0 R/W LED mode select

This bit and bit 7 of this register select the LED mode.

For LED definitions, see pins 1, 2, 3, 4, 5 and 6 of Pin

Description and I/O Assignment listing.

Notes:

LEDSEL1 is also external strap-in pin #23.

LEDSEL0 is also external strap-in pin #70.

0 Special

TPID

R/W Used for direct mode forwarding from port 3. See description in spanning tree functional description. mode

0 = disable

1 = enable

Register 12 (0x0C): Global Control 10

7-6

5-4

3-2

1-0

LEDSEL0

(pin 70) value during reset

0

Tag_0x3 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x3.

Tag_0x2 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x2.

Tag_0x1 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x1.

Tag_0x0 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x0.

Default

01

01

00

00

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Register 13 (0x0D): Global Control 11

7-6

5-4

3-2

1-0

Tag_0x7 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x7.

Tag_0x6 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x6.

Tag_0x5 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x5.

Tag_0x4 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x4.

Register 14 (0x0E): Global Control 12

Default

11

11

10

10

7 Unknown Send packets with unknown destination MAC addresses to

Packet

Default specified port(s) in bits [2:0] of this register.

0 = disable

Port

Enable

1 = enable

Default

0

0x0

Do not change the default values.

2-0 Unknown Specify which port(s) to send packets with unknown

Packet

Default

Port destination MAC addresses. This feature is enabled by bit

[7] of this register.

Bit 2 stands for port 3.

Bit 1 stands for port 2.

Bit 0 stands for port 1.

An ‘1’ includes a port.

An ‘0’ excludes a port.

Register 15 (0x0F): Global Control 13

111

7-3 PHY

Address

R/W 00000 : N/A

00001 : Port 1 PHY address is 0x1

00010 : Port 1 PHY address is 0x2

11101 : Port 1 PHY address is 0x29

11110 : N/A

11111 : N/A

Note:

Port 2 PHY address = (Port 1 PHY address) + 1

Default

00001

000

Do not change the default values.

Port Registers

The following registers are used to enable features that are assigned on a per port basis. The register bit

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KSZ8893MQL/MBL

Register 16 (0x10): Port 1 Control 0

Register 32 (0x20): Port 2 Control 0

Register 48 (0x30): Port 3 Control 0

Bit Name R/W

7 Broadcast = 1, enable broadcast storm protection for

Storm

Protection

Enable ingress packets on port

= 0, disable broadcast storm protection

6 DiffServ

Priority

Classification

Enable

R/W = 1, enable DiffServ priority classification for ingress packets (IPv4 and IPv6) on port

= 0, disable DiffServ function

Priority

Classification

R/W = 1, enable 802.1p priority classification for ingress packets on port

Enable

= 0, disable 802.1p

4-3 Port-based R/W = 00, ingress packets on port will be

Priority

Classification classified as priority 0 queue if “Diffserv” or

“802.1p” classification is not enabled or fails to classify.

= 01, ingress packets on port will be classified as priority 1 queue if “Diffserv” or

“802.1p” classification is not enabled or fails to classify.

= 10, ingress packets on port will be classified as priority 2 queue if “Diffserv” or

“802.1p” classification is not enabled or fails to classify.

= 11, ingress packets on port will be classified as priority 3 queue if “Diffserv” or

“802.1p” classification is not enabled or fails to classify.

2

1

Tag Insertion

Tag Removal

Queues Select

Enable

Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time. The OR’ed result of

802.1p and DSCP overwrites the port priority.

R/W = 1, when packets are output on the port, the switch will add 802.1p/q tags to packets without

802.1p/q tags when received. The switch will not add tags to packets already tagged. The tag inserted is the ingress port’s “port VID”.

= 0, disable tag insertion

R/W = 1, when packets are output on the port, the switch will remove 802.1p/q tags from packets with 802.1p/q tags when received. The switch will not modify packets received without tags.

= 0, disable tag removal

R/W = 1, the port output queue is split into four priority queues.

= 0, single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority.

Default

0

0

0

00

0

0

0

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Register 17 (0x11): Port 1 Control 1

Register 33 (0x21): Port 2 Control 1

Register 49 (0x31): Port 3 Control 1

Bit Name R/W

7 Sniffer Port R/W = 1, Port is designated as sniffer port and will transmit packets that are monitored.

= 0, Port is a normal port

6

5

Receive Sniff R/W = 1, All packets received on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port”

= 0, no receive monitoring

Transmit Sniff R/W = 1, All packets transmitted on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port”

= 0, no transmit monitoring

4 Double Tag R/W = 1, All packets will be tagged with port default tag of ingress port regardless of the original packets are tagged or not

= 0, do not double tagged on all packets

Priority = 1, if the packet’s “user priority field” is greater

Ceiling than the “user priority field” in the port default tag register, replace the packet’s “user priority field” with the “user priority field” in the port default tag register.

= 0, do not compare and replace the packet’s

‘user priority field”

VLAN membership

R/W Define the port’s egress port VLAN membership.

The port can only communicate within the membership. Bit 2 stands for port 3, bit 1 stands for port 2, bit 0 stands for port 1.

An ‘1’ includes a port in the membership.

An ‘0’ excludes a port from membership.

Default

0

0

0

0

0

111

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Register 18 (0x12): Port 1 Control 2

Register 34 (0x22): Port 2 Control 2

Register 50 (0x32): Port 3 Control 2

Bit Name R/W Default

0

Do not change the default value.

6 Ingress

Filtering

VLAN = 1, the switch will discard packets whose VID port membership in VLAN table bits [18:16] does not include the ingress port.

= 0, no ingress VLAN filtering. non = 1, the switch will discard packets whose VID

PVID Packets does not match ingress port default VID.

= 0, no packets will be discarded

Flow

Control

R/W = 1, will always enable full duplex flow control on the port, regardless of AN result.

= 0, full duplex flow control is enabled based on

AN result.

0

0

0

Pin value during reset:

For port 1,

P1FFC pin

For port 2,

P2FFC pin

For port 3, this bit has no meaning. Flow control is set by

Reg. 6, bit 5.

Enable

R/W = 1, enable port’s half duplex back pressure

= 0, disable port’s half duplex back pressure

2 Transmit R/W = 1, enable packet transmission on the port

Enable

= 0, disable packet transmission on the port

1 Receive

Enable

R/W = 1, enable packet reception on the port

= 0, disable packet reception on the port

0 Learning

Disable

R/W = 1, disable switch address learning capability

= 0, enable switch address learning

Note:

Bits [2:0] are used for spanning tree support.

1

1

0

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Register 19 (0x13): Port 1 Control 3

Register 35 (0x23): Port 2 Control 3

Register 51 (0x33): Port 3 Control 3

Bit Name R/W

[15:8]

Tag Port’s default tag, containing

7-5 : User priority bits

4 : CFI bit

3-0 : VID[11:8]

Register 20 (0x14): Port 1 Control 4

Register 36 (0x24): Port 2 Control 4

Register 52 (0x34): Port 3 Control 4

Default

0x00

Bit Name R/W

Tag Port’s default tag, containing

[7:0]

Default

0x01

Note:

Registers 19 and 20 (and those corresponding to other ports) serve two purposes:

1. Associated with the ingress untagged packets, and used for egress tagging.

2. Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.

Register 21 (0x15): Port 1 Control 5

Register 37 (0x25): Port 2 Control 5

Register 53 (0x35): Port 3 Control 5

Bit Name R/W Default

0x0

Do not change the default values.

00

These bits determine what kinds of frames are limited and counted against ingress rate limiting.

= 00, limit and count all frames

= 01, limit and count Broadcast, Multicast, and flooded unicast frames

= 10, limit and count Broadcast and Multicast frames only

= 11, limit and count Broadcast frames only

0

= 1, each frame’s minimum inter frame gap

(IFG) bytes (12 per frame) are included in

Ingress and Egress rate limiting calculations.

= 0, IFG bytes are not counted.

0

= 1, each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations.

= 0, preamble bytes are not counted.

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Register 22 (0x16): Port 1 Control 6

Register 38 (0x26): Port 2 Control 6

Register 54 (0x36): Port 3 Control 6

Bit Name R/W

7-4 Ingress

Rate

3-0 Ingress

Rate

R/W

Ingress data rate limit for priority 1 frames

Ingress traffic from this priority queue is shaped according to the ingress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

R/W

Ingress data rate limit for priority 0 frames

Ingress traffic from this priority queue is shaped according to the ingress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

Default

0x0

0x0

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Register 23 (0x17): Port 1 Control 7

Register 39 (0x27): Port 2 Control 7

Register 55 (0x37): Port 3 Control 7

Bit Name R/W

7-4 Ingress

Rate

3-0 Ingress

Rate

R/W

Ingress data rate limit for priority 3 frames

Ingress traffic from this priority queue is shaped according to the ingress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

R/W

Ingress data rate limit for priority 2 frames

Ingress traffic from this priority queue is shaped according to the ingress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

Default

0x0

0x0

February 2010 74 M9999-021110-1.6

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Register 24 (0x18): Port 1 Control 8

Register 40 (0x28): Port 2 Control 8

Register 56 (0x38): Port 3 Control 8

Bit Name R/W

7-4 Egress

Rate

Rate

R/W

Egress data rate limit for priority 1 frames

Egress traffic from this priority queue is shaped according to the egress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

When TX multiple queue select enable is off

(only 1 queue per port), rate limiting applies only to priority 0 queue.

Pri0

Egress data rate limit for priority 0 frames.

Egress traffic from this priority queue is shaped according to the egress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

When TX multiple queue select enable is off

(only 1 queue per port), rate limiting applies only to priority 0 queue.

Default

0x0

0x0

February 2010 75 M9999-021110-1.6

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Register 25 (0x19): Port 1 Control 9

Register 41 (0x29): Port 2 Control 9

Register 57 (0x39): Port 3 Control 9

Bit Name R/W

7-4 Egress

Rate

Rate

R/W

Egress data rate limit for priority 3 frames

Egress traffic from this priority queue is shaped according to the egress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

When TX multiple queue select enable is off

(only 1 queue per port), rate limiting applies only to priority 0 queue.

Pri2

Egress data rate limit for priority 2 frames

Egress traffic from this priority queue is shaped according to the egress rate selected below:

0000 = Not limited (Default)

0001 = 64 Kbps

0010 = 128 Kbps

0011 = 256 Kbps

0100 = 512 Kbps

0101 = 1 Mbps

0110 = 2 Mbps

0111 = 4 Mbps

1000 = 8 Mbps

1001 = 16 Mbps

1010 = 32 Mbps

1011 = 48 Mbps

1100 = 64 Mbps

1101 = 72 Mbps

1110 = 80 Mbps

1111 = 88 Mbps

Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited).

When TX multiple queue select enable is off

(only 1 queue per port), rate limiting applies only to priority 0 queue.

Default

0x0

0x0

February 2010 76 M9999-021110-1.6

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Note:

Most of the contents in registers 26-31 and registers 42-47 for ports 1 and 2, respectively, can also be accessed with the MIIM PHY registers.

Register 26 (0x1A): Port 1 PHY Special Control/Status

Register 42 (0x2A): Port 2 PHY Special Control/Status

Register 58 (0x3A): Reserved, not applied to port 3

Bit Name

7

6-5

Vct 10M Short

Vct_result

RO

RO

4 Vct_en R/W

(SC) has completed, this bit will be self-cleared.

= 0, indicate cable diagnostic test (if enabled) has completed and the status information is valid for read.

3 Force_lnk R/W

11 = cable diagnostic test has failed

1 = Force link pass

0 = Normal Operation

2 Pwrsave R/W 0 = Enable power saving

1 = Disable power saving

1 Remote

Loopback

1 = Less than 10 meter short

00 = normal condition

01 = open condition detected in cable

10 = short condition detected in cable

R/W 1 = Perform Remote loopback, as follows:

Port 1 (reg. 26, bit 1 = ‘1’)

Start: RXP1/RXM1 (port 1)

Loopback: PMD/PMA of port 1’s PHY

End: TXP1/TXM1 (port 1)

Port 2 (reg. 42, bit 1 = ‘1’)

Start: RXP2/RXM2 (port 2)

Loopback: PMD/PMA of port 2’s PHY

End: TXP2/TXM2 (port 2)

0 = Normal Operation

Default

0

00

0

0

1

0

0

Distance to the fault.

It’s approximately 0.4m*vct_fault_count[8:0]

Register 27 (0x1B): Port 1 LinkMD Result

Register 43 (0x2B): Port 2 LinkMD Result

Register 59 (0x3B): Reserved, not applied to port 3

Bit Name

7-0 Vct_fault_count[7

:0]

RO

Bits[7:0] of VCT fault count

Distance to the fault.

It’s approximately 0.4m*Vct_fault_count[8:0]

Default

0x00

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Register 28 (0x1C): Port 1 Control 12

Register 44 (0x2C): Port 2 Control 12

Register 60 (0x3C): Reserved, not applied to port 3

Bit Name R/W

7 Auto

Negotiation

Enable

6 Force Speed

R/W = 0, disable auto negotiation; speed and duplex are determined by bits 6 and 5 of this register.

= 1, auto negotiation is on

R/W = 1, forced 100BT if AN is disabled (bit 7)

= 0, forced 10BT if AN is disabled (bit 7)

Default

For port 1, P1ANEN pin value during reset.

For port 2, P2ANEN pin value during reset

5 Force Duplex R/W = 1, forced full duplex if (1) AN is disabled or (2)

AN is enabled but failed.

= 0, forced half duplex if (1) AN is disabled or (2)

AN is enabled but failed.

Control capability

R/W = 1, advertise flow control (pause) capability

= 0, suppress flow control (pause) capability from transmission to link partner

3 Advertise

100BT Full

= 1, advertise 100BT full duplex capability

= 0, suppress 100BT full duplex capability from

Duplex

Capability transmission to link partner

2 Advertise

100BT Half

= 1, advertise 100BT half duplex capability

= 0, suppress 100BT half duplex capability from

Duplex

Capability transmission to link partner

1 Advertise

10BT Full

= 1, advertise 10BT full duplex capability

= 0, suppress 10BT full duplex capability from

Duplex

Capability transmission to link partner

0 Advertise = 1, advertise 10BT half duplex capability

10BT Half

Duplex

Capability

= 0, suppress 10BT half duplex capability from transmission to link partner

For port 1, P1SPD pin value during reset.

For port 2, P2SPD pin value during reset.

For port 1, P1DPX pin value during reset.

For port 2, P2DPX pin value during reset.

ADVFC pin value during reset.

1

1

1

1

February 2010 78 M9999-021110-1.6

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Register 29 (0x1D): Port 1 Control 13

Register 45 (0x2D): Port 2 Control 13

Register 61 (0x3D): Reserved, not applied to port 3

Bit Name R/W

7

6

5

LED Off

Txdis

Restart AN

R/W = 1, turn off all port’s LEDs (LEDx_3, LEDx_2,

LEDx_1, LEDx_0, where “x” is the port number).

These pins will be driven high if this bit is set to one.

= 0, normal operation

R/W = 1, disable the port’s transmitter

= 0, normal operation

R/W = 1, restart auto-negotiation

= 0, normal operation

Far- end Fault

R/W = 1, disable far-end fault detection and pattern transmission.

= 0, enable far-end fault detection and pattern transmission

3

Default

0

0

0

0

0

Note: Only port 1 supports fiber.

This bit is applicable to port

1 only.

Power Down R/W = 1, power down

= 0, normal operation

MDI/MDI-X

R/W = 1, disable auto MDI/MDI-X function

= 0, enable auto MDI/MDI-X function

1

0

Force MDI

Loopback

R/W If auto MDI/MDI-X is disabled,

= 1, force PHY into MDI mode (transmit on

RXP/RXM pins)

=

0, force PHY into MDI-X mode (transmit on

TXP/TXM pins)

R/W = 1, perform loopback, as indicated:

Port 1 Loopback (reg. 29, bit 0 = ‘1’)

Start: RXP2/RXM2 (port 2)

Loopback: PMD/PMA of port 1’s PHY

End: TXP2/TXM2 (port 2)

Port 2 Loopback (reg. 45, bit 0 = ‘1’)

Start: RXP1/RXM1 (port 1)

Loopback: PMD/PMA of port 2’s PHY

End: TXP1/TXM1 (port 1)

= 0, normal operation

0

For port 2,

P2MDIXDIS pin value during reset.

0

0

For port 2,

P2MDIX pin value during reset.

February 2010 79 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

Register 30 (0x1E): Port 1 Status 0

Register 46 (0x2E): Port 2 Status 0

Register 62 (0x3E): Reserved, not applied to port 3

Bit Name R/W

7

6

5

4

MDI-X Status

AN Done

Link Good

RO

RO

RO

RO

= 1, MDI-X

= 0, MDI

= 1, auto-negotiation completed

= 0, auto-negotiation not completed

= 1, link good

= 0, link not good

= 1, link partner flow control (pause) capable

= 0, link partner not flow control (pause) capable

3

2

1

0

Partner Flow

Control

Capability

Partner 100BT

Full Duplex

Capability

Partner 100BT

Half Duplex

Capability

Partner 10BT

Full Duplex

Capability

Partner 10BT

Half Duplex

Capability

RO

RO

RO

RO

= 1, link partner 100BT full duplex capable

= 0, link partner not 100BT full duplex capable

= 1, link partner 100BT half duplex capable

= 0, link partner not 100BT half duplex capable

= 1, link partner 10BT full duplex capable

= 0, link partner not 10BT full duplex capable

= 1, link partner 10BT half duplex capable

= 0, link partner not 10BT half duplex capable

0

0

0

0

Default

0

0

0

0

Register 31 (0x1F): Port 1 Status 1

Register 47 (0x2F): Port 2 Status 1

Register 63 (0x3F): Port 3 Status 1

Bit Name R/W

7 Hp_mdix R/W 1 = HP Auto MDI/MDI-X mode

0 = Micrel Auto MDI/MDI-X mode

Default

1

Note: Only ports

1 and 2 are PHY ports.

This bit is not applicable to port

3 (MII).

0

5 Polrvs RO

Do not change the default value.

1 = polarity is reversed

0 = polarity is not reversed

0

Note: Only ports

1 and 2 are PHY ports.

This bit is not applicable to port

3 (MII).

0

Control Enable

RO

Control Enable

RO

1 = transmit flow control feature is active

0 = transmit flow control feature is inactive

1 = receive flow control feature is active

0 = receive flow control feature is inactive

0

February 2010 80 M9999-021110-1.6

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Register 31 (0x1F): Port 1 Status 1 (continued)

Register 47 (0x2F): Port 2 Status 1 (continued)

Register 63 (0x3F): Port 3 Status 1 (continued)

Bit Name R/W

2 Operation

Speed

RO

1 Operation

Duplex

RO

1 = link speed is 100Mbps

0 = link speed is 10Mbps

1 = link duplex is full

0 = link duplex is half

0 Far-end Fault RO = 1, Far-end fault status detected

= 0, no Far-end fault status detected

Default

0

0

0

Note: Only port

1 supports fiber.

This bit is applicable to port 1 only.

Advanced Control Registers

The IPv4/IPv6 TOS Priority Control Registers implement a fully decoded, 128-bit DSCP (Differentiated Services

Code Point) register set that is used to determine priority from the ToS (Type of Service) field in the IP header.

The most significant 6 bits of the ToS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bits in the DSCP register to determine the priority.

Register 96 (0x60): TOS Priority Control Register 0

Bit Name R/W

7-6

5-4

3-2

DSCP[7:6]

DSCP[5:4]

DSCP[3:2]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x0C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x08.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x04.

1-0 DSCP[1:0] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x00.

Default

00

00

00

00

February 2010 81 M9999-021110-1.6

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Register 97 (0x61): TOS Priority Control Register 1

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[15:14]

DSCP[13:12]

DSCP[11:10]

DSCP[9:8]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x1C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x18.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x14.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x10.

Register 98 (0x62): TOS Priority Control Register 2

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[23:22]

DSCP[21:20]

DSCP[19:18]

DSCP[17:16]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x2C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x28.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x24.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x20.

00

00

00

00

00

00

KSZ8893MQL/MBL

Default

00

Default

00

February 2010 82 M9999-021110-1.6

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Register 99 (0x63): TOS Priority Control Register 3

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[31:30]

DSCP[29:28]

DSCP[27:26]

DSCP[25:24]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x3C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x38.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x34.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x30.

Register 100 (0x64): TOS Priority Control Register 4

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[39:38]

DSCP[37:36]

DSCP[35:34]

DSCP[33:32]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x4C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x48.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x44.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x40.

00

00

00

00

00

00

KSZ8893MQL/MBL

Default

00

Default

00

February 2010 83 M9999-021110-1.6

Micrel, Inc.

Register 101 (0x65): TOS Priority Control Register 5

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[47:46]

DSCP[45:44]

DSCP[43:42]

DSCP[41:40]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x5C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x58.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x54.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x50.

Register 102 (0x66): TOS Priority Control Register 6

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[55:54]

DSCP[53:52]

DSCP[51:50]

DSCP[49:48]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x6C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x68.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x64.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x60.

00

00

00

00

00

00

KSZ8893MQL/MBL

Default

00

Default

00

February 2010 84 M9999-021110-1.6

Micrel, Inc.

Register 103 (0x67): TOS Priority Control Register 7

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[63:62]

DSCP[61:60]

DSCP[59:58]

DSCP[57:56]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x7C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x78.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x74.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x70.

Register 104 (0x68): TOS Priority Control Register 8

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[71:70]

DSCP[69:68]

DSCP[67:66]

DSCP[65:64]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x8C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x88.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x84.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x80.

00

00

00

00

00

00

KSZ8893MQL/MBL

Default

00

Default

00

February 2010 85 M9999-021110-1.6

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Register 105 (0x69): TOS Priority Control Register 9

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[79:78]

DSCP[77:76]

DSCP[75:74]

DSCP[73:72]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x9C.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x98.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x94.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0x90.

Register 106 (0x6A): TOS Priority Control Register 10

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[87:86]

DSCP[85:84]

DSCP[83:82]

DSCP[81:80]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xAC.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xA8.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xA4.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xA0.

00

00

00

00

00

00

KSZ8893MQL/MBL

Default

00

Default

00

February 2010 86 M9999-021110-1.6

Micrel, Inc.

Register 107 (0x6B): TOS Priority Control Register 11

Bit Name R/W

7-6

5-4

3-2

1-0

DSCP[95:94]

DSCP[93:92]

DSCP[91:90]

DSCP[89:88]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xBC.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xB8.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xB4.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xB0.

Register 108 (0x6C): TOS Priority Control Register 12

Bit Name

7-6

5-4

3-2

1-0

DSCP[103:102] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xCC.

DSCP[101:100] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xC8.

DSCP[99:98]

DSCP[97:96]

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xC4.

R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xC0.

00

00

00

00

00

00

KSZ8893MQL/MBL

Default

00

Default

00

February 2010 87 M9999-021110-1.6

Micrel, Inc.

Register 109 (0x6D): TOS Priority Control Register 13

Bit Name

7-6

5-4

3-2

1-0

DSCP[111:110] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xDC.

DSCP[109:108] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xD8.

DSCP[107:106] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xD4.

DSCP[105:104] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xD0.

Register 110 (0x6E): TOS Priority Control Register 14

Bit Name

7-6

5-4

3-2

1-0

DSCP[119:118] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xEC.

DSCP[117:116] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xE8.

DSCP[115:114] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xE4.

DSCP[113:112] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xE0.

00

00

00

00

00

00

KSZ8893MQL/MBL

Default

00

Default

00

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Register 111 (0x6F): TOS Priority Control Register 15

Bit Name

7-6

5-4

3-2

1-0

DSCP[127:126] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xFC.

DSCP[125:124] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xF8.

DSCP[123:122] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xF4.

DSCP[121:120] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP

TOS/DiffServ/Traffic Class value is 0xF0.

Registers 112 to 117

Default

00

00

00

00

Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address is used as the Source

Address for the MAC’s full duplex flow control (PAUSE) frame.

Register 112 (0x70): MAC Address Register 0

Bit Name R/W Default

0x00

Register 113 (0x71): MAC Address Register 1

Bit Name R/W Default

0x10

Register 114 (0x72): MAC Address Register 2

Bit Name R/W Default

0xA1

Register 115 (0x73): MAC Address Register 3

Bit Name R/W Default

0xFF

Register 116 (0x74): MAC Address Register 4

Bit Name R/W Default

0xFF

Register 117 (0x75): MAC Address Register 5

Bit Name R/W

7-0 MACA[7:0] R/W

Default

0xFF

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Micrel, Inc. KSZ8893MQL/MBL

Registers 118 to 120

Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KSZ8893MQL/MBL and the external processor.

Register 118 (0x76): User Defined Register 1

Bit Name R/W

7-0 UDR1 R/W

Register 119 (0x77): User Defined Register 2

Bit Name R/W

7-0 UDR2 R/W

Default

0x00

Default

0x00

Register 120 (0x78): User Defined Register 3

Bit Name R/W

7-0 UDR3

Registers 121 to 131

R/W

Default

0x00

Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC address table, and MIB counters.

Register 121 (0x79): Indirect Access Control 0

Bit Name R/W Default

000

4 Read High /

Write Low

1-0 Indirect

Address High

Do not change the default values.

R/W = 1, read cycle

= 0, write cycle

00 = static MAC address table selected

01 = VLAN table selected

10 = dynamic MAC address table selected

11 = MIB counter selected

R/W Bits [9:8] of indirect address

0

00

00

Register 122 (0x7A): Indirect Access Control 1

Bit Name R/W

7-0 Indirect

Address Low

R/W Bits [7:0] of indirect address

Default

0000_0000

Note:

A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.

Register 123 (0x7B): Indirect Data Register 8

Bit Name R/W

Status

RO This bit is applicable only for dynamic MAC address table and MIB counter reads.

= 1, read is still in progress

= 0, read has completed

Default

0

2-0 Indirect

[66:64]

RO Bits [66:64] of indirect data

0000

000

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Register 124 (0x7C): Indirect Data Register 7

Bit Name R/W

[63:56]

Data Bits [63:56] of indirect data

Register 125 (0x7D): Indirect Data Register 6

Bit Name R/W

[55:48]

Data Bits [55:48] of indirect data

Register 126 (0x7E): Indirect Data Register 5

Bit Name R/W

7-0 Indirect

[47:40]

R/W Bits [47:40] of indirect data

Register 127 (0x7F): Indirect Data Register 4

Bit Name R/W

[39:32]

Data Bits [39:32] of indirect data

Register 128 (0x80): Indirect Data Register 3

Bit Name R/W

7-0 Indirect

[31:24]

R/W Bits [31:24] of indirect data

Register 129 (0x81): Indirect Data Register 2

Bit Name R/W

[23:16]

Data Bits [23:16] of indirect data

Default

0000_0000

Default

0000_0000

Default

0000_0000

Default

0000_0000

Default

0000_0000

Default

0000_0000

Register 130 (0x82): Indirect Data Register 1

Bit Name R/W

Data Bits [15:8] of indirect data

[15:8]

Default

0000_0000

Register 131 (0x83): Indirect Data Register 0

Bit Name R/W

Data Bits [7:0] of indirect data

[7:0]

Registers 132 to 141

Default

0000_0000

Reserved registers 132 to 141 are used by Micrel for internal testing only. Do not change the values of these registers.

Register 132 (0x84): Digital Testing Status 0

Bit Name R/W

2-0 Om_split

Status

Default

00000

000

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Register 133 (0x85): Digital Testing Control 0

Bit Name R/W

Dbg[7:0]

Register 134 (0x86): Analog Testing Control 0

Bit Name R/W

(dgt_actl0)

Register 135 (0x87): Analog Testing Control 1

Bit Name R/W

(dgt_actl1)

Register 136 (0x88): Analog Testing Control 2

Bit Name R/W

(dgt_actl2)

Register 137 (0x89): Analog Testing Control 3

Bit Name R/W

(dgt_actl3)

Register 138 (0x8A): Analog Testing Status

Bit Name R/W

Register 139 (0x8B): Analog Testing Control 4

Bit Name R/W

(dgt_actl4)

Register 140 (0x8C): QM Debug 1

Bit Name R/W

QM_Debug bit[7:0]

Register 141 (0x8D): QM Debug 2

Bit Name R/W

Do not change the default values.

QM_Debug bit[8]

February 2010

KSZ8893MQL/MBL

Default

0x3F

Default

0x00

Default

0x00

Default

0x00

Default

0x00

Default

0x00

Default

0x40

Default

0x00

Default

0000_000

0

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Micrel, Inc. KSZ8893MQL/MBL

Static MAC Address Table

The KSZ8893MQL/MBL supports both a static and a dynamic MAC address table. In response to a Destination

Address (DA) look up, the KSZ8893MQL/MBL searches both tables to make a packet forwarding decision. In response to a Source Address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes.

The static DA look up result takes precedence over the dynamic DA look up result. If there is a DA match in both tables, the result from the static table is used. The entries in the static table will not be aged out by the

KSZ8893MQL/MBL.

The static table is accessed by a external processor via the SMI, SPI or I

2 performs all addition, modification and deletion of static MAC table entries.

C interfaces. The external processor

Bit Name

57-54 FID

R/W Default

R/W Filter VLAN ID – identifies one of the 16 active VLANs 0000

53 Use FID 0

52 Override

51 Valid

50-48 Forwarding

Ports

R/W = 1, use (FID+MAC) for static table look ups

= 0, use MAC only for static table look ups

R/W = 1, override port setting “transmit enable=0” or

“receive enable=0” setting

= 0, no override

R/W = 1, this entry is valid, the lookup result will be used

= 0, this entry is not valid

R/W These 3 bits control the forwarding port(s):

001, forward to port 1

010, forward to port 2

100, forward to port 3

011, forward to port 1 and port 2

110, forward to port 2 and port 3

101, forward to port 1 and port 3

111, broadcasting (excluding the

0

0

000

0x0000_0

000_0000

Table 16. Format of Static MAC Table (8 Entries)

Examples:

1. Static Address Table Read (Read the 2 nd

Entry)

Write to reg. 121 (0x79) with 0x10

Write to reg. 122 (0x7A) with 0x01

Then,

Read reg. 124 (0x7C), static table bits [57:56]

Read reg. 125 (0x7D), static table bits [55:48]

Read reg. 126 (0x7E), static table bits [47:40]

Read reg. 127 (0x7F), static table bits [39:32]

Read reg. 128 (0x80), static table bits [31:24]

Read reg. 129 (0x81), static table bits [23:16]

Read reg. 130 (0x82), static table bits [15:8]

Read reg. 131 (0x83), static table bits [7:0]

// Read static table selected

// Trigger the read operation

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2. Static Address Table Write (Write the 8 th

Entry)

Write to reg. 124 (0x7C), static table bits [57:56]

Write to reg. 125 (0x7D), static table bits [55:48]

Write to reg. 126 (0x7E), static table bits [47:40]

Write to reg. 127 (0x7F), static table bits [39:32]

Write to reg. 128 (0x80), static table bits [31:24]

Write to reg. 129 (0x81), static table bits [23:16]

Write to reg. 130 (0x82), static table bits [15:8]

Write to reg. 131 (0x83), static table bits [7:0]

Write to reg. 121 (0x79) with 0x00

Write to reg. 122 (0x7A) with 0x07

// Write static table selected

// Trigger the write operation

KSZ8893MQL/MBL

VLAN Table

The KSZ8893MQL/MBL uses the VLAN table to perform look ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (filter ID), VID (VLAN ID), and VLAN membership as described in the following table.

Bit Name R/W

19 Valid R/W

= 0, entry is invalid

18-16 Membership R/W Specify which ports are members of the VLAN. If a DA lookup fails (no match in both static and dynamic tables), the packet associated with this

VLAN will be forwarded to ports specified in this field. For example, 101 means port 3 and 1 are in this VLAN.

15-12 FID R/W Filter ID. KSZ8893MQL/MBL supports 16 active

VLANs represented by these four bit fields. FID is the mapped ID. If 802.1Q VLAN is enabled, the look up will be based on FID+DA and

FID+SA.

11-0 VID R/W IEEE 802.1Q 12 bits VLAN ID

Table 17. Format of Static VLAN Table (16 Entries)

Default

1

111

0x0

0x001

If 802.1Q VLAN mode is enabled, KSZ8893MQL/MBL will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place. If the VID is valid, the FID is retrieved. The FID+DA and FID+SA lookups are performed. The FID+DA look up determines the forwarding ports. If FID+DA fails, the packet will be broadcast to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned.

Examples:

1. VLAN Table Read (read the 3 rd

entry)

Write to reg. 121 (0x79) with 0x14

Write to reg. 122 (0x7A) with 0x02

Then,

Read reg. 129 (0x81), VLAN table bits [19:16]

Read reg. 130 (0x82), VLAN table bits [15:8]

Read reg. 131 (0x83), VLAN table bits [7:0]

// Read VLAN table selected

// Trigger the read operation

2. VLAN Table Write (write the 7 th

entry)

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Write to reg. 129 (0x81), VLAN table bits [19:16]

Write to reg. 130 (0x82), VLAN table bits [15:8]

Write to reg. 131 (0x83), VLAN table bits [7:0]

Write to reg. 121 (0x79) with 0x04

Write to reg. 122 (0x7A) with 0x06

// Write VLAN table selected

// Trigger the write operation

KSZ8893MQL/MBL

Dynamic MAC Address Table

The KSZ8893MQL/MBL maintains the dynamic MAC address table. Read access is allowed only.

Default

70-67

66

65-56

55-54

53-52

Ready

Reserved

MAC Empty

No of Valid

Entries

Time Stamp

Source Port

RO

RO

RO

RO

RO

= 1, entry is not ready, continue retrying until this bit is set to 0

= 0, entry is ready

Reserved

= 1, there is no valid entry in the table

= 0, there are valid entries in the table

Indicates how many valid entries in the table

0x3ff means 1K entries

0x001 means 2 entries

0x000 and bit 66 = 0 means 1 entry

0x000 and bit 66 = 1 means 0 entry

2 bits counter for internal aging

The source port where FID+MAC is learned

00 : port 1

01 : port 2

10 : port 3

1

00_0000_0000

00

51-48 FID 0x0

0x0000_0000_0000

Table 18. Format of Dynamic MAC Address Table (1K Entries)

Example:

Dynamic MAC Address Table Read (read the 1 st

entry and retrieve the MAC table size)

Write to reg. 121 (0x79) with 0x18

Write to reg. 122 (0x7A) with 0x00

// Read dynamic table selected

// Trigger the read operation

Then,

Read reg. 123 (0x7B), bit [7]

dynamic table bits [66:64]

// if bit 7 = 1, restart (reread) from this register

Read reg. 124 (0x7C), dynamic table bits [63:56]

Read reg. 125 (0x7D), dynamic table bits [55:48]

Read reg. 126 (0x7E), dynamic table bits [47:40]

Read reg. 127 (0x7F), dynamic table bits [39:32]

Read reg. 128 (0x80), dynamic table bits [31:24]

Read reg. 129 (0x81), dynamic table bits [23:16]

Read reg. 130 (0x82), dynamic table bits [15:8]

Read reg. 131 (0x83), dynamic table bits [7:0]

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MIB (Management Information Base) Counters

The KSZ8893MQL/MBL provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.”

Bit Name

31 Overflow RO

= 0, no counter overflow

= 1, counter value is valid

= 0, counter value is not valid

29-0 Counter values RO Counter value

Table 19. Format of “Per Port” MIB Counters

Default

0

0

0

“Per Port” MIB counters are read using indirect memory access. The base address offsets and address ranges for all three ports are:

Port 1, base is 0x00 and range is (0x00-0x1f)

Port 2, base is 0x20 and range is (0x20-0x3f)

Port 3, base is 0x40 and range is (0x40-0x5f)

Port 1 MIB counters are read using the indirect memory offsets in the following table.

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

0x10

0x11

0x12

0x0

0x1

0x2

0x3

0x4

0x5

RxLoPriorityByte

RxHiPriorityByte

RxUndersizePkt

RxFragments

RxOversize

RxJabbers

RxSymbolError

RxCRCError

RxAlignmentError

RxControl8808Pkts

RxPausePkts

RxBroadcast

RxMulticast

RxUnicast

Rx64Octets

Rx65to127Octets

Rx128to255Octets

Rx256to511Octets

Rx512to1023Octets

Description

Rx lo-priority (default) octet count including bad packets

Rx hi-priority octet count including bad packets

Rx undersize packets w/ good CRC

Rx fragment packets w/ bad CRC, symbol errors or alignment errors

Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes)

Rx packets longer than 1522 bytes w/ either CRC errors, alignment errors, or symbol errors (depends on max packet size setting)

Rx packets w/ invalid data symbol and legal packet size.

Rx packets within (64,1522) bytes w/ an integral number of bytes and a bad CRC (upper limit depends on max packet size setting)

Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC

(upper limit depends on max packet size setting)

Number of MAC control frames received by a port with 88-08h in EtherType field

Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType

(88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC

Rx good broadcast packets (not including error broadcast packets or valid multicast packets)

Rx good multicast packets (not including MAC control frames, error multicast packets or valid broadcast packets)

Rx good unicast packets

Total Rx packets (bad packets included) that were 64 octets in length

Total Rx packets (bad packets included) that are between 65 and 127 octets in length

Total Rx packets (bad packets included) that are between 128 and 255 octets in length

Total Rx packets (bad packets included) that are between 256 and 511 octets in length

Total Rx packets (bad packets included) that are between 512 and 1023 octets in length

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0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

Description

Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting)

TxLoPriorityByte

TxHiPriorityByte

Tx lo-priority good octet count, including PAUSE packets

Tx hi-priority good octet count, including PAUSE packets

TxLateCollision The number of times a collision is detected later than 512 bit-times into the Tx of a packet

TxPausePkts

TxBroadcastPkts

TxMulticastPkts

TxUnicastPkts

TxDeferred

TxTotalCollision

Number of PAUSE frames transmitted by a port

Tx good broadcast packets (not including error broadcast or valid multicast packets)

Tx good multicast packets (not including error multicast packets or valid broadcast packets)

Tx good unicast packets

Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium

Tx total collision, half duplex only

TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions

TxSingleCollision Successfully Tx frames on a port for which Tx is inhibited by exactly one collision

TxMultipleCollision Successfully Tx frames on a port for which Tx is inhibited by more than one collision

Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets

Bit Name

30-16 Reserved

15-0 Counter Value RO Counter Value

Table 21. Format of “All Port Dropped Packet” MIB Counters

Default

N/A

0

“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters are shown in the following table:

0x100

0x101

0x102

0x103

0x104

0x105

Port1 TX Drop Packets

Port2 TX Drop Packets

Port3 TX Drop Packets

Port1 RX Drop Packets

Port2 RX Drop Packets

Port3 RX Drop Packets

Description

TX packets dropped due to lack of resources

TX packets dropped due to lack of resources

TX packets dropped due to lack of resources

RX packets dropped due to lack of resources

RX packets dropped due to lack of resources

RX packets dropped due to lack of resources

Table 22. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets

Examples:

1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)

Write to reg. 121 (0x79) with 0x1c

Write to reg. 122 (0x7A) with 0x0e

Then

// Read MIB counters selected

// Trigger the read operation

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Read reg. 128 (0x80), overflow bit [31] valid bit [30] counter bits [29:24]

Read reg. 129 (0x81), counter bits [23:16]

Read reg. 130 (0x82), counter bits [15:8]

Read reg. 131 (0x83), counter bits [7:0]

KSZ8893MQL/MBL

// If bit 31 = 1, there was a counter overflow

// If bit 30 = 0, restart (reread) from this register

2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)

Write to reg. 121 (0x79) with 0x1c

Write to reg. 122 (0x7A) with 0x2e

// Read MIB counter selected

// Trigger the read operation

Then,

Read reg. 128 (0x80), overflow bit [31] valid bit [30] counter bits [29:24]

Read reg. 129 (0x81), counter bits [23:16]

Read reg. 130 (0x82), counter bits [15:8]

Read reg. 131 (0x83), counter bits [7:0]

// If bit 31 = 1, there was a counter overflow

// If bit 30 = 0, restart (reread) from this register

3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)

Write to reg. 121 (0x79) with 0x1d

Write to reg. 122 (0x7A) with 0x00

Then

Read reg. 130 (0x82), counter bits [15:8]

Read reg. 131 (0x83), counter bits [7:0]

// Read MIB counter selected

// Trigger the read operation

Additional MIB Counter Information

“Per Port” MIB counters are designed as “read clear.” These counters will be cleared after they are read.

“All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or validity; therefore, the application must keep track of overflow and valid conditions.

To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are

160 registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds.

A high performance SPI master is also recommended to prevent counters overflow.

February 2010 98 M9999-021110-1.6

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Absolute Maximum Ratings

(1)

Supply Voltage

(V

DDATX

, V

DDARX

, V

DDIO

) ........................... –0.5V to +4.0V

Input Voltage (all inputs). ............................. –0.5V to +5.0V

Output Voltage (all outputs) ......................... –0.5V to +4.0V

Lead Temperature (soldering, 10sec.) ....................... 270°C

Storage Temperature (T s

) .........................–55°C to +150°C

KSZ8893MQL/MBL

Operating Ratings

(2)

Supply Voltage

(V

DDATX

, V

DDARX

, V

DDIO

).....................+3.1V to +3.5V

Ambient Temp. of MQL(T

A

) ...................0°C to +70°C

Ambient Temp. of MQLI/MBL AM(T

Junction Temp. (T

J

) ..........................................125°C

Package Thermal Resistance

(3)

A

) -40°C to +85°C

JA

) No Air Flow........................ 42.91°C/W

PQFP (θ

JC

) No Air Flow.......................... 19.6°C/W

JA

) No Air Flow...................... 38.50°C/W

LFBGA (θ

JC

) No Air Flow...................... 12.50°C/W

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Electrical Characteristics

(1)

KSZ8893MQL/MBL

Supply Current -

Current consumption is for the single 3.3V supply KSZ8893MQL/MBL device only, and includes the 1.2V supply voltages (VDDA, VDDAP, VDDC) that are provided by the KSZ8893MQL/MBL via power output pin 22.

- Each PHY port’s transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V

100BASE-TX

(transceiver + digital I/O)

10BASE-T

(transceiver + digital I/O)

TTL Inputs

Input High Voltage

Input Low Voltage

Input Current

I

I

I

100BASE-TX Operation (All Ports @ 100% Utilization)

ddxio

VDDATX, VDDARX, VDDIO = 3.3V

10BASE-T Operation (All Ports @ 100% Utilization)

ddxio

V

V in ih il

VDDATX, VDDARX, VDDIO = 3.3V

V in

= GND ~ VDDIO

TTL Outputs

Output High Voltage

Output Low Voltage

Output Tri-State Leakage

V oh

V ol

I

I oh ol

= -8 mA

= 8 mA

|I oz

|

100BASE-TX Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

Voltage

Output Voltage Imbalance

Rise/Fall Time

Rise/Fall Time Imbalance

Duty Cycle Distortion

Overshoot

Reference Voltage of ISET

Output Jitter

10BASE-T Receive

V

V o imb

100

Ω termination across differential output.

100

Ω termination across differential output

T r

/T f

V set

Peak-to-peak

Squelch Threshold

V sq

5 MHz square wave

10BASE-T Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

Voltage

Output Jitter

V p

100

Ω termination across differential output

Peak-to-peak

2.0V

-10µA

2.4V

120mA

90mA

0.8V

10µA

0.4V

10µA

0.95V 1.05V

3ns 5ns

0ns 0.5ns

+ 0.25ns

5%

0.5V

400mV

2.4V

2%

1.8ns 3.5ns

February 2010 100 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

Notes:

1. Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level.

2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage

level (Ground to V

DD

)

3. No (HS) heat spreader in this package. The thermal junction to ambient (θ

JA

) and the thermal junction to case (θ

JC

) are under air velocity

0m/s.

4. Specification for packaged product only. A single port’s transformer consumes an additional 45mA at 3.3V for 100BASE-T and 70mA at

3.3V for 10BASE-T.

February 2010 101 M9999-021110-1.6

Micrel, Inc.

Timing Specifications

EEPROM Timing

KSZ8893MQL/MBL

Figure 14. EEPROM Interface Input Timing Diagram

Figure 15. EEPROM Interface Output Timing Diagram

Timing Parameter

t cyc1 t s1 t h1 t ov1

Description

Setup time

Hold time

Min

20

20

Typ

Table 23. EEPROM Timing Parameters

Max Unit

ns ns

February 2010 102 M9999-021110-1.6

Micrel, Inc.

SNI Timing

KSZ8893MQL/MBL

Figure 16. SNI Input Timing Diagram

Figure 17. SNI Output Timing Diagram

Timing Parameter Description

t cyc2 t s2 t h2 t ov2

Clock cycle

Setup time

Hold time

Output valid

Min

10

0

0

Typ

100

3

Table 24. SNI Timing Parameters

Max

6

Unit

ns ns ns ns

February 2010 103 M9999-021110-1.6

Micrel, Inc.

MII Timing

MAC Mode MII Timing

R e c e i v e

T i m i n g

M R X C L K

M R X D V

M R X D [ 3 : 0 ] t s 3 t cyc3

Figure 18. MAC Mode MII Timing – Data Received from MII

t h 3

KSZ8893MQL/MBL

Figure 19. MAC Mode MII Timing – Data Transmitted to MII

Timing Parameter Description

tcyc3

(100BASE-TX) tcyc3

(10BASE-T)

Clock cycle

100BASE-TX

Clock cycle

10BASE-T

Min Typ Max Unit

40 ns

400 ns th3 Hold 3 ns ns

Table 25. MAC Mode MII Timing Parameters

February 2010 104 M9999-021110-1.6

Micrel, Inc.

PHY Mode MII Timing

KSZ8893MQL/MBL

Figure 20. PHY Mode MII Timing – Data Received from MII

Figure 21. PHY Mode MII Timing – Data Transmitted to MII

Timing Parameter Description

tcyc4

(100BASE-TX) tcyc4

(10BASE-T)

Clock cycle

100BASE-TX

Clock cycle

10BASE-T

Min Typ Max Unit

40 ns

400 ns th4 Hold 1 ns ns

Table 26. PHY Mode MII Timing Parameters

February 2010 105 M9999-021110-1.6

Micrel, Inc.

RMII Timing

T ra n s m it

T im in g

R E F C L K tc y c

KSZ8893MQL/MBL

t

1 t

2

M T X D [1 :0 ]

M T X E N

Receive

Tim ing

R E FC LK

Figure 22: RMII Timing – Data Received from RMII tcyc

M R X D [1:0]

M R X D V t o d

Figure 23: RMII Timing – Data Input to RMII

February 2010

Timing Parameter Description Min Typ Max Unit

tcyc Clock

20 ns ns ns

Table 27: RMII Timing Parameters

106 M9999-021110-1.6

Micrel, Inc.

I2C Slave Mode Timing

KSZ8893MQL/MBL

Figure 24. I2C Input Timing

Figure 25. I2C Start Bit Timing

Figure 26. I2C Stop Bit Timing

Figure 27. I2C Input Timing

Timing Parameter Description Min Typ

Ttbs

Ttbh

Start bit setup time

Start bit hold time

33

33

Tsbs Stop bit setup time 2

Tsbh Stop bit hold time 33

Tov

Table 28. I2C Timing Parameters

Note

: Data is only allowed to change during SCL low time except start and stop bits.

February 2010

Max Unit

ns ns ns ns ns

107 M9999-021110-1.6

Micrel, Inc.

SPI Timing

Input Timing

KSZ8893MQL/MBL

Figure 28. SPI Input Timing

Timing Parameter Description

tCHSL tSLCH tCHSH tSHCH tSHSL tDVCH tCHDX tCLCH tCHCL tDLDH tDHDL

Min

SPIS_N inactive hold time

SPIS_N active setup time

SPIS_N active old time

SPIS_N inactive setup time

SPIS_N deselect time

90

90

90

90

100

Data input setup time

Data input hold time

Clock rise time

Clock fall time

20

30

Data input rise time

Data input fall time

Table 29. SPI Input Timing Parameters

Max

1

1

1

1

Units

ns ns us us us us ns ns ns ns ns

February 2010 108 M9999-021110-1.6

Micrel, Inc.

Output Timing

KSZ8893MQL/MBL

Figure 29. SPI Output Timing

Timing Parameter Description Min Max Units

tCLQX tCLQV tCH tCL tQLQH

SPIQ hold time

Clock low to SPIQ valid

Clock high time

Clock low time

SPIQ rise time

0

90

90

0

60

50 ns ns ns ns tQHQL SPIQ fall time 50 ns tSHQZ SPIQ 100

Table 30. SPI Output Timing Parameters

February 2010 109 M9999-021110-1.6

Micrel, Inc.

T X + /T X -

Auto-Negotiation Timing

A u to-N egotiation - F ast L in k P u lse T im in g

F L P

B u rst

F L P

B u rst

T X + /T X -

t

F L P W t

B T B

C lock

P u lse

t

P W t

C T D

D ata

P u lse

t

P W t

C T C

Figure 30: Auto-Negotiation Timing

C lock

P u lse

KSZ8893MQL/MBL

D ata

P u lse

Timing Parameter Description

t

BTB

FLP burst to FLP burst t

FLPW

FLP burst width t

PW

Clock/Data pulse width t

CTD

Clock pulse to Data pulse t

CTC

Clock pulse to Clock pulse

Number of Clock/Data pulse per burst

Min

8

Typ

16

2

100

Max

24

Units

ms ms ns

55.5

111

64

128

69.5

139

µs

µs

17 33

Table 31: Auto-Negotiation Timing Parameters

February 2010 110 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

Reset Timing

The KSZ8893MQL/MBL reset timing requirement is summarized in the following figure and table.

Figure 31. Reset Timing

Parameter Description Min Units

t sr

Stable supply voltages to reset High 10 ms t cs

Configuration setup time t ch time

50

50 ns ns t rc

Reset to strap-in pin output 50 us

Table 32. Reset Timing Parameters

After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on the managed interface (I2C slave, SPI slave, SMI, MIIM).

February 2010 111 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

Reset Circuit

The reset circuit in Figure 32 is recommended for powering up the KSZ8893MQL/MBL if reset is triggered only by the power supply.

VCC

D1: 1N4148

KS8893M

RST

D1

R 10K

C 10uF

Figure 32. Recommended Reset Circuit

The reset circuit in Figure 33 is recommended for applications where reset is driven by another device (e.g., CPU,

FPGA, etc),. At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the

KSZ8893MQL/MBL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up.

VCC

February 2010

R 10K

D1

KS8893M CPU/FPGA

RST

RST_OUT_n

D2

C 10uF

D1, D2: 1N4148

Figure 33. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output

112 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

Selection of Isolation Transformers

An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements.

The following table gives recommended transformer characteristics.

Turns ratio

Open-circuit inductance (min.)

Leakage inductance (max.)

Inter-winding capacitance (max.)

D.C. resistance (max.)

Insertion loss (max.)

HIPOT (min.)

1 CT : 1 CT

350

μH

0.4

μH

12pF

0.9

Ω

1.0dB

1500Vrms

Table 33. Transformer Selection Criteria

100mV, 100kHz, 8mA

1MHz (min.)

0MHz – 65MHz

Magnetic Manufacturer

Bel Fuse

Bel Fuse (MagJack)

Bel Fuse (MagJack)

Part Number

S558-5999-U7

SI-46001

SI-50170

Auto MDI-X

Yes

Yes

Yes

Number of Port

1

1

1

Pulse (low cost) H1260 Yes 1

Transpower HB726 Yes 1

TDK (Mag Jack) 1 TLA-6T718 Yes

Table 34. Qualified Single Port Magnetics

Selection of Reference Crystal

Frequency tolerance (max)

Load capacitance (max)

Series resistance

±50

20

25 ppm pF

Ω

Table 35. Typical Reference Crystal Characteristics

February 2010 113 M9999-021110-1.6

Micrel, Inc.

Package Information

KSZ8893MQL/MBL

February 2010

Figure 34. 128-Pin PQFP Package

114 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

February 2010

Figure 35. 100_Ball LFBGA Package

115 M9999-021110-1.6

Micrel, Inc. KSZ8893MQL/MBL

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL: +1 (408) 944-0800 FAX: +1 (408) 474 1000 WEB: http:/www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a

Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

© 2007 Micrel, Incorporated.

February 2010 116 M9999-021110-1.6

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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:

KSZ8893MQL KSZ8893MQL AM KSZ8893MQL-EVAL KSZ8893MBL-TR KSZ8893MQL-AM-TR KSZ8893MQL-AM

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:

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