M45PE16 16-Mbit, page-erasable serial flash memory Features

M45PE16 16-Mbit, page-erasable serial flash memory Features
M45PE16
16-Mbit, page-erasable serial flash memory
with byte alterability and a 75 MHz SPI bus interface
Features
■
SPI bus compatible serial interface
■
75 MHz clock rate (maximum)
■
16-Mbit page-erasable flash memory
■
Page of 256 bytes
– Page write in 11 ms (typical)
– Page program in 0.8 ms (typical)
– Page erase in 10 ms (typical)
■
Sector erase (512 Kbits)
■
Hardware write protection of the bottom sector
(64 Kbytes)
■
Electronic signature
– JEDEC standard two-byte signature
(4015h)
– Unique ID code (UID) with 16 bytes readonly, available upon customer
■
2.7 to 3.6 V single supply voltage
■
Deep power-down mode 1 µA (typical)
■
More than 100 000 write cycles
■
More than 20 years data retention
■
Packages
– ECOPACK® (RoHS compliant)
May 2008
VFQFPN8 (MP)
6 × 5 mm
SO8W (MW)
208 mils body width
Rev 8
1/47
www.numonyx.com
1
Contents
M45PE16
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13
4.5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6
Active power, standby power and deep power-down modes . . . . . . . . . . 13
4.7
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4
Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4.1
2/47
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M45PE16
Contents
6.4.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 23
6.7
Page write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.8
Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9
Page erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10
Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11
Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.12
Release from deep power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3/47
List of tables
M45PE16
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
4/47
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics - 50 MHz operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC characteristics - 75 MHz operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SO8W - 8 lead plastic small outline, 208 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
M45PE16
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MLP and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20
Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 21
Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 22
Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Page erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Release from deep power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 31
Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Write protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SO8W - 8 lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . . 43
5/47
Description
1
M45PE16
Description
The M45PE16 is a 16-Mbit (2 Mbit x8 bit) serial paged flash memory accessed by a high
speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the page write or
page program instruction. The page write instruction consists of an integrated page erase
cycle followed by a page program cycle.
The memory is organized as 32 sectors, each containing 256 pages. Each page is 256-byte
wide. Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152
bytes.
The memory can be erased a page at a time, using the page erase instruction, or a sector at
a time, using the sector erase instruction.
Important note
Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of
2008.
Figure 1.
Logic diagram
VCC
D
Q
C
S
M45PE16
W
Reset
VSS
AI06884
Table 1.
Signal names
Signal name
6/47
Function
Direction
C
Serial Clock
Input
D
Serial data input
Input
Q
Serial data output
Output
S
Chip Select
Input
W
Write Protect
Input
Reset
Reset
Input
VCC
Supply voltage
VSS
Ground
M45PE16
Description
Figure 2.
MLP and SO8 connections
M45PE16
D
C
Reset
S
1
2
3
4
8
7
6
5
Q
VSS
VCC
W
AI06885C
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
7/47
Signal descriptions
2
Signal descriptions
2.1
Serial data output (Q)
M45PE16
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at serial data input (D) are latched on the rising edge of Serial Clock (C). Data on
serial data output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and serial data output (Q) is at high
impedance. Unless an internal read, program, erase or write cycle is in progress, the device
will be in the standby mode (this is not the deep power-down mode). Driving Chip Select (S)
Low enables the device, placing it in the active power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the device enters the reset mode. In this mode, the output Q is
high impedance.
If an internal operation (write, erase or program cycle) is in progress when Reset (Reset) is
driven Low, the device enters the reset mode and any on-going write, program or erase
cycle is aborted. The addressed data may be lost.
2.6
Write Protect (W)
This input signal puts the device in the hardware protected mode, when Write Protect (W) is
connected to VSS, causing the first 256 pages of memory to become read-only by protecting
them from write, program and erase operations. When Write Protect (W) is connected to
VCC, the first 256 pages of memory behave like the other pages of memory.
8/47
M45PE16
2.7
Signal descriptions
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/47
SPI modes
3
M45PE16
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 3.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI bus master
SPI memory
device
R
CS3
VCC
C Q D
VSS
R
VCC
C Q D
VSS
SPI memory
device
VSS
SPI memory
device
R
CS2 CS1
S
W
Reset
S
W
Reset
S
W
Reset
AI12836c
1. The Write Protect (W) signal should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the serial data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M45PE16 is not selected if the bus master leaves the S line in the high impedance
state. As the bus master may enter a state where all inputs/outputs are in high impedance at
the same time (for example, when the bus master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the bus master leaves the
SPI bus in high impedance.
10/47
M45PE16
SPI modes
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the bus
master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs.
Figure 4.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
11/47
Operating features
4
Operating features
4.1
Sharing the overhead of modifying data
M45PE16
To write or program one (or more) data bytes, two instructions are required: write enable
(WREN), which is one byte, and a page write (PW) or page program (PP) sequence, which
consists of four bytes plus data. This is followed by the internal cycle (of duration tPW or tPP).
To share this overhead, the page write (PW) or page program (PP) instruction allows up to
256 bytes to be programmed (changing bits from ‘1’ to ‘0’) or written (changing bits to ‘0’ or
‘1’) at a time, provided that they lie in consecutive addresses on the same page of memory.
4.2
An easy way to modify data
The page write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
The page write (PW) instruction is entered by driving Chip Select (S) Low, and then
transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte,
and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data
bytes are written to the data buffer, starting at the address given in the third address byte
(A7-A0). When Chip Select (S) is driven High, the write cycle starts. The remaining,
unchanged, bytes of the data buffer are automatically loaded with the values of the
corresponding bytes of the addressed memory page. The addressed memory page then
automatically put into an erase cycle. Finally, the addressed memory page is programmed
with the contents of the data buffer.
All of this buffer management is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a byte-by-byte basis.
For optimized timings, it is recommended to use the page write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several page write (PW)
sequences with each containing only a few bytes (see Section 6.7: Page write (PW),
Table 12: AC characteristics - 50 MHz operation, and Table 13: AC characteristics - 75 MHz
operation).
12/47
M45PE16
4.3
Operating features
A fast way to modify data
The page program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to ‘0’ that had
previously been set to ‘1’.
This might be:
●
when the designer is programming the device for the first time
●
when the designer knows that the page has already been erased by an earlier page
erase (PE) or sector erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available
●
when the designer knows that the only changes involve resetting bits to ‘0’ that are still
set to ‘1’. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see Section 6.8: Page
program (PP), Table 12: AC characteristics - 50 MHz operation, and Table 13: AC
characteristics - 75 MHz operation).
4.4
Polling during a write, program or erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (tPW, tPP, tPE, or tSE). The write in progress (WIP) bit is provided in the
status register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
4.5
Reset
An internal power-on reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the power-on process, and only
driving it High when VCC has reached the correct voltage level, VCC(min).
4.6
Active power, standby power and deep power-down modes
When Chip Select (S) is Low, the device is enabled, and in the active power mode.
When Chip Select (S) is High, the device is disabled, but could remain in the active power
mode until all internal cycles have completed (program, erase, write). The device then goes
in to the standby power mode. The device consumption drops to ICC1.
The deep power-down mode is entered when the specific instruction (the enter deep powerdown mode (DP) instruction) is executed. The device consumption drops further to ICC2.
The device remains in this mode until another specific instruction (the release from deep
power-down mode and read electronic signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the deep power-down mode. This can
be used as an extra software protection mechanism, when the device is not in active use, to
protect the device from inadvertent write, program or erase instructions.
13/47
Operating features
4.7
M45PE16
Status register
The status register contains two status bits that can be read by the read status register
(RDSR) instruction. See Section 6.4: Read status register (RDSR) for a detailed description
of the status register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M45PE16 boasts the following data protection mechanisms:
●
Power-on reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
●
Program, erase and write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a write enable (WREN)
instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
14/47
Power-up
–
Reset (Reset) driven Low
–
Write disable (WRDI) instruction completion
–
Page write (PW) instruction completion
–
Page program (PP) instruction completion
–
Page erase (PE) instruction completion
–
Sector erase (SE) instruction completion
●
The hardware protected mode is entered when Write Protect (W) is driven Low,
causing the first 256 pages of memory to become read-only. When Write Protect (W) is
driven High, the first 256 pages of memory behave like the other pages of memory
●
In addition to the low power consumption feature, the deep power-down mode offers
extra software protection from inadvertent write, program and erase instructions while
the device is not in active use.
M45PE16
5
Memory organization
Memory organization
The memory is organized as:
●
8192 pages (256 bytes each).
●
2,097,152 bytes (8 bits each)
●
32 sectors (512 Kbits, 65536 bytes each)
Each page can be individually:
●
programmed (bits are programmed from 1 to 0)
●
erased (bits are erased from 0 to 1)
●
written (bits are changed to either 0 or 1)
The device is page or sector erasable (bits are erased from 0 to 1).
Table 2.
Memory organization
Sector
Address range
31
1F0000h
1FFFFFh
30
1E0000h
1EFFFFh
29
1D0000h
1DFFFFh
28
1C0000h
1CFFFFh
27
1B0000h
1BFFFFh
26
1A0000h
1AFFFFh
25
190000h
19FFFFh
24
180000h
18FFFFh
23
170000h
17FFFFh
22
160000h
16FFFFh
21
150000h
15FFFFh
20
140000h
14FFFFh
19
130000h
13FFFFh
18
120000h
12FFFFh
17
110000h
11FFFFh
16
100000h
10FFFFh
15
0F0000h
0FFFFFh
14
0E0000h
0EFFFFh
13
0D0000h
0DFFFFh
12
0C0000h
0CFFFFh
11
0B0000h
0BFFFFh
10
0A0000h
0AFFFFh
9
090000h
09FFFFh
8
080000h
08FFFFh
15/47
Memory organization
M45PE16
Table 2.
Memory organization (continued)
Sector
Figure 5.
Address range
7
070000h
07FFFFh
6
060000h
06FFFFh
5
050000h
05FFFFh
4
040000h
04FFFFh
3
030000h
03FFFFh
2
020000h
02FFFFh
1
010000h
01FFFFh
0
000000h
00FFFFh
Block diagram
Reset
W
High voltage
generator
Control logic
S
C
D
I/O shift register
Q
Address register
and counter
Status
register
256-byte
data buffer
Y decoder
1FFFFFh
010000h
First 256 pages can
be made read-only
000000h
0000FFh
256 bytes (page size)
X decoder
AI06886
16/47
M45PE16
6
Instructions
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on serial data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ) or
read status register (RDSR) instruction, the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a page write (PW), page program (PP), page erase (PE), sector erase (SE),
write enable (WREN), write disable (WRDI), deep power-down (DP) or release from deep
power-down (RDP) instruction, Chip Select (S) must be driven High exactly at a byte
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses after Chip Select (S) being driven Low is
an exact multiple of eight.
All attempts to access the memory array during a write cycle, program cycle or erase cycle
are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected.
Table 3.
Instruction
Instruction set
Description
One-byte instruction
code
Address Dummy
bytes
bytes
Data
bytes
WREN
Write enable
0000 0110
06h
0
0
0
WRDI
Write disable
0000 0100
04h
0
0
0
RDID
Read identification
1001 1111
9Fh
0
0
1 to 3
RDSR
Read status register
0000 0101
05h
0
0
1 to ∞
READ
Read data bytes
0000 0011
03h
3
0
1 to ∞
Read data bytes at higher
speed
0000 1011
0Bh
3
1
1 to ∞
PW
Page write
0000 1010
0Ah
3
0
1 to 256
PP
Page program
0000 0010
02h
3
0
1 to 256
PE
Page erase
1101 1011
DBh
3
0
0
SE
Sector erase
1101 1000
D8h
3
0
0
DP
Deep power-down
1011 1001
B9h
0
0
0
RDP
Release from deep
power-down
1010 1011
ABh
0
0
0
FAST_READ
17/47
Instructions
6.1
M45PE16
Write enable (WREN)
The write enable (WREN) instruction (Figure 6) sets the write enable latch (WEL) bit.
The write enable latch (WEL) bit must be set prior to every page write (PW), page program
(PP), page erase (PE), and sector erase (SE) instruction.
The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 6.
Write enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
18/47
M45PE16
6.2
Instructions
Write disable (WRDI)
The write disable (WRDI) instruction (Figure 7) resets the write enable latch (WEL) bit.
The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The write enable latch (WEL) bit is reset under the following conditions:
●
Power-up
●
Write disable (WRDI) instruction completion
●
Page write (PW) instruction completion
●
Page program (PP) instruction completion
●
Page erase (PE) instruction completion
●
Sector erase (SE) instruction completion
Figure 7.
Write disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
19/47
Instructions
6.3
M45PE16
Read identification (RDID)
The read identification (RDID) instruction allows to read the device identification data:
●
Manufacturer identification (1 byte)
●
Device identification (2 bytes)
●
A unique ID code (UID) (17 bytes, of which 16 available upon customer request).
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx.
The device identification is assigned by the device manufacturer, and indicates the memory
type in the first byte (40h), and the memory capacity of the device in the second byte (15h).
The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes
of the optional customized factory data (CFD) content. The CFD bytes are read-only and
can be programmed with customers data upon their demand. If the customers do not make
requests, the devices are shipped with all the CFD bytes programmed to zero (00h).
Any read identification (RDID) instruction while an erase or program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on
serial data output (Q). Each bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 8.
The read identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the standby power mode. Once in
the standby power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Table 4.
Read identification (RDID) data-out sequence
Device identification
UID
Manufacturer identification
Memory type
Memory capacity
CFD length
CFD content
40h
15h
10h
16 bytes
20h
Figure 8.
Read identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
C
Instruction
D
Manufacturer identification
UID
Device identification
High Impedance
Q
15 14 13
MSB
MSB
3
2
1
0
MSB
AI06809c
20/47
M45PE16
6.4
Instructions
Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase or write cycle is in progress.
When one of these cycles is in progress, it is recommended to check the write in progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the status
register continuously, as shown in Figure 9.
The status bits of the status register are as follows:
6.4.1
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write, program
or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is
in progress.
6.4.2
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write, program or erase instruction is accepted.
Table 5.
Status register format
b7
b0
0
0
0
0
0
(1)
0
WIP(1)
WEL
1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically
set and reset by the internal logic of the device).
Figure 9.
Read status register (RDSR) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status register out
Status register out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
21/47
Instructions
6.5
M45PE16
Read data bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any read data bytes (READ)
instruction, while an erase, program or write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 10. Read data bytes (READ) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
D
3
2
1
0
MSB
Data out 1
High Impedance
Q
7
6
5
4
3
Data out 2
2
1
0
7
MSB
AI03748D
1. Address bits A23 to A21 are don’t care.
22/47
M45PE16
6.6
Instructions
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on serial data output (Q), each bit
being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 11.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing
the read sequence to be continued indefinitely.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip
Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read
data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 11. Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24-bit address
23 22 21
D
3
2
1
0
High Impedance
Q
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy byte
D
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
7
Q
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
AI04006
1. Address bits A23 to A21 are don’t care.
23/47
Instructions
6.7
M45PE16
Page write (PW)
The page write (PW) instruction allows bytes to be written in the memory. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. After the
write enable (WREN) instruction has been decoded, the device sets the write enable latch
(WEL).
The page write (PW) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address bytes and at least one data byte on serial data input (D). The
rest of the page remains unchanged if no power failure occurs during this write cycle.
The page write (PW) instruction performs a page erase cycle even if only one byte is
updated.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are written from the start address of the same
page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 12.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be written correctly within the same page. If less than
256 data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the page write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several page write (PW)
sequences with each containing only a few bytes (see Table 12: AC characteristics - 50 MHz
operation and Table 13: AC characteristics - 75 MHz operation).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the page write (PW) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed page write cycle (whose duration is
tPW) is initiated. While the page write cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed page write cycle, and is 0 when it is completed. At some unspecified time
before the cycle is complete, the write enable latch (WEL) bit is reset.
A page write (PW) instruction applied to a page that is hardware protected is not executed.
Any page write (PW) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
24/47
M45PE16
Instructions
Figure 12. Page write (PW) instruction sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-bit address
23 22 21
D
3
2
Data byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
D
7
6
MSB
5
4
3
2
Data byte 3
1
0
7
MSB
6
5
4
3
2
Data byte n
1
0
7
6
5
4
3
2
1
0
MSB
AI04045
1. Address bits A23 to A21 are don’t care.
2. 1 ≤ n ≤ 256.
25/47
Instructions
6.8
M45PE16
Page program (PP)
The page program (PP) instruction allows bytes to be programmed in the memory (changing
bits from ‘1’ to ‘0’, only). Before it can be accepted, a write enable (WREN) instruction must
previously have been executed. After the write enable (WREN) instruction has been
decoded, the device sets the write enable latch (WEL).
The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address bytes and at least one data byte on serial data input (D). If
the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are programmed from the start address of the
same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select
(S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 13.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see Table 12: AC
characteristics - 50 MHz operation and Table 13: AC characteristics - 75 MHz operation).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the page program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose
duration is tPP) is initiated. While the page program cycle is in progress, the status register
may be read to check the value of the write in progress (WIP) bit. The write in progress
(WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset.
A page program (PP) instruction applied to a page that is hardware protected is not
executed.
Any page program (PP) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
26/47
M45PE16
Instructions
Figure 13. Page program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-bit address
23 22 21
D
3
2
Data byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
D
7
6
MSB
5
4
3
2
Data byte 3
1
0
7
MSB
6
5
4
3
2
Data byte n
1
0
7
6
5
4
3
2
1
0
MSB
AI04044
1. Address bits A23 to A21 are don’t care.
2. 1 ≤ n ≤ 256.
27/47
Instructions
6.9
M45PE16
Page erase (PE)
The page erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The page erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (D). Any address inside the
page is a valid address for the page erase (PE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the page erase (PE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed page erase cycle (whose duration is tPE) is initiated.
While the page erase cycle is in progress, the status register may be read to check the value
of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed
page erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is complete, the write enable latch (WEL) bit is reset.
A page erase (PE) instruction applied to a page that is hardware protected is not executed.
Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 14. Page erase (PE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24-bit address
23 22
2
1
0
MSB
AI04046
1. Address bits A23 to A21 are don’t care.
28/47
M45PE16
6.10
Instructions
Sector erase (SE)
The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (D). Any address inside the
sector (see Table 3) is a valid address for the sector erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed sector erase cycle (whose duration is tSE) is
initiated. While the sector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is complete, the write enable latch (WEL) bit is reset.
A sector erase (SE) instruction applied to a sector that contains a page that is hardware
protected is not executed.
Any sector erase (SE) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 15. Sector erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24-bit address
23 22
2
1
0
MSB
AI03751D
1. Address bits A23 to A21 are don’t care.
29/47
Instructions
6.11
M45PE16
Deep power-down (DP)
Executing the deep power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the deep power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all write, program and erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the standby mode
(if there is no internal cycle currently in progress). But this mode is not the deep power-down
mode. The deep power-down mode can only be entered by executing the deep power-down
(DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in Table 11:
DC characteristics).
Once the device has entered the deep power-down mode, all instructions are ignored
except the release from deep power-down (RDP) instruction. This releases the device from
this mode.
The deep power-down mode automatically stops at power-down, and the device always
powers-up in the standby mode.
The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on serial data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced
to ICC2 and the deep power-down mode is entered.
Any deep power-down (DP) instruction, while an erase, program or write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 16. Deep power-down (DP) instruction sequence
S
0
1
2
3
4
5
6
7
tDP
C
Instruction
D
Standby mode
Deep power-down mode
AI03753D
30/47
M45PE16
6.12
Instructions
Release from deep power-down (RDP)
Once the device has entered the deep power-down mode, all instructions are ignored
except the release from deep power-down (RDP) instruction. Executing this instruction
takes the device out of the deep power-down mode.
The release from deep power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on serial data input (D). Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 17.
The release from deep power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the
standby mode. Chip Select (S) must remain High at least until this period is over. The device
waits to be selected, so that it can receive, decode and execute instructions.
Any release from deep power-down (RDP) instruction, while an erase, program or write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Release from deep power-down (RDP) instruction sequence
S
0
1
2
3
4
5
6
7
tRDP
C
Instruction
D
High Impedance
Q
Deep power-down mode
Standby mode
AI06807
31/47
Power-up and power-down
7
M45PE16
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
●
VCC(min) at power-up, and then for a further delay of tVSL
●
VSS at power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while VCC is less than the
POR threshold value, VWI – all operations are disabled, and the device does not respond to
any instruction.
Moreover, the device ignores all write enable (WREN), page write (PW), page program (PP),
page erase (PE) and sector erase (SE) instructions until a time delay of tPUW has elapsed
after the moment that VCC rises above the VWI threshold. However, the correct operation of
the device is not guaranteed if, by this time, VCC is still below VCC(min). No write, program or
erase instructions should be sent until the later of:
●
tPUW after VCC passed the VWI threshold
●
tVSL after VCC passed the VCC(min) level
These values are specified in Table 6.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for read instructions even if the tPUW delay is not yet fully elapsed.
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the power-up and power-down phases.
At power-up, the device is in the following state:
●
The device is in the standby mode (not the deep power-down mode).
●
The write enable latch (WEL) bit is reset.
●
The write in progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each
device in a system should have the VCC rail decoupled by a suitable capacitor close to the
package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the POR threshold
value, VWI, all operations are disabled and the device does not respond to any instruction
(the designer needs to be aware that if a power-down occurs while a write, program or erase
cycle is in progress, some data corruption can result).
32/47
M45PE16
Power-up and power-down
Figure 18. Power-up timing
VCC
VCC(max)
Program, erase and write commands are rejected by the device
Chip selection not allowed
VCC(min)
tVSL
Reset state
of the
device
Read access allowed
Device fully
accessible
VWI
tPUW
time
AI04009C
Table 6.
Power-up timing and VWI threshold
Symbol
Parameter
Min
Max
Unit
tVSL(1)
VCC(min) to S low
30
tPUW(1)
Time delay before the first write, program or erase instruction
1
10
ms
VWI(1)
Write inhibit voltage
1.5
2.5
V
µs
1. These parameters are characterized only, over the temperature range –40 °C to +85 °C.
33/47
Initial delivery state
8
M45PE16
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). All usable status register bits are ‘0’.
9
Maximum ratings
Stressing the device above the rating listed in the Table 7: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
Table 7.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature
TLEAD
Lead temperature during soldering
Min
Max
Unit
–65
150
°C
See note (1)
°C
VIO
Input and output voltage (with respect to ground)
–0.6
VCC + 0.6
V
VCC
Supply voltage
–0.6
4.0
V
–2000
2000
V
VESD
Electrostatic discharge voltage (human body
model)(2)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
34/47
M45PE16
10
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions
Symbol
VCC
TA
Table 9.
Parameter
Min
Max
Unit
Supply voltage
2.7
3.6
V
Ambient operating temperature
–40
85
°C
Min
Max
Unit
AC test measurement conditions(1)
Symbol
CL
Parameter
Load capacitance
30
pF
Input rise and fall times
5
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 19. AC test measurement I/O waveform
Input levels
Input and output
timing reference levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 10.
Symbol
COUT
CIN
Capacitance(1)
Parameter
Output capacitance (Q)
Input capacitance (other pins)
Test condition
Min
Max
Unit
VOUT = 0 V
8
pF
VIN = 0 V
6
pF
1. Sampled only, not 100% tested at TA = 25 °C and a frequency of 33 MHz.
35/47
DC and AC parameters
Table 11.
DC characteristics
Symbol
Parameter
Test condition (in addition to
those in Table 8)
Min
Max
Unit
ILI
Input leakage current
±2
µA
ILO
Output leakage current
±2
µA
ICC1
Standby current
(standby and reset modes)
S = VCC, VIN = VSS or VCC
50
µA
ICC2
Deep power-down current
S = VCC, VIN = VSS or VCC
10
µA
C = 0.1VCC / 0.9.VCC at 75 MHz,
Q = open
12
ICC3
36/47
M45PE16
Operating current
(FAST_READ)
mA
C = 0.1VCC / 0.9.VCC at 33 MHz,
Q = open
4
ICC4
Operating current (PW)
S = VCC
15
mA
ICC5
Operating current (SE)
S = VCC
15
mA
VIL
Input Low voltage
0.3VCC
V
VIH
Input High voltage
0.7VCC VCC+0.4
V
VOL
Output Low voltage
IOL = 1.6 mA
VOH
Output High voltage
IOH = –100 µA
– 0.5
0.4
VCC–0.2
V
V
M45PE16
Table 12.
DC and AC parameters
AC characteristics - 50 MHz operation
Test conditions specified in Table 8 and Table 9
Symbol
Alt.
fC
fC
fR
tCH(1)
tCL(1)
Parameter
Typ
Max
Unit
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP,
WREN, WRDI, RDSR, RDID
D.C.
50
MHz
Clock frequency for read instructions
D.C.
33
MHz
tCLH
Clock High time
9
ns
tCLL
Clock Low time
9
ns
0.1
V/ns
S active setup time (relative to C)
5
ns
S not active hold time (relative to C)
5
ns
Clock slew
tSLCH
Min
tCSS
tCHSL
rate 2
(peak to peak)
tDVCH
tDSU
Data in setup time
2
ns
tCHDX
tDH
Data in hold time
5
ns
tCHSH
S active hold time (relative to C)
5
ns
tSHCH
S not active setup time (relative to C)
5
ns
100
ns
tSHSL
tCSH
S deselect time
tSHQZ(2)
tDIS
Output disable time
8
ns
tCLQV
tV
Clock Low to Output Valid
8
ns
tCLQX
tHO
Output hold time
0
ns
tWHSL
Write protect setup time
50
ns
tSHWL
Write protect hold time
100
ns
tDP(2)
tRDP(2)
tRLRH(2)
S to deep power-down
3
µs
S High to standby mode
30
µs
tRST
Reset pulse width
10
µs
tRHSL
tREC
Reset recovery time
3
µs
tSHRH
Chip should have been deselected before
reset is de-asserted
10
ns
tPW(3)
Page write cycle time (256 bytes)
11
23
ms
Page program cycle time (256 bytes)
0.8
3
ms
tPP(3)
Page program cycle time (n Bytes)
int(n/8) × 0.025
tPE
Page erase cycle time
10
20
ms
tSE
Sector erase cycle time
1
5
s
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2,
int(17/8) = 3.
37/47
DC and AC parameters
Table 13.
M45PE16
AC characteristics - 75 MHz operation(1)
Test conditions specified in Table 8 and Table 9
Symbol
Alt.
fC
fC
fR
Min
Typ
Max
Unit
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP, WREN,
WRDI, RDSR, RDID
D.C.
75
MHz
Clock frequency for read instructions
D.C.
33
MHz
(2)
tCLH
Clock High time
6
ns
(2)
tCLL
Clock Low time
6
ns
0.1
V/ns
S active setup time (relative to C)
5
ns
S not active hold time (relative to C)
5
ns
tCH
tCL
Parameter
(3)
Clock slew rate
tSLCH
tCSS
tCHSL
(peak to peak)
tDVCH
tDSU
Data in setup time
2
ns
tCHDX
tDH
Data in hold time
5
ns
tCHSH
S active hold time (relative to C)
5
ns
tSHCH
S not active setup time (relative to C)
5
ns
100
ns
tSHSL
tCSH
S deselect time
tSHQZ(3)
tDIS
Output disable time
tCLQV
tV
tCLQX
tHO
Clock Low to Output valid under 30 pF/10 pF
8
ns
8/6
ns
Output hold time
0
ns
tWHSL(4)
Write protect setup time
20
ns
tSHWL(4)
Write protect hold time
100
ns
tDP(3)
S to deep power-down
3
µs
tRDP(3)
S High to standby mode
30
µs
tW
tPW(5)
tPP(5)
Write status register cycle time
3
15
ms
Page write cycle time (256 bytes)
11
23
ms
Page program cycle time (256 bytes)
0.8
3
ms
Page program cycle time (n bytes)
int(n/8) × 0.025(6)
tPE
Page erase cycle time
10
20
ms
tSE
Sector erase cycle time
1
5
s
1. Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008 (see Important note on
page 6).
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
5. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
6.
int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
38/47
M45PE16
DC and AC parameters
Figure 20. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
D
High Impedance
Q
AI01447C
Figure 21. Write protect setup and hold timing
W
tSHWL
tWHSL
S
C
D
High Impedance
Q
AI07439
Figure 22. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D ADDR.LSB IN
AI01449e
39/47
DC and AC parameters
Table 14.
M45PE16
Reset conditions
Test conditions specified in Table 8 and Table 9
Symbol
Alt.
tRLRH(1)
tRST
tSHRH
Parameter
Conditions
Min
Typ
Max
Unit
Reset pulse width
10
µs
Chip should have been
Chip Select High to
deselected before reset is
Reset High
de-asserted
10
ns
1. Value guaranteed by characterization, not 100% tested in production.
Table 15.
Timings after a Reset Low pulse(1)
Test conditions specified in Table 8 and Table 9
Symbol
Alt.
Parameter
Conditions: reset pulse occurred
Min
Typ
Max
Unit
While decoding an instruction
WREN, WRDI, RDID, RDSR, READ,
FAST_READ, PW, PP, PE, SE, DP,
RDP
30
µs
Under completion of an erase or
program cycle of a PW, PP, PE, SE
operation
300
µs
Device deselected (S High) and in
standby mode
0
µs
(2):
tRHSL
Reset
tREC recovery
time
1. All the values are guaranteed by characterization, and not 100% tested in production.
2.
S remains Low while Reset is Low.
Figure 23. Reset AC waveforms
S
tSHRH
Reset
tRHSL
tRLRH
AI06808
40/47
M45PE16
Package mechanical
To meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second level interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
Figure 24. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package outline
A
D
aaa C A
R1
D1
E1
E2
e
bbb
E
M C A B
B
2x
b
0.10 C B
aaa C B
11
Package mechanical
0.10 C A
D2
θ
L
A2
ddd
A
A1 A3
C
70-ME
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
41/47
Package mechanical
Table 16.
M45PE16
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package mechanical data
millimeters
inches
Symbol
A
Typ
Min
Max
Typ
Min
Max
0.85
0.80
1.00
0.033
0.031
0.039
0.00
0.05
0.000
0.002
0.014
0.019
0.126
0.142
A1
42/47
A2
0.65
0.026
A3
0.20
0.008
b
0.40
D
6.00
0.236
D1
5.75
0.226
D2
3.40
E
5.00
0.197
E1
4.75
0.187
E2
4.00
3.80
4.30
0.157
0.150
0.169
e
1.27
–
–
0.050
–
–
R1
0.10
0.00
0.004
0.000
L
0.60
0.50
0.024
0.020
0.35
3.20
0.48
3.60
0.75
0.016
0.134
0.029
Θ
12°
12°
aaa
0.15
0.006
bbb
0.10
0.004
ddd
0.05
0.002
M45PE16
Package mechanical
Figure 25. SO8W - 8 lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 17.
SO8W - 8 lead plastic small outline, 208 mils body width, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
2.50
Max
0.098
A1
0.00
0.25
0.000
0.010
A2
1.51
2.00
0.059
0.079
b
0.40
0.35
0.51
0.016
0.014
0.020
c
0.20
0.10
0.35
0.008
0.004
0.014
CP
0.10
0.004
D
6.05
0.238
E
5.02
6.22
0.198
0.245
E1
7.62
8.89
0.300
0.350
–
–
–
–
k
0°
10°
0°
10°
L
0.50
0.80
0.020
0.031
N (number of pins)
8
e
1.27
0.050
8
43/47
Ordering information
12
M45PE16
Ordering information
Table 18.
Ordering information scheme
Example:
M45PE16
–
V
MP 6
T
P
Device type
M45PE = page-erasable serial flash memory
Device function
16 = 16 Mbits (2 Mbit x8)
Operating voltage
V = VCC = 2.7 to 3.6 V
Package
MP = VFQFPN8 (MLP8) 6 × 5 mm
MW = SO8W (208 mils width)
Device grade
6 = industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Note:
44/47
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx sales office.
M45PE16
13
Revision history
Revision history
Table 19.
Document revision history
Date
Version
30-Apr-2003
1.0
Initial release.
04-Jun-2003
1.1
Description corrected of entering hardware protected mode (W must be
driven, and cannot be left unconnected).
26-Nov-2003
2.0
VIO(min) extended to -0.6V, and tPW(typ), tPP(typ) improved. tWHSL and
tSHWL added. MLP8 and SO16 pages added, and LGA package
removed. Table of contents, and Pb-free options added.
31-Mar-2004
2.1
Document promoted to product preview.
23-Jul-2004
2.2
SO connections illustration corrected. Wording clarified for device grade
in ordering information table.
3
An easy way to modify data, A fast way to modify data, Page write (PW)
and Page program (PP) sections updated to explain optimal use of page
write and page program instructions. Table 12: AC characteristics 50 MHz operation updated.
4
Document put in new template.
tSHQZ end timing line modified in Figure 22: Output timing.
Packages are ECOPACK® compliant. VDFPN and SO16W packages
removed. SO8W and VFQFPN8 packages added (see Section 11:
Package mechanical). Blank option removed below Plating technology in
Table 18: Ordering information scheme.
Document status promoted to preliminary data.
5
50 MHz frequency added, 25 MHz frequency removed.
Figure 3: Bus master and memory devices on the SPI bus modified,
Note 1 modified, Note 2 added. Small text changes.
ICC3 updated in Table 11: DC characteristics.
Table 12: AC characteristics - 50 MHz operation updated.
VIO max modified in Table 7: Absolute maximum ratings.
fR, tPW, tPP, updated in Table 12: AC characteristics - 50 MHz operation.
6
Section 2.5: Reset (Reset) modified and the signal can no longer be
driven Low to protect the array at a critical time. Section 2.7: VCC supply
voltage and Section 2.8: VSS ground added.
Figure 3: Bus master and memory devices on the SPI bus modified and
explanatory paragraph added.
At power-up The write in progress (WIP) bit is reset.
Note modified below Table 10: Capacitance.
Table 14: Reset conditions and Table 15: Timings after a Reset Low pulse
added. Small text changes.
Packages specifications updated (see Section 11: Package mechanical).
04-Aug-2005
15-Jun-2006
16-Oct-2006
09-Feb-2007
Changes
45/47
Revision history
Table 19.
Document revision history (continued)
Date
Version
10-Dec-2007
7
Applied Numonyx branding.
8
Document status promoted from preliminary data to datasheet.
Removed ‘low voltage’ from the title. Updated the value for the maximum
clock frequency (from 50 to 75 MHz) throughout the document.
Added: Table 13: AC characteristics - 75 MHz operation and ECOPACK®
text in Section 11: Package mechanical.
Modified: Table 11: DC characteristics, Figure 3: Bus master and memory
devices on the SPI bus, Section 3: SPI modes, and Section 6.3: Read
identification (RDID).
15-May-2008
46/47
M45PE16
Changes
M45PE16
Please Read Carefully:
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visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
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