BBK 9915 S DVD Recorder Service Manual
Below you will find brief information for DVD Recorder bbk9915S. The bbk9915S is a DVD recorder that can record all kinds of AV input signals, such as TV, ordinary VCD and DV video camera, into high quality DVD disc. It also has a high capacity DVD player, capable of realizing all functions of ordinary DVD player. In addition, it supports multiple input sources recording, providing multiple output signals, and offers multiple recording qualities and methods.
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R SERVICE MANUAL bbk9915S bbk9915S INDEX PREFACE PREFACE ............................................................................................................................................. 1 FRANT PENEL&REAR PENEL ....................................................................................................................................... 2 ................................................................................................................................ 3 REMOTE CONTROL BLOCK DIAGRAM BLOCK DIAGRAM ......................................................................................................................... 4 EXPLODED VIEW ....................................................................................................................................... 5 EXPLODED VIEW PARTS SPECIFICATIONS DMN-8600 ....................................................................................................................................... 6-8 SST39VF160 ............................................................................................................................................ 9 M13S128168A .....................................................................................................................................10 TSB41AB1 ............................................................................................................. 11 ADV7302 ....................................................................................................................... 12-13 CS4360 .................................................................................................................. 14-15 CS5333 ......................................................................................................................................... 16-17 IS24C16......................................................................................................................................... 18 74HC/HCT14 ........................................................................................................................................ 19 74ALVT16373............................................................................................................................... 20 MM1225 ................................................................................................................................................. 21-22 LP2995 ....................................................................................................................... 23 PQXXXEZ02Z .................................................................................................................................. 24 MS34X15 ..................................................................................................................... 25 TUNER ..................................................................................................................... 26 SCHEMATIC DIAGRAM&PCB SILKSCREEN MAIN SCHEMATIC ................................................................................................................................ 27-42 AV INPUT/OUTPUT SCHEMATIC........................................................................................................................................ 43-47 VFD DRIVER ......................................................................................................................................... 48-50 POWER SCHEMATIC .................................................................................................. 51-53 PARTS LIST MAIN BOARD ................................................................................................................................. 54-56 POWER BOARD ........................................................................................................................................... 57-58 KEY BOARD .......................................................................................................................... 59 FRONT AV BOARD ..................................................................................................................................... 60 DV BOARD ........................................................................................................................ 61 AV BOARD ........................................................................................................................ 62-63 Features Introduing American LSI (C-CUBE) Company's latest SoC AV system (AVS)recorder processor this unit is, capable of recording all kinds of AV input signals, such as TV, ordinary VCD and DV video camera, into high quality DVD disc. In addition, this player is also a high capacity DVD player, capable of realizing all functions of ordinary DVD player. This 2-in-1 init will make your life more enjoyable and wonderful. Support multiple input sources recording 1 Composite video input Provide multiple output signals 1 1.Composite video output 2 S-video output 2 S-video input 3 TV tuner input 3 Component video output 4 SCART output; 4 DV input 5 Analog audio terminal input. 5 L/R double audio channels output 6 Optical / Coaxial output. Multiple DVD recording qualities This unit provides you with 4 kinds of recording qualities, each of which has different resolution and recording time, to make you choose between high resolution picture quality and super long time of recording. Multiple recording methods This unit facilitates your usage with three kinds of recording methods: ordinarily manual recording, time recording, OTR one-touch recording and DV recording. Convenient menu operation This unit incorporates convenient interface menu operation. No need for you to remember the multifarious function buttons on remote control, and you can realize the majority of functions through using a few direction and selection buttons. Standby function Remote control standby function makes your operation more convenient and helps you fulfill time recording function on the basis of saving electric power. Highly intelligent upgrading function This unit has automatic upgrading function to make you upgrade it into the latest edition with our upgrading disc at any time. This player can use the following discs This unit can play DVD, DVD+R, DVD+RW, VCD, SVCD, CD-DA and MP3. This unit can record DVD+R and DVD+RW 1 Illustration of the Front Panel 4 3 2 5 6 7 8 11 10 bbk9915S 21 20 19 14 18 17 16 15 13 12 9 STANDBY/ON button 8 PLAY button 15 Right audio channel input terminal 2 Infrared remote sensor 9 NEXT button 16 Left audio channel input terminal 3 SOURCE button 10 PREV button 17 Front Video input terminal 4 VFD display window 11 REC button 18 Front S-Video input terminal 5 OPEN/CLOSE button 12 CH+ button 19 DV input terminal 6 STOP button 13 CH- button 20 STANDBY indicator 7 PAUSE button 14 Disc tray 21 Open the terminal protection cover here The function of buttons on the front panel is the same with that of the corresponding ones on the remote control. The input terminals on the front panel can only be seen when the protection cover is opened. Illustration of the Rear Panel 5 bbk9915S BBK ELECTRONICS CORP.,LTD. Made In China 2 3 4 5 6 7 8 9 10 11 12 13 TV TUNER input terminal 5 L/R channel audio input terminals 9 5.1 CH output terminals 2 TV TUNER output terminal 6 COMPOSITE VIDEO output terminal 10 L/R channel audio output terminal 11 COAXIAL output terminal 3 Rear video input terminal 7 S-VIDEO output terminal 12 OPTICAL output terminal Rear S-Video input terminal 8 13 SCART output terminal 4 COMPONENT VIDEO output terminal 4 STANDBY/ON button Illustration of the Remote Control Standby 2 AUDIO button Switch the audio channel Switch the audio stream STANDBY/ON AUDIO MUTE ZOOM ANGLE IS/PS 4 35 5 33 1 2 3 4 5 6 7 8 9 ADD/ CLEAR 0 GOTO 6 7 7 11 12 10 DISC OPER SETUP TIMER STOP NAVIGATION PLAY RETURN PAUSE/STEP 28 11 TIMER button 12 STOP button Enter the timing record setup 27 26 13 REV Stop playing/recording SKIP FWD 25 14 15 16 EDIT button Enter the edit mode 29 EDIT SETUP button System setup 30 9 CURSOR buttons Move the cursor 9 SELECT 10 8 31 8 TITLE button Display DVD titles menu 32 MENU TITLE NUMBER buttons ADD/CLEAR button Add/Clear the content items in the list window Clear the wrong input numbers 5 6 ZOOM button Zoom in the DVD picture. 34 4 MUTE button Mute the sound 36 1 2 3 3 OPEN/ CLOSE SUBTITLE PAL/NTSC REPEAT CH - CH+ RECORD SOURCE VOL- VOL+ 24 22 18 21 19 20 PLAY button Play a disc 23 17 bbk9915S 13 14 REV button Fast backward play 15 Forward button Fast forward play 16 PAL/NTSC button The PAL/NTSC TV output system conversion 17 REPEAT button 18 RECORD button Repeat playback 28 Record the external signals RETURN button 19 Back to the previous menu 29 Enter the disc operate mode 30 SELECT button 20 MENU button 21 22 23 ANGLE button 35 24 PREV button The progressive scan and interlacing scan conversion 25 NEXT button SUBTITLE button 26 IS/PS button Skip backward Skip forward PAUSE/STEP button Pause or play frame by frame Change subtitle languages 36 CH+ button Switch TV channels Change camera angles 34 27 CH- button Switch TV channels GOTO button Play from the desired location 33 VOL+ button Increase volume Display the disc menu Open/close PBC 32 27 VOL- button Decrease volume Confirm the selected item 31 SOURCE button Enter monitoring mode, switch external input signal source. DISC OPER button OPEN/CLOSE button 27 NAVIGATION button Display/hide menu Open or close the disc tray 5 BLOCK DIAGRAM DVD+RW DVD Recordable POW ER BOA RD 5AB 9915-0 AC 100V-240V INPUT 5VSTB +3.3V +5V +2.5V +12V -12V -22V FRONT AV INPUT BAB99150 DV(1394PHY) INPUT JACK Scart output Video output (component) A/V input Audio DAC 5.1CH Cs4 360 FP Control DMN-8600 NTSC/PAL Encoder (ADV 73 02) AV INPUT/OUTPUT BOARD 7AB9915-2 5.1CH Audio output MAIN BOARD NTSC/PAL Decoder SAA7115 Audio DV(1394) Phy Front Panel FRONT PANEL 4AB9915-0 DISPLAY &KEYPAD TV Tuner SDR/DDR SDRAM FLASH 39VF160 1M×16bit 2AB9915-1 2AB9915-2 4 EXPLODED VIEW 5 PARTS SPECIFICATIONS LSI Logic Confidential DMN8600 Chapter Application Example The DMN-8600’s high level of on-chip system integration drastically reduces system component count (BOM), and consequently system cost. Figure 2.1 shows a block diagram of an advanced DVD recorder appliance with analog time shift based on a DMN-8600. Figure 2.1 RF System Block Diagram for a DMN-8600-Based Advanced DVD Recorder Appliance SDR/DDR SDRAM TV Tuner w/ MTS Decoder Video NTSC/PAL Decoder Audio Audio ADC 4 Ch 1394 1394 Phy NTSC/PAL Encoder S/PDIF DMN-8600 Audio DAC 6 + 2 Ch RISC CPU DVD Recordable or IDE HDD 56 K Modem Modem DAA IR POTS Serial GPIO FP Control Front Panel Glue Logic SDRAM Display Keypad The only major components needed to complete the design are: • 8 to 64 Mbytes SDRAM • TV tuner • Analog video encoder and decoder DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved. 6 Video Audio LSI Logic Confidential Figure 6.1 DMN-8600 System Interfaces CLKI CLKX CLKO/DAC PLL_BYPASS RREF System Services Bitstream I/O 1394/Firewire BIO_PHY_DATA[7:0] BIO_PHY_CTL[1:0] BIO_LREQ BIO_LPS BIO_LINK_ON BIO_PHY_CLK MCONFIG MCONFIG[1:0] SDRAM_CLK[1:0] SDRAM_CLK[1:0] SDRAM_CKE SDRAM_CAS SDRAM_RAS SDRAM SDRAM_DQM[3:0] Interface SDRAM_A[15:0] SDRAM_DQ[31:0] SDRAM_WE SDRAM_DQS[3:0] SDRAM_VREF VI_CLK[0] VI_D[9:2] Video I/O VI_VSYNC[0] Interface VO_D[15:0] VO_CLK DVD (SD) Interface SD_DATA[7:0] SD_SECSTART SD_CLK SD_RDREQ SD_WRREQ SD_ACK SD_ERROR SBP Interface SBP_DATA SBP_CLK SBP_REQ SBP_RD SBP_ACK SBP_FRAME SPI (Serial I/O) SIO_SPI_CLK SIO_SPI_MOSI SIO_SPI_MISO SIO_SPI_CS[3:0] IDC (Serial I/O) Boundary Scan (JTAG) DMN-8600 AI_SCLK AO_SCLK AI_MCLKO AO_MCLKO AI_D[1:0] AO_D[3:0] AI_FSYNC AO_FSYNC AO_IEC958 Audio I/O Interface H_INT H_RST H_DATA[31:0] H_ADDR[2:0] H_DMAREQ H_RD H_RD/WR H_CS H_WAIT H_DTACK Host Slave Interface M_GPIO[5:0] M_RST M_CS[5:0] M_A[26:22] M_A[21:6]/M_D[15:0] M_A[5:1] M_UWE, M_UDS M_RD/WR, M_LWE M_OE, M_LDS M_ALE M_WAIT M_DTACK CD_DATA CD_LRCK CD_BCK CD_C2PO SIO_SDA SIO_SCL TRST TDO TDI TMS TCK CD Interface ATAPI_RESET ATAPI_DATA[15:0] ATAPI_ADDR[4:0] ATAPI_DIOW ATAPI_DIOR ATAPI_INTRQ ATAPI_IORDY ATAPI_DMARQ ATAPI_DMAACK ATAPI Interface SIO_IRTX1 SIO_IRTX2 SIO_IRRX IR (Serial I/O) SIO_UART1_TX SIO_UART1_RX SIO_UART1_RTS SIO_UART1_CTS UART1 SIO_UART2_TX SIO_UART2_RX UART2 Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved. 7 Host Master Interface LSI Logic Confidential Figure 18.45 308-Pin BGA Package Mechanical Dimensions A1 D1 e Y W V U T R P N M L K J H G F E D C B A c e b E1 ddd q A A2 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20 Bottom View Pin A1 Indicators Dimensions in mm Top View E3 E2 E Min. 2.20 – 1.12 – 0.51 26.80 – 23.80 17.95 26.80 – 23.80 17.95 Nom. 2.33 0.60 1.17 0.75 0.56 27.00 24.13 24.00 18.00 27.00 24.13 24.00 18.00 Max. 2.50 – 1.22 – 0.61 27.20 – 24.20 18.05 27.20 – 24.20 18.05 Min. 0.087 – 0.044 – 0.020 1.055 – 0.937 0.707 1.055 – 0.937 0.707 Nom. 0.092 0.024 0.046 0.030 0.022 1.063 0.950 0.945 0.709 1.063 0.950 0.945 0.709 Max. 0.098 – 0.048 – 0.024 1.071 – 0.953 0.711 1.071 – 0.953 0.711 e ddd – – 1.27 – – 0.15 – – 0.050 – – 0.006 q D3 Dimensions in inches Symbol A A1 A2 b c D D1 D2 D3 E E1 E2 E3 30˚ Typ 30˚ Typ 1. The metric (millimeter) values are the controlling dimensions and should be used for PC board design. D2 2. Dimension b is measured at the maximum solder ball diameter. D 3. Minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. Important: This drawing may not be the latest version. Package Mechanical Specifications Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved. 8 16 Megabit Multi-Purpose Flash SST39VF160Q / SST39VF160 Advance Information FUNCTIONAL BLOCK DIAGRAM 16,777,216 bit EEPROM Cell Array X-Decoder A19 - A0 Address Buffer & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ15 - DQ0 VDDQ 329 ILL B1.2 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Standard Pinout Top View Die Up SST39VF160Q A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up SST39VF160 329 ILL F01.2 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 329 ILL F01a.0 FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP PACKAGES 1 2 3 4 5 6 1 2 3 4 5 6 A A3 A7 NC WE# A9 A13 A A3 A7 NC WE# A9 A13 B A4 A17 NC NC A8 A12 B A4 A17 NC NC A8 A12 C A2 A6 A18 NC A10 A14 C A2 A6 A18 NC A10 A14 D A1 A5 NC A19 A11 A15 D A1 A5 NC A19 A11 A15 E A0 DQ0 DQ2 DQ5 DQ7 A16 E A0 DQ0 DQ2 DQ5 DQ7 A16 F CE# DQ8 DQ10 DQ12 DQ14 VDDQ F CE# DQ8 DQ10 DQ12 DQ14 NC G OE# DQ9 DQ11 VDD DQ13 DQ15 G OE# DQ9 DQ11 VDD DQ13 DQ15 H VSS DQ1 DQ3 DQ6 H VSS DQ1 DQ3 DQ6 DQ4 SST39VF160Q VSS DQ4 SST39VF160 329 ILL F02.4 VSS 329 ILL F02a.0 FIGURE 2: PIN ASSIGNMENTS FOR 48-PIN TFBGA © 1998 Silicon Storage Technology, Inc. 329-09 11/98 9 ESMT M13S128168A ;( 45-45 45 45 5( 2 2 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm PIN PITCH) Publication Date : Nov. 2002 Revision : 0.2 Elite Semiconductor Memory Technology Inc. 10 SLLS423D – JUNE 2000 – REVISED SEPTEMBER 2002 description (continued) required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB1 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41AB1 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active. PHP package terminal diagram XI PLLGND PLLVDD FILTER1 FILTER0 RESET LREQ DGND DGND DVDD DVDD XO PHP PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 TSB41AB1 7 31 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 LPS DGND C/LKON PC0 PC1 PC2 ISO CPS DV DD TESTM SE SM SYSCLK CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PD 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 AGND AVDD R1 R0 AGND TPBIAS TPA+ TPA– TPB+ TPB– AGND AVDD ADV7302A/ADV7303A The ADV7302A/ADV7303A is a lead-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure tin electroplate. The device is suitable for lead-free applications and is able to withstand surface-mount soldering at up to 255°C (± 5°C). In addition, it is backward compatible with conventional tin-lead soldering processes. This means that the electroplated tin coating can be soldered with tin-lead solder pastes at conventional reflow temperatures of 220°C to 235°C. ABSOLUTE MAXIMUM RATINGS* VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V VDD_IO to IO_GND . . . . . . . . . . . . . –0.3 V to VDD_IO + 0.3 V Ambient Operating Temperature (TA) . . . . . . . 0°C to +70°C Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE THERMAL CHARACTERISTICS Model Package Description Package Option θJC = 11°C/W θJA = 47°C/W ADV7302AKST ADV7303AKST Plastic Quad Flatpack Plastic Quad Flatpack ST-64B ST-64B CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7302A/ADV7303A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. S_VSYNC S_HSYNC GND_IO GND_IO S0 S1 VDD S2 DGND S3 S4 S5 S6 S7 CLKN_B GND_IO PIN CONFIGURATION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IO 1 GND_IO 2 48 S_BLANK PIN 1 IDENTIFIER 47 RSET1 46 VREF GND_IO 3 Y0 4 45 COMP1 Y1 5 44 DAC A 43 DAC B Y2 6 Y3 7 ADV7302A/ADV7303A 42 DAC C Y4 8 TOP VIEW (Not to Scale) 41 VAA 40 AGND Y5 9 VDD 10 DGND 11 39 DAC D Y6 12 37 DAC F Y7 13 36 COMP2 GND_IO 14 35 RSET2 34 EXT_LF 38 DAC E GND_IO 15 33 RESET C0 16 CLKIN_A RTC_SCR_TR C7 C6 C5 C4 C3 P_VSYNC P_BLANK P_HSYNC SCLK SDA I2C ALSB C2 C1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Input/Output Function 1 VDD_IO P Power Supply for Digital Inputs and Outputs 4–9, 12, 13 Y0–Y7 I 8-Bit Progressive Scan/HDTV Input Port for Y Data. The LSBs are set up on Pins Y0 and Y1. In default mode, the input on this port is output on DAC D. 16–18, 26–30 C0–C7 I 8-Bit Progressive Scan/HDTV Input Port for CrCb Color Data in 4:2:2 Input Mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U) data. The LSBs are set up on Pins C0 and C1. In default mode, the input on this port is output on DAC E. 12 REV. A ADV7302A/ADV7303A Pin No. Mnemonic 2 Input/Output Function 19 IC I This input pin must be tied high (VDD_IO) for the ADV7302A/ADV7303A to interface over the I2C port. 20 ALSB I/O TTL Address Input. This signal sets up the LSB of the MPU address. When this pin is tied low, the I2C filter is activated, which reduces noise on the I2C interface. 21 SDA I/O MPU Port Serial Data Input/Output 22 SCLK I MPU Port Serial Interface Clock Input 23 P_HSYNC I Video Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD Mode and HD Only Mode 24 P_VSYNC I Video Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD Mode and HD Only Mode 25 P_BLANK I Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode and HD Only Mode 31 RTC_SCR_TR I Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input, and Subcarrier Reset Input 32 CLKIN_A I Pixel Clock Input for HD Only or SD Only Modes 33 RESET I This input resets the on-chip timing generator and sets the ADV7302A/ ADV7303A into default register setting. Reset is an active low signal. 34 EXT_LF I External Loop Filter for the internal PLL 35, 47 RSET2, 1 I A 760 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes of the DAC outputs. 36, 45 COMP2, 1 O Compensation Pin for DACs. Connect 0.1 µF Capacitor from COMP Pin to VAA. 37 DAC F O In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and Simultaneous HD/SD: Pr/Red (HD) Analog Output 38 DAC E O In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and Simultaneous HD/SD: Pb/Blue (HD) Analog Output 39 DAC D O In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and Simultaneous HD/SD: Y/Green (HD) Analog Output 40 AGND G Analog Ground 41 VAA P Analog Power Supply 42 DAC C O Chroma/Red/V SD Analog Output 43 DAC B O Luma/Blue/U SD Analog Output 44 DAC A O CVBS/Green/Y SD Analog Output 46 VREF I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V) 48 S_BLANK I/O Video Blanking Control Signal for SD 49 S_VSYNC I/O Video Vertical Control Signal for SD. Option to output SD VSYNC or SD HSYNC in SD Slave Mode 0 and/or any HD Mode. 50 S_HSYNC I/O Video Horizontal Control Signal for SD. Option to output SD HSYNC or HD HSYNC in SD Slave Mode 0 and/or any HD Mode. 53–55, 58–62 S0–S7 I 8-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port for Cr (Red/V) color data in 4:4:4 Input Mode. The LSBs are set up on Pins S0 and S1. In Default Mode, the input on this port is output on DAC F. 10, 56 VDD P Digital Power Supply 11, 57 DGND G Digital Ground 63 CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV Mode. This clock input pin is only used in Simultaneous SD/HD Mode. 2, 3, 14, 15, 51, 52, 64 GND_IO REV. A Digital Ground 13 14 15 16 17 IS24C08-2, IS24C08-3 FUNCTIONAL BLOCK DIAGRAM 8 SDA 5 SCL 6 WP 7 HIGH VOLTAGE GENERATOR, TIMING & CONTROL CONTROL LOGIC X DECODER Vcc SLAVE ADDRESS REGISTER & COMPARATOR EEPROM ARRAY WORD ADDRESS COUNTER GND Y DECODER ACK 4 Clock DI/O > nMOS DATA REGISTER PIN CONFIGURATION PIN DESCRIPTIONS 8-Pin DIP and SOIC A0-A2 Address Inputs SDA Serial Address/Data I/O SCL Serial Clock Input A0 1 8 VCC WP Write Protect Input A1 2 7 WP Vcc Power Supply A2 3 8 SCL GND Ground GND 4 5 SDA SCL This input clock pin is used to synchronize the data transfer to and from the device. The IS24C08-2 and IS24C08-3 only use A2 input for hardwire addressing and a total of two devices may be addressed on a single bus system. The A0 and A1 pins are not used by IS24C08-2 and IS24C08-3. They may be left floating or tied to either GND or Vcc. SDA The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc. WP WP is the Write Protect pin. If the WP pin is tied to Vcc the upper half array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device. A0, A1, A2 The A0, A1 and A2 are the device address inputs. These pins are not used by IS24C16-2 and IS24C16-3. A0 and A1 may be left floating or tied to either GND or Vcc. A2 should be tied to either GND or Vcc. 18 Philips Semiconductors Product specification Hex inverting Schmitt trigger 74HC/HCT14 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 3, 5, 9, 11, 13 1A to 6A data inputs 2, 4, 6, 8, 10, 12 1Y to 6Y data outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUT OUTPUT nA nY L H H L Notes 1. H = HIGH voltage level L = LOW voltage level APPLICATIONS • Wave and pulse shapers • Astable multivibrators • Monostable multivibrators Fig.4 Functional diagram. Fig.5 Logic diagram (one Schmitt trigger). 19 Philips Semiconductors Product specification 2.5V/3.3V 16-bit transparent D-type latch (3-State) LOGIC SYMBOL 47 LOGIC SYMBOL (IEEE/IEC) 46 44 43 41 40 38 37 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1LE 1 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2 3 36 35 5 33 6 32 8 30 9 29 11 27 12 2LE 24 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 13 14 16 17 19 20 22 23 SA00044 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 1D0 – 1D7 2D0 – 2D7 Data inputs 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 1Q0 – 1Q7 2Q0 – 2Q7 Data outputs 1, 24 48, 25 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 1OE, 2OE 1LE, 2LE GND VCC 1OE 1 1EN 1LE 48 C3 2OE 24 2EN 2LE 25 C4 1D1 47 3D 2 1Q1 1D2 46 3 1Q2 1D3 44 5 1Q3 1D4 43 6 1Q4 1D5 41 8 1Q5 1D6 40 9 1Q6 1D7 38 11 1Q7 1D8 37 12 1Q8 2D1 36 13 2Q1 2D2 35 14 2Q2 2D3 33 16 2Q3 2D4 32 17 2Q4 2D5 30 19 2Q5 2D6 29 20 2Q6 2D7 27 22 2Q7 2D8 26 23 2Q8 26 2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 25 74ALVT16373 4D 1∇ 2∇ SW00010 PIN CONFIGURATION Output enable inputs (active-Low) Enable inputs (active-High) Ground (0V) Positive supply voltage 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE SA00043 20 2-Input 1-Output Video Switch (75Ω driver)/3-Input 1-Output Video Switch (75Ω driver) MM1221~1228 MITSUMI 2-Input 1-Output Video Switch (75Ω driver)/3-Input 1-Output Video Switch (75Ω driver) Monolithic IC MM1221~MM1228 Outline These ICs are high grade video switches with 2-input 1-output or 3-input 1-output and built-in 75Ω driver. The series includes those with and without built-in clamp and 6dB amp circuits. Circuit configuration tables and block diagrams are as follows. MM1228 is used as the representative model in this description. MM1221~MM1228 Series Circuit Configuration Table Model name # of Inputs # of Outputs 6dB amp circuit Clamp circuit Power supply voltage range MM1221 2 1 No No 8~13V MM1222 2 1 Yes No 8~13V MM1223 3 1 No No 8~13V MM1224 3 1 Yes No 8~13V MM1225 2 1 No Yes 4.7~13V MM1226 2 1 Yes Yes 4.7~13V MM1227 3 1 No Yes 4.7~13V MM1228 3 1 Yes Yes 4.7~13V MM1221~MM1228 Input/Output Voltage Measurement Values (typ.) Model name MM1221 MM1222 MM1223 MM1224 MM1225 MM1226 MM1227 MM1228 Power supply 9V 12V Unit Input voltage 4.53 6.05 V Output voltage 4.5 6.1 V Input voltage 4.05 5.4 V Output voltage 5.34 7.12 V Input voltage 4.53 6.05 V Output voltage 4.5 6.1 V Input voltage 4.05 5.4 V Output voltage 5.34 7.12 V voltage 5V Input voltage 1.27 2.17 2.86 V Output voltage 1.31 2.25 2.96 V Input voltage 1.3 2.2 2.9 V Output voltage 1.4 2.23 2.88 V Input voltage 1.27 2.17 2.86 V Output voltage 1.31 2.25 2.96 V Input voltage 1.3 2.2 2.9 V Output voltage 1.4 2.23 2.88 V 21 2-Input 1-Output Video Switch (75Ω driver)/3-Input 1-Output Video Switch (75Ω driver) MM1221~1228 MITSUMI Block Diagram (MM1221~MM1228) Control input truth table SW L H Control input truth table SW L H OUT IN1 IN2 Control input truth table SW1 L H L/H SW2 L L H OUT IN1 IN2 Control input truth table OUT IN1 IN2 IN3 SW1 L H L/H 22 SW2 L L H OUT IN1 IN2 IN3 LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS. n n n n n n n n Patents Pending Low output voltage offset Works with +5v, +3.3v and 2.5v rails Source and sink current Low external component count No external resistors required Linear topology Available in SO-8, PSOP-8 or LLP-16 packages Low cost and easy to use Applications n DDR Termination Voltage n SSTL-2 n SSTL-3 Typical Application Circuit 20039302 © 2003 National Semiconductor Corporation DS200393 www.national.com 23 LP2995 DDR Termination Regulator July 2003 24 MSP 34x5G PRELIMINARY DATA SHEET NC VREF1 DACM_L SC1_OUT_R DACM_R SC1_OUT_L VREF2 NC NC AHVSUP NC 33 32 31 30 29 28 27 26 25 24 23 CAPL_M 34 22 RESETQ AHVSS 35 21 I2S_DA_IN2 AGNDC 36 20 DVSS SC2_IN_L 37 19 DVSUP SC2_IN_R 38 18 ADR_CL ASG 39 17 I2S_DA_IN1 SC1_IN_L 40 16 I2S_DA_OUT SC1_IN_R 41 15 I2S_WS VREFTOP 42 14 I2S_CL MONO_IN 43 13 I2C_DA AVSS 44 12 I2C_CL MSP 34x5G 1 2 3 4 5 6 7 8 9 10 11 AVSUP STANDBYQ ANA_IN1+ ADR_SEL ANA_IN− D_CTR_I/O0 TESTEN D_CTR_I/O1 XTAL_IN TP XTAL_OUT Fig. 4–10: 44-pin PMQFP package 25 11.Terminal for External Connection & Outline Drawing 26 SCHEMATIC DIAGRAM&PCB SILKSCREEN D C B A AI_D0 12 AO_D0 12 AO_D1 12 AO_D2 12 AO_D3 12 AO_SCLK 12 AO_FSYNC 6 AO_IEC958 12 AO_MCLKO 12 12 AI_SCLK 12 AI_FSYNC 12 AI_MCLKO 6,7 /SYS_RST 10 VI_D[9..2] 10 VI_VSYNC0 10 VI_CLK0 11 VO_D0 11 VO_D1 11 VO_D2 11 VO_D3 11 VO_D4 11 VO_D5 11 VO_D6 11 VO_D7 11 VO_D8 11 VO_D9 11 VO_D10 11 VO_D11 11 VO_D12 11 VO_D13 11 VO_D14 11 VO_D15 11 VO_CLK RP1 1 2 3 4 22 DNS-22 DNS-22 DNS-22 22 22 22 22 5 CLKI CLKX U1 NC NC NC NC NC NC NC NC NC NC C6 103 C45 103 C7 103 C8 103 C47 104 C9 104 C11 104 C12 104 GND_SSTL2 C50 103 C13 104 DMN8600 C14 104 U19 W20 + E5_VPAD C15 47u/16 E5_VDDX E5_AVDD E5_VDLL E5_V5BIAS SSTL2_VDD E5_VCORE C24 103 C41 103 C25 103 V33 C40 103 3 C42 103 C26 103 C43 103 C27 103 C44 103 C28 103 Y20 2 U13 + C33 47u/16 C18 104 C34 104 C19 104 C35 104 C20 104 C36 104 2 7,10,11,12,13 7,10,11,12,13 /E5_CS1 6 /E5_CS0 7 C22 104 C38 104 V33 C23 104 E5_VCORE C39 104 V33 C4 104 5V VCC BBK IR_IN + 13 (/ETHER_IRQ) (MUTE) (/RST) Tuesday, August 12, 2003 Document Number L1 B601 (DEM/GPO) C2 47u/16 Size C Title Date: DMN8600 3.3V V25 2.5V V18 1.8V *0 D1 *1N6263 2 R6 /E5_CS2 MCONFIG1 /E5_OE 6,7 /E5_WEH (E5_GPIO1) E5_GPIO1 13(E5_GPIO2) E5_GPIO2 6 (E5_GPIO3) E5_GPIO3 12(E5_GPIO0) E5_GPIO0 13(E5_GPIO4) E5_GPIO4 7,8,10,11 /E5_WEL 6,7 (E5_GPIO5) E5_GPIO5 13(/WAIT) /WAIT 6 /DTACK 1 R2 *10K E5_SPI_CLK 13 E5_SPI_MISO 13 E5_SPI_MOSI 13 E5_UART1_RTS 6 E5_VDDX E5_UART1_CTS 6 E5_UART1_TX 6 E5_UART1_RX 6 SDA SCL C21 104 C37 104 E5_VPAD ATAPI_RESET 7 ATAPI_DMAACK_L 7 ATAPI_DMARQ 7 ATAPI_IORDY 7 ATAPI_INTRQ 7 ATAPI_DIOR_L 7 ATAPI_DIOW_L 7 AtapiAddr0 7 AtapiAddr1 7 AtapiAddr2 7 AtapiAddr3 7 AtapiAddr4 7 ATAPI_DATA15 7 ATAPI_DATA14 7 ATAPI_DATA13 7 ATAPI_DATA12 7 ATAPI_DATA11 7 ATAPI_DATA10 7 ATAPI_DATA9 7 ATAPI_DATA8 7 ATAPI_DATA7 7 ATAPI_DATA6 7 ATAPI_DATA5 7 ATAPI_DATA4 7 ATAPI_DATA3 7 ATAPI_DATA2 7 ATAPI_DATA1 7 ATAPI_DATA0 7 HD15 HD14 HD13 HD12 HD11 HD10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 6,7 HD[15..0] R25 22 MCONFIG0 E5_MA22 7 E5_MA5 6,7 E5_MA4 6,7 E5_MA3 6,7 E5_MA2 6,7 E5_MA1 6,7 E5_MA26 E5_MA25 E5_MA24 E5_MA23 /E5_CS5 /E5_CS4 /E5_CS3 E5_ALE 6,7 E5 signals named after master host's E5_UART2_TX E5_UART2_RX ALE Y16 Y15 V15 Y13 W10 W9 U7 Y10 U8 Y9 V9 U9 W4 Y3 V5 W5 Y4 V6 Y5 Y6 U6 W6 V7 W7 Y8 Y7 V8 W8 Y11 U10 V11 V10 Y12 V12 W11 U11 V13 W12 U12 Y14 V14 W13 W14 W15 M16 Y1 U1 W1 T3 W2 V3 T1 W3 V2 V1 U3 V4 Y2 U2 T2 R2 R1 P2 N3 M4 N1 N2 N4 P1 P3 P4 R3 R4 General decoupling cap placement: ATAPI_RESET ATAPI_DMAACK_L ATAPI_DMARQ ATAPI_IORDY ATAPI_INTRQ ATAPI_DIOR_L ATAPI_DIOW_L AtapiAddr0 AtapiAddr1 AtapiAddr2 AtapiAddr3 AtapiAddr4 ATAPI_DATA15 ATAPI_DATA14 ATAPI_DATA13 ATAPI_DATA12 ATAPI_DATA11 ATAPI_DATA10 ATAPI_DATA9 ATAPI_DATA8 ATAPI_DATA7 ATAPI_DATA6 ATAPI_DATA5 ATAPI_DATA4 ATAPI_DATA3 ATAPI_DATA2 ATAPI_DATA1 ATAPI_DATA0 MCONFIG0 PCI_GNT_L PCI_REQ_L PCI_INTA_L PCI_CBE_L0 PCI_CBE_L1 PCI_CBE_L2 PCI_CBE_L3 PCI_PAR PCI_FRAME_L PCI_IRDY_L PCI_TRDY_L PCI_STOP_L PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 Y18 V19 Caps with smaller capacitance values to be closer to respective power pins compared to those of larger values. All should be as close as possible. C16 47u/16 + C32 47u/16 + SIO_SDA SIO_SCL SIO_IRRX 3 SIO_UART2_TX SIO_UART2_RX 4 C49 104 E5_VDDX C10 104 SSTL2_VDD E5_AVDD C48 103 V20 V17 U20 W19 3 E5_SDRAM_DQ[31..0] E5_VDDREF C46 104 4 OE#/SIO_IRTX2 MAddress2/SIO_IRTX1 4,5 E5_SDRAM_A[15..0] VI_D2 VI_D3 VI_D4 VI_D5 VI_D6 VI_D7 VI_D8 VI_D9 VI_VSYNC0 VI_CLK0 TCK TDI TDO TMS TRST_L D14 AO_D0 AO_0 C14 AO_D1 AO_1 B15 AO_D2 AO_2 A15 AO_D3 AO_3 A14 AO_SCLK AOSCLK D13 AO_FSYNC AOFSYNC B14 AO_IEC958 AOIEC B13 AO_MCLKO AOMCLKO C13 AI_D0 D12 AI_D1 AI_D1 B12 AI_SCLK AISCLK C12 AI_FSYNC AIFSYNC A13 AI_MCLKO AIMCLKO A10 CLKI CLKI B10 CLKX CLKX A12 CLKO A7 BYPASS_PLL W16 PCI_RST_L D8 C7 B7 B6 D7 B2 C3 C2 D3 C4 B3 A2 A1 C1 A5 A3 B1 A4 D6 C5 B4 B5 C6 D2 A6 C30 104 E5_V5BIAS VDD_REF R_REF VSS_REF AGND0 AGND1 AGND2 AGND3 GNDX J4 VO_D0 VO_0 H2 VO_D1 VO_1 H3 VO_D2 VO_2 H4 VO_D3 VO_3 G1 VO_D4 VO_4 G2 VO_D5 VO_5 G3 VO_D6 VO_6 F1 VO_D7 VO_7 F2 VO_D8 VO_8 G4 VO_D9 VO_9 E1 VO_D10 VO_10 F3 VO_D11 VO_11 E2 VO_D12 VO_12 D1 VO_D13 VO_13 E3 VO_D14 VO_14 F4 VO_D15 VO_15 H1 VO_CLK A9 C9 A8 C8 C10 D11 C11 B11 C29 103 E5_AGND MAddress26/SIO_SPI_CLK MAddress5/SIO_SPI_CS3 MAddress22/SIO_SPI_CS2 MAddress23/SIO_SPI_CS1 MAddress24/SIO_SPI_CS0 MAddress1/SIO_SPI_MISO MAddress25/SIO_SPI_MOSI 5 R11 R12 R13 R14 R15 R16 R17 R18 22 22 22 22 4,5 E5_SDRAM_CAS# 4,5 E5_SDRAM_RAS# 4,5 E5_SDRAM_CLKE 4,5 E5_SDRAM_WE# 4,5 E5_SDRAM_CLK0 4,5 E5_SDRAM_CLK#0 4,5 E5_SDRAM_CLK1 4,5 E5_SDRAM_CLK#1 3,4,5 VREF R19 R20 R21 R22 22 100 104 1.18K/1% R27 22 22/RP 8 7 6 5 22/RP 8 7 6 5 VI_D2 VI_D3 VI_D4 VI_D5 VI_D6 VI_D7 VI_D8 VI_D9 R23 R24 C1 6 E5_TCK 6 E5_TDI 6 E5_TDO 6 E5_TMS 6 E5_TRST 22/RP 8 7 6 5 RP2 1 2 3 22/RP 4 8 7 6 5 RP4 1 2 3 4 R26 GND Y1 13.5MHz BIO_PHY_DATA7 BIO_PHY_DATA6 BIO_PHY_DATA5 BIO_PHY_DATA4 BIO_PHY_DATA3 BIO_PHY_DATA2 BIO_PHY_DATA1 BIO_PHY_DATA0 8 BIO_PHY_CTL1 8 BIO_PHY_CTL0 8 BIO_LREQ 8 BIO_LPS 8 BIO_LINK_ON 8 BIO_PHY_CLK E5_VDDREF 8 8 8 8 8 8 8 8 27PF 27PF GND_SSTL2 RP3 1 2 3 4 C5 C31 E5_DLLGND 1 1 + /E5_CS1 /E5_CS0 R7 R5 R4 R3 10K 1K 10K 10K 10K 10K V33 /E5_CS2 R8 R1 10K MCONFIG1 E5_GPIO2 R9 TP1 E5_GPIO3 TP2 E5_GPIO4 1 TP3 10K 1 R10 E5_GPIO5 1 /WAIT E5_UART2_TX 2 E5_V5BIAS 13 of Rev 0.0 E5_VDDREF E5_VDDX E5_AVDD SSTL2_VDD E5_VCORE E5_UART2_RX C3 47u/16 Sheet D C B A 27 A18 C20 E18 E17 F17 C19 D19 D18 B20 C18 A20 B18 C17 A17 B19 A19 3 3 SDRAM_DQM0 SDRAM_DQS0 SDRAM_DQ7 SDRAM_DQ6 SDRAM_DQ5 SDRAM_DQ4 SDRAM_DQ3 SDRAM_DQ2 SDRAM_DQ1 SDRAM_DQ0 VSS_PC2_CTR1 VSS_PC2_CTR2 VSS_PC2_CTR3 VSS_PC2_CTR4 VSS_PC2_CTR5 VSS_PC2_CTR6 VSS_PC2_CTR7 VSS_PC2_CTR8 VSS_PC2_CTR9 VSS_PC2_CTR10 VSS_PC2_CTR11 VSS_PC2_CTR12 VSS_PC2_CTR13 VSS_PC2_CTR14 VSS_PC2_CTR15 VSS_PC2_CTR16 VSS_PC2_CTR17 VSS_PC2_CTR18 VSS_PC2_CTR19 VSS_PC2_CTR20 VSS_PC2_CTR21 VSS_PC2_CTR22 VSS_PC2_CTR23 VSS_PC2_CTR24 VSS_PC2_CTR25 VSS_PC2_CTR26 VSS_PC2_CTR27 VSS_PC2_CTR28 VSS_PC2_CTR29 VSS_PC2_CTR30 VSS_PC2_CTR31 VSS_PC2_CTR32 VSS_PC2_CTR33 VSS_PC2_CTR34 VSS_PC2_CTR35 VSS_PC2_CTR36 GND_DLL0 GND_DLL1 SDRAM__A15 SDRAM__A14 SDRAM__A13 SDRAM__A12 SDRAM__A11 SDRAM__A10 SDRAM__A9 SDRAM__A8 SDRAM__A7 SDRAM__A6 SDRAM__A5 SDRAM__A4 SDRAM__A3 SDRAM__A2 SDRAM__A1 SDRAM__A0 3 3 H8 H9 H10 H11 H12 H13 J8 J9 J10 J11 J12 J13 K8 K9 K10 K11 K12 K13 L8 L9 L10 L11 L12 L13 M8 M9 M10 M11 M12 M13 N8 N9 N10 N11 N12 N13 U17 T17 SDRAM_DQM1 SDRAM_DQS1 SDRAM_DQ15 SDRAM_DQ14 SDRAM_DQ13 SDRAM_DQ12 SDRAM_DQ11 SDRAM_DQ10 SDRAM_DQ9 SDRAM_DQ8 AVDD0 AVDD1 AVDD2 AVDD3 VDDX A16 C15 B16 B17 3 3 SDRAM_DQM2 SDRAM_DQS2 SDRAM_DQ23 SDRAM_DQ22 SDRAM_DQ21 SDRAM_DQ20 SDRAM_DQ19 SDRAM_DQ18 SDRAM_DQ17 SDRAM_DQ16 D10 B9 D9 B8 A11 SDRAM_WE_L SDRAM_CKE SDRAM_RAS_L SDRAM_CAS_L 5V_BIAS1 MAddress3/SIO_UART1_RTS WR#/SIO_UART1_CTS MAddress4/SIO_UART1_TX CS0#/SIO_UART1_RX 3 3 SDRAM_DQM3 SDRAM_DQS3 SDRAM_DQ31 SDRAM_DQ30 SDRAM_DQ29 SDRAM_DQ28 SDRAM_DQ27 SDRAM_DQ26 SDRAM_DQ25 SDRAM_DQ24 G19 E20 F20 F19 H17 G18 G17 F18 E5_SDRAM_DQ31 E19 E5_SDRAM_DQ30 D20 E5_SDRAM_DQ29 E5_SDRAM_DQ28 E5_SDRAM_DQM2 K20 E5_SDRAM_DQ27 E5_SDRAM_DQS2 J19 E5_SDRAM_DQ26 H19 E5_SDRAM_DQ25 H18 E5_SDRAM_DQ24 J17 J18 J20 K17 E5_SDRAM_DQ23 K18 E5_SDRAM_DQ22 K19 E5_SDRAM_DQ21 E5_SDRAM_DQ20 E5_SDRAM_DQM1 L17 E5_SDRAM_DQ19 E5_SDRAM_DQS1 M19 E5_SDRAM_DQ18 N18 E5_SDRAM_DQ17 M18 E5_SDRAM_DQ16 L20 M17 L19 M20 E5_SDRAM_DQ15 N19 E5_SDRAM_DQ14 L18 E5_SDRAM_DQ13 E5_SDRAM_DQ12 E5_SDRAM_DQM0 N17 E5_SDRAM_DQ11 E5_SDRAM_DQS0 R19 E5_SDRAM_DQ10 P19 E5_SDRAM_DQ9 P18 E5_SDRAM_DQ8 R20 P17 T20 R18 E5_SDRAM_DQ7 T19 E5_SDRAM_DQ6 R17 E5_SDRAM_DQ5 E5_SDRAM_DQ4 E5_SDRAM_DQ3 E5_IRTX2 W17 E5_SDRAM_DQ2 E5_IRTX1 U14 E5_SDRAM_DQ1 E5_SDRAM_DQ0 Y17 W18 V16 V18 Y19 T18 U18 U16 VDD_DLL0 U15 VDD_DLL1 N20 P20 U5 SDRAM_CLK_L0 SDRAM_CLK0 E5_SDRAM_A15 E5_SDRAM_A14 E5_SDRAM_A13 E5_SDRAM_A12 E5_SDRAM_A11 E5_SDRAM_A10 E5_SDRAM_A9 E5_SDRAM_A8 E5_SDRAM_A7 E5_SDRAM_A6 E5_SDRAM_A5 E5_SDRAM_A4 E5_SDRAM_A3 E5_SDRAM_DQM3 E5_SDRAM_A2 E5_SDRAM_DQS3 E5_SDRAM_A1 E5_SDRAM_A0 H20 G20 VDD_PAD0 VDD_PAD1 VDD_PAD2 VDD_PAD3 VDD_PAD4 VDD_PAD5 VDD_PAD6 VDD_PAD7 VDD_PAD8 VDD_CORE0 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_25V0 VDD_25V1 VDD_25V2 VDD_25V3 VDD_25V4 VDD_25V5 D16 E4 K5 L5 T4 T12 T11 E11 E9 D5 D4 J5 M5 U4 T9 T10 E12 E10 J16 K16 L16 C16 D17 D15 SDRAM_VREF BIO_PHY_DATA7 BIO_PHY_DATA6 BIO_PHY_DATA5 BIO_PHY_DATA4 BIO_PHY_DATA3 BIO_PHY_DATA2 BIO_PHY_DATA1 BIO_PHY_DATA0 BIO_PHY_CTL1 BIO_PHY_CTL0 BIO_LREQ BIO_LPS BIO_LINK_ON BIO_PHY_CLK SDRAM_CLK_L1 SDRAM_CLK1 K3 K2 K1 J1 M2 M3 L3 J2 L2 J3 M1 L4 K4 L1 D C B A 5 5 E5_SDRAM_DQ[31..0] 2 E5_SDRAM_DQ28 E5_SDRAM_DQ26 E5_SDRAM_DQ27 E5_SDRAM_DQ24 1 2 3 4 1 2 3 4 1 2 3 4 E5_SDRAM_DQ23 E5_SDRAM_DQ21 E5_SDRAM_DQ22 E5_SDRAM_DQ29 1 2 3 4 E5_SDRAM_DQM1 2 E5_SDRAM_DQ8 E5_SDRAM_DQ18 E5_SDRAM_DQM2 2 E5_SDRAM_DQM0 2 E5_SDRAM_DQ15 E5_SDRAM_DQ9 E5_SDRAM_DQ10 1 2 3 4 8 7 6 5 E5_SDRAM_DQ4 E5_SDRAM_DQ6 E5_SDRAM_DQ5 E5_SDRAM_DQ7 E5_SDRAM_DQ0 E5_SDRAM_DQ1 E5_SDRAM_DQ2 E5_SDRAM_DQ3 4 RP7 RP6 56/RP 8 7 6 5 56/RP 8 7 6 5 4,5 SDRAM_DQM0 SDRAM_DQ15 SDRAM_DQ9 SDRAM_DQ10 SDRAM_DQ23 SDRAM_DQ21 SDRAM_DQ22 SDRAM_DQ29 4,5 SDRAM_DQM1 SDRAM_DQ8 SDRAM_DQ18 4,5 SDRAM_DQM2 RP5 RP8 56/RP 8 7 6 5 SDRAM_DQ4 SDRAM_DQ6 SDRAM_DQ5 SDRAM_DQ7 SDRAM_DQ28 SDRAM_DQ26 SDRAM_DQ27 SDRAM_DQ24 RP9 56/RP 8 7 6 5 SDRAM_DQ0 SDRAM_DQ1 SDRAM_DQ2 SDRAM_DQ3 56/RP 8 7 6 5 RP10 56/RP 1 2 3 4 SDRAM_DQ16 SDRAM_DQ19 SDRAM_DQ17 SDRAM_DQ20 SDRAM_DQ12 SDRAM_DQ14 SDRAM_DQ13 SDRAM_DQ11 RP12 56/RP 1 2 3 4 4,5 SDRAM_DQM3 SDRAM_DQ31 SDRAM_DQ30 SDRAM_DQ25 RP11 56/RP 1 2 3 4 8 7 6 5 RP13 56/RP 1 2 3 4 8 7 6 5 E5_SDRAM_DQ16 E5_SDRAM_DQ19 E5_SDRAM_DQ17 E5_SDRAM_DQ20 8 7 6 5 E5_SDRAM_DQ12 E5_SDRAM_DQ14 E5_SDRAM_DQ13 E5_SDRAM_DQ11 E5_SDRAM_DQM3 2 E5_SDRAM_DQ31 E5_SDRAM_DQ30 E5_SDRAM_DQ25 The VTT side of the terminaton resistors should be placed on a wide VTT island on the surface layer. The island is located at each end of the bus, so it does not interfere with the signal routing. 4 4,5 SDRAM_DQ[31..0] 3 E5_SDRAM_DQS0 2 R30 R29 R28 51 51 51 51 4,5 SDRAM_DQS3 4,5 SDRAM_DQS2 4,5 SDRAM_DQS1 4,5 SDRAM_DQS0 2 E5_SDRAM_DQS1 2 R31 C52 C53 C54 104 C55 104 C56 104 C58 SSTL2_VDD E5_SDRAM_DQS2 2 SSTL2_VDD C51 103 C57 103 C66 103 103 VTT E5_SDRAM_DQS3 2 VTT C65 C72 104 C71 47u/16 C68 47u/16 C73 104 VREF Tuesday, August 12, 2003 Document Number 2,4,5 Size C TERM AT E5 Date: Title BBK V25_D C69 104 GND_SSTL2 104 + C64 C67 220u/10 C63 + C62 C70 220u/10 GND_SSTL2 VTT + SSTL2_VDD C61 8 7 6 5 C60 2 VTT PVIN AVIN VDDQ C59 GND_SSTL2 LP2995 NC GND VSENSE VREF 104 104 U2 104 1 2 3 4 + 104 C75 103 103 103 C74 104 104 104 VREF needs to be decoupled to both SSTL2_VDD and SSTL2_GND with balanced decoupling capacitors. 2,4,5 VREF VREF should be routed over a reference plane and isolated, and possibly shielded with both SSTL2_VDD and SSTL2_GND 3 1 1 Sheet 3 of 13 Rev 0.0 D C B A 28 D C B A 5 8 7 6 5 8 7 6 5 1 2 3 4 1 2 3 4 RP20 56/RP 1 2 3 4 RP18 56/RP 1 2 3 4 RP16 56/RP 8 7 6 5 RP14 56/RP 8 7 6 5 SDRAM_DQ16 SDRAM_DQ19 SDRAM_DQ20 SDRAM_DQ21 SDRAM_DQ15 SDRAM_DQ14 SDRAM_DQ13 SDRAM_DQ12 SDRAM_DQ11 SDRAM_DQ10 SDRAM_DQ9 SDRAM_DQ8 SDRAM_DQ4 SDRAM_DQ5 SDRAM_DQ6 SDRAM_DQ7 RP24 1 2 3 4 56/RP 8 7 6 5 RP23 56/RP 8 7 6 5 SDRAM_DQ24 SDRAM_DQ25 SDRAM_DQ26 SDRAM_DQ27 SDRAM_DQ22 SDRAM_DQ23 SDRAM_DQ18 3,5 SDRAM_DQM2 3,5 SDRAM_DQM3 3,5 SDRAM_DQM1 3,5 SDRAM_DQM0 3,5 SDRAM_DQS3 3,5 SDRAM_DQS2 3,5 SDRAM_DQS1 3,5 SDRAM_DQS0 SDRAM_DQ17 SDRAM_DQ28 SDRAM_DQ29 SDRAM_DQ30 SDRAM_DQ31 56 56 56 51 51 51 51 56 56/RP 8 7 6 5 R46 R45 R44 R43 R42 R41 R40 R205 RP25 1 2 3 4 1 2 3 4 RP22 1 2 3 4 56/RP 8 7 6 5 SDRAM_DQ0 SDRAM_DQ1 SDRAM_DQ2 SDRAM_DQ3 VREF needs to be decoupled to both SSTL2_VDD and GND_SSTL2 with balanced decoupling capacitors. VTT VTT 5 3,5 SDRAM_DQ[31..0] 4 4 C80 104 C76 104 C81 104 C77 103 C82 103 C78 103 C83 103 C79 SSTL2_VDD 104 C92 104 C84 104 C93 104 C85 103 C94 103 C86 103 C95 103 C87 104 C96 104 C88 104 C97 104 C89 SSTL2_VDD 104 3 VREF 2,3,5 GND_SSTL2 + C90 47u/16 + C91 47u/16 VTT GND_SSTL2 The VTT side of the terminaton resistors should be placed on a wide VTT island on the surface layer. The island is located at each end of the bus, so it does not interfere with the signal routing. 3 2 2 VTT RP15 1 2 3 4 56/RP 8 7 6 5 E5_SDRAM_A4 E5_SDRAM_A5 E5_SDRAM_A6 E5_SDRAM_A7 E5_SDRAM_A0 E5_SDRAM_A1 E5_SDRAM_A2 E5_SDRAM_A3 E5_SDRAM_A14 E5_SDRAM_A11 E5_SDRAM_A9 E5_SDRAM_A8 56/RP 8 7 6 5 RP19 56/RP 1 2 3 4 RP17 1 2 3 4 8 7 6 5 E5_SDRAM_A15 E5_SDRAM_A12 E5_SDRAM_A13 E5_SDRAM_A10 2,5 E5_SDRAM_CLKE 2,5 E5_SDRAM_CAS# 2,5 E5_SDRAM_RAS# 2,5 E5_SDRAM_WE# 2,5 E5_SDRAM_CLK1 2,5 E5_SDRAM_CLK0 2,5 E5_SDRAM_CLK#1 2,5 E5_SDRAM_CLK#0 RP21 56/RP 1 2 3 4 51 51 51 51 51 51 51 51 8 7 6 5 R32 R33 R34 R35 R36 R37 R38 R39 BBK Tuesday, August 12, 2003 Document Number Title Size C 1 1 Sheet 4 2,5 E5_SDRAM_A[15..0] TERM AT DDR & VREF/VTT Date: of 13 Rev 0.0 D C B A 29 2,4 E5_SDRAM_A[15..0] 5 E5_SDRAM_CLKE 2,4 E5_SDRAM_RAS# 2,4 E5_SDRAM_CAS# 2,4 E5_SDRAM_WE# 2,4 SDRAM_DQM0 3,4 SDRAM_DQM1 3,4 SDRAM_DQS0 3,4 SDRAM_DQS1 3,4 E5_SDRAM_A15 E5_SDRAM_A12 E5_SDRAM_A13 E5_SDRAM_A0 E5_SDRAM_A1 E5_SDRAM_A2 E5_SDRAM_A3 E5_SDRAM_A4 E5_SDRAM_A5 E5_SDRAM_A6 E5_SDRAM_A7 E5_SDRAM_A8 E5_SDRAM_A9 E5_SDRAM_A10 E5_SDRAM_A11 45 46 24 44 23 22 21 20 47 16 51 26 27 29 30 31 32 35 36 37 38 39 40 28 41 U3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 BA0 BA1 CS# CKE RAS# CAS# WE# LDM UDM LDQS UDQS CLK CLK# 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NC NC NC NC NC NC NC NC GND GND GND GNDQ GNDQ GNDQ GNDQ GNDQ R47 C103 55 104 C104 61 104 C105 1 104 C106 18 104 C107 103 C108 103 C109 103 C110 103 C111 GND_SSTL2 M1 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 19 25 42 43 50 53 15 104 34 48 66 6 12 52 58 64 C102 VREF 2,3,4 VREF VCC VCC VCC VCCQ VCCQ VCCQ VCCQ VCCQ 9 104 47u/16 C101 C98 8MX16 DDR 3 104 49 1 18 33 3 9 15 55 61 E5_SDRAM_CLK0 2,4 E5_SDRAM_CLK#0 2,4 SSTL2_VDD 33 C100 SSTL2_VDD 104 4 C112 47u/16 3,4 SDRAM_DQ[31..0] Option for 256Mb SDRAM_DQ0 SDRAM_DQ1 SDRAM_DQ2 SDRAM_DQ3 SDRAM_DQ4 SDRAM_DQ5 SDRAM_DQ6 SDRAM_DQ7 SDRAM_DQ8 SDRAM_DQ9 SDRAM_DQ10 SDRAM_DQ11 SDRAM_DQ12 SDRAM_DQ13 SDRAM_DQ14 SDRAM_DQ15 10K + 3 2,4 E5_SDRAM_A[15..0] 2 E5_SDRAM_A15 E5_SDRAM_A12 E5_SDRAM_A13 E5_SDRAM_A0 E5_SDRAM_A1 E5_SDRAM_A2 E5_SDRAM_A3 E5_SDRAM_A4 E5_SDRAM_A5 E5_SDRAM_A6 E5_SDRAM_A7 E5_SDRAM_A8 E5_SDRAM_A9 E5_SDRAM_A10 E5_SDRAM_A11 26 27 29 30 31 32 35 36 37 38 39 40 28 41 104 C120 103 C121 103 C122 103 C123 103 C124 49 1 18 33 3 9 15 55 61 24 44 23 22 21 20 47 16 51 C125 47u/16 45 46 C119 + E5_SDRAM_CLKE 2,4 E5_SDRAM_RAS# 2,4 E5_SDRAM_CAS# 2,4 E5_SDRAM_WE# 2,4 SDRAM_DQM2 3,4 SDRAM_DQM3 3,4 SDRAM_DQS2 3,4 SDRAM_DQS3 3,4 104 VREF C118 2 E5_SDRAM_CLK1 2,4 E5_SDRAM_CLK#1 2,4 SSTL2_VDD 104 SSTL2_VDD 3 U4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 BA0 BA1 CS# CKE RAS# CAS# WE# LDM UDM LDQS UDQS CLK CLK# VREF VCC VCC VCC VCCQ VCCQ VCCQ VCCQ VCCQ C99 8MX16 DDR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NC NC NC NC NC NC NC NC GND GND GND GNDQ GNDQ GNDQ GNDQ GNDQ 47u/16 M2 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 19 25 42 43 50 53 34 48 66 6 12 52 58 64 R48 GND_SSTL2 1 Sheet U22 M1 U25 M2 3,4 SDRAM_DQ[31..0] Document Number 1 SDRAM_CLK0 SDRAM_CLK1 SDRAM_A15 Option for 256Mb SDRAM_DQ16 SDRAM_DQ17 SDRAM_DQ18 SDRAM_DQ19 SDRAM_DQ20 SDRAM_DQ21 SDRAM_DQ22 SDRAM_DQ23 SDRAM_DQ24 SDRAM_DQ25 SDRAM_DQ26 SDRAM_DQ27 SDRAM_DQ28 SDRAM_DQ29 SDRAM_DQ30 SDRAM_DQ31 10K LAYOUT NOTE: E5 PLACEMENT BBK Tuesday, August 12, 2003 Title Size C 2 (8M BY 16) DDR SDRAM Date: 5 of 13 Rev 0.0 D C B A 40 30 D C B A 5 + + D 2,7 HD[15..0] C B A V33 5 /ETHER_IRQ V33 2 E5_UART1_TX 2 E5_UART1_RX 5 /SYS_RST 2,7 E5_MA3 2,7 4 10K R55 V33 R50 PDI 10K C126 22u/16 F_Y_IN F_CVBS_IN + /RST_HOST_LED /RST_SW D2 IN4148 VCC 13 /RST_HOST_LED R54 10K 2 AO_IEC958 13 F_CVBS_IN 2 E5_GPIO2 13 F_Y_IN 3 IN4148 D3 5 6 U7 1 D4 IN4148 9 MM1225XF In1 SW In2 NC R204 *0 U6C 74AHCT14 1 2 3 4 D5 IN4148 1 D6 2 R56 22K 2 1 10 PDO 3 U5 NC GND NC RES VDD 1 2 3 4 5 C127 104 R51 0 VCC VCC *V6300F Package: SOT-23 5L 4 U6B 74AHCT14 OPTICAL 13 SPDIF_OUT 13 Size B Tuesday, August 12, 2003 Document Number 1 1 Sheet FP, RST, IR, AV IO/ELink-3 CON, UART Date: Title BBK 2 U6A 74AHCT14 L2 IN4148 R59 R57 33 C128 F_Y_IN/F_CVBS_IN 120 0 R60 330 VCC 104 GND RESET CIRCUITRY 2 8 7 6 5 8 U6D 74AHCT14 Gnd Out VCC NC C129 104 2 *0 R49 of 13 2,7 /SYS_RST 6 Rev 0.0 31 J1 R53 10K 10K R52 E-Link III Connector E5_TMS E5_TDI E5_TDO E5_TCK E5_TRST R58 10K User can put a 6 pins 50mil header without putting the 50 pins header for JTAG debuging E5_UART1_CTS 2 E5_UART1_RTS 2 3 2 1 E5_MA5 2,7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 4 6 8 10 2 1 /E5_CS1 2 E5_TMS 2 /E5_WEL 2,7 E5_TDO 2 E5_MA2 2,7 E5_TDI 2 E5_MA4 2,7 E5_TRST 2 E5_TCK 2 /WAIT 2 HD15 HD8 E5_GPIO2 2 E5_ALE 2,7 HD11 HD7 HD12 HD14 HD13 HD10 /E5_OE 2,7 HD5 HD1 /RST_SW HD0 E5_MA1 2,7 HD2 HD9 HD3 HD4 HD6 CON50/SMT/TH/50 + + + + + UART SERIAL IO J2 + + + + + DNS CON5X2 1 3 5 7 9 4 2 1 D C B A 2 ATAPI_RESET R86 680 5 2 2 2 2 10 U6E 74AHCT14 U11 13 A0 VCC A1 WP A2 SCL GND SDA DNS AT24C16 1 2 3 4 V33 12 104 4 C136 R67 VCC 4.7K 4.7K R68 /RST_AUDIO 12,13 /RST_7115 2,8,10,11 /RST_7302 2,8,10,11 /RST_PHY 2,8,10,11 U6F 74AHCT14 10K R72 VCC RSTATA 2 ATAPI_INTRQ 2 ATAPI_IORDY 2 ATAPI_DMARQ ATA_A1 ATA_A0 ATA_A2 CS1FX CS3FX DIOW DIOR DMACK 2 2 2 2 SCL SDA 8 7 6 5 2,10,11,12,13 2,10,11,12,13 HD_AT4 HD_AT5 HD_AT6 HD_AT7 HD_AT0 HD_AT1 HD_AT2 HD_AT3 RP28 33/RP 1 2 3 4 HD_AT8 HD_AT9 HD_AT10 HD_AT11 RP27 33/RP 1 2 3 4 RP29 33/RP 4 3 2 1 HD_AT12 HD_AT13 HD_AT14 HD_AT15 8 7 6 5 5 6 7 8 RP30 33/RP 4 3 2 1 2 2 2 2 ATAPI_DATA8 2 ATAPI_DATA9 2 ATAPI_DATA10 2 ATAPI_DATA11 2 5 6 7 8 ATAPI_DATA12 ATAPI_DATA13 ATAPI_DATA14 ATAPI_DATA15 2 2 2 2 ATAPI_DATA4 ATAPI_DATA5 ATAPI_DATA6 ATAPI_DATA7 ATAPI_DATA0 ATAPI_DATA1 ATAPI_DATA2 ATAPI_DATA3 DEDICATED ATAPI INTERFACE 8 7 6 5 Select the source of /RST 11 0 82 82 82 33 33 33 33 RP31 33/RP 8 7 6 5 R98 R99 R100 R101 1 2 3 4 R81 R82 R83 R84 BOARD REGISTERS 2,8,10,11 E5_GPIO4 VCC R71 10K R87 INT_ATA IORDY DMARQ 4.7K C137 22PF AtapiAddr1 AtapiAddr0 AtapiAddr2 AtapiAddr3 AtapiAddr4 2 ATAPI_DIOW_L 2 ATAPI_DIOR_L 2 ATAPI_DMAACK_L 2 4 3 2,6 HD[15..0] 3 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 E5_ALE 2,6 C130 104 C131 104 C133 104 C135 104 E5_MA1 2,6 E5_MA2 2,6 E5_MA3 2,6 E5_MA4 2,6 E5_MA5 2,6 E5_MA22 2 V33 47 46 44 43 41 40 38 37 1 48 36 35 33 32 30 29 27 26 24 25 7 18 31 42 U9 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1OE 1LE 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2OE 2LE VCC VCC VCC VCC RSTATA HD_AT7 HD_AT6 HD_AT5 HD_AT4 HD_AT3 HD_AT2 HD_AT1 HD_AT0 DMARQ DIOW DIOR IORDY DMACK INT_ATA ATA_A1 ATA_A0 CS1FX BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA[22..1] 2 3 5 6 8 9 11 12 BA14 BA15 2,6 /E5_WEL BA16 BA17 2,6 /SYS_RST BA18 BA19 BA20 BA21 BA1 BA2 BA3 BA4 BA5 BA22 ATA_A2 CS3FX CAB_SEL 2 HD_AT8 HD_AT9 HD_AT10 HD_AT11 HD_AT12 HD_AT13 HD_AT14 HD_AT15 KEYWAY (NO PIN) 13 14 16 17 19 20 22 23 4 10 15 21 28 34 39 45 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 10K R61 V33 R62 0 R97 0 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 A19/A19/A21 NC/A20/A20 ACC WP#/ACC RY/BY/A19 BA19 BA18 BA8 BA7 BA6 BA5 BA4 BA3 BA2 U10 A15 A14 A13 A12 A11 A10 A9 A8 A19/A19/A21 NC/A20/A20 WE RST ACC WP/ACC RY/BY/A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 V33 1 BA17 HD15 HD7 HD14 HD6 HD13 HD5 HD12 HD4 HD11 HD3 HD10 HD2 HD9 HD1 HD8 HD0 WP#/ACC C132 104 C134 104 A19/A19/A21 BA1 0 NC/A20/A20 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DNS-0 RY/BY/A19 A16 BYTE/VIO VSS D15 D7 D14 D6 D13 D5 D12 D4 VCC D11 D3 D10 D2 D9 D1 D8 D0 OE VSS CE A0 R63 DNS-0 MX29LV160 /SYS_RST R64 DNS-0 BA1 BA17 BA22 R65 R64,R65,R66,R70 Not Stuff BA21 Stuff 0 R69 R66 R69,R70 BA20 Size R64,R65,R66 DNS-0 2MB R69 4MB R69,R70 V33 R64,R65,R66 8MB HD[7] HD[2] HD[1:0] HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HOST Read 2,6 HD[15..0] BBK 00 01 10 11 0 1 0 1 1 2 3 Document Number Sheet 7 of HD[15..0] 2,6 /E5_OE 2,6 13 Rev 0.0 /E5_CS0 2 DNS HEADER 3X1 Samsung - K4H281638D-TCB3 Micron - MT46V8M16-55 ESMT - M13S128168A-6T Tuesday, August 12, 2003 1 Nanya 128Mb DDR SDRAM 256Mb DDR SDRAM Normal Mode (Jumper 1-2) Debuge Mode (Jumper 2-3) Size C FLASH, BREG, ATA, IDC Date: Title JP1 R70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FLASH MEMORY(2 or 4 or 8 Mb) 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 GND GND GND GND GND GND GND GND 74LVC16373 J3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 HEADER 20X2 2 D C B A 32 D C B A 5 *0 R85 *0 R88 DNS-100K 100K DNS-100K DNS-100K DNS-100K DNS-100K DNS-100K 100K R73 R74 R75 R76 R77 R78 R79 R80 R89 100K R90 DNS100K R91 100K R92 100K R93 DNS-100K R94 DNS-100K R95 DNS-100K R96 100K 5 C141 56PF R103 51 1K V33_PHY_D 27PF C139 27PF C138 103 C148 104 C149 4 Y2 24.576MHz PHY_XO SYSCLK CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PD BIO_LREQ U12 1 2 3 4 5 6 7 8 9 10 11 12 PHY_XI FIREWIRE PHY R110 PHY_PD 22 GND_PHY_D R105 GND_PHY_D C147 680 680 680 103 2 BIO_LPS 2 BIO_PHY_CLK 2 BIO_PHY_CTL0 2 BIO_PHY_CTL1 BIO_PHY_DATA0 BIO_PHY_DATA1 BIO_PHY_DATA2 BIO_PHY_DATA3 BIO_PHY_DATA4 BIO_PHY_DATA5 BIO_PHY_DATA6 BIO_PHY_DATA7 GND_PHY_D 2 2 2 2 2 2 2 2 V33_PHY_D R111 DNS-10K R113 R116 R118 R119 GND_PHY_D C146 V33_PHY_D 103 PHY_PC0 PHY_PC1 PHY_PC2 TSB41AB1 S-PQFP-48-TI C150 104 C151 36 35 34 33 32 31 30 29 28 27 26 25 TPBIAS TPA+ TPATPB+ TPB- PHY_R1 PHY_R0 V33_PHY_A GND_PHY_A PHY_R1 R117 10K 10K R102 3 6.34K/1% R104 1M/1% R107 TPBIAS R106 56.2/1% 56.2/1% R108 5.11K/1% R112 56.2/1% R109 C143 224 GND_PHY_A 56.2/1% C144 GND_PHY_A 221 3 GND_PHY_A GND_PHY_A GND_PHY_D V33_PHY_D V33_PHY_D GND_PHY_D 1K 1K R120 R114 R115 AGND AVDD R1 R0 AGND TPBIAS TPA+ TPATPB+ TPBAGND AVDD C140 104 PHY_ISO 104 V33_PHY_A + C17 10u/16 GND_PHY_A PHY_R0 2 BIO_LREQ 2,7,10,11 /RST_PHY 2 BIO_LINK_ON 10K 10u/16 C145 GND_PHY_D V33 + GND_PHY_D 4 PHY_SE PHY_SM D C B A 5 + C142 1u/50 GND_PHY_A R207 R209 R206 R208 22 22 22 22 TPATPA+ TPBTPB+ 2 GND_PHY_A TPA+ TPATPB+ TPB- 2 CN6 *IEEE1394(4P) 1 2 3 4 5 6 TPBTPB+ TPATPA+ GND_PHY_A 1 3 2 4 TOP VIEW CN1 6P2.0 1 2 3 4 5 6 BBK Tuesday, August 12, 2003 Document Number Title Size C 1394 PHY Date: 1 1 Sheet 8 of 13 Rev 0.0 D C B A 33 PHY_FILT1 PHY_FILT0 48 47 46 45 44 43 42 41 40 39 38 37 LREQ DGND DGND DVDD DVDD XO XI PLLGND PLLVDD FILTER1 FILTER0 RESET LPS DGND C/LKON PC0 PC1 PC2 ISO CPS DVDD TESTM SE SM 13 14 15 16 17 18 19 20 21 22 23 24 PHY_PC0 PHY_PC1 PHY_PC2 PHY_ISO PHY_CPS D VOUT DV33 U13 PQ018EZ02/PQ070XZ02 3 VIN 2 R220 *1K 3 4 R122 *2.2K L18 + C155 330u/16 *FB + V18 V25 C284 104 C156 104 C283 103 C170 104 L7 *B601 V33 C282 47u/16 2_5V + C168 330u/16 C117 104 R123 *1K R124 *1K 4 L8 B601 L9 B601 V33 VCC C153 104 C161 104 3 3 + + C152 47u/16 C159 100u/16 DV33 V25_VOUT_A C169 104 + L3 L4 L5 L6 C165 100u/16 B601 B601 B601 B601 V25_D C166 104 + + 2 V33_PHY_A 10u/16 C154 V33_AIN_A + GND_AIN 104 C162 VCC_VOUT_A C160 100u/16 GND_VOUT C164 VCC_AOUT_A C163 104 GND_AOUT 220u/10 BBK POWER CONN Document Number Title Size A4 Tuesday, August 12, 2003 2 Date: Sheet 1 1 9 of 13 Rev 0.0 34 5 1 VIN VIN VOUT VOUT ADJ U8 LT1117-3.3 4 U14 PQ025EZ01 R219 0 1 R121 *1K MAIN POWER REG 2_5V C158 104 3 GND ADJ 4 1 C157 220u/10 VCC C167 104 C172 104 5 GND + V33 + C171 220u/10 VC ADJ 5 C B A 5 2 VC 2 D C B A 13 R_Y_IN 6 F_Y_IN/F_CVBS_IN 13 R_C_IN 13 F_C_IN 5 R125 R127 R129 R133 18 18 18 18 R126 56 R128 56 R130 56 R134 56 R136 56 C175 C176 C177 C179 C181 C182 473 473 473 473 473 473 C184 10u/16 C178 27PF C180 27PF TP4 TP5 104 C187 104 C188 104 C189 104 C190 104 C191 4 2,7,11,12,13 SDA 2,7,11,12,13 SCL C186 2,7,8,11 /RST_7115 104 V33_VID C185 C195 104 V33_VIA 104 C194 104 C173 473 473 C183 C174 GND_VIN CLK_VI_XTAL Y3 24.576MHz 100 CLK_VI_XTALI R141 104 3 20 18 19 16 14 13 10 12 22 47 21 80 V33_VID 32 31 8 5 6 4 7 GND_VIN 42 SDA SCL 41 V33_VIA 9 15 24 43 75 1 25 51 83 33 93 68 58 27 23 17 11 GND_VIN V33_VID GND_VIN IDC Slave Addr: 0x42/43 AI11 AI12 AI1D AI21 AI22 AI2D AI24 AI23 AOUT ITRI AGND XTRI ITRDY AMXCLK VXDD VXSS XTAL XTOUT XTALI SDA SCL VDDA0 VDDA1 VDDA2 CE VSSA2 VSSA1 VSSA0 VDDCI VDDE VDDE VDDE VDDE VDDI VDDI VDDI VDDI VDDI ASCLK ALRCLK AMCLK 18 18 + B601 2 C193 104 39 40 37 R135 R138 L10 C192 100u/16 GND_VIN 3 1 IDQ IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 XDQ XRH XRV XRDY RTS1 RTS0 RTCO LLC2 ICLK LLC XCLK RESON VSSI VSSI VSSI VSSE VSSE VSSE VSSE TRSTN TCK TDO TDI TMS U15 46 54 55 56 57 59 60 61 62 81 82 84 85 86 87 89 90 95 92 91 96 35 34 36 29 45 28 94 VI_7 VI_6 VI_5 VI_4 VI_3 VI_2 VI_1 VI_0 2 RP32 33/RP 5 6 7 8 VI_D9 VI_D8 VI_D7 VI_D6 ADC_SEL1 13 ADC_SEL0 13 4 3 2 1 VI_[7..0] VI_7 VI_6 VI_5 VI_4 V33_VID VI_D5 VI_D4 VI_D3 VI_D2 10K RP33 33/RP 5 6 7 8 22 4 3 2 1 R137 VI_D[9..2] Document Number 2 Tuesday, August 12, 2003 1 R132 V33_VID 10K Sheet R131 1 10K V33_VID Size C VIDEO IN Date: Title BBK VI_3 VI_2 VI_1 VI_0 R139 ALRCLK POR: 0 = 24.576MHz src 1 = 32MHz src (int. pulldown) 30 38 88 63 76 50 26 100 97 98 2 3 99 SAA7115 QFP-100 TP6 2 13 13 11 VI_VSYNC0 2 GPO1 GPO2 RTC0 of VI_CLK0 2 10 13 Rev 0.0 D C B A 35 64 65 66 67 69 70 71 72 52 53 48 49 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 HPD7 HPD6 HPD5 HPD4 HPD3 HPD2 HPD1 HPD0 IGPV IGPH IG0 IG1 79 78 77 74 73 44 13 R_CVBS_IN 13 TV_CVBS_IN R140 56 GND_VIN DV33 1 + 4 1 D C B A 5 1 VO_D0 VO_D1 VO_D2 VO_D3 VO_D4 VO_D5 2 2 2 2 2 2 VO_D6 2 VO_D7 2 C232 104 C233 5 C231 104 V25_D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R145 R146 R148 R149 VO_CLK R150 4.7K C225 104 C226 ADV7302 104 V25_VOUT_A 4.7K 4.7K 4.7K 4.7K VDD_IO GND_IO GND_IO Y0 Y1 Y2 Y3 Y4 Y5 VDD DGND Y6 Y7 GND_IO GND_IO C0 U16 + C224 10u/16 4 C227 104 TP9 TP10 1 1 1 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TP7 TP8 100 R147 C200 104 R142 1.5K HPD7/GPIO7 HPD6/GPIO6 HPD5/GPIO5 HPD4/GPIO4 HPD3/GPIO3 HPD2/GPIO2 HPD1/GPIO1 HPD0/GPIO0 PADDR WR RD SDA SCL TTXDATI TTXDATO TST RST CVBSI Y C G_Y B_U R_V *104 *104 *104 Y C CVBS R/Y-V G/Y B/Y-U VREF ISET XTALI XTALO INT FLD_CB C211 C209 C204 C201 100u/16 GND_VOUT V25_VOUT_A C196 104 8 7 6 5 4 3 2 1 29 10 11 19 20 21 22 23 24 25 26 16 28 27 32 33 30 31 13 34 VDAT7 VDAT6 VDAT5 VDAT4 VDAT3 VDAT2 VDAT1 VDAT0 CLK27 HSYNC/CB VSYNC U17 *CS4955 L13 *FB C197 104 R143 1.5K R144 680 C210 *104 VO_D7 VO_D6 VO_D5 VO_D4 VO_D3 VO_D2 VO_D1 VO_D0 R158 *100 DV33 C199 821 C198 392 IDC Slave Addr: 0xD4/54 S_BLANK Rset 1 VREF COMP1 DAC A DAC B DAC C VAA AGND DAC D DAC E DAC F COMP2 Rset_2 EXT_LF RESET ADV7302 2 VO_CLK 2,7,10,12,13 SDA 2,7,10,12,13 SCL R160 *100 R163 *10K 3 3 44 48 47 R_V G_Y B_U CVBSI Y C R157 *4.7K GND_VOUT 39 40 43 38 37 9 12 14 15 Y R151 C205 *220 *331 R156 C222 *220 *331 R153 C214 220 *331 CVBSI G_Y C202 *22PF L11 1.8uH C212 *22PF L14 1.8uH C219 *22PF L17 1.8uH C206 101 C215 101 C223 101 Y_O Y/G_O 13 2 13 2 C R_V R152 C207 *220 *331 R154 C216 *220 *331 R155 C220 *220 *331 B_U VCC_VOUT_A R162 0 C203 *22PF L12 1.8uH C213 *22PF L15 1.8uH C218 *22PF L16 1.8uH R161 *3.9K 2 R164 3.9K C208 101 C217 101 C221 101 R159 150 Q1 3906 GND_VOUT C_O 13 Pr/R_O 13 1 1 CVBS_O 13 Tuesday, August 12, 2003 Document Number VIDEO OUT C113 220u/10 R210 *2.2 Pb/B_O 13 BBK Title Size C Date: Sheet 11 of 13 Rev 0.0 D C B A 36 VO_D8 2 VO_D9 2 VO_D10 2 VO_D11 2 VO_D12 2 VO_D13 2 VO_D14 2 VO_D15 2 C230 104 VO_CLK 2 C229 104 GND_VOUT VO_CLK D RTC0 2,7,10,12,13 SDA 2,7,10,12,13 SCL 10 2,7,8,10 /RST_7302 C228 104 V25_D 104 GND_VOUT 2,7,8,10 /RST_7302 GND_VOUT + VO_D2 VO_D1 VO_D0 4 + C B A 5 1 3 17 36 41 46 VDD VAA0 VAA1 VAA2 GNDD GNDA0 GNDA1 GNDA2 18 35 42 45 VO_D7 VO_D6 VO_D5 VO_D4 VO_D3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DGND CLKIN_B S7 S6 S5 S4 S3 DGND VDD S2 S1 S0 GND_IO GND_IO S_HSYNC S_VSYNC C1 C2 I2C ALSB SDA SCL P_HSYNC P_VSYNC P_BLANK C3 C4 C5 C6 C7 RTC_SCR_TR CLKIN_A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D C B A A_L_IN 13 A_R_IN 13 R212 150 R211 150 C114 103 GND_AIN 5 C116 10u/16 DV33 V33_AIN_A C115 103 AO_D0 2 R217 *0 VCC_AOUT_A DV33 C250 10K ADC_DIV ADC_DIF DNS 1u/50 10K C266 104 C267 + AO_MCLKO 2 AO_SCLK 2 AO_FSYNC 2 AO_D3 2 AO_D2 2 AO_D1 2 SCL 2,7,10,11,13 SDA 2,7,10,11,13 /RST_AUDIO 7,13 C252 4 C256 104 MCLK SCLK LRCK SDATA FILT+ VQ REF_GND TST GND DNS 104 GND_AOUT + DV33 AO_D0 2 VL VA RST DIF DIV AINR AINL U20 C255 10u/16 14 13 16 9 8 1 5 CS5333 4 2 3 7 4 11 15 12 10 6 C251 + DV33 DNS 1u/50 7 5 6 2 3 4 15 13 11 12 10 1 14 8 22 IDC Slave Addr: 0x22/23 C235 C234 10u/16 10u/16 3 U18 C263 1u/50 20 19 18 17 16 15 14 13 12 11 DNS 104 DNS 104 0 0 DNS 3.3u/16 R173 10K DV33 R172 *10K DV33 R171 10K R216 R215 R176 *10K L_OUT + C257 10u/16 GND_AOUT C258 104 R175 *10K R180 *10K R178 10K DV33 R174 *10K DV33 GND_AOUT 9 21 16 17 20 19 18 24 23 25 27 26 28 10u/16 L_OUT R_OUT MUTE_6CH C236 *0 *0 10u/16 AOUTL1 AOUTR1 MUTEC1 AOUTL2 AOUTR2 MUTEC2 FILT+ VQ AOUTL3 AOUTR3 MUTEC3 GND1 GND2 CS4360 LATI2S SCKDSD SDIDEM MUTEB MODE CSBIWL VREFP VREFN VMID VOUTL C261 104 VCC_AOUT_A C260 104 + 3 C249 C237 MCLK BCLK LRCK SDATA1 SDATA2 SDATA3 M2 AD0/CS SCL SDA RST VLS VLC VD VA C254 DNS 104 U19 WM8728 LRCIN DIN BCKIN MCLK ZERO DGND DVDD VOUTR AGND AVDD + C265 C247 10u/16 R213 R214 + 10u/16 1 2 3 4 5 6 7 8 9 10 C259 10u/16 GND_AOUT 104 22 47K C262 AI_MCLKO 2 AI_SCLK 2 AI_FSYNC 2 AI_D0 2 GND_AIN 1u/50 C248 C238 C246 C239 + + DNS 3.3u/16 + DNS 104 C253 + 2 E5_GPIO3 SCL SDA GND_AIN 2,7,10,11,13 2,7,10,11,13 MUTE_2CH + IDC Slave Addr: 0x20/21 + R183 R184 R_OUT 104 C264 R179 10K R177 *10K DV33 AIN_D GND_AIN + Audio Out (2 & 6 ch) 104 DNS-10K DNS-10K R181 + GND_AIN /RST_AUDIO 7,13 R185 R186 R182 Audio In 5 R169 R168 R167 R166 R165 5.6K 5.6K 5.6K 5.6K 5.6K 5.6K C240 122 DNS IN4148 D7 2 GND_AOUT R170 1 D9 2 IN4148 D8 IN4148 1 2 1 GND_AOUT 2 C241 122 2 C242 122 C243 122 MUTE C244 122 13 C245 122 CENTER 13 SUBWOOFER 13 REAR_L 13 REAR_R 13 A_R_OUT 13 A_L_OUT 13 BBK Tuesday, August 12, 2003 Document Number Title Size C Audio IN/OUT Date: 1 1 Sheet 12 of 13 Rev 0.0 D C B A 37 + D C B A CN4 10P2.5 1 2 3 4 5 6 7 8 9 10 P_CTL 5VSTB +3.3V VCC GND GND GND +2.5V +2.5V 5 2 E5_SPI_MISO 2 E5_SPI_CLK 2 E5_GPIO0 2 IR_IN 6 /RST_HOST_LED L20 FB FB V33 C275+ 104 4 R190 R191 R187 R188 R189 5V_STB + C273 10u/16 VCC + 33 33 33 33 33 C281 *10u/16 + C279 C277 104 330u/16 4 C280 *104 R194 *4.7K R198 *1K 1 2 3 4 5 6 7 8 9 10 VDD GP5 GP4 GP3 3 GND GP0 GP1 GP2 U21 *68HC908QT1 CN3 10P2.0 1 2 3 4 3 /RST_HOST_LED CPUMUTE RTC_INT PSW R197 *0 R195 *4.7K GND VFD_DIO VFD_CLK VFD_STB IR_IN 5V_STB /RST_HOST_LED P_CTL_PSW R200 *4.7K R199 *4.7K R193 *4.7K FRONT PANEL INTERFACE D_FM FP_SCLK RDY_FM /FP_RST D_HOST ATN_FM C268 C269 C270 C271 C272 2_5V + C274 330u/16 5V_STB D10 *3.3V R202 *2.2 1/4W C276 330u/16 47PF 47PF 47PF 47PF 47PF C278 104 5V_STB 2 E5_SPI_MOSI 2 E5_GPIO1 L19 5 R192 0 P_CTL STBY POFF IR ADDRESS:07F8 KEY VALUE:01FE 8 7 6 5 R201 *0 R196 *10K IR_IN CN2 24P1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 GND_AOUT CN5 26P1.0 OPTICAL 6 SPDIF_OUT 6 SUBWOOFER 12 MUTE 12 CENTER 12 /RST_AUDIO 7,12 REAR_R 12 REAR_L 12 A_R_OUT 12 A_L_OUT 12 GPO1 10 GPO2 10 E5_GPIO5 2 ADC_SEL0 10 ADC_SEL1 10 SDA 2,7,10,11,12 SCL 2,7,10,11,12 Y_O 11 11 5V_STB C_O CVBS_O 11 11 Pr/R_O 11 Y/G_O R_C_IN 10 Pb/B_O 11 R_Y_IN 10 F_Y_IN 6 F_CVBS_IN 6 R_CVBS_IN 10 F_C_IN 10 TV_CVBS_IN 10 A_L_IN 12 A_R_IN 12 Size B Tuesday, August 12, 2003 Document Number INTERFACE Date: Title BBK A_R_IN A_L_IN V2_IN V4_IN V1_IN V3_IN R_Y_IN R_C_IN B_U_OUT G_Y_OUT R_V_OUT V_OUT S_C_OUT RTC_INT S_Y_OUT SCART1 SCART2 CPUMUTE MICDET A/V I/O Connector E5_GPIO1 2 P_CTL R203 1K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND_AIN 2 1 1 Sheet 13 of 13 Rev 0.0 38 D C B A 39 40 41 42 4 3 +5V S1 S2 S 1 2 1 3 2 1 3 R2 15K R3 15K R4 10K R142 B221 R143 B221 R144 B221 R15 10K R5 10K B EXT_AUDIO_IN_L EXT_AUDIO_IN_R R_C_IN D6 1N4148 R_Y_IN D5 1N4148 V2_IN +5V D4 1N4148 D2 1N4148 C3 4.7u/50 C6 4.7u/50 +5V +5V D7 1N4148 D8 1N4148 C14 4.7u/50 F_AUDIO_IN_R C11 10u/16 + + R24 4.7K + Q2 3904 Q1 3906 R146 75 F_AUDIO_IN_L D9 1N4148 V3_IN +5V BTSC_AINL 2 2 X0 X1 X2 X3 Y0 Y1 Y2 Y3 INH A B C8 103 1 5 2 4 6 10 9 12 14 15 11 BTSC_AINR IN_L BTSC_AINL IN_R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R14 *0 *0 R27 *20K R25 *20K C Y X C2 104 + A 0 1 0 1 +6V R1 D1 6.2V R21 0 *0 A_L_IN A_R_IN A_L_IN +12V R145 0 A_R_IN 220 R22 *0 D GPIO4 GPIO7 GPIO8 GPIO12 +5V F_Y_IN + R7 *0 D CN1 24P1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CN2 26P1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 <Title> MICDETCT AUDIO_SEL1 AUDIO_SEL2 POWER_OFF/16316 RDY C19 103 3 Date: SCART1 SCART2 ADC_SEL0 ADC_SEL1 OPTICAL 6 SPDIF_OUT 6 E 5V_STB SUBWOOFER 5 MUTE 3 CENTER 5 /RST_BTSC 3 REAR_R 4 REAR_L 4 A_R_OUT 3 A_L_OUT 3 SCART1 3 CPUMUTE 3 GPIO4 3 IIC_SDA 2 IIC_SCL 2 RTC_INT 2 S_Y_OUT 2 S_C_OUT 2 E Sheet 1 B_U_OUT 6 G_Y_OUT 6 R_V_OUT 6 V_OUT 2 R_V_OUT G_Y_OUT B_U_OUT R_C_IN R_Y_IN F_Y_IN V3_IN V2_IN V4_IN V1_IN A_L_IN A_R_IN Wednesday, August 20, 2003 Size Document Number Custom<Doc> Title N/A R_AUDIO F_AUDIO TUNER LSI ADC_SEL1 R16 -12V 220 R118 10K Q20 3904 R147 75 TV_MONO C18 220u/10 BBK SOURCE R_AUDIO TUNER F_AUDIO LOOP ADC_SEL0 R120 3.3K R119 3.3K + C15 10u/16 TV_CVBS R_CVBS1 F_CVBS F_C_IN ADC_SEL0 1 0 1 0 +6V D3 6.2V R8 R117 10K Q19 3904 ADC_SEL1 1 1 0 0 C7 47u/16 C4 4.7u/50 C5 4.7u/50 C1 47u/16 13 B 0 0 1 1 +5V 5V_STB C9 + 104 3 U1 4052 3.3K 0 R122 *0 3 +5V D17 1N4148 D16 1N4148 V1_IN V2_IN V3_IN V4_IN TV_MONO C17 4.7u/50 C12 + 100u/16V R11 3.3K C20 102 IN_L R6 B221 IN_R C24 *4.7u/50 C23 *4.7u/50 TV_IF R10 R121 C13 103 R20 10K R30 *10K +5V + C10 100u/16V R29 *10K R18 2.2K V1_IN R12 IIC_SDA IIC_SCL BTSC_AINR R9 *0 V4_IN R_OUT 3,6 L_OUT 3,6 +12V TUN1 JS-6A/L1615BG AFO Vif CVBS 2nd IF OUT AFC OUT AGC NC AS SDA SCL BM BT NC R133 R134 *0 *0 R23 22 D14 1N4148 D15 1N4148 + R127 *4.7K R26 1K R126 *4.7K D10 1N4148 +5V +5V C16 4.7u/50 D11 1N4148 R28 4.7K + 3 4 2 R13 15K R17 15K R19 10K R135 B221 R136 R_Y_IN *0 C22 104 R137 *0 SCART1 R_C_IN R139 B221 C of 7 Rev 1.0 43 A 6 6 6 R138 *0 B + AUDIO IN 3 4 2 1 AV2-8.4-6G CS-09 CN3 7P2.0 CVBS 2 R_Cr G_Y B_Cb L_OUT 3,6 R_OUT 3,6 CVBS/S_VIDEO IN S3 *SCART 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 R124 *4.7K 1 2 3 4 5 6 7 SCART2 + 2 1 R125 *4.7K A VEE + + 16 VSS 7 VDD 8 4 3 2 1 + 4 3 2 A V_OUT 1 S_Y_OUT 1 S_C_OUT 1 +5V +5V C25 220u/10 R36 330 R43 330 C26 220u/10 + 1 A R32 6.8K R33 0 R39 6.8K R41 0 B B R35 6.8K R42 6.8K Q3 3904 R37 470 Q4 3904 R44 470 C R31 B221 R34 B221 BT1 3V D13 1N4148 D12 1N4148 R38 B221 5V_STB C CVBS 1 RTC_INT 1 C29 *20PF X1 32.768KHZ/20pF C28 20PF Title D Size A4 D Date: 1 3 4 2 X1 X2 INT GND U2 PCF8563 S CVBS/S-VIDEO 1 3 4 2 S4 CS-09 5V_STB 1 2 3 4 IIC_SDA 1 IIC_SCL 1 R40 4.7K <Title> Document Number <Doc> VCC SQW SCL SDA Wednesday, August 20, 2003 8 7 6 5 Sheet E E 2 C27 104 of 7 Rev 1.0 44 4 3 2 1 + R47 4.7K R58 4.7K B R50 *33K R61 *33K R64 *1K C68 104 C40 47u/16 Q9 *3904 C67 104 R51 24K C35 151 2 3 6 5 1 4558 U3B C64 104 A+12V A+12V C65 104 7 4558 U3A A-12V A-12V C66 104 GPIO4 -12V +12V +5V MICIN C C41 104 1 C C31 10u/16 C36 10u/16 R66 10 R49 47K R48 330 R59 R62 47K -12V C33 102 330 C38 102 R132 2.2K R68 2.2K R70 SCART1 1 *2.2K R72 *2.2K MUTE 1 CPUMUTE 1 R53 1K R56 1K Q5 3904 D R_OUT L_OUT Q8 3904 5V_STB R123 100 3906 R52 100K A-12V R_OUT 1,6 C34 103 L_OUT 1,6 Q10 3906 Q6 22K R60 C39 100u/16V Sheet AMUTE 4,5 R63 220 3906 Q7 Wednesday, August 20, 2003 Document Number <Doc> <Title> R69 10K R67 30K Q11 3904 Title Size A4 D Date: E E 3 +5V R54 *0 7 Rev 1.0 5V_STB R55 0 of 45 R45 24K C30 151 R129 33K R131 33K MICIN A-12V CN4 *7P2.0 1 A+12V 2 3 4 5 6 7 - R65 *2.2K C43 104 + C32 102 C37 102 Q21 3906 + C70 47u/16 R71 10 + - A R46 4.7K R57 4.7K R130 *2.2K +5V +12V C42 47u/16 C69 104 + A_R_OUT 1 -12V R128 *2.2K -12V AGND +12V GND +5V +5V A_L_OUT 1 SCART1 1 CN5 5P2.5 1 2 3 4 5 B + 4 3 2 1 A + + + 4 8 4 8 4 3 2 1 B R75 4.7K R73 24K C44 151 2 3 - C46 102 R78 24K C48 151 6 5 + R74 4.7K R81 4.7K R82 4.7K 1 4558 U4B 7 4558 U4A A-12V A-12V - A REAR_R 1 REAR_L 1 C50 102 B + 4 3 2 1 A C A+12V A+12V C + + 4 8 4 8 C45 10u/16 C49 10u/16 R77 47K R76 330 AMUTE 3,5 R83 R84 47K C47 102 330 C51 102 R79 1K 1K R80 LT_OUT Title D Size A4 D Date: Q12 3904 REAR_R_OUT REAR_L_OUT Q13 3904 <Title> Document Number <Doc> REAR_R_OUT 6 Sheet REAR_L_OUT 6 Wednesday, August 20, 2003 E E 4 of 7 Rev 1.0 46 4 3 2 1 R87 4.7K 1 4558 U5A A-12V A-12V 7 4558 U5B A+12V A+12V C53 10u/16 C57 10u/16 C R89 47K R96 47K R88 330 R95 AMUTE 3,4 C C55 102 330 C59 102 R91 1K 1K R92 Q14 3904 D CENTER_OUT SUBWOOFER_OUT Q15 3904 Title Size A4 D Date: CENTER_OUT 6 SUBWOOFER_OUT 6 <Title> Document Number <Doc> Wednesday, August 20, 2003 Sheet E E 5 of 7 Rev 1.0 47 B R85 24K C52 151 2 3 - C54 102 R90 24K C56 151 6 5 + A R86 4.7K R93 4.7K R94 4.7K - CENTER 1 SUBWOOFER 1 C58 102 B + 4 3 2 1 A + + 4 8 4 8 4 3 2 1 4 3 A 1 R_V_OUT 1 B_U_OUT 1 G_Y_OUT +5V +5V +5V C60 220u/10 C61 220u/10 R103 330 + 2 C63 220u/10 R110 330 + 1 R115 330 + A R97 6.8K R99 0 R106 6.8K R108 0 R112 6.8K R113 0 R102 6.8K R109 6.8K R114 6.8K B Q16 3904 R104 470 Q17 3904 R111 470 R116 470 Q18 3904 B 1 1 G_Y B_Cb R_Cr B221 1 R98 B221 B221 R100 R101 1 OPTICAL C +5V C C62 104 1 SPDIF_OUT 1,3 R_OUT 1,3 L_OUT 1,3 5 CENTER_OUT D B221 S5 AV12-8.4-2G-2 E 1 6 4 2 17 15 13 18 16 14 23 21 19 24 22 20 B221 8 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 7 5 R105 4 REAR_L_OUT R107 1,3 L_OUT R_OUT 4 REAR_R_OUT 5 SUBWOOFER_OUT 1 2 3 OP1 GP1F32T 10 6 12 TOP VIEW Document Number <Doc> Wednesday, August 20, 2003 E 9 <Title> Sheet 11 Title Size A4 D Date: of 7 Rev 1.0 48 4 3 2 1 2 TV_IF A FB1 B601 C76 101 VCC_AIN + + 2 TV_MONO R141 1K C85 10u/16 C90 10u/16 C78 56PF VCC_AIN C C73 10u/16 U6 + C74 104 C71 1 C72 + 1 3.3u/50 2 104 2 C75 10u/16 AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC DACM_L DACM_R VREF2 NC NC D 33 32 31 30 29 28 27 26 25 24 23 102 C83 102 C84 Wednesday, August 20, 2003 Document Number <Doc> <Title> MSP34X5G-PMQFP44 Title Size A4 D Date: C80 474 C82 474 Sheet E E 7 BTSC_AINL 7 4 3 2 1 Rev <RevCode> BTSC_AINR of 49 B 33PF AVSUP ANA_IN1+ ANA_INTESTEN XTAL_IN XTAL_OUT TP D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ 103 C89 DVSUP C88 10u/16 + 1 2 3 4 CLK_MSP_XIN 5 CLK_MSP_XOUT 6 7 8 Y1 9 18.432MHz 10 11 +5V IIC_SCL 1 2 BTSC TV_MONO C79 33PF AVSUP AHVSUP C81 R140 0 C87 471 C92 471 BDCOMP IDC Slave Addr: 0x80/81 C77 56PF C86 152 C91 152 IIC_SDA /RST_BTSC C + +5V FB2 B601 B 44 43 42 41 40 39 38 37 36 35 34 AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L AGNDC AHVSS CAPL_M I2C_SCL I2C_SDA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 TP_CO DVSUP DVSS I2S_DA_IN2 RESETQ 12 13 14 15 16 17 18 19 20 21 22 4 3 2 1 A 1 2 1 2 50 CAM350 PRO V 7.0 : Thu Aug 28 11:23:30 2003 - (Untitled) : BS.pho 51 CAM350 PRO V 7.0 : Thu Aug 28 11:23:35 2003 - (Untitled) : TL.pho 1 52 CAM350 PRO V 7.0 : Thu Aug 28 11:23:40 2003 - (Untitled) : TS.pho 53 CN1 5P2.0 5 4 3 2 1 K1 K3 K6 K9 R4 10K SW SW SW VCC C11 2.2u/16 R24 10K R1 VCC R22 4.7K 2.2 1/4W F+ FC1 22u/50 -24V C2 104 SW SW 220 SW R7 220 C17 102 220 220 R8 R11 R9 LD2 B LD4 G LD5 R Q1 8050C LD3 G R14 10K R5 10K K10 K7 K4 K2 + 1 + VDD D5 1N4148 K5 K8 K11 R6 10K VDD P_CTL_PSW SW SW SW U2 R2 1 2 3 HS0038A2 OUT VCC GND 220 R LD1 KEY_04 C3 103 D1 1N4148 KEY03 KEYC KEYB KEYA 0 R23 R25 10 D6 1N4148 5V_STB C9 20PF R12 100 + + VDD C10 20PF Y2 32.766KHZ/20pF FIP24 P00 P01 P02 P03 P04 P05 P06 P07 IC X2 X1 VSS0 D2 1N4148 40 41 42 43 44 45 46 47 48 49 50 51 52 KEY02 KEY_01 VDD D3 1N4148 D4 1N4148 C18 4.7u/16 1 C7 30PF Y1 5MHZ/20pF C6 30PF IR 2 C19 103 C21 103 U1 A UPD16316 R17 2.7K C20 47u/16 A G[1:6] R18 2.7K C8 102 FIP12 FIP11 FIP10 FIP9 FIP8 FIP7 FIP6 FIP5 FIP4 FIP3 FIP2 FIP1 FIP0 R13 *10K R19 2.7K 26 25 24 23 22 21 20 19 18 17 16 15 14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 VDD R10 10 VDD ZD1 *4.3V 1/2W 数量 P[1:16] R3 270K 更改单号 审 核 C12 C13 C14 C15 C16 *30PF *30PF *30PF *30PF *30PF 更改 设 计 -24V C4 103 C5 103 批 准 日期 VDD 5V_STB 签名 标准化 D_FM FP_SCLK RDY_FM /FP_RST D_HOST ATN_FM VFD G1 G2 G3 G4 G5 G6 F- P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 F+ 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 F1 F1 VFD1 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 NX NX NX NX NX NX NX 1G 2G 3G 4G 5G 6G F2 F2 HNVC05SS41 CN2 10P2.0 共 1 张 版次 1.0 广东步步高电子工业有限公司 第 1 张 BBK GND 1 VFD_DIO 2 VFD_CLK 3 VFD_STB 4 IR_IN 5 5V_STB 6 /RST_HOST_LED 7 P_CTL_PSW 8 D_HOST 9 ATN_FM 10 AB9915面板原理图 54 G6 G5 G4 G3 G2 G1 P16 P15 P14 39 38 37 36 35 34 33 32 31 30 29 28 27 FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16 FIP15 FIP14 FIP13 VLOAD VDD1 VDD0 XT1 XT2 RESET P10 P11 P12 SCK SO SI INTP0 INTP1 TI 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 1 2 1 CAM350 PRO V 7.0 : Mon Sep 15 08:53:16 2003 - (Untitled) : BL.pho 55 CAM350 PRO V 7.0 : Mon Sep 15 08:53:24 2003 - (Untitled) : TS.pho 56 3 ISENCE NC 6 4 DRAIN DRAIN 5 B R1 470K 1/2W C4 103/1KV R2 68K 2W T1 BCK-28-0300 1 3 C 15 14 13 12 11 10 9 8 7 *101/500V D2 HER303 C19 *101/500V D1 HER105 C18 D3 SR1060 + L1 FB D + -12V C2 104 IC4 PQ12RD21 Vin R7 10K 1/4W STBY 签名 标准化 Vo Vc + + 2 + + CE16 100u/25 +12V R4 1K +3.3V D14 1N5401 D15 1N5401 +5V C16 104 F+ F-25V GND +5V 板号 5AB9915-0 SWITCH POWER SUPPLY 开关电源原理图 C15 104 -25V R3 10K CE15 220u/16 CE17 220u/16 C20 104 + Q2 1PP15N03L R8 CE7 10u/25 C21 102 CE13 47u/50 批 准 日期 330 1/4W CE10 GZ1000u/10 R21 150 1/4W 1PP15N03L Q1 1 CE2 100u/25 D13 5.1V 1/2W 更改单号 Q3 2N5551 CE9 GZ2200u/10 L5 10uH + + CE4 470u/25 STBY Q5 2N5551 R19 10K L2 FB L3 10uH R18 10K 1% R9 47K + CE8 R16 GZ1000u/10 *10K 1% CE3 470u/25 CE1 100u/25 + 100u/25 CE12 D5 BYW29E-200 C17 101 CE6 GZ2200u/10 D6 HER105 D8 HER105 C12 104 R17 4.7K R11 10K 1% Q4 2N5401 R10 10K 数量 审 核 D GND 3 + 7 + VCC D4 HER107 5 6 IC2 PC817 R14 1.2K + + FB A C1 *221 AC400V 2 D10 1N4007 + L4 FB R5 33 1/4W R13 22 1/4W C5 *101 1KV R6 470K 1/2W C9 *104 C7 104 IC3 TL431 +12V R20 1K 更改 设 计 冯红俊 CE14 100u/25 C8 104 CN5 5P2.0 1 2 3 4 5 E CN1 2P2.5 1 2 CN2 5P2.5 1 2 3 4 5 CN3 10P2.5 1 2 3 4 5 6 7 8 9 10 5VSTB TO fan CE18 *1000u/10 CN4 4P3.96 1 2 3 4 TO HDD 共 1 张 版次 1.0 +5V +12V D16 + 12.5mm P_CTL 5VSTB +3.3V +3.3V +5V GND GND GND +2.5V/5 +2.5V/G -12V GND +12V GND +5V +12V BBK E 广东步步高电子工业有限公司 第 1 张 57 D11 1N4007 CE5 100uF/400V 8 D9 1N4007 D12 1N4007 GND D7 HER105 SOFT R12 0.47 1W R15 470 C + LF1 40mHX2 C10 473 1 CE11 22u/25 C11 104 C6 221 AC400V 2 RT1 10/4A(104MS) t IC1 ICE2A365/ICE2A365 J12 7.5mm B 4 C13 104/~275 RV1 *910K/1/2W F1 250V/T2AL 2 1 BCN2 *2P7.92 C3 C14 221 AC400V 221 AC400V BCN1 2P7.92 A 3 1 4 3 2 1 1 2 4 3 2 1 CAM350 PRO V 7.0 : Thu Aug 28 11:48:46 2003 - (Untitled) : bl.pho 58 CAM350 PRO V 7.0 : Thu Aug 28 11:48:52 2003 - (Untitled) : to.pho 59 PARTS LIST ITEM MAIN BOARD DESCRIPTION QTY 1 RESISTOR 1/16W 0Ω ±5% 13 2 RESISTOR 1/16W 22Ω ±5% 22 3 RESISTOR 1/16W 33Ω ±5% 10 4 5 6 7 8 9 RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR 1/16W 330Ω ±5% 1/16W 680Ω ±5% 1/16W 1K ±5% 1/16W 1.5K ±5% 1/16W 4.7K ±5% 1/16W 5.1K ±5% 2 5 5 2 8 1 10 RESISTOR 1/16W 10K ±5% 26 11 12 13 14 15 16 17 RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR 1/16W 22K ±5% 1/16W 47K ±5% 1/16W 100K ±5% 1/16W 1MΩ ±5% 1/10W 1.18K ±1% 1/16W 100Ω ±5% 1/16W 6.2K ±5% 1 1 6 1 1 3 1 18 RESISTOR 1/16W 51Ω ±5% 17 19 20 21 22 23 RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR 1/16W 120Ω ±5% 1/16W 3.9K ±5% 1/16W 5.6K ±5% 1/16W 150Ω ±5% 1/16W82Ω±5% 1 1 6 3 3 24 RESISTOR 1/16W 56Ω ±5% 14 25 26 27 RESISTOR CHIP RESISTOR CHIP RESISTOR 1/16W 18Ω ±5% 1/16W33Ω ±5% 8P 1/16W22Ω ±5% 8P 6 7 4 28 CHIP RESISTOR 1/16W56Ω ±5% 8P 21 29 ELEC.CAP ELEC.CAP11 16V10U±20%5×11 2 17 31 ELEC.CAP ELEC.CAP11 16V47U±20%5×11 2 15 32 33 33 35 36 37 ELEC.CAP ELEC.CAP ELEC.CAP ELEC.CAP CER.CAP CER.CAP ELEC.CAP11 16V100U±20%6×12 2.5 ELEC.CAP11 16V220U±20%6×12 2.5 ELEC.CAP11 25V3.3U±20%5×11 2 ELEC.CAP11 16V330U±20%8×12 3.5 50V 22P ±5% NPO 0603 50V 47P ±5% NPO 0603 5 7 2 5 1 5 60 LOCATION L2,R51,R62,R63,R69,R81,R97,R162,R192, R213,R214,R223,R219 R11~R15,R16,R17,R18,R19,R20,R21,R22,R 23,R25,R26,R105,R139,R183,R206,R207,R 208,R209 R57,R98,R99,R100,R101,R187,R188,R189, R190,R191 R59,R153 R86,R116,R118,R119,R144 R8,R110,R114,R115,R203 R142,R143 R67,R68,R71,R145,R146,R148,R149,R150 R112 R1,R3,R4,R5,R7,R9,R10,R47,R48,R50,R52, R53,R54,R55,R58,R61,R72,R87,R113,R117 ,R120,R131,R132,R137,R181,R182 R56 R184 R74,R80,R89,R91,R92,R96 R104 R27 R24,R141,R147 R102 R28,R29,R30,R31,R32,R33,R34,R35,R36,R 37,R38,R39,R40,R41,R42,R43,R103 R60 R164 R165~R169,R170 R159,R211,R212 R82,R83,R84 R44,R45,R46,R126,R128,R130,R134,R136, R140,R205,R106~R109 R125,R127,R129,R133,R135,R138 RP27,RP28,RP29,RP30,RP31,RP32,RP33 RP1,RP2,RP3,RP4 RP5,RP6,RP7,RP8,RP9,RP10,RP11,RP12, RP13,RP14,RP15,RP16,RP17,RP18,RP19, RP20,RP21,RP22,RP23,RP24,RP25 C17,C116,C126,C145,C154,C184,C224,C23 4~C238,C239,C255,C257,C259,C273 C2,C3,C15,C16,C32,C33,C68,C71,C90,C91, C98,C99,C112,C125,C152 C159,C160,C165,C192,C201 C67,C70,C113,C157,C163,C171,C285 C246,C247 C155,C168,C274,C276,C277 C137 C268,C269,C270,C271,C272 M AIN BOARD DESCRIPTION ITEM QTY LOCATION 38 39 CER.CAP CER.CAP 50V 101 ±5% NPO 0603 50V 221 ±5% NPO 0603 6 1 C206,C208,C215,C217,C221,C223 C144 C6~C8,C24~C29,C40~C45,C48,C50,C53,C 54,C57,C61,C62,C66,C75,C78,C79,C82,C8 46 3,C86,C87,C94,C95,C108~C111,C115,C114 ,C121~C124,C146~C148,C283 6 C5,C31,C138,C139,C178,C180 1 C141 C173,C174,C175,C176,C177,C179,C181,C1 8 82 C4,C9~C14,C18~C23,C30,C34~C39,C46,C 47,C49,C51,C52,C55,C56,C58~C60,C63~C 65,C69,C72~C74,C76,C77,C80,C81,C84,C8 5,C88,C89,C92,C93,C96,C97,C100~C107,C 123 117~C120,C127~C136,C140,C149~C151,C1 53,C156,C158,C161,C162,C164,C166,C167, C169,C170,C172,C183,C185~C191,C193~C 197,C200,C225~C233,C248,C249,C252~C2 54,C256,C264~C267,C275,C278,C279,C284 40 CER.CAP 50V 103 ±10% 0603 41 42 CER.CAP CER.CAP 50V 27P ±5% NPO 0603 50V 56P ±5% NPO 0603 43 CER.CAP 50V 473 ±10% 0603 44 CER.CAP 50V104 ±20% 0603 45 45 46 47 48 49 50 51 52 53 52 52 55 56 CER.CAP CER.CAP CER.CAP CER.CAP CER.CAP FERRITE BEAD INDUCTOR IRON FERRITE BEAD DIODE TRANSISTOR IC IC IC IC 50V 821 ±10% 0603 10V 105 +80%-20% 0603 50V 122 ±10% 0603 50V 392 ±10% 0603 25V 224 +80%-20% 0603 FB 1.8UH ±10% 1608 FCM1608-601T02 1N4148 3906 24C16 SOP CS4360 SSOP CS5333 SSOP RT9164-33CG SOT-223 1 5 7 1 1 2 6 8 4 1 1 1 1 1 C199 C250,C251,C142,C262,C263 C1,C240,C241~C245 C198 C143 L19,L20 L11,L12,L14,L15,L16,L17 L1,L3,L4,L5,L6,L8,L9,L10 D2,D7~D9 Q1 U11 U18 U20 U8 57 IC DMN-8600 D0 BGA 1 U1 58 IC LP2995 SOP 1 U2 59 IC M13S128168A-6T TSOP 2 U3,U4 60 IC SN74HCT14PWR TSSOP 1 U6 61 IC MM1225XF SOP 1 U7 1 U9 1 1 1 62 IC SN74ALVCH16373 TSSOP 63 64 65 66 IC IC IC IC TSB41AB1PHP QFP PQ018EZ02ZP PQ025EZ01ZP SAA7115HL QFP 1 U12 U13 U14 U15 67 IC ADV7302AKST QFP 1 U16 69 CRYSTAL 24.576MHz 49-S 2 Y2,Y3 70 71 CRYSTAL PCB 13.50MHZ 49-S 2AB9915-1 1 1 Y1 61 MAIN BOARD DESCRIPTION ITEM 72 73 74 75 76 77 WAFER WAFER WAFER WAFER WAFER WAFER QTY 6P 2.0mm 10P 2.5mm 10P 2.0mm 20P 2.5mm 13P1.0mm 12P1.0mm 1 1 1 1 1 1 62 LOCATION CN1 CN4 CN3 J3 CN5 CN2 POWER BOARD DESCRIPTION ITEM QTY LOCATION 1 RESISTOR 1/16W 0Ω ±5% 1 R13 2 CARBON FILM RESISTOR 1/4W33Ω±5% 10 1 R5 3 CARBON FILM RESISTOR 1/4W330Ω±5% 10 1 R8 4 CARBON FILM RESISTOR 1/4W470Ω±5% 10 1 R15 5 CARBON FILM RESISTOR 1/4W1K±5% 10 2 R4,R20 6 CARBON FILM RESISTOR 1/4W4.7K±5% 10 1 R17 7 CARBON FILM RESISTOR 1/4W10K±5% 10 4 R3,R7,R19,R10 8 CARBON FILM RESISTOR 1/4W47K±5% 10 1 R9 9 CARBON FILM RESISTOR 1/4W1.2K±5% 10 1 R14 10 CARBON FILM RESISTOR 1/4W150Ω±5% 10 1 R21 11 CARBON FILM RESISTOR 1W0.33Ω±5% 12.5×7 1 R12 12 METAL FILM RESISTOR 1/4W10K±1% 10 2 R11,R18 13 METAL OXIDE FILM RESISTOR 2W68K±5% 15 1 R2 14 METAL OXIDE FILM RESISTOR 1/2W470K±5% 12.5 2 R1,R6 15 CER.CAP 50V 473 ±20% 2.5mm 1 C10 16 CARBON FILM RESISTOR 1/2W910K±5% 12.5×7 1 RV1 17 CER.CAP 50V 104 +80%-20% 5mm 7 C2,C7,C8,C12,C15,C16,C20 18 CER.CAP 1000V 103 +80%-20% 7.5mm 1 C4 19 CER.CAP 500V 101 ±10% 5mm 1 C17 20 CAP CT81 400V221±10% 10mm 2 C3,C14 21 CAP 400VAC 222 ±20% 10mm 1 C6 22 CAP 275V 104 ±20% 15mm 1 C13 23 CAP 50V 224 ±10% 5mm 1 C11 24 ELEC.CAP ELEC.CAP11 25V100U±20%6×12 2.5 5 CE1,CE2,CE12,CE14,CE16 25 ELEC.CAP ELEC.CAP110 25V470U±20%10×16 5 2 CE3,CE4 26 ELEC.CAP ELEC.CAP11 25V10U±10%5×11 2 1 CE7 27 ELEC.CAP ELEC.CAP110 25V22U±20%5×11 2 1 CE11 28 ELEC.CAP ELEC.CAP110 50V47U±20%6×12 2.5 1 CE13 29 ELEC.CAP ELEC.CAP110 16V220U±20%6×12 2.5 2 CE15,CE17 30 ELEC.CAP GZ 10V2200U±20%10×20 5 2 CE6,CE9 31 ELEC.CAP GZ 10V1000U±20%8×16 3.5 2 CE8,CE10 32 ELEC.CAP LS 400V100U±20%22×30 10 1 CE5 33 FERRITE BEAD FB 3 L1,L2,L4 34 INDUCTOR IRON 10UH 3A 5mm 2 L3,L5 35 TRANSFOMER BCK-28-0300 1 T1 36 DIODE 1N4007 4 D9,D10,D11,D12 63 POWER BOARD DESCRIPTION ITEM QTY LOCATION 37 DIODE 1N5401 2 D14,D15 38 DIODE HER105 4 D1,D6,D7,D8 39 DIODE HER107 1 D4 40 DIODE HER303 1 D2 41 DIODE BYW29E-200 TO-220 1 D5 42 ZENER 5.1V 1/2W 1 D13 43 DIODE MBR1060 TO-220 1 D3 44 TRANSISTOR 2N5401 1 Q4 45 TRANSISTOR 2N5551 2 Q3,Q5 46 MOSFET 1PP14N03L TO-220 2 Q1,Q2 47 IC LM431ACZ TO-92 1 IC3 48 IC PQ12RD21 TO-220 1 IC4 49 IC ICE 2A365 DIP 1 IC1 50 INDUCTOR IRON UT-20 40mH ±20% 10×13 1 LF1 51 THERM RESISTOR NTC SCK-104MS±20% 1 RT1 52 OPTOTRANSISTOR NEC2561 1 IC2 53 PCB 5AB9915-0 1 54 WAFER 2P 2.5mm 1 CN1 55 WAFER 5P 2.5mm 1 CN2 56 WAFER 5P 2.0mm 1 CN5 57 WAFER 10P 2.5mm 1 CN3 58 WAFER 4P 3.96mm 1 CN4 59 WAFER 2P 8.0mm 2# 1 BCN1 64 FUSE T2AL 250V 1 F1 66 RADIATOR 11×15×31 LFDR9905 2 D3,D5 64 KEY BOARD DESCRIPTION ITEM 1 RESISTOR 2 QTY 1/16W 0Ω ±5% LOCATION 1 R3 CARBON FILM RESISTOR 1/4W2.2Ω±5% 10 1 R1 3 CARBON FILM RESISTOR 1/4W10Ω±5% 10 2 R25,R10 4 CARBON FILM RESISTOR 1/6W100Ω±5% 7.5 1 R12 5 CARBON FILM RESISTOR 1/4W4.7K±5% 10 2 R15,R22 6 CARBON FILM RESISTOR 1/4W10K±5% 10 5 R4,R5,R6,R14,R24 7 CARBON FILM RESISTOR 1/4W220Ω±5% 10 2 R2,R11 8 CARBON FILM RESISTOR 1/4W2.7K±5% 10 3 R17,R18,R19 9 CER.CAP 50V 102 ±10% 2.5mm 2 C8,C17 10 CER.CAP 50V 103 ±10% 5mm 5 C3,C4,C5,C19,C21 11 CER.CAP 50V 104 ±20% 5mm 1 C2 12 CER.CAP 50V 20P ±10% NPO 2.5mm 2 C9,C10 13 CER.CAP 50V 30P ±5% NPO 2.5mm 2 C6,C7 14 ELEC.CAP ELEC.CAP11C 50V22U±20%6×7 2.5 1 C1 15 ELEC.CAP ELEC.CAP11C 16V4.7U±20%4×7 1.5 1 C11 16 ELEC.CAP ELEC.CAP11C 16V10U±20%4×7 1.5 1 C18 17 ELEC.CAP ELEC.CAP11C 16V47U±20%5×7 2 1 C20 18 DIODE 1N4148 6 D1~D6 19 LED 3R 4HD RED 1 LD1 20 LED 3B3HC 1 LD5 21 TRANSISTOR 9015C 1 Q2 22 TRANSISTOR S8050D 1 Q1 23 IC D16316 QFP 1 U1 24 CRYSTAL 32.768KHz 3×9 1 Y2 25 CRYSTAL 5.00MHZ 49-S 1 Y1 26 LED DISPLAYS HNV-06SC23 1 VFD1 27 TACT SWITCH 6×6×1 11 K1~K11 28 PCB 4AB9915-1 1 35 REMOTE RECEIVING HS0038B3V 1 65 U2 FRONT AV BOARD DESCRIPTION ITEM QTY 1 RESISTOR 1/16W 0Ω ±5% 1 2 WAFER AV3-SK-01 1 66 LOCATION CN1 DV BOARD DESCRIPTION ITEM QTY 1 RESISTOR 1/16W 0Ω ±5% 1 2 1394WAFER IEEE1394 4P/F DIP 1 67 LOCATION CN1 AV BOARD ITEM DESCRIPTION QTY 1 RESISTOR 1/16W 0Ω ±5% 11 2 3 4 5 RESISTOR RESISTOR RESISTOR RESISTOR 1/16W 10Ω ±5% 1/16W 22Ω ±5% 1/16W 75Ω ±5% 1/16W 220Ω ±5% 2 1 2 3 6 RESISTOR 1/16W 330Ω ±5% 11 7 8 9 10 RESISTOR RESISTOR RESISTOR RESISTOR 1/16W 470Ω ±5% 1/16W 1K ±5% 1/16W 2.2K ±5% 1/16W 3.3K ±5% 5 4 4 4 11 RESISTOR 1/16W 4.7K ±5% 14 12 RESISTOR 1/16W 6.8K ±5% 10 13 14 15 16 17 18 19 20 21 22 RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR ELEC.CAP 1/16W 10K ±5% 1/16W 15K ±5% 1/16W 24K±5% 1/16W 22K ±5% 1/16W 33K ±5% 1/16W 47K ±5% 1/16W 100K ±5% 1/16W 100Ω ±5% 1/16W 30K ±5% ELEC.CAP11 10V220U±20%6×12 2.5 8 4 6 1 2 6 1 1 1 6 23 ELEC.CAP ELEC.CAP11 16V10U±20%5×11 2 13 24 25 26 27 28 29 30 ELEC.CAP ELEC.CAP ELEC.CAP ELEC.CAP CER.CAP CER.CAP CER.CAP ELEC.CAP11 16V47U±20%5×11 2 ELEC.CAP11 16V100U±20%6×12 2.5 ELEC.CAP11 16V4.7U±20%5×11 2 ELEC.CAP11 50V3.3U±20%5×11 2 50V 33P ±5% NPO 0603 50V 101 ±5% NPO 0603 50V 151 ±5% NPO 0603 5 2 7 1 2 1 6 31 CER.CAP 50V 102 ±10% 0603 15 32 33 34 35 CER.CAP CER.CAP CER.CAP CER.CAP 50V 152 ±10% 0603 50V 103 ±10% 0603 50V 56P ±5% NPO 0603 50V 471 ±10% 0603 2 5 2 2 36 CER.CAP 50V104 ±20% 0603 15 37 CER.CAP 25V 474 +80%-20% 0603 2 38 FERRITE BEAD FCM1608K-221T05 14 39 40 FERRITE BEAD ZENER FCM1608-601T02 6.2V 1/2W 2 2 68 LOCATION R11,R14,R22,R33,R41,R55,R99,R108,R113, R140,R145 R71,R66 R23 R146,R147 R1,R8,R63 R48,R59,R36,R43,R76,R83,R88,R95,R103, R110,R115 R37,R44,R104,R111,R116 R26,R53,R56,R141 R18,R68,R72,R132 R119~R122 R24,R28,R46,R47,R57,R58,R74,R75,R81,R 82,R86,R87,R93,R94 R32,R35,R39,R42,R97,R102,R106,R109,R1 12,R114 R4,R5,R15,R19,R20,R69,R117,R118 R2,R3,R13,R17 R45,R51,R73,R78,R85,R90 R60 R129,R131 R49,R62,R77,R84,R89,R96 R52 R123 R67 C18,C25,C26,C60,C61,C63 C11,C15,C31,C36,C45,C49,C53,C57,C73,C 75,C85,C88,C90 C1,C7,C10,C40,C42 C12,C39 C3~C6,C14,C16,C17 C71 C79,C81 C76 C30,C35,C44,C48,C52,C56 C20,C32,C33,C37,C38,C46,C47,C50,C51,C 54,C55,C58,C59,C83,C84 C86,C91 C8,C13,C19,C34,C89 C77,C78 C87,C92 C2,C9,C22,C27,C41,C43,C62,C64,C65,C66, C67,C68,C69,C72,C74 C80,C82 R31,R34,R38,R98,R100,R101,R105,R107,R 6,R135,R139,R142,R143,R144 FB1,FB2 D1,D3 AV BOARD ITEM 41 DIODE 42 TRANSISTOR 43 TRANSISTOR 44 IC 45 IC 46 IC 47 CRYSTAL 48 TUNER 49 OPTICAL OUTPUT 50 PCB 51 SCARTWAFER 52 WAFER 53 WAFER 54 WAFER 55 WAFER 56 WAFER 57 WAFER 58 WAFER DESCRIPTION QTY 13 15 4 1 3 1 1 1 1 1 1 2 1 1 1 1 1 1 1N4148 3904 3906 ELEC.CAP4052BCN DIP RC4558D SOP MSP3415G QFP 18.432MHz 49-S JS-6B2/L121-D5 GP1F32T 7AB9915-2 SCART-01 CS-09 AV2-8.4-6G AV12-8.4--2G-2 5P 2.5mm 7P 2.0mm 13P1.0mm 12P1.0mm 69 LOCATION D2,D4~D11,D14~D17 Q2~Q5,Q8,Q11~Q20 Q1,Q6,Q7,Q10 U1 U3~U5 U6 Y1 TUN1 OP1 S3 S2,S4 S1 S5 CN5 CN3 CN2 CN1 BBK ELECTRONICS CORP., LTD. 23 Bubugao Road, Wusha, Chang'an, Dongguan, China http: //www.gdbbk.com ">

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Key features
- Record all AV input signals to DVD
- High capacity DVD player
- Multiple input & output signals
- Multiple recording qualities & methods
- Convenient menu operation
- Standby function
- Upgrading function
- Play DVD, DVD+R, DVD+RW, VCD, SVCD, CD-DA and MP3
Frequently asked questions
It can play DVD, DVD+R, DVD+RW, VCD, SVCD, CD-DA and MP3.
It can record DVD+R and DVD+RW.
The unit provides 4 kinds of recording qualities, each with different resolution and recording time.
The unit offers three kinds of recording methods: ordinary manual recording, time recording, OTR one-touch recording and DV recording.