LG U8120 mobile phone Service Manual

Below you will find brief information for mobile phone U8120. The U8120 is a GSM and WCDMA dual-mode mobile phone with a camera, a keypad, a display and other features. It is designed to be used for communication and multimedia purposes.

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P/N : MMBD0035201 Date: july, 2004 / Issue 1.0

Service Manual

U8120

1. INTRODUCTION .............................. 6

1.1 Purpose................................................... 6

1.2 Regulatory Information............................ 6

1.3 Abbreviations .......................................... 8

2. PERFORMANCE............................ 10

2.1 System Overview .................................. 10

2.2 Usable environment .............................. 11

2.3 Radio Performance ............................... 11

2.4 Current Consumption............................ 17

2.5 RSSI...................................................... 17

2.6 Battery Bar ............................................ 17

2.7 Sound Pressure Level........................... 18

2.8 Charging ............................................... 19

3. Technical Brief .............................. 20

3.1 Digital Baseband(DBB)&

Multimedia Processor ........................... 20

3.1.1 General Description ........................ 20

3.1.2 Hardware Architecture .................... 21

3.1.3 External memory interface .............. 25

3.1.4 RF Interface .................................... 26

3.1.5 SIM Interface .................................. 28

3.1.6 UART Interface ............................... 28

3.1.7 GPIO (General Purpose Input/Output) map ................................................. 29

3.1.8 USB ................................................ 31

3.1.9 IrDA Interface.................................. 33

3.1.10 Folder ON/OFF Operation ............ 34

3.1.11 Power On Sequence..................... 35

3.1.12 Key Pad ........................................ 36

3.2 GAM Hardware Subsystem .................. 37

3.2.1 General Description ........................ 37

3.2.2 Block Description ............................ 38

3.2.3 Camera & Camera FPC Interface... 40

3.2.4 Camera Position Detection ............. 42

3.2.5 Camera Regulator .......................... 42

3.2.6 Display & LCD FPC Interface ......... 43

3.2.7 Main LCD Backlight Illumination ..... 46

3.2.8 Sub LCD Backlight Illumination ...... 47

3.2.9 Keypad Illumination ........................ 48

3.2.10 Camera Flash Illumination ............ 49

3.3 LCD Module .......................................... 50

3.4 Analog Baseband (ABB) Processor...... 51

3.4.1 Overview of Audio path................... 51

3.4.2 Audio Signal Processing &

Interface .......................................... 52

3.4.3 Audio Mode..................................... 54

3.4.4 Voice Call........................................ 55

3.4.5 MIDI (Ring Tone Play) .................... 59

3.4.6 MP3 (Audio Player)......................... 60

3.4.7 Video Telephony ............................. 61

3.4.8 Audio Main Component .................. 62

3.4.9 GPADC(General Purpose ADC) and

AUTOADC2 .................................... 64

3.4.10 Charger control ............................. 65

3.4.11 Fuel Gauge ................................... 66

3.4.12 Battery Temperature

Measurement ................................ 67

3.4.13 Charging Part................................ 68

3.5 Voltage Regulation ............................... 71

3.5.1 Internal Regulation.......................... 71

3.5.2 External Regulation ........................ 71

3.6 General Description .............................. 73

3.7 GSM Mode............................................ 75

3.7.1 Receiver.......................................... 75

3.7.2 Transmitter...................................... 80

3.8 WCDMA Mode ...................................... 82

3.8.1 Receiver.......................................... 82

- 3 -

Table Of Contents

3.8.2 Transmitter...................................... 85

3.8.3 Frequency Generation .................... 89

4. TROUBLE SHOOTING .................. 91

4.1 Power ON Trouble ................................ 91

4.2 USB Trouble ......................................... 93

4.3 SIM Detect Trouble ............................... 94

4.4 Keypad Trouble..................................... 95

4.5 Camera Trouble .................................... 96

4.6 Main LCD Trouble................................. 98

4.7 Sub LCD Trouble .................................. 99

4.8 Keypad Backlight Trouble ................... 100

4.9 Folder ON/OFF Trouble ...................... 102

4.10 Camera Detection Trouble................ 104

4.11 Camera Flash Trouble ...................... 106

4.12 Audio Trouble Shooting .................... 108

4.13 Charger Trouble Shooting................. 123

4.14 RF Component.................................. 126

4.15 Procedure to check ........................... 128

4.16 Checking Common

Power Source Block.......................... 129

4.16.1 Step 1 ......................................... 130

4.16.2 Step 2 ......................................... 131

4.16.3 Step 3 ......................................... 132

4.16.4 Step 4 ......................................... 133

4.16.5 Checking Regular Part................ 136

4.17 Checking VCXO Block ...................... 137

4.18 Checking Ant. SW Module Block ...... 142

4.19 Checking Antenna Switch Block input logic.......................................... 143

4.19.1 Mode Logic by TP Command ..... 143

4.19.2 Checking Switch Block power source .............................. 145

4.20 Checking WCDMA Block .................. 151

4.20.1 Checking ..................................... 152

4.20.2 Checking Ant. SW module .......... 152

4.20.3 Checking Control Signal ............. 152

4.20.4 Checking RF TX Level ................ 155

4.20.5 Checking PAM Block .................. 158

4.20.6 Checking RX I,Q ......................... 162

4.20.7 Checking RX Level ..................... 164

4.21 Checking GSM Block ........................ 166

4.21.1 Checking Regulator Circuit ........ 167

4.21.2 Checking VCXO Block ............... 167

4.21.3 Checking Ant. SW Module .......... 167

4.21.4 Checking Control Signal ............. 168

4.21.5 Checking RF Tx Path.................. 170

4.21.6 Checking RF Rx Path ................. 175

5. BLOCK DIAGRAM ....................... 180

5.1 GSM & WCDMA RF Block.................. 180

5.2 Interface Diagram ............................... 182

5.3 Detailed Interface Signal..................... 184

6. DISASSEMBLY INSTRUCTION... 186

7. DOWNLOAD ................................ 194

8. CALIBRATION ............................. 207

8.1 General Description ............................ 207

8.2 XCALMON Environment ..................... 207

8.2.1 H/W Environment.......................... 207

8.2.2 S/W Environment .......................... 207

8.2.3 Configuration Diagram of

Calibration Environment................ 207

8.3 Calibration Explanation ....................... 208

8.3.1 Overview ....................................... 208

8.3.2 Calibration Items ........................... 208

8.3.3 EGSM 900 Calibration Items ........ 209

- 4 -

8.3.4 DCS 1800 Calibration Items ......... 214

8.3.5 WCDMA Calibration Items ............ 217

8.3.6 Baseband Calibration Item ........... 225

8.4 Program Operation ............................. 226

8.4.1 XCALMON Program Overview ..... 226

8.4.2 XCALMON Icon Description ......... 227

8.4.3 Calibration Procedure ................... 230

8.4.4 Calibration Result Message .......... 232

9. CIRCUIT DIAGRAM ..................... 235

10. PCB LAYOUT ............................. 244

11. EXPLODED VIEW &

REPLACEMENT PART LIST ..... 248

11.1 EXPLODED VIEW ............................ 248

11.2 Replacement Parts

<Mechanic component>.................... 249

<Main component> ........................... 252

11.3 Accessory ......................................... 271

Table Of Contents

- 5 -

1. INTRODUCTION

1. INTRODUCTION

1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the features of this model.

1.2 Regulatory Information

A. Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services.

System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it. The manufacturer will not be responsible for any charges that result from such unauthorized use.

B. Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.

C. Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the phones or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.

D. Maintenance Limitations

Maintenance limitations on the phones must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.

Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.

- 6 -

1. INTRODUCTION

E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. In accordance with these agencies, you may be required to provide information such as the following to the end user.

F. Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.

G. Interference and Attenuation

A phone may interfere with sensitive laboratory equipment, medical equipment, etc.

Interference from unsuppressed engines or electric motors may cause problems.

H. Electrostatic Sensitive Devices

ATTENTION

Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.

Following information is ESD handling:

• Service personnel should ground themselves by using a wrist strap when exchange system boards.

• When repairs are made to a system board, they should spread the floor with anti-static mat which is also grounded.

• Use a suitable, grounded soldering iron.

• Keep sensitive parts in these protective packages until these are used.

• When returning system boards or parts like EEPROM to the factory, use the protective package as described.

- 7 -

1. INTRODUCTION

1.3 Abbreviations

For the purposes of this manual, following abbreviations apply:

GPRS

GSM

IPUI

LCD

LDO

LED

OPLL

PAM

PCB

PGA

PLL

DSP

DTC

EEPROM

ESD

FPCB

GMSK

GPIB

APC

BER

CC-CV

CLA

DAC

DCS dBm

Automatic Power Control

Baseband

Bit Error Ratio

Constant Current – Constant Voltage

Cigar Lighter Adapter

Digital to Analog Converter

Digital Communication System dB relative to 1 milliwatt

Digital Signal Processing

DeskTop Charger

Electrical Erasable Programmable Read-Only Memory

Electroluminescence

Electrostatic Discharge

Flexible Printed Circuit Board

Gaussian Minimum Shift Keying

General Purpose Interface Bus

General Packet Radio Service

Global System for Mobile Communications

International Portable User Identity

Intermediate Frequency

Liquid Crystal Display

Low Drop Output

Light Emitting Diode

Offset Phase Locked Loop

Power Amplifier Module

Printed Circuit Board

Programmable Gain Amplifier

Phase Locked Loop

- 8 -

PSTN

RLR

RMS

RTC

SAW

SIM

SLR

SRAM

UMTS

Public Switched Telephone Network

Radio Frequency

Receiving Loudness Rating

Root Mean Square

Real Time Clock

Surface Acoustic Wave

Subscriber Identity Module

Sending Loudness Rating

Static Random Access Memory

Universal Mobile Telephony System

1. INTRODUCTION

- 9 -

2. PERFORMANCE

Item

Shape

Size

Weight

Power

Talk Time

Standby Time

Antenna

LCD

Main LCD BL

Sub LCD BL

Vibrator

LED Indicator

C-MIC

Receiver

Earphone Jack

SIM Socket

Volume Key

Voice Key

I/O Connect

2. PERFORMANCE

2.1 System Overview

Specification

GSM900/1 800 & WCDMA Folder- Dual Mode Handset

49.5 x 95.7 x 22.5 mm

120g (with Battery)

4.0V > 1200mAh Li-Ion

Over 140 Min (WCDMA, Tx=12 dBm, Voice)

Over 180 Min (GSM, Tx=Max, Voice)

Over 120 hrs (WCDMA, DRX=1.28)

Over 1 50 hrs (GSM, Paging period=9)

Fixed Type (Fixed Screw)

176 x 220 Pixel

White LED Back Light

7-color LED

Yes (Coin Type)

7-color(Sub LCD BL)

Yes

Yes (3.0V/1.8V)

Push Type(+,-)

Push Type (Memo)

24 Pin

- 10 -

2. PERFORMANCE

2.2 Usable environment

1) Environment

Item

Voltage

Size

Storage

Humidity

Spec.

4.0 (Typ), 3.4 (Min), (Shut Down: 3.2)

-20 ~ + 60

-30 ~ + 85 max. 85

2) Environment(Accessory)

Item

Power

* CLA: 12~24V(DC)

Spec.

Available power

Min

100

Typ.

220

Max

240

Unit

Vac

Unit

°C

2.3 Radio Performance

1) Transmitter -GSM Mode

No

Conducted

Spurious

Emission

Item

MS allocated

Channel

Idle Mode

100k ~ 1GHz

GSM

1G ~ 12.75GHz

-39dBm

-33dBm

9k ~ 1GHz

DCS

1G ~ 1710MHz

-39dBm

-33dBm

1710M ~ 1785MHz -39dBm

1785M ~ 12.75GHz

-33dBm

100k ~ 880MHz

880M ~ 915MHz

915M ~ 1000Mz

1G ~ 1.71GHz

-60dBm

-62dBm

-60dBm

-50dBm

100k ~ 880MHz

880M ~ 915MHz

915M ~ 1000MHz

1G ~ 1.71GHz

-60dBm

-62dBm

-60dBm

-50dBm

1.71G ~ 1.785GHz

-56dBm 1.71G ~ 1.785GHz

-56dBm

1.785G ~ 12.75GHz

-50dBm 1.785G ~ 12.75GHz

-50dBm

- 11 -

2. PERFORMANCE

Radiated

Spurious

Emission

Item

MS allocated

Channel

Idle Mode

Frequency Error

30M ~ 1GHz

1G ~ 4GHz

GSM

30M ~ 880MHz

880M ~ 915MHz

915M ~ 1000Mz

1G ~ 1.71GHz

-36dBm

-30dBm

30M ~ 1GHz

DCS

1G ~ 1710MHz

-36dBm

-30dBm

1710M ~ 1785MHz -36dBm

1785M ~ 4GHz -30dBm

-57dBm 30M ~ 880MHz

-59dBm 880M ~ 915MHz

-57dBm 915M ~ 1000MHz

-47dBm 1G ~ 1.71GHz

-57dBm

-59dBm

-57dBm

-47dBm

1.71G ~ 1.785GHz

-53dBm 1.71G ~ 1.785GHz

-53dBm

1.785G ~ 4GHz -47dBm 1.785G ~ 4GHz -47dBm

±0.1ppm

±5(RMS)

±0.1ppm

±5(RMS)

Phase Error

Frequency Error Under

Multipath and Interference

Condition

Output RF

Spectrum

Due to

±20(PEAK) ±20(PEAK)

3dB below reference sensitivity 3dB below reference sensitivity

RA250: ±200Hz

HT100: ±100Hz

RA250: ±250Hz

HT100: ±250Hz

TU50: ±100Hz

TU3: ±150Hz

0 ~ 100kHz

200kHz

250kHz

400kHz modulation 600 ~ 1800kHz

1800 ~ 3000kHz

3000 ~ 6000kHz

+0.5dB

-30dB

-33dB

-60dB

TU50: ±150Hz

TU1.5: ±200Hz

0 ~ 100kHz

200kHz

250kHz

400kHz

-66dB 600 ~ 1800kHz

-69dB 1800 ~ 6000kHz

+0.5dB

-30dB

-31dB

-33dB

-60dB

-73dB

Due to

Switching transient

≥6000kHz

400kHz

600kHz

1200kHz

1800kHz

-71dB ≥6000kHz

-77dB

-19dB 400kHz

-21dB 600kHz

-21dB 1200kHz

-24dB 1800kHz

-22dB

-24dB

-27dB

- 12 -

2. PERFORMANCE

Item

Intermodulation attenuation

Transmitter Output Power

Burst timing

GSM

–

DCS

Frequency offset 800kHz

Intermodulation product should be Less than 55dB below the level of Wanted signal

Power control Power Tolerance Power control Power Tolerance

Level (dBm) (dB) Level (dBm) (dB)

±3

9 25

1023

Mask IN

±3

±5

±3

20±3

±3

±4

1010±4

11 8 ±4

Mask IN

±4

±5

0±5

- 13 -

2. PERFORMANCE

2) Transmitter-WCDMA Mode

Maximum Output Power

Frequency Error

Item

Open Loop Power control in uplink

Specification

Class3: +24dBm(+1/-3dB)

Class4: +21dBm(±2dB)

±0.1ppm

±9dB@normal, ±12dB@extreme

Adjust output(TPC command) cmd 1dB 2dB 3dB

+1 +0.5/1.5 +1/3 +1.5/4.5

4 Inner Loop Power control in uplink 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5

-1 -0.5/-1.5 -1/-3 -1.5/-4.5

group(10equal command group)

+1 +8/+12 +16/+24

5 Minimum Output Power -50dBm(3.84MHz)

Qin/Qout:DPCCH quality levels

6 Out-of-synchronization handling of output power Toff@DPCCH/lor:-22->-28dB

Ton@DPCCH/lor:-24->-18dB

7 Transmit OFF Power -56dBm(3.84M)

±25us

8 Transmit ON/OFF Time Mask

PRACH, CPCH, uplink compressed mode

±25us

9 Change of TFC

10Power setting in uplink compressed

Occupied Bandwidth(OBW)

Spectrum emission Mask power varies according to the data rate

DTX: DPCH off

(minimize interference between UE)

±3dB(after 14slots transmission gap)

5MHz(99%)

-35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz, 30k

-35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz, 1M

-39-10*(∆f-7.5)dBc@∆f=7.5~8.5MHz, 1M

-49 dBc@∆f=8.5~12.5MHz, 1M

- 14 -

2. PERFORMANCE

No Item

13 Adjacent Channel Leakage Ratio(ACLR)

Spurious Emissions

*: additional requirement

15 Transmit Intermodulation

16 Error Vector Magnitude(EVM)

17 Transmit OFF Power

Specification

33dB@5MHz, ACP>-50dBm

43dB@10MHz, ACP>-50dBm

-36dBm@f=9~150KHz, 1k BW

-36dBm@f=150KHz~30MHz, 10k

-36dBm@f=30~1000MHz, 100k

-30dBm@f=1~12.75GHz, 1M

-41dBm*@1893.5~1919.6MHz, 300k

-67dBm*@925~935MHz, 100k

-79dBm*@935~960MHz, 100k

-71dBm*@1805~1880MHz, 100k

-31dBc@5MHz, Interferer -40dBc

-41dBc@10MHz, Interferer -40dBc

17.5% (>-20dBm)

(@12.2k, 1DPDCH+1DPCCH)

-15dB@SF=4, 768kbps, multi-code transmission

3)Receiver - GSM Mode

Item

Sensitivity (TCH/FS Class II)

Co-Channel Rejection

(TCH/FS Class II, RBER, TUhigh/FH)

3 Adjacent Channel

Rejection

200kHz

400kHz

Intermodulation Rejection

Blocking Response

(TCH/FS Class II, RBER)

GSM

-105dBm

C/Ic=7dB

DCS

-105dBm

C/Ic=7dB

C/Ia1=-12dB

C/Ia2=-44dB

Wanted Signal: -98dBm

1’st interferer: -44dBm

C/Ia1=-12dB

C/Ia2=-44dB

Wanted Signal: -96dBm

1’st interferer: -44dBm

2’st interferer: -45dBm

Wanted Signal: -101dBm

2’st interferer: -44dBm

Wanted Signal: -101dBm

Unwanted Signal: Depend on freq. Unwanted Signal: Depend on freq.

- 15 -

2. PERFORMANCE

4) Receiver - WCDMA Mode

No Item

18 Reference Sensivitivity Level

19 Maximum Input Level

20Adjacent Channel Selectivity(ACS)

21 In-band Blocking

22 Out-band Blocking

23 Spurious Response

24 Intermodulation Characteristic

25 Spurious Emissions

- 16 -

Specification

-106.7dBm(3.84M)

-25dBm(3.84MHz)

-44dBm/3.84MHz(DPCH_Ec)

UE@+20dBm output power(class3)

33dB

UE@+20dBm output power(class3)

-56dBm/3.84MHz@10MHz

UE@+20dBm output power(class3)

-44dBm/3.84MHz@15MHz

UE@+20dBm output power(class3)

-44dBm/3.84MHz@f=2050~2095 &

2185~2230MHz, band a)

UE@+20dBm output power(class3)

-30dBm/3.84MHz@f=2025~2050 &

2230~2255MHz, band a)

UE@+20dBm output power(class3)

-15dBm/3.84MHz@f=1~2025 &

2255~12500MHz, band a)

UE@+20dBm output power(class3)

-44dBm CW

UE@+20dBm output power(class3)

-46dBm CW@10MHz &

-46dBm/3.84MHz@20MHz

UE@+20dBm output power(class3)

-57dBm@f=9KHz~1GHz, 100k BW

-47dBm@f=1~12.75GHz, 1M

-60dBm@f=1920~1980MHz, 3.84MHz

-60dBm@f=2110~2170MHz, 3.84MHz

2. PERFORMANCE

2.4 Current Consumption

(VT test : Speaker off, LCD backlight On)

WCDMA

GSM

Stand by

120Hours=10mA

(DRX=1.28)

150Hours=8mA

(paging=9period)

Voice Call

140Min=514mA

(Tx=12dBm)

180Min=400mA

(Tx=Max)

100Min=720mA

(Tx=12dBm)

2.5 RSSI

TBD

GSM

BAR 4

→ 3

BAR 3

→ 2

-91 ±2dBm

-96 ±2dBm

BAR 2

→ 1

-101 ±2dBm

BAR 1

→ 0-10

WCDMA(TBD)

2.6 Battery Bar

Indication

BAR 4

→ 3 (68%)

BAR 3

→ 2 (47%)

BAR 2

→ 1 (26%)

BAR 1

→ Icon Blinking (5%)

Low voltage, warning message

Power OFF

- 17 -

Voltage

3.87 ±0.03V

3.77 ±0.03V

3.72 ±0.03V

3.50 ±0.03V

3.50 ±0.03V(Talk: 1min. interval) -5%

3.46 ±0.03V(Standby: 3min. Inverval) -3%

3.10 ±0.03V

↓ (WCDMA Talk)

3.20 ±0.03V

↓ (else)

2. PERFORMANCE

2.7 Sound Pressure Level

Test Item

Sending Loudness Rating (SLR)

Receiving Loudness Rating (RLR)

Side Tone Masking Rating (STMR)

Echo Loss (EL)

Sending Distortion (SD)

Receiving Distortion (RD)

Idle Noise-Sending (INS)

Idle Noise-Receiving (INR)

Sending Loudness Rating (SLR)

10Receiving Loudness Rating (RLR)

Side Tone Masking Rating (STMR)

Echo Loss (EL)

Sending Distortion (SD)

Receiving Distortion (RD)

Idle Noise-Sending (INS)

16 Idle Noise-Receiving (INR)

TDMA NOISE

–.GSM: Power Level: 5

DCS: Power Level: 0

(Cell Power: -90 ~ -105dBm)

–.Acoustic(Max Vol.)

MS/HEADSET SLR: 8±3dB

MS/HEADSET RLR: -13±1dB/-15dB

Headset

(SLR/RLR: mid-Value Setting)

GSM

DCS

GSM

DCS

SEND

REV.

SEND

REV.

SEND

REV.

SEND

REV.

HEAD

SET

Specification

NOM

MAX

NOM

MAX

NOM

MAX

NOM

MAX

8±3dB

-1±3dB

-13±1dB

17dB over

40dB over

NOM

MAX refer to TABLE 30.3

refer to TABLE 30.4

-64dBm0p under

NOM

MAX

NOM

MAX

-47dBPA under

-36dBPA under

8±3dB

NOM

MAX

NOM

MAX

-1±3dB

-12±3dB

25dB over

NOM

MAX

40dB over refer to TABLE 30.3

refer to TABLE 30.4

NOM

MAX

NOM

MAX

-55dBm0p under

-45dBPA under

-40dBPA under

-62dBm under

- 18 -

2. PERFORMANCE

2.8 Charging

• Normal mode: Complete Voltage: 4.2V

Charging Current: 600mA

• Await mode: In case of During a Call, should be kept 3.9V

(GSM: It should be kept 3.9V in all power level

WCDMA: It will not be kept 3.9V in some power level)

Extend await mode: At Charging prohibited temperature(-20C under or 60C over)

(GSM: It should be kept 3.7V in all power level

WCDMA: It will not be kept 3.7V in some power level)

- 19 -

3. TECHNICAL BRIEF

3. Technical Brief

3.1 Digital Baseband(DBB) & Multimedia Processor

3.1.1 General Description

A. Features

• CPU ARM946 running at 104 MHz

- 32 kB Instruction Cache, 16 kB Data Cache, 128 kB Instruction TCM and 128 kB Data TCM

- 8 channel DMAC

• DSP C55x (LEAD3) Megastar (MGS3_2.0B) running at 170 MHz

- 144 kWord ROM, 32 kWord DARAM, 32 kWord SARAM

- 7 channel DMAC

- Dedicated API channel to DSP memory (not locked up to other DMA channels)

• UMTS Access

- Support for WCDMA/GSM Dual Mode

- GSM/GPRS network signaling (from Layer 1 to 3)

- WCDMA Ciphering and Integrity

- High Speed Serial Link (HSSL) to the WCDMA Modem (at Layer 1)

- GSM AMR

- Multislot Class 8

- HSCSD 14.4 kb/s

• MMI

- Keypad Interface

- Tone Generator Interface

- Camera Data and Programmable Display Interfaces

- Enhanced graphics support for QCIF display

• Operation and Services

- I 2 C™ Interface

- SIM Interfaces

- General Purpose I/O (GPIO) Interface

- External Memory Interface that supports FLASH, SRAM and PSRAM

- JTAG

- RTC

- ETM (in Prototype Package)

• Data Communication

- IrDA ® (SIR)

- UARTs (ACB, EDB (RS232))

- Slave USB

• Package

- 12 by 12 mm 289 pin FPBGA Production Package

- 20 -

3. TECHNICAL BRIEF

3.1.2 Hardware Architecture

The hardware structure is delivered as five separate hardware macros to the top-level design, also depicted in Figure.

Figure. Simplified Block Diagram

- 21 -

3. TECHNICAL BRIEF

A. Block Diagram

Figure. Simplified Block Diagram

B. CPU Hardware Subsystem

The CPU subsystem incorporates:

• CPU Sub chip

• Backplane

• JTAG

• DMA Controller

• System Buffer RAM

• Boot ROM

• External Memory Interface (EMIF) for connection to external SRAM and Flash memories.

The bus architecture is built on the ARM AMBA standard with multi-layer AHB (Advanced High-speed

Bus) and APB (Advanced Peripheral Bus) for the peripheral buses.

There are two AHB busses, the CPU AHB and the DMA AHB.

Clocks to the CPU subsystem are distributed from the system control (SYSCON) backplane clocking.

The reset lines are all asynchronously asserted low and synchronously negated high.

The CPU subsystem has separate clocking and reset for the ARM946, AHB system, EMIF and DMAC.

- 22 -

3. TECHNICAL BRIEF

C. Peripheral Hardware Subsystem

There are 29 peripherals within the peripheral hardware subsystem. With the exception of the USB, all hardware peripheral blocks are APB slave peripherals. From an architecture-hierarchy perspective, the SYSCON block is an APB slave on the slow APB bridge, but resides at the top level of the ASIC.

The APB provides a simple interface to support low-performance peripherals.

Within the peripheral subsystem, there are four separate APB busses with AHB to APB (AHB2APB) bridges to the multi-layer AHB.

D. DSP Hardware Subsystem

The DSP subsystem provides support for processor intensive activity, such as voice coding and multimedia application support. The DSP subsystem includes the standard C55xTM Core (LEAD3) from Texas Instruments with associated memory system and peripherals.

E. GAM Hardware Subsystem

The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display. GAM also provides support for the camera module. The visual data could be graphics, still images or video.

The GAM subsystem consists of five modules:

• GRAM - graphics memory (160 kB).

• GAMCON . GAM controller.

• GRAPHCON . graphics controller.

• PDI/SSI - programmable display interface for parallel/serial displays.

• CDI - camera data interface.

F. GSM Hardware Subsystem

The GSM subsystem is a stand-alone sub-chip incorporating GSM modem and interface to GSM radio together with memory control (MEMSYS) and internal RAM (IRAM).

The hardware peripheral blocks are RXIF, FCHDET, CRYPTO, EQU, NODI, 4 x CHD, GPRS

CRYPTO, GPRS CRC24, CHE, DIRMOD, CLKCON, SERCON, TIMGEN, MEMSYS and IRAM.

The peripherals are accessible to the AHB (CPU-only) by an asynchronous I/O bridge.

The dual port IRAM is accessible to the AHB (CPU and DMA) by a synchronous AHB slave interface.

- 23 -

3. TECHNICAL BRIEF

G. System Control Subsystem

The system controller subsystem (SYSCON) is primarily responsible for generating clock signals and distributing the clock and reset signals within the ASIC and certain external devices. The GSM core,

GAM and DSP subsystems include their own system controllers that are sourced from SYSCON.

SYSCON consists of analog and digital PLL clocks and a clock squarer. The block is a slave peripheral on the slow APB bus under control of the CPU.

The programming of SYSCON controls the fundamental modes of operation within the ASIC.

Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control registers. SYSCON also controls the requesting protocol through which different sub-blocks in

Ericsson DB 20000 can request clocks derived from the system clock.

The system controller also stores the chip-ID number in a read only register.

- 24 -

3. TECHNICAL BRIEF

3.1.3 External memory interface

There are four independent chip selects (CS0, CS1, CS2, CS3) provided for external memories and each has an address range of 256 Mb.

RF calibration data, Audio parameters and battery calibration data etc are stored in flash memory area.

A. U8100 & U8120

• 384Mb flash memory + 64Mb PSRAM

• 4-CS(Chip Select) are used

Device Part Name

MCP

FLASH

PSRAM

S71WS256HC0BAW00

Am29BDS128HD9VKI

S71WS256HC0BAW00

Interface Spec.

Maker

Async

Read Access Time

Page Burst

AMD

56 ns

70 ns

–

20 ns

13.5 ns at 54MHz

–

Write

Access

Time

56 ns

70 ns

Table External memory interface for U8100 & U8120

B. U8120

• 512Mb flash memory + 64Mb PSRAM

• 3-CS(Chip Select) are used

Device

MCP

FLASH

PSRAM

Part Name

RD38F4050L0YTQ0

NZ48F4000L0YBQ0

RD38F4050L0YTQ0

Interface Spec.

Maker

Async

Read Access Time

Page Burst

Intel

85 ns

25 ns

14 ns at 54MHz

10 ns at 66MHz

Write

Access

Time

85 ns

Table External memory interface for U8120

- 25 -

3. TECHNICAL BRIEF

3.1.4 RF Interface

A. MARITA Interface

Marita controls GSM RF part using these signals through GSM RF chip-Ingela.

• RFCLK, RFDAT, RFSTR : Control signals for Ingela

• TXON, RXON

• PCTL

: Control signals for TX and RX part of Ingela

: Control signal for GSM TX PAM

• BANDSEL0: Band selection signal for GSM or DCS

• ANTSW[0:3] : Control signals for antenna switch

• DCLK, IDATA, QDATA : GSM/DCS RX Data

• DIRMOD[A:D] : GSM/DCS TX Data

Figure. Schematic of MARITA RF Interface

B. WANDA Interface

Wanda controls WCDMA RF part using these signals through W-CDMA RF chip-Wopy & Wivi.

Figure. Schematic of WANDA RF Interface

- 26 -

3. TECHNICAL BRIEF

Figure. Schematic of WANDA RF Interface

• RADIO_CLK, RADIO_DAT, RADIO_STR : Control signals for Wivi & Wopy

• RXIA, RXIB, RXQA, RXQB : WCDMA RX Data

• TXIA, TXIB, TXQA, TXQB

• HSSLRX_D, HSSLRX_CLK

• HSSLTX_D, HSSLTX_CLK

: WCDMA TX Data

: Marita & Wanda Communication Signal

- 27 -

3. TECHNICAL BRIEF

3.1.5 SIM Interface

SIMDAT0, SIMCLK0, SIMRST0 ports are used to communicate DBB(MARITA) with ABB(VINCENNE) and filter.

SIM (Interface between DBB and ABB)

SIMDAT0SIM card bidirectional data line

SIMCLK0SIM card reference clock

SIMRST0SIM card async/sync reset

Table. SIM Interface

SIMVCC

VDIG

10K

SIMDAT0

SIMCLK0

SIMRST0

SDAT SIMDAT

SCLK SIMCLK

SRST SIM RST

Figure. SIM Interface

15K

VDD

DAT

CLK CARD

RST

3.1.6 UART Interface

UART signals are connected to MARITA GPIO through IO connector

UART0

Resource Name

GPIO10UARTRX0

GPIO11

Note

Transmit Data

UARTTX0Receive Data

UART1

GPIO14

GPIO15

GPIO16

GPIO17

UARTRX1

UARTTX1

UARTRTS1

UARTCTS1

Transmit Data (UART1)

Receive Data (UART1)

Request To Send

Clear To Send

Table. UART Interface

- 28 -

3. TECHNICAL BRIEF

3.1.7 GPIO (General Purpose Input/Output) map

In total 40 allowable resources. This model is using 25 resources.

GPIO Map, describing application, I/O state, and enable level are shown in below table.

IO # Application

GPIO00 Not used

GPIO01 BL_PWL

GPIO02 7C_LED_VDD_EN

GPIO03 PULSESKIP (Not used)

GPIO04 CAMERA_DET

GPIO05 GPIO05 (Not used)

GPIO06 AMPCTR

GPIO07 TGBUZZ (Not used)

GPIO10UARTRX0

GPIO11 UARTTX0O

GPIO12 Not used –

GPIO13 Not used

GPIO14 UARTRX1

GPIO15 UARTTX1

GPIO16 UARTRTS1

–

GPIO17 UARTCTS1

GPIO20CAM_REG_EN

GPIO21 CAM_FLASH_ON

GPIO22 TP2125 (Not used)

GPIO23 CAM_FLASH_SHOT

GPIO24 Not used

GPIO25 Not used

GPIO26 Not used

GPIO27 Not used

GPIO30Not used

GPIO31 Not used

–

GPIO

–

UART1

GPIO

Resource

–

GPIO

–

GPIO

UART0

Inactive State

–

Low

–

High

–

Low

High

–

High

–

Low

–

Low

–

High

–

High

–

Low

High

Low

–

Active State

–

High

–

Low

–

High

- 29 -

3. TECHNICAL BRIEF

IO # Application

GPIO32 KEY_LED_ONOFF

GPIO33 Not used

GPIO34 Not used

GPIO35 LCDVSYNCI (Not used)

GPIO36 SPKMUTE

GPIO37 Not used

GPIO40USBSENSE

GPIO41 Not used

GPIO42 BL_EN

GPIO43 FOLDER_DET

GPIO44 EN_LED_R

GPIO45 EN_LED_G

GPIO46 EN_LED_B

GPIO47 IRDA_REG_CTRL

–

Table. MARITA GPIO Map Table

–

GPIO

Resource

GPIO

–

GPIO

–

GPIO

Inactive State

Low

–

Active State

High

–

Low High

LOW (Ear piece) HIGH (Speaker)

–

Low

–

High

–

Low

High

Low

–

High

Low

High

- 30 -

3. TECHNICAL BRIEF

3.1.8 USB

The USB block supports the implementation of a "full-speed" device fully compliant to USB 2.0

standard. It provides an interface between the CPU (embedded local host) and the USB wire, and handles USB transactions with minimal CPU intervention.

The USB specification allows up to 15 pairs of endpoints. Data for each endpoint is buffered in RAM within the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO register access. High-speed (high throughput) endpoints can use DMA while slower endpoints can use FIFO register access.

The USB block can request up to six DMA channels, three for IN endpoints and three for OUT endpoints.

USB Function

USBDP

Note

USB differential (+) line

USBDM USB differential (-) line

USBSENSE (GPIO40) USB detection (input)

USBPUEN

VDDUSB

USB pull-up control

Power supply for MARITA USB block

Table. USB Signal Interface of MARITA

Figure. Schematic of MARITA USB block

- 31 -

3. TECHNICAL BRIEF

USB regulator input voltage is 5V and uses external USB device power through IO Connector.

Output voltage is 3.3V and supply to MARITA USB block.

USB is detected by MARITA GPIO40(USBSENES).

• VUSB / (10K + 51K) = VUSBSENSE / 51K

Figure. Schematic of USB Regulator

Figure. Schematic of USB filter

- 32 -

3. TECHNICAL BRIEF

3.1.9 IrDA Interface

MARITA supports FIR, MIR and SIR mode.

In this model, the IrDA block supports SIR (Standard IrDA) mode.

SIR supports data rates up to 115,200 bps, including 9,600/19,200/38,400/57,600 bps.

In this mode, IrDA uses eight data bits per character and one stop bit.

IrDA supports a protocol defined by the IrDA Association.

Figure. Schematic of MARITA IrDA Interface

- 33 -

3. TECHNICAL BRIEF

3.1.10 Folder ON/OFF Operation

There is a magnet to detect the folder status, opened or closed.

If a magnet is close to the hall-effect switch (U1 on keypad), the voltage at pin2 of U1 goes to 0V.

Otherwise, 2.8V.

This folder signal is delivered to MARITA GPIO43.

VCAM

R3206

100K

CAMERA_DET

C3204

0.1u

C3205

10p

Figure. Schematic of MARITA IrDA Interface

- 34 -

3. TECHNICAL BRIEF

3.1.11 Power On Sequence

1 User press END key and ONSWAn signal is changed to Low.

2 VINCENNE initiate the internal oscillator and power up the regulators.

3 VINCENNE generate a power for MARITA.

4 VINCENNE release the power reset signal(PWRRSTn) and generate an interrupt(IRQ0n) to

MARITA.

Press END key

ONSWAn

VINCENNE

Power for

MARITA

ONSWA

PWRRST

IRQ

RESETB

PWRRSTn

IRQ0n

MARITA

RESPOW_N

IRQ0_N

RESOUT0_N

Figure. Power On Sequence

- 35 -

3. TECHNICAL BRIEF

3.1.12 Key Pad

There are 26 buttons and 3 side keys in Figure 3-xx.Shows the Keypad circuit.‘END’ Key is connected

ONSWAn from Vincenne.

KEYIN0KEYIN1

KEYOUT0SIDE1

KEYOUT1

KEYOUT2

KEYOUT3

KEYOUT4

KEYOUT5

SEND

CLEARER

KEYIN2

SIDE2

BACK

MULTI

Table Key Matrix Mapping Table

KEYIN3

SIDE3

KEYIN4

0DOWN

GAME

CAM

RIGHT

LEFT

Figure. Power On Sequence

- 36 -

3.2 GAM Hardware Subsystem

3. TECHNICAL BRIEF

Figure. GAM Subsystem Functional Block Diagram

3.2.1 General Description

• GRAM - graphics memory (160 kB).

• GAMCON . GAM controller.

• GRAPHCON . graphics controller.

• PDI/SSI - programmable display interface for parallel/serial displays.

• CDI - camera data interface.

- 37 -

3. TECHNICAL BRIEF

3.2.2 Block Description

GAM Controller(GAMCON)

The GAM Controller (GAMCON) is responsible for clock gating and distribution within the GAM module. GAMCON receives the HCLK from SYSCON and distributes to GRAPHCON, GRAM, PDI and

CDI. GAMCON also distributes the GAM reset signal to GRAPHCON, GRAM, PDI and CDI. The reset signals CIRES_N and PDIRES_N are distributed from GAMCON to the camera and display module respectively, see Figure. The CIPCLK is used to clock the received data into the camera data interface. The CIPCLK can be in the range of 100 kHz to 16 MHz.

Graphics RAM (GRAM) Block

GAM includes 160 kB of graphics memory (GRAM) in order to support display screen sizes of QCIF + alfa display size and three frame buffers when decoding QCIF video.

The GRAM can be accessed in 8, 16 or 32-bit mode. Write access takes a single AHB clock cycle.

Non-sequential read and the first access of a sequential read access takes two AHB clock cycles.

Subsequent sequential read access take a single AHB clock cycle.

The GRAM contains both frame buffer and temporary data. There are three image areas with one used for normal MMI graphics and the other two areas used for still images, video frames or camera frames. The three image areas can be combined into one frame buffer.

GRAM is required to transfer a VGA (640 by 480 pixels) image from the camera data interface (CDI) over DMA at 100 MBit/s, within a 50 ms timeframe. The GRAM is used as a buffer, but the average transfer bandwidth required is approximately 3 Mword/s (32-bit word), that is 12 MByte/s.

Graphics Controller (GRAPHCON) Block

GRAPHCON is controlled by the application CPU and can perform operations on pixels and image areas. Images can be moved and merged with other images and text.

The GRAPHCON block receives graphical objects from GRAM and performers the appropriate graphical manipulation. The resulting data is transfers to the display interface (PDI). GRAPHCON can receive images from the camera data interface (CDI) and send them to the PDI automatically.

GRAPHCON performs conversion from YUV to RGB and can scale (zoom) still or video images.

Programmable Display Interface (PDI) Block

The programmable display interface (PDI) is designed to interface both parallel and serial display modules. The display data is transferred from the 32 word FIFO on GAMCON to the display module via the PDI block. The PDI block is built around a micro controller and executes 16-bit instruction words to individually control the I/O ports. It has a 128 byte program memory, programmable by the

CPU, which can store up to 64 instructions.

The CPU transfers all set-up and control data to the display. Data is transferred to PDI as 32-bit words, which in turn writes 8-bit data to the display. The programmable PDI block is configured at the software build stage, to support either parallel interface such as PPI or serial interface such as SSI or

I2C.

- 38 -

3. TECHNICAL BRIEF

Camera Data Interface (CDI) Block

The camera data interface (CDI) block is designed to support a range of still image camera modules.

An 8-bit parallel bus supports data transfer from the camera module to the CDI.

The pixel clock is an output clock from the camera module to the CDI and qualifies the data on the parallel bus. One byte of data is captured on each rising edge of the pixel clock. CDI allows the pixel clock to be in the range of 100 kHz to 16 MHz.

The horizontal synchronization line is an input from the camera module and defines one scan-line of image data. The horizontal synchronization line can be programmed to be active high or low. The vertical synchronization line is an input from the camera module and defines one image frame (image height) of data. The vertical synchronization line can be programmed to be active high or low.

The frame rate can be adjusted by skipping frames and various interrupts are used to inform the application CPU regarding the progress of incoming images and potential errors. The normal data format on the data bus is YUV 4:2:2 (raw binary image data) according to the CCIR-656 standard. A function within the CDI can be programmed to reorder the YUV parameters as they pass through the

CDI. In addition, the CDI is able to detect the end of an image and perform some truncation as well as overflow conditions. There is nothing preventing the use of other data types such as JPEG or RGB (as long as the timing is followed), but only YUV data can be sent to the display.

Camera images can also be sent to a DMA channel to store the image in external memory.The I2C interface and GPIO are part of the interface to the camera module, but they are not part of the CDI block. The I2C is used to set-up and control the camera module.

The camera module I2C lines must go high impedance when the supply is removed from the camera.

The I2C commands needed to control the camera, as well as the functional behavior of the module, are also different for each implementation.

The ON-signal (GPIO) is used to power-on the camera from Standby or Off mode (implementation dependent). This signal must be held low when the mobile equipment is powered down and during the mobile equipment reset period. The GPIO pin can also be an input or high impedance during mobile equipment reset and start. In this case, it must have pull-down to ground.

The camera module reset signal is an output to the camera module.

- 39 -

3. TECHNICAL BRIEF

3.2.3 Camera & Camera FPC Interface

PDID1

PDID2

PDID3

PDID4

PDID5

PDID6

PDID7

I2CSCL

I2CSDA

CIPCLK

CIVSYNC

CIHSYNC

CIRES_N

CID0

CID1

CID2

CID3

CID4

CID5

CID6

CID7

H15

G21

E19

E20

E21

H14

F19

F20

G18

G19

G20

C18

B19

A20

H13

G14

B20

H18

VDIG

PDID1

PDID2

PDID3

PDID4

PDID5

PDID6

PDID7

VCORE

VDIG

I2CDAT

CIPCLK

CIVSYNC

CIHSYNC

CIRES_N

CID0

CID1

CID2

CID3

CID4

CID5

CID6

CID7

CAMERA I/F

RTC_GND

I2CCLK

R3333 NA

Figure. Camera Interface (in Marita)

I2CCLK_CAMERA

Figure. Camera Board to Board Connector

- 40 -

3. TECHNICAL BRIEF

The Camera module is connected to main board with 20pin Board to Board connector (AXK7L80225).

Its interface is dedicated camera interface port in Marita. The camera port supply 24MHz master clock to camera module and receive 12MHz pixel clock (30fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV data from camera module. The camera module is controlled by I2C port.

Pin Name

DOUT4

DOUT5

DOUT1

DOUT2

DCLK DO

DOUT0DO

DOUT3

EXTCLK

10GND

11 FSSTB

Pin Type

DVDD

GND

SCL

RESET

AVDD

SDA

DOUT6

20DOUT7

Image data output

Description

Image data output

Vertical Synchronization Pulse Output

Image data output

Clock for Output Data

Image data output

External Clock Input

Ground

Strobe Pulse for Flash

VDD for the Digital Circuit

Ground

Clock for IIC bus Command

Reset Terminal

VDD for the Sensor and PLL

Horizontal Synchronization Pulse Output

Clock for IIC bus Command

Image data output

Table. Interface between Camera Module and Main Board (in camera module)

- 41 -

3. TECHNICAL BRIEF

3.2.4 Camera Position Detection

GPIO_04 detects the Camera Position (front or back)

Figure. Camera Position Detection

3.2.5 Camera Regulator

GPIO_20 enables Camera Regulator Operation

Figure. Camera Regulator

- 42 -

3. TECHNICAL BRIEF

3.2.6 Display & LCD FPC Interface

LCD module include device in table 3-2

Device

Main LCD

Sub LCD

Main LCD Backlight

Sub LCD Backlight

Type

176 x RGB x 220 65K Color TFT LCD

96 x 64 Mono FSTN LCD

White LED

7 color LED

Table. Devices in LCD Module

LCD module is connected to key board with 40-pin BtoB connector (CONN_40_AXK840145J) and

Speaker, Receiver, Vibrator, Camera Flash is connected by soldering the leads to 9 pads in LCD module.

The Main LCD is controlled by 8-bit PDI(Parallel Data Interface) in Marita and Sub LCD is controlled by 8-bit PDI in Marita.

PIN SYMBOL I/O REMARKS

EARP

EARM

SPKP

SPKM

MOTOR_BATT

MOTOR_GND

VOUT_F1

VSIG_F2

FUNCTION

SPK TERMINAL

Ear Piece Plus

Ear Piece Minus

Loud Speaker Plus

Loud Speaker Minus

MOTOR TERMINAL

MOTOR Power

MOTOR Ground

CAMERA FLASH TERMINAL

FLASH Power

FLASH Signal

Dummy Ground

Table. Interface between LCD module and Speaker, Receiver, Vibrator, Flash

- 43 -

3. TECHNICAL BRIEF

SYMBOL

GND Ground

FUNCTION

CAM_FLASH_SHOT Turn ON the Camera Flash Shot

MOTOR_BATT

SPKP

SPKM

MOTOR Power

Loud Speaker Plus

EN_LED_G

Loud Speaker Minus

Enable Signal for Sub LCD Backlight

LED(Green)

7C_LED_VDD

BL_EN

10PDID2

Power Supply for Sub LCD Backlight

Enable Signal for Main LCD Backlight

PDID4

PDID6

LCDRDX

LCDRS

Parallel Data 2 bit for Main/Sub LCD

Parallel Data 4 bit for Main/Sub LCD

Parallel Data 6 bit for Main/Sub LCD

Read Signal for Main/Sub LCD status

LCDCSX_SUB

LCDVSYNCI

GND

Chip Select Signal for Sub LCD

Main LCD Vertical Synch. Signal

Ground

GND

20GND

GND

Ground

VDIG_2.8V

LCDERESX

LCDCSX_MAIN

LCDWRX

PDID7

PDID5

Power Supply for system and I/O Logic(2.8V)

Reset Signal for Main/Sub LCD

Chip Select Signal for Main LCD

Write Signal for Main/Sub LCD

Parallel Data 7 bit for Main/Sub LCD

Parallel Data 5 bit for Main/Sub LCD

I/O REMARKS

- 44 -

3. TECHNICAL BRIEF

30PDID3

SYMBOL

PDID1

BL_PWL

VBATI_4.2V

EN_LED_B

EN_LED_R

EARP

ERAM

GND

CAM_FLASH_ON

40GND

FUNCTION

Parallel Data 3 bit for Main/Sub LCD

Parallel Data 1 bit for Main/Sub LCD

Main LCD PWL signal

Battery Power(4.2V)

Enable Signal for Sub LCD Backlight

LED(Blue)

Enable Signal for Sub LCD Backlight

LED(Red)

Ear Piece Plus

Ear Piece Minus

Ground

Turn ON the Camera Flash

Continuous ON

Ground

I/O

Table. Interface between LCD module and main board(in LCD Module)

REMARKS

- 45 -

3. TECHNICAL BRIEF

3.2.7 Main LCD Backlight Illumination

There are 4 white LEDs in Main LCD Backlight circuit which are driven by 4.5V Regulated Output

Charge Pump(SC604). GPIO_01(BL_PWL) is used for Backlightbrightness control.

Figure. Charge Pump Circuit for Main LCD Backlight

* LED : SSC-HWTS902(Seoul Semiconductor)

- 46 -

3. TECHNICAL BRIEF

3.2.8 Sub LCD Backlight Illumination

GPIO_02(7C_LED_VDD_EN) in Marita enables 7 color LED. 7 color LED consists of Red LED, Green

LED and Blue LED. GPIO_44(EN_LED_R), GPIO_45(EN_LED_G) and GPIO_46(EN_LED_B) in

Marita does ON or OFF its own LEDs.

Figure. Sub LCD Backlight 4.5V

In case of power off mode, if TA is inserted, Red LED is turned-on.

- 47 -

3. TECHNICAL BRIEF

3.2.9 Keypad Illumination

There are 19 blue LEDs in key board backlight circuit, which aredriven by GPIO_32

(KEY_LED_ONOFF) line form Marita.

Figure. Keypad Backlight Blue LED Interface

Figure. Keypad Backlight Circuit

- 48 -

3. TECHNICAL BRIEF

3.2.10 Camera Flash Illumination

Camera Flash illumination circuit make 3 modes using white LED. Mode 1. Is Continuous ON mode using GPIO_21(CAM_FLASH_ON), Mode 2. Is Flash Shot using GPIO_23(CAM_FLASH_SHOT) and

Mode 3. combines Mode 1. and Mode 2.

Figure. Camera Flash Circuit

Figure. Camera Flash FPCB & Circuit

- 49 -

3. TECHNICAL BRIEF

3.3 LCD Module

Figure. LCD Module Block Diagram

Figure. LCD Module(Main & Sub LCD)

- 50 -

3.4 Analog Baseband (ABB) Processor

3.4.1 Overview of Audio path

3. TECHNICAL BRIEF

Figure. Audio Path Block Diagram

- 51 -

3. TECHNICAL BRIEF

3.4.2 Audio Signal Processing & Interface

Audio signal processing is divided Uplink path and downlink path.

The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal and then transmit it to DBB Chip (Marita).

This transmitted signal is reformed to fit in GSM & WCDMA Frame format and delivered to RF Chip.

The downlink path amplifies the signal from DBB chip (Marita) and outputs it to Receiver (or Speaker).

The audio interface consists of PCM encoding and decoding circuitry, microphone amplifiers and earphone drivers.

The PCM encoder and decoder blocks are two-channel, 16-bit circuits with programmable gain amplifiers (PGA).

The decoder has a receive volume control. The audio inputs and outputs can be switched to normal or auxiliary ports.

Figure. Audio Interface Detailed Diagram (VICENNE)

- 52 -

Figure. Audio Section scheme

- 53 -

3. TECHNICAL BRIEF

3.4.3 Audio Mode

Audio Mode includes three states. (Voice call, Midi.MP3).

Each states is sorted by the total 7 Modes according to external Devices

(Receiver, Loud Speaker, Headset).

Video Telephony Mode Operate on state of the WCDMA CALL.

Voice call

MIDI

MP3

Mode

Receiver Mode

Loud Speaker Mode

Headset Mode

Video Telephony Mode

Only Loud Speaker

Loud Speaker Mode

Headset Mode

VINCENNE In/Out Port

OUT

MIC1P/MIC1N

BEARP/BEARN

BEARP

AUXI1

MIC1P/MIC1N

AUXO1/AUXO2

BEARP

AUXO1/AUXO2

Table Audio Mode

- 54 -

3. TECHNICAL BRIEF

3.4.4 Voice Call

3.4.4.1 Voice call Downlink Mode(Receiver, Speaker, Headset)

This section provides a detailed description of the Voice Call RX functions.

Figure. Voice call Downlink Scheme

- 55 -

3. TECHNICAL BRIEF

The voice decoder accepts a serial input stream of linear PCM coded speech. The receive band-pass filter is the next step in the CODEC receive path. Following the filter is the DAC, followed by a PGA enabling to adjust or trim the circuit in the product for different sensitivity of the earphone and spread in the RX path. The final step in the receive path is the earphone amplifier and the auxiliary output.

The auxiliary audio amplifier is intended to drive low impedance headphones. The earphone amplifier and the auxiliary audio outputs can be powered down (muted) via I2C. Both the earphone driver and one of the auxiliary drivers can simultaneously provide an output signal during voice decoding.

• Receiver Mode : Earphone amplifier

→ BEARP/N Port → Receiver(32Ω)

• Loud Speaker Mode : Earphone amplifier

→ BEARP Port → Analog S/W(ADG702) →

AUDIO AMP(LM4894IBP)

→ Speaker(8Ω)

•Video Telephony Mode : Earphone amplifier

→ BEARP Port → Analog S/W(N2603) →

AUDIO AMP (LM4894IBP)

→ Speaker(8Ω)

• Headset Mode : Auxiliary audio amplifier

→ AUXO1/2 →

TJATTE2 IN (AFMS_R_INT/AFMS_L_INT)

→

TJATTE2 OUT(AFMS_R/AFMS_L)

→ Head Phone

Speaker Phone Mode has two GPIO switching control ports. One is SPKMUTE and the other is

AMPCTRL. SPKMUTE controls analog switch( ADG702) and AMPCTRL controls shutdown of

AUDIOAMP(LM4894IBP). Video Telephony Mode has same paths with Loud Speaker Mode.

Mode

Receiver

Headset

Loud Speaker

Video Telephony

SPKMUTE

High

Low

Table Speaker Phone Mode GPIO control state

AMPCTRL

Low

High

* SPKMUTE; MARITA GPIO36

* AMPCTRL; MARITA GPIO06

- 56 -

3. TECHNICAL BRIEF

3.4.4.2 Voice Call Uplink Mode (Receiver, Speaker, Headset)

This section provides a detailed description of the Voice Call TX functions.

Figure. Voice call Uplink Scheme

The Uplink supports two microphones and two auxiliary inputs to the speech encoder blocks. Both microphone inputs are compatible with an electric microphone.

The VINCENNE internal voltage source (CCO) provides the necessary drive current for the electric microphone. The voltage source is via I2C programmable to supply 2.2V or 2.4V. But the voltage source of our Model is to supply 2.4V.

The auxiliary audio inputs can be used as an alternative source of speech, a source from an external microphone or as an analog loop connection. Figure shows that the audio inputs are fed to the transmit PGAs, which enables to adjust the total gain in the product for different sensitivities of the microphones and spread in the transmit paths. The ADCs are followed by the transmit band pass filters, which accept the maximum output swing that the microphone preamplifiers can deliver without clipping, and maintain a good signal-to-noise ratio. The high pass filter in the TX-paths can be disabled via I2C; still removing the DC offset from the signal. For one of the two transmit paths, a transmit gain control amplifier precedes the final encoding of the PCM output.

- 57 -

3. TECHNICAL BRIEF

Each Voice Uplink Mode paths shown below.

Receiver Mode : C-MIC(OBG-15S44)

→ TJATTE2 IN (MICP/N) → TJATTE2 OUT

(MICP_INT/MICN_INT)

→ VICENNE Input(MIC1N/1P)

Loud Speaker Mode : C-MIC(OBG-15S44)

→ TJATTE2 IN (MICP/N) →

TJATTE2 OUT(MICP_INT/MICN_INT)

→ VICENNE Input(MIC1N/1P)

Video Telephony Mode : C-MIC(OBG-15S44)

→ TJATTE2 IN (MICP/N) → TJATTE2 OUT

(MICP_INT/MICN_INT)

→ VICENNE Input(MIC1N/1P)

Headset Mode : Headset MIC

→ EARJACK S/W(X2602, Pin Num 2) → TJATTE2 IN(ATMS_CAP)

TJATTE2 OUT (ATMS_INT) VICENNE Input(AUXI1)

When the headset is inserted, GPA6(Circuit Diagram net Name) converted into low state.

So, the headset icon is displayed on Main LCD.

- 58 -

3. TECHNICAL BRIEF

3.4.5 MIDI (Ring Tone Play)

This section provides a detailed description of the MIDI and WAV-file functions.

Figure. MIDI Scheme

External MIDI path is the same as Voice Loudspeaker downlink Mode, except source in MARITA (DSP and Audio Mixer).

• MIDI : MARITA

→ PCM Decoder → Earphone amplifier → BEARP Port → Analog S/W(ADG702) →

AUDIO AMP(LM4894IBP)

→ Speaker(8Ω)

MIDI being played through external Device Speaker only. MIDI Mode control port shown below

STATE(SPK ONLY)

MIDI ON

MIDI OFF

SPKMUTE

LOW

High

Tabel MIDI GPIO Control STATE

AMPCTRL

High

Low

* SPKMUTE; MARITA GPIO36

* AMPCTRL; MARITA GPIO06

- 59 -

3. TECHNICAL BRIEF

3.4.6 MP3 (Audio Player)

This section provides a detailed description of the MP3 file functions.

Figure. MP3 Scheme

MP3 function supports PCM 44/48KHz sampling rate.The PCM44/48 RX-path is intended to be used as a stereo music headphones. It is also possible to connect a differential load or to use the RX-path with only one channel running (mono).

In stereo mode, auxiliary outputs (AUXO1 and AUXO2) can be used to drive the headset.

In single channel mode (mono), BEARP can be used to drive a load (Speaker).

- 60 -

3.4.7 Video Telephony

This section provides a description of the Video Telephony functions.

3. TECHNICAL BRIEF

Figure. Video Telephony Scheme

Video Telephony Mode has same paths with Loud Speaker Mode.

STATE(SPK ONLY)

Video Telephony ON

Video Telephony OFF

SPKMUTE

LOW

High

Tabel Video Telephony GPIO Control STATE

* SPKMUTE; MARITA GPIO36

* AMPCTRL; MARITA GPIO36

AMPCTRL

High

Low

- 61 -

3. TECHNICAL BRIEF

3.4.8 Audio Main Component

There are 6 components in U8100 schematic Diagram. Part Number marked on U8100 Schematic

Diagram.

ITEM

Dual Speaker

C-MIC

Audio AMP

TJATTE2

Ear-JACK

Analog Switch

Part Name

EMD1940A

OBG-15S44

LM4894IBP

IP4025CS20

HSJ1730

ADG702

Tabel Audio Component List

Part Number

X2603

N2601

N2602

X2602

N2603

TJATTE2 Description

The TJATTE2 is a 6-channel RC low pass filter array that is designed to provide filtering of undesired

RF signals in the 800-2700 MHz frequency band.

In addition, the TJATTE2 incorporates diodes to provide protection to downstream components from

Electrostatic Discharge (ESD) voltages as high as 8 kV.

PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION

A1 MICN B1 GND C1 CCO D1 MICN-int

A2 MICP

A3 ATMS

GND

ATMS_AD

GND

MICP-int

ATMS-int

A4 ATMS-cap

A5 AFMS_L

B4 AFMS_R

B5 VDD

C4 GND

C5 GND

D4 AFMS_R-int

D5 AFMS_L-int

Tabel TJATTE Pin Description

- 62 -

Figure. TJATTE2 Block Diagram

- 63 -

3. TECHNICAL BRIEF

3.4.9 GPADC(General Purpose ADC) and AUTOADC2

The GPADC consists of a 14 input MUX and an 8-bit ADC. The analog input signal is selected with the

MUX and converted in the ADC.

The GPADC has a built in controller, AUTOADC2, which is able to operate in the background without software intervention. The AUTOADC2 periodically measures the battery voltage or current. Figure shows the schematic of GPADC part. The GPADC channel spec is as following Table.

Figure. Schematic of GPADC and AUTOADC2

Figure. GPADC and AUTOADC2 Block diagram

ADC 6 channels

Resource Name

GPA0RTEMP

GPA2

GPA3

VLOOP

WPOWERSENSE

GPA4

GPA6

GPA7

WRFLOOP

GPA6

VBACKUP

Table. GPADC channel spec

Description

Radio temperature sense

Loop voltage sense

Reference voltage for PAM

Lock inform

Headset detect

Backup battery

- 64 -

3. TECHNICAL BRIEF

3.4.10 Charger control

A programmable charger in AB2000 is used for battery charging. It is possible to set limits for the output voltage at CHSENSE- and the output current from DCIO via the sense resistor to CHSENSE-.

The voltage at CHSENSE- and the current feed to CHSENSE- cannot be measured directly by the

GPADC. Instead, the two measuring amplifiers translate these inputs to a voltage proportional to the input and within the range of the GPADC. Figure shows the schematic of charging control part.

DCIN_3

C2280

1608

Q2201

Si5441DC

R2214

0.1

DCIO

CHREG

CHSENSE+

CHSENSE-

DCIN_2

VBATI

Figure. Schematic of charging control part

Figure. Battery charging block diagram

- 65 -

3. TECHNICAL BRIEF

3.4.11 Fuel Gauge

AB2000 supports the measurement of the current consumption/charging current in the U8100 with a fuel gauge block. By constantly integrating the current flowing into and out of the battery, the fuel gauge block is used to determine the remaining battery capacity.

The function of the fuel gauge block is schematically described in Figure. A sense resistor

R_FGSENSE is connected in series with the battery. The voltage across the resistor, equivalent to the current entering/leaving the battery, is integrated using an ADC block.

Figure. The analog front-end of the fuel gauge block

Figure. The Schematic of the fuel gauge block

Name

FGSENSE+

FGSENSE-

Type

Analog

Unused

VBAT

Description

Fuel gauge current sensing input positive

Fuel gauge current sensing input negative

Table. Fuel Gauge channel spec

- 66 -

3. TECHNICAL BRIEF

3.4.12 Battery Temperature Measurement

The BDATA node, the constant current source, feed the battery data output while monitoring the voltage at the battery data node with GPADC. This battery data is converted to the battery temperature. Figure shows the schematic of battery temperature measurement part.

Figure. Battery Temperature Measurement

Name

BDATA

Type

Digital Input/Output

Unused

Unconnected

Table BDATA channel spec

Description

Current output

- 67 -

3. TECHNICAL BRIEF

3.4.13 Charging Part

The charging block in AB2000 processes the charging operation by using VBAT voltage. It is enabled or disabled by the assertion/negation of the external signal DCIO. Part of the charging block are activated and deactivated depending on the level of VBAT. Figure shows the schematic of charging part.

Figure. Charging Part

When VBAT is below a certain value, 3.2V, a current generator take care of initial charging of the

CHSENSE+ node and internal trickle charge signal is active. This part of the charging block is powered on and active when DCIO is asserted. The DCIO signal is asserted when its voltage is above the voltage at VBAT. As soon as generator is turned off and all parts of the charging block are functional and active.

Battery block indication as shown in Fig

4.20 ~ 3.87 (V)

100 ~ 68 (%)

3.87 ~ 3.77 (V)

68 ~ 47 (%)

3.77 ~ 3.72 (V)

47 ~ 26 (%)

3.72 ~ 3.50 (V)

26 ~ 5 (%)

Figure. Battery Block Indication

3.50 ~ 3.20 (V)

5 ~ 0 (%)

- 68 -

3. TECHNICAL BRIEF

Trickle charging

When the VBAT is below a certain value, 3.2V, a current generator take care of internal trickle charge signal is active. The charging current is set to 50mA.

Parameter

Trickle current

Min Typ Max Unit

3050 60mA

Table BDATA channel spec

Normal charging

When the VBAT voltage is within limits or the internal regulators are turned on, the current source for trickle charging is turned off and all parts of the charging block are active. The charging method is

‘CCCV’. (Constant Current Constant Voltage)

This charging method is used for Lithium chemistry battery packs. The CCCV method regulates the charge current and the VBAT voltage. This charging method prevents the battery voltage to go above the charge set in the CCCV algorithm. This picture shows the charging voltage(a) and charging current change(b).

(a) Charging voltage

(b) Charging current

Figure. CCCV charging method

- 69 -

3. TECHNICAL BRIEF

• Charging Method : CCCV (Constant Current Constant Voltage)

• Maximum Charging Voltage : 4.2V

• Maximum Charging Current : 600mA

• Nominal Battery Capacity : 1200 mAh

• Charger Voltage : 4.6V

• Charging time : Max 3.5h

• Full charge indication current (icon stop current) : 80mA

• Low battery POP UP : Idle - 3.46V, Dedicated – 3.50V

• Low battery alarm interval : Idle - 3 min, Dedicated - 1 min

• Cut-off voltage : WCDMA call - 3.1V, ELSE – 3.2V

Charging of Extended Temperature

When the battery temperature is outside the normal charging specification, the battery voltage, VBAT, is maintained at 3.7V.

•Under 0 °C : Extended temperature

•From 0 °C to 55 °C : Normal charging temperature

•Over 55 °C : Extended temperature

- 70 -

3. TECHNICAL BRIEF

3.5 Voltage Regulation

3.5.1 Internal Regulation

There are LDO (Low Drop Output) regulators and BUCK converter in AB2000 (Vincenne) chip. LDO regulators and BUCK converter generate the following voltages : 1.5V, 1.8V and 2.75V. The output of these LDOs supply VDD-A, VDD-B and VDIG with 2.75V. BUCK converter steps down the VBAT to

1.5V for VCORE and VRTC, and to 1.8V for VMEM voltage. The output of these LDOs and BUCK converter are as following Table. Figure shows the power supply of each module in U8100.

3.5.2 External Regulation

1.5V LDO - supply 1.5V for wanda core

2.8V LDO - supply 2.8V for IrDA

2.8V LDO - supply 2.8V for Camera

3.3V LDO - supply 3.3V for USB

4.5V DC-DC converter – supply 4.5V for LCD back light

- 71 -

3. TECHNICAL BRIEF

L12

Pin

B12

A11

M11

Name

VDD_A

VDD_B

VDD_D

VDD_E

VDDLP

VDDBUCK

VSSBUCK

Figure. Power Supply Scheme

Type

Power Supply

Output voltage

2.75V

Description

Supply output

Power Supply

1.8V

1.5V

Supply output

Low Power supply output

Power Supply

Unused: VBAT Buck converter switch supply

GND

Table BDATA channel spec

Buck converter switch ground

- 72 -

3. TECHNICAL BRIEF

3.6 General Description

The RF part includes a dual-band GSM/DCS part (900 and 1800MHz) and W-CDMA part for IMT-2000

(UL 1900MHz, DL 2100MHz). It also contains Antenna Switch, WCDMA duplexer, WCDMA Power

Amplifier and GSM Power Amplifier.

The whole structure of Radio part is shown in Figure 3-1.

UMT S RX SAW UMT S RX IF SAW

Antenna

T est po int

Antenna Switch

Isola to r

Duplex er

UM TS Wo py

RF PLL

/VCO

UMTS PA

UMT S T X SAW

DC/DC

Ro sa lie

DCS RX SAW

UM TS Wivi

T ank

IF PLL /VCO

÷

GSM RX SAW

GSM Dual PA

DCS Ba lun

÷

GSM Inge la

Loo p filter

Dio de

XO (13 MHz)

ADC

Clk

GSM Herta

GSM B alun

Prescale r

Figure 3-1. Block diagram of RF part

Starting at the antenna end, an antenna switch provides switching capability needed for three frequency bands (900, 1800 and 2100MHz). For the W-CDMA part, duplexer is included to facilitate the simultaneous transmission and reception required for the FDD mode.

The main components in the radio are Wopy (W-CDMA receiver ASIC), Wivi(W-CDMA transmitter

ASIC), Ingela(GSM/GPRS transceiver) and two power amplifiers.

The mixed-signal circuit ASIC, Vincenne provides power supply for the main RF components.

- 73 -

3. TECHNICAL BRIEF

The control flow for the Radio is shown in Figure 3-2.

Figure 3-2. RF control signal flow diagram

The Marita(the main processor) controls the overall radio system. In the GSM/GPRS air interface mode, this control is handled via direct interfaces to individual RF components. The Marita(the main processor) also handles the antenna switch mechanism for selection of mode.

In the W-CDMA mode, the RF system is managed via the Wanda (WCDMA digital base-band coprocessor ASIC) and its DSP processor.

- 74 -

3. TECHNICAL BRIEF

3.7 GSM Mode

3.7.1 Receiver

The received RF signal on the antenna connector arrives via antenna switch at external band pass filters for band selectivity. One filter is required per supported GSM band. The corresponding LNA amplifies the signal for optimum noise suppression.

The LNA output signal is mixed with the on-channel LO generated by the proper VCO and transformed into a Q and an I signal. The I and Q signals are low pass filtered with two parallel high dynamic range filters.

Finally, the filtered I and Q signals are converted by a sigma-delta converter into two 13 Mbps digital bit streams by Herta(A/D converter), then fed to the Marita baseband ASIC.

A. Front end.

RF Front end consists of antenna, antenna switch(N1000), two RF SAWs(Z1100, Z1110) and dual band LNAs integrated in transceiver(N1100). The Received RF signals(GSM 925MHz ~ 960MHz, DCS

1805MHz ~ 1880MHz) are fed into the antenna or coaxial connector. An antenna matching circuit is between the antenna and the coaxial connector.

The Antenna Switch(N1000) is used to select the signal path, which is one of WCDMA, GSM RX,

GSM TX, DCS RX, and DCS TX. The control signals VC1, VC2 and VCG of antenna switch (N1000) are connected to Marita baseband ASIC(D2000) to control the signal path. For example, when the

GSM RX path is turned on, the received RF signal, which has passed through the antenna switch, is filtered by GSM RF SAW filter to suppress any unwanted signal except GSM RX band. The filtered RF signal is amplified by an LNA integrated in the transceiver IC(N1100) and is passed to a direct conversion demodulator. The process for DCS RX is also the same as GSM RX case.

The logic for antenna switch is given below Table 3-1.

GSM TX

GSM RX

DCS TX

DCS RX

WCDMA

VC1

2.8V ~ 3.0V

VC2

2.8V ~ 3.0V

VCG

2.8V ~ 3.0V

Table 3-1. Antenna Switch logic

- 75 -

3. TECHNICAL BRIEF

B. Receiver Block.

The circuit contains one frequency down-conversion section for each receive band and a common base band amplifier and filter section. The GSM900 RF part consists of a low noise amplifier followed by high dynamic range mixers.

The DCS 1800 RF part also has low noise amplifier connected to the other mixers.

The amplified RF signal is mixed with the quadrature local oscillator signal to create in-phase (I) and quadrature phase (Q) baseband signals. The I and Q signals are then buffered and low pass filtered.

The same baseband circuitry is used for all bands.

Balanced signals are used for minimizing cross talk due to package parasitics. An impedance level at

RF of 150 ohms for the GSM 900 input and 50 ohms for the DCS 1800 input is chosen to minimmize current consumption at best noise performance.

The low gain mode in GSM 900 is used in high input signal mode. There is no gain switch in DCS

1800.

Figure 3-3 shows a block diagram of the receiver block.

Figure 3-3. Block diagram of receiver part.

- 76 -

3. TECHNICAL BRIEF

C. LO Block

The LO signals from the receive VCO section drive the dividers for GSM 900 and DCS 1800 respectively to provide quadrature LO signals to the receive mixers. The LO signal is also supplied to the prescaler and transmit output buffer.

Figure 3-4 shows a block diagram of the LO block.

Figure 3-4. Block diagram of the LO part.

- 77 -

3. TECHNICAL BRIEF

D. VCO Block

The VCOs are fully integrated balanced LC oscillators with on-chip resonators. The receive VCOs run on double frequency.

Different frequency ranges can be selected in the VCOs for GSM/DCS band operation.

The VCOs are supplied from a separated external voltage regulator to avoid frequency pushing and up conversion of low frequency noise. A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency.

Figure 3-5 shows a block diagram of the VCO block.

Figure 3-5. Block diagram of the VCO part.

- 78 -

3. TECHNICAL BRIEF

E. PLL Block

The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection and transmitter modulation is controlled via the prescaler modulus inputs MODA ~ MODD and the prescaler offset value N offset. The MODA ~ MODD signals could be delayed 0, 5, 10 or 15 ns with

MD bits to be synchronized with the XO signal.

Figure 3-6 shows a block diagram of the PLL block.

Figure 3-6. Block diagram of the PLL part.

- 79 -

3. TECHNICAL BRIEF

3.7.2 Transmitter

A 4-bit sigma-delta bit stream comes from the Marita ASIC including both channel information and the

GMSK phase information. Via the 3-wire control bus also driven from Marita, the selection of transmitter band is made. The 4bits from the bit stream provides the fine-tuning of the division ratio before going to the divider of the used VCO (low band, 900MHz or high band, 1800MHz).

The modulated VCO signal is fed to the output buffer. One buffer is available for each of the low and high bands. Trimming capability is included for best match versus the PA used.

The GSM/GPRS transceiver, Ingela, output is passed to the dual-band PA that after amplification feeds the signal via a low pass filter to the antenna switch and further to the antenna.

The transmit block consists of two differential high power transmit output buffers with controllable output power. The modulated transmit signal from the VCO buffer is amplified to a level suitable to drive the external power amplifier. The buffer outputs are of open collector type and must be terminated into a suitable load.

Figure 3-7 shows a block diagram of the transmitter block.

Figure 3-7. Block diagram for the transmitter.

- 80 -

3. TECHNICAL BRIEF

A. Power Amplifier

The Power Amplifier (N1300) is intended for use in EGSM and DCS/PCS mobile equipment. It is a module with two parallel amplifier chains, with one chain for the EGSM transmitter section and one for the DCS/PCS transmitter section. Each chain amplifies the RF signal from the respective transmitter to the antenna. The power amplifier supports class 10.

Band selection and the output power level of the RF amplifier are controlled by discrete signals Vband and Vapc respectively from the digital baseband controller ASIC.

Figure 3-8. Block diagram of the Power Amplifier with Two Parallel chains.

- 81 -

3. TECHNICAL BRIEF

3.8 WCDMA Mode

3.8.1 Receiver

The received RF signal on the antenna connector arrives via the antenna switch to the duplexer. The duplexer directs the signal to the LNA, which resides in Wopy (W-CDMA Receive ASIC) as every other active part of the radio receiver. The LNA has two different gain settings. From the output of the LNA, the signal is fed to the input of a RF SAW filter, and then appears at the differential output of the filter.

The differential output of the RF SAW filter is connected to the differential mixer input, and the received signal is down-converted to a 190MHz IF frequency (with the RFLO signal) by the mixer.

At 190MHz, the signal is filtered in a differential (input and output) IF SAW filter, with the approximate bandwidth of 4MHz, and then again the signal is fed to Wopy (W-CDMA Receive ASIC), this time to the differential IF input, which also has a LNA.

From the 190MHz, the signal is mixed down to base-band I and Q which represented signals (using the IFLO signal). Finally the signals are filtered in low pass filters and amplified in base-band VGAs.

The I and Q represented signals appear at the output of Wopy (W-CDMA Receive ASIC) as differential voltages.

The large signal gain provided by the processing steps from the antenna down to base-band gives a

DC offset at the outputs of Wopy (W-CDMA Receive ASIC). To eliminate this, there are DC-offset compensation loops included, one in the VGA of each of the I and the Q signals.

A. IFLO Section

The balanced IFLO signal from an external IFVCO drives the divider to provide qaudrature LO signals to the RxIF mixers. The LO buffers amplifies the signal to a suitable amplitude and DC level to drive the RxIF mixers.

Figure 3-9. Block diagram of the IFLO section.

- 82 -

3. TECHNICAL BRIEF

B. RFLO Section

The VCO is a fully integrated balanced LC oscillator with on-chip resonator. An on-chip varactor is used to control the frequency over the desired tuning range.

A separate external voltage regulator supplies the VCO with power to avoid frequency pushing and up conversion of low frequency noise. A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency. Via the serial interface, the

VTUNE voltage can be set to VCC/2 to check the center frequency of the VCO. The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection is set via the serial interface.

Figure 3-10. Block diagram of the RFLO section

- 83 -

3. TECHNICAL BRIEF

C. Reference Section

The reference block consists of a balanced oscillator and a buffer amplifier. The crystal unit and the feedback capacitors are external. The current consumption when only the reference oscillator and the output buffer are activated must be kept to an absolute minimum.

Figure 3-11. Block diagram of the Reference section.

- 84 -

3. TECHNICAL BRIEF

3.8.2 Transmitter

Analogue differential signals (currents), representing I and Q, are sent to the radio ASCI Wivi (W-

CDMA Transmitter ASIC) from the D/A converter in Wanda (W-CDMA digital base-band coprocessor

ASIC). The signals are filtered in a reconstruction filter and then modulated up to 380MHz (using the

IFLO signal). The signal is then amplified in a VGA and filtered in an external filter (an LC filter). After filtering, the signal is mixed to its final frequency (using the RFLO) and amplified in a differential output

RF buffer with two different gain settings (high gain or low gain).

The differential RF signal is fed into a SAW filter with a single ended output, and is then amplified in a stand-alone RF buffer. After the RF buffer, the signal is filtered again in a SAW filter before it is fed to the PA (Power Amplifier).

In the PA the signal is amplified for the last time before leaving the radio. After the PA, the signal is sent through an isolator and through the duplexer, which directs the transmit signal to the antenna connector via the antenna switch.

The PA has variable supply voltage, which adapts itself by means of a control loop so that the linearity of the PA is kept constant. The variable supply voltage is provided from the battery through a DC/DC converter and a signal linearity detector sits at the PA output. The detected signal at the PA output is compared with a reference (supplied by the Vincenne, the mixed-signal circuit ASIC), and the error signal is used in a loop filter, which provides the control signal to the DC/DC converter.

A. Reconstruction Filters

The reconstruction filters consist of input buffers that provide the correct DC biasing for the preceding

DAC in the digital baseband controller, and a low-pass filter for removing the unwanted high frequency components from the baseband input waveform.

The filter inputs are adapted for use with a current-source type of input signal.

B. IQ-modulator

The IQ-modulator receives the incoming I and Q analog baseband signals at baseband frequency and converts them to an intermediate frequency of 380MHz.

C. Variable Gain Amplifier (VGA)

Comprising two cascaded variable gain amplifiers, the VGA-together with the RF mixer- controls the power of the transmitter.

The first of these two amplifiers, the so-called QVGA, enables fine-tuning of the transmitter by varying the gain in 0.25dB steps, that is 0/0.25/0.5/0.75dB. The second amplifier provides a 54dB gain range in 1 dB steps (54steps = 55 levels).

- 85 -

3. TECHNICAL BRIEF

D. IF Band Bass Filter (IFBP)

The IF filter suppresses spurious signals and eliminates unwanted frequency components generated in the IQ modulator and subsequently amplified in the VGA. The filter is tuned using an external RLC load as shown in Figure 3-12.

Figure 3-12. Principle Schematic of the IFBP.

- 86 -

3. TECHNICAL BRIEF

E. RF Mixer and Buffer

The RF mixer converts the signal output from the IF BP filter from an intermediate frequency (IF) to the final radio frequency (RF). The mixer can be switched between three different gain levels: high gain

(HG), medium gain (MG), and low gain (LG).

The LO buffer provides the buffering for either an internal LO signal generated within the internal

RFPLL, or an external LO signal applied to the RFLO/RFLOBAR pins. External DC blocking is necessary for the external LO signal.

The RF buffer is used to drive an external PA stage. The buffer is of an open-collector design. The gain switching together with the VGA amplifier at IF will enable an output power control in 0.25 dB steps over no less than 80dB.

The programmable bias in the high and mid-gain settings is specified as a reduction of bias current from the maximum bias condition. It should achieve a reduction of bias current from the nominal value of 17mA to 3mA (signal ended) in 7 steps.

Figure 3-13. Block Diagram of RF Mixer and Buffer.

- 87 -

3. TECHNICAL BRIEF

F. Power Amplifier

The N1630(RF9266) is a high-power, high-efficiency linear amplifier module targeting W-CDMA transmitter ASIC. The module is fully matched to 50( for easy system integration and utilizes advanced

GaAs HBT process technology. The PA features an integrated RF power output detection network and is compatible with DC-DC converter operation in DC power management applications. Additionally, a variable bias-current allows the idle current to be adjusted for optimum performance at a given RF output power.

Figure 3-14. Block Diagram of W-CDMA power amplifier.

- 88 -

3. TECHNICAL BRIEF

3.8.3 Frequency Generation

The Wopy (W-CDMA Receive ASIC) contains the active elements for a 13MHz VCXO, which is designed to be the reference frequency of the UE.

There are two synthesizers in the W-CDMA part of the radio, an intermediate frequency (IF) synthesizer and a radio frequency (RF) synthesizer. They generate the Intermediate Frequency Local

Oscillator (IFLO) and Radio Frequency Local Oscillator (RFLO) signals. Both synthesizers are used in both the transmitter and the receiver, which gives the radio a fixed duplex distance of 190MHz.

The RF synthesizer is in the Wopy (W-CDMA Receive ASIC), except for the loop filter, which is external. The 13MHz clock is used as the reference, and the phase detector frequency is 200kHz. The programmable divider makes the RF synthesizer cover the 2300~2360MHz band.

The IF synthesizer is in the Wivi (W-CDMA Transmitter ASIC), except for the loop filter. The 13MHz is used as the reference, and the phase detector frequency is 1MHz. The IF VCO runs at 1520MHz given that the (programmable) reference divider is set to 13.

The synthesizers are controlled by Wanda (W-CDMA digital base-band coprocessor ASIC) via the serial bus to Wivi (W-CDMA Transmitter ASIC) and Wopy (W-CDMA Receive ASIC).

- 89 -

3. TECHNICAL BRIEF

A. IF PLL

The IF LO frequency synthesis comprises the four following parts:

- Input buffer: A 13MHz input buffer with DC-biasing provided at source.

- VCO: Operating on 1.52GHz which is 4times the TX-IF frequency (380MHz) and 8 times the RX-IF

(190MHz), this is a fully integrated balanced LC oscillator with on-chip resonator. On-chip varactor are used to tune the VCO frequency.

- Prescaler

- Phase-detector with charge pump

For maintaining check on the VCO center frequency, the tuning voltage is set to Vcc/2. External DC blocking capacitors must be used on the IFLO/IFLOBAR signals.

Figure 3-15. Block Diagram of Frequency Synthesizer Part(IF PLL).

- 90 -

4. TROUBLE SHOOTING

4. TROUBLE SHOOTING

4.1 Power ON Trouble

START

The vol tage of main battery is higher than 3.2V ?

Yes

Press END key.

Longer than 3 Seconds

Keypad LED ON?

END key oper ates wel l?

ONSWAn(C2621) level is low when END key press ed.

Yes

Follow the

LCD Trouble shooting guide

Charge or change main battery

Follow the keypad Trouble shooting guide

Check the voltage.

VCORE (R2210) 1.5V

VDIG (R2200) 2.8V

VMEM (R2201) 1.8V

VRTC (R2202) 1.5 V

VEXT1.5 (N22 03 Pin#3) 1.5V

VDD_A (R1810) 2.8 V

VDD_B (R1811) 2.8 V

Change main board

Yes

The phone should work

ONSWAn

N2000

C2621

- 91 -

4. TROUBLE SHOOTING

R2202

< Main Board - Top side >

N2203

Pin #3

R1810

R1811

R2210

R2201

R2200

< Main Board - Bottom side >

- 92 -

4. TROUBLE SHOOTING

4.2 USB Trouble

START

(Measure during t he state of

USB module running)

Input power(N2204, pin1) is 5V?

Yes

Output power(N2204, pin5) is 3.3V?

Yes

USBSENSE level is 2.8V?

Yes

VUSB(R3103) is 3.3V?

Yes

Change main board

No Check host USB port or USB cable

Resolder or change N2204

Resolder R2232 or R2233

Resolder R3103

USBSENSE

N2204 R2232 R2233 R3103

- 93 -

4. TROUBLE SHOOTING

4.3 SIM Detect Trouble

• SIM control path

- MARITA generates SIM interface signals(2.75V level) to VINCENNE.

- Vincenne converts SIM interface signals to 1.8V/3V.

START

Reconnect SIM card

SIM work well?

Resolder X2300 on main PCB and check the contact between X2300 and SIM card

Yes

SIM work well?

Change SIM card

Finish

SIM work well?

Change main board

Yes

Finish

X2300

- 94 -

4. TROUBLE SHOOTING

4.4 Keypad Trouble

• Keypad signals go to MARITA and VINCENNE through board-to-board connector.

START

Press the keypad

Keypad operates well?

Resolder X3200 on main board and CN962 on keypad

Yes

Finish

Keypad operates well?

Change Keypad

Yes

Finish

Keypad operates well?

Change main board

Yes

Finish

Pin # 2~#7

ONSWAn

KEYIN0

KEYIN1

KEYIN2

KEYIN3

KEYIN4

X3200

Pin #45~#50

KEYOUT5

KEYOUT4

KEYOUT3

KEYOUT2

KEYOUT1

KEYOUT0

Pin #12~#17

KEYOUT5

KEYOUT4

KEYOUT3

KEYOUT2

KEYOUT1

KEYOUT0

CN962

Pin #54~#59

ONSWAn

KEYIN0

KEYIN1

KEYIN2

KEYIN3

KEYIN4

- 95 -

4. TROUBLE SHOOTING

4.5 Camera Trouble

Camera control signals are generated by Marita

- 96 -

Camera control signals are generated by Marita

4. TROUBLE SHOOTING

- 97 -

4. TROUBLE SHOOTING

4.6 Main LCD Trouble

LCD control signals are generated by Marita.

- 98 -

4.7 Sub LCD Trouble

4. TROUBLE SHOOTING

- 99 -

4. TROUBLE SHOOTING

4.8 Keypad Backlight Trouble

- 100 -

- 101 -

4. TROUBLE SHOOTING

4.9 Folder ON/OFF Trouble

- 102 -

4. TROUBLE SHOOTING

VCAM

C3204

0.1u

R3206

100K

C3205

10p

CAMERA_DET

Be sure that magnet is here

- 103 -

4. TROUBLE SHOOTING

4.10 Camera Detection Trouble

- 104 -

- 105 -

4. TROUBLE SHOOTING

4.11 Camera Flash Trouble

- 106 -

- 107 -

4. TROUBLE SHOOTING

4.12 Audio Trouble Shooting

A. Receiver

• Signals to the receiver

– Receiver signals are generated at Vincenne

• BEARP, BEARM

– Receiver path :

• 1. Vincenne (BEARP, BEARM) ->

• 2. X3200 on main board ->

• 3. CN962 on key PCB ->

• 4. CN963 on key PCB ->

• 5. LCD Module ->

• 6. Receiver

• Note : It is recommanded that engineer should check the soldering of R, L, C along the corresponding path before every step.

- 108 -

4. TROUBLE SHOOTING

START

Connect the phone to net work

Equipment and setup call

Setup 1KHz tone out

Does the sine wave appear at R2619 ?

YES

Change t he m ain board

Change the Key boar d

Does the sine wave appear at Num ber 37,38 pin in the key Bíd CN963?

YES

Does the sine wave appear at EAR(+) PAD in LCD Module?

Change t he LCD module

YES

Is the soldering o t the receiv er OK?

YES

Can you hear sine wave out of the receiv er ?

END

YES

Resolder R eceiver

Change t he Receiver

- 109 -

4. TROUBLE SHOOTING

R2619

Pin 38, 39

CN963

- 110 -

4. TROUBLE SHOOTING

Measured 1khz Sine Wave Signal

- 111 -

4. TROUBLE SHOOTING

B. Speaker (Voice Loud Speaker, Midi, MP3, Key Tone)

• Signals to the speaker

– Speaker signals are generated at Vincenne

• BEARP

– Speaker path :

• 1. Vincenne (BEARP) ->

• 2. C2604 on main board ->

• 3. N2603(ADG) on main board ->

• 4. N2601(Audio Amp) on main board ->

• 5. CN963 on key PCB ->

• 6. LCD Module ->

• 7. Speaker

• Note : It is recommanded that engineer should check the soldering of R, L, C along the corresponding path before every step.

- 112 -

4. TROUBLE SHOOTING

START

Connect the phone to net work

Equipment and setup call

Setup 1KHz tone out

Does the sine wave appear at C2604 ?

YES

Does the sine wave appear at R2607 ?

Change t he main board

Resolder or change N2603

YES

Does the sine wave appear at R2621 ?

Change t he main board

YES

Does the sine wave appear at number 4 pin in key Bíd CN963 ?

Change the key B,d

YES

Does the sine wave appear at spk(+) pad in LCD module ?

YES

Can you hear sine wave out of the receiv er ?

END

YES

Change t he LCD Module

Change the Speake r

- 113 -

4. TROUBLE SHOOTING

C2604

R2621

R2607

Pin 4

40 1

N2603

CN963

- 114 -

4. TROUBLE SHOOTING

Measured 1khz Sine Wave Signal

- 115 -

4. TROUBLE SHOOTING

C. Microphone (Voice call, Voice Recorder, Video Recorder)

• Microphone Signal Flow

– MIC is enable by MIC Bias

– MICBAS, MICIP, MICIN signals to ABB ( Vincenne )

• Check Points

– Microphone bias

– Audio signal level of the microphone

– Soldering of components

• Signal from the mic

– MIC ->

– N2602(TJATTE2) on main board ->

– C2615 on main board ->

– Vincenne

- 116 -

4. TROUBLE SHOOTING

START

Check the MIC b ias l evel at the pad of MIC+(X2603)

Is the level o f M IC+ AND MIC-

2.2Volt ?

Yes

Change t he MIC

Yes

Check the signal level at C2615 at the putti ng

Audio signal in MIC

Yes

A few hundred of m V of the si gnal measured ?

Resolder C2615, C2617, C2616 and try again.

If fail again, chage the main Bíd

Yes

Change t he main B,d

Does it work p roperly ?

END

YES

- 117 -

4. TROUBLE SHOOTING

C2616

C2615

C2617

- 118 -

Measured Some Noise Signal

4. TROUBLE SHOOTING

- 119 -

4. TROUBLE SHOOTING

D. Headset Receiver (Voice call, Video Telephony, MP3)

START

Connect the phone to network

Equipment and setup call

Setup 1KHz tone out

Insert Head set.

Does the Headset ico n display on the main LCD?

YES

Does the sine wave appear at C2611,C2619 ?

YES

Does the level of R3381 under 0.5Volt ?

YES

Does the level of R2613 over 2.0Vo lt ?

Change t he main B,d

Resolde r R2613,R3397

R3381,R3303.

And try ag ain fr om the start

Does the sine wave appear at C3268,C3269 ?

YES

Resolder X2602 Pins or change the Head set

Change t he main B íd

Can you hear sine wave out of the re ceiv er ?

END

YES

Change t he main B íd

- 120 -

4. TROUBLE SHOOTING

E. Headset MIC(Voice call, Video Telephony)

START

Insert Head set.

Does t he Headset ico n display on the main LCD?

YES

Check the signal level at R3397 at the putting

Audio signal in MIC

A few hundred of m V of the signal measured at C2612 ?

YES

Change t he main B íd

Does the level of R3397 under 0.5Volt ?

YES

Does the level of R2613 over 2.0Vo lt ?

Change t he main B,d

Resolde r R2613,R3397

And try again from the start

Resolder C2613,

R3397 and try again.

If fail again,

Change t he m ain Bíd

Does it work p roperly ??

END

YES

Try again from the start

- 121 -

4. TROUBLE SHOOTING

R3381

X2602

C2610

R2613

C2619

C2611

C2612

R3397

C2613 8

- 122 -

4.13 Charger Trouble Shooting

4. TROUBLE SHOOTING

Figure. 13. Main Battery Charging Path

• Charging Procedure

- Connecting TA and Charger Detection

- Control the charging current by AB2000(Vincenne)

- Charging current flows into the battery

• Check Point

- Connection of TA

- Charging current path

- Battery

• Trouble shooting setup

- Connect TA and battery to the phone

• Trouble Shooting Procedure

- Check the charger connecter

- Check the Charging current Path

- Check the battery

- 123 -

4. TROUBLE SHOOTING

①

②

③

Figure. 14. Trouble Shooting - Charging

- 124 -

4. TROUBLE SHOOTING

③

②

Figure. 15. Main Board - I/O connector and FET

①

- 125 -

4. TROUBLE SHOOTING

4.14 RF Component

N1331 N1330 Z1100 Z1110

N1620

B1501

Z1500

N1700

Figure 4-1. RF component (Top)

Reference

B1501

Description

Temperature Sensor

B1770Crystal

N1101 GSM ADC

N1330GSM TX Balun

N1331 DCS TX Balun

N1400 WCDMA RX IC

N1620DC/DC Convertor

Reference

N1700

Z1110

Description

WCDMA TX IC

GSM RX SAW

Z1420WCDMA RX IF SAW

Z1500 WCDMA TX RF SAW

- 126 -

Z1420

Z1400

N1400

N1101

B1770

4. TROUBLE SHOOTING

W1001

N1002

N1000

V1001

N1300

Figure 4-2. RF component (Bottom)

Reference

N1000

N1002

N1300

Description

Ant. SW Module

Duplexer

GSM PAM

N1630WCDMA PAM

Reference

N1650

N1850

V1001

Description

Isolator

Regulator

Transistor

Test Connector

N1630

N1650

N1850

- 127 -

4. TROUBLE SHOOTING

4.15 Procedure to check

start

Oscilloscope settiong

1. Check

Power Source Block

2. Check

VCXO Block

3. Check

Ant. SW Module

Agillent 8960 : Test mode(WCDMA)

Ch. 9750 (Uplink)

Ch. 10700 (Downlink)

4. Check

WCDMA Block

Agillent 8960 : Test mode(GSM)

Ch. 62, P.L. 7 level setting

Ch. 62, -60dBm setting

5. Check

GSM Block

Redownload SW, Cal

- 128 -

4. TROUBLE SHOOTING

4.16 Checking Common Power Source Block

Step 3

WCDMA PAM Block

Step 1

Regulator Block

Step 2

GSM PAM Block

Vincenne Block

Power Source Block

Figure 4-3. Common Source Block(Bottom)

- 129 -

4. TROUBLE SHOOTING

4.16.1 Step 1

Check VBATI

(R1850)

LP39 81 I LD- 2.8

Figure 4-4. Regulator Block

R2216 R2215

Check Point

( C 3215 )

Step 1

Check Point (C3215) in

Power Source Block

To Check Power source to Check if main power source input or not

Check Point (R2215) in

Power Source Block

To Check Power source

Figure 4-5. Power Source Block

3.7V OK ?

Yes

Check Soldering

(C3215)

Yes

Change the Board

3.7V OK ?

Yes

Short?

Yes

Resoldering

Change the Board

See The Step 2

Check Soldering

(R2215 & R2216)

I n Power Source Block

Check (C3215 & R2215) in Block to check inner line connection

From R1805 to R2215

- 130 -

4. TROUBLE SHOOTING

4.16.2 Step 2

Step 2

Check VBATI (R1850) in Regulator Block

1 to

Check if main power source input or not

3.7V OK ?

Yes

See The Step 3

Check (R2215 & R1805) in Block

1, 5 to check inner line connection

From R1850 to R2215

Short?

Yes

Check Soldering

(R2215 & R2216)

In Power Source Block

Change the Board

- 131 -

4. TROUBLE SHOOTING

4.16.3 Step 3

GSM PAM

VBATI

(R1326)

L1300

Figure 4-6. GSM PAM Block

Step 3

Check VBATI (R1326) in GSM PAM Block

2 to Check if main power source input or not

3.7V OK ?

Yes

See The Step 4

Check L1300 to check if power source input or not

3.7V OK ?

Yes

Check L1300 & R1326 inner Line connection

Check (L1300 & R2215) in Block

2, 5 to check inner line connection

From L1300 to R2215

Short?

Yes

Change L1300

Short?

Yes

Check Soldering

(R2215 & R2216)

I n Power Source Block

Change the Board

- 132 -

4. TROUBLE SHOOTING

4.16.4 Step 4

R22 16

R22 15

WCDMA PAM

Figure 4-7. WCDMA PAM Block

VBATI

(R163 1)

Check Po int

( C32 15 )

Figure 4-7-1. PAM-Power Source

- 133 -

4. TROUBLE SHOOTING

Step 4

Check R1631 in WCDMA

PAM block

3.7V OK ?

Yes

See the Next Page

Shor t?

Yes

Check Soldering

(R2215 & R2216)

In Power Source Block

Change the Board

- 134 -

4. TROUBLE SHOOTING

VCCB

(R 181 1)

VCCA

(R 181 0)

Figure 4-8. Power for Radio ASIC

Ingela (N1100)

Vincenne

(N2000)

VDD_A

VDD_B

C1810

10u

2012

C1811

4.7u

R1810

R1811

C1802

10u

2012

VCCA

VCCB

Wopy (N1400)

Check Poin t

VCCA(R181 0)

Chec k Poin t

VCCB (R181 1)

2.75V OK ?

Yes

2.75V OK ?

Yes

Common I nput Power is OK

See The Next Part

Change the Board

Before Change,

Check soldering

- 135 -

4. TROUBLE SHOOTING

4.16.5 Checking Regular Part

LP3981ILD-2.8

Reg ulat or

V_ wi vi_B

(N1700)

V_ wi vi_A

(N1700)

Figure 4-9. Regulator Block

EXTLDO

( R1851)

Figure 4-10. Regular Circuit Diagram

Check Poin t

(R182 5)

(R182 6)

To Check Reg ulator

Out pu t Vol tage

2.8V OK ?

Yes

Regulator Circuit is OK,

See the next Page

Point High

Yes

Check EX TL OD

Point

To Check regulator e nable signal

Change The Regulator

Change the Board

- 136 -

4. TROUBLE SHOOTING

4.17 Checking VCXO Block

The reference frequency (13MHz) from B1770 (Crystal) is used WCDMA TX part, GSM part and BB part. Therefore you have to check below 4 point.

Check 3

Chec k 2

Figure 4-12. Top Place

Check 4

Check 1

Figure 4-13. Connection for Checking VCXO Block

- 137 -

4. TROUBLE SHOOTING

Check 1. Crystal part

If you already check this crystal part, you can skip check 1.

Figure 4-14. Test Point (Crystal Part)

Figure 4-15. Schematic of the Crystal Part

Figure 4-16. 13MHz at B1770.3

- 138 -

Check 2,3 13MHz at WCDMA TX part and GSM part

4. TROUBLE SHOOTING

N1770.B1

N1770.C1

N1100.K9

Figure 4-17. Test point (13MHz at TX Part)

Figure 4-18. 13MHz at N1770.B1 and N1100.K9

- 139 -

4. TROUBLE SHOOTING

Check 4. 13MHz at BB part

N1400.C1

Figure 4-19. Test Point (13MHz at BB Part)

Figure 4-20. Schematic (13MHz at BB Part)

Figure 4-21. 13MHz at N1400.C1

- 140 -

- 141 -

4. TROUBLE SHOOTING

4.18 Checking Ant. SW Module Block

ANTSW2

ANTSW1

ANTSW0

ANTSW3

LMSP

-0064

(N1000)

Figure 4-20. Antenna Switch Block(Bottom)

- 142 -

4. TROUBLE SHOOTING

4.19 Checking Antenna Switch Block input logic

4.19.1 Mode Logic by TP Command

Low

EGSM Rx

MODE=0

SWRX=64 ,10 24 ,2

Low

EGSM Tx

MODE=0

SWTX=1, 64, 7,1 024 ,1

Low

DCS Rx

MODE=2

SWRX=699,1024,2

DCS Tx

MODE=2

SWTX=1,699,0,1024, 1

Low

- 143 -

4. TROUBLE SHOOTING

ANTSW1

ANTSW2

ANTSW3

Low

WCDMA Mode

MODE=4

WTXC=9750,0,1,

SYCT=1 07 00

TXGN=1,43

Band

EGSM Tx

EGSM Rx

DCS Tx

DCS Rx

WCDMA

ANTSW0

ANTSW1

Table 4-1. Antenna Switch Module Logic

ANTSW2

ANTSW3

- 144 -

4. TROUBLE SHOOTING

4.19.2 Checking Switch Block power source

❈ Before Checking this part, must check common power source (through Vincenne) part

TP Comma nd

MODE=0

SWRX= 64,1024,2

C heck Soldering .

It is necessary to c heck shor t co nditi on.

Using Tester, Che ck 4 resistor

ANTSW0(R1 003 ),ANTSW1( R10 04),

ANTSW2(R1 005 ),ANTSW3( R10 06)

Open?

Yes

Check A NTSW0(R1003)

To check Sw itch i np ut power source.

High

Yes

OK?

Yes

Check soldering

(R1003)

Resoldering

Check each mode

by TP command

Change the Board

- 145 -

4. TROUBLE SHOOTING

A. EGSM Rx Mode

ANTSW1

ANTSW2

ANTSW3

Low

EGSM Rx

MODE=0

SWRX= 64, 10 24 ,2

Figure 4-21. EGSM Rx Mode

EGSM Rx

Logic OK?

Yes

See the Next mode

(EGSM Tx Mode)

4. 4. 1 part C heck

OK?

Yes

Change the Board

Try 4.4.1 part

- 146 -

4. TROUBLE SHOOTING

B. EGSM Tx Mode

ANTSW1

ANTSW2

ANTSW3

Low

High

EGSM Tx

MODE=0

SWTX= 1,6 4, 7, 102 4, 1

Figure 4-22. EGSM Tx Mode

EGSM Tx

Logic OK?

Yes

See the Next mode

(DCS Tx Mode)

4.4.1 part Check OK?

Yes

ANTSW1 : Low

ANTSW2 : Low

ANTSW3 : Low

Yes

Change V1001

Try 4.4.1 part

Change the Board

- 147 -

4. TROUBLE SHOOTING

C. DCS Rx Mode

ANTSW1

ANTSW2

ANTSW3

High

Low

DCS Rx

MODE= 2

SWRX=6 99 ,1 02 4,2

Figure 4-23. DCS Rx Mode

DCS Rx

Logic OK?

Yes

See the Next mode

( DCS Tx Mode)

4.4. 1 p ar t Check

OK?

Yes

Change the Board

Try 4.4.1 part

- 148 -

4. TROUBLE SHOOTING

D. DCS Tx Mode

ANTSW1

ANTSW2

ANTSW3

Low

High

Low

DCS Tx

MODE=2

SWTX= 1,6 99 ,0 ,1 02 4,1

Figure 4-24. DCS Tx Mode

DCS Tx

Logic OK?

Yes

WCDMA Mode

4.4. 1 p ar t Check

OK?

Yes

Change the Board

Try 4.4.1 part

- 149 -

4. TROUBLE SHOOTING

E. WCDMA Mode

ANTSW1

ANTSW2

ANTSW3

Low

WCDMA Mode

MODE=4

WTXC=9 75 0, 0,1, 0

SYCT= 107 00

TXGN=1,4 3

Figure 4-25. WCDMA Mode

WCDMA

Logic OK?

Yes

I nput Signal and Power to

Antenna Switch Block is OK.

See the Next Pa ge

4.4. 1 p ar t Check

OK?

Yes

Change the Board

Try 4.4.1 part

- 150 -

4. TROUBLE SHOOTING

4.20 Checking WCDMA Block

start

1. Check VCXO Block

2. Check Ant. SW

Module

3. Chec k Contr ol Signa l

4. Check RF Tx Level

5. Check PAM Block

6. C hec k Rx IQ

7. C heck RF Rx Level

Redo wnload SW, Cal

③

⑤

- 151 -

⑦

①

⑥

4. TROUBLE SHOOTING

4.20.1 Checking

Refer to 4.4

4.20.2 Checking Ant. SW module

Refer to 4.5

4.20.3 Checking Control Signal

First of all, you have to check control signal. (data, clk, strobe)

Figure 4-28. Test Point (Control Signal)

TP 1402(CLK)

TP 1402(DATA)

TP 140 2(STROBE)

Figure 4-29. Schematic (Control Signal)

- 152 -

4. TROUBLE SHOOTING

Figure 4-30. Connection for Checking Control Signal

- 153 -

4. TROUBLE SHOOTING

TP1403(STRO BE)

TP1401(DATA)

TP1402(CLK)

TP1403(STRO BE)

TP1401(DATA)

TP1402(CLK)

Figure 4-30. Control signal

- 154 -

4. TROUBLE SHOOTING

4.20.4 Checking RF TX Level

Check 3

N1002.Ant

Check 1

W1001

Check 2

N1000.8

Check 4

N1650.Out

Check 7

Z1500.2

Check 5

N1650.In

Check 6

N1630.21

Figure 4-31. Test Point (RF TX Level)

- 155 -

4. TROUBLE SHOOTING

Figure 4-32. Connection for Checking RF TX Level

- 156 -

4. TROUBLE SHOOTING

To verify that the phone fulfils requirements on maximum output power.

- 157 -

4. TROUBLE SHOOTING

4.20.5 Checking PAM Block

Rosalie

VBATI

(R162 9)

WD CDCREF

(R1621)

WPAREF

(R 1617)

WCDMA

PAM(N1630)

Wivi in put

(R1605 )

WPA ( R1630) fro m Rosalie

Step1: Check PAM(N1630) control signal from N2000

Step2: Check PAM(N1630) control signal from N1620

❈ Before Checking this part , must check 4.2 Common power source(Battery Direct) part

- 158 -

4. TROUBLE SHOOTING

TP Command

-mode =4

-Wtxc=9750,0,1,0

-Syct=10700

-Txgn=1,43

-TFTI=10700

Step1: Check PAM control signal from N2000

Check R16 17

To Check PAM con trol signal from Vi nce nne

(WP A R EF)

Mean Value

2.4V ?

Yes

Change the Board

Before Change board,

Check soldering(R1617)

See the Step 2

- 159 -

4. TROUBLE SHOOTING

TP Command

-mode =4

-Wtxc=9750,0,1,0

-Syct=10700

-Txgn=1,43

-TFTI=10700

Step2: Check PAM control signal from DC/DC converter(N1620)

Check R16 03

To Check PAM VCC BIAS fr om DC/ DC co nver tor

(V CC WPA )

Mean Value

2.4V ?

Yes

Check The DC/ DC convertor(N1620) Part

Change the PAM

Mean Value

Check R16 21

To Check DC /DC conver tor co ntrol si gnal

From Vincen ne(N2000)

(WDCDCREF)

2.5V ?

Yes

Mean Value

Change the DC/DC

Converter

Before Change board,

check soldering VBATI(R1631)

Change the Board

Before Change board,

Check soldering(R1621)

- 160 -

4. TROUBLE SHOOTING

TP Command

-mode =4

-Wtxc=9750,0,1,0

-Syct=10700

-Txgn=1,43

-TFTI=10700

23dBm ?

Check Duplex output

(C1012)

Yes

To Check PAM output

WCDMA PAM i s OK

See t he Next page

Check R1605

To Check PAM Input level

Check R1617

To Check PAM control signal from

Vincenne(N2000)

(WPAREF)

Check R1603

To Check PAM VCC BIAS from DC/DC convertor(N1620)

(VCCWPA)

Level

< -10 dBm?

Yes

Level

>2 dBm

Yes

2.5V ?

Yes

3.4V ?

Yes

Change The

PAM (N1630)

Download the SW

& Calibrate

Check the WCDMA RF

Tx Chip(Wivi)

Check the Vincenne to WCDMA PAM Signal line

2.5V ?

Change the Rosaili

- 161 -

4. TROUBLE SHOOTING

4.20.6 Checking RX I,Q

To verify the RX path you have to check the pk-pk level and the shape of the RX I,Q.

N1400.A7 (RXQA)

N1400.A8 (RXQB)

N1400.A9 (RXIA)

N1400.A10 (RXI B)

Figure 4-33. WCDMA RF RX IC (Top)

Figure 4-34. RX I,Q signal (CW:2142MHz)

Figure 4-35. RX I,Q signal (CW:2141MHz)

- 162 -

Figure 4-36. RX I, Q signal

4. TROUBLE SHOOTING

- 163 -

4. TROUBLE SHOOTING

4.20.7 Checking RX Level

Checkt 1

N1002.Ant

Check 2

N1400.H1

Check 3

N1400.B1

Figure 4-37. Peak level at N1400.B1

Figure 4-38. Connection for Checking RX Level

- 164 -

- 165 -

4. TROUBLE SHOOTING

4.21 Checking GSM Block

start

1. Check Regulator

Circ uit

2. Check VCXO

Bloc k

3. Check Ant. SW

Modu le

4. Chec k Control

Signal

5. Chec k RF Tx Path

6. Chec k RF Rx Path

Redow nload SW, Cal

④

⑤

⑥

④

②

- 166 -

4. TROUBLE SHOOTING

4.21.1 Checking Regulator Circuit

Refer to chapter 4.3 Checking Common Power Source Block.

IF you already check this point while Checking Common Power Source Block, You can skip this test.

4.21.2 Checking VCXO Block

Refer to chapter 4.4 Checking VCXO Block.

IF you already check this point while Checking VCXO Block, You can skip this test.

4.21.3 Checking Ant. SW Module

Refer to chapter 4.6 Checking Antenna Switch Block input logic.

IF you already check this point while Checking Antenna Switch Block input logic, You can skip this test.

- 167 -

4. TROUBLE SHOOTING

4.21.4 Checking Control Signal

Test Program Script

MODE=0

SWTX=1,64,7,1024,1

VCCA

(C1330)

VCCA

(L1200)

LPF block

TXON

(R1333)

RADSTR

(T P1203)

RADDAT

(T P1202)

RADCLK

(TP1201)

Vtune

(C1223)

VCCA

(L1120)

VCCA

(L1202)

RADSTR

RADCLK

RADDAT

TXON

Vtune

Figure 4-39. GSM RF Control signal

- 168 -

4. TROUBLE SHOOTING

Check TP1201,TP1202,TP1203

Check if there is any major difference.

Refer to left side of Figure 4-35 .

Simiar?

Yes

Check the short status between TP1201~TP1203

Short?

Redownload SW

Yes

Change t he board

Check R1333,C1223.

Check if there is any major difference.

Refer to right side of Figure 4-35

Similar?

Yes

Control signal is OK.

See next page to check.

Check voltage of L1120,L1200,L1202,R1335

Vcca=2.7V?

Resoldering Vcca block

(L1120,L1200,L1202,R1335)

Yes

Resoldering LPF block

- 169 -

4. TROUBLE SHOOTING

4.21.5 Checking RF Tx Path

A. GSM Tx path Level

Figure 4-40. GSM/DCS Tx Path Level

- 170 -

1

4. TROUBLE SHOOTING

5'

5

Figure 4-41. Test Point of GSM/DCS Tx path

N1300

- 171 -

4. TROUBLE SHOOTING

B. GSM Tx Output Level Check

Figure 4-42. GSM Tx Level at

Test Program Script

1. GSM Tx

MODE=0

SWTX=1,64,5,1024,1

2. DCS Tx

MODE=2

SWTX=1,699,0,1024,1 v. Agilent 8960 setting

: GSM BCH+TCH mode v. Oscilloscope setting

Check GSM/DCS output power at ①.

Check if there is any Major difference.

Refer to Figure 4-42 .

GSM > 32dBm

DCS > 29dBm

Similar?

Yes

GSM/DCS Tx Path OK.

See chapter 4.8.6

to check Rx path

See next page to check Tx path

- 172 -

4. TROUBLE SHOOTING

C. GSM RF Transceiver IN/OUT Signal Check

N1331

②

MODA

(R1213)

MODB

(R1212)

MODC

(R1211)

MODD

(R1210)

④

DCS Tx

(R1341)

GSM Tx

(R1338)

N1330

GSM Tx

(L1330)

DCS Tx

(L1331)

③

MODA

MODB

Figure 4-43. GSM Tx MODE signal

Check Mode(A/B/C/D)signal at

②.

Check if there is any Major difference.

Refer to right side of Figure 4-43 .

Simiar?

Yes

Resoldering MODE block

(R1210,R1211,R1212,R1213)

Check GSM RF Transceiver

Output power at

③

Check GSM/DCS Tx Balun output power at ④ .

GSM/ DCS

>- 5dBm

Yes

GSM/DCS

>- 7dBm

Yes

Redownload SW

Resoldering Tx Balun

GSM : N1330

DCS : N1331

See next page to check Tx path

- 173 -

4. TROUBLE SHOOTING

D. GSM PAM Check

GSM Tx

(C1341)

DCS Tx

(C1352)

Vapc

(C1327)

APC block

TXON

Vapc (GSM)

TXON

Vapc (DCS)

Figure 4-44. GSM/DCS Tx control signal

Check Vapc level.

Check if there is any Major difference. V apc > 1 .5 V ?

Refer to Figure 4-44 .

Y e s

N o

Resolderin g APC block

N o

Check GSM/DCS PAM output power at ⑤ .

G SM: > 23dBm

D C S: > 20dBm

Y e s

GSM Tx Pat h OK. See N ext p ag e t o ch eck

C hang ing GSM PAM

( N1 3 00 )

- 174 -

4.21.6 Checking RF Rx Path

A. GSM Rx path Level

4. TROUBLE SHOOTING

Figure 4-45. GSM/DCS Rx Path Level

- 175 -

4. TROUBLE SHOOTING

Z1110 Z1100

N1100

N1101

Test Program Script

1. GSM Rx

MODE=0

SWRX=64,1024,2

2. DCS Rx

MODE=2

SWRX=699,1024,2 v Agilent 8960 Setting

CW Mode

GSM : -50dBm@Ch65(948MHz)

DCS : -50dBm@Ch700(1842.8MHz) v Oscilloscope Setting

- 176 -

③

②

①

4. TROUBLE SHOOTING

B. GSM I/Q Signal Check

Idata

(TP1142)

Qdata

(TP1141)

DCLK

(TP1143)

VDIG_HERTA

R1150

I Data

Q Data

DCLK

Figure 4-46. Herta IQ data and DCLK

QRB

QRA

IRB

IRA

Figure 4-47. Ingela IQ signal

- 177 -

QRB

(R1103)

QRA

(R1104)

IRB

(R1105)

IRA

(R1106)

4. TROUBLE SHOOTING

QRB

QRA

Figure 4-48. Ingela IQ signal

Check GSM/DCS Rx IQ data at

Check if there is any Major difference.

Similar?

Refer to Figure 4-46.

Yes

Check GSM/DCS Rx IQ signal

Refer to Figure 4-47.

Similar?

Yes

Check GSM/DCS Rx IQ signal level at

Refer to Figure 4-48.

IQ signal

: 200mV ?

Yes

GSM Rx path OK.

VDIG_HERTA= 2.7V?

Yes

Redownload SW

Resoldering Vcca block

(L1120,L1200,L1202,R1335)

Resoldering R1150

See next page to check Rx path

- 178 -

C. GSM RF Level Check

Z1100

4. TROUBLE SHOOTING

③

Z1110

Figure 4-49. GSM/DCS Rx Path

v Agilent 8960 Setting

CW Mode

GSM : -50dBm@Ch65(948MHz)

DCS : -50dBm@Ch700(1842.8MHz)

Check GSM/DCS Rx signal level at ③ .

GSM:-51.5dBm

DCS:-51.5dBm

Yes

Change Ant. SW module (N1000)

GSM Rx path OK.

- 179 -

5. BLOCK DIAGRAM

5. BLOCK DIAGRAM

5.1 GSM & WCDMA RF Block

UMT S IF Filter

Z1420

T es t Conn.

W1001

Du plex er

N1002

UMT S PAM

N1630

DC DC

N1620

V arac tor

V 1770

Crys tal - 13M

B 1770

DCS Rx Filter

Z 1100

GSM PAM

N130 0

GSM RX Filter

Z 1110

DCS Balun

N1331

GSM Balun

N1330

Figure 5-1. RF Block Diagram

- 180 -

5. BLOCK DIAGRAM

Block

Common

WCDMA

GSM

Ref. Name

N1000

Part Name

LMSP-0064

W1001 KMS-507

B1770TSX-8A

N1002 DFYK61G95LBNCB

LZT-108-

N1400

Z1400

5323(WOPY)

LK20A

Z1420TMX-M453

Function

Switch

Test Connector

Crystal

Duplexer

Receiver

RX RF Filter

RX IF Filter

DC/DC

PAM

Isolator

N1630RF9266

N1650 CEO0401G95DCB

N1700

LZT-108-

5322(WIVI)

Z1500

D2006

Z1100

SX-S205B

ROP-101-3033

(WANDA)

B7714

Transmitter

TX RF Filter

Analog

Baseband

DCS RX Filter

Comment

Band select

Calibration, etc

Reference –13M

TRX

Direct Conversion

N1100

LZT-108-5325

(INGELA)

N1300 CX77304

N1330LDB21897M15C

N1331 LDB211G8020C

POP-101-3035

D2000

(MARITA)

Transceiver

PAM

GSM Balun

DCS Balun

Modem

TRX

GSM/DCS Dual

Table 5-1. RF Block Component

- 181 -

5. BLOCK DIAGRAM

5.2 Interface Diagram

13M _ M CLK

Figure 5-2. Interface Diagram 1

- 182 -

5. BLOCK DIAGRAM

Function Block

13M

32K

Signal

Control

Bus

Name

13M_MCLK

13M_R

RFLO

IFLO

32K

W-RF RX

W-RF TX

G/D-RF RX

G/D-RF TX

I/Q_WR

I/Q_WT

I/Q_GA

I/Q_GD

SW Ctrl

G-Band SEL

W-PA Ctrl

G-PA Ctrl

Pctl

VCXO Ctrl

RXON

TXON

Bus_W

Bus_G

Bus-G/WPA

Schematic_Signal

Name

Function

MCLK

XOOA/XOOB

RFLO/RFLOBAR

IFLO/IFLOBAR

RTCCLK

WCDMA_RX

WCDMA_TX

GSM_RX/DCS_RX

Main clock to BB

Ref for PLL

RF LO Generation

IF LO Generation

Real Time

RX RF signal

TX RF signal

RX RF signal

GSM_TXDCS_TX

RXIA/RXIB/RXQA/RXQB

TXIA/TXIB/TXQA/TXQB

IRA/IRB/QRA/QRB

RX RF signal

WCDMA RXIQ

WCDMA TXIQ

GSM RX analog

IDATA/QDATA

ANTSW0/1/2/3

GSM RX digital

Band/System switch

BSEL0GSM/DCS switch

WPAREF PAM Ref. Bias

PAREG

PCTL

VCXOCONT

RXON

TXON

WDAT/WCLK/WSTR

RADDAT/RADCLK/RADSTR

DACDAT/DACCLK/DACSTR

Power control

TX power control

AFC

RX block ON

TX block ON

PLL program

TX Gain program

Table 5-2. Interface Signal Block

- 183 -

5. BLOCK DIAGRAM

5.3 Detailed Interface Signal

RF

Co mmo n

AN TS W [3..0]

Reg. O n/Off for S wi tch/ GS M

GSM / GPRS

Inge la / He rta

I2C D A T

I2C C LK

MC LK

R ES ETB

QD ATA

IDA TA

DC LK

RX ON

S TROB E

DA TA

CLK

BS EL

MO D [D..A ]

P ULS ES KIP

PC TL

TX ON

VLOOP

GSM / GPRS

PAM

UM TS

Co mmo n

BS EL

PAS ENS E+

PAS ENS E-

PAR EG

DA TA

CLK

S TROB E

AD CS TR

RTEMP

UM TS

Wo py

UM TS

Wiv i

UM TS

PAM

IRA / B

QR A /B

R EFO N/XO OO N

WR FLO OP

MC LK

VC XO CO N T

IIN / IINB AR

QIN / Q INBA R

WIFLOOP

WD CD C R EF

WPA R EF

WPOW ERS ENS E

Figure 5-3. Interface Diagram 2

AN TS W [3..0]

Baseband

I2CS D A (Combi ne to Vince nne)

I2CS C L (Combine to Vince nne )

S YS C LK2

R ES ETon (R ES O UT3)

QD ATA

IDA TA

DC LK

RX ON

R FS TR

R FD A T

R FC LK

BS EL0

D IR MO D [D..A]

P ULS ES KIP (GP IO03)

PC TL

TX ON (C ombine to Vincenne )

CLKR EQ

M arita

VLOOP (GPA2)

PAS ENS E+

PAS ENS E-

PAR EG / IO UT

Vince nne

Radi o_D A T

Radi o_C LK

Radi o_S TR

Wa nda

AD_S TR (C ombine to Vincen ne / Marita)

IRA / B

QR A /B

IIN / IINB AR

QIN / Q INBA R

WR FLO OP (GP A4)

VC XO CO N T (D A C03)

WD CD C R EF (D AC01)

WPA R EF (D A C02)

WPOW ERS ENS E (GP A3)

WIFLOOP (GPA6)

EX TLDO

RTEMP (GP A0)

Vince nne

CLK (to Vincenne / W an da)

MC LK (to Vince nne / Wan da / Mari ta)

- 184 -

Figure 5-4. Power Diagram

- 185 -

5. BLOCK DIAGRAM

6. DISASSEMBLY INSTRUCTION

6. DISASSEMBLY INSTRUCTION

- 186 -

- 187 -

6. DISASSEMBLY INSTRUCTION

- 188 -

- 189 -

6. DISASSEMBLY INSTRUCTION

- 190 -

- 191 -

6. DISASSEMBLY INSTRUCTION

- 192 -

- 193 -

6. DISASSEMBLY INSTRUCTION

7. DOWNLOAD

7. DOWNLOAD

The Purpose of Downloading Software

• To make a phone operate at the first manufacturing

– A phone = Hardware + Software

– A phone cannot operate with hardware alone.

– The hardware with the suitable software can operate properly.

• To upgrade the software of the phone

– The software of the phone may be changed to enhance the performance of the phone.

– The older version software of the phone can be replaced to the newer version.

• Download Tools

FlashRW : Download tool for U81X0 software

Download Environment Setup

U81X0 UART data cable

USB cable

U81X0 Download can be done via UART & USB

- 194 -

7. DOWNLOAD

U81X0 Download (1) – FlashRW configuaration

1. Execute FLASHRW.exe.

2. Press the “Global Settings” on the top menu to configure FlashRW environment

- 195 -

7. DOWNLOAD

U8120 Download (2) – FlashRW configuaration

3. Select Loader File for Product.

You can use browse button to select Loader File.

You must select only U8120_CXC1325712_R2H(R5E_Signed by cust_brown).pldr for U8120.

You may select any loader of 3 loaders in loader folder for U8120.

Loader File is provided with FlashRW.

4. Select Port configurations for both RS232 Port and USB Port.

Baudrate should be 115200bps.

You have to do FlashRW configuration only at the first time of installation

- 196 -

U81X0 Download (3) – Phone Model Selection

1. Press Button for Model.

2. Select Model to download images

7. DOWNLOAD

- 197 -

7. DOWNLOAD

U81X0 Download (4) – Download file selection

1. Press “Add” button to select LGE SSW files to download.

2. Press “Add1” button to select LGE GDFS file to download.

Click to select file

<Before Select>

U81X0 download file is selected

- 198 -

<After Select>

U81X0 Download (5) – Connect & Download

1. Click on connector icon ( ) to connect to the phone

Check the Dialog Box that say “Please,switch on the target”.

2. Connect the phone to PC via Cable for Downloading.

Phone should be turned off.

3. Turn the phone on to connect to PC.

7. DOWNLOAD

- 199 -

7. DOWNLOAD

U81X0 Download (6) – USB Driver Install

1. If you use FlashRW Tool firstly, Error will happen because of USB Driver uninstalled.

You have to do FlashRW USB Driver Installation only at the first time of installation

- 200 -

7. DOWNLOAD

U81X0 Download (7) – USB Driver Install

2. Push “the Next Button” in Found New Hardware Wizard

3. Select “Search for a suitable driver for my device” in Found New Hardware Wizard

- 201 -

7. DOWNLOAD

U81X0 Download (8) – USB Driver Install

4. Select “Specify a location” in Found New Hardware Wizard

5. Push “the Browse Button” , and then select “USB driver Information file”

This File is provided with FlashRW.

- 202 -

U81X0 Download (9) – USB Driver Install

6. Push “the Next Button” in Found New Hardware Wizard

7. Push “the Finish Button” in Found New Hardware Wizard

7. DOWNLOAD

- 203 -

7. DOWNLOAD

U81X0 Download (10) – USB Driver Install

8. Close FlashRW.exe

9. Remove & Insert Main battery to reset the phone

% This action for USB Driver Install is done only at the first time of installation

If you want to download Software, just do as same as U81X0 Download (5) – Connect & Download says

- 204 -

U81X0 Download (11) – Connect & Download

7. DOWNLOAD

< While Downloading >

- 205 -

< After Downloading finished >

7. DOWNLOAD

U81X0 Download (12) - Trouble shooting

• Check these questions when trouble happens.

1. Check if UART & USB Port configuration is right.

2. Do not change RS-232 baud rate(115200BPS). It is fixed and never changed.

3. Check if UART & USB Cable is connected.

- 206 -

8. CALIBRATION

8. CALIBRATION

8.1 General Description

This document describes the construction and the usage of the software used for the calibration of

LG’s GSM/GPRS/WCDMA Multimedia Mobile Phone (U8120). The calibration menu and their results are displayed in PC terminal by Mobile phone.

This calibration software includes GSM, DCS, WCDMA Band RF partscalibration and Battery calibration. This calibration software was called “XCALMON(eXtended CALibration and MONitor program)”. From now on, the calibration software will be called XCALMON in this document.

8.2 XCALMON Environment

8.2.1 H/W Environment

- PC with RS-232 Interface & GPIB card installed

- GSM/GPRS/WCDMA Multimedia Mobile Set (U8120)

- Agilent 8960 Series 10 E5515C Instrument (E1985B ver04.08)

- Tektronix PS2521G Power Supply

- ETC (GPIB cable, Serial cable, RF cable, Power cable, Dummy battery)

8.2.2 S/W Environment

- National Instrument GPIB &VISA (ver 2.60 full)driver install

- Agilent 8960 VXI driver(E1960)install

- XCALMON EXE files

- OS :Window98,Window2000,WindowXP

- Serial port configuration :

Baud rate:115200 /Char length:8bit /No Parity/No Flow control

Stop bits:1 bit

8.2.3 Configuration Diagram of Calibration Environment

Figure 8-1. Calibration Configuration Figure

- 207 -

8. CALIBRATION

8.3 Calibration Explanation

8.3.1 Overview

In this section,it is explained each calibration item in the XCALMON.Also the explanation includes technical information such as basic formula of calibration and settings for key parameters in each calibration procedure.

At first,when any of calibration is done,the results are displayed in the XCALMON result window and the result of calibration will be stored in GDFS(Global Data Flash Storage).

8.3.2 Calibration Items

A. EGSM 900 Band

- MODA-D(MD bit)Delay Calibration

- RXVCO Varactor Operating Point Calibration

- TXVCO Varactor Operating Point Calibration

- TX Loop Bandwidth Calibration

- VCXO Calibration

- TX Power Calibration

- RSSI and AGC Calibration

B. DCS 1800 Band

- RXVCO Varactor Operating Point Calibration

- TXVCO Varactor Operating Point Calibration

- TX Loop Bandwidth Calibration

- TX Power Calibration

- RSSI Cal i br at i on

C. WCDMA Band

- RF VCO Center Frequency Calibration

- TX Carrier Suppression Calibration

- TX LPF Bandwidth Calibration

- TX Maximum Output Power Calibration

- TX Power Table Calibration

- TX Open Loop Power Control Calibration

- RX LPF Bandwidth Calibration

- RX LNA Gain Switch and AGC Hysteresis Calibration

- RX AGC Gain Max and Rx RSSI Calibration

- 208 -

8. CALIBRATION

8.3.3 EGSM 900 Calibration Items

A. MOD-A(MD bit) Delay Calibration

- Pur pose

The procedure is designed to calibrate the timing alignment between the MODA-D signals and the reference signal (13 MHz).It also ensures that the MOD signals have stable values when they are clocked into the divider of the Phase-Locked Loop (PLL).

- Procedure Proposal

1. Set the ME to mid channel in the GSM TX band.

2. Set the delay setting in default mode,that is,no delay.

3. Wait approximately 300 us to 400 us to allow the PLL to lock.

4. Measure the RMS phase error.A threshold value of >20 deg indicates that the PLL is running in the forbidden time region.

5. Save the RMS phase error result locally.

6. Step up the delay setting according to Table 8.1 below.

7. Repeat from step 4.

8. Choose delay setting that gives maximum distance to the consecutive field of corrupted RMS phase error values in the vector.

9. Store delay setting both to the GD_RF_Mod_Delay and to the GD_DirMod_Mod_Delay.

10. Reset the radio.

[3]

[4]

[5]

[6]

[7]

Index

[0]

[1]

[2]

DIMC

00(0)

011(3)

1 00(0)

01(1)

10(2)

11(3)

Table 8-1. Delay Settings for the MOD-A

- 209 -

8. CALIBRATION

B. RXVCO Varactor Operating Point Calibration

- Pur pose

To adjust the varactor diode to a pre-determined operating point,so that the loop voltage of the

RXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all RX channels can be reached.

- Procedure Proposal

1. Put the ME in static RX mode.

2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~7.

Find a CVCO value that fulfills the requirements on loop voltage for low and high channel.

3. If there are several CVCO values that fulfill the loop voltage requirements,then the optimum CVCO value is the one that centers the loop voltage within the specified limits.

4. Store the selected CVCO in the memory.

(GD_RX_VCO_Centre_Frequency_Adjustment_Band)

5. Reset the radio.

C. TXVCO Varactor Operating Point Calibration

- Pur pose

To adjust the varactor diode to a pre-determined operating point,so that the loop voltage of the TXVCO

(measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all TX channels can be reached.

- Procedure Proposal

1. Put the phone in static TX mode.

2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~7.

Find a CVCO value that fulfills the requirements on loop voltage for low and high channel.

3. If there are several CVCO values that fulfill the loop voltage requirements,then the optimum CVCO value is the one that centers the loop voltage within the specified limits.

4. Store the selected CVCO in the memory.

(GD_TX_VCO_Centre_Frequency_Adjustment_Band)

5. Reset the radio.

D. TX Loop Bandwidth Calibration

- Pur pose

The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current.

Note:This also indirectly adjusts the VCO gain that can otherwise not be calibrated.

This will ensure a correct transfer function for the modulation and keep phase error to a minimum.

- 210 -

8. CALIBRATION

- Procedure Proposal

1. Put the ME in switched TX mode on mid channel in frequency interval 11 for EGSM

(with random modulation).

2. Measure the RMS phase error at the RF connector.

3. Tune the phase detector current (IPHD)until the phase error is minimized.If two IPHD settings gave the same RMS,choose the lowest value.Measure 10 bursts for each value.

4. Calculate and store the IPHD values in GDFS

(GD_IPHD_8Temperature_and_24Channel_Compensation_Band)

5. The offsets in the table are steps in the IPHD Table 8.2 and all offsets refer to the calibrated value

(Trim) at mid channel in room temperature.

Frequency Interval

01 2 3 4 5 6 7 8 9 10 21 22 23

0-2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

1 -2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

2 -2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

3 -2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

4 -2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

5 -2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

6 -2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

7 -2 -2 -2 -2 -1 -1 -1 -1 -1 000001 1 1 1 1 1 2 2 2 2

Table 8-2. IPHD Compensation for EGSM Band

E. VCXO Calibration

- Pur pose

This procedure aims to calibrate the value of DAC3 to establish a VCXO-frequency that is sufficiently close to 13 MHz at room temperature.It also ensures that the VCXO tuning range is sufficient,and that the temperature compensation table for VCXO is completed accordingly.

Note:The frequencies in this section are related to the 13 MHz VCXO-frequency.

Depending on the calibration procedure,the 13 MHz VCXO frequency can be acquired by first measuring an EGSM,DCS,or W-CDMA RF frequency at the antenna and then translating the measured frequency to the 13 MHz VCXO frequency.

- Procedure Proposal

1. Put the ME in switched low power TX mode with a modulated carrier on a mid channel.

Use the calibrated value of the cap array and phase detector current.

2. Tune DAC3 in AB 2000 (VCXOCONT)to end and mid values,and check tuning range.

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8. CALIBRATION

Acquire the following VCXO (13 MHz)frequencies: fmin =13 MHz VCXO-frequency @DAC3=1 fmid =13 MHz VCXO-frequency @DAC3=1024 fmax =13 MHz VCXO-frequency @DAC3=2047

Note that it is necessary to translate the measured RF-frequency (EGSM,DCS,or W- CDMA)to the 13

MHz VCXO-frequency.

3. Acquire the ME temperature,TCal,from the temperature sensor in ME.

4. Store fmin,fmid,fmax and TCal for calculation.

5. Calculate the DAC-value,VCXOCONTCal,that gives zero frequency error at the mid channel, using piecewise linear interpolation,and store the value in the memory

(GD_RF_SYNT_CONFIG_ID and GD_VCXO)

6. Calculate

K_LO =(fmid –fmin)/1023

K_HI =(fmax –fmid)/1023

Each value is then multiplied by 100 and rounded to nearest integer, with the results stored in the memory (GD_RF_SYNT_CONFIG_ID).

AFC_DAC_STEP_LO =ROUND(100*K_LO)

AFC_DAC_STEP_HI =ROUND(100*K_HI) where ROUND(x)=x rounded to the nearest integer.

F. TX Power Calibration

- Pur pose

These procedures describe how to tune the different power levels of the power amplifier to output powers corresponding to values in GSM 05.05,and explain how to calculate intermediate power levels that will ensure a good power versus time performance.

- Procedure Proposal

1. Reset the DIRMOD-block, and select a‚ mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burst modulation.

2. Use the Multi-burst method to characterize the relation between output power and the DACvalue.Then store the DAC values that give the closest approximations to the power targets defined in Table 8-3.

3. To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed.However,the output power must be kept within the tolerances specified in Table 8-3.

4. Store DAC values in memory (GD_FullPower_Band).

5. Initiate the intermediate value calculation,which calculatesand st or e t he val ues in memory

(GD_IntermediatePower_Up/Down_1.7_Band).

6. The difference between the transmitter power at two adjacent power control levels, measured at the same frequency,shall not be less than 0.5 dB and not more than 3.5 dB.

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8. CALIBRATION

PL 12

PL 13

PL 14

PL 15

PL 16

PL 17

PL 18

PL 19

Parameter

PL 5

PL 6

PL 7

Target Full Power (dBm)

PL 8

PL 9

PL 1023.0

PL 11

Tolerances (dB)

±0 Vol

Table 8-3. Target Power Levels for EGSM

G. RSSI and AGC Calibration

- Purpose

This procedure satisfies the two following requirements:

Calibrate an absolute power level on the antenna to a corresponding RSSI value. This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power. The formula y=kx+m is used. (Where k is the slope value, x the RSSI value, y the actual level, and m is an offset value.)

Calculate the attenuation when the Low Noise Amplifier is switched off in the receiver branch. The attenuation value is stored in the flash memory and used when very high input signals are fed into the

ME.

- Procedure Proposal

1. Select switched receiver on a mid EGSM Channel.

2. Feed a modulated -68.5dBmsignal, on the same mid EGSM-Channel to the antenna input. Measure the RSSI value, calculate the RSSI table and store the value in GDFS as parameter:

GD_RXLEVS_DBM_BURST_M_BAND.

3. On the same channel, now feed a modulated -50dBmsignal and measure the RSSI value.

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8. CALIBRATION

4. Switch off the LNA, using the command FREC=3,0,1, and measure the RSSI value.

5. Calculate the difference between on and off (converting the result to‚ real dB attenuation) and store the result in GD_MPH_RX_AGC_Parameters_Band.

8.3.4 DCS 1800 Calibration Items

A. RXVCO Varactor Operating Point Calibration

- Purpose

To adjust thevaractordiode to a pre-determined operating point, so that the loop voltage of the RXVCO

(measured with an ADC in AB 2000) is withinthe valid range. This is necessary to secure that all RX channels can be reached.

- Procedure Proposal

1. Put the ME in static RX mode.

2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltagefor low and high channel.

3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits.

4. Store the selected CVCO in the memory. (GD_BAND_RX_VCO_Centre_Frequency_Adjustment)

5. Reset the radio.

B. TXVCO Varactor Operating Point Calibration

- Purpose

To adjust thevaractordiode to a pre-determined operating point, so that the loop voltage of the TXVCO

(measured with an ADC in AB 2000) is withinthe valid range. This is necessary to secure that all TX channels can be reached.

- Procedure Proposal

1. Put the phone in static TX mode.

2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltagefor low and high channel.

3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits.

4. Store the selected CVCO in the memory. (GD_BAND_TX_VCO_Centre_Frequency_Adjustment)

5. Reset the radio.

C. TX Loop Bandwidth Calibration

- Purpose

The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current.

Note: This also indirectly adjusts the VCO gain that can otherwise notbe calibrated.

This will ensure a correct transfer function for the modulation and keep phase error to a minimum.

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8. CALIBRATION

- Procedure Proposal

1. Put the ME in switched TX mode on mid channel in frequency interval 11 for DCS (with random modulation).

2. Measure the RMS phase error at the RF connector.

3. Tune the phase detector current (IPHD) until the phase error is minimized. If two IPHD settings gave the same RMS, choose the lowest value. Measure 10 bursts for each value.

4. Calculate and store the IPHD values in GDFS

(GD_IPHD_8Temperature_and_24Channel_Compensation_Band)

5. The offsets in the table are steps in the IPHD Table 8.4 andall offsets refer to the calibrated value

(Trim) at mid channel in room temperature.

Frequency Interval

01 2 3 4 5 6 7 8 9 10 21 22 23

0-6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5

1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 001 1 2 2 3 3 4 4 5 5 5

2 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 001 1 2 2 3 3 4 4 5 5 5

3 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 001 1 2 2 3 3 4 4 5 5 5

4 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 001 1 2 2 3 3 4 4 5 5 5

5 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 001 1 2 2 3 3 4 4 5 5 5

6 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 001 1 2 2 3 3 4 4 5 5 5

7 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 001 1 2 2 3 3 4 4 5 5 5

Table 8-4. IPHD Compensation for DCS Band

D. TX Power Calibration

- Purpose

To tune the different DCS power levels of the power amplifier tooutput powers corresponding to values in GSM 05.05 and calculate the intermediate levels that ensure a good power versus time performance.

- Procedure Proposal

1. Reset the DIRMOD-block, and select a ‚mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burst modulation.

2. Use the Multi-burst method to characterize the relation between output power and the DAC-value.

Then store the DAC values that give the closest approximations to the power targets defined in

Table 8-5.

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8. CALIBRATION

3. To avoid yield problems with the power template and switchingtransients spectrum a margin to the compression point of the PA should be observed. However, the output power must be kept within the tolerances specified in Table 8-5.

4. Store DAC values in memory (GD_FullPower_Band).

5. Initiate the intermediate value calculation, which calculatesand store the values in memory

(GD_IntermediatePower_Up/Down_1.7_Band).

6. The difference between the transmitter power at two adjacent power control levels, measured at the same frequency, shall not be less than 0.5 dB and not more than 3.5 dB.

Target Full Power (dBm)

30.0

Tolerances (dB)

+0.5 – 1.0

Vol

PL 7

PL 8

PL 9

PL 10

PL 11

PL 12

PL 13

PL 14

PL 15

Parameter

PL 0

PL 1

PL 2

PL 3

PL 4

PL 5

PL 6

20.0

10.0

±0.5

Vol

Vol 0.0

±1

Table 8-5.Target Power Levels for DCS

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8. CALIBRATION

E. RSSI Calibration

- Purpose

This procedure calibrates an absolute power level on the antennaagainst a corresponding RSSI value.

This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power. The formula y=kx+m is used. (Where k is the slope value, x the

RSSI value, y the actual level, and m is an offset value).

- Procedure Proposal

1. Select switched receiver on a mid DCS-Channel.

2. Feed a modulated -68.5dBmsignal, on the same mid DCS Channel to the antenna input. Measure the RSSI value, calculate the RSSI table, and store it to the memory

(GD_BAND_RXLEVS_DBM_BURST_M[2]) –1 byte.

8.3.5 WCDMA Calibration Items

A. RF VCO Center Frequency Calibration

- Purpose

This procedure is designed to calibrate the RFVCO (Radio Frequency Voltage Controlled Oscillator) center frequency of the Ericsson RF 2110 (hereafter referred to as the RF 2100) and ensure that all channels can be reached with sufficient margin.

The objective of the calibration is to determine a CVCO (Center VCO) value that guarantees the functionality of the RFLO (Radio Frequency Local Oscillator).

- Procedure Proposal

1. Start the VCXO and RFVCO. VCXOCONT is set to its calibrated value, Ericsson AB 2000 DAC3.

2. Measure the loop voltage (WRFLOOP), with the AB 2000 ADC (GPA4), for all CVCO settings, that is, 0-7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is that that centers the loop voltage within the specified limits.

3. Store the calibrated CVCO value in GD_RF_SYNT_CONFIG_ID.

B. TX Carrier Suppression Calibration

- Purpose

DC offset compensation the carrier, to the wanted signal at the IQ-modulator output.

The leakage is caused by imperfections in the basebandIQ-path and inside the IQ-modulator. It impairs the modulation accuracy and results in a high vector magnitude (EVM). The outcome of the calibration is values for RECDCI and RECDCQ that minimize the carrier.

- Procedure Proposal

1. Set the ME in TX mode on mid-channel. Use typical TX settings. Generate 960 kHz square-wave on both I and Q with amplitude = 8 (sine-wave could be used instead).

Start with the best value from earlier calibrated units on RECDCI on RECDCQ.

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8. CALIBRATION

2. Measure the relative power between the 1950 MHz carrier and 1949.04 MHz at the antenna output.

Jump to step 6 if the requirement is met.

3. Step RECDCI from 0 to 3. Set TXON = 0 and wait 1 ms before changing RECDCI from 3 to 5. Set

TXON = 1, wait 1 ms and continue with stepping from 5 to 7.

4. Set RECDCI to the value that minimizes the 1950 MHz carrier. If this involves a change of sign the

TXON switching and delay sequence in point 3 must beexecuted. Jump to 6 if the requirement is met.

5. Find and set RECDCQ to the value that minimizes the 1950 MHz carrier. This can be made by stepping RECDCQ from 0 to 7 with the TXON switching and delay sequence in step 3.

6. If the requirements are not met, repeat steps 3, 4 and, if necessary, 5 once with the new RECDCI and RECDCQ (found in 4 and 5) as initial values. Otherwise proceed with step 6.

7. Save the finaldBcvalue (for statistics), RECDCI and RECDCQ. Store the calibrated parameters in

GD_RF_TX_CONFIG_ID.

C. TX LPF Bandwidth Calibration

- Purpose

The low pass filters within the Ericsson DB 2100 (hereafter referred to as DB 2100) are designed to prevent spurious emissions output from the TX IQ-D/A (Digital-Analog) converters Œ without adversely affecting the signal or causing a deterioration of the modulation accuracy.

The objective of this calibration is to determine the values forLPQ and LPBW that offer the best trade off against the system-related requirements. These settings determine the cut-off frequency and should always have the same value.

- Procedure Proposal

1. Use typical TX settings. Generate a 960 kHz square-wave at baseband without phase shift between

I and Q. The amplitude should be about 50% of fullscale.

2. Measure the relative power between 1952.88 MHz (fc+ 3*960 kHz) and 1949.04 MHz (fc Œ 960 kHz) in dB at the antenna output. Find the setting of LPQ =LPBW between 3 and 15 that obtains the dBcvalue closest to the typical value. Start with the best value from earlier calibrated units.

Spectrum analyzer settings (example):

RBW = 300 kHz, Span = 8 MHz.

3. Set LPQ=LPBW to the found value in 2. Also save thedBcand the decided LPQ = LPBW value for statistics. Store the calibrated parameters in GD_RF_TX_CONFIG_ID.

D. TX Maximum Output Power Calibration

- Purpose

These procedures verify that the ME can meet the requirements onmaximum output power. The calibration aims to establishWPABias, VGA and QVGA settings that fulfill ACLR requirements for maximum output power, both in high, medium, and low gain mode.

These calibrations are designed to conform to the ME maximum output power and ACLR requirements specified in 3GPP Spec TS34.121.

- Procedure Proposal

1. Use typical TX settings, mid channel.

2. Set gain to the best value based upon previous calibrated units.

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8. CALIBRATION

3. Measure output power as broadband power.

4. If the ACLR requirements, described in Table 11 are not met, calculate the test step necessary to achieve the correct power. Use correlation from earlier calibrated units to calculate the new gain setting (default correlation between VGA and output power is 1 dB and for QVGA 0.25dB).

5. Measure ACLR at this power level.

6. If the ACLR requirement is not met, reduce VGA and QVGA.

7. Measure and store the temperature at this point. This provides the value forTPmax.

8. This power and gain setting is to be used in calibration of TX power table.

9. Set gain to maximum power in medium gain mode and measure ACLR at this power level.RFBiasshould be set to 1 andWPABiasshould be set to the same value as for maximum output power.

10. If the requirements are not met, step the gain down and measure ACLR until the requirements are met. The correlation between ACLR and output power is that 1 dB in power equals typical 3 dB in

ACLR. Use correlation from earlier calibrated units to calculate the new gain setting.

11. This power,Pmax measMG, is input to the calibration of TX power table.

12. Set gain to maximum power in low gain mode and measure ACLR at this power level.

RFBiasshould be set to 1 andWPABiasshould be set to the same value as for maximum output power.

13. If the requirements are not met, step the gain down and measure ACLR until the requirements are met. Use known correlation from earlier calibrated units to calculate the new gain setting.

14. This power,Pmax measLG, and gain setting provides input to the calibration of TX power table.

E. TX Power Table Calibration

- Purpose

The calibration data contained within the TX Power Table controls the gain for all types of power change; including, the inner-loop power control and maximum output power of the platform.

The purpose of this calibration is to complete the TX Power gain table with values for VGA, QVGA,

RFBIAS, WPABias, and WDCDCREF that meet the specified requirements for inner-loop powercontrol and Maximum output power. The size of hysteresis area must also be found.

These calibrations are designed to conform to the ME maximum output power, inner loop power control, change of TFC and (PRACH preamble tolerances)requirements specified in 3GPP Spec

TS34.121.

- Procedure Proposal

This calibration consists of two parts: first measurements and then an off-line calculation. The measurement results are used for characterizing the hardware so that proper settings can be calculated for all tables. Settings and limitations are also used from maximum output calibration.

1. Perform measurements

(1) VGA behavior in LG (Low Gain) mode. PABias should not be offset and RFBIAS should be 1.

(2) VGA behavior in MG (Medium Gain mode). PABias should not be offset and RFBIAS should be 1.

(3) QVGA behavior in LG mode

(4) IQ-Gain behavior in LG mode.

(5) WPABias gain step size. Every eighth setting is measured twice. For better accuracy take the average of each step pair. Interpolate the gain steps in between the averaged measured values.

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8. CALIBRATION

(6) WDCDCREF gain step size. Every fifth setting is measured twice. For better accuracy take the average of each step pair. Interpolate the gain steps in between the averaged measured values.

(7) Size of step between LG/MG and MG/HG and between each setting of RFBIAS (1-7). The main purpose is to find the relative difference at different frequencies. Distribute with equal frequency offset except if there are known ‚worst-case frequencies. Measured at 5 channels, maximum and minimum steps reported. Average value of minimum and maximum should be used in following calculations.

(8) Measure properties: Measure the following properties using a modulated signal:

WPA-gain expansion versus output power on mid channel.

Compensation needed for maximum output power over the band (13 channels).

2. Perform offline calculations

(1) Calculate the compensation values for Table 8-6. Store these values in

GD_RF_TXGAIN_TB_SEL_ID.

(2) Extract the range of needed compensation tables (minimum and maximum).

(3) Calculate the expected compensation for each table in dB (use ‚table 0 for the table that is ‚0 dB or closest to ‚0 dB) and spread out the rest to achieve equidistant compensations.

(4) Calculate and store the 24 sets of tables, GD_RF_TX_GAIN_TB0_ID to

GD_RF_TX_GAIN_TB23_ID. Each set of tables shall include:

One High-gain table: 44 bytes.

One Low-gain table: 44 bytes.

One RFBias table: 22 bytes.

One WDCDCRef table: 44 bytes.

One WPABias table: 44 bytes.

One value for IQ-Gain: 1 bit (will occupy 1 byte).

One value for TABLE_OVERLAP: 1 byte.

One value for UPPER_LIMIT: 1 byte.

(5) Calculate the actual compensation (for maximum output power) that each of these 24 tables will give. Store this in GD_RF_TX_FREC_INT_ID.

3. Store data in GDFS

Temp.

UARFCN

9612 9637 9662 9687 9712 9737 9763 9788 9813 9838 9863 9888

-15

Table 8-6.The Complete Gain Compensation Table

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8. CALIBRATION

E. TX Open Loop Power Control Calibration

- Purpose

The purpose of the calibration of open loop power control is to store parameters for the Open Loop

Power Control algorithm. This is a pure off-line calculation. Use data (positions and output power, in dBm) from table 0. Curve fitting should be done preferably with minimum square method.

System related requirements:

Open loop power control

Maximum allowed UL TX Power

UE Transmitted power

- Procedure proposal

1. Create a curve fitting for the low-gain region, use positions with a power greater than -50 dBm:

Position = B3 * Pout + A3

2. Extract A3 and B3.

3. The power level (output power) at the highest position in the low-gain region sets the parameter P2.

4. Divide the high-gain region into two regions at the split between mid-gain and high-gain. The output power at this position sets the parameter P1.

5. Do a curve fitting for the mid-gain region (where RFBias > 0) of the high-gain region, use powerlevels from P2: Position = B2 * Pout + A2

6. Extract A2 and B2

7. Do a curve fitting for the high-gain region (where RFBias = 0) of the high-gain region:

Position = B1 * Pout + A1

8. Extract A1 and B1

9. Save A1, A2, A3, B1, B2, B3, P1 and P2 in GD_RF_TX_GAIN_PARAM_ID.

Figure 8-2. Example of Position versus Power and Calculated Equations

- 221 -

8. CALIBRATION

F. RX LPF Bandwidth Calibration

- Purpose

This procedure calibrates the LPF bandwidth. The bandwidth of the channel filters will affect system parameters as reception sensitivity and adjacent channel selectivity. The procedure also verifies that the IF-filter is properly matched.

Figure 8-3. AGC Block Diagram (Parameter Ak, Output1, and Pref)

- Procedure Proposal

1. Feed a CW carrier at 2140 MHz with a power of -60dBm into the antenna connector.

2. Set UE in RX-mode on 10695ch.

3. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode.

4. Set RF 2110 LPQ and LPBW to 8, that is, LPQ=LPBW=8.

5. Get Ak (output2) from N slots. Calculate Average_Ak (Ak_IB) according to the equation below.

N should be as large as possible, with respect to time consumption.

6. Set UE on 10705ch and get Ak (output2). Calculate Average_Ak (Ak_LB) according to the Equation 1.

7. Calculate IF-filter symmetry using the following equation.

IF_SYM = Ak_IB - Ak_LB

8. Set UE on 10685ch and get Ak (output2). Calculate Ak (Ak_OB) according to the Equation 1.

9. Calculate selectivity level using following equation.

Ak_SE = Ak_OB – Ak_IB

10. If the requirement is not met, decrease LPBW and LPQ one step and repeat from 8.

11. Store the resulting LPBW and LPQ in GD_RF_RX_CONFIG_ID.

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8. CALIBRATION

F. RX LNA Gain Switch and AGC Hysteresis Calibration

- Purpose

This procedure calibrates the gain correction parameter of Ak in the AGC algorithm between GLNA=0 and GLNA=1; that is, it establishes the gain difference in the LNA between high gain mode and low gain mode. It also calibrates AGC_UL and AGC_LL, the upper and lower Ak values where the AGC should switch between high and low LNA gain (AGC hysteresis).

Figure 8-4. LNA Gain Switch and AGC Hysteresis Parameters

- Procedure Proposal

1. Set the UE in RX-mode on 10695ch.

2. Feed a CW carrier at 2140 MHz with a power level of -65dBm.

3. Set the AGC_UL and AGC_LL to maximum. GLNA is forced to low gain mode.

4. Get average Ak from Equation 1 and save it. (Ak_LG)

5. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode.

6. Get average Ak. (Ak_HG)

7. (Ak_LG) - (Ak_HG) = (Correction).

8. Round off (Correction) to integer (AGC_CR) and store it in GDFS (GD_RF_RX_CONFIG_ID).

AGC_CR is an AGC algorithm parameter and is set to DB 2100 RFIF.

9. Calculate AGC_LL=8+AGC_CR and AGC_UL=18+AGC_CR and store them in GDFS

(GD_RF_RX_CONFIG_ID). AGC_LL and AGC_UL are AGC algorithm parameters and are set to

DB 2100 RFIF.

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8. CALIBRATION

G. RX AGC Gain Max and RX RSSI Calibration

- Purpose

To prevent wind up in AGC algorithm, this procedure calibrates the absolute power levels at the antenna connector against RSSI values and the maximum gain setting for AGC. Reference [6] specifies that the reporting range of the RSSI should be between -100 dBm to -25 dBm. The specified accuracy requirement is applied to the received power from -94 through -50 dBm. This is the last RX calibration.

LPBW, LPQ, AGC_CR, AGC_LL and AGC_UL must be calibrated according to above calibrations respectively and applied to this calibration. Initially, the AGC anti-wind up is turned on using

AGC_GMAX=127. Use the calibrated value after step 2, otherwise the AGC wind up may occur at the beginning of the RSSI calibration.

- Procedure Proposal

1. Set the ME in RX-mode on channel 10695.

2. Feed a CW carrier at 2140 MHz with a power level of -105 dBm. Get average_Ak (output2), add 6 to the value and store it in GDFS as AGC_GMAX (GD_RF_RX_CONFIG_ID), rounded off to an integer. Set the AGC parameter AGC_GMAX to the calibrated value.

3. Clear Ak ‚table 0.

4. Change the CW carrier power level to -95 dBm.

5. Read Ak value (output2) and calculate Average_Ak (Equation 1). Store Pin_Corrected (Equation 2) at Ak=round(Average_Ak). N in Equation 1 should be as large as possible.

Pin_Corrected = Pin-round(Average_Ak)+Average_Ak Equation 2

6. Then increase the output level of the signal generator to -80, -60, -40 and -25 dBm and store the corrected RF input level and Ak to the memory respectively.

7. Use the average Ak values and Pin_Corrected from the two lowest power levels (-95 and -80 dBm) to extrapolate Ak and Pin_Corrected for -110 dBm according to:

Average_Ak_110 = 2*Average_Ak_95 – Average_Ak_80

Pin_Corrected_110 = Pin_Corrected_95 – Pin_Corrected_80

8. Store Average_Ak_110 and Pin_Corrected_110 according to step 4.

9. Perform the interpolation. AK_BANK_SEL in DB 2100 shall be set to 0.

10. Measure the ME temperature (T) and save for offline calculations.

11. Store the result to GDFS. (GD_RF_RX_AK_TB0_ID). When stored in GDFS, the first position in the table (Ak=0) should be replaced with the table number (0-23) in bcd format and the second position (Ak=1) set to 0xffff to flag that the table is calibrated. Position 2 to 5 should be set to zero.

12. Perform the offline calculations and check the requirements.

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8. CALIBRATION

8.3.6 Baseband Calibration Item

A. Battery Voltage Calibration

- Purpose

Calibrates the voltage table for the power management functionality. Some voltage measurements in the remaining test will be done with calculated voltage levels from this test.

- Procedure Proposal

1. Send the command LVBA=0 to reset local values in Test Program.

2. Set voltage on VBATT to 3.20 V.

3. Send the command LVBA=5,0x140 to read the low voltage level from ADC.

4. Set voltage on VBATT to 4.10 V.

5. Send the command LVBA=5,0x19A to read the high voltage level from ADC.

6. Send the command LVBA=1 to store local values into global data.

7. Send the command LVBA=3 to view and record values stored in global data.

Voltage Level on VBATT (V)

3.2

4.1

Min.

100

Typ.

125

Max.

Unit

HEX

60DEC

96 HEX

150 DEC

Table 8-7. Battery Voltage Calibration Limits

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8. CALIBRATION

8.4 Program Operation

8.4.1 XCALMON Program Overview

When you try to calibrate the U8120 mobile phone, you should make a configuration of calibration environment like Figure7-1. And if you finish making configuration, please execute the XCALMON program. Running the XCALMON program, you should show XCALMON program window like

Figure7-5.

If XCALMON program would be executed, it checks the connection of instruments and initializes them automatically. The result of checking and initializing instruments was shown like Figure7-6.

XCALMON supports three functions.

- Calibration of EGSM 900, DCS 1800, and WCDMA band

- Instrument (Agilent8960, Tektronix PS2521G) control

- UART communication with U8120 mobile phone

XCALMON has three windows and each window support different function.

- ITP(Integrated Test Program) starting window using production loader

- Calibration tree window

- Command window which supports interactive ITP commands like Hyper terminal

Figure 8-5. XCALMON Window

- 226 -

8. CALIBRATION

8.4.2 XCALMON Icon Description

A. DOS Window Icon

When you click the DOS window icon, then you should see the ITP command window like DOS window of DOS-operating system. In ITP command window, you should communicate with U8120 mobile phone which is running in ITP mode.

For example, if you will enter command “VERS” and enter the return key, you should get the response of the present running ITP version information from U8120 mobile phone.

Figure 8-6. XCALMON ITP Command Window

B. Calibration Tree Window Icon

When you click the calibration window icon ”C”, then you should see the calibration tree window. That will be shown all calibration items. If you want to calibrate U8120 mobile phone for all calibration items, you should select “Calibration” and push “F4” button in your keyboard.

Also there are four tap view in calibration window.

- OUTPUT : All results of calibration

- STATUS : Summary of calibration result

- INSTRUMENT : Control and view instrument connection status

- UART : Control and view UART connection status

- 227 -

8. CALIBRATION

Figure 8-7. XCALMON Calibration Tree Window (OUTPUT Tab)

Figure 8-8. XCALMON Calibration Tree Window (INSTRUMENT Tab)

- 228 -

8. CALIBRATION

Figure 8-9. XCALMON Calibration Tree Window (UART Tab)

C. ITP Starting Window Using Production Loader

When you click the ITP starting window icon”L”, then you should see the ITP starting window. That dialog window just wait for power-on of U8120 mobile phone. When it will occur power-on, it automatically start ITP running.

If you want to change the start address of ITP, you could change that address directly.

To change ITP start address is possible when we download “Production loader” previously.

- 229 -

8. CALIBRATION

Figure 8-10. XCALMON ITP Starting Window (Using Production Loader)

8.4.3 Calibration Procedure

Calibration procedure of XCALMON was the same as below procedure.

- Configuration of calibration

- Running ITP using production loader

- Calibration start using XCALMON

- Verification of calibration result

A. Configuration of Calibration

Configure to calibrated U8120 mobile phone like Figure7-1. If configuration will be accomplished, start

XCALMON program.

B. Running ITP Using Production Loader

If XCALMON will be executed, you should run ITP using “L” ITP starting icon at first.

Click the “L” icon, then you will see the ITP start window like Figure7-10.

When you will turn on the U8120 mobile phone, the production loader will be downloaded automatically like Figure7-11 and then it will execute the ITP at once.

If the ITP will operate normally, you should see the characters “TP, OK” in ITP command window like

Figure7-12.

- 230 -

Figure 8-11. Production Loader Downloading

Figure 8-12. ITP Start Complete Window

- 231 -

8. CALIBRATION

C. Calibration Start Using XCALMON

If you want to calibrate U8120 mobile phone, click the calibration icon “C”.

And then you will see the calibration tree window like Figure7-6.

To start calibration, you should select “Calibration” item and push “F4” button in your keyboard.

D. Verification of calibration result

If the calibration will be ended, you will see several message window and the result of calibration through OUTPUT & STATUS tab view.

The detail explanation of those will be described in chapter 7.4.4

8.4.4 Calibration Result Message

If the calibration is over without error, “PASS” message window will show up like Figure7-13. On the contrary, if the calibration is over with some error, “FAIL” message window will show up like Figure7-14.

Additionally, in all of the cases, it is possible to check the calibration result with OUTPUT & STATUS tab view.

Figure 8-13. Calibration PASS Message Window

- 232 -

8. CALIBRATION

Figure 8-14. Calibration FAIL Message Window

Figure 8-15. Calibration Result from OUTPUT Tab View

- 233 -

8. CALIBRATION

Figure 8-16. Calibration Result from STATUS Tab View

- 234 -

9. CIRCUIT DIAGRAM

VDD_A

VDD_B

EXTLDO

VBATI

WCDMA_TX

GSM_TX

DCS_TX

VCCB

ANTSW3

ANTSW2

ANTSW1

ANTSW0

C1012

22p

N1002

DFYK61G95LBNCB

C1010

1000p

V1001

RN47A4

R1001

R1002

R1007

GND2

GND1

GND5

GND4

GND3

12 14 6

ANT

N1000

LMSP54MA-213

VC2

VC1

VDD

16 4 2

C1011

22p

R1006

C1007

0.01u

C1001

10p

R1005

C1009

10p

C1002

0.01u

R1004

C1008

10p

C1003

0.01u

R1003

C1004

0.01u

C1005

10p

C1013

22p

R1804

R1800

C1800

0.1u

N1800

LP2985AIBP-2.8

ON_OFF GND

VIN

BYPASS

VOUT

C1801

1000p

R1850

R1851

C1850

0.1u

C1852

10u

2012

N1850

VOUT

VIN

VOUT_SE

LP3981ILD-2.8

VEN

BYPASS

GND1

C1851

0.033u

C1810

10u

2012

C1811

10u

2012

R1810

R1811

R1801

R1825

R1826

ANT

W1001

KMS-507

L1001

6.8nH

C1000

3.9p

L1002

6.8nH

WCDMA_RX

ANTPAD

DCS_RX

GSM_RX

C1802

10u

2012

VCCA

VCCB

V_wivi_A

V_wivi_B

SG Kang Tuesday, September 04, 2003 5:01:55 pm

SG Kang

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP 1

ANT SW to ANT

U8120 PT V1.3 STG INTEL PAM

Drawing Number:

- 235 -

9. CIRCUIT DIAGRAM

1 2 3

4 5 6 7 8 9 10

VCCB

WCDMA_RX

WDAT

WCLK

WSTR

GPRFCTRL

CLKREQ

C1400

C1401

22p

L1401

2.2nH

C1402

1000p

TP1401 TP1402 TP1403

R1401

C1403

22p

C1404

0.01u

R1410

C1414

22p

Z1400

B7752

L1411

6.8nH

C1412

1.2p

C1413

1.2p

C1425

2200p

R1440

C1424

22p

C1444

22p

L1422

68nH

1608

L1421

68nH

1608

Z1420

TMX-M453

IN-

SHIELD

OUT+

IN+

GND

OUT-

C1441

2200p C1443

1.2p

L1441

100nH

1608

C1442

2200p

C1422

27p

C1421

R1411

3.3K

C1423

27p

C1448

0.01u

C1447

0.01u

IFOUTB

VCCMIX

MIXINA

MIXINB

GNDBIAS

GNDEME

RFIN

GNDBYP

VCCRF

GNDIF

DATA

CLK

STROBE

GLNA

N1400

LZT-108-5323

VCCREF

XOIA

XOIB

VCCBUS

IFLOA

IFLOB

GNDRFLO

RFLOOA

B10

C10

D10

E10

XOOA

XOOB

GNDREF

GNDBUS

REFON

GNDVCO

F10

G10

H10

J10

C1453

0.01u

C1454

0.01u

C1451

0.01u

C1452

0.01u

R1760

L1760

1uH

C1760

0.01u

C1761

82p

C1431

22p

C1776

4.7p

R1430

C1777

47p

B1770

TSX-8A

HOT2 GND2

2 GND1

HOT1

13MHz

C1773

4.7p

C1772

330p

C1778

56p

R1772

10K

R1771

10K

V1770

BBY58-02W

C1750 22p

R1505

C1751 22p

R1770

C1770

0.01u

C1407

22p

L1402

R1720

5.6K

C1721

390p

R1721

C1722

C1740

0.01u

C1741

22p

R1740

C1730

0.01u

C1731

22p

R1730

RXQA

RXQB

RXIA

RXIB

MCLK

VCCB

VCXOCONT

IFLO

IFLOBAR

RFLO

RFLOBAR

XOOA

XOOB

VCCB

C1720

5600p

R1723

WRFLOOP

R1431

R2108

100

FROM MARITA SIDE FOR POWER SAVING

11 12

1 2 3 4 5 6 7 8

Changed by:

SG Kang

Date Changed:

Tuesday, September 04, 2003

Engineer:

SG Kang

Drawn by:

SG Kang

R&D CHK:

DOC CTRL CHK:

Time Changed:

12:50:11 pm

MFG ENGR CHK:

QA CHK:

TITLE:

REV:

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP 1

UMTS RX (WOPY)

Size:

12 1 8 A

U8120 PT V1.3 STG INTEL PAM

Drawing Number:

Page:

- 236 -

9. CIRCUIT DIAGRAM

1 2 3 4 5 6 7 8 9 10 11

WCDMA_TX

VCCWPA

R1630

C1632

0.01u

C1631

10p

V_wivi_A

B1501

V+ VO

GND1

GND2 NC

LM20BIM7X

V_wivi_A

V_wivi_B

N1650

CE0401G95DCB000-TT1

N1630

RF9266

GND5

GND6

GND7

VCC21

VCC22

GND8

VCC11

VCC12

VDETECT

VCC_DET

GND2

VCC_BIAS2

VCC_BIAS1

GND1

VCTRL2

VCTRL1

R1632

C1635

R1631

R1617

RTEMP

VBATI

C1636

R1997

WDCDCREF

VBATI

R1633

R1623

R1621

R1629

R1626

33K

N1620

MAX1820ZEBC

_SKIP SYNC

COMP

OUT

_SHDN

BATT

C1622

22p

REF

GND

PGND

C1626

330p

C1623

10u

2012

C1624

4.7u

3838

L1621

4.7uH

C1627

4.7u

R1606

R1605

R1604

R1501

R1703

C1501

47p

WPAREF

RFLO

RFLOBAR

V_wivi_A

L1506

Z1500

SX-S205B

S_OUT

B_IN2

B_IN1

C1514

0.01u

C1513

0.01u

L1507

BLM15BB750SN1J

C1511

10p

C1512

10p

R1503

R1510

C1510

0.01u

C1509

10p

L1503

5.6nH

L1504

8.2nH

C1504

10p

C1715

100p

L1720

C1716

4.7p

C1714

100p

R1502

680

L1501

15nH

C1508

2.2p

L1505

10nH

C1507

C1502

L1502

15nH

R1504

680

C1505

22p

OUT

OUTBAR

GNDRF

MIXOUT

MIXOUTBAR

VCCIF

IFBP

J10

IFBPBAR

VTUNERF

GNDRFLO2

GNDRF1

GNDRF2

GNDRF3

GNDIF

N1700

LZT-108-5322

QINBAR

QIN

INBAR

VCCBB

VCCIFPHD

PHDIFOUT

VCCIFPLL

GNDIFVCO1

VCCIFVCO

CLK

GNDIFPHD

GNDIFPLL

WON

A10

C1712

R1711

C1710

150p

R1710

4.7K

C1503

22p

C1702

22p

C1602

22p

C1704

22p

C1711

3300p

C1701

0.01u

C1601

0.01u

C1703

0.01u

R1701

R1603

TP1504

TP1503

TP1502

TP1501

R1702

L1601

L1602

L1603

L1604

L1605

R1627

39K

TP1701 TP1702

R1628

100K

C1628

1000p

VCCWPA

WPOWERSENSE

IFLOBAR

IFLO

V_wivi_B

V_wivi_A

XOOA

XOOB

TXQB

TXQA

TXIB

TXIA

V_wivi_B

WDAT

WCLK

WSTR

1 2 3 4 5 6 7 8

Changed by:

SG Kang

Date Changed:

Tuesday, September 04, 2003

Time Changed:

5:04:02 pm

Engineer:

SG Kang

Drawn by:

SG Kang

R&D CHK:

DOC CTRL CHK:

MFG ENGR CHK:

QA CHK:

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP 1

TITLE:

UMTS TX (WIVI) to ISOLATOR

U8120 PT V1.3 STG INTEL PAM

REV: Drawing Number:

Size:

12 1 8 A

Page:

- 237 -

9. CIRCUIT DIAGRAM

1 2 3 4 5 6 7 8 9 10 11

VDDBUF

PASENSE+

PASENSE-

PAREG

IOUT

VDIG

FF_IN

EXPOUT

VDDPA

VSSPA

GSM_TX

DCS_TX

TXON

RXON

BSEL0

PCTL

MODA

MODB

MODC

MODD

VCCA

XOOB

XOOA

PULSESKIP

VLOOP

VBATI

R1302

C1322

150p

BLM31PG601SN1

R1301

L1300

R1329

R1328

R1321

C1315

10u

2012

C1311

10u

2012

C1312

0.01u

C1313

22p

BLM15AB601SN1J

L1320

C1323

100p

R1322

R1323

R1327

C1326

R1325

V1330

2SD2216J

R1324

R1326

0.05

C1325

100p

C1320

470p

C1321

470p

C1300

0.068u

VDIG

R1151

I2CDAT

I2CCLK

SYSCLK2

RESOUT3n

C1327

33p

C1324

100p

C1343

C1341

33p

C1352

10p

C1342

R1343

R1350

C1351

C1340

C1350

R1361

EGSM_OUT

DCS_PCS_IN

DCS_PCS_OUT

SKY77321

N1300

RSVD

EGSM_IN

TX_ENABLE

R1345

R1338

R1339

R1337

NA C1332

33p

N1330

LDB21897M15C

R1332

L1330

33nH

R1333

0 R1113

C1335 C1113 C1334

22p 22p 22p

C1336

L1333

R1334

R1210

L1200

100

R1211

R1212

100

R1213

100

C1205

22p

C1201

0.01u

R1272

R1273

C1271

1000p

L1201

5.6nH

1608

C1270

1000p

C1331

22p C1337

22p

R1344

R1341

R1342

L1332

BLM15BB750SN1J

R1340

C1333

10p

N1331

LDB211G8020C

L1331

22nH

L1230

C1230

C1231

K10

NC5

MODA

MODB

MODC

MODD

VCCPLL

XOOB

XOOC

NC6

GNDBUF

NC3

GNDPLL

XOOLA

N1100

LZT-108-5325

RFHD

RFHC

GNDRF

RFLB

RFLA

VCCRF

QRB

QRA

IRB

IRA

REON

CLK

DATA

STROBE

A10

C1330

22p

R1335

C1102

10p

L1100

3.9nH

C1101

10p

R1121

R1250

C1250

R1224

C1221

0.01u

R1220

560

L1220

100uH

C1220

C1225

1800p

2012

R1222

120

C1224

1200p

R1223

390

C1222

560p

C1223

330p

TP1201

TP1202

TP1203

B7714

G1 G2 G3

C1203

22p

C1202

0.01u

Z1100

L1202

C1115

RXON

C1114

C1240

R1240

C1100

L1101

3.3nH

10p

VCCA

DCS_RX

C1112

33p

L1110

18nH

C1111

33p

Z1110

B7705 3

4 5

L1120

C1104

0.01u

C1103

22p

C1110

33p

L1111

10nH

R1103

R1104

GSM_RX

VCCA

R1105

R1106

C1156

0.01u

TP1151

TP1152

R1140

100K

AVDD

I2CDAT

I2CCLK

MCLK

RESETB

QDAT

IDAT

DCLK

IRA

IRB

QRA

QRB

RXSTR

AUXI1

CCO

MICIP

MICIN

GPA0

GPA1

GPA2

GPA3

GPA4

GPA5

GPA6

GPA7

PCMDL

PCMCLK

PCMSYN

ADSTR

AUXO2

BEARP

BEARN

PCMUL

GPDAT

GPCLK

DAC01

DAC02

DAC03

N1101

LZT-108-5321

DACCLK

DACDAT

DACSTR

DEC1

DEC2

DEC3

DEC4

DEC5

REXT

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

NC1

NC2

TP1141 TP1142 TP1143

C1150

0.01u

C1143

0.068u

C1151

C1140

0.068u

R1150

C1153

C1155

C1141

0.068u

C1142

0.068u

C1144

0.068u

QDATA

IDATA

DCLK

VDIG

VDIG_HERTA

GPRFCTRL

RADCLK

RADDAT

RADSTR

VCCA

1 2 3 4 5 6 7 8

Changed by:

JS Joo

Date Changed:

Tuesday, September 04, 2003

Engineer:

JS Joo

Drawn by:

JS Joo

R&D CHK:

DOC CTRL CHK:

Time Changed:

7:25:06 pm

MFG ENGR CHK:

QA CHK:

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP 1

TITLE:

REV:

Size:

GSM/DCS (INGELA)

12 1 8 A

U8120 PT V1.3 STG INTEL PAM

Drawing Number:

Page:

- 238 -

9. CIRCUIT DIAGRAM

1 2 3 4 5 6 7 8 9 10 11 12

VDIG

LM20BIM7X

GND2 NC

GND1

V+

U3106

R3328

8.2K

PT1

47K

R3384

R3327

180K

R3379

ONSWAn

ONSWBn

ONSWC

RTCCLK

SIMDAT0

SIMCLK0

SIMRST0

MCLK

I2CDAT

I2CCLK

CLKREQ

PWRREQn

VDIG

VBAT_C

ADCSTR

RTEMP

VLOOP

WPOWERSENSE

WRFLOOP

GPA6

VBACKUP

DCIN_3

DCIN_2

MOTOR_BATT

DACDAT

DACSTR

DACCLK

VSSPA

VDDPA

VDDBUF

PASENSE+

PASENSE-

PAREG

IOUT

PCMSYN

PCMCLK

PCMDATB

PCMDATA

R3045

100K

TP3004

TP3000

C2280

1608

TP2311 TP2310

R3041

100K

R3042

100K

R3043

100K

R3046

100K

R3047

100K

4.7u

C3013

Q2201

SI5441DC

R3382

4.7

R3049

100K

R2205

C2281

4.7u

R2214

0.1

VBATI

VDIG

R3378

3.3K

VDIG

Q3203

DTA114EETL

C2211

0.1u

C2212

0.1u

C2213

C2214

0.1u

VBAT

R2215

0.05

R2218

R2217

VDIG

R3002

R2212

C2607

2012

R3019

C2621

C3246

0.1u

C2209

0.1u

C2207

0.1u

R2312

10K

R2220

100K

C3271

47p

C3272

47p

C2210

0.1u

D2010

EN_LED_R

1SS388

ROP-101-3029_2C

ONSWA

ONSWB

ONSWC

INTLCKB

XTAL1

XTAL2

SDAT

SCLK

SRST

C10

MCLK

SDA

SCL

CLK_REQ

SLEEP

J12

H12

VREF

DEC0

DEC1

DEC2

IREF

A12

VBAT_A

M12

VBAT_B

VBAT_C

VBAT_D

M10

L10

K10

L11

K11

J11

J10

MOD1

ADSTR

GPA0

GPA1

GPA2

GPA3

GPA4

GPA6

GPA7

GPA12

GPA13

DCIO

CHREG

CHSENSE+

CHSENSE-

F11

FGSENSE+

F12

FGSENSE-

H10

D10

VSS_A

VSS_B

VSS_C

VSS_D

SUB

VSSBUCK

TEST

B11

BDATA

VIBR

B10

A10

DACDAT

DACSTR

DACCLK

E10

G12

C12

E12

E11

D11

D12

VSSPA

VDDPA_DAC

VDDBUF

PASENSE+

PASENSE-

PAREG

IOUT

PCMSYN

PCMCLK

PCMO

PCMI

VDDCODEC

VDDBEAR

VDDADC

VSSADC

VSSCODEC

VSSBEAR

N2000

VINCENNE

EN_LED_TC

MIC1P

MIC1N

AUXI1

MIC2P

MIC2N

AUXI2

GPA5

AUXO2

K12

VSSTH1

VSSTH2

VSSTH3

VSSTH4

VSSTH5

VSSTH6

VSSTH7

VSSTH8

VSSTH9

VSSTH10

VSSTH11

VSSTH12

VSSTH13

VSSTH14

VSSTH15

VSSTH16

VSSTH31

VSSTH30

VSSTH29

VSSTH28

VSSTH27

VSSTH26

VSSTH25

VSSTH24

VSSTH23

VSSTH22

VSSTH21

VSSTH20

VSSTH19

VSSTH18

VSSTH17

RESETB

IRQ

PWRRST

LED1

LED2

32KHZ

SIMOFF

SIMVCC

SIMDAT

SIMCLK

SIMRST

CDCDA

C2301

C2300

1608

CDCDB

VDD_A

B12

VDD_B

A11

EXTLDO

C11

VDD_D

VDD_E

VDDLP

M11

L12

C2203

R2305

15K

1608

R3376

R2313

R2306

VDD_A

VDD_B

EXTLDO

R2202

R2203

1608

R2107

VDDBUCK

PBUCK

NBUCK

SWBUCK

VBUCK

VDD_IO

R3345

2125

0.51

Q2200

3 D2

2 G1

1 S1

D1 6

SI1555DL

VBAT_C

R2235

VRTC

BA3000

C3247

BACKUP BATTERY

VBACKUP

R2208

0.1u

0.22

V2201

RB521S-30

TP3316 INDICATOR LED

V3202

RB521S-30

L2200 22uH

ELL5GM220M

CHOKE COIL

DACO1

DACO2

DACO3

G11

H11

TXON

EXPOUT

FF_IN

G10

F10

BEARP

BEARN

C2619

100u

R3031

C2638

C2637

VCORE

WDCDCREF

WPAREF

VCXOCONT

TXON

EXPOUT

FF_IN

C3248

0.1u

C2202

4.7u

R2210

C2206

2012

10u

V2300

IO1

DALC208SC6

IO4

REF2

IO2

REF1

IO3

R2201

R2213

0.22

L2202

VMEM

BLM18PG121SN1

1608 120 OHM BEAD

C2205 10u

2012

C2302 & C2303 CLOSER TO SIM SOCKET SIM HOLDER

R3248

VBATI

VCORE

C2604

0.1u

1608

C2200

10u

2012

R2200

RESOUT0n

IRQ0n

PWRRSTn

X2300

GND3

GND1

GND4 GND2

KPD9D-8S-2.54SF

N2603

ADG702

GND

VDD

R2607

3.9K

L2603

BLM15BB750SN1J

L2608

BLM15BB750SN1J

VDIG

C3221

AUXO1

CCO

C2608

1608

22K

R2617

C2612

0.068u

HOOK

22p

C2614

22p

C2618

C2611

100u

R2613

C2615

0.068u

C2617

0.068u

C2610

22p

C2609

0.01u

N2602 IP4025CX20

MICP

AFMS_R_INT

CCO

MICP_INT

MICN

ATMS

MICN_INT ATMS_CAP

AFMS_R

B4 D3

ATMS_INT

ATMS_AD

AFMS_L_INT

GND1

GND2

GND3

AFMS_L

VDD

GND4

GND5

GND6

C2616

22p

R3397

C2613

0.033u

C3277

4.7uF, 2012

X2603

SUMY0004501

OBG-15S44-C2KU

C3270

C3266

10p

X2602

C2630

22p

PWRRSTn

D2016

RB521S-30

C3267

TJATTE2

3.3V REG

N2204

ON_OFF BYPASS

GND

C2276

100p

C3268

47p

C3269

47p

VUSB

C3278

100p

R3395

VDIG

R3385

R3303

100K

R3381

47K

D2015

RB521S-30

IRDA_REG_CTRL

C2631

22p

C3275

VBUS

VIN VOUT

LP2985IM5X-3.3

R2232

10K C2278

2.2u

2012

C2277

4.7u

USBSENSE

R2233

51K

FB3

FB4

R2614

R2619

R2618

R3386

VBATI

C3051

2.2u

2012

C2635

C2603 1u

1608

R2615

VBATI

R2608

C2605

3.9K

0.1u

TP3318

TP3319

GPA6

GPIO05

C2634

AUDIO AMP

N3000

ON_OFF BYPASS

GND

VIN VOUT

LP2985IM5X-2.8

C3273

R2606

N2601

VDD

IN-

IN+

VO2

VO1

BYPASS

SD_SEL SD_MODE

GND

LM4898ITL

VDIG

R2609

33K

EARP

EARM

C2274

0.1u

33K

C3274

SPKMUTE

N2203

VIN VOUT

VSS NC

1 4

S-817A15ANB-CUE-T2

AMPCTRL

1.5V REGULATOR

C3046

100p

C3052

4.7u

R3050

TGBUZZ

C2606

0.33u

1608

R2610

100K

L2606

L2605

VIRDA

C2633

22p

C2632

22p

C2272

1608

VEXT15

R2621 0

R2620 0

2 3 4 5 6

USB REGULATOR

7 8

Changed by: mentor

SPKP

SPKM

IRDA REGULATOR

Date Changed:

Tuesday, September 04, 2003

Time Changed:

7:25:29 pm

Engineer:

TAE-SUNG, HA

Drawn by:

R&D CHK:

TAE-SUNG, HA

DOC CTRL CHK:

MFG ENGR CHK:

QA CHK:

TITLE:

REV:

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP 1

BB MAIN PCB

VINCENNE

Size:

12 1 8 A

U8120 PT V1.3 STG INTEL PAM

Drawing Number:

Page:

- 239 -

9. CIRCUIT DIAGRAM

RTCCLK

ONSWC

R2100

C2100 and C2101 close to B2100

32.768KHz

C2100

22p

TP3317

C2101

22p

RTC_GND

TP2106

VPPFLASH

PWRRSTn

CLKREQ

IRQ0n

PULSESKIP

R2123

120K

Q2100

R3100

RN1107

C2104

1000p

TP3313

VDIG

BL_PWL

7C_LED_VDD_EN

UART0

CAMERA_DET

GPIO05

AMPCTRL

TGBUZZ

UARTRX0

UARTTX0

UART1

DAC

USB

HSSL

MCLK

TP3126

SYSCLK1

SYSCLK2

RESOUT0n

RESOUT1n

TP2102

RESOUT3n

PWRREQn

ISSYNCn

ISEVENTn

UARTRX1

UARTTX1

UARTRTS1

UARTCTS1

CAM_REG_EN

CAM_FLASH_ON

TP2125

CAM_FLASH_SHOT

KEY_LED_ONOFF

LCDVSYNCI

SPKMUTE

USBSENSE

BL_EN

FOLDER_DET

EN_LED_R

EN_LED_G

EN_LED_B

IRDA_REG_CTRL

DACCLK

DACDAT

DACSTR

ADCSTR

USBDP

USBDM

USBPUEN

HSSLRXCLK

HSSLRX

HSSLTXCLK

HSSLTX

TP2404

TP2405

TP2401

TP2402

TP2403

TP2100 TP2101

D2012

C2102 330p

R2109 47

1SS388

P13

MCLK

SYSCLK0

SYSCLK1

SYSCLK2

SERVICE_N

RESPOW_N

RESOUT0_N

RESOUT1_N

RESOUT2_N

RESOUT3_N

RESOUT4_N

CLKREQ

PWRREQ_N

ISSYNC_N

ISEVENT_N

IRQ0_N

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

GPIO35

GPIO36

GPIO37

GPIO40

GPIO41

GPIO42

GPIO43

GPIO44

GPIO45

GPIO46

GPIO47

DACCLK

DACDAT

DACSTR

ADCSTR

M14

P18

R21

AA2

AA5

P10

P15

N14

W20

V19

W21

U18

T18

U19

U20

N15

U21

T19

T20

R19

R18

V17

AA21

Y19

AA20

W19

Y20

J15

J20

H19

USBDP

USBDM

USBPUEN

HSSLRXCLK

HSSLRX

HSSLTXCLK

HSSLTX

L14

NC0

JTAG I/F

MARITATCK

MARITATMS

MARITATDI

MARITATDO

MARITATRST

MARITARTCK

MARITATEMU0

MARITATEMU1

VIRDA

IrDA

N3100

CIM-80S7B-T

GND

VCC

SHIELD

RXD

TXD

LEDK

LEDA

SIR TRANCEIVER

SD(L:ACTIVE, H:SHUTDOWN)

LOW POWER MODE : LEDA VCC

C3137

0.47u

1608

RF I/F

VDDC 1.5V

VEXT15

VCORE

D2000

ROP-101-3035_1

MARITA

VDDE 1.5V

1.8V

VCORE VMEM

2.75V

VDIG

0.1u

C2221

0.1u

C2220

0.1u

C2223

0.1u

C2244

0.1u

C2247

0.1u

C2255

0.1u

C2218

0.1u

C2217

0.1u

C2222

0.1u

C2243

0.1u

C2246

0.1u

C2216

0.1u

C2242

0.1u

C2245

0.1u

C2219

0.1u

C2256

0.1u

C2250

0.1u

C2258

0.1u

C2257

0.1u

C2251

0.1u

C2252

0.1u

C2253

0.1u

C2262

0.1u

C2263

0.1u

C2259

0.1u

C2261

0.1u

C2260

KEY I/F PCM I/F

1.8V

VMEM

3.3V

VUSB

1.5V

VRTC VEXT15

R3333 NA

* MEMORY CHANGE HISTORY

U8100 WS01-1

U8100 WS01-2

U8100 WS01-3

U8100 WS01-4 2002.09.13

U8100 WS01-5

MCP 64/08.

64/64/16

0.8 PITCH 14 X 8 X 1.4

0.8 PITCH 10 X 8 X 1.4

U8100 ES01-1 DEFAULT

OPTION

U8100 ES01-2

U8100 ES01-3 TOSHIBA

U8100 ES01-6 TOSHIBA

OPTION

64/64/16

64D/64D/16PS

128L/128L

64/64/16

128/128/64

128

128/128/64

128

128/128

0.8 PITCH 10 X 8 X 1.4

0.8 PITCH 9 X 12 X 1.4

ADR(1:24)

D10

D11

D12

D13

D14

D15

CS0_N

CS1_N

CS2_N

CS3_N

WE_N

OE_N

MEMBE0_N

MEMBE1_N

MEMADV_N

MEMCLK

MEMWAIT_N

B10

F19

F20

G18

G19

G20

H18

H15

G21

E19

E20

E21

H14

D19

C19

D18

C20

C21

E18

B18

D17

C18

B19

A20

H13

G14

B20

PDIRES_N

PDIC0

PDIC1

PDIC2

PDIC3

PDIC4

PDID0

PDID1

PDID2

PDID3

PDID4

PDID5

PDID6

PDID7

I2CSCL

I2CSDA

CIPCLK

CIVSYNC

CIHSYNC

CIRES_N

CID0

CID1

CID2

CID3

CID4

CID5

CID6

CID7

A17

A18

A19

A20

A21

A22

A23

A24

A10

A11

A12

A13

A14

A15

A16

C17

B17

G13

C16

C15

B15

H12

D14

B14

C14

G12

B13

C13

H11

D12

C12

G11

D11

C11

H10

C10

D10

DAT(6)

DAT(7)

DAT(8)

DAT(9)

DAT(10)

DAT(11)

DAT(12)

DAT(13)

DAT(14)

DAT(15)

DAT(0)

DAT(1)

DAT(2)

DAT(3)

DAT(4)

DAT(5)

VDIG

ADR(9)

ADR(10)

ADR(11)

ADR(12)

ADR(13)

ADR(14)

ADR(15)

ADR(16)

ADR(17)

ADR(18)

ADR(19)

ADR(1)

ADR(2)

ADR(3)

ADR(4)

ADR(5)

ADR(6)

ADR(7)

ADR(8)

ADR(20)

ADR(21)

ADR(22)

ADR(23)

ADR(24)

DAT(0:15)

CS2 not used

MEM_CS0_N

MEM_CS1_N

MEM_CS3_N

MEM_WE_N

MEM_OE_N

MEM_BE0_N

MEM_BE1_N

MEM_ADV_N

MEM_CLK

LCDRESX

LCDCSX_SUB

LCDWRX

LCDRS

LCDCSX_MAIN

LCDRDX

PDID0

LCD I/F

PDID1

PDID2

PDID3

PDID4

PDID5

PDID6

PDID7

VDIG

VCORE VDIG

I2CDAT

CIPCLK

CIVSYNC

CIHSYNC

CIRES_N

CID0

CID1

CID2

CID3

CID4

CID5

CID6

CID7

CAMERA I/F

VMEM

MEM_WAIT_N

VMEM

RTC_GND

I2CCLK

I2CCLK_CAMERA

U8100 PT V1.0 NMBI TOSHIBA

U8100 PT V1.0 Staggered TOSHIBA

U8100 PT V1.1 Staggered AMD

U8120 PT V1.1 Staggered INTEL

128/128/64

128

128/128/64

128

128/128/64

128

256/64

256 option-128

0.8 PITCH 9 X 12 X 1.4

0.8 PITCH 9 X 12 X 1.25

0.8 PITCH 9 X 11.5 X 1.0

0.8 PITCH 8 X 11 X 1.2

0.8 PITCH 8 X 11 X 1.0

0.8 PITCH 8 X 10 X 1.2

DAT(0:15)

Rout track on inner layer

DAT(8)

DAT(7)

DAT(6)

DAT(5)

DAT(4)

DAT(3)

DAT(2)

DAT(1)

DAT(0)

DAT(15)

DAT(14)

DAT(13)

DAT(12)

DAT(11)

DAT(10)

DAT(9)

DAT(0:15)

Rout track on inner layer

DAT(8)

DAT(7)

DAT(6)

DAT(5)

DAT(4)

DAT(3)

DAT(2)

DAT(1)

DAT(0)

DAT(15)

DAT(14)

DAT(13)

DAT(12)

DAT(11)

DAT(10)

DAT(9)

CS1

MEM_CS1_N

VMEM

MEM_CS0_N

CS 0,3

MEM_CS3_N

MEM_CLK

MEM_WAIT_N

RESOUT0n

MEM_ADV_N

MEM_OE_N

MEM_WE_N

MEM_BE1_N

MEM_BE0_N

MEM_CLK

MEM_WAIT_N

RESOUT0n

MEM_ADV_N

MEM_OE_N

MEM_WE_N

ADDRESS X DATA = 2^24 X 2^4 = 2^28 =256MBIT

A23 = 256MBIT

D15

D14

D13

D12

D11

D10

_F3_CE

_F2_CE

_F1_CE

S_CS2

_S_CS1

_P1_CS

_P2_CS U3103

RD38F4050L0YTQ0

P_MODE

CLK

WAIT

MCP

A25

A24

A23

A22

A21

A20

A19

A18

A12

A11

A10

A17

A16

A15

A14

A13

_F_RST

_F_WP

_ADV

_F2_OE

_F1_OE

_R_OE

F2_VCC1

F2_VCC2

_F_WE

_R_WE

F1_VCC1

F1_VCC2

_R_UB

_R_LB

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VSS0

VCCQ2

VCCQ1

VCCQ0

S_VCC

P_VCC

F_VPP

C3136

0.22u

50V 1608

VMEM

ADR(15)

ADR(14)

ADR(13)

ADR(12)

ADR(11)

ADR(10)

ADR(9)

ADR(8)

ADR(7)

ADR(6)

ADR(5)

ADR(4)

ADR(3)

ADR(2)

ADR(1)

ADR(24)

ADR(23)

ADR(22)

ADR(21)

ADR(20)

ADR(19)

ADR(18)

ADR(17)

ADR(16)

ADR(1:24)

C3133

0.1u

C3135 C3134

0.1u

VMEM

R3400 0

V2203

RB521S-30

VPPFLASH_MEM

ADDRESS X DATA = 2^24 X 2^4 = 2^28 =256MBIT

A23 = 256Mbit, A22=128Mbit

D15

D14

D13

D12

D11

D10

_F3_CE

_F2_CE

_F1_CE

S_CS2

_S_CS1

_P1_CS

_P2_CS U3104

NZ48F4000L0YBQ0

P_MODE

CLK

WAIT

_F_RST

FLASH

_F_WP

_ADV

_F2_OE

F2_VCC1

F2_VCC2

_F1_OE

_R_OE

A18

A17

A16

A15

A14

A13

A12

A11

A10

A25

A24

A23

A22

A21

A20

A19

_F_WE

_R_WE

F1_VCC1

F1_VCC2

_R_UB

_R_LB

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VSS0

VCCQ2

VCCQ1

VCCQ0

S_VCC

P_VCC

F_VPP

Short-256Mbit

Open-128Mbit

C3 R3399

ADR(24)

ADR(23)

ADR(22)

ADR(21)

ADR(20)

ADR(19)

ADR(18)

ADR(17)

ADR(16)

ADR(15)

ADR(14)

ADR(13)

ADR(12)

ADR(11)

ADR(10)

ADR(9)

ADR(8)

ADR(7)

ADR(6)

ADR(5)

ADR(4)

ADR(3)

ADR(2)

ADR(1)

ADR(1:24)

C3276

0.1u

C3222

0.1u

VPPFLASH_MEM

VMEM

C3225

0.22u

50V 1608

Changed by: mentor

Date Changed:

Tuesday, September 04, 2003

Time Changed:

9:42:54 am

Engineer:

Drawn by:

SUNG-JU, YOU

R&D CHK:

SUNG-JU, YOU

TITLE:

DOC CTRL CHK:

MFG ENGR CHK:

QA CHK: REV:

LG ELECTRONICS INC.

3G HANDSETS LAB

DEVELOPMENT GROUP1

BB MAIN PCB

MARITA

Size:

12 1 8 A

U8120 PT V1.3 STG INTEL PAM

Drawing Number:

Page:

- 240 -

9. CIRCUIT DIAGRAM

1 2 3 4 5 6 7 8 9 10 11 12

VDIG VBATI

CONN_10_5087_060_920_829

X3200

B'd to B'd CONNECTOR I/F

ONSWAn

KEYIN0

KEYIN1

KEYIN2

KEYIN3

KEYIN4

7C_LED_VDD

CAM_FLASH_ON

CAM_FLASH_SHOT

BL_PWL

FOLDER_DET

KEY_LED-

EARM

EARP

BL_EN

MOTOR_BATT

SPKP

SPKM

LCDCSX_SUB

LCDRESX

LCDVSYNCI

LCDWRX

LCDRS

LCDCSX_MAIN

LCDRDX

PDID0

PDID1

PDID2

PDID3

PDID4

PDID5

PDID6

PDID7

EN_LED_R

EN_LED_G

EN_LED_B

KEYOUT0

KEYOUT1

KEYOUT2

KEYOUT3

KEYOUT4

KEYOUT5

MARITATEMU1

MARITATEMU0

MARITARTCK

MARITATRST

MARITATDO

MARITATDI

MARITATMS

MARITATCK

CAM_REG_EN

VBATI

C3244

2.2u

2012

U3102

GND

OUT

ADJ

MIC5219BM5

C3243

470p

CAMERA REGULATOR

VCAM

C3245

10u

VCAM

C3204

0.1u

R3206

100K

CAMERA_DET

C3205

10p

CAMERA ROTATION DETECTOR

2 3

CID4

CID5

CIVSYNC

CID1

CID2

CIPCLK

CID0

CID3

SYSCLK1

R3357 51

R3360 51

R3363 51

X3201

PDM : ENBY0017602

AXK7L80225

CAMERA I/F

R3364

R3365

R3366

R3367

FB2

1608

I2CCLK_CAMERA

CIRES_N

CIHSYNC

FB1

1608

I2CDAT

CID6

CID7

VCAM

7C_LED_VDD

R3388

C3202

10u

2012

R3263

4.7

VBATI

C3203

1608

C3200 1u

1608

SC600B

N3201 SC600BIMSTR

VOUT CF2+

CF1+

VIN

FID0

FID1

CF1-

GND

CF2-

R3389

C3201

1608

100

CHARGE PUMP

R3390 100

D2013

1SS388

D2014

1SS388

7C_LED_VDD_EN

EN_LED_TC B

SUB LCD BACKLIGHT 4.5V

KEY_LED-

R3207

R3208

6 5 4

EMX18

Q3200

1 2 3

CURRENT LIMIT

15mA x 16 = 240mA

KEYPAD BACKLIGHT BLUE LED I/F

KEY_LED_ONOFF

VDIG

HF DETECTION

TP3200

VBAT

DCIN_2

KNATTE

TP3342 TP3341

VPPFLASH_MEM

VPPFLASH

R3401 NA

UARTRX1

UARTTX1

UARTRX0

UARTTX0

ONSWBn

DCIN_3

TP3306

R3353

R3352

R3351

R3350

VDIG

N2300 IP4022CX20

TP3337

TP3336 D1

DTMS_i

DFMS_i

CTMS_i

CFMS_i

VPPFLASH_i

CTS_ON_i

DCIO_i

DTMS_e

DFMS_e

CTMS_e

CFMS_e

VPPFLASH_e

CTS_ON_e

DCIO_e

TP3343

TP3340

TP3338

TP3339

UARTCTS1

UARTRX1

USBDP

USBDM

Q2300

RN1107

C3220

0.1u

VBUS

VBATI

R2502

V2500

RB521S-30

TP3346

R2500

L2500

GND

3_3V

USBUF01W6

R2501

TP3345

TP3344

VBACKUP

PCMCLK

PCMSYN

HF MIC TP3202

PCMDATA

HF SPK N

TP3203

HF SPK P TP3204

UARTRTS1

PCMDATB

VBAT

USBPUEN

UARTTX1

USB FILTER

R3220

R3249

R3222

R3223

R3225

R3227

R3228

R3229

R3230

R2319

R3232

R3233

I/O CONNECTOR

5 6 7 8

Q3201 NA

UMC4N

BLM18PG121SN1

L2201

C3215

33u

3216

C2208

1608

PDM : ENEY0003301

20_5124_024_500_858

X3203

VBAT_GND_1

VBAT_GND_2

BATT_ID

HF_MODE

DSR

PWR_+5V_1

PWR_+5V_2

ON_SW1

PCM_RXA_IN

PCM_CLK

PCM_SYNC

USB_RX

PCM_TXA_OUT

PWR_GND_1

RXD

TXD

USB_TX

USB_PWR

DCD

RI_TMS

PWR_GND_2

RFR_RTS

PWR_+4_2V_1

PWR_+4_2V_2

CTS

DTR

V_BAT_1

V_BAT_2

V_BAT_3

GND1

GND2

TP3307

CRS08

V3200

R3235

2.75V

DTC SENSE

TP3205

Changed by: mentor

Date Changed:

Tuesday, September 04, 2003

Time Changed:

2:11:39 pm

Engineer:

Drawn by:

R&D CHK:

S .Y SEOK

DOC CTRL CHK:

MFG ENGR CHK:

QA CHK:

TITLE:

REV:

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP1

BB MAIN PCB

MULTIMEDIA INTERFACE

Size:

12 1 8 A

U8120 PT V1.3 STG INTEL PAM

Drawing Number:

Page:

- 241 -

9. CIRCUIT DIAGRAM

1.5V

VCORE

1.5V

VCORE VRTC VEXT15

VEXT15 WANDAVDDA

VCORE WANDAVDDD

VDIG VCORE

RF CONTROL

WSTR

RF RX DATA

RF TX DATA

Q3204 PMST3904

WCLK

WDAT

R3326

RXIA

RXIB

RXQA

RXQB

ADCSTR

TXIA

TXIB

TXQA

TXQB

HSSL LINK (MARITA)

CLK INTERFACE

VINCENNE INTERFACE

HSSLTX

HSSLRXCLK

HSSLRX

HSSLTXCLK

ISSYNCn

ISEVENTn

MCLK

RTCCLK

CLKREQ

RESOUT1n

DACCLK

DACDAT

DACSTR

TP2119

TP2116

C2103

330p

R2400

43K

G16

G17

G15

F16

G13

E15

F13

JTAG_TRSTN

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

EMU1

EMU0

R17

P15

M13

RADIO_CLK

RADIO_DAT

RADIO_STR

C2400

R10

N10

T10

0.1u

M16

ADC_I_IN

ADC_I_IN_INV

ADC_Q_IN

ADC_Q_IN_INV

ADC_RXEXTREF_P

ADC_RXEXTREF_N

AD_STR

DAC_I_OUT

DAC_I_OUT_INV

DAC_Q_OUT

DAC_Q_OUT_INV

DAC_TXEXTRES

B16

A16

A15

C14

HSSLRX_D

HSSLTX_CLK

HSSLTX_D

HSSLRX_CLK

A13

B12

U12

ID_BALL

IS_SYNC_N

IS_EVENT_N

APLL_ATEST1

U13

T16

R15

T15

N13

MCLK

CLK32

HCLK

CLKRQ

RESET_N

N15

L13

M15

DAC_CLK

DAC_DAT

DAC_STR

E12

C13

UART_TX

UART_RX

C2215

0.1u

R2120

D2006

ROP-101-3033_1

EMIF_D0

EMIF_D1

EMIF_D2

EMIF_D3

EMIF_D4

EMIF_D5

EMIF_D6

EMIF_D7

EMIF_D8

EMIF_D9

EMIF_D10

EMIF_D11

EMIF_D12

EMIF_D13

EMIF_D14

EMIF_D15

EMIF_D16

EMIF_D17

EMIF_D18

EMIF_D19

EMIF_D20

EMIF_D21

EMIF_D22

EMIF_D23

EMIF_D24

EMIF_D25

EMIF_D26

EMIF_D27

EMIF_D28

EMIF_D29

EMIF_D30

EMIF_D31

EMIF_AWE_N

EMIF_ARE_N

EMIF_AREADY

EXT_MEM_UBUS10

EXT_MEM_UBUS11

EXT_MEM_UBUS12

EXT_FRAME_STROBE

N12

T14

R14

E17

CPU_IACK

CPU_XF

CPU_IRQ1

CPU_IRQ0

CPU_CLKOUT

M17

C2227

0.1u

C2238

0.1u

C2236

0.1u

C2240

0.1u

C2230

0.1u

C2224

0.1u

C2239

0.1u

C2232

0.1u

C2226

0.1u

C2229

0.1u

C2234

0.1u

C2241

0.1u

C2235

0.1u

C2228

0.1u

C2225

0.1u

C2233

0.1u

C2231

0.1u

C2237

0.1u

TP2120

Changed by: mentor

Date Changed:

Tuesday, September 04, 2003

Time Changed:

9:42:54 am

Engineer:

MYUNG-LAE, CHO

Drawn by:

MYUNG-LAE, CHO

R&D CHK:

TITLE:

DOC CTRL CHK:

MFG ENGR CHK:

QA CHK: REV:

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP 1

BB MAIN PCB

WANDA

Size:

12 1 8 A

U8120 PT V1.3 STG INTEL PAM

Drawing Number:

Page:

- 242 -

9. CIRCUIT DIAGRAM

1 2 3 4

VBATI_4.2V

7C_LED_VDD

VDIG_2.8V

CN962

BOARD TO BOARD CONECTOR

ONSWAn

KEYIN0

KEYIN1

KEYIN2

KEYIN3

KEYIN4

CAM_FLASH_ON

CAM_FLASH_SHOT

BL_PWL

FOLDER_DET

KEY_LED-

EARM

EARP

BL_EN

MOTOR_BATT

SPKP

SPKM

LCDCSX_SUB

LCDVSYNCI

LCDWRX

LCDRS

LCDCSX_MAIN

LCDRDX

PDID0

PDID1

PDID2

PDID3

PDID4

PDID5

PDID6

PDID7

EN_LED_R

EN_LED_G

EN_LED_B

KEYOUT0

KEYOUT1

KEYOUT2

KEYOUT3

KEYOUT4

KEYOUT5

MARITATEMU1

MARITATEMU0

MARITARTCK

MARITATRST

MARITATDO

MARITATDI

MARITATMS

MARITATCK

LCDRESX

CAM_FLASH_ON

EARP

EARM

EN_LED_R

EN_LED_B

BL_PWL

PDID1

PDID3

PDID5

PDID7

LCDWRX

LCDCSX_MAIN

LCDRESX

LCDVSYNCI

LCDCSX_SUB

LCDRS

LCDRDX

PDID6

PDID4

PDID2

PDID0

BL_EN

EN_LED_G

SPKM

SPKP

MOTOR_BATT

CAM_FLASH_SHOT

D2 SMF05C

R1152

R1151

270

C27 C28

47p 47p

R1134

R1135

R1136

R1137

R1138

R1139

100

C29 C30 C31 C32 C33 C34

30p 30p 30p 30p 30p 30p

R1145

R1140

R1141

R1142

R1143

R1144

100

C35 C36 C37 C38 C39 C40

30p 30p 30p 30p 30p 30p

R1146

R1147

R1148

R1149

R1150

R1153

100

270

C43 C44 C45 C46 C41 C42

30p 30p 30p 30p 30p 47p

TOSHIBA LCD I/F

U8100 KEY V0.8

2003.11.18

LCDRESX PULL DOWN R MOVE

TVS VDIG

U8100 KEY PT V1.1

2004.01.14

ESD EMI FILTER -> RC Filter

VBATI_4.2V

HSMR-C191

KEY_LED-

1 2 3

KEYPAD BACKLIGHT BLUE LED

4 5

8 9 10 11 12

CONN_40_AXK840145J

CN963

VBATI_4.2V

VDIG_2.8V

7C_LED_VDD

C26

0.1u

KB26

END

1SS388

KB1

KB2

KB3

KB4

SEND

KB5

MENU

SIDE1

KB6

KB7

KB8

KB9

CLEAER

KB10

SIDE2

KB11

KB12

KB13

KB14

BACK

KB15

SEARCH

MULTI

SIDE3

KB16

KB17

KB18

KB19

U8100_SIDEKEY_PAD

R1103

470

R1102

470

R1104

470

KB21

C23

470p

C24

470p

C22

470p

CN964

4 R1154 470

KEYOUT0

KEYOUT1 C

KB22

KEYOUT2

DOWN

KB23

KEYOUT3

RIGHT

KB24

KEYOUT4

GAME LEFT

KB20 KB25

KEYOUT5

CAM OK

KEYPAD

VDIG_2.8V

R1130

100K

C25

0.1u

C21

10p

FOLDER_DET

6 7

FOLDER OPEN DETECTOR

Changed by: mentor

Date Changed:

FEB,17,2003

Engineer:

Drawn by:

R&D CHK:

DOC CTRL CHK:

MFG ENGR CHK:

Time Changed: QA CHK:

TITLE:

REV:

LG ELECTRONICS INC.

3G HANDSETS LAB.

DEVELOPMENT GROUP 1

U8100 KEY PT V1.3

BB KEY PAD PCB

2004.02.09

Drawing Number:

Size:

12 1 8 A

Page:

- 243 -

10. PCB LAYOUT

- 244 -

10. PCB LAYOUT

- 245 -

10. PCB LAYOUT

- 246 -

10. PCB LAYOUT

- 247 -