SERVICE MANUAL DV985S

SERVICE MANUAL
DV985S
CONTENTS
SAFETY PRECAUTIONS
1
PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES)DEVICES
1
CONTROL BUTTON LOCATIONS AND EXPLANATIONS
2
PREVERTION OF STATIC ELECTRICITY DISCHARGE
3
ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT
4
OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST
4
BRACKET EXPLOSED VIEW AND PART LIST
6
MISCELLANEOUS
7
ELECTRICAL CONFIRMATION
8
VI DEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION
8
VI DEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION
9
MPEG BOARD CHECK WAVEFORM
10
FLI2300 DIGITAL VIDEO CONVERTER DATE SHEET
11
AM29LV160D
19
HY57V641620HG
24
SiI 164 PANELLINK TRANSMITTER
27
MT1389
41
SCHEMATIC & PCB WIRING DIAGRAM
44
SPARE PARTS LIST
60
1. SAFETY PREAUTIONS
1.1 GENERAL GUIDELINES
1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have
been overheated or damaged by the short circuit.
2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers
shields are properly installed.
3. After servicing, make the following leakage current checks to prevent the customer from being exposed
to shock hazards.
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO
ELECTROSTATICALLY SENSITIVE(ES)DEVICES
Some semiconductor(solid state)devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive(ES)Devices. Examples of typical ES devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain
off any ESD on your body by touching a known earth ground. Alternatively, obtain and wear a commercially
availabel discharging ESD wrist strap, which should be removed for potential shock reasons prior to
applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES
devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are
ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam, alminum foil or comparable conductive material).
7. Immediately before removing the protective material from the leads of a replacement ES device, touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD).
notice (1885x323x2 tiff)
1
Front Panel Illustration
3
2
POWER switch
4
IR SENSOR
2
Disc tray
5
Display window
3
OPEN/CLOSE button
6
PLAY/PAUSE button
2
4
5
6
7
7
STOP button
4.PREVENTION OF STATIC ELECTRICITY DISCHARGE
The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
body. Use due caution to electrostatic breakdown when servicing and handling the laser diode.
4.1.Grounding for electrostatic breakdown prevention
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
grounding works is completed.
4.1.1. Worktable grounding
1. Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the
sheet.
4.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity from your body.
safety_3 (1577x409x2 tiff)
4.1.3.Handling of optical pickup
1. To keep the good quality of the optical pickup maintenance parts during transportation and before
installation, the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure. (See this Technical Guide).
2. Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
4.2. Handling precautions for Traverse Unit (Optical Pickup)
1. Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2. When replacing the optical pickup, install the flexible cable and cut is short land with a nipper. See the
optical pickup replacement procedure in this Technical Guide. Before replacing the traverse unit, remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
3. The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
4. The half-fixed resistor for laser power adjustment cannot be adjusted. Do not turn the resistor.
3
5. Assembling and disassembling the mechanism unit
5.1 Optical pickup Unit Explosed View and Part List
Pic (1)
4
Materials to Pic (1)
No.
PARTS CODE
PARTS NAME
Q ty
14692200
SF-HD60
1
1
1EA0311A06300
ASSY, CHASSIS, COMPLETE
1
2
1EA0M10A15500
ASSY, MOTOR, SLED
1
Or
1EA0M10A15501
ASSY, MOTOR, SLED
1
3
1EA2451A24700
HOLDER, SHAFT
3
4
1EA2511A29100
GEAR, RACK
1
5
1EA2511A29200
GEAR, DRIVE
1
6
1EA2511A29300
GEAR, MIDDLE, A
1
7
1EA2511A29400
GEAR, MIDDLE, B
1
8
1EA2744A03000
SHAFT, SLIDE
1
9
1EA2744A03100
SHAFT, SLIDE, SUB
1
10
1EA2812A15300
SPRING, COMP, TYOUSEI
3
11
1EA2812A15400
SPRING, COMP, RACK
1
21
1EA0B10B20100
ASSY, PWB
1
Or
1EA0B10B20200
ASSY, PWB
1
31
SEXEA25700---
SPECIAL SCREW BIN+-M2X11
3
32
SEXEA25900---
SPECIAL SCREW M1.7X2.2
2
33
SFBPN204R0SE-
SCR S-TPG PAN 2X4
2
34
SFSFN266R0SE-
SCR S-TPG FLT 2.6X6
1
35
SWXEA15400---
SPECIAL WASHER 1.8X4 X0.25
2
Note : This parts list is not for service parts supply.
5
5.2 Bracket Explosed View and Part List
Pic (2)
Materials to Pic(2)
1.bracket
2.belt
3.screw
4.belt wheel
5.gearwheel
6.iron chip
7. Immobility mechanism equipment
8. Magnet
9. Platen
10. Bridge bracket
11. screw
12. screw
13. Big bracket
14. front silicon rubber
15. Back silicon rubber
16. Pick-up
17. Pick-up
18. switch
19. Five-pin flat plug
20. screw
21. PCB
22. motor
23. Motor wheel
24. screw
25.tray
Before going process with disassembly and installation, please carefully both
peruse the chart and confirm the materials.
6
5.3 MISCELLANEOUS
5.3.1 Protection of the LD(Laser diode)
Short the parts of LD circuit pattern by soldering.
5.3.2 Cautions on assembly and adjustment
Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are
grounded,and that personnel wear wrist straps for ground.
Open the LD short lands quickly with a soldering iron after a circuit is connected.
Keep the power source of the pick-up protected from internal and external sources of electrical
noise.
Refrain from operation and storage in atmospheres containing corrosive gases (such as H2S,SO2,
NO2 and Cl2)or toxic gases or in locations containing substances(especially from the organic silicon,cyan,
formalin and phenol groups)which emit toxic gases.It is particularly important to ensure that none of the
above substances are present inside the unit.Otherwise,the motor may no longer run.
7
6.Electrical Confirmation
6.1. Video Output (Luminance Signal) Confirmation
DO this confirmation after replacing a P.C.B.
Measurement point
Mode
Disc
Video output terminal
Color bar 75%
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
DVDT-S15
or
DVDT-S01
Measuring equipment,tools
Confirmation value
200mV/dir,10 sec/dir
1000mVp-p±30mV
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV
8
6.2 Video Output(Chrominance Signal) Confirmation
Do the confirmation after replacing P.C.B.
Measurement point
Mode
Disc
Video output terminal
Color bar 75%
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
DVDT-S15
or
DVDT-S01
Measuring equipment,tools
Screwdriver,Oscilloscope
200mV/dir,10 sec/dir
Confirmation value
621mVp-p±30mV
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV
9
7.MPEG BOARD CHECK WAVEFORM
7.1 27MHz WAVEFORM
DIAGRAM
7.2 IC5L0380R PIN.2 WAVEFORM DIAGRAM
10
FLI2300 Digital Video Converter Data Sheet
1
DESCRIPTION
1.5
The FLI2300 is a highly integrated digital video
format converter for CRT-TV applications using
patented deinterlacing and post processing algorithms
from Faroudja Laboratories, coupled with highly
flexible scaling, a wide variety of aspect ratio
conversions, and other special video enhancing
features to produce the highest quality image.
1.1
•
•
•
1.2
Cross Color Suppressor (CCS) - Removes cross
color artifacts in composite video signals due to
poor Y/C separation in standard 2-D video
decoders, eliminating the need for expensive 3-D
video decoders.
Outputs
Interlaced or Progressive output
•
The output can be either analog YUV/RGB
through the integrated 10-bit Digital-To-Analog
Converter (DAC), or digital 24-bit RGB, YCrCb,
YPrPb (4:4:4), or digital 16/20-bit Y Cr/Cb
(4:2:2) Output pixel rate up to 150 MHz
maximum
Per-pixel Motion Adaptive Deinterlacing
•
Patented FilmMode Processing - Used for proper
de-interlacing of 3:2 and 2:2 pulldown material.
•
Edit Correction - Film content is continuously
monitored for any break in sequence caused by
“bad edits” and quickly compensates for the
most effective reduction in artifacts.
•
DCDi™ by Faroudja - Video is analyzed on a
single pixel granularity to detect presence or
absence of angled lines and edges, which are
then processed to produce a smooth and natural
looking image without visible artifacts or
“jaggies”.
1.7
Formats
•
Input color manipulation matrix supports all
color spaces: RGB, YPrPb, 4:4:4 YCrCb, 4:2:2
YCr/Cb, ITU-R BT656, ITU-R BT601
•
Output supports analog RGB, YPrPb, and
YCrCb;
•
Output supports digital RGB, YPrPb, 4:4:4
YCrCb and 4:2:2 YCr/Cb
Deinterlacing
•
Input pixel rate up to 75MHz maximum
•
•
•
1.6
Digital input, 8-bit Y/Cr/Cb (ITU-R BT656), 8bit Y/Pr/Pb, 16-bit Y Cr/Cb (ITU-R BT601), 24bit RGB, YCrCb, YPrPb
Output resolutions include 480p, 576p, 720p,
1080i, 1080p, and VGA to SXGA
1.4
Motion Adaptive Noise Reduction - Improves
picture quality for off-air material.
Inputs
Input all industry standard and non-standard
video resolutions, including 480i (NTSC), 576i
(PAL/SECAM), 480p, 720p, 1080i, and VGA to
XGA
•
1.3
Front End Processing
•
Scaling
•
High Quality Fully
Dimensional Scaler
•
Aspect Ratio Conversion for “Anamorphic” or
“Panoramic” (non-linear)
•
Display 4:3 images on 16:9 displays and vice
versa, including Letterbox to Fullscreen,
Pillarbox, and Subtitle Display Modes
•
Pixel and line dropper to generate PIP windows
1.8
•
Programmable
Two
TrueLife™ Enhancer
Two dimensional, non-linear, luma and chroma
video enhancer brings out details in the picture,
producing a more life-like image.
Frame Rate Conversion
Tearless
Frame
50/60/72/75/100/120 Hz
Rate
1.9
Conversion
•
Memory
32-bit wide SDRAM (i.e. one 2M x 32-bit)
controller, up to 166 MHz operation, for external
SDRAM
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
11
FLI2300 Digital Video Converter Data Sheet
2
BLOCK DIAGRAMS
Figure 2.1: FLI2300– Simplified Internal Block Diagram
Port 2
8-bit
656 Input
Port 1
8/16/24-bit
RGB/YCrCb
Input
Input Processor
with Auto Sync
and auto Adjust
Clock
Generation
PLLs
Noise Reducer,
Deinterlacer, Frame
Rate Converter and
SDRAM interface
Vertical and
Horizontal
Scalers
Output
Processor with
Sync Generation
and DACs
Vertical and
Horizontal
Enhancers
2Mx32
SDRAM
(external)
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12
16/20/24-bit
RBG/YCrCb
Digital Outputs
RBG/YCrCb
Analog Outputs
FLI2300 Digital Video Converter Data Sheet
3
PIN INFORMATION
3.1
Pin Diagram
IN_CLK1_PORT1
HSYNC2_PORT1
PLL_PVSS
PLL_PVDD
AVDD_PLL_BE2
AVDD_PLL_BE1
AVSS_PLL_BE1
160
165
AVDD_PLL_FE
AVDD_PLL_SDI
AVSS_PLL_SDI
AVSS_PLL_BE2
DAC_PVSS
AVSS_PLL_FE
DAC_VDD
DAC_VSS
DAC_AVDDB
DAC_B_OUT
DAC_AVSSG
DAC_AVDDG
DAC_G_OUT
DAC_AVSSB
170
180
175
DAC_AVSSR
DAC_AVDDR
DAC_R_OUT
DAC_VREFIN
DAC_VREFOUT
DAC_RSET
DAC_COMP
DAC_GR_AVSS
DAC_AVSS
DAC_AVDD
DAC_GR_AVDD
185
TEST0
DAC_PVDD
TEST1
XTAL IN
TEST2
190
IN_CLK_PORT2
VDD9
XTAL OUT
VSS
D1_IN_1
VDDcore8
D1_IN_0
D1_IN_4
D1_IN_3
D1_IN_2
VSScore
195
1
200
D1_IN_6
D1_IN_5
FIELD ID_PORT2
D1_IN_7
205
HSYNC_PORT2
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
VSYNC_PORT2
Figure 3.1: Pinout Information
155
G/Y/Y_OUT_6
G/Y/Y_OUT_5
G/Y/Y_OUT_4
5
G/Y/Y_OUT_3
VSYNC2_PORT1
150
FIELD ID2_PORT1
VDD1
VSS
IN_CLK2_PORT1
B/Cb/D1_0
VSS
VDD8
145
15
R/V/Pr_OUT_4
VDDcore1
VSScore
140
B/Cb/D1_5
20
135
R/Cr/Cb Cr_1
B/U/Pb_OUT_5
25
B/U/Pb_OUT_4
R/Cr/Cb Cr_5
R/Cr/Cb Cr_6
130
R/Cr/Cb Cr_7
G/Y/Y_0
30
B/U/Pb_OUT_1
B/U/Pb_OUT_0
125
CTLOUT4
120
40
TEST OUT0
115
TEST
DEV_ADDR1
TEST3
SDRAM CLKIN
VSS
45
VDD6
SDATA
RESET_N
110
VDD3
VSS
SDRAM CLKOUT
SDRAM DQM
SDRAM CSN
SDRAM BA0
SDRAM BA1
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13
SDRAM ADDR(0)
SDRAM ADDR(1)
SDRAM WEN
105
100
Package: 208-pin PQFP
SDRAM ADDR(3)
SDRAM ADDR(2)
SDRAM ADDR(5)
SDRAM ADDR(4)
VDDcore5
VSScore
95
SDRAM ADDR(7)
SDRAM ADDR(6)
SDRAM ADDR(8)
SDRAM ADDR(9)
90
TEST IN
SDRAM ADDR(10)
VDD5
VSS
SDRAM DATA(31)
85
SDRAM DATA(28)
SDRAM DATA(29)
SDRAM DATA(30)
SDRAM DATA(26)
SDRAM DATA(27)
80
VSScore
SDRAM DATA(25)
VDDcore4
SDRAM DATA(23)
SDRAM DATA(24)
SDRAM DATA(22)
75
SDRAM DATA(20)
SDRAM DATA(21)
SDRAM DATA(18)
SDRAM DATA(19)
SDRAM DATA(17)
VDDcore3
VSScore
SDRAM DATA(16)
65
SDRAM DATA(14)
SDRAM DATA(15)
SDRAM DATA(13)
VSS
SDRAM DATA(12)
60
SDRAM DATA(11)
VDD4
SDRAM DATA(7)
SDRAM DATA(8)
SDRAM DATA(9)
SDRAM DATA(10)
SDRAM DATA(6)
SDRAM DATA(5)
SDRAM DATA(4)
SDRAM DATA(3)
70
50
55
SDRAM DATA(0)
SDRAM DATA(1)
SDRAM DATA(2)
CTLOUT3
CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
IN_SEL
DEV_ADDR0
SCLK
CLKOUT
VSScore
VDDcore6
35
VDDcore2
VSScore
G/Y/Y_5
G/Y/Y_6
G/Y/Y_7
B/U/Pb_OUT_3
B/U/Pb_OUT_2
VSS
VDD7
G/Y/Y_1
G/Y/Y_2
G/Y/Y_3
G/Y/Y_4
R/V/Pr_OUT_0
B/U/Pb_OUT_7
B/U/Pb_OUT_6
R/Cr/Cb Cr_2
VDD2
VSS
R/V/Pr_OUT_3
R/V/Pr_OUT_2
VSScore
VDDcore7
R/V/Pr_OUT_1
B/Cb/D1_6
R/Cr/Cb Cr_3
R/Cr/Cb Cr_4
R/V/Pr_OUT_7
R/V/Pr_OUT_6
R/V/Pr_OUT_5
B/Cb/D1_2
B/Cb/D1_3
B/Cb/D1_7
R/Cr/Cb Cr_0
G/Y/Y_OUT_2
G/Y/Y_OUT_1
G/Y/Y_OUT_0
10
B/Cb/D1_1
B/Cb/D1_4
OE
G/Y/Y_OUT_7
SDRAM CASN
SDRAM RASN
FLI2300 Digital Video Converter Data Sheet
3.2
Pin
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Pin details
Pin Name
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1
VSS
IN_CLK2_PORT1
B/Cb/D1_0
B/Cb/D1_1
B/Cb/D1_2
B/Cb/D1_3
B/Cb/D1_4
VDDcore1
VSScore
B/Cb/D1_5
B/Cb/D1_6
B/Cb/D1_7
R/Cr/Cb Cr_0
R/Cr/Cb Cr_1
R/Cr/Cb Cr_2
R/Cr/Cb Cr_3
R/Cr/Cb Cr_4
R/Cr/Cb Cr_5
R/Cr/Cb Cr_6
R/Cr/Cb Cr_7
G/Y/Y_0
VDD2
VSS
G/Y/Y_1
G/Y/Y_2
G/Y/Y_3
G/Y/Y_4
VDDcore2
VSScore
G/Y/Y_5
G/Y/Y_6
G/Y/Y_7
IN_SEL
TEST
DEV_ADDR1
Table 3.1: FLI2300 pin details
Internal
Voltage
I/O Type
Drive Pull up/
Description
Tolerance
Pulldown
Horizontal sync or reference -CTL1 of Port 1
Input
5v
Vertical sync or reference -CTL1 of Port 1
Input
5v
Odd/Even Field identification -CTL1 of Port 1
Input
5v
Data Clock input -CTL1 of Port 1
Input
5v
Horizontal sync or reference –CTL2 of Port 1
Input
5v
Vertical sync or reference –CTL2 of Port 1
Input
5v
Odd/Even Field identification –CTL2 of Port 1
Input
5v
Power
3.3 V - Power pin for IO
Ground
Ground
Data Clock input –CTL2 of Port 1
Input
5v
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Power
1.8 V - Power pin for core
Ground
Ground
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Port 1 – Digital video input (Blue/Cb/D1)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Red/Cr/CrCb)
Input
5v
Port 1 – Digital video input (Green/Y)
Input
5v
Power
3.3 V - Power pin for IO
Ground
Ground
Port 1 – Digital video input (Green/Y)
Input
5v
Port 1 – Digital video input (Green/Y)
Input
5v
Port 1 – Digital video input (Green/Y)
Input
5v
Port 1 – Digital video input (Green/Y)
Input
5v
Power
1.8 V - Power pin for core
Ground
Ground
Port 1 – Digital video input (Green/Y)
Input
5v
Port 1 – Digital video input (Green/Y)
Input
5v
Port 1 – Digital video input (Green/Y)
Input
5v
Output to select external video mux
Output
5v
8 mA
Connect to Ground
Input
5v
Device address setting 1
Input
5v
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14
FLI2300 Digital Video Converter Data Sheet
Pin
No
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Pin Name
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3
VSS
SDRAM DATA(0)
SDRAM DATA(1)
SDRAM DATA(2)
SDRAM DATA(3)
SDRAM DATA(4)
SDRAM DATA(5)
SDRAM DATA(6)
SDRAM DATA(7)
SDRAM DATA(8)
SDRAM DATA(9)
SDRAM DATA(10)
SDRAM DATA(11)
VDD4
VSS
SDRAM DATA(12)
SDRAM DATA(13)
SDRAM DATA(14)
SDRAM DATA(15)
VDDcore3
VSScore
SDRAM DATA(16)
SDRAM DATA(17)
SDRAM DATA(18)
SDRAM DATA(19)
SDRAM DATA(20)
SDRAM DATA(21)
SDRAM DATA(22)
SDRAM DATA(23)
SDRAM DATA(24)
SDRAM DATA(25)
VDDcore4
VSScore
SDRAM DATA(26)
SDRAM DATA(27)
SDRAM DATA(28)
SDRAM DATA(29)
SDRAM DATA(30)
SDRAM DATA(31)
VDD5
I/O Type
Input
I/O
I/O
Input
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Voltage
Drive
Tolerance
Internal
Pull up/
Pulldown
5v
5v
5v
5v
8 mA
8 mA
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
5v
5v
5v
5v
4 mA
4 mA
4 mA
4 mA
PD
PD
PD
PD
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
5v
5v
5v
5v
5v
5v
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
PD
PD
PD
PD
PD
PD
PU
Description
Device address setting 0
2-wire serial control bus clock
2-wire serial control bus data
Reset
3.3 V – Power pin for IO
Ground
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
3.3 V – Power pin for IO
Ground
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
1.8 V - Power pin for core
Ground
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
1.8 V – Power pin for core
Ground
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
3.3 V – Power pin for IO
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
15
FLI2300 Digital Video Converter Data Sheet
Pin
No
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
Pin Name
VSS
TEST IN
SDRAM ADDR(10)
SDRAM ADDR(9)
SDRAM ADDR(8)
SDRAM ADDR(7)
SDRAM ADDR(6)
VDDcore5
VSScore
SDRAM ADDR(5)
SDRAM ADDR(4)
SDRAM ADDR(3)
SDRAM ADDR(2)
SDRAM ADDR(1)
SDRAM ADDR(0)
SDRAM WEN
SDRAM RASN
SDRAM CASN
SDRAM BA1
SDRAM BA0
SDRAM CSN
SDRAM DQM
SDRAM CLKOUT
VDD6
VSS
SDRAM CLKIN
TEST3
TEST OUT0
TEST OUT1
118 CTLOUT0
Ground
Input
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Output
Power
Ground
Input
Input
Output
Output
Tristate O/P
119 CTLOUT1
Tristate O/P
120 CTLOUT2
Tristate O/P
121 CTLOUT3
Tristate O/P
122 CTLOUT4
123
124
125
126
127
128
129
I/O Type
VDDcore6
VSScore
CLKOUT
B/U/Pb_OUT_0
B/U/Pb_OUT_1
VDD7
VSS
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Voltage
Drive
Tolerance
5V
5v
5v
5v
5v
5v
8 mA
8 mA
8 mA
8 mA
8 mA
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
4 mA
8 mA
12 mA
5v
12 mA
8 mA
5v
8 mA
5v
8 mA
5v
8 mA
5v
8 mA
5v
8 mA
5v
5v
5v
12 mA
8 mA
8 mA
Internal
Pull up/
Pulldown
Description
Ground
Test input-Connect to ground
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
1.8 V – Power pin for core
Ground
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM address bus *
SDRAM write enable *
SDRAM row address select *
SDRAM column address select *
SDRAM bank select 1*
SDRAM bank select 0*
SDRAM CS *
SDRAM DQM *
Clock out to SDRAM *
3.3 V - Power pin for IO
Ground
Trace delayed SDRAM Clock in
Test input – Connect to ground
Test output – leave open
Test output – leave open
Control signal output selectable as HSync1/
CSync/HRef/Monitor coast
Control signal output selectable as
VSync1/CRef/VRef/Film Indicator
Control signal output selectable as Monitor
coast/HRef/VDD_en / HSync2
Control signal output selectable as Film
Indicator/VRef/backlight_en/VSync2
Control signal output selectable as CRef/Field
ID/CSync/Monitor coast
1.8 V - Power pin for core
Ground
Output data rate clock
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
3.3 V – Power pin for IO
Ground
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
16
FLI2300 Digital Video Converter Data Sheet
Pin
No
Pin Name
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
B/U/Pb_OUT_2
B/U/Pb_OUT_3
B/U/Pb_OUT_4
B/U/Pb_OUT_5
B/U/Pb_OUT_6
B/U/Pb_OUT_7
R/V/Pr_OUT_0
R/V/Pr_OUT_1
VDDcore7
VSScore
R/V/Pr_OUT_2
R/V/Pr_OUT_3
R/V/Pr_OUT_4
R/V/Pr_OUT_5
R/V/Pr_OUT_6
R/V/Pr_OUT_7
VDD8
VSS
G/Y/Y_OUT_0
G/Y/Y_OUT_1
G/Y/Y_OUT_2
G/Y/Y_OUT_3
G/Y/Y_OUT_4
G/Y/Y_OUT_5
G/Y/Y_OUT_6
G/Y/Y_OUT_7
OE
PLL_PVDD
PLL_PVSS
AVSS_PLL_BE1
AVDD_PLL_BE1
AVDD_PLL_BE2
AVSS_PLL_BE2
AVSS_PLL_SDI
AVDD_PLL_SDI
AVDD_PLL_FE
AVSS_PLL_FE
DAC_PVSS
DAC_VDD
DAC_VSS
DAC_BOUT
DAC_AVDDB
DAC_AVSSB
DAC_GOUT
DAC_AVDDG
I/O Type
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Input
Power
Ground
Ground
Power
Power
Ground
Ground
Power
Power
Ground
Ground
Power
Ground
Output
Power
Ground
Output
Power
Voltage
Drive
Tolerance
5v
5v
5v
5v
5v
5v
5v
5v
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
5v
5v
5v
5v
5v
5v
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
5v
5v
5v
5v
5v
5v
5v
5v
5v
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
34 mA
34 mA
Internal
Pull up/
Pulldown
Description
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
1.8 V – Power pin for core
Ground
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
3.3 V – Power pin for IO
Ground
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Output data enable for Digital video output
1.8 V – Power pin for PLL pads
Ground for PLL pads
PLL Ground
1.8 V – Power pin for PLL
1.8 V – Power pin for PLL
PLL Ground
PLL Ground
1.8 V – Power pin for PLL
1.8 V – Power pin for PLL
PLL Ground
Ground for DAC pads
1.8 V – Digital power pin for DAC
DAC digital Ground
Analog B/U output
3.3 V – Analog power pin for B channel
Analog Ground for B channel
Analog G/Y output
3.3 V – Analog power pin for G channel
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
17
FLI2300 Digital Video Converter Data Sheet
Pin
No
175
176
177
178
179
180
Pin Name
DAC_AVSSG
DAC_ROUT
DAC_AVDDR
DAC_AVSSR
DAC_COMP
DAC_RSET
181 DAC_VREFOUT
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Note:
DAC_VREFIN
DAC_AVDD
DAC_AVSS
DAC_GR_AVSS
DAC_GR_AVDD
DAC_PVDD
TEST0
TEST1
TEST2
XTAL IN
XTAL OUT
VDD9
VSS
IN_CLK_PORT 2
D1_IN_0
VDDcore8
VSScore
D1_IN_1
D1_IN_2
D1_IN_3
D1_IN_4
D1_IN_5
D1_IN_6
D1_IN_7
FIELD ID_PORT 2
VSYNC_ PORT 2
HSYNC_PORT 2
I/O Type
Voltage
Drive
Tolerance
Ground
Output
Power
Ground
Output
Output
Output
34 mA
Input
Power
Ground
Ground
Power
Power
Input
Input
Input
Input
Output
Power
Ground
Input
Input
Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
5v
5v
5v
5v
5v
4 mA
4 mA
5v
5v
5v
5v
5v
5v
5v
5v
5v
5v
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
Internal
Pull up/
Pulldown
Description
Analog Ground for G channel
Analog R/V output
3.3 V – Analog power pin for R channel
Analog Ground for R channel
Compensation for video DACs
Current setting resistor for video DACs
1.28 V Internally generated voltage reference for
video DACs
External Voltage reference for video DACs
3.3 V – Analog power pin for DAC
Analog Ground for DAC
Ground for DAC Guard ring
3.3 V – Power pin for DAC Guard ring
3.3 V –Power pin for DAC pads
Test pin – connect to ground
Test pin – connect to ground
Test pin – connect to ground
External parallel crystal oscillator
External parallel crystal oscillator
3.3 V - Power pin for IO
Ground
Port 2 - Data Clock input
Port 2 - ITU-R BT656 digital data input
1.8 V – Power pin for core
Ground
Port 2 - ITU-R BT656 digital data input
Port 2 - ITU-R BT656 digital data input
Port 2 - ITU-R BT656 digital data input
Port 2 - ITU-R BT656 digital data input
Port 2 - ITU-R BT656 digital data input
Port 2 - ITU-R BT656 digital data input
Port 2 - ITU-R BT656 digital data input
Port 2 - Odd/Even Field identification
Port 2 - Vertical sync or reference
Port 2 - Horizontal sync or reference
1) * - The connection of these pins depends on the type of external SDRAM used. See Appendix 3
2) For 16/20 bit Y and muxed C output modes see Appendix 2 for pin configuration
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
18
8. Am29LV160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Embedded Algorithms
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Manufactured on 0.23 µm process technology
— Fully compatible with 0.32 µm Am29LV160B device
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycle guarantee
per sector
■ 20-year data retention at 125°C
■ High performance
— Reliable operation for the life of the system
— Access times as fast as 70 ns
■ Ultra low power consumption (typical values at
5 MHz)
■ Package option
— 48-ball FBGA
— 200 nA Automatic Sleep mode current
— 48-pin TSOP
— 200 nA standby mode current
— 44-pin SO
■ CFI (Common Flash Interface) compliant
— 9 mA read current
— 20 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ Compatibility with JEDEC standards
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Pinout and software compatible with singlepower supply Flash
— Supports full chip erase
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
— Provides a software method of detecting program
or erase operation completion
■ Ready/Busy# pin (RY/BY#)
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Unlock Bypass Program Command
— Provides a hardware method of detecting
program or erase cycle completion (not available
on 44-pin SO)
■ Erase Suspend/Erase Resume
— Reduces overall programming time when issuing
multiple program command sequences
■ Top or bottom boot block configurations
available
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
19
Publication# 22358
Rev: B Amendment/+3
Issue Date: November 10, 2000
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV160D
Voltage Range: VCC = 2.7–3.6 V
-70
-90
-120
Max access time, ns (tACC)
70
90
120
Max CE# access time, ns (tCE)
70
90
120
Max OE# access time, ns (tOE)
30
35
50
Speed Option
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A19
Am29LV160D
20
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
Reverse TSOP
21
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
CONNECTION DIAGRAMS
RESET#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SO
WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
FBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
A19
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Special Handling Instructions
Special handling is required for Flash Memory products
in FBGA packages.
A
22
F6
G6
BYTE# DQ15/A-1
H6
VSS
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
PIN CONFIGURATION
A0–A19
LOGIC SYMBOL
= 20 addresses
20
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1
A0–A19
= DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
16 or 8
DQ0–DQ15
(A-1)
BYTE#
= Selects 8-bit or 16-bit mode
CE#
= Chip enable
CE#
OE#
= Output enable
OE#
WE#
= Write enable
RESET#
= Hardware reset pin
RY/BY#
= Ready/Busy output
(N/A SO 044)
WE#
RESET#
BYTE#
VCC
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS
= Device ground
NC
= Pin not connected internally
23
RY/BY#
(N/A SO 044)
HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
8.1 HY57V641620HG
DESCRIPTION
The Hyundai HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3±0.3V power supply Note)
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4, 8 or Full page for Sequential Burst
•
Data mask function by UDQM or LDQM
•
Internal four banks operation
- 1, 2, 4 or 8 for Interleave Burst
•
.
24
Programmable CAS Latency ; 2, 3 Clocks
HY57V641620HG
PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0,BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
LDQM, UDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
25
HY57V641620HG
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
1Mx16 Bank 3
CLK
Row active
Column
Pre
Decoders
UDQM
Y decoders
LDQM
Bank Select
A0
A1
Column Add
Counter
Address
Registers
Address buffers
A11
BA0
BA1
Memory
Cell
Array
Burst
Counter
Mode Registers
CAS Latency
26
Data Out Control
Pipe Line Control
DQ0
I/O Buffer & Logic
Column
Active
1Mx16 Bank 0
Sense AMP & I/O Gate
WE
refresh
1Mx16 Bank 1
X decoders
CAS
1Mx16 Bank 2
X decoders
RAS
State Machine
CS
Row
Pre
Decoders
X decoders
X decoders
CKE
DQ1
DQ14
DQ15
SiI 164 PanelLink Transmitter
Data Sheet
September 2002
General Description
Features
•
•
The SiI 164 transmitter uses PanelLink® Digital
technology to support displays ranging from VGA to
UXGA resolutions (25 - 165Mpps) in a single link
interface.
•
The SiI 164 transmitter has a highly flexible interface
with either a 12-bit mode (½ pixel per clock edge) or
24-bit mode 1 pixel per clock edge input for true color
(16.7 million) support. In 24-bit mode, the SiI 164
supports single or dual edge clocking. In 12-bit mode,
the SiI164 supports dual edge single clocking or
single edge dual clocking. The SiI 164 can be
2
programmed though an I C interface. In addition the
SiI 164 also supports Receiver and Hot Plug
Detection.
PanelLink Digital technology simplifies PC design by
resolving many of the system level issues associated
with high-speed mixed signal design, providing the
system designer with a digital interface solution that is
quicker to market and lower in cost.
•
•
•
•
•
•
•
•
Scaleable Bandwidth: 25 - 165MHz Flexible
Graphics Controller Interface: 12-bit or 24-bit
mode 1 pixel/clock inputs
Flexible Input Clocking: Single clock single
edge (24-bit), Single clock dual edge (12-/24bit), Dual clock single edge (12-bit)
2
I C Slave Programming Interface up to 100kHz
Low Voltage Interface: 3.3V with option for 1.0
to 3.0V Low Voltage Signal Mode
Monitor Detection supported through hot plug
and receiver detection
De-skewing Option varies input clock to input
data timing
Low Power: 3.3V operation (120mA max.) and
Power Down mode (1mA max.)
Cable Distance Support: over 5m with twisted
pair and fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards
compliant with VESA® P&DTM and DFP)
Standard and Pb-free packages (see pg 29)
AGND
TX2+
TX2-
AVCC
TX1+
TX1-
AGND
TX0+
TX0-
AVCC
TXC+
TXC-
AGND
EXT_SWING
PVCC1
PGND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SiI 164 Pin Diagram
16
GND
34
15
BSEL/SCL
DKEN
35
14
DSEL/SDA
D23
36
13
ISEL/RST#
D22
37
12
VCC
D21
38
11
MSEN
D20
39
10
PD#
D19
40
D18
41
D17
42
D16
VCC
33
RESERVED
SiI 164
64-Pin TQFP
(Top View)
61
62
63
64
D2
D1
D0
GND
VCC
60
1
D3
48
59
GND
D4
DE
58
VREF
2
D5
3
47
57
46
D12
IDCK+
D13
56
HSYNC
IDCK-
4
55
45
D6
D14
54
VSYNC
D7
5
53
44
D8
D15
52
CTL3/A3/DK3
D9
6
51
43
D10
CTL2/A2/DK2
50
CTL1/A1/DK1
7
D11
8
49
EDGE/HTPLG
PVCC2
9
Figure 1. Pin Diagram for SiI 164
27
SiI 164 PanelLink Transmitter
Data Sheet
Functional Description
TX2+
TX1+
TX0+
TXC+
MSEN
The SiI 164 is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 24 bits for data Input to
allow for panel support up to UXGA resolution. Figure 2 shows the functional blocks of the chip.
PanelLink
Digital
core
Registers
&
Configuration
Logic Block
VREF
IDCK-
IDCK+
VSYNC
HSYNC
D[23:0]
CTL/A/DK[3:1]
BSEL/SCL
DKEN
PD
EDGE/HTPLG
DSEL/SDA
ISEL/RST
DE
Data Capture
Logic Block
A[3:1]
SCL
I2C
Slave
Machine
SDA
EXT_SWING
Figure 2. Functional Block Diagram
PanelLink TMDS Digital Core
The PanelLink TMDS core encodes video information onto three TMDS differential data lines and the differential
clock. The video data is input by the Data Capture Logic Block, as a 12- or 24-bit bus, using one or two clocks with
one or two edges per clock. An attached monitor may be sensed using the HTPLG pin or internally with Receiver
Sense. This detected state may be output onto the MSEN pin. The device may be powered down using the PD#
pin or with an internal register. The SiI 164 is reset using the ISEL/RST# pin. A resistor tied to the EXT_SWING
pin is used to control the TMDS swing amplitude.
2
I C Interface and Registers
2
2
The SiI 164 uses a slave I C interface, capable of running at 100kHz. The slave I C interface is not 5V tolerant. If
the switching levels from the host are not 3.3V, then a voltage level shifter must be used. See Figure 16 and
Figure 17 on page 24 for a system diagram.
A connected display may be detected using the DVI Hot Plug signal, attached to the HTPLG pin; or with the
Receiver Sense logic internal to the SiI 164. The state of the detection, or an interrupt signal indicating a change of
state, may be sent to the MSEN pin. This is useful to the host controller monitoring the SiI 164.
28
SiI 164 PanelLink Transmitter
Data Sheet
Data Capture Logic
Video data is input to the SiI 164 by way of a 12-bit or 24-bit interface. The functionality of this interface is affected
by several of the configuration register settings, as follows.
•
BSEL selects between 12-bit and 24-bit input bus widths.
•
DSEL selects between single-edge and dual-edge modes for the input clocks.
•
EDGE selects between rising and falling edge on the input clocks.
•
CLK+ and CLK- provide the one or two clocks required for latching the input data bus.
•
The PD# input selects the chip power down mode and allows for disabling of the TMDS outputs.
The ISEL/RST# input resets the HDCP engine and internal registers and is asserted after power up and receipt of
a stable input pixel clock.
29
SiI 164 PanelLink Transmitter
Data Sheet
Electrical Specifications
Absolute Maximum Conditions
Absolute Maximum Conditions are defined as the worst case conditions the part will tolerate without sustaining
damage. Permanent device damage may occur if absolute maximum conditions are exceeded. Proper operation
under these conditions is not guaranteed. Functional operation should be restricted to the conditions described
under Normal Operating Conditions.
Symbol
VCC
VI
VO
TJ
TSTG
Parameter
Supply Voltage 3.3V
Input Voltage
Output Voltage
Junction Temperature (with power applied)
Storage Temperature
Min
-0.3
-0.3
-0.3
Typ
-65
Max
4.0
VCC+ 0.3
VCC+ 0.3
125
150
Units
V
V
V
°C
°C
Normal Operating Conditions
Symbol
VCC
VCCN
TA
Parameter
Supply Voltage
Supply Voltage Noise
Ambient Temperature (with power applied)
θJA
Thermal Resistance (Junction to Ambient)
Min
3.0
Typ
3.3
0
25
1
Max
3.6
100
70
Units
V
mVP-P
64
°C/W
°C
Note
1. Airflow at 0m/s.
Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol
VIH
VIL
VDDQ
VSH
2
VSL
VCINL
VCIPL
IIL
VIH
Parameter
High Swing High-level Input
Voltage
High Swing Low-level Input
Voltage
Low Swing Voltage
Low Swing High-level Input
Voltage
Low Swing Low-level Input
Voltage
1
Input Clamp Voltage
1
Input Clamp Voltage
Input Leakage Current
High Swing High-level Input
Voltage
Conditions
VREF = VCC
Min
1
VDDQ/2 +
300mV
VREF = VDDQ/2
ICL = -18mA
ICL = 18mA
-10
VREF = VCC
Max
Units
V
0.8
V
3.0
V
V
VDDQ/2 –
100mV
GND -0.8
VCC + 0.8
10
V
2.0
VREF = VCC
VREF = VDDQ/2
Typ
2.0
V
V
µA
V
Notes
1. Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions
2. VDDQ defines the maximum voltage level of Low Swing input. It is not an actual input voltage. Chip characterization for
Low Swing operation is performed at 1.5V only. Voltage level of Low Swing input should never exceed absolute
maximum rating.
30
SiI 164 PanelLink Transmitter
Data Sheet
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
VOD
VDOH
IDOS
IPD#
ICCT
Parameter
Differential Voltage Single ended
peak to peak amplitude
Differential High-level Output
1
Voltage
Differential Output Short Circuit
1
Current
2
Power-down Current
Transmitter Supply Current
Conditions
RLOAD = 50Ω, REXT_SWING = 510Ω
Min
510
Typ
550
Max
590
AVCC
VOUT = 0 V
IDCK= 165 MHz, 1-pixel/clock
mode, REXT_SWING = 510Ω,
IVCC = VCC,
3
Worst Case Pattern
Notes
1. Guaranteed by design.
2. Assumes all inputs to the transmitter are not toggling.
3. Black and white checkerboard pattern, each checker is one pixel wide.
31
0.2
85
Units
mV
V
5
µA
1.0
120
mA
mA
SiI 164 PanelLink Transmitter
Data Sheet
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
TCIP
Parameter
IDCK Period, 1-pixel/clock
Conditions
Min
6
FCIP
TCIH
IDCK Frequency, 1-pixel/clock
IDCK High Time at 165MHz
25
2.0
TCIL
IDCK Low Time at 165MHz
2.0
TIJIT
TSIDF
TDDR
Worst Case IDCK Clock Jitter
Data, DE, VSYNC, HSYNC
Setup Time to IDCK falling edge
(Default De-skew Setting)
Data, DE, VSYNC, HSYNC
Hold Time from IDCK falling edge
(Default De-skew Setting)
Data, DE, VSYNC, HSYNC
1
Setup Time to IDCK rising edge
(Default De-skew Setting)
Data, DE, VSYNC, HSYNC
1
Hold Time from IDCK rising edge
(Default De-skew Setting)
Data, DE, VSYNC, HSYNC
1
Setup Time to IDCK falling/rising edge
(Default De-skew Setting)
Data, DE, VSYNC, HSYNC
1
Hold Time from IDCK falling/rising edge
(Default De-skew Setting)
VSYNC, HSYNC Delay from DE falling
1
edge
1
VSYNC, HSYNC Delay to DE rising edge
THDE
DE high time
TLDE
DE low time
THIDF
TSIDR
THIDR
TSID
THID
TDDF
Typ
2,3
Max
40
Units
ns
165
MHz
ns
2
Figure
Figure 3
ns
Figure 3
Figure 3
Single Edge
(DSEL = 0,
EDGE = 0)
1.0
ns
ns
Figure 6
Single Edge
(DSEL = 0,
EDGE = 0)
0.9
ns
Figure 6
Single Edge
(DSEL = 0,
EDGE = 1)
1.0
ns
Figure 6
Single Edge
(DSEL = 0,
EDGE = 1)
0.9
ns
Figure 6
Dual Edge
(DSEL = 1,
BSEL = 0)
0.6
ns
Dual Edge
(DSEL = 1,
BSEL = 0)
1.3
ns
1TCIP
ns
Figure 7
ns
ns
Figure 7
Figure 8
Figure 8
ps
µs
Figure 5
1TCIP
1
8191TCIP
1
128TCIP
TSTEP
TRESET
De-skew step size increment
Duration of RESET signal Low required for
valid Reset
DKEN = 1
260
TI2CDVD
SDA Data Valid Delay from SCL high
3
to low transition
CL = 10pf
CL = 400pf
SHLT
Differential Swing High-to-Low Transition
Time
RLOAD = 50Ω,
REXT_SWING =
510Ω
170
SLHT
Differential Swing Low-to-High Transition
Time
RLOAD = 50Ω,
REXT_SWING =
510Ω
170
10
ns
ns
ns
ps
Figure 9
200
700
2000
230
200
230
ps
Figure 4
Notes
1. Guaranteed by design.
2. Actual jitter tolerance may be higher depending on the frequency of the jitter.
2
2
3. All Standard mode I C (100kHz) timing requirements are guaranteed by design. Fast mode I C (400kHz) timing
requirements are guaranteed at 10pf loading.
32
Figure 4
SiI 164 PanelLink Transmitter
Data Sheet
Input Timing Diagrams
TCIP
TCIH
2.0 V
2.0 V
2.0 V
0.8 V
0.8 V
TCIL
Figure 3. Clock Cycle High/Low Times
SLHT
SHLT
80% VOD
20% VOD
Figure 4. Low Swing Differential Times
VCC
ISEL/RST#
TRESET
Figure 5. ISEL/RST# Minimum Timing
33
SiI 164 PanelLink Transmitter
Data Sheet
50 %
IDCK
50 %
TSIDF
D[23:0], DE,
HSYNC,VSYNC
THIDF
50 %
50 %
TSIDR
THIDR
Figure 6. Input Data Setup/Hold Time to IDCK
DE
DE
0.8 V
0.8 V
TDDF
TDDR
VSYNC, HSYNC,
CTL[3:1]
VSYNC, HSYNC,
CTL[3:1]
0.8 V
0.8 V
Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE
THDE
2.0 V
DE
2.0 V
0.8 V
0.8 V
TLDE
Figure 8. DE High and Low Times
SDA
TI2I2CDVD
SCL
2
Figure 9. I C Data Valid Delay (driving Read Cycle data)
34
SiI 164 PanelLink Transmitter
Data Sheet
Pin Descriptions
Input Pins
Pin Name
Pin # Type Description
D[23:12]
36-47
In
D[11:0]
5055,
58-63
In
IDCK+
IDCK-
57
56
In
In
DE
2
In
HSYNC
VSYNC
CTL1/A1/DK1
CTL2/A2/DK2
CTL3/A3/DK3
4
5
8
7
6
In
In
In
Top half of 24-bit pixel bus.
When BSEL = HIGH,
this bus inputs the top half of the 24-bit pixel bus.
When BSEL = LOW,
these bits are not used to input pixel data. In this mode, the state of D[23:16] is input to the
2
I C register CFG. This allows 8-bits of user configuration data to be read by the graphics
2
2
controller through the I C interface (see I C register definition). When not used D[23:16]
should be tied to ground. D[15:12] are reserved for SiI use only and should be tied to GND.
Bottom half of 24-bit pixel bus / 12-bit pixel bus input.
When BSEL = HIGH,
this bus inputs the bottom half of the 24-bit pixel bus.
When BSEL = LOW,
this bus inputs ½ a pixel (12-bits) at every latch edge (both falling and/or rising) of the clock.
Input Data Clock +. This clock is used for all input modes.
Input Data Clock –. This clock is only used in 12-bit mode when dual edge clocking is turned
off (DSEL = LOW). It is used to provide the ODD latching edges for dual clock single edge.
If BSEL = HIGH or DSEL = HIGH,
this pin is unused and should be tied to GND.
Input Data Enable. This signal qualifies the active data area. DE is always required by the
transmitter and must be high during active display time and low during blanking time.
Horizontal Sync input control Signal
Vertical Sync input control signal.
The use of these multi-function inputs depends on the settings of ISEL/RST# and DKEN.
These inputs are regular high-swing 3.3V CMOS level inputs. These pins contain weak pulldown resistors so that if left unconnected, they will be LOW.
When ISEL/RST# = LOW, DKEN = LOW
General Purpose Input CTL[3:1] pins are active, for backward compatibility. These pins
must be used to send DC signals only during the blanking time.
When ISEL/RST# = LOW, DKEN = HIGH
DK[3:1] are active, these inputs are used to select the De-skewing setting for the input bus.
When ISEL/RST# = HIGH, DKEN = HIGH
2
A[3:1] are active, these bits are used to set the lower 3 bits of the I C device address.
35
SiI 164 PanelLink Transmitter
Data Sheet
Pin Descriptions (cont’d)
Configuration Pins
Pin Name Pin #
Type
MSEN
11
Out
ISEL/RST#
13
In
BSEL/SCL
15
In
DSEL/SDA
14
In/Out
EDGE/
HTPLG
9
In
DKEN
35
In
Description
Monitor Sense. This pin is an open collector output. The behavior of this output depends on
2
whether I C interface active:
2
I C bus inactive (ISEL/RST# = LOW)
HIGH level indicates a powered on receiver is detected at the differential outputs.
A LOW level indicates a powered on receiver is not detected.
2
I C bus is enabled (ISEL/RST# = HIGH)
2
2
The output is programmable through the I C interface (see I C Register Definitions).
An external 5K pull-up resistor to VDDQ is required on this pin.
2
I C Interface Select.
ISEL/RST#=HIGH,
2
I C interface is active.
ISEL/RST#=LOW,
2
I C is inactive and the chip configuration is read from the configuration strapping pins. This pin
2
also acts as an asynchronous reset to the I C interface controller. The reset is active when this
input is held LOW.
2
Note: When the I C interface is active, DKEN must be set HIGH.
2
2
Input bus select / I C clock. This pin is an open collector input. If I C bus is enabled
2
2
(ISEL/RST# = HIGH), then this pin is the I C clock input. If the I C is disabled (ISEL/RST# =
LOW), then this pin selects the input bus width.
Input Bus Select:
HIGH selects 24-bit input mode
LOW selects 12-bit input mode
2
2
Dual edge clock select / I C Data. This pin is an open collector input/output. If I C bus is
2
2
enabled (ISEL/RST# = HIGH), then this pin is the I C data line. If the I C bus is disabled
(ISEL/RST# = LOW), then this pin selects whether single clock dual edge is used.
Dual Edge clock select:
When HIGH, IDCK+ latches input data on both falling and rising clock edges.
When LOW, IDCK+/IDCK- latches input data on only falling or rising clock edges.
In 24-/12-bit mode:
If HIGH (dual edge), IDCK+ is used to latch data on both falling and rising edges.
st
nd
If LOW (single edge), IDCK+ latches 1 half data and IDCK- latches 2 half data.
2
Edge select / Hot Plug input. If the I C bus is enabled (ISEL/RST# = HIGH), then this pin is
TM
®
TM
used to monitor the “Hot Plug” detect signal (Please refer to the DVI or VESA P&D and
DFP standards). This Input is ONLY 3.3V tolerant and has no internal de-bouncer circuit.
2
If I C bus is disabled (ISEL/RST# = LOW), then this pin selects the clock edge that will latch
the data. How the EDGE setting works depends on whether dual or single edge latching is
selected:
Dual Edge Mode (DSEL = HIGH)
EDGE = LOW, the primary edge (first latch edge after DE is asserted) is the falling edge.
EDGE = HIGH, the primary edge (first latch edge after DE is asserted) is the rising edge.
Note: In 24-bit Single Clock Dual Edge mode, EDGE is ignored.
Single Edge Mode (DSEL = LOW)
EDGE = LOW, the falling edge of the clock is used to latch data.
EDGE = HIGH, the rising edge of the clock is used to latch data.
De-skewing enable.
2
I C mode (ISEL/RST# = HIGH)
DKEN pin must be set to HIGH. DK[3:1] pins are ignored and the De-skewing increments are
2
2
selected through the I C interface (see the I C register definitions).
2
Non I C mode (ISEL/RST# = LOW)
DKEN = LOW, then default De-skewing setting is used.
DKEN = HIGH, then DK[3:1] is used as the De-skewing setting. The De-skewing increments
are TSTEP. Please see Data De-skew Feature for an illustration.
36
SiI 164 PanelLink Transmitter
Data Sheet
Pin Descriptions (cont’d)
Input Voltage Reference Pin
Pin Name Pin # Type
VREF
3
Description
Analog In
Input Reference Voltage. Selects the Swing range of the digital inputs, which include only
D[23:0], IDCK+, IDCK-, DE, VSYNC, and HSYNC. Input pins SCL and SDA, RST, BSEL,
DSEL, EDGE and PD# require 3.3V high swing signals and are not changed by the VREF
input.
To set the digital inputs to 3.3V High Voltage Swing, VREF must be set to 3.3V.
To set the digital inputs to Low Voltage Swing, VREF must be set to ½ of VDDQ where
VDDQ is swing level of input signal. Thus for DVO mode(1.5V Low Voltage Swing) VREF
should be set to 0.75V and BSEL=LOW.
Power Management Pins
Pin Name Pin #
PD#
10
Type
Description
Power Down (active LOW). A HIGH level indicates normal operation. A LOW level
indicates Power Down mode. In Power Down mode the Analog core is disabled and Output
2
buffers/pins are tri-stated however the Input buffer/pins and I C Block for read and write are
2
2
active. PD# pin is disabled during I C mode. PD# should be tied low during I C mode.
In
Differential Signal Data Pins
Pin Name
Pin #
Type
TX0+
TX0TX1+
TX1TX2+
TX2TXC+
TXCEXT_SWING
25
24
28
27
31
30
22
21
19
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Description
TMDS Low Voltage Differential Signal input data pairs.
These pins are tri-stated when PD# is pulled low.
TMDS Low Voltage Differential Signal input clock pair.
These pins are tri-stated when PD# is pulled low.
Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor sets the
amplitude of the voltage swing. A smaller resistor value sets a larger voltage swing and
vice versa. For remote display applications a 510Ω resistor is recommended. While for
notebook computers 680Ω is recommended to ensure voltage swing is not overdriven
over a short cable distance.
Reserved Pins
Pin Name
RESERVED
Pin # Type Description
34
In
Must be tied LOW for normal operation.
Power and Ground Pins
Pin Name
Pin #
Type
VCC
GND
AVCC
AGND
PVCC1
PVCC2
PGND
1,12,33
16,48,64
23,29
20,26,32
18
49
17
Power
Ground
Power
Ground
Power
Power
Ground
37
Description
Digital VCC, must be set to 3.3V nominal.
Digital GND.
Analog VCC, must be set to 3.3V nominal.
Analog GND.
Primary PLL Analog VCC, must be set to 3.3V nominal.
Filter PLL Analog VCC, must be set to 3.3V nominal.
PLL Analog GND.
SiI 164 PanelLink Transmitter
Data Sheet
I2C Registers
2
I C Register Mapping
Addr.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Bit 7
0x09
VLOW (RO)
0x0A
0x0B
7
0x0C
Bit 6
RSVD[1:0]
Bit 5
Bit 3
VND_IDL (RO)
VND_IDH (RO)
DEV_IDL (RO)
DEV_IDH (RO)
DEV_REV (RO)
RSVD[7:0]
FRQ_LOW (RO)
FRQ_HIGH (RO)
VEN
HEN
DSEL (RW)
(R/W)
(R/W)
MSEL[2:0] (RW)
TSEL (RW)
DK[3:1] (RW)
SCNT
(RW)
Bit 4
DKEN (RW)
4
CFG[7:0] (RO)
RSVD
Bit 2
Bit 1
Bit 0
BSEL (RW)
EDGE (RW)
PD (RW)
RSEN (RO)
HTPLG
(RO)
MDI (RW)
CTL[3:1] (RW)
PLLF[3:1]
(RW)
RSVD[3:0]
RSVD
PFEN
(RW)
0x0D
RSVD[3:0]
0x0E
RSVD[7:0]
0x0F
RSVD[7:0]
Notes
1. All values are Bit 7(MSB) and Bit 0(LSB).
2. Registers that can be written and read from are listed as (R/W) while registers that can be read only are listed with (RO).
3. Actual jitter tolerance may be higher depending on the frequency of the jitter.
4. Contents of this register are dependent on the status of pins D[23:16].
2
5. After the RESET signal is deasserted in I C mode, only PD and MSEL have a default value or can retain their
programmed value set before the reset. All other registers do not have a default value or retain their value after a reset.
2
As such all required registers other than PD and MSEL must reinitialized in I C mode after being powered up or reset.
6. Registers listed as RSVD are reserved and for Silicon Image, Inc use only.
7. 0x0C is also called the VDJK Register. Default setting for the VDJK register 0x0C is 89h, which is optimum for most
applications.
38
SiI 164 PanelLink Transmitter
Data Sheet
2
I C Register Definitions
Register Name
VND_IDL
VND_IDH
DEV_IDL
DEV_IDH
DEV_REV
FRQ_LOW
FRQ_HIGH
PD
Access
RO
RO
RO
RO
RO
RO
RO
RW
EDGE
RW
BSEL
RW
DSEL
RW
HEN
RW
VEN
RW
MDI
RW
HTPLG
RSEN
RO
RO
TSEL
RW
MSEL[2:0]
RW
VLOW
RO
CTL[3:1]
RW
Description
Vendor ID Low byte (01h)
Vendor ID High byte (00h)
Device ID Low byte (06h)
Device ID High byte (00h)
Device Revision (00h)
Low frequency limit at 1-pixel/clock mode (MHz) (19h)
High frequency limit at 1-pixel/clock mode Max frequency minus 65MHz (MHz) (64h)
Power Down mode (same function as PD# pin)
0 – Power Down (Default after RESET)
1 – Normal operation
Edge Select (same function as EDGE pin)
0 – Input data is falling edge latched (falling edge latched first in dual edge
mode)
1 – Input data is rising edge latched (rising edge latched first in dual edge
mode)
Input Bus Select (same function as BSEL pin)
0 – Input data bus is 12-bits wide
1 – Input data bus is 24-bits wide
Dual Edge Clock Select (same function as DSEL pin)
0 – Input data is single edge latched
1 – Input data is dual edge latched
Horizontal Sync Enable:
0 – HSYNC input is transmitted as fixed LOW
1 – HSYNC input is transmitted as is
Vertical Sync Enable:
0 – VSYNC input is transmitted as fixed LOW
1 – VSYNC input is transmitted as is
Monitor Detect Interrupt
0 – Detection signal has changed logic level (write one to this bit to clear)
1 – Detection signal has not changed state
Hot Plug Detect input, the state of HTPLG pin can be read from this bit
Receiver Sense (only available for use in DC coupled systems)
0 – Active/Powered Receiver not detected
1 – Active/Powered Receiver detected
Interrupt Generation Method
0 – Interrupt bit (MDI) is generated by monitoring RSEN
1 – Interrupt bit (MDI) is generated by monitoring HTPLG
Select source of the MSEN output pin
000 – Force MSEN outputs high (disabled – default after RESET)
001 – Outputs the MDI bit (interrupt)
010 – Output the RSEN bit (receiver detect)
011 – Outputs the HTPLG bit (hot plug detect)
1xx – RESERVED
This bit is a 1 if the VREF setting
1 – Indicates High Swing inputs
0 – Indicates Low Swing inputs
General purpose inputs (same as CTL[3:1] pins)
39
SiI 164 PanelLink Transmitter
Data Sheet
2
I C Register Definitions (cont’d)
Register Name
Access
CFG[7:0]
RO
PFEN
RW
PLLF[3:1]
RW
SCNT
RW
DK[3:1]
RW
DKEN
RW
Description
Contains state of inputs D[23:16]. These pins can be used to provide user selectable
2
configuration data through the I C bus. Only available in 12-bit mode
PLL Filter Enable in the VDJK Register.
1 – To enable PLL Filter (recommended setting)
0 – To disable PLL Filter
Set characteristics of PLL filter in the VDJK register
100 – Recommended value
SYNC Continuous
1 – To enable (recommended setting)
0 – To disable
De-skewing Setting. Increment 260psec.
000 – 1 step -> minimum setup / maximum hold
001 – 2 step
010 – 3 step
011 – 4 step
100 – 5 step -> default (recommended setting)
101 – 6 step
110 – 7 step
111 – 8 step -> maximum setup / minimum hold
Please see Data De-Skew Feature for an illustration
De-skewing Enable through DK[3:1] bits. When DKEN pin is HIGH via pin or set to 1,
then De-skew is enabled. When set to 0 De-skew is disabled. Please see Data Deskew Feature for an illustration.
40
MT1389
8.2 MT1389
Progressive-Scan DVD Player SOC
Specifications are subject to change without notice
MediaTek MT1389 is a DVD player system-on-chip (SOC) which incorporates advanced features like high
quality TV encoder and state-of-art de-interlace processing. The MT1389 enables consumer electronics
manufacturers to build high quality, cost-effective DVD players, portable DVD players or any other home
entertainment audio/video devices.
Based on MediaTek’s world-leading DVD player SOC architecture, the MT1389 is the 3rd generation of the DVD
player SOC. It integrates the MediaTek 2nd generation front-end analog RF amplifier and the Servo/MPEG AV
decoder.
The progressive scan of the MT1389 utilized a proprietary advanced motion-adaptive de-interlace algorithm to
achieve the best movie/video playback. It can easily detect 3:2/2:2 pull down source and restore the correct
original pictures. It also supports a patent-pending edge-preserving algorithm to remove the saw-tooth effect.
Key Features
DVD
PUH
Module
CVBS, Y/C,
Component
MT1389L
Applications
FLASH
Front-panel
Remote
SDPIF
RF/Servo/MPEG Integration
High Performance Audio Processor
Motion-Adaptive, Edge-Preserving De-interlace
108MHz/12-bit, 6 CH TV Encoder
Audio DAC
DRAM
DVD Player System Diagram Using MT1389
41
Standard DVD Players
Portable DVD Players
MT1389
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
General Feature List
Super Integration DVD player single chip
High performance analog RF amplifier
Servo controller and data channel processing
MPEG-1/MPEG-2/JPEG video
Dolby AC-3/DTS/DVD-Audio
Unified memory architecture
Versatile video scaling & quality
enhancement
OSD & Sub-picture
2-D graphic engine
Built-in clock generator
Built-in high quality TV encoder
Built-in progressive video processor
Audio effect post-processor
Audio input port
High Performance Analog RF Amplifier
Programmable fc
Dual automatic laser power control
Defect and blank detection
RF level signal generator
Speed Performance on Servo/Channel Decoding
DVD-ROM up to 4XS
CD-ROM up to 24XS
Channel Data Processor
Digital data slicer for small jitter capability
Built-in high performance data PLL for
channel data demodulation
EFM/EFM+ data demodulation
Enhanced channel data frame sync protection
& DVD-ROM sector sync protection
Servo Control and Spindle Motor Control
Programmable frequency error gain and
phase error gain of spindle PLL to control
spindle motor on CLV and CAV mode
Built-in ADCs and DACs for digital servo
control
Provide 2 general PWM
Tray control can be PWM output or digital
output
Embedded Micro controller
Built-in 8032 micro controller
Built-in internal 373 and 8-bit programmable
lower address port
42
1024-bytes on-chip RAM
Up to 4M bytes FLASH-programming
interface
Supports 5/3.3-Volt. FLASH interface
Supports power-down mode
Supports additional serial port
DVD-ROM/CD-ROM Decoding Logic
High-speed ECC logic capable of correcting
one error per each P-codeword or
Q-codeword
Automatic sector Mode and Form detection
Automatic sector Header verification
Decoder Error Notification Interrupt that
signals various decoder errors
Provide error correction acceleration
Buffer Memory Controller
Supports 16Mb/32Mb/64Mb/128Mb SDRAM
Supports 16-bit SDRAM data bus
Provide the self-refresh mode SDRAM
Block-based sector addressing
Support 3.3 Volt. DRAM Interface
Video Decode
Decodes MPEG1 video and MPEG2 main level,
main profile video (720/480 and 720x576)
Smooth digest view function with I, P and B
picture decoding
Baseline, extended-sequential and
progressive JPEG image decoding
Support CD-G titles
Video/OSD/SPU/HLI Processor
Arbitrary ratio vertical/horizontal scaling of
video, from 0.25X to 256X
65535/256/16/4/2-color bitmap format OSD,
256/16 color RLC format OSD
Automatic scrolling of OSD image
Slide show transition as DVD-Audio
Specification
2-D Graphic Engine
Support decode Text and Bitmap
Support line, rectangle and gradient fill
Support bitblt
Chroma key copy operation
Clip mask
MT1389
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
Audio Effect Processing
Dolby Digital (AC-3)/EX decoding
DTS/DTS-ES decoding
MLP decoding for DVD-Audio
MPEG-1 layer 1/layer 2 audio decoding
MPEG-2 layer1/layer2 2-channel audio
High Definition Compatible Digital (HDCD)
Windows Media Audio (WMA)
Advanced Audio Coding (AAC)
Dolby ProLogic II
Concurrent multi-channel and downmix out
IEC 60958/61937 output
- PCM / bit stream / mute mode
- Custom IEC latency up to 2 frames
Pink noise and white noise generator
Karaoke functions
- Microphone echo
- Microphone tone control
- Vocal mute/vocal assistant
- Key shift up to +/- 8 keys
- Chorus/Flanger/Harmony/Reverb
Channel equalizer
3D surround processing include virtual
surround and speaker separation
43
TV Encoder
Six 108MHz/12bit DACs
Support NTSC, PAL-BDGHINM, PAL-60
Support 525p, 625p progressive TV format
Automatically turn off unconnected channels
Support PC monitor (VGA)
Support Macrovision 7.1 L1, Macrovision
525P and 625P
CGMS-A/WSS
Closed Caption
Progressive Output
Automatic detect film or video source
3:2 pull down source detection
Advanced Motion adaptive de-interlace
Edge Preserving
Minimum external memory requirement
Audio Input
Line-in/SPDIF-in for versatile audio
processing
Outline
256-pin LQFP package
3.3/1.8-Volt. Dual operating voltages
F
E
D
C
B
ASTB
SW1
1
R425
10K
10K
R423
D403
D402
TC404
100UF/10V
10K
R424
C407
104
C408
104
K403
K402
K401
8050
V405
R428
10K
CPU+3.3V
KEY3
KEY2
KEY1
LED
R427
10K
1
2
3
4
D401
1N4148
VFD-35
SEG1
0R(DNS)
R426
FIL-
2
1
2
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
8
7
6
5
GRID6
GRID5
GRID4
GRID3
GRID2
GRID1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
GND
GP0
GP1
GP2
12C508A
vdd
GP5
GP4
GP3
U403
F1
F1
FIL+
35
34
R420 0R
R421
10K
R422
10K
STB
IR
23
24
25
26
27
28
29
30
31
32
33
1K
R441
S9
S10
S11
S12/G1
VEE
S13/G1
S14/G9
S15/G8
S16/G7
G6
G5
LED3
22uF/16V
TC403
R419
10K
SEG9
SEG10
SEG11
SEG12
-25V
SEG13
SEG14
SEG15
SEG16
GRID6
GRID5
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
VCC
22
21
20
19
18
17
16
15
14
13
12
U401
UPD16312
S8
S7
S6
S5
S4
S3
S2
S1
VDD
KEY4
KEY3
G4
G3
G2
G1
VDD
LED4
LED3
LED2
LED1
VSS
OSC
3
8550
V401
R442
330R
VCC
LED
34
35
36
37
38
39
40
41
42
43
44
GRID4
GRID3
GRID2
GRID1
VCC
LED4
LED3
LED2
LED1
GND
PLED1
C401
104
1K
R429
R405
33K
KEY2
KEY1
STB
CLK
VSS
DIN
DO
SW4
SW3
SW2
SW1
11
10
9
8
7
6
5
4
3
2
1
GND
R401
R402
R403
R404
VFDST
33K
33K
33K
33K
V402
8550
R430
330R
1K
1K
1K
1K
1K
R415
100
IR
R412
33K
LED1
CPU+3.3V
TC402
100uF/16V
VCC
R406
R407
R408
R409
R410
R411
R416 33K
10K
VCC
CPU+3.3V
SW1
MSW
SW2
SW3
SW4
F2
F2
1K
R431
1
2
3
C403
101
VFDCK
VFDAT
U402
HS0038A2
R434
330R
R444
330R
8050
R418
10R
R446
330R
1K
R443
V406
FIL+
R445
330R
VCC
C406
101
LED
LED401
V403
8050
R432
330R
VCC
R417
10K
VCC
TC401
100uF/16V
R414
33K
KEY4
KEY3
KEY2
KEY1
R433
330R
104
C405
C404
101
R413
33K
OLED
6G
5G
4G
3G
2G
1G
NC
NC
NC
NC
NC
NC
NC
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
PLED
VFD401
OLED1
4
5
LED4
FIL-25V
GND
VCC
SW1
PLED1
STB
CPU+3.3V
GND
PLED
OLED
OLED1
1
2
3
4
5
6
7
8
9
10
11
12
13
LED2
XS12
XS401
1K
R435
LED402
LED
R437
330R
V404
8050
R436
330R
VCC
IR
GND
VFDST
VFDCK
VFDAT
ASTB
6
1
2
3
1
2
2
LED403
LED
R438
330R
1
2
3
4
5
6
LED404
LED
R439
330R
XS06
XS402
1
2
44
1
2
A
1
LED405
LED
R440
330R
E
D
C
B
A
9. SCHEMATIC & PCB WIRING DIAGRAM
FRONT SCHEMATIC DIAGRAM
FRONT SCHEMATIC DIAGRAM
45
46
F
E
D
C
B
1
!
!
!
D501
1N4007
BCN501
~220V
!
F501
T1.6A/250V
!
L501
D502
1N4007
2
2
R517
R501
680K 2W
BC501
~275V 104
R504
30K
720K/1W
D504
1N4007
TC501
47uF/400V
D503
1N4007
1
2
3
4
ADJ HV
FB
NC
CS VCC
GND DRV
U501
NCP1200
C503
101/1KV
R503
39K/2W
8
7
6
5
C506
102
3
U505
IRFBC20
C505
101
R516
1.5K
TC502
47uF/50V
300
R515
D517
HER105
R505
33ohm
D506
HER105
D505
HER107
C502
103/1KV
3
!
BC503
~400V 221
U502
2501
!
R502
1/1W
C501
101/1KV
L503
FB
EI128/8-2
10
11
7
9
15
12
13
16
6
!
4
3
2
TR501
14
D511
HER105
TC512
47uF/50V
C513
101
D512
HER105
C511
101
C509
101
HER303
22K
R512
L502
10uH/1A
D509
SR303
D510
D508
HER105
C507
101
C514
101
C516
101
D513
HER105
U506
MCR100-6
D518
C518
104
G
K
U503
LM431A
330
R506
A
K
R
R509
10K
IN
C520
104
TC506
1000uF/10V
1
4.7K R510
104
C519
TC511
100uF/16V
5
5.1V
ZD501
3
R518
330
STB
R520
10R/2W
STB
DET
OK
AGND
+9V
-9V
GND
+5V
GND
CPU3.3V
FL+
FL-21V
TC513
100uF/16V
R521
100R
1/4W
100uF/16V
TC508
SA+5V
R511
220R/1W
R514
10K
+5V
+3.3V
CPU+3.3V
C510
104
U504
LM7805
OUT
V502
2N5551
CPU+3.3V
D515
HER203
D516 JUMPER
R508
3.3K
D514
1N4007
TC510
1000uF/10V
TC505
1000uF/10V
R507
1K
C508
104
+9V
1K
R513
C517
104
TC515
470uF/25V
L507 10uH/2A
TC504
470uF/16V
D507
1N4148
C515
104
L506
10uH/2A
HER303
L505
10uH/1A
TC503
470uF/16V
TC509
1000uF/10V
A
4
GND
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
-9V
TC516
47uF/50V
1
2
3
4
5
6
7
8
9
10
11
12
13
+5V
XS13 2.0mm
CN501
ZD502
9.1V/1W
ZD503
3.9V
CPU3.3V
DET
OK
AGND
+9V
-9V
GND
+5V
GND
+3.3V
GND
SA+5V
L508
10uH/1A
CN502
XS13 2.5mm
6
E
D
C
B
A
POWER BOARD SCHEMATIC DIAGRAM
POWER BOARD SCHEMATIC DIAGRAM
47
48
A
B
C
1
2
2
PLED1
1
LED901
R-G LED
2
OLED
LED902
R-G LED
K901
3 1
3
3
6x6x1
2
D
1
OLED1
SW
GND
3
PLED1
STB
CPU+3.3V
GND
PLED
OLED
OLED1
FL+
FL-21V
GND
+5V
SW
STB
DET
OK
AGND
+9V
-9V
GND
+5V
GND
CPU+3.3V
FL+
FL-21V
1
2
3
4
5
6
7
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
XS06
4
XS903
XS06
XS902
XS901
4
5
5
Date:
File:
B
Size
Title
28-Aug-2004
D:\维修手册\DV985S\7969-32.DDB
Number
6
Sheet of
Drawn By:
6
Revision
A
B
C
D
AUX FRONT BOARD SCHEMATIC DIAGRAM
PLED
AUX FRONT BOARDSCHEMATIC DIAGRAM
49
F
E
D
C
B
1
PDAT0
PDAT2
R704
4.7K
VCC
XS28
XS701
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
R712
2.2K
2.2K
R710
330R
+10V
R709
AGND VGND
LFE
+10V
CC
SR
SL
R
VIEDO
PDAT0
L
Pb
Y1
Pr
C
PDAT2
PDAT1
SPDIF
VCC
Y
AGND
V703
8050
R711
1K
A+10V
AGND
V702
8050
R708
33R
A+10V
2
AGND
R713
0R
VGND
C707
105
VGND
C
Y
C719
TC706
TC705
C718
VIEDO
AGND
C716
104
V701
8050
R705
75R
L714 FCM
L713 FCM
104
L711
FBSMT
104
FBSMT
2.2R
3
VGND
220uF R706
220uF/16V
L712
220uF/16V
104
C721
TC701
AGND
VCC
3
VJS3921
2
1
2
6
5
VGND
105
105
VGND
C713
20
18
16
14
12
10
8
6
4
C712
L715 FBSMT
L716 FBSMT
VGND
C715
224
68R
R703
A(B)OUT
A(B)IN
A(A)OUT
A-COM
RETURN
A(A)IN
BLUE I/O
FUNC SW
RETURN
CONT
GREEN I/O
NC
RETURN
RETURN
RED I/O
BLK I/O
RETURN
TRTURN
V-OUT
V-IN
GND
JK706
FBSMT
L710
SPDIF
21
19
17
15
13
11
9
7
5
3
1
C711
104
AGND
JK703B
V-OUT5
VCC
VGND
R707
A+10V
7
2
3
50
4
A
1
GND
VCC
JK703A
S-VIDEO
3
2
JK705
OPTICAL
1
VIN
4
Pr
Pb
SPDIF
Y1
220uF/16V R
C722 104
TC704
C706
102
C705
102
C704
102
C703
102
C702
102
C701
102
FBSMT
L709
FBSMT
L708
FBSMT
L707
R702 100R
220R
R701
G
FB
L706
FB
L705
FB
L704
FB
L703
FB
L702
FB
L701
220uF/16V B
VGND
C717 104
TC703
C710
104
TC702
1000uF/10V
C720 104
R
L
SR
SL
LFE
CC
5
VGND
AGND
12
10
3
11
8
5
2
5
2
RCA-407
6
4
3
1
JK702
9
7
6
4
1
JK701
AV8
RED
BLUE
BLACK
GREEN
RED
WHITE
6
E
D
C
B
A
OUTPUT BOARD SCHEMATIC DIAGRAM
OUTPUT BOARD SCHEMATIC DIAGRAM
51
F
1
DATA2
DATA13
2
DATA15
DATA14
DATA12
D1DATA2
DATA11
D1DATA3
DATA10
D1DATA4
DATA9
D1DATA5
DATA8
D1DATA6
DATA7
DATA6
DATA5
DATA4
DATA3
DATA1
DATA16
100R
DATA17
DATA0
DATA18
100R
100R
DATA19
E
SCL R220
SDA R221
SOFT_RESET
R216
DATA20
10K
DATA21
R218
DATA22
R210
0R
DATA23
D
DATA24
R217
10K
FLI2300
DATA26
Vdd IO 3.3V
D1DATA7
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1(3.3)
VSSio1
IN_CLK2_PORT1
B/Cb/D1_0
B/Cb/D1_1
B/Cb/D1_2
B/Cb/D1_3
B/Cb/D1_4
VDDcore1(1.8)
VSScore
B/Cb/D1_5
B/Cb/D1_6
B/Cb/D1_7
R/Cr/CbCr_0
R/Cr/CbCr_1
R/Cr/CbCr_2
R/Cr/CbCr_3
R/Cr/CbCr_4
R/Cr/CbCr_5
R/Cr/CbCr_6
R/Cr/CbCr_7
G/Y/Y_0
VDD2(3.3)
VSSio2
G/Y/Y_1
G/Y/Y_2
G/Y/Y_3
G/Y/Y_4
VDDcore2(1.8)
VSScore
G/Y/Y_5
G/Y/Y_6
G/Y/Y_7
IN_SEL
TEST
DEV_ADDR1
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3(3.3)
VSSio3
SDRAM D0
SDRAM D1
SDRAM D2
DATA25
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DATA27
U201
DATA28
B
DATA29
100
TC201
10uF/16V
DATA30
R205
DAC 3.3V
DATA31
DCLK
C206
104
GND
3
ADDR10
VDD IO 3.3V
0R
0R
0R
47K
ADDR9
22Rx4
GND
C207
104
104
GND_EARTH
DAC 3.3V
DAC 1.8V
GND_EARTH
GND_EARTH
ADDR8
R206
R207
R208
1
2
3
4
C208
ADDR7
RP202
33pF
C202
ADDR6
8
7
6
5
R211
TC202
22uF/16V
ADDR5
YDATA3
YDATA2
YDATA1
YDATA0
33pF
C201
X201 13.5MHz
R213
0R
ADDR4
A
RP201 22Rx4
1
2
3
4
3
ADDR3
8
7
6
5
R212
187
ADDR2
YDATA7
YDATA6
YDATA5
YDATA4
2
D1DATA0
D1DATA1
OE
G/Y/Y_OUT_7
G/Y/Y_OUT_6
G/Y/Y_OUT_5
G/Y/Y_OUT_4
G/Y/Y_OUT_3
G/Y/Y_OUT_2
G/Y/Y_OUT_1
G/Y/Y_OUT_0
VSSio
VDD8(3.3)
R/Y/Pr_OUT_7
R/Y/Pr_OUT_6
R/Y/Pr_OUT_5
R/Y/Pr_OUT_4
R/Y/Pr_OUT_3
R/Y/Pr_OUT_2
VSScore
VDDcore7(1.8)
R/Y/Pr_OUT_1
R/Y/Pr_OUT_0
B/U/Pb_OUT_7
B/U/Pb_OUT_6
B/U/Pb_OUT_5
B/U/Pb_OUT_4
B/U/Pb_OUT_3
B/U/Pb_OUT_2
VSSio7
VDD7(3.3)
B/U/Pb_OUT_1
B/U/Pb_OUT_0
CLKOUT
VSScore
VDDcore6(1.8)
CTLOUT4
CTLOUT3
CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
TEST3
SDRAM CLKIN
VSSio6
VDD6(3.3)
SDRAM CLKOUT
SDRAM DQM
SDRAM CSN
SDRAM BA0
SDRAM BA1
SDRAM CASN
SDRAM RASN
DATA[0..31]
ADDR[0..10]
0R
0R
0R
PLL1.8V
GND_EARTH
R269
48R
R264
R265
R266
WEN
R214
4.7K
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
RP203
22RX4
R209
OPTION TO MOUNTED
L204
0R
OE
5.6uH
+1.8VD
RFC
L208
C213
104
1
22R
22R
R222
R223
R219
10K
RASN
CASN
BA1
BA0
CSN
DQM
SDRAM_CLK
SDRAM_CLK#
CTL4OUT
22R
R224
1
1
TP205
TP204
SDRAM_CLK
SDRAM_CLK#
CTL1OUT
CTL0OUT
CLKOUT
RP208 22RX4
R225
22R
B/U_OUT[0..7]
5
R227
61
62
63
64
ADDR4
CSN
67
68
20
R228
470
3.3V
100R
19
18
CASN
RASN
17
23
BA1
WEN
22
BA0
59
28
71
16
14
21
30
57
69
70
73
65
ADDR9 66
ADDR10 24
ADDR8
ADDR7
ADDR6
ADDR5
ADDR3
ADDR2
ADDR1
25
26
27
60
C215
1043
ADDR0
C210
104
C229
104
DQM
L210
L211
C214
104
R226
ADDR[0..10]
R/V_OUT[0..7]
G/Y_OUT[0..7]
104
C227
TP203
L201
5.6uH/5%
TC205
2.2uF/25V
+3.3VD
TC204
100uF/16V
100uF/16V
TC203
1
8 G/Y_OUT7
2
7 G/Y_OUT6
3
6 G/Y_OUT5
4
5 G/Y_OUT4
1
8 G/Y_OUT3
2
7 G/Y_OUT2
3
6 G/Y_OUT1
4
5 G/Y_OUT0
RP204
22RX4
RP205 22RX4
1
8 R/V_OUT7
2
7 R/V_OUT6
3
6 R/V_OUT5
4
5 R/V_OUT4
1
8 R/V_OUT3
2
7 R/V_OUT2
3
6 R/V_OUT1
4
5 R/V_OUT0
RP206 22RX4
RP207 22RX4
1
8 B/U_OUT7
2
7 B/U_OUT6
3
6 B/U_OUT5
4
5 B/U_OUT4
1
8 B/U_OUT3
2
7 B/U_OUT2
3
6 B/U_OUT1
4
5 B/U_OUT0
Vdd core 1.8
TC209
10uF/16V
DAC 1.8V
L203
5.6uH
+1.8VD
RFC
L207
+3.3VAR
DAC_ROUT
DAC_GOUT
DAC_BOUT
4
PLL1.8V
GND_FIELD SIGNAL
GND_FIELD SIGNAL
R268
48R
GND
R267
48R
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
HS_PORT2
VS_PORT2
FID_PORT2
D1_IN_7
D1_IN_6
D1_IN_5
D1_IN_4
D1_IN_3
D1_IN_2
D1_IN_1
VSScore
VDDcore8(1.8)
D1_IN_0
IN_CLK_PORT2
VSSio10
VDD9(3.3)
XTAL OUT
XTAL IN
TEST2
TEST1
TEST0
DAC_PVDD(3.3)
DAC_GR_AVDD(3.3)
DAC_GR_AVSS
DAC_AVSS
DAC_AVDD(3.3)
DAC_VREFIN
DAC_VREFOUT
DAC_RSET
DAC_COMP
DAC_AVSSR
DAC_AVDDR(3.3)
DAC_ROUT
DAC_AVSSG
DAC_AVDDG(3.3)
DAC_GOUT
DAC_AVSSB
DAC_AVDDB(3.3)
DAC_BOUT
DAC_VSS
DAC_VDD(1.8)
DAC_PVSS
AVSS_PLL_FE
AVDD_PLL_FE(1.8)
AVDD_PLL_SDI(1.8)
AVSS_PLL_SDI
AVSS_PLL_BE2
AVDD_PLL_BE2(1.8)
AVDD_PLL_BE1(1.8)
AVSS_PLL_BE1
PLL_PVSS
PLL_PVDD(1.8)
SDRAM D3
SDRAM D4
SDRAM D5
SDRAM D6
SDRAM D7
SDRAM D8
SDRAM D9
SDRAM D10
SDRAM D11
VDD4(3.3)
VSSio4
SDRAM D12
SDRAM D13
SDRAM D14
SDRAM D15
VDDcore3(1.8)
VSScore
SDRAM D16
SDRAM D17
SDRAM D18
SDRAM D19
SDRAM D20
SDRAM D21
SDRAM D22
SDRAM D23
SDRAM D24
SDRAM D25
VDDcore4(1.8)
VSScore
SDRAM D26
SDRAM D27
SDRAM D28
SDRAM D29
SDRAM D30
SDRAM D31
VDD5(3.3)
VSSio5
TEST IN
SDRAM ADDR10
SDRAM ADDR9
SDRAM ADDR8
SDRAM ADDR7
SDRAM ADDR6
VDDcore5(1.8)
VSScore
SDRAM ADDR5
SDRAM ADDR4
SDRAM ADDR3
SDRAM ADDR2
SDRAM ADDR1
SDRAM ADDR0
SDRAM WEN
ADDR1
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
ADDR0
CKE
CLK
CS
RAS
CAS
WE
BA1
BA0
DQM3
DQM2
DQM1
DQM0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
A8
A9
A10
A4
A5
A6
A7
A0
A1
A2
A3
U202
C211
104
C231
104
C216
104
1
15
29
43
VDD1
VDD2
VDD3
VDD4
VSS1
VSS2
VSS3
VSS4
86
72
58
44
C237
104
6
C219
104
C239
104
C241
104
Vdd core 1.8
C220
104
104
C203
Vdd IO 3.3V
3.3V
86 PIN TSOP
51
53
54
56
45
47
48
50
37
39
40
42
31
33
34
36
80
82
83
85
74
76
77
79
8
10
11
13
2
4
5
7
MT48LC2M32B2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DATA31
DATA30
DATA29
DATA28
DATA27
DATA26
DATA25
DATA24
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA[0..31]
CLAMP ADAPTOR TO BE USED FOR FLI2300
CHIP.
NO DIRECT SOLDERING OF FLI2300
C235
104
C218
104
MT48LC2M32B2
C212
104
C233
104
C217
104
3
9
35
41
49
55
75
81
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
52
6
12
32
38
46
52
78
84
1
E
D
C
B
A
OUTPUT AUX FRONT BOARDSCHEMATIC DIAGRAM
OUTPUT AUX FRONT BOARD SCHEMATIC DIAGRAM
53
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
D1DATA2
DATA11
D1DATA3
DATA10
D1DATA4
DATA9
D1DATA5
DATA8
D1DATA6
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA18
DATA1
DATA19
DATA0
DATA20
100R
DATA21
100R
100R
DATA22
SCL
R220
SDA
R221
SOFT_RESET
R216
DATA23
10K
DATA24
R218
DATA25
R210
0R
DATA26
R217
10K
FLI2300
DATA27
Vdd IO 3.3V
D1DATA7
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1(3.3)
VSSio1
IN_CLK2_PORT1
B/Cb/D1_0
B/Cb/D1_1
B/Cb/D1_2
B/Cb/D1_3
B/Cb/D1_4
VDDcore1(1.8)
VSScore
B/Cb/D1_5
B/Cb/D1_6
B/Cb/D1_7
R/Cr/CbCr_0
R/Cr/CbCr_1
R/Cr/CbCr_2
R/Cr/CbCr_3
R/Cr/CbCr_4
R/Cr/CbCr_5
R/Cr/CbCr_6
R/Cr/CbCr_7
G/Y/Y_0
VDD2(3.3)
VSSio2
G/Y/Y_1
G/Y/Y_2
G/Y/Y_3
G/Y/Y_4
VDDcore2(1.8)
VSScore
G/Y/Y_5
G/Y/Y_6
G/Y/Y_7
IN_SEL
TEST
DEV_ADDR1
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3(3.3)
VSSio3
SDRAM D0
SDRAM D1
SDRAM D2
DATA28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DATA29
U201
DATA30
100
TC201
10uF/16V
DATA31
R205
DAC 3.3V
C207
104
ADDR10
DCLK
C206
104
GND
33pF
ADDR9
VDD IO 3.3V
0R
0R
0R
47K
R211
GND_EARTH
DAC 3.3V
DAC 1.8V
GND_EARTH
GND_EARTH
ADDR8
R206
R207
R208
GND
33pF
104
ADDR7
22Rx4
1
2
3
4
C208
ADDR6
RP202
TC202
22uF/16V
ADDR5
8
7
6
5
C202
ADDR4
YDATA3
YDATA2
YDATA1
YDATA0
C201
X201 13.5MHz
R213
0R
ADDR3
8
7
6
5
R212
187
ADDR2
YDATA7
YDATA6
YDATA5
YDATA4
D1DATA0
D1DATA1
OE
G/Y/Y_OUT_7
G/Y/Y_OUT_6
G/Y/Y_OUT_5
G/Y/Y_OUT_4
G/Y/Y_OUT_3
G/Y/Y_OUT_2
G/Y/Y_OUT_1
G/Y/Y_OUT_0
VSSio
VDD8(3.3)
R/Y/Pr_OUT_7
R/Y/Pr_OUT_6
R/Y/Pr_OUT_5
R/Y/Pr_OUT_4
R/Y/Pr_OUT_3
R/Y/Pr_OUT_2
VSScore
VDDcore7(1.8)
R/Y/Pr_OUT_1
R/Y/Pr_OUT_0
B/U/Pb_OUT_7
B/U/Pb_OUT_6
B/U/Pb_OUT_5
B/U/Pb_OUT_4
B/U/Pb_OUT_3
B/U/Pb_OUT_2
VSSio7
VDD7(3.3)
B/U/Pb_OUT_1
B/U/Pb_OUT_0
CLKOUT
VSScore
VDDcore6(1.8)
CTLOUT4
CTLOUT3
CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
TEST3
SDRAM CLKIN
VSSio6
VDD6(3.3)
SDRAM CLKOUT
SDRAM DQM
SDRAM CSN
SDRAM BA0
SDRAM BA1
SDRAM CASN
SDRAM RASN
DATA[0..31]
ADDR[0..10]
0R
0R
0R
PLL1.8V
GND_EARTH
R269
48R
R264
R265
R266
WEN
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
R214
4.7K
RP203
22RX4
R209
OPTION TO MOUNTED
L204
0R
OE
5.6uH
+1.8VD
RFC
L208
TC203
C213
104
TP203
104
C227
R219
10K
RASN
CASN
BA1
BA0
CSN
DQM
SDRAM_CLK
1
SDRAM_CLK
SDRAM_CLK#
TP205
R227
23
BA1
1
22
BA0
CTL1OUT
CTL0OUT
22R
22R
R222
R223
SDRAM_CLK#
59
CTL4OUT
22R
R224
67
68
20
R228
470
3.3V
100R
CSN
19
18
CASN
RASN
17
WEN
28
71
16
14
21
30
57
69
70
73
CLKOUT
R226
61
62
63
64
25
26
27
60
C215
104
ADDR8 65
ADDR9 66
ADDR10 24
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
C210
104
C229
104
DQM
L210
L211
C214
104
RP208 22RX4
R225
22R
TP204
B/U_OUT[0..7]
ADDR[0..10]
R/V_OUT[0..7]
G/Y_OUT[0..7]
1
TC205
2.2uF/25V
L201
5.6uH/5%
TC204
100uF/16V
+3.3VD
100uF/16V
1
8 G/Y_OUT7
2
7 G/Y_OUT6
3
6 G/Y_OUT5
4
5 G/Y_OUT4
1
8 G/Y_OUT3
2
7 G/Y_OUT2
3
6 G/Y_OUT1
4
5 G/Y_OUT0
RP204
22RX4
RP205 22RX4
1
8 R/V_OUT7
2
7 R/V_OUT6
3
6 R/V_OUT5
4
5 R/V_OUT4
1
8 R/V_OUT3
2
7 R/V_OUT2
3
6 R/V_OUT1
4
5 R/V_OUT0
RP206 22RX4
RP207 22RX4
1
8 B/U_OUT7
2
7 B/U_OUT6
3
6 B/U_OUT5
4
5 B/U_OUT4
1
8 B/U_OUT3
2
7 B/U_OUT2
3
6 B/U_OUT1
4
5 B/U_OUT0
Vdd core 1.8
TC209
10uF/16V
DAC 1.8V
L203
5.6uH
+1.8VD
RFC
L207
+3.3VAR
DAC_ROUT
DAC_GOUT
DAC_BOUT
PLL1.8V
GND_FIELD SIGNAL
GND_FIELD SIGNAL
R268
48R
GND
R267
48R
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
HS_PORT2
VS_PORT2
FID_PORT2
D1_IN_7
D1_IN_6
D1_IN_5
D1_IN_4
D1_IN_3
D1_IN_2
D1_IN_1
VSScore
VDDcore8(1.8)
D1_IN_0
IN_CLK_PORT2
VSSio10
VDD9(3.3)
XTAL OUT
XTAL IN
TEST2
TEST1
TEST0
DAC_PVDD(3.3)
DAC_GR_AVDD(3.3)
DAC_GR_AVSS
DAC_AVSS
DAC_AVDD(3.3)
DAC_VREFIN
DAC_VREFOUT
DAC_RSET
DAC_COMP
DAC_AVSSR
DAC_AVDDR(3.3)
DAC_ROUT
DAC_AVSSG
DAC_AVDDG(3.3)
DAC_GOUT
DAC_AVSSB
DAC_AVDDB(3.3)
DAC_BOUT
DAC_VSS
DAC_VDD(1.8)
DAC_PVSS
AVSS_PLL_FE
AVDD_PLL_FE(1.8)
AVDD_PLL_SDI(1.8)
AVSS_PLL_SDI
AVSS_PLL_BE2
AVDD_PLL_BE2(1.8)
AVDD_PLL_BE1(1.8)
AVSS_PLL_BE1
PLL_PVSS
PLL_PVDD(1.8)
SDRAM D3
SDRAM D4
SDRAM D5
SDRAM D6
SDRAM D7
SDRAM D8
SDRAM D9
SDRAM D10
SDRAM D11
VDD4(3.3)
VSSio4
SDRAM D12
SDRAM D13
SDRAM D14
SDRAM D15
VDDcore3(1.8)
VSScore
SDRAM D16
SDRAM D17
SDRAM D18
SDRAM D19
SDRAM D20
SDRAM D21
SDRAM D22
SDRAM D23
SDRAM D24
SDRAM D25
VDDcore4(1.8)
VSScore
SDRAM D26
SDRAM D27
SDRAM D28
SDRAM D29
SDRAM D30
SDRAM D31
VDD5(3.3)
VSSio5
TEST IN
SDRAM ADDR10
SDRAM ADDR9
SDRAM ADDR8
SDRAM ADDR7
SDRAM ADDR6
VDDcore5(1.8)
VSScore
SDRAM ADDR5
SDRAM ADDR4
SDRAM ADDR3
SDRAM ADDR2
SDRAM ADDR1
SDRAM ADDR0
SDRAM WEN
ADDR1
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
ADDR0
CKE
CLK
CS
RAS
CAS
WE
BA1
BA0
DQM3
DQM2
DQM1
DQM0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
A8
A9
A10
A4
A5
A6
A7
A0
A1
A2
A3
U202
C211
104
C231
104
C216
104
1
15
29
43
VDD1
VDD2
VDD3
VDD4
VSS1
VSS2
VSS3
VSS4
86
72
58
44
C218
104
C237
104
C219
104
C239
104
C241
104
Vdd core 1.8
C220
104
104
C203
Vdd IO 3.3V
3.3V
86 PIN TSOP
51
53
54
56
45
47
48
50
37
39
40
42
31
33
34
36
80
82
83
85
74
76
77
79
8
10
11
13
2
4
5
7
MT48LC2M32B2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DATA31
DATA30
DATA29
DATA28
DATA27
DATA26
DATA25
DATA24
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA[0..31]
CLAMP ADAPTOR TO BE USED FOR FLI2300
CHIP.
NO DIRECT SOLDERING OF FLI2300
C235
104
MT48LC2M32B2
C212
104
C233
104
C217
104
3
9
35
41
49
55
75
81
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
54
6
12
32
38
46
52
78
84
RP201 22Rx4
1
2
3
4
DVI BOARD SCHEMATIC DIAGRAM
C
B
A
F
E
D
R201
R202
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DAC_BOUT
DAC_GOUT
DAC_ROUT
+5V
XS28
XS202
1
86.6R
R274
86.6R
R272
86.6R
R271
C274
56PF
GND
SCL
SDA
GND_EARTH
C280
56PF
GND_EARTH
C277
56PF
1
2
3
4
L218
1uH
L216
1uH
L214
1uH
+5V
FBSMT
FBSMT
L215
1uH
+5V
TP202
1
L219
1uH
GND_EARTH
C281
180PF
GND_EARTH
C278
180PF
L217
1uH
C276
56PF
R270
86.6R
+5V
+3.3VAR
CLKOUT
VD203
1N4148
VD202
1N4148
R273
86.6R
+5V
VD205
1N4148
VD204
1N4148
R275
86.6R
VD207
1N4148
VD206
1N4148
2
GND_EARTH GND_EARTH
GND_EARTH
C282
56PF
+5V
BOUT#
GOUT#
DAC 3.3V
IDCK+
IDCK-
DE
HSYNC
VSYNC
D16
D17
D18
D19
D20
D21
D22
D23
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
U205
ROUT#
5.6uH
L202
57
56
GND_EARTH GND_EARTH
GND_EARTH
C279
56PF
4
5
43
42
41
40
39
38
37
36
53
52
51
50
47
46
45
44
63
62
61
60
59
58
55
54
CTL4OUT CREF 2
CTL0OUT
CTL1OUT
R/V_OUT7
R/V_OUT6
R/V_OUT5
R/V_OUT4
R/V_OUT3
R/V_OUT2
R/V_OUT1
R/V_OUT0
G/Y_OUT7
G/Y_OUT6
G/Y_OUT5
G/Y_OUT4
G/Y_OUT3
G/Y_OUT2
G/Y_OUT1
G/Y_OUT0
B/U_OUT7
B/U_OUT6
B/U_OUT5
B/U_OUT4
B/U_OUT3
B/U_OUT2
B/U_OUT1
B/U_OUT0
GND_EARTH GND_EARTH
GND_EARTH
100uF/16V
TC218
R/V_OUT[0..7]
G/Y_OUT[0..7]
TP201
B/U_OUT[0..7]
1
C275
180PF
GND_EARTH
XS04
XS201
SCL1
SDA1
FBSMT SOFT_RESET
GND
SCL
FBSMT
SDA
FBSMT
GND
FBSMT
FBSMT
GND
FBSMT YDATA0
FBSMT YDATA1
GND
FBSMT YDATA2
FBSMT YDATA3
GND
FBSMT YDATA4
FBSMT YDATA5
GND
FBSMT YDATA6
FBSMT YDATA7
GND
FBSMT DCLK
GND
FBSMT
GND_EARTH
4.7K
4.7K
L235
L236
L234
L233
L231
L232
L229
L230
L227
L228
L225
L226
L223
L224
L221
L222
L220
1
12
33
VDD
VDD
VDD
VSS
VSS
VSS
47uF/16V
R263
10K
+5V
VIN
L209
SDA11#
SDA1
SCL11#
R262
10K
+5V
10k
6
5
4
3
1
2
3
4
R203
4.7K
1
2
3
XS04
R230
5.1K
SCL1
+5V
GND
+3.3VD
+3.3VAR
TC211
100UF/16V
100uF/16V
TC207
+3.3VAR
L206
L205
C226
104
100R
100R
VIN
TC212
更改 数量 更改单号
设 计
审 核
标准化
批 准
4
签 名
VOUT
U204
LD1086DT18
2
日期
R253
0R
R235
4.7K
R236
4.7K
5
C4
C5
C3
24
23
22
21
20
19
18
17
DVI-I
104
104
板号: 2971A-0
解码&伺服板
104
C266
C230
R259
0R
R258
10K
C228
+3.3VD L213
5.6uH
SDA##
3.3V_TMDS
AHSYNC
AGND
ABLUE
RXC-
RXC+
SHLDC
RX5+
RX5-
SHLD0/5
RX0+
RX0-
JK201
DV971A
104
C265
+1.8VD
R257
0R
R256
10K
3.3V_TMDS
SCL##
TC213
100UF/16V
R255
0R
R254
10K
R252
10K
CTL1#
3.3V_TMDS
CTL2#
10UF/16V
C264
104
3
AGREEN
ARED
HPD
AVSYNC
GND
DDC_DAT
+5V
DDC_CLK
RX3+
RX4+
RX3-
RX4-
SHLD1/3
SHLD2/4
RX1+
RX2+
RX1-
RX2-
5
3.3V_TMDS
GOUT# C2
TC208
100uF/16V
+1.8VD
16
8
15
7
14
6
ROUT# C1
CTL1OUT
USE MIRROR IMAGE ON HOST SIDE
DL4001
VD201
C225
104
TC216
47uF/10V
R260
4.7K
+3.3AVR
C224
104
R234
SDA11#
R243
(DNS)
3904
Q201
R244 R242
(DNS) 10K
R233
+5V
5
SOFT_RESET
13
12
4
11
3
10
2
9
1
SDA
SCL
4
3.3V_TMDS
SCL11#
3.3V_TMDS
R229
510
3.3V_TMDS
11
19
9
13 ISEL#
R245
(DNS)
100R
CTL1# R231
CTL2#
CTL3#
8
7
6
100R
100R
14 SDA## R232
15 SCL## R276
31
30
28
27
25
24
22
21
C255
100nF
R204
4.7K
XS203
U206
NDC7002C
VOUT
2
C223
104
0R
2.2K
MSEN
EXT_SWING
R240
C222
104
ISEL/RST
CTL1
CTL2
CTL3
SDA
SCL
TX2+
TX2-
TX1+
TX1-
TX0+
TX0-
TXC+
TXC-
10k
0R
3.3V_TMDS
EDGE/HTPLG
R241
U203
LD1086DT33
TC215
10UF/16V
C254
100nF
3
C221
104
R239
R238
R237
VOLTAGE CONVERSION
R261
4.7K
+3.3AVR
TC210
100UF/16V
+5V
TC214
10UF/16V
+5V
TMDS TX
3
DKEN
3.3V_TMDS
SIL 170B
TC217
DAC 3.3V
16
48
64
23
29
AVDD
AVDD
20
26
32
AVSS
AVSS
AVSS
18
49
PVDD
PVDD
PVSS
17
27
MH1
35
RES
34
VREF
3
PWRDWN
10
ADJ
1
2
ADJ
55
1
MH2
28
1
104
C268
104
C234
C236
104
C271
104
质量
共 2 张
104
C270
104
C240
104
C245
R249
0R
R248
10K
TC219
100uF/16V
3.3V
104
C247
R251
0R
R250
10K
104
数量
版次：1.0
104
C273
3.3V_TMDS
C272
104
C242
104
C246
CTL3#
3.3V_TMDS
6
广东步步高电子工业有限公司AV厂
比例
第 2 张
104
C269
104
C238
104
BBK
104
C267
104
C232
C244
104
ISEL#
3.3V_TMDS
C243
PLL1.8V
CTL0OUT
BOUT#
6
F
E
D
C
B
A
DVI BOARD SCHEMATIC DIAGRAM
F
E
D
C
B
A
C302
104
R319
150K
R323
1.5K
1
2.2R\1/4W
R326
R325
(TRCLOSE1)
470R
TROPEN
LOAD-
1R
V307
8050
V306
8550
C308
DNS
680K
R317
R320
150K
2200pF
C307
TRSO
V1P4
STBY
20K
151
R313
10K
TC308
47uF/16V
R340
R321
1R
C304
GND TC304
FMSO 47uF/16V
R312
SL+
SLMO_VCC
C305
104
C303
104
C312
104
C311
104
22
23
24
25
26
27
28
VCC
V310
9014-S
ADIN
OPOP+
OPO
VINFFC
VOSL
VINSLVINSL+
CF2
CF1
VINFC
VOFC+
VOFCVO2+
VOSLPGND
PVCC1
VCC
F
B
A
RFO
IOA
D
C
V20
E
MDI1
R327
470R
R324
1.5K
V1P4
SP-
C310
2200pF
V309
8550
0R
V308
8050
R322
680K
R318
U302
BA5954
PREGND
VINLD
CTK2
CTK1
VINTK
BIAS
STBY
IOA
C301
104
100K
AVCC
VOTK+
VOTKVOLD+
VOLDPGND
VNFTK
PVCC2
0R
FBSMT
FBSMT
FBSMT
FBSMT
FBSMT
FBSMT
FBSMT
FBSMT
FBSMT
FBSMT
FBSMT
R303
L312
L314
L316
L317
L318
L319
L320
L321
L322
L323
L324
15
16
17
18
19
20
21
FBSMT
FBSMT
L310
L311
R305
1R
FBSMT
FBSMT
10uH
FBSMT
FBSMT
L304
L305
L306
L307
L308
R304
1R
FBSMT
10uH
L301
L303
V304
2SK3018-S
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V303
2SK3018-S
XS301
24P0.5mm
R310
10K
10K
R311
V305
3904-S
100K
FOSO
V1P4
10K
R339
R315
20K
SPSP+
DMSO
R306
1R
(TRCLOSE1)
TROPEN
(TROPEN1)
TRCLOSE
SP+
SL+
SLLIMIT
2
89V33
TRIN
V18
C2167
104
DV33A
C207
C309
104
C212
330pF
R210
R211
C254
104
C251
104
C247
104
C2174
104
C252
104
C246
104
0R
0R
MDI1
MDI2
TRO
FOO
C248
104
C256
104
C257
104
C249
104
C215
1500pF
3
L202
FB
C258
104
C250
104
USBP
USBM
USBVDD
ADIN
TROUT TDI
TMS
TRIN
TCK
STBY
TRCLOSE TDO
V18
A2
A3
A4
A5
A6
A7
A8
A18
A19
18K
20K
C253
104
DV33
C214
104
C213
330pF
R212
0R
R330 10K
R2165
RFOP
RFON
R228
0R
0R
0R
0R
DNS
1uF
1uF
C240
1uF
FEO
0R TEO
TEZISLV
OPO
104
OPOP+
10K DMO
15K FMO
TROPEN
V2P8
V20
V1P4
R329 10K
C245
104
LOADLOAD+
TROUT
C204
LDO2
LDO1
RFSVDD3
E
F
DMSO R208
FMSO R209
L201
FB
C203
D
1uF
C202
A
1uF
C201
B
C229
104
C238
104
3
C
C206 C205
120p
R201
C
R202
B
R203
A
R204
D
SUBA
SUBB
SUBC
SUBD
RFO
C237
104
C236
104
RFSVDD3
C235
104
RFVDD3
C234
104
ADCVDD3
TC248
47uF/16V
VREFN
PWR#
PCE#
PRD#
TC247
22uF/16V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C239
104
AVDD3
R297
R298
R299
AGND
DVDA
DVDB
DVDC
DVDD
DVDRFIP
DVDRFIN
MA
MB
MC
MD
SA
SB
SC
SD
CDFON
CDFOP
TNI
TPI
MDI1
MDI2
LDO2
LDO1
SVDD3
CSO/RFOP
RFLVL/RFON
SGND
V2REFO
V20
VREFO
FEO
TEO
TEZISLV
OP_OUT
OP_INN
OP_INP
DMO
FMO
TROPENPWM
PWMOUT1/V_ADIN9
TRO
FOO
USB_VSS
USBP
USBM
USB_VDD3
FG/V_ADIN8
TDI/V_ADIN4
TMS/V_ADIN5
TCK/V_ADIN6
TDO/V_ADIN7
DVDD18
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
HIGHA0
IOA18
IOA19
DVSS
APLLCAP
APLLVSS
R223
15K
VREFP
100K
TC202
10uF/16V
(DNS)
R220
5
R219
R218
R217
R216
R215
(DNS)
(DNS)
(DNS)
(DNS)
1K
R227
JITFO C233
YUV3
4
V1P4 C222
C223 20pF
1000pF
YUV1
PLLVDD3
R2166
C211
89V33 104
C210
153pF
V1P4
TRSO
FOSO
C244
104
L236 FB AVDD3
L235
FB
XS302
5P2.0mm
1
2
3
4
5
ADIN
C209
TC204
47uF/16V
C243
104
V1P4
TC205
47uF/16V
C242
104
DV33
C306
151
C230
104
TC206
47uF/16V
C208
DV33 V18
L234
RFV18
FB
L250
FB
L208
FB
L207 FB
C241
104
R307
1R
VCC
R316 20K
L302
FB
LOAD+
TC309
47uF/16V
1
2
3
4
5
6
XS303
XS06
7
6
5
4
3
2
1
14
13
12
11
10
9
8
LDO-AV33
TC303
47uF/16V
V302
2SB1132-S LDO1
R331 0R
DQS0
TC302
47uF/16V
LDO2
V301
2SB1132-S
L205
FB
C231
104
L309
FB
TC211
220uF/16V
RFV33
LDO-AV33
MO_VCC
R302
10R
R301
10R
TC301
220uF/16V
L238
FB
DV33
L206 FB
C228
104
C227
104
C226
104
C225
0.033uF
C224
104 R224
104
C2175
0R
0R
0R
DWR#
DCE#
DRD#
PWR#
A16
A15
A14
A13
A12
A11
2
RFVDD3
VREFN
VREFP
A10
A9
A20
PCE#
A1
PRD#
AVCC
AD0
AD1
AD2
AD3
R309
C221 1uF
ADCVDD3
C220
0.047uF
C219
0.047uF
PLLVDD3
AD4
AD5
AD6
A21
R308
0.47uF
JITFN C218
JITFO
XI
XO
RFV18
MT1389
U201
AD7
A17
A0
29
30
ASPDIF
AMDAT
V18
GND
GND
ACLK
ABCK
ALRCK
89V33
RESET#
V18
MUTE_DAC
ASDAT2
ASDAT1
ASDAT0
VSCK
VSDA
VSTB
SCL
SDA
SCL1
SDA1
RXD
TXD
10K
FS0
FS1
URST#
IR
R314
YUV7
DQM0
DQS0
DQ7
R206
YUV6
YUV5
DQ6
DQ5
R205
YUV4
DQ4
DQ3
R207
YUV2
6
HSYNC#
VSYNC#
R213
1K
0R
VOICE-DET
V18
R287
DMA8
DMA9
DMA11
DCKE
DCLK
DMA7
DMA4
DMA5
DMA6
DQ27
DQ28
DQ29
DQ30
DQ31
DQ26
DQ22
DQ23
DQM2
27MHZ
DQ24
DQ25
DV33
R2164
10K
DQ9
DQ10
DQ11
DQ12
DQ13
RAS#
CAS#
WE#
DQM1
LIMIT
DQ8
BA0
CS#
DMA0
DMA10
BA1
DMA3
DMA2
DMA1
DCLKB
0R
DQ17
DQ18
DQ19
DQ20
DQ21
YUV0
1.8K
TC201
10uF/16V
DQ16
R214
FS
C216
C217
104
89V33
L203
DACVDD3 FB
DV33
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
R262
750K
100pF JITFN
YUV0/CIN
FS
VREF
DACVDDC
RD16
RD17
RD18
RD19
RD20
RD21
DVDD3
RD22
RD23
DQM2
DQM3
RD24
RD25
DVSS
RD26
DVDD18
RD27
RD28
RD29
RD30
RD31/ASDATA5
DVDD3
RA4
RA5
RA6
DVSS
RA7
DVSS
RA8
RA9
RA11
CKE
RCLK
DVDD3
RCLKB
RVREF/V_ADIN3
DVDD18
RA3
RA2
RA1
DVSS
RA0
RA10
BA1
DVSS
BA0
RCS
DVDD3
RAS
CAS
RWE
DQM1
DQS1
RD8
DVSS
RD9
RD10
RD11
DR12
RD13
DQ2
DQ1
DQ0
DQ15
1
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
AVDD3
IREF
RFGC
OSN
OSP
CEQN
CEQP
RFGND
CRTPLP
HRFZC
RFRPAC
RFRPDC
RFVDD3
S_VREFN
S_VREFP
ADCVSS
S_VCM
ADCVDD3
LPFOP
LPFIN
LPFIP
LPFON
PLLVDD3
IDACEXLP
PLLVSS
JITFN
JITFO
XTALI
XTALO
RFVDD18
RFGND18
SPDIF
MC_DATA
DVSS
ASDATA4
DVDD18
ASDATA3
ASDATA2
ASDATA1
ASDATA0
DVSS
ACLK
ABCK
ALRCK
DVDD3
SPBCK/ASDATA5
SPLRCK
SPDATA
SPMCLK
HSYNC/V_ADIN2
YUV7/ASDATA5
VSYNC/V_ADIN1
DVDD3
YUV6/R
YUV5/B
DACVSSA
YUV4/G
DACVDDA
YUV3/CVBS
DACVSSB
YUV2/C
DACVDDB
YUV1/Y
DACVSSC
APLLVDD3
IOWR
A16
HIGHA7
HIGHA6
HIGHA5
HIGHA4
HIGHA3
DVDD3
HIGHA2
HIGHA1
IOA20
IOCS
IOA1
IOOE
DVDD3
AD0
AD1
AD2
AD3
DVSS
AD4
AD5
AD6
IOA21/V_ADIN0
ALE
AD7
A17
IOA0
DVSS
UWR
URD
DVDD18
UP1_2
UP1_3
UP1_4
UP1_5
UP1_6
UP1_7
UP3_0
UP3_1
UP3_4
UP3_5
DVDD3
ICE
PRST
IR
INT0
DQM0
DQS0
RD7
DVSS
RD6
RD5
DVSS
RD4
RD3
DVDD18
RD2
RD1
RD0
RD15
DVDD3
RD14
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DQ14
56
2
1
F
E
D
C
B
A
MIAN SCHEMATIC DIAGRAM
F
E
D
R233
VIDEO_U
VIDEO_Y1
VIDEO_V
AGND
+9V
1
0R
R237
R236
0R(DNS)
VGND AGND
LFE
Cc
SR
1
2
75R 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
-9V
SDA
SCL
VGND
YUV0
YUV1
YUV2
YUV3
YUV4
YUV5
YUV6
YUV7
16
14
15
13
32
33
27
28
30
31
12
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
27MHZ 29
RESET# 34
FIELD/CB
VREF
VDD
VDD
VDD
VDD
RED
C
Y
CVBS
VSYNC
RD
GREEN
WR
TTXDAT BLUE
TTXRQ
INT
ISET
PADDR
2
GNDA
GNDA
XTALOUT GNDA
XTALIN GNDA
TEST
SDA
SCL
C271
C2171
104
DQM0
DQM1
DCS#
DRAS#
DCAS#
DWE#
18
35
42
45
37
43
VGND VGND
Y6
39
Y5
Y4
Y2
47
40
Y1
48
R277
3.9K±1%
10R VSYNC#
Y3
R275
11
10R HSYNC#
XI
44
R272
C297
104
C272
104
DV33A
104
C2163
104
6
12
46
52
3
9
43
49
1
14
27
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
3
C2168
104
XS28
XS205
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
C2158
27pF(DNS)
L268
L267
L264
L265
L266
L262
L263
L260
L261
L258
L259
L256
L257
L254
L255
L252
L253
L251
C255
104
3
TO DVI CONNECTOR
C232
104
AVCCV
1
FB
FB
FB
FB
FB
FB
FB
SCL1
SDA1
VCC
27MHZ
YUV6
YUV7
YUV4
YUV5
YUV2
YUV3
FB
FB
FB
FB
YUV0
YUV1
HSYNC#
VSYNC#
FB
FB
FB
FB
SCL
SDA
V18
TC239
47uF/16V
0R(DNS)
R253
R252
10K
TC217
100uF/16V
Q204
9016
VD201
1N4148
C2161
104
0R
R251
C273
104
L228
FB
C279
104
GND
A0
AD7
AD14
AD6
AD13
AD5
AD12
AD4
VD
AD11
AD3
AD10
AD2
AD9
AD1
AD8
AD0
DRD#
GND
DCE#
A1
A17
11
1N4004
VD203
0R
L204
R255
HCU04
U205C
HCU04
TC237
FB(DNS)
47uF/16V
6
VD
12
DV33
5
0R(DNS)
R2159
URST#
R256
33R
VCC
DV33
13
U209
LM1117MP-1.8(DNS)
U205F
R250
0R(DNS)
R243
1.2K
R242
3.3K
1N4004
VD202
C278
102
5
HCU04
R254
1K
10
U205E
TC209
220uF/16V
8M_FLASH(TSOP)
48
A15
A16
47
A14
BYTE
46
A13
Vss
45
A12
DQ15/A-1
44
A11
DQ7
43
A10
DQ14
42
A9
DQ6
41
A8
DQ13
40
A19
DQ5
39
NC
DQ12
38
WE
DQ4
37
RESET
Vcc
36
NC
DQ11
35
NC
DQ3
34
RY/BY
DQ10
33
A18
DQ2
32
A17
DQ9
31
A7
DQ1
30
A6
DQ8
29
A5
DQ0
28
A4
OE
27
A3
Vss
26
A2
CE
25
A1
A0
4
U214
DV33
2 A5VV
IEC958
C277
10pF(DNS)
27MHZ
XI
XTALI
TC245
C282 220uF/16V
104
FB
0R(DNS)
R222
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TC249
47uF/16V
AVCCV
A19
A18
A8
A7
A6
A5
A4
A3
A2
A16
A15
A14
A13
A12
A11
A10
A9
AA20
AA21
DWR#
URST#
VP
UPA[20..0]
UPD[15..0]
R249
10R(DNS)
L269
RESET#
C281
104
FB
FB
FB
C280
104
C276
27pF
0R
L249
2.7uH(DNS)
XO
4
U205B
HCU04
C274
104
DV33
R247
0R(DNS)
3
TC210
47uF/16V
FB
L217
AVCC
R241
4.7K(DNS)
0R
2
VD
R248
C275 X201
27pF 27MHz
R245
0R(DNS)
R246 100K
U205A
HCU04
C2164
104
1
C2166
104
SD33
SD33
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
R244
TC213
220uF/16V
VSSQ
VSSQ
VSSQ
VSSQ
VCCQ
VCCQ
VCCQ
VCCQ
VCC
VCC
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
C2169
SDRAM 64M
VSS
VSS
VSS
NC
NC
DQML
DQMH
/CS
/RAS
/CAS
/WE
CLK
CKE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
BA0/A13
BA1/A12
U211
C2170
104
SD33
54
41
28
36
40
15
39
19
18
17
16
AVCCVAVCCV
10
9
38
17
36
41
46
23
24
25
26
29
30
31
32
33
34
22
35
20
21
SDCLK 38
SDCKE 37
DV33
L227
FB
33R
33R
33R
33R
33R
33R
104
TC208
TC207
220uF/16V
220uF/16V
FB
VCC
HSYNC/CB
PDAT0
PDAT1
PDAT2
PDAT3
PDAT4
PDAT5
PDAT6
PDAT7
V0
V1
V2
V3
V4
V5
V6
V7
CLOCK
RESET
U206
CS4955
104
104
VCC
L226
C270
DV33
OR
AVCC
R265
R266
R267
R2162
0R
CS#
RAS#
CAS#
WE#
DMA11
R231
33R
DCLK R263
DCKE R264
C269
+9V
R271
R221
C261
102(DNS)
R260
680R
GND
AVCC
MUTE_DAC C268
MUTEA
104
XS28
XS204
FB
FB
1K
FB
L209
ASTB L224
L225
U208
BA033FP(DNS)
VSTB
VSCK
VSDA
FS0
FBSMT VOICE-DET
FBSMT OKA
GND
FB
FB
C266
47pF
FB
HSYNC#
VSYNC#
IEC958
VCC
VIDEO_Y
VIDEO_C
IR#
IR
R230
4.7K
C260
102(DNS)
SCL
SDA
FBSMT
FBSMT
FBSMT
FBSMT
DV33
C265
47pF
GND
R229
0R
8
7
6
5
L223
L222
L220
L221
L218
L219
C264
47pF
VCC
XS13
XS203
1
2
3
4
5
6
7
8
9
10
11
12
13
C263
47pF
L230
L231
L232
L233
L229
FBSMT
C262
47pF
DC/NC
VCC
RST_/NC RST/WP
WP/RST_
SCL
VSS
SDA
VIDEO_COMP
R234
Lt
0R(DNS)
AGND
Rt
R235
0R
SL
FS1
B
C
XS201
7
6
5
4
3
2
1
XS07
1
2
3
4
A
R259
680R
2 BA1
1
C259
104
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
R232 DMA8
33R DMA9
DMA10
MA11
BA0
#BA1
4.7K
4.7K
R238
R239
2
4.7K
R240
DV33
0R
A21
A20
0R(DNS)
0R(DNS)
R258
R257
R2140
U202
AT24C16X4050
IN
GND
OUT
57
1
2
3
14
7
GND
OUT
IN
1
2
3
1
Y6
Y5
Y4
Y1
Y2
Y3
ASPDIF
VGND
R280
150R
VGND
150R
R276
VGND
R273
150R
R270
150R
VGND
R274
150R
C2150
104
0R
L248
C2104 0R
47pF
L247
C2101 0R
47pF
C298
47pF
L246
L245
C295 0R
47pF
L244
C292 0R
47pF
L243
C289 0R
47pF
C2151
104
VGND
R261
150R
VGND
C2152
104
A5VV
L213
1.8uH
C2105
101
L215
1.8uH
C2102
101
L214
1.8uH
C299
101
VGND
L212
1.8uH
C296
101
C293
101
L211
1.8uH
C290
101
L210
1.8uH
TC203
10uF/16V
6
VGND
Q225
3906
R2172
150R
A5VV
VGND
Q224
3906
R2171
150R
A5VV
Q223
3906
R2170
150R
A5VV
Q222
3906
VIDEO_Y
VIDEO_C
VIDEO_V
VIDEO_U
VGND
VIDEO_Y1
VGND
VIDEO_COMP
R2169
150R
A5VV
VGND
Q221
3906
R2168
150R
A5VV
VGND
Q220
3906
R2167
150R
A5VV
E
D
C
B
A
MIAN SCHEMATIC DIAGRAM
F
E
D
C
B
C2138
104
C284
104
R288
4.7K
DV33
1
C2142
104
C2139
104
DV33
C287
104
C2143
104
C2140
104
R281
R284
R286
R283
R285
R2173
TC244
10uF/16V
SLRCK
SACLK
SBCLK
AMDAT
R289
47K
C2141
104
AGND
-9V
AGND
+9V
1
2
3
4
XS04(DNS)
XS202
1
2
3
4
5
6
7
8
R268
0R(DNS)
R269
0R(DNS)
DV33
Cc
LFE
SL
AGND
SR
Lt
Rt
DV33
RXD
TXD
GND
USBP
USBM
VCC
R278
0R(DNS)
R279
0R(DNS)
CS5333(16)
VL
MCLK
SCLK
SDATA
VA
GND
LRCK
DIN
U210
0R
0R
0R
0R
0R
0R
RST
VQ
AINL
AINR
REF_G
FILT+
TST
DIF
R2116
100K
R2115
100K
R2114
100K
R2113
100K
R2112
100K
R2111
100K
16
15
14
13
12
11
10
9
AGND
AGND
C267
104
1K
1K
R2126
1K
R2125
R2124
1K
R2123
1K
105
C286
2
TC243
1uF/16V
105
C285
TC242
1uF/16V
R2128
1K
Q210
2SC1815-YS
R2127
1K
Q209
2SC1815-YS
Q208
2SC1815-YS
Q207
2SC1815-YS
1K
R2122
R2121
1K
Q206
2SC1815-YS R2120
1K
R2119
1K
1K
Q205
2SC1815-YS
R2118
R2117
C288
102
150R
R2180
CH-R
OKA
RESET#
CH-C
CH-SW
CH-SL
ACLK
ABCK
ALRCK
ASDAT0
ASDAT1
ASDAT2
10uF/16V
TC224
10uF/16V
TC223
10uF/16V
TC222
10uF/16V
TC221
10uF/16V
TC241
MUTE-1
CH-SR
CH-L
10uF/16V
TC240
3
R291
R292
R293
R294
R295
R296
7
33R
33R
33R
33R
33R
33R
1
7
-9V
+9V
C2117
R2137
-9V
3
2
101
6
4580
U221B
5
6
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
AGND
C2127
102
R2151
R2150
AGND
C2124
102
R2147
4.7K
AGND
C2121
102
R2143
R2142
AGND
C2118
102
R2139
R2138
AGND
C2115
102
R2135
R2134
AGND
R2146
R2149
20K
C2126
101
3
U221A
4580
2
C2123 101
R2145 20K
5
U220B
4580
101
R2141 20K
U220A
4580
3
2
4.7K
4.7K
C2112
102
R2131
R2130
20K
U219B
4580
5
6
101
20K
U219A
4580
C2120
SACLK
SBCLK
SLRCK
SDATA0
SDATA1
SDATA2
-9V
+9V
-9V
+9V
-9V
+9V
1
7
+9V
C2114
-9V
R2133
1
101
20K
C2111
+9V
R2129
8
4
8
4
8
4
A
3
8
4
8
4
2
8
58
4
1
C2136
122
R2155 6.8K
C2135
122
R2154 6.8K
C2133
122
0R
C2128
MUTE3
MUTE2
MUTE1
C2131
0R
L
R
SW
VD209
1N4148
VD208
1N4148
VD207
1N4148
/C
SL#
C2137
683(DNS)
C2119
0R
R2102
1K
R2101
1K
SR#
RESET#
SCL
SDA
SDATA0
SDATA1
SDATA2
SBCLK
SLRCK
SACLK
R282
0R
VCC
R2105
-9V 330R
Q211
1015
R2104
1K
R2103
+9V 1K
TC238
2.2uF/16V(DNS)
TC230
10uF/16V
TC229
10uF/16V
TC228
10uF/16V
CS4360
VLS
SDIN1
SDIN2
SDIN3
SCLK
LRCK
MCLK
VD
GND
RST
SCL
SDA
CS
VLC
U207
MUTEA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10uF/16V
TC227
10uF/16V
TC226
5
10uF/16V
C2154
104
DV33
TC225
TC231
10uF/16V
0R
0R(DNS)
C2153
104
R226
R225
C2132
683(DNS)
AVCC
OKA
C2116
102
AGND
C2134
683(DNS)
R2153 6.8K
C2130
122
R2152 6.8K
C2129
122
R2148 6.8K
20K
R2156
C2122
122
R2136 6.8K
20K
R2132
4
R2106
10K
AGND
AGND
C#
TC234
47uF/16V
AGND
Q218
1015
0R
R2108
10K
TC232
10uF/16V
TC233
10uF/16V
Q219
1015
MUTE-1
VOICE-DET
C2157
104
C2156
104
C#
LFE#
MUTE3
MUTE1
LL
RR
MUTE2
LS
RS
VD205
1N4148
LFE#
LS
RS
LL
RR
R2107
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Q212
2SC1815-Y
MUTEC1
AOUTA1
AOUTB1
MUTEC2
AOUTA2
AOUTB2
VA
GND
AOUTA3
AOUTB3
MUTEC3
VQ
FILT+
M2
R2109
150R
AGND
TC236
10uF/16V
AVCC
C2155
104
6
+9V
TC235
220uF/16V
VD206
1N4148
E
D
C
B
A
MIAN SCHEMATIC DIAGRAM
MIAN SCHEMATIC DIAGRAM
59
10. SPARE PARTS LIST
DV985S MATERIAL LIST
1. POWER BOARD
NO
MATERIAL
18
19
20
CARBON FILM RESISTOR
CARBON FILM RESISTOR
CARBON FILM RESISTOR
CARBON FILM RESISTOR
METAL FILM RESISTOR
METAL FILM RESISTOR
METAL OXIDE FILM
RESISTOR
CARBON FILM RESISTOR
CARBON FILM RESISTOR
CARBON FILM RESISTOR
CARBON FILM RESISTOR
METAL OXIDE FILM
RESISTOR
METAL OXIDE FILM
RESISTOR
HIGH VOTAGE RESISTOR
CARBON FILM RESISTOR
METAL OXIDE FILM
RESISTOR
MAGNETIC BEAD
INDUCTOR
PORCELAIN CAPACITOR
PORCELAIN CAPACITOR
TERYLENE CAPACITOR
21
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SPECIFICATIONS/PART NUMBER QUANTITY
LOCATION
1/4W1.5K±5%SHAPED10
1/4W100Ω±5%
1/4W330Ω±5%SHAPED10
1/4W1K±5%SHAPED10
1/4W2.7K±1%SHAPED10
1/4W10K±1%
1
1
1
2
1
2
R516
R521
R506
R507,R513
R509
R508,R518
1W1Ω±5%FLAT SHAPED15×7
1
R502
1/4W30K±5% SHAPED10
1/4W10K±5% SHAPED10
1/4W4.7K±5% SHAPED10
1/4W22K±5% SHAPED10
1
1
1
1
R504
R514
R510
R512
1W 220Ω±5％ R-SHAPED15×8
1
R511
2W68K±5% FLAT SHAPED15×7
1
R503
1/2W680K±5%
1/4W300Ω±5% SHAPED10
1W720K±5% FLAT SHAPED15×
7
1
1
R501
R515
1
R517
RH354708
1
L503
50V 100P ±10% 5mm
1000V 103 +80%-20% 7.5mm
100V 102 ±5% 3.5mm
5
1
1
PORCELAIN CAPACITOR
50V 104 ±20% 5mm
7
PORCELAIN CAPACITOR
PORCELAIN CAPACITOR
CERAMIC CAPACITOR
CERAMIC CAPACITOR
TERYLENE CAPACITOR
TERYLENE CAPACITOR
CD
CD
CD
CD
CD
CD
CHOKE COIL
CHOKE COIL
1000V 101 +80%-20% 7.5mm
1000V 101 ±10% 7.5mm
CT81 250VAC221±20% 10mm
CT81 250VAC221±10% 10mm
275V 104 ±20% 15mm
275V 104 ±10% 15mm
CD11T 16V100u±20%6×12 2.5
CD11T 25V470u±20%10×16 5
CD11T 50V22U±20%5×11 2
CD11T 50V47u±20%6×12 2.5
CD11T 10V1000u±20%8×16 3.5
CD294 400V47U±20%22×25 10
VERTICAL 10UH 1A 5mm
VERTICAL 10UH 2A 5mm
3
3
1
1
1
1
3
2
2
2
4
1
2
2
C507,C509,C511,C513,C514
C502
C506
C508,C510,C517,C515,C518,C51
9,C520
C516,C503,C501
C516,C503,C501
BC503
BC503
BC501
BC501
TC508,TC511,TC513
TC503,TC504
TC502,TC516
TC512,TC515
TC505,TC506,TC509,TC510
TC501
L502,L505
L506,L507
SWITCHING POWER
TRANSFORMER
BCK-28-0272
1
T501
SR160
HER105
Φ0.6 SHAPED12.5mm
HER303
HER107
1
4
2
2
1
D514
D508,D511,D512,D513
D510,JP505
D518,D509
D505
5.1V 1/2W
1
ZD501
9.1V 1W
1
ZD502
SCOTTKEY
DIODE
CONNECTION CORDS
DIODE
DIODE
VOTAGE REGULATOR
DIODE
VOTAGE REGULATOR
DIODE
60
41
DIODE
1N4148
2
D507,D517
42
VOTAGE REGULATOR
DIODE
3.3V 1/2W
1
ZD503
43
DIODE
1N4007
4
D501~D504
44
45
46
2N5551
NCP1200P60 DIP
P4NC60 SEALED TO-220
SSS4N60B TO-220
TLV431 TO-92
UT-20 40mH ±20% 10×13
1
1
1
1
1
1
V502
U501
U505
U505
U503
L501
HS817
1
U502
51
52
53
54
55
56
TRIODE
IC
IC
IC
IC
POWER GRID FILTER
PHOTOELECTRIC
COUPLER
CONTROLABLE SILICON
CONTROLABLE SILICON
SOCKET
SOCKET
CONNECTION CORDS
CONNECTION CORDS
SCHOTTKEY
CONNECTION CORDS
MCR100-6
NCR169D TO-92
13P 2.5mm
2 P 8.0mm 2#
Φ0.6 SHAPED5mm
Φ0.6 SHAPED10mm
SR360
Φ0.6 SHAPED7.5mm
1
1
1
1
3
5
1
2
57
HEAR RADIATION BOARD
11×15×25 WHITEAB905
2
58
TAPPING SCREW
BT 3×8 BLACK
2
59
60
61
62
63
FUSE
FUSE HOLDER
POWER GROUND PIECE
IC
PCB
T1.6AL 250V
BLX-2
AB903
LM7805 SEALEDTO-220
5967G-0
1
1
1
1
1
U506
U506
CN502
BCN501
JP502,JP506,JP508
JP501,JP503,JP504,JP510,D516
D515
JP507,JP511
FIXED HEAT RADIATION
BOARD
U504,U505 FOR HEAR
RADIATION
F501
FOR F501
G503
U504
64
SOCKET
13P 2.0mm
1
47
48
49
50
CN501
2.MAIN BOARD
NO
MATERIAL
SPECIFICATIONS/PART NUMBER QUANTITY
LOCATION
1
SPONGE SOFT SPACER
15×7×3.5 BOUBLE FACED
HARD
2
2
VFD SPONGE
10×10×6
1
4
5
1N4148
D16312GB QFP
PT6312LQ QFP
HNV 06SC22 BLUE SCREEN
VFD16-0604
HNV 06SC22
2
1
1
1
1
1
HERIZONTAL6×6×1
3
K401～K403
8
SMD DIODE
IC
IC
VFD
VFD
VFD
LIGHT TOUCH RESTORE
SWITCH
IR SENSOR
CONNECT IR SENSOR WITH
PCB
D401,D402
U401
U401
VFD401
VFD401
VFD401
HS0038B3V
1
U402
9
SMD RESISTOR
1/16W 0Ω ±5%
2
R420,R421
10
HEAT SHRINK TUBE
ф0.8
11
SMD RESISTOR
1/16W 10Ω ±5%
3
R418,R433,R434
12
CARBON FILM RESISTOR
1/6W75Ω±5%SHAPED7.5
1
R432
13
CARBON FILM RESISTOR
1/6W220Ω±5%SHAPED7.5
1
R436
6
7
CONNECT VFD WITH PCB
0.008
61
14
SMD RESISTOR
1/16W 100Ω ±5%
5
15
SMD RESISTOR
1/16W 10K ±5%
6
16
17
18
SMD RESISTOR
SMD RESISTOR
SMD RESISTOR
1/16W 33K ±5%
1/16W 51K ±5%
1/16W 330Ω ±5%
8
1
2
19
SMD RESISTOR
1/16W 1K ±5%
9
20
21
22
23
24
25
26
27
SMD LIGHTING DIODE
LIGHTING DIODE
CD
SMD CAPACITOR
CD
SMD TRIODE
SMD TRIODE
PCB
2
2
1
4
3
2
2
1
28
CORD ARRAY
29
SOFT CORD ARRAY
LTST-C930TBKT
3B3HC
CD11C 16V22U±20%4×7 1.5
50V 104 +80%-20% 0603
CD11C 16V33U±20%5×7 2
8050D
8550D
4971-0
6-7P130 2.0 2WITH NEEDLE
AND THE SAME DIRECTION
6CORDS
12-6/6P 230×2 2.0 T3 WITH
NEEDLE AND THE SAME
DIRECTION
30
SOFTWARE PROGRAM
EPROM
ROM969S-0A(53S）
1
R415,R437,R438,R439,R440
R416,R417,R419,R422,R427,R42
8
R401~R404,R411~R414
R405
R430,R442
R406~R410,R429,R431,R435,R44
1
LED04,LED05
LED402,LED403
TC403
C401,C405,C407,C408
TC401,TC402,TC404
V403,V404
V401,V402
1
XS402
1
XS401
3.OUTPUT BOARD
NO
MATERIAL
SPECIFICATIONS/PART NUMBER QUANTITY
LOCATION
1
SMD RESISTOR
1/16W 100Ω ±5%
1
R702
2
3
CARBON FILM RESISTOR
SMD RESISTOR
1/4W68Ω±5%
1/16W 2.2Ω ±5%
1
1
R703
R706
4
CARBON FILM RESISTOR
1/4W220Ω±5%
1
R701
5
SMD CAPACITOR
50V 102 ±10% 0603
6
C701~C706
6
SMD CAPACITOR
SMD CAPACITOR
SMD CAPACITOR
SMD CAPACITOR
SMD CAPACITOR
SMD CAPACITOR
MAGNETIC BEADS
INDUCTOR
25V 104 +80%-20% 0805
50V 104 +80%-20% 0805
50V104 ±20% 0603
50V 224 +80-20% 0805
25V 224 +80%-20% 0805
16V 224 +80%-20% 0805
2
2
1
1
1
1
C710,C711
C710,C711
C716
C715
C715
C715
RH354708
4
L705,L707,L709,L710
PHOTOELECTRIC
TRANSFORMER
TX179ATW
1
JK705
PHOTOELECTRIC
TRANSFORMER
TX179AT
1
JK705
11
OUTJACK SOCKET
AV4-8.4-6G-3
1
JK702
12
OUTJACK SOCKET
13
OUTJACK SOCKET
14
CABLE SOCKET
15
CONNECTION CORDS
7
8
9
10
SA-001-012 BLACK IRON
PLATE SHIELDED
AV8-8.4-6G-3
14P1.0mm STRAITHR DOUBLE
PLUG
1
JK703
1
JK701
1
XS701
Φ0.6 SHAPED5mm
7
JP704,JP706,JP707,JP710,JP711,
JP712,JP701
62
16
17
CONNECTION CORDS
SCART SOCKET
Φ0.6 SHAPED10mm
SCART-01
5
1
18
CONNECTION CORDS
Φ0.6 SHAPED7.5mm
11
19
SMD MAGNETIC BEAD
FCM1608K-221T05
8
20
21
22
23
24
25
27
SMD CAPACITOR
PORCELAIN CAPACITOR
TRIODE
AMD RESISTOR
CARBON FILM RESISTOR
CARBON FILM RESISTOR
SMD RESISTOR
50V 20P ±5% NPO 0603
50V 20P ±10% NPO 5mm
S8050D
1/16W 4.7K ±5%
1/4W330Ω±5%
1/4W33Ω±5%
1/16W 1K ±5%
1
1
3
1
1
1
1
JP705,R707,L713,L714,JP719
JK706
JP702,JP703,JP708,JP709,JP713
~JP718,JP720
L715，
L716,L701~L704,L706,L708
C713
C712
V701~V703
R704
R709
R708
R711
28
SMD RESISTOR
1/16W 2.2K ±5%
2
R710,R712
29
30
31
32
33
SMD RESISTOR
SMD RESISTOR
SMD RESISTOR
CD
CD
1
1
2
5
1
R705
C707
34
SHIELDED CORDS
1/16W 75Ω ±5%
16V 105 +80%-20% 0603
1/16W 0Ω ±5%
CD11 16V220U±20%6×12 2.5
CD11 10V1000U±20%8×16 3.5
26# 100 1PSHIELDED HOLEф
4.2
35
PCB
7969-3
1
L711,L712
TC701,TC703~TC706
TC702
1
4. OUTPUT AUX FRONT BOARD
NO
MATERIAL
SPECIFICATIONS/PART NUMBER QUANTITY
LOCATION
R206~R209,R226,R240,R242,R249,R
251,R253,R255,R259,R264,R265,R26
6
1
SMD RESISTOR
1/16W 0Ω ±5%
15
2
SMD RESISTOR
1/16W 33Ω ±5%
5
R222,R223,R224,R225 ,R213
3
SMD ARRAY RESISTOR
1/16W33Ω ±5% 8P
8
4
SMD RESISTOR
1/16W 100Ω ±5%
6
5
SMD RESISTOR
1/16W 150Ω ±5%
1
RP203~RP208,RP201,RP202
R205,R216,R220,R221,R233,R23
4
R212
6
SMD RESISTOR
1/16W 470Ω ±5%
1
R228
7
SMD RESISTOR
1/16W 510Ω ±5%
1
R229
8
SMD RESISTOR
1/16W 1.2K ±5%
1
R204
9
SMD RESISTOR
1/16W 1.5K ±5%
1
R235
10
11
12
SMD RESISTOR
SMD RESISTOR
SMD RESISTOR
1/16W 2K ±5%
1/16W 2.2K ±5%
1/16W 3.3K ±5%
1
1
1
R203
R241
R236
13
SMD RESISTOR
1/16W 4.7K ±5%
1
R214
14
SMD RESISTOR
1/16W 5.1K ±5%
1
R230
15
16
SMD RESISTOR
SMD RESISTOR
1/16W 10K ±5%
1/16W 47K ±5%
6
1
17
CD
CD11 16V10U±20%5×11 2
5
18
19
CD
CD
CD11 16V22U±20%5×11 2
CD11 16V47U±20%5×11 2
1
3
20
CD
CD11 16V100U±20%6×12 2.5
9
21
SMD CAPACITOR
50V 27P ±5% NPO 0603
2
R217~R219,R243,R256 ,R237
R211
TC201,TC209,TC212,TC214,TC2
15
TC202
TC205,TC216,TC217
TC210,TC211,TC213,TC203,TC2
04,TC207,TC208,TC218,TC219
C201,C202
63
SMD CAPACITOR
50V 104 +80%-20% 0603
54
SMD CAPACITOR
25V 104 +80%-20% 0603
54
23
SMD MAGNETIC BEAD
FCM1608K-221T05
19
24
SMD MAGNETIC BEAD
RH354708
10
25
26
27
28
29
SMD TRIODE
DVI SOCKET
IC
IC
IC
3904
(24+5)P REFLECTIVE PLUG
FLI2310-BD QFP
AMS1084CD TO-252
MT48LC2M32B2 TSOP
1
1
1
2
1
C203,C206~C208,C210~C214,C2
16~C247,C264~C273,C254,C255
,C215
C203,C206~C208,C210~C214,C2
16~C247,C264~C273,C254,C255
,C215
L220~L236,L203,L204
L201,L202,L205,L206,L207,L208
,L209,L210,L211,L213
Q201
JK201
U201
U203,U204
U202
30
IC
SIL164CT64 QFP
1
U205
31
CRYSTAL OSCILLATOR
1
X201
32
CABLE SOCKET
13.50MHZ 49-S
14P1.0mmSTRAITHT BOUBLE
PLUG
1
XS202
33
PCB
C971-0
1
22
4. AUX FRONT BOARD
NO
MATERIAL
1
SMD DUAL COLOUR
LIGHTING DIODE
2
SOFT ARRAY COARD
3
4
LIGHT-TOUCH RESTORE
SWITCH
PCB
SPECIFICATIONS/PART NUMBER QUANTITY
LIGHTING ON TOP 0603×2
REN&BLUE
13P60 2.0 2PLUG WITH
REFLECTIVE NEDDLE
LOCATION
1
LED901
1
XS901
HERIZONTAL 6×6×1
1
9971-0
1
5. DECODE BOARD
NO
MATERIAL
SPECIFICATIONS/PART NUMBER QUANTITY
LOCATION
C2119,C2128,C2131,L210~L215,R20
1~R204,R212,R226,R228,R245,R247,
R2161,R251,R255,R257,R258,R282,
R298,R299,R303,R318,R331,R2159,
R297,R236,R234,R249
1
SMD RESISTOR
1/16W 0Ω ±5% 0603
34
2
3
4
CARBON FILM RESISTOR
SMD RESISTOR
SMD RESISTOR
1/4W2.2Ω±5%
1/16W1Ω±5% 0603
1/16W 10Ω ±5% 0603
1
6
2
5
SMD RESISTOR
1/16W 33Ω ±5% 0603
16
6
SMD RESISTOR
1/16W 150Ω ±5% 0603
8
7
SMD RESISTOR
1/16W 160Ω ±5% 0603
6
8
SMD RESISTOR
1/16W 330Ω ±5% 0603
1
R304~R307,R321,R340
R301,R302
R231,R232,R256,R263~R267,R29
1~R296,R2162 ,L202
R2109,R2180,R2167~R2172
R261,R270,R273,R274,R276,R28
0
R2105
9
SMD RESISTOR
1/16W 470Ω ±5% 0603
2
R325,R327
10
SMD RESISTOR
1/16W 680Ω ±5% 0603
2
11
SMD RESISTOR
1/16W 1K ±5% 0603
20
12
13
14
SMD RESISTOR
SMD RESISTOR
SMD RESISTOR
1/16W 1.5K ±5% 0603
1/16W 510Ω ±5% 0603
1/16W 3.3K ±5% 0603
3
1
1
R259,R260
L225,R213,R215,R2101~R2104,R
2117,R2118~R2128 ,R254
R323,R324,R243
R214
R242
64
R326
15
SMD RESISTOR
1/16W 3.9K ±5% 0603
1
R277
16
SMD RESISTOR
1/16W 4.7K ±5% 0603
16
R238~R240,R2130,R2131,R2134,R21
35,R2138~R2140,R2142,R2143,R214
6,R2147,R2150,R2151
17
SMD RESISTOR
1/16W 6.8K ±5% 0603
6
18
SMD RESISTOR
1/16W 10K ±5% 0603
12
19
20
SMD RESISTOR
SMD RESISTOR
1/16W 15K ±5% 0603
1/16W 20K ±5% 0603
2
4
21
SMD RESISTOR
1/16W24K±5% 0603
6
22
SMD RESISTOR
1/16W 18K ±5% 0603
1
R2136,R2148,R2152~R2155
R208,R229,R252,R309,R311,R31
3,R314,R329,R330,R339
,R2164,R2106
R209,R223
R211,R312,R315,R316
R2129,R2133,R2137,R2141,R214
5,R2149
R210
23
SMD RESISTOR
1/16W 150K ±5% 0603
2
R319,R320
24
PRECISION SMD RESISTOR 1/16W 680K ±1% 0603
2
R317,R322
25
PRECISION SMD RESISTOR 1/16W 750K ±1% 0603
1
26
SMD RESISTOR
1/16W 100K ±5% 0603
10
27
CD
CD11 16V10U±20%5×11 2
19
R227
R224,R308,R310,R2111~R2116
,R246
TC201,TC202,TC217,TC221~TC
233,TC236,TC240,TC241
28
CD
CD11 16V220U±20%6×12 2.5
9
29
CD
CD11 16V47U±20%5×11 2
15
30
31
SMD CAPACITOR
SMD CAPACITOR
50V 20P ±5% NPO 0603
50V 27P ±5% NPO 0603
1
2
32
SMD CAPACITOR
50V 47P ±5% NPO 0603
17
33
SMD CAPACITOR
50V 101 ±5% NPO 0603
8
C233,C2111,C2114,C2117,C2120,C2
123,C2126,C206
34
SMD CAPACITOR
50V 331 ±5% NPO 0603
2
C212,C213
35
SMD CAPACITOR
50V 151 ±5% NPO 0603
2
C304,C306
77
C207,C211,C214,C216,C217,C22
4,C226~C231,C234~C239,C241~
C254,C256~C259,C267~C274,C2
79,C301~C303,C305,C309,C311,
C312,C2138~C2143,C2153~C215
7,C2161,C2163,C2169,C2166,C21
74,C2175,C2168,C297,C280,C281
,C282,C2152,C232,C255
C207,C211,C214,C216,C217,C22
4,C226~C231,C234~C239,C241~
C254,C256~C259,C267~C274,C2
79,C301~C303,C305,C309,C311,
C312,C2138~C2143,C2153~C215
7,C2161,C2163,C2169,C2166,C21
74,C2175,C2168,C297,C280,C281
,C282,C2152,C232,C255
36
SMD CAPACITOR
50V 104 +80%-20% 0603
SMD CAPACITOR
25V 104 +80%-20% 0603
77
37
SMD CAPACITOR
16V 105 +80%-20% 0603
6
38
SMD CAPACITOR
50V 102 ±10% 0603
8
39
SMD CAPACITOR
50V 122 ±10% 0603
6
40
SMD CAPACITOR
50V 152 ±10% 0603
1
65
TC207~TC209,TC211,TC213,TC235,
TC245,TC301,TC203
TC204~TC206,TC210,TC234,TC
237,TC302~TC304,TC308,TC309
,TC247,TC248,TC239,TC249
C222
C275,C276
C262~C265,C266,C289,C290,C29
2,C293,C295,C296,C298,C299,C2
101,C2102,C2104,C2105
C201~C204,C221,C240
C2112,C2115,C2118,C2121,C212
4,C2127,C223,C278
C2122,C2129,C2130,C2133,C213
5,C2136
C215
41
SMD CAPACITOR
50V 222 ±10% 0603
2
C307,C310
42
SMD CAPACITOR
50V 153 ±10% 0603
1
C210
43
44
45
46
47
SMD CAPACITOR
SMD CAPACITOR
SMD CAPACITOR
SMD ELETRIC SENSOR
SMD INDUCTOR
MAGNETIC BEAD
INDUCTOR
16V 333 ±10% 0603
16V 473 ±10% 0603
16V474 +80%-20% 0603
10UH ±10% 2012
1.8UH ±10% 1608
1
2
1
3
6
RH354708
11
49
SMD MAGNETIC BEAD
FCM1608K-221T05
53
50
SMD RESISTOR
1/16W 4.7Ω ±5% 0603
1
C225
C219,C220
C218
L303,L306,L217
L243~L248
L205,L209,L220,L221,L222,L223
,L227,L228,L226.L302,L269
L201,L203,L207~L208,L224,L23
4~L236,L238,L250,L309,L229~L
233,L301,L304,L305,L307,L308,
L310~L312,L314,L316~L324,L25
1~L268,R271
L206
48
51
SMD DIODE
1N4148
6
VD201,VD205~VD209
SMD DIODE
LS4148
6
VD201,VD205~VD209
SMD DIODE
LL4148
6
VD201,VD205~VD209
52
TRIODE
C8050
2
V307,V308
53
TRIODE
8550C
2
V306,V309
54
SMD TRIODE
9014C
1
V310
55
TRIODE
9015C
1
Q204
56
57
58
59
TRIODE
SMD TRIODE
TRIODE
SMD TRIODE
C1815Y
C1815
2SA1015
3904
1
6
3
1
60
SMD TRIODE
3906
6
61
62
63
SMD TRIODE
SMD TRIODE
IC
IC
IC
IC
IC
2SK3018
2SB1132
NJM4558M SOP
4580 SOP
4558 SOP
MM74HCU04M SOP
HCU04 SOP
2
2
3
3
3
1
1
Q212
Q205~Q210
Q211,Q218,Q219
V305
Q220,Q221,Q222,Q223,Q224,Q22
5
V303,V304
V301,V302
U219,U220,U221
U219,U220,U221
U219,U220,U221
U205
U205
65
IC
HY57V641620HGT-7 TSOP
1
U211
66
67
68
69
70
71
IC
IC
IC
IC
IC
IC
IC
KSV464P4JA-70 TSOP
LM1117MP-ADJ SOT-223
CS4360 SSOP
CS4955-CQ TQFP
24C02N SOP
MT1389FE/C(C-VERSION) QFP
BA5954FP HSOP
1
1
1
1
1
1
1
U211
U209
U207
U206
U202
U201
U302
72
CRYSTAL OSCILLATOR
1
X201
73
CABLE SOCKET
2
XS204,XS205
74
PCB
27.00MHz 49-S
14P1.0mmSTAIGHT DOUBLE
LINE PLUG
2985S-2
75
SOCKET
5P 2.0mm
1
XS302
76
SOCKET
6P 2.0mm
1
XS303
77
SOCKET
7P 2.0mm
1
XS201
78
SOCKET
13P2.5mm
1
XS203
79
CABLE SOCKET
24P0.5mm SMD UP-CONNECT
WITH BUTTTON
1
XS301
64
66
1

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