Silicon Laboratories | SI5316 | Si5316

Si5316
P RECISION C L O C K J I T T E R A TTENUATOR
Description
„
The Si5316 is a low jitter, precision jitter attenuator for
high-speed communication systems, including OC-48,
OC-192, 10G Ethernet, and 10G Fibre Channel. The
Si5316 accepts dual clock inputs in the 19, 38, 77, 155,
311, or 622 MHz frequency range and generates a
jitter-attenuated clock output at the same frequency.
Within each of these clock ranges, the device can be
tuned approximately 15% higher than nominal
SONET/SDH frequencies, up to a maximum of
710 MHz in the 622 MHz range. The Si5316 is based
on Silicon Laboratories' 3rd-generation DSPLL®
technology, which provides any-rate frequency
synthesis and jitter attenuation in a highly integrated
PLL solution that eliminates the need for external
VCXO and loop filter components. The DSPLL loop
bandwidth is digitally programmable, providing jitter
performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the
Si5316 is ideal for providing jitter attenuation in high
performance timing applications.
„
Applications
„
„
„
„
„
„
Optical modules
SONET/SDH OC-48/OC-192/STM-16/STM-64 line
cards
10GbE, 10GFC line cards
ITU G.709 line cards
Wireless basestations
Test and measurement
Synchronous Ethernet
Features
Fixed frequency jitter attenuator with selectable
clock ranges at 19, 38, 77, 155, 311, and 622 MHz
(710 MHz max)
„ Support for SONET, 10GbE, 10GFC, and
corresponding FEC rates
„ Ultra-low jitter clock output with jitter generation as
low as 0.3 psRMS (50 kHz–80 MHz)
„
„
„
„
„
„
„
„
„
„
Integrated loop filter with selectable loop bandwidth
(100 Hz to 7.9 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Dual clock inputs with integrated clock select mux
One clock input can be 1x, 4x, or 32x the frequency
of the second clock input
Single clock output with selectable signal format:
LVPECL, LVDS, CML, CMOS
LOL, LOS alarm outputs
Pin programmable settings
On-chip voltage regulator for 1.8 ±5%, 2.5 ±10%, or
3.3 V ±10% operation
Small size (6 x 6 mm 36-lead QFN)
Pb-free, RoHS compliant
Xtal or Refclock
CK1DIV
Signal Format
÷
CKIN1
DSPLL ®
CK2DIV
÷
CKIN2
Loss of Signal
Disable
VDD (1.8, 2.5, or 3.3 V)
Signal
Detect
GND
Clock
Select
Rev. 0.4 4/08
CKOUT
Frequency Bandwidth
Select
Select
Loss of
Lock
PLL
Bypass
Copyright © 2008 by Silicon Laboratories
Si5316
Si5316
Table 1. Performance Specifications1
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Supply Current
Input/Output Clock Frequency (CKIN1, CKIN2,
CKOUT)
Symbol
TA
VDD
Test Condition
IDD
fOUT = 622.08 MHz
LVPECL format output
fOUT = 19.44 MHz
CMOS format output
Disable Mode
FRQSEL[1:0] = LL
FRQSEL[1:0] = LM
FRQSEL[1:0] = LH
FRQSEL[1:0] = ML
FRQSEL[1:0] = MM
FRQSEL[1:0] = MH
CKF
3-Level Input Pins
Input Mid Current
IIMM
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing
CKNDPP
Common Mode Voltage
CKNVCM
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
Output Clock (CKOUT)
Common Mode
Differential Output Swing
Single Ended Output Swing
Rise/Fall Time
Duty Cycle Uncertainty
PLL Performance
Jitter Generation
LVPECL output,
fIN = fOUT = 622.08
BW[1:0] = HM
CKNTRF
CKNDC
VOCM
VOD
VSE
CKOTRF
CKODC
JGEN
Min
–40
2.97
2.25
1.71
—
Typ
25
3.3
2.5
1.8
217
Max
85
3.63
2.75
1.89
243
Unit
ºC
V
V
V
mA
—
194
220
mA
—
19.38
38.75
77.5
155.0
310.0
620.0
165
—
—
—
—
—
—
215
22.28
44.56
89.13
178.25
356.5
710.0
mA
MHz
See Note 2.
–2
—
2
µA
1.8 V ±5%
2.5 V ±10%
3.3 V ±10%
20–80%
Whichever is smaller
0.25
0.9
1.0
1.1
—
40
2
—
—
—
—
—
—
—
1.9
1.4
1.7
1.95
11
60
—
VPP
V
V
V
ns
%
ns
VDD – 1.42
1.1
0.5
—
–40
—
—
—
230
—
VDD – 1.25
1.9
0.93
350
40
V
VPP
V
ps
ps
—
—
0.32
0.31
0.42
0.41
ps rms
ps rms
LVPECL
100 Ω load
line-to-line
20–80%
LVPECL
Differential 100 Ω
line-to-line;
measured at 50% point
50 kHz–80 MHz
12 kHz–20 MHz
Notes:
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs, an external resistor voltage divider is recommended.
2
Rev. 0.4
Si5316
Table 1. Performance Specifications1 (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Jitter Transfer
External Reference Jitter
Transfer
Phase Noise
fIN = fOUT = 622.08
Symbol
JPK
JPKEXTN
Test Condition
Min
—
—
Typ
0.05
30
Max
0.1
—
Unit
dB
kHz
CKOPN
Subharmonic Noise
fIN = fOUT = 622.08
Spurious Noise
fIN = fOUT = 622.08
Package
Thermal Resistance
Junction to Ambient
SPSUBH
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
Phase Noise @ 100 kHz
Offset
—
—
—
—
—
—
–65
–95
–110
–117
–130
–90
–50
–87
–100
–110
–125
–85
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
SPSPUR
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
—
–98
–75
dBc
θJA
Still Air
—
38
—
ºC/W
Notes:
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs, an external resistor voltage divider is recommended.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 3.6
V
LVCMOS Input Voltage
VDIG
–0.3 to (VDD + 0.3)
V
Operating Junction Temperature
TJCT
–55 to 150
ºC
Storage Temperature Range
TSTG
–55 to 150
ºC
2
kV
ESD MM Tolerance; All pins except CKIN+/CKIN–
200
V
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
700
V
ESD MM Tolerance; CKIN+/CKIN–
150
V
Latch-Up Tolerance
JESD78 Compliant
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except
CKIN+/CKIN–
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Rev. 0.4
3
Si5316
0
Phase Noise (dBc/Hz)
-20
-40
-60
-80
-100
-120
-140
-160
100
1000
10000
100000
1000000
10000000
Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
Jitter Band
Brick Wall, 100 Hz to 100 MHz
4
Jitter, RMS
1,279 fs
SONET_OC48, 12 kHz to 20 MHz
315 fs
SONET_OC192_A, 20 kHz to 80 MHz
335 fs
SONET_OC192_B, 4 MHz to 80 MHz
194 fs
SONET_OC192_C, 50 kHz to 80 MHz
318 fs
Brick Wall, 800 Hz to 80 MHz
343 fs
Rev. 0.4
100000000
Si5316
C4 1 µF
System
Power
Supply
C3 0.1 µF
Ferrite
Bead
C2 0.1 µF
VDD = 3.3 V
C1 0.1 µF
130 Ω
GND
CKIN1+
VDD
130 Ω
0.1 µF
CKOUT+
CKIN1–
82 Ω
+
Clock
Output
100 Ω
CKOUT–
82 Ω
–
0.1 µF
Input
Clock
Sources1
VDD = 3.3 V
130 Ω
130 Ω
CKIN2+
CKIN2–
82 Ω
82 Ω
Option 1:
CKIN_1 Loss of Signal
C2B
CKIN_2 Loss of Signal
LOL
PLL Loss of Lock Indicator
XA
Crystal (114.285 MHz)
XB
Option 2:
C1B
Si5316
0.1 µF
38.88 MHz Refclk+
XA
0.1 µF
38.88 MHz Refclk–
XB
VDD
15 kΩ
RATE2
Crystal/Ref Clk Rate
15 kΩ
Input Clock Select
CS
VDD
15 kΩ
Input Clock 1 Pre-Divider Select
Input Clock 2 Pre-Divider Select
15 kΩ
VDD
15 kΩ
Frequency Select
15 kΩ
Signal Format Select
15 kΩ
Clock Output Disable/
Bypass Mode Control
Reset
FRQSEL[1:0]2
15 kΩ
VDD
CK2DIV2
15 kΩ
VDD
15 kΩ
Bandwidth Select
CK1DIV2
VDD
15 kΩ
BWSEL[1:0]2
15 kΩ
SFOUT[1:0]2
VDD
15 kΩ
DBL_BY2
15 kΩ
RST
Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes 3-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
Figure 2. Si5316 Typical Application Circuit
Rev. 0.4
5
Si5316
1. Functional Description
1.1. External Reference
The Si5316 is a precision jitter attenuator for high-speed
communication systems, including OC-48/STM-16, OC192/STM-64, 10G Ethernet, and 10G Fibre Channel.
The Si5316 accepts dual clock inputs in the 19, 38, 77,
155, 311, or 622 MHz frequency range and generates a
jitter-attenuated clock output at the same frequency.
Within each of these clock ranges, the device can be
tuned approximately 15% higher than nominal
SONET/SDH frequencies, up to a maximum of
710 MHz in the 622 MHz range. The Si5316 is based on
Silicon
Laboratories'
3rd-generation
DSPLL®
technology, which provides any-rate frequency
synthesis and jitter attenuation in a highly integrated
PLL solution that eliminates the need for external VCXO
and loop filter components. For applications which
require input clocks at different frequencies, the
frequency of CKIN1 can be 1x, 4x, or 32x the frequency
of CKIN2 as specified by the CK1DIV and CK2DIV
inputs.
The Si5316 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 100 Hz to
7.9 kHz. To calculate potential loop bandwidth values
for a given input/output clock frequency, Silicon
Laboratories offers a PC-based software utility,
DSPLLsim, that calculates valid loop bandwidth settings
automatically. This utility can be downloaded from
http://www.silabs.com/timing; click on Documentation.
An external, 38.88 MHz clock or a low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to operate.
Silicon Laboratories recommends using a high quality
crystal. Specific recommendations may be found in the
Family Reference Manual. An external 38.88 MHz clock
from a high quality OCXO or TCXO can also be used as
a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5316. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
The Si5316 supports manual active input clock
selection. The Si5316 monitors both input clocks for
loss-of-signal and provides a LOS alarm when it detects
missing pulses on either input clock. Hitless switching is
not supported by the Si5316. During a clock transition,
the phase of the output clock will slew at a rate defined
by the PLL loop bandwidth until the original input clock
phase to output clock phase is restored. The device
monitors the lock status of the PLL. The lock detect
algorithm works by continuously monitoring the phase
of the input clock in relation to the phase of the
feedback clock.
The Si5316 has one differential clock output. The
electrical format of the clock output is programmable to
support LVPECL, LVDS, CML, or CMOS loads. For
system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
6
Rev. 0.4
Si5316
NC
NC
SFOUT1
VDD
GND
SFOUT0
CKOUT–
CKOUT+
NC
2. Pin Descriptions: Si5316
36 35 34 33 32 31 30 29 28
RST
1
27 CK2DIV
NC
2
26 CK1DIV
C1B
3
25 FRQSEL1
C2B
4
VDD
5
XA
6
XB
7
GND
8
20 GND
NC
9
19 GND
24 FRQSEL0
GND
Pad
23 BWSEL1
22 BWSEL0
21 CS
LOL
CKIN1–
CKIN1+
RATE1
DBL_BY
CKIN2–
CKIN2+
VDD
RATE0
10 11 12 13 14 15 16 17 18
Table 3. Si5316 Pin Descriptions
Pin #
1
Pin Name
RST
I/O
I
2, 9, 28,
29, 36
NC
—
3
C1B
O
4
C2B
O
5, 10, 32
VDD
VDD
Signal Level
Description
LVCMOS
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state. Clock outputs are tristated
during reset. After rising edge of RST signal, the Si5316 will perform
an internal self-calibration when a valid signal is present.
This pin has a weak pull-up.
—
No Connect.
These pins must be left unconnected for normal operation.
LVCMOS
CKIN1 Loss of Signal.
Active high Loss-of-signal indicator for CKIN1. Once triggered, the
alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
LVCMOS
CKIN2 Loss of Signal.
Active high Loss-of-signal indicator for CKIN2. Once triggered, the
alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins:
5
0.1 µF
10
0.1 µF
32
0.1 µF
A 1.0 µF should also be placed as close to device as is practical.
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
Rev. 0.4
7
Si5316
Table 3. Si5316 Pin Descriptions (Continued)
Pin #
7
6
Pin Name
XB
XA
I/O
I
Signal Level
Description
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be from
a high-quality clock source (TCXO, OCXO). Frequency of crystal or
external clock is set by the RATE pins.
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
8, 19*,
20*, 31
GND
11
15
RATE0
RATE1
I
3-Level*
12
13
CKIN2+
CKIN2–
I
Multi
14
DBL_BY
I
3-Level*
16
17
CKIN1+
CKIN1–
I
Multi
18
LOL
O
LVCMOS
21
CS
I
LVCMOS
*Note: May be left NC.
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M. The "HH" setting is not supported.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Input 2.
Differential input clock. This input can also be driven with a singleended signal.
Output Disable/Bypass Mode Control.
Controls enable of CKOUT divider/output buffer path and PLL
bypass mode.
L = CKOUT enabled
M = CKOUT disabled
H = Bypass mode with CKOUT enabled
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Input 1.
Differential input clock. This input can also be driven with a singleended signal.
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked
1 = PLL unlocked
Input Clock Select.
This pin functions as the input clock selector. This input is internally
deglitched to prevent inadvertent clock switching during changes in
the CKSEL input state.
0 = Select CKIN1
1 = Select CKIN2
Must be driven high or low.
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
8
Rev. 0.4
Si5316
Table 3. Si5316 Pin Descriptions (Continued)
Pin #
23
22
Pin Name
BWSEL1
BWSEL0
I/O
I
25
24
FRQSEL1
FRQSEL0
I
26
CK1DIV
I
27
CK2DIV
I
Signal Level
Description
3-Level
Bandwidth Select.
Three level inputs that select the DSPLL closed loop bandwidth.
Detailed operations and timing characteristics for these pins may be
found in the Any-Rate Precision Clock Family Reference Manual.
These pins are both pull-ups and pull-downs and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
3-Level
Frequency Select.
Sets the output frequency of the device. When the frequency of
CKIN1 is not equal to CKIN2, the lower frequency input clock must
be equal to the output clock frequency. These pins have both weak
pull-ups and weak pull-downs and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
3-Level
Input Clock 1 Pre-Divider Select.
Pre-divider on CKIN1. Used with CK2DIV to divide input clock
frequencies to a common value.
L = CKIN1 input divider set to 1.
M = CKIN1 input divider set to 4.
H = CKIN1 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
3-Level
Input Clock 2 Pre-Divider Select.
Pre-divider on CKIN2. Used with CK1DIV to divide input clock
frequencies to a common value.
L = CKIN2 input divider set to 1.
M = CKIN2 input divider set to 4.
H = CKIN2 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
Rev. 0.4
9
Si5316
Table 3. Si5316 Pin Descriptions (Continued)
Pin #
33
30
Pin Name
SFOUT0
SFOUT1
I/O
I
Signal Level
Description
3-Level
Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for CKOUT. Valid settings
include LVPECL, LVDS, and CML. Also includes selections for
CMOS mode, tristate mode, and tristate/sleep mode.
SFOUT[1:0]
34
35
CKOUT–
CKOUT+
O
Multi
GND PAD
GND
GND
Supply
Signal Format
HH
LVDS
HM
Reserved
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—low swing
LH
CMOS
LM
Disabled
LL
Reserved
These pins have both weak pull-ups and weak pull-downs and
default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Output.
Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electrical impedance
to a ground plane.
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
10
Rev. 0.4
Si5316
3. Ordering Guide
Ordering Part Number
Package
ROHS6, Pb-Free
Temperature Range
Si5316-C-GM
36-Lead 6 x 6 mm QFN
Yes
–40 to 85 °C
Rev. 0.4
11
Si5316
4. Package Outline: 36-Lead QFN
Figure 3 illustrates the package details for the Si5316. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 3. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
θ
—
—
12º
b
0.18
0.25
0.30
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
D
D2
L
6.00 BSC
3.95
4.10
4.25
Min
Nom
Max
0.50
0.60
0.70
e
0.50 BSC
ddd
—
—
0.10
E
6.00 BSC
eee
—
—
0.05
E2
3.95
4.10
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
12
Rev. 0.4
Si5316
5. Recommended PCB Layout
Figure 4. PCB Land Pattern Diagram
Rev. 0.4
13
Si5316
Table 5. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
E
5.42 REF.
D
5.42 REF.
E2
4.00
4.20
D2
4.00
4.20
GE
4.53
—
GD
4.53
—
X
—
0.28
Y
0.89 REF.
ZE
—
6.31
ZD
—
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
14
Rev. 0.4
Si5316
DOCUMENT CHANGE LIST
Revision 0.23 to 0.24
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„
„
„
„
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Showed preferred interface for an external reference
clock in Figure 2, “Si5316 Typical Application
Circuit,” on page 5.
Updated 3. "Ordering Guide" on page 11.
Added “5. Recommended PCB Layout”.
Revision 0.24 to Revision 0.3
„
„
„
„
„
„
„
Changed 1.8 V operating range ±5%.
Updated Table 1 on page 2.
Updated Table 2 on page 3.
Updated Table 3 on page 7.
Added table under Figure 1 on page 4.
Updated 1. "Functional Description" on page 6.
Clarified 2. "Pin Descriptions: Si5316" on page 7
including pull-up/pull-down.
Revision 0.3 to Revision 0.4
„
„
„
„
„
Updated Table 1, “Performance Specifications1,” on
page 2.
Updated Table 3, “Si5316 Pin Descriptions,” on
page 7.
Updated Figure 2, “Si5316 Typical Application
Circuit,” on page 5.
Updated 1.1. "External Reference" on page 6.
Updated 2. "Pin Descriptions: Si5316" on page 7.
Rev. 0.4
15
Si5316
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16
Rev. 0.4
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