User`s manual | Analog Devices ADSP-2181 Network Card User Manual

a
FEATURES
PERFORMANCE
30 ns Instruction Cycle Time @ 5.0 Volts
33 MIPS Sustained Performance
34.7 ns Instruction Cycle Time @ 3.3 Volts
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, & Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead TQFP/128-Lead PQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables &
Program Overlays
8-Bit DMA to Byte Memory for Transparent
Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Memory Strobe & Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DSP Microcomputers
ADSP-2181/ADSP-2183
FUNCTIONAL BLOCK DIAGRAM
POWERDOWN
CONTROL
DATA ADDRESS
GENERATORS
DAG 1 DAG 0
PROGRAMMABLE
I/O
FLAGS
MEMORY
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
BYTE DMA
CONTROLLER
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0
SPORT 1
TIMER
INTERNAL
DMA
PORT
DMA
BUS
ADSP-2100 BASE
ARCHITECTURE
GENERAL DESCRIPTION
The ADSP-2181/ADSP-2183 is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSP-2181/ADSP-2183 combines the ADSP-2100 family
base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The ADSP-2181/ADSP-2183 integrates 80K bytes of on-chip
memory configured as 16K words (24-bit) of program RAM,
and 16K words (16-bit) of data RAM. Power down circuitry is
also provided to meet the low power needs of battery operated
portable equipment. The ADSP-2181 is available in 128-pin
TQFP and 128-pin PQFP packages; the ADSP-2183 is available in the TQFP package only.
In addition, the ADSP-2181/ADSP-2183 supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle,
bit test—new ALU constants, new multiplication instruction
(x squared), biased rounding, result free ALU operations, I/O memory
transfers, and global interrupt masking, for increased flexibility.
Fabricated in a high speed, double metal, low power, 0.5 µm
CMOS process, the ADSP-2181 operates with a 30 ns instruction cycle time (34.7 ns for the ADSP-2183). Every instruction
can execute in a single processor cycle.
The ADSP-2181/ADSP-2183’s flexible architecture and comprehensive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle the ADSP-2181/
ADSP-2183 can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADSP-2181/ADSP-2183
This takes place while the processor continues to:
• receive and transmit data through the two serial ports
• receive and/or transmit data through the internal DMA port
• receive and/or transmit data through the byte DMA port
• decrement timer
Additional Information
This data sheet provides a general overview of ADSP-2181/
ADSP-2183 functionality. For additional information on the
architecture and instruction set of the processor, refer to the
ADSP-2100 Family User’s Manual. For more information about
the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.
Development System
The ADSP-2100 Family Development Software, a complete set of
tools for software and hardware system development, supports the
ADSP-2181/ADSP-2183. The System Builder provides a high
level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. The C
Compiler, based on the Free Software Foundation’s GNU C
Compiler, generates ADSP-2181/ADSP-2183 assembly source
code. The source code debugger allows programs to be corrected
in the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-2181 based evaluation board with PC monitor software
plus Assembler, Linker, Simulator, and PROM Splitter software.
The ADSP-2181 EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features:
• 33 MHz ADSP-2181
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort® Codec
• RS-232 Interface to PC with Windows 3.1 Control Software
• Stand-Alone Operation with Socketed EPROM
• EZ-ICE Connector for Emulator Control
• DSP Demo Programs
The ADSP-2181 EZ-ICE® Emulator aids in the hardware debugging of ADSP-2181 system. The emulator consists of hardware, host computer resident software, and the target board
connector. The ADSP-2181/ADSP-2183 integrates on-chip
emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires
fewer mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. The ADSP-2181/ADSP-2183
device need not be removed from the target system when using
the EZ-ICE, nor are any adapters needed. Due to the small
footprint of the EZ-ICE connector, emulation can be supported
in final board designs.
The EZ-ICE performs a full range of functions, including:
• Stand-alone or in-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
ARCHITECTURE OVERVIEW
The ADSP-2181/ADSP-2183 instruction set provides flexible
data moves and multifunction (one or two data moves with a
computation) instructions. Every instruction can be executed in
a single processor cycle. The ADSP-2181/ADSP-2183 assembly
language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2181/ADSP2183. The processor contains three independent computational
units: the ALU, the multiplier/accumulator (MAC) and the
shifter. The computational units process 16-bit data directly and
have provisions to support multiprecision computations. The
ALU performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical
and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2181/ADSP-2183 executes
looped code with zero overhead; no explicit jump instructions
are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for circular buffers.
Efficient data transfer is achieved with the use of five internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual as well as page 11 of this
data sheet for exact specifications of the EZ-ICE target board
connector.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
–2–
REV. 0
ADSP-2181/ADSP-2183
Program memory can store both instructions and data, permitting the ADSP-2181/ADSP-2183 to fetch two operands in a
single cycle, one from program memory and one from data
memory. The ADSP-2181/ADSP-2183 can fetch an operand from
program memory and the next instruction in the same cycle.
In addition to the address and data bus for external memory
connection, the ADSP-2181/ADSP-2183 has a 16-bit Internal
DMA port (IDMA port) for connection to external systems.
The IDMA port is made up of 16 data/address pins and five
control pins. The IDMA port provides transparent, direct access
to the DSPs on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH, and BG).
One execution mode (Go Mode) allows the ADSP-2181/ADSP2183 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted.
The ADSP-2181/ADSP-2183 can respond to eleven interrupts.
There can be up to six external interrupts (one edge-sensitive,
two level-sensitive, and three configurable) and seven internal
interrupts generated by the timer, the serial ports (SPORTs),
the Byte DMA port, and the power-down circuitry. There is
also a master RESET signal.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2181/ADSP-2183 provides up to 13 general-purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag. In
addition, there are eight flags that are programmable as inputs
or outputs, and three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n processor cycles, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2181/ADSP-2183 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2181/ADSP2183 SPORTs. Refer to the ADSP-2100 Family User’s Manual
for further details.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulse widths and timings.
The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
ADSP-2181/ADSP-2183 INTEGRATION
21xx CORE
POWER
DOWN
CONTROL
LOGIC
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
DATA
SRAM
16k × 16
PROGRAM
SRAM
16k × 24
BYTE
DMA
CONTROLLER
2
8
PROGRAMMABLE
I/O
3
PROGRAM
SEQUENCER
FLAGS
PMA BUS
14
PMA BUS
DMA BUS
14
DMA BUS
14
MUX
EXTERNAL
ADDRESS
BUS
PMD BUS
PMD BUS
24
EXTERNAL
DATA
BUS
BUS
EXCHANGE
DMD BUS
DMD
BUS
MUX
24
16
INPUT REGS
REGS
INPUT
INPUTREGS
REGS
INPUT
INPUT REGS
ALU
ALU
MAC
MAC
SHIFTER
OUTPUT REGS
REGS
OUTPUT
OUTPUTREGS
REGS
OUTPUT
OUTPUT REGS
COMPANDING
CIRCUITRY
TIMER
16
TRANSMIT REG
TRANSMIT REG
5
RECEIVE REG
RECEIVE REG
SERIAL
PORT 0
SERIAL
PORT 0
R BUS
5
Figure 1. ADSP-2181/ADSP-2183 Block Diagram
REV. 0
–3–
5
INTERNAL
DMA
PORT
16
4
INTERRUPTS
ADSP-2181/ADSP-2183
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
Pin
Name(s)
• SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.
#
of
Pins
CLKOUT 1
SPORT0
5
SPORT1
5
Input/
Output Function
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed, serial bitstream.
IRD, IWR
IS
IAL
2
1
1
I
I
I
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
IAD
IACK
16
1
I/O
O
PWD
PWDACK
FL0, FL1,
FL2
PF7:0
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
GND
VDD
1
1
I
O
Processor Clock Output.
Serial Port I/O Pins
Serial Port 1 or Two External
IRQs, Flag In and Flag Out
IDMA Port Read/Write Inputs
IDMA Port Select
IDMA Port Address Latch
Enable
IDMA Port Address/Data Bus
IDMA Port Access Ready
Acknowledge
Powerdown Control
Powerdown Control
3
8
1
1
1
1
1
1
1
1
1
11
6
O
I/O
*
*
*
*
*
*
*
*
*
–
–
Output Flags
Programmable I/O Pins
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
Ground Pins
Power Supply Pins
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
Pin Descriptions
The ADSP-2181/ADSP-2183 is available in 128-lead TQFP
and 128-lead PQFP packages.
PIN DESCRIPTIONS
Pin
Name(s)
#
of
Pins
Input/
Output Function
Address
14
O
Address Output Pins for Program,
Data
24
I/O
RESET
IRQ2
1
1
I
I
Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)
Processor Reset Input
Edge- or Level-Sensitive
Interrupt Request
IRQL0,
IRQL1
2
I
IRQE
1
I
BR
BG
BGH
PMS
DMS
BMS
IOMS
CMS
RD
WR
MMAP
BMODE
CLKIN,
XTAL
1
1
1
1
1
1
1
1
1
1
1
1
I
O
O
O
O
O
O
O
O
O
I
I
Level-Sensitive Interrupt
Requests
Edge-Sensitive Interrupt
Request
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Program Memory Select Output
Data Memory Select Output
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Memory Map Select Input
Boot Option Control Input
2
I
Clock or Quartz Crystal Input
Data, Byte, & I/O Spaces
O
I/O
I/O
*These ADSP-2181/ADSP-2183 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function except during
emulation, and do not require pull-up or pull-down resistors.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2181/ADSP-2183 provides four dedicated external
interrupt input pins, IRQ2, IRQL0, IRQL1, and IRQE. In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN
and FLAG_OUT, for a total of six external interrupts. The ADSP2181/ADSP-2183 also supports internal interrupts from the timer,
the byte DMA port, the two serial ports, software, and the
power-down control circuit. The interrupt levels are internally
prioritized and individually maskable (except power down and
reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed
to be either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I, and the interrupt registers are shown in Figure 7.
–4–
REV. 0
ADSP-2181/ADSP-2183
Table I. Interrupt Priority & Interrupt Vector Addresses
Source of Interrupt
Interrupt Vector
Address (Hex)
Reset (or Power-Up with PUCR = 1)
Power Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Power Down
The ADSP-2181/ADSP-2183 processor has a low power
feature that lets the processor enter a very low power dormant state through hardware or software control. Here is a
brief list of power-down features. Refer to the ADSP-2100
Family User’s Manual, Chapter 9 “System Interface” for detailed information about the power-down feature.
• Quick recovery from power down. The processor begins
executing instructions in as few as 100 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running
during power down without affecting the lowest power rating and 100 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 100 CLKIN
cycle start up.
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
• Power down is initiated by either the power-down pin
(PWD) or the software power-down force bit.
• Interrupt support allows an unlimited number of instructions to be executed before optionally powering down.
The power-down interrupt also can be used as a nonmaskable, edge sensitive interrupt.
The ADSP-2181/ADSP-2183 masks all interrupts for one instruction cycle following the execution of an instruction that
modifies the IMASK register. This does not affect serial port
autobuffering or DMA transfers.
• Context clear/save control allows the processor to continue where it left off or start with a clean context when
leaving the power-down state.
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts
to be either edge- or level-sensitive. The IRQE pin is an external
edge sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level sensitive interrupts.
• The RESET pin also can be used to terminate power
down.
• Power-down acknowledge pin indicates when the processor has entered power down.
The IFC register is a write-only register used to force and clear
interrupts.
Processor supply current during power down varies with
temperature, see Figures 8 and 15.
On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are
twelve levels deep to allow interrupt, loop, and subroutine
nesting.
Idle
When the ADSP-2181/ADSP-2183 is in the Idle Mode, the
processor waits indefinitely in a low power state until an
interrupt occurs. When an unmasked interrupt occurs, it is
serviced; execution then continues with the instruction following the IDLE instruction.
The following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2181/
ADSP-2183 to let the processor’s internal clock signal be
slowed, further reducing power consumption. The reduced
clock frequency, a programmable fraction of the normal
clock rate, is specified by a selectable divisor given in the
IDLE instruction. The format of the instruction is
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2181/ADSP-2183 has three low power modes that
significantly reduce the power dissipation when the device operates under standby conditions. These modes are:
• Power Down
• Idle
• Slow Idle
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT, and timer clock,
are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard
IDLE instruction.
The CLKOUT pin may also be disabled to reduce external
power dissipation.
REV. 0
–5–
ADSP-2181/ADSP-2183
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2181/ADSP-2183 will remain
in the idle state for up to a maximum of n processor cycles (n =
16, 32, 64, or 128) before resuming normal operation.
The ADSP-2181/ADSP-2183 uses an input clock with a frequency equal to half the instruction rate; a 16.67 MHz input
clock yields a 30 ns processor cycle (which is equivalent to
33 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when
enabled.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
Because the ADSP-2181/ADSP-2183 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2181/ADSP-2183, two serial devices, a byte-wide
EPROM, and optional external program and data overlay
memories. Program-mable wait state generation allows the processor connects easily to slow peripheral devices. The ADSP2181/ADSP-2183 also provides four external interrupts and two
serial ports or six external interrupts and one serial port.
CLKIN
XTAL
CLKOUT
ADSP-2181/
ADSP-2183
ADSP-2181/
ADSP-2183
1/2x CLOCK
OR
CRYSTAL
14
CLKIN
A13-0
ADDR13-0
XTAL
FL0-2
PF0-7
IRQ2
IRQE
IRQL0
IRQL1
D23-16
24
DATA
DATA23-0
Figure 3. External Crystal Connections
A0-A21
D15-8
BYTE
MEMORY
Reset
The RESET signal initiates a master reset of the ADSP-2181/
ADSP-2183. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after
power up, the clock continues to run and does not require
stabilization time.
CS
BMS
A10-0
ADDR
D23-8
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SERIAL
DEVICE
DATA
CS
IOMS
ADDR
SERIAL
DEVICE
IDMA PORT
SYSTEM
INTERFACE
OR
µCONTROLLER
16
IRD
IWR
IS
IAL
IACK
IAD15-0
2048 LOCATIONS
A13-0
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
I/O SPACE
(PERIPHERALS)
D23-0
DATA
PMS
DMS
CMS
OVERLAY
MEMORY
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the minimum pulse width specification, tRSP.
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
BR
BG
BGH
PWD
PWDACK
Figure 2. ADSP-2181/ADSP-2183 Basic System Configuration
Clock Signals
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended.
The ADSP-2181/ADSP-2183 can be clocked by either a crystal
or by a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual for detailed information on
this power-down feature.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
–6–
REV. 0
ADSP-2181/ADSP-2183
Table II.
Memory Architecture
The ADSP-2181/ADSP-2183 provides a variety of memory and
peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O.
Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2181/ADSP-2183 has
16K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces
using the external data bus. Both an instruction opcode and a
data value can be read from on-chip program memory in a
single cycle.
Data Memory is a 16-bit-wide space used for the storage of
data variables and for memory-mapped control registers. The
ADSP-2181/ADSP-2183 has 16K words on Data Memory RAM
on chip, consisting of 16,352 user-accessible locations and 32
memory-mapped registers. Support also exists for up to two 8K
external memory overlay spaces through the external data bus.
PMOVLAY Memory
A13
A12:0
0
Internal
Not Applicable
Not Applicable
1
External
Overlay 1
0
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
This organization provides for two external 8K overlay segments
using only the normal 14 address bits. This allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space in that the processor core (i.e., the sequencer)
does not take into account the PMOVLAY register value. For
example, if a loop operation was occurring on one of the external overlays and the program changes to another external overlay or internal memory, an incorrect loop operation could occur.
In addition, care must be taken in interrupt service routines as
the overlay registers are not automatically saved and restored on
the processor mode stack.
Byte Memory provides access to an 8-bit wide memory space
through the Byte DMA (BDMA) port. The Byte Memory interface provides access to 4 MBytes of memory by utilizing eight
data lines as additional address lines. This gives the BDMA Port
an effective 22-bit address range. On power-up, the DSP can
automatically load bootstrap code from byte memory.
I/O Space allows access to 2048 locations of 16-bit-wide data.
It is intended to be used to communicate with parallel peripheral devices such as data converters and external registers or
latches.
For ADSP-2100 Family compatibility, MMAP = 1 is allowed.
In this mode, booting is disabled and overlay memory is disabled (PMOVLAY must be 0). Figure 5 shows the memory map
in this configuration.
Program Memory
The ADSP-2181/ADSP-2183 contains a 16K × 24 on-chip
program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can
complete in a single cycle. In addition, the ADSP-2181/ADSP2183 allows the use of 8K external memory overlays.
PROGRAM MEMORY
0x3FFF
INTERNAL 8K
(PMOVLAY = 0,
MMAP = 1)
0x2000
0x1FFF
The program memory space organization is controlled by the
MMAP pin and the PMOVLAY register. Normally, the ADSP2181/ADSP-2183 is configured with MMAP = 0 and program
memory organized as shown in Figure 4.
PROGRAM MEMORY
ADDRESS
8K EXTERNAL
0x0000
Figure 5. Program Memory (MMAP = 1)
ADDRESS
0x3FFF
Data Memory
8K INTERNAL
The ADSP-2181/ADSP-2183 has 16,352 16-bit words of internal data memory. In addition, the ADSP-2181/ADSP-2183
allows the use of 8K external memory overlays. Figure 6 shows
the organization of the data memory.
(PMOVLAY = 0,
MMAP = 0)
OR
EXTERNAL 8K
(PMOVLAY = 1 or 2,
MMAP = 0)
0x2000
0x1FFF
DATA MEMORY
8K INTERNAL
32 MEMORY–
MAPPED REGISTERS
ADDRESS
0x3FFF
0x3FEO
0x0000
0x3FDF
INTERNAL
8160 WORDS
Figure 4. Program Memory (MMAP = 0)
0x2000
There are 16K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to
something other than 0, external accesses occur at addresses
0x2000 through 0x3FFF. The external address is generated as
shown in Table II.
8K INTERNAL
(DMOVLAY = 0)
OR
EXTERNAL 8K
(DMOVLAY = 1, 2)
0x1FFF
0x0000
Figure 6. Data Memory
REV. 0
–7–
ADSP-2181/ADSP-2183
There are 16,352 words of memory accessible internally when
the DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
Byte Memory
Table III.
DMOVLAY
Memory
A13
A12:0
0
Internal
Not Applicable
Not Applicable
1
External 0
Overlay 1
13 LSBs of Address
Between 0x0000
and 0x1FFF
2
External 1
Overlay 2
13 LSBs of Address
Between 0x0000
and 0x1FFF
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K × 8.
The byte memory space on the ADSP-2181/ADSP-2183 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte
memory uses data bits 23:16 and address bits 13:0 to create a
22-bit address. This allows up to a 4 meg × 8 (32 megabit)
ROM or RAM to be used without glue logic. All byte memory
accesses are timed by the BMWAIT register.
Byte Memory DMA (BDMA)
This organization allows for two external 8K overlays using only
the normal 14 address bits.
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register.
I/O Space
The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to
build the word size selected. Table V shows the data formats
supported by the BDMA circuit.
The ADSP-2181/ADSP-2183 supports an additional external
memory space called I/O space. This space is designed to support simple connections to peripherals or to bus interface ASIC
data registers. I/O space supports 2048 locations. The lower
eleven bits of the external address bus are used; the upper three
bits are undefined. Two instructions were added to the core
ADSP-2100 Family instruction set to read from and write to I/O
memory space. The I/O space also has four dedicated three-bit
wait state registers, IOWAIT0-3, which specify up to seven wait
states to be automatically generated for each of four regions.
The wait states act on address ranges as shown in Table IV.
Table V.
Table IV.
Address Range
Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
BTYPE
Internal
Memory Space
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
Composite Memory Select (CMS)
The ADSP-2181/ADSP-2183 has a programmable memory
select signal that is useful for generating memory select signals
for memories mapped to more than one space. The CMS signal
is generated to have the same timing as each of the individual
memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory, and use either DMS or PMS as the additional
address bit.
The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
MMAP, PMOVLAY or DMOVLAY.
–8–
REV. 0
ADSP-2181/ADSP-2183
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses.
Table VI. Boot Summary Table
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
Internal Memory DMA Port (IDMA Port)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2181/ADSP-2183. The
port is used to access the on-chip program memory and data
memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot be used, however, to write to the
DSP’s memory-mapped control registers.
BMODE
Booting Method
0
0
BDMA feature is used in default mode
to load the first 32 program memory
words from the byte memory space.
Program execution is held off until all
32 words have been loaded.
0
1
IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program
memory location 0 is written to.
1
X
Bootstrap features disabled. Program
execution immediately starts from
location 0.
BDMA interface is set up during reset to the following defaults
when BDMA booting is specified: the BDIR, BMPAGE, BIAD,
and BEAD registers are set to 0, the BTYPE register is set to 0
to specify program memory 24 bit words, and the BWCOUNT
register is set to 32. This causes 32 words of on-chip program
memory to be loaded from byte memory. These 32 words are
used to set up the BDMA to load in the remaining program
code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip
program memory. Execution then begins at address 0.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP2181/ADSP-2183 is operating at full speed.
The DSP memory address is latched and then is automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for
each memory access.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14bit address and 1-bit destination type can be driven onto the bus
by an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
IDMA Port Booting
The ADSP-2181/ADSP-2183 can also boot programs through
its Internal DMA port. If BMODE = 1 and MMAP = 0, the
ADSP-2181/ADSP-2183 boots from the IDMA port. IDMA
feature can load as much on-chip memory as desired. Program
execution is held off until on-chip program memory location 0 is
written to.
Once the address is stored, data can then be either read from, or
written to, the ADSP-2181/ADSP-2183’s on-chip memory. Asserting the select line (IS) and the appropriate read or write line
(IRD and IWR respectively) signals the ADSP-2181/ADSP2183 that a particular transaction is required. In either case,
there is a one-processor-cycle delay for synchronization. The
memory access consumes one additional processor cycle.
The ADSP-2100 Family development software (Revision 5.02
and later) can generate IDMA compatible boot code.
Bus Request & Bus Grant
The ADSP-2181/ADSP-2183 can relinquish control of the data
and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR)
signal. If the ADSP-2181/ADSP-2183 is not performing an external memory access, then it responds to the active BR input in
the following processor cycle by:
• three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
• asserting the bus grant (BG) signal, and
• halting program execution.
Once an access has occurred, the latched address is automatically incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Bootstrap Loading (Booting)
The ADSP-2181/ADSP-2183 has two mechanisms to allow automatic loading of the on-chip program memory after reset. The
method for booting after reset is controlled by the MMAP and
BMODE pins as shown in Table VI.
If Go Mode is enabled, the ADSP-2181/ADSP-2183 will not
halt program execution until it encounters an instruction that
requires an external memory access.
BDMA Booting
When the BMODE and MMAP pins specify BDMA booting
(MMAP = 0, BMODE = 0), the ADSP-2181/ADSP-2183 initiates a BDMA boot sequence when reset is released. The
REV. 0
MMAP
–9–
ADSP-2181/ADSP-2183
If the ADSP-2181/ADSP-2183 is performing an external
memory access when the external device asserts the BR signal,
then it will not three-state the memory interfaces or assert the
BG signal until the processor cycle after the access completes.
The instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses.
INSTRUCTION SET DESCRIPTION
The ADSP-2181/ADSP-2183 assembly language instruction set
has an algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program execution from the point where it stopped.
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
The BGH pin is asserted when the ADSP-2181/ADSP-2183 is
ready to execute an instruction but is stopped because the external bus is already granted to another device. The other device
can release the bus by deasserting bus request. Once the bus is
released, the ADSP-2181/ADSP-2183 deasserts BG and BGH
and executes the external memory access.
• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible
with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP2181/ADSP-2183’s interrupt vector and reset vector map.
Flag I/O Pins
The ADSP-2181/ADSP-2183 has eight general purpose programmable input/output flag pins. They are controlled by two
memory mapped registers. The PFTYPE register determines the
direction, 1 = output and 0 = input. The PFDATA register is
used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the ADSP2181/ADSP-2183’s clock. Bits that are programmed as outputs
will read the value being output. The PF pins default to input
during reset.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
I/O Space Instructions
The instructions used to access the ADSP-2181/ADSP-2183’s
I/O memory space are as follows:
Syntax:
In addition to the programmable flags, the ADSP-2181/ADSP2183 has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0,
FL1, and FL2. FL0-FL2 are dedicated output flags. FLAG_IN
and FLAG_OUT are available as an alternate configuration of
SPORT1.
IO(addr) = dreg
dreg = IO(addr);
where addr is an address value between 0 and 2047 and dreg is
any of the 16 data registers.
Examples:
BIASED ROUNDING
IO(23) = AR0;
AR1 = IO(17);
A mode is available on the ADSP-2181/ADSP-2183 to allow
biased rounding in addition to the normal unbiased rounding.
When the BIASRND bit is set to 0, the normal unbiased rounding operations occur. When the BIASRND bit is set to 1, biased
rounding occurs instead of the normal unbiased rounding.
When operating in biased rounding mode all rounding operations with MR0 set to 0x8000 will round up, rather than only
rounding odd MR1 values up. For example:
MR value before RND biased RND result unbiased RND result
00-0000-8000
00-0001-8000
00-0000-8000
00-0001-8000
00-0002-8000
00-0002-8000
00-0000-8001
00-0001-8001
00-0001-8001
00-0001-8001
00-0002-8001
00-0002-8001
00-0000-7FFF
00-0000-7FFF
00-0000-7FFF
00-0001-7FFF
00-0001-7FFF
00-0001-7FFF
Description: The I/O space read and write instructions move
data between the data registers and the I/O
memory space.
This mode only has an effect when the MR0 register contains
0x8000; all other rounding operation work normally. This mode
allows more efficient implementation of bit-specified algorithms
that use biased rounding, for example the GSM speech compression routines. Unbiased rounding is preferred for most
algorithms.
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
EE
Note: BIASRND bit is bit 12 of the SPORT0 Autobuffer
Control register.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2181/ADSP-2183 has on-chip emulation support and
an ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14pin plug. See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products.
The ICE-Port interface consists of the following ADSP-2181/
ADSP-2183 pins:
–10–
REV. 0
ADSP-2181/ADSP-2183
These ADSP-2181/ADSP-2183 pins must be connected only to
the EZ-ICE connector in the target system. These pins have no
function except during emulation, and do not require pull-up or
pull-down resistors. The traces for these signals between the
ADSP-2181/ADSP-2183 and the connector must be kept as
short as possible, no longer that 3 inches.
The following pins are also used by the EZ-ICE:
BR
BG
RESET
GND
The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2181/ADSP-2183 in the target system. This
causes the processor to use its ERESET, EBR, and EBG pins
instead of the RESET, BR, and BG pins. The BG output is
three-stated. These signals do not need to be jumper-isolated in
your system.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
1
2
3
4
BG
EBG
BR
5
6
7
×
8
9
10
EBR
KEY (NO PIN)
EINT
ELIN
ELOUT
ECLK
11
13
Restriction: All memory strobe signals on the ADSP-2181/
ADSP-2183 (RD, WR, PMS, DMS, BMS, CMS, and IOMS)
used in your target system must have 10 kΩ pull-up resistors
connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to
guarantee their state during prolonged three-state conditions
resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not
being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced
by the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
ERESET
• EZ-ICE emulation ignores RESET and BR when singlestepping.
TOP VIEW
Figure 7. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie, and Samtec.
REV. 0
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
• EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal.
14
RESET
PM, DM, BM, IOM, & CM
EMS
12
EE
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines
listed below.
Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing requirements within published limits.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
GND
Target Memory Interface
• EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
–11–
ADSP-2181–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
B Grade
Min
Max
Min
Max
Unit
4.5
0
5.5
+70
4.5
–40
5.5
+85
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
1, 2
Hi-Level Input Voltage
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
IDD
Supply Current (Idle)9, 10
Supply Current (Dynamic)10, 11
CI
Input Pin Capacitance3, 6, 13
CO
Output Pin Capacitance6, 7, 13, 14
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max,
VIN = VDD max8
@ VDD = max,
VIN = 0 V8
@ VDD = max
@ VDD = max
tCK = 30 ns12
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
2.0
2.2
K/B Grades
Max
0.8
Unit
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
16.5
µA
mA
100
mA
8
pF
8
pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.
2
Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.
3
Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0–A13, DT0, DT1, CLKOUT, FL2-0.
5
Although specified for TTL outputs, all ADSP-2181 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD0–IAD15, PF0–PF7.
8
0 V on BR, CLKIN Active (to force three-state condition).
9
Idle refers to ADSP-2181 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
Current reflects device operating with no output loads.
11
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
12
VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.
13
Applies to TQFP and PQFP package types.
14
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–12–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2181
ABSOLUTE MAXIMUM RATINGS *
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C
Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280°C
*
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
The ADSP-2181 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-2181 features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2181 has been classified as
a Class 2 device.
WARNING!
ESD SENSITIVE DEVICE
Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.
ADSP-2181 TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
MEMORY TIMING SPECIFICATIONS
The table below shows common memory device specifications
and the corresponding ADSP-2181 timing parameters, for your
convenience.
Memory
Device
Specification
ADSP-2181 Timing
Timing
Parameter
Parameter Definition
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.
Address Setup to
tASW
Write Start
Address Setup to
tAW
Write End
Address Hold Time tWRA
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Data Hold Time
tDH
OE to Data Valid
tRDD
Address Access Time tAA
Data Setup Time
tDW
A0–A13, xMS Setup before
WR Low
A0–A13, xMS Setup before
WR Deasserted
A0–A13, xMS Hold after
WR Deasserted
Data Setup before WR
High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data Valid
xMS = PMS, DMS, BMS, CMS, IOMS
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5tCKI. The ADSP-2181 uses an input clock
with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns processor cycle (equivalent to 33 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (30 ns) – 7 ns = 8 ns
REV. 0
–13–
ADSP-2181/ADSP-2183
(C × VDD2 × f ) is calculated for each output:
ADSP-2181
# of
Pins × C
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
Address, DMS
Data Output, WR
RD
CLKOUT
×f
×5 V
× 52 V
× 52 V
× 52 V
× 33.3 MHz
× 16.67 MHz
× 16.67 MHz
× 33.3 MHz
2
= 66.6 mW
= 37.5 mW
= 4.2 mW
= 8.3 mW
116.6 mW
Total power dissipation for this example is PINT + 116.6 mW.
θJA
θJC
θCA
TQFP
PQFP
50°C/W
41°C/W
2°C/W
10°C/W
48°C/W
31°C/W
2181 POWER, INTERNAL
570
550
VDD = 5.5V
530
POWER (PINT) – mW
Package
1000
VDD = 5.5V
CURRENT (LOG SCALE) – µA
× 10 pF
× 10 pF
× 10 pF
× 10 pF
8
9
1
1
× VDD2
VDD = 5.0V
VDD = 4.5V
510
480
450
VDD = 5.0V
420
390
425mW
365mW
360
330
100
550mW
490mW
300
VDD = 4.5V
330mW
275mW
270
240
28
29
10
30
31
32
1/tCK – MHz
33
34
POWER, IDLE1, 2
95
90
VDD = 5.5V
0
–5
25
55
POWER (PIDLE) – mW
85
85
TEMPERATURE – °C
NOTES:
1. REFLECTS ADSP-2181 OPERATION IN LOWEST POWER MODE.
(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY
USER'S MANUAL FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
80
75
70
75mW
VDD = 5.0V
70mW
65
60
55
60mW
VDD = 4.5V
54mW
50
Figure 8. Power-Down Supply Current (Typical)
45
40
28
POWER DISSIPATION
90mW
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
70
C = load capacitance, f = output switching frequency.
65
47mW
29
30
31
32
1/fCK – MHz
33
34
POWER, IDLE n MODES3
POWER (PIDLEn) – mW
75
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
IDLE;
70mW
60
55
60mW
50
45
40
35
35mW
IDLE (16)
IDLE (128)
31mW
30
25
28
33mW
29mW
29
30
31
32
1/fCK – MHz
33
34
VALID FOR ALL TEMPERATURE GRADES.
1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2IDLE REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
The application operates at VDD = 5.0 V and tCK = 30 ns.
3TYPICAL
POWER DISSIPATION AT 5.0V VDD DURING EXECUTION OF IDLE n
INSTRUCTION (CLOCK FREQUENCY REDUCTION).
DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
Total Power Dissipation = PINT + (C × VDD2 × f )
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 9).
4I
Figure 9. Power vs. Frequency
–14–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2181
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the following equation:
CAPACITIVE LOADING
Figures 10 and 11 show the capacitive loading characteristics of
the ADSP-2181.
t DECAY =
from which
30
T = +85°C
VDD = 4.5V
t DIS = t MEASURED – t DECAY
25
RISE TIME (0.4V–2.4V) – ns
CL • 0.5V
iL
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
20
15
INPUT
3.0V
1.5V
0.0V
OUTPUT
2.0V
1.5V
0.3V
10
5
0
0
100
50
150
CL – pF
200
250
300
Figure 12. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
Figure 10. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
18
VALID OUTPUT DELAY OR HOLD – ns
16
14
12
10
8
Output Enable Time
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.
6
4
REFERENCE
SIGNAL
2
tMEASURED
NOMINAL
tENA
–2
VOH
(MEASURED)
–4
–6
0
50
100
150
200
tDIS
VOH
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
OUTPUT
250
CL – pF
VOL
(MEASURED)
Figure 11. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
VOL
(MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
TEST CONDITIONS
Output Disable Time
Figure 13. Output Enable/Disable
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
IOL
TO
OUTPUT
PIN
+1.5V
50pF
IOH
Figure 14. Equivalent Device Loading for AC Measurements (Including All Fixtures)
REV. 0
–15–
ADSP-2181/ADSP-2183
ADSP-2183–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
B Grade
Min
Max
Min
Max
Unit
3.0
0
3.6
+70
3.0
–40
3.6
+85
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
Hi-Level Input Voltage1, 2
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
IDD
Supply Current (Idle)9, 10
Supply Current (Dynamic)10, 11
CI
Input Pin Capacitance3, 6, 13
CO
Output Pin Capacitance6, 7, 13, 14
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max,
VIN = VDD max8
@ VDD = max,
VIN = 0 V8
@ VDD = max, tCK = 34.7 ns
@ VDD = max
tCK = 34.7 ns12
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
2.0
2.2
K/B Grades
Max
0.4
Unit
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
9
µA
mA
54
mA
8
pF
8
pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.
2
Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.
3
Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0-A13, DT0, DT1, CLKOUT, FL2-0.
5
Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD0–IAD15, PF0–PF7.
8
0 V on BR, CLKIN Active (to force three-state condition).
9
Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
Current reflects device operating with no output loads.
11
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
12
VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.
13
Applies to TQFP and PQFP package types.
14
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–16–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2183
ABSOLUTE MAXIMUM RATINGS *
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C
*
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
The ADSP-2183 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-2183 features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2183 has been classified as
a Class 2 device.
WARNING!
ESD SENSITIVE DEVICE
Proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to
the destination before devices are removed.
ADSP-2183 TIMING PARAMETERS
GENERAL NOTES
MEMORY TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
The table below shows common memory device specifications
and the corresponding ADSP-2183 timing parameters, for your
convenience.
TIMING NOTES
Switching characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to
the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Memory
Device
Specification
ADSP-2183 Timing
Timing
Parameter
Parameter Definition
Address Setup to
tASW
Write Start
Address Setup to
tAW
Write End
Address Hold Time tWRA
Data Setup Time
tDW
Data Hold Time
tDH
OE to Data Valid
tRDD
Address Access Time tAA
A0–A13, xMS Setup before
WR Low
A0–A13, xMS Setup before
WR Deasserted
A0–A13, xMS Hold after
WR Deasserted
Data Setup before WR
High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data Valid
xMS = PMS, DMS, BMS, CMS, IOMS
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5tCKI. The ADSP-2183 uses an input clock
with a frequency equal to half the instruction rate: a 14.4 MHz
input clock (which is equivalent to 57.6 ns) yields a 34.7 ns processor cycle (equivalent to 28.8 MHz). tCK values within the
range of 0.5tCKI period should be substituted for all relevant
timing parameters to obtain the specification value.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (34.7 ns) – 7 ns = 11.7 ns
REV. 0
–17–
ADSP-2181/ADSP-2183
(C × VDD2 × f ) is calculated for each output:
ADSP-2183
ENVIRONMENTAL CONDITIONS
# of
Pins × C
Ambient Temperature Rating:
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
Package
θJA
Address, DMS
Data Output, WR
RD
CLKOUT
× 10 pF
× 10 pF
× 10 pF
× 10 pF
8
9
1
1
× VDD2
×f
× 3.32 V
× 3.32 V
× 3.32 V
× 3.32 V
× 33.3 MHz
× 16.67 MHz
× 16.67 MHz
× 33.3 MHz
= 29.0 mW
= 16.3 mW
= 1.8 mW
= 3.6 mW
50.7 mW
Total power dissipation for this example is PINT + 50.7 mW.
θJC
θCA
POWER, INTERNAL1,4
200
50°C/W
41°C/W
2°C/W
10°C/W
48°C/W
31°C/W
CURRENT (LOG SCALE) – µA
195mW
180
1000
VDD = 3.6V
VDD = 3.3V
VDD = 3.0V
100
VDD = 3.6V
190
POWER (PINT) – mW
TQFP
PQFP
175mW
170
160mW
160
VDD = 3.3V
150
140mW
140
125mW
130
VDD = 3.0V
120
110mW
110
100
22
23
24
10
25
26 27 28
1/tCK – MHz
29
30
31
POWER, IDLE1,2
34
32
VDD = 3.6V
33mW
0
–5
25
55
TEMPERATURE – °C
POWER (PIDLE) – mW
30
85
NOTES:
1. REFLECTS ADSP-2183 OPERATION IN LOWEST POWER MODE.
(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY
USER'S MANUAL FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
28
27mW
26
VDD = 3.3V
27mW
24
22
21mW
20
VDD = 3.0V
21mW
18
17mW
16
14
Figure 15. Power-Down Supply Current (Typical)
12
10
22
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
23
24
25
26 27 28
1/tCK – MHz
29
30
31
POWER, IDLE n MODES3
30
28
IDLE
26
POWER (PIDLEn) – mW
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
27mW
24
22
20
21mW
18
16
14
12mW
13mW
IDLE
(16)
12mW
IDLE
(128)
12
10
11mW
8
6
22 23 24 25 26 27 28 29 30 31
1/tCK – MHz
VALID FOR ALL TEMPERATURE GRADES.
1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2IDLE REFERS TO ADSP-2183 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
The application operates at VDD = 3.3 V and tCK = 34.7 ns.
3TYPICAL
POWER DISSIPATION AT 3.3V VDD DURING EXECUTION OF IDLE n
INSTRUCTION (CLOCK FREQUENCY REDUCTION).
DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
Total Power Dissipation = PINT + (C × VDD × f )
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 16).
2
4I
Figure 16. Power vs. Frequency
–18–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2183
from which
t DIS = t MEASURED – t DECAY
CAPACITIVE LOADING
Figures 17 and 18 show the capacitive loading characteristics of
the ADSP-2183.
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
30
T = +85°C
VDD = 3.0V
INPUT
3.0V
1.5V
0.0V
OUTPUT
2.0V
1.5V
0.3V
RISE TIME (0.4V – 2.4V) – ns
25
20
15
Figure 19. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
10
5
0
Output Enable Time
0
25
50
75
100
CL – pF
125
150
175
200
Figure 17. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
18
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.
16
VALID OUTPUT DELAY
OR HOLD – ns
14
REFERENCE
SIGNAL
12
tMEASURED
10
tENA
8
VOH
(MEASURED)
6
4
tDIS
VOH
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
OUTPUT
2
VOL
(MEASURED)
NOMINAL
–2
VOL
(MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
–4
–6
0
25
50
75
100
CL – pF
125
150
175
200
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 18. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
Figure 20. Output Enable/Disable
IOL
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the following equation:
t DECAY =
REV. 0
CL • 0.5V
iL
–19–
TO
OUTPUT
PIN
+1.5V
50pF
IOH
Figure 21. Equivalent Device Loading for AC Measurements (Including All Fixtures)
ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Min
Max
Unit
60
20
20
150
ns
ns
ns
Clock Signals and Reset
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5tCK – 7
0.5tCK – 7
0
20
ns
ns
ns
Control Signals
Timing Requirements:
tRSP
RESET Width Low
5tCK1
ns
ADSP-2183
28.8 MHz
Parameter
Min
Max
Unit
69.4
20
20
150
ns
ns
ns
Clock Signals and Reset
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5tCK – 7
0.5tCK – 7
0
20
ns
ns
ns
Control Signals
Timing Requirements:
tRSP
RESET Width Low
5tCK1
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 22. Clock Signals
–20–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements:
tIFS
tIFH
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25tCK + 15
0.25tCK
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
ns
ns
0.5tCK – 7
0.25tCK + 5
ns
ns
Max
Unit
ADSP-2183
28.8 MHz
Parameter
Min
Interrupts and Flag
Timing Requirements:
tIFS
tIFH
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25tCK + 15
0.25tCK
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
ns
ns
0.5tCK – 7
0.25tCK + 6
ns
ns
NOTES
1
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out 4.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 23. Interrupts and Flags
REV. 0
–21–
ADSP-2181/ADSP-2183
ADSP-2181/ADSP-2183
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirements:
tBH
tBS
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
0.25tCK + 2
0.25tCK + 17
Switching Characteristics:
tSD
CLKOUT High to xMS,
RD, WR Disable
tSDB
xMS, RD, WR
Disable to BG Low
tSE
BG High to xMS,
RD, WR Enable
tSEC
xMS, RD, WR
Enable to CLKOUT High
tSDBH
xMS, RD, WR
Disable to BGH Low2
tSEH
BGH High to xMS,
RD, WR Enable2
ns
ns
0.25tCK + 10
ns
0
ns
0
ns
0.25tCK – 7
ns
0
ns
0
ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
tSD
tSEC
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 24. Bus Request–Bus Grant
–22–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Min
Max
Unit
0.5tCK – 9 + w
0.75tCK – 10.5 + w
ns
ns
ns
Memory Read
Timing Requirements:
tRDD
RD Low to Data Valid
tAA
A0-A13, xMS to Data Valid
tRDH
Data Hold from RD High
0
Switching Characteristics:
RD Pulse Width
tRP
tCRD
CLKOUT High to RD Low
tASR
A0-A13, xMS Setup before RD Low
tRDA
A0-A13, xMS Hold after RD Deasserted
tRWR
RD High to RD or WR Low
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 6
0.25tCK – 3
0.5tCK – 5
0.25tCK + 7
ns
ns
ns
ns
ns
ADSP-2183
28.8 MHz
Parameter
Min
Max
Unit
0.5tCK – 9 + w
0.75tCK – 12.5 + w
ns
ns
ns
Memory Read
Timing Requirements:
tRDD
RD Low to Data Valid
tAA
A0-A13, xMS to Data Valid
tRDH
Data Hold from RD High
0
Switching Characteristics:
tRP
RD Pulse Width
tCRD
CLKOUT High to RD Low
tASR
A0-A13, xMS Setup before RD Low
tRDA
A0-A13, xMS Hold after RD Deasserted
tRWR
RD High to RD or WR Low
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 6
0.25tCK – 3
0.5tCK – 5
0.25tCK + 7
w = wait states x t CK
xMS = PMS, DMS, CMS, IOMS, BMS
CLKOUT
A0 – A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D
tAA
tRDD
WR
Figure 25. Memory Read
REV. 0
–23–
tRDH
ns
ns
ns
ns
ns
ADSP-2181/ADSP-2183
ADSP-2181/ADSP-2183
Parameter
Min
Max
Unit
Memory Write
Switching Characteristics:
tDW
Data Setup before WR High
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE
WR Low to Data Enabled
tASW
A0-A13, xMS Setup before WR Low
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
tAW
A0-A13, xMS, Setup before WR Deasserted
tWRA
A0-A13, xMS Hold after WR Deasserted
tWWR
WR High to RD or WR Low
0.5tCK – 7+ w
0.25tCK – 2
0.5tCK – 5 + w
0
0.25tCK – 6
0.25tCK – 7
0.25tCK – 5
0.75tCK – 9 + w
0.25tCK – 3
0.5tCK – 5
0.25 tCK + 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w = wait states x t CK
xMS = PMS, DMS, CMS, IOMS, BMS
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
tDDR
D
tDW
tWDE
RD
Figure 26. Memory Write
–24–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2181/ADSP-2183
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
tSCK
SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH
DR/TFS/RFS Hold after SCLK Low
tSCP
SCLKIN Width
50
4
7
20
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
tSCDE
SCLK High to DT Enable
tSCDV
SCLK High to DT Valid
tRH
TFS/RFSOUT Hold after SCLK High
tRD
TFS/RFSOUT Delay from SCLK High
tSCDH
DT Hold after SCLK High
tTDE
TFS (Alt) to DT Enable
tTDV
TFS (Alt) to DT Valid
tSCDD
SCLK High to DT Disable
tRDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
0.25tCK
0
0.25tCK + 10
15
0
15
0
0
14
15
15
tCC
tSCK
SCLK
tSCP
tSCS
tSCP
tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
ALTERNATE
FRAME MODE
tRDV
RFS
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 27. Serial Ports
REV. 0
ns
ns
ns
ns
–25–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2181/ADSP-2183
ADSP-2181/ADSP-2183
Parameter
Min
Max
Unit
IDMA Address Latch
Timing Requirements:
tIALP
Duration of Address Latch1, 3
tIASU
IAD15–0 Address Setup before Address Latch End3
tIAH
IAD15–0 Address Hold after Address Latch End3
tIKA
IACK Low before Start of Address Latch1
tIALS
Start of Write or Read after Address Latch End2, 3
10
5
2
0
3
ns
ns
ns
ns
ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
Start of Write or Read = IS Low and IWR Low or IRD Low.
3
End of Address Latch = IS High or IAL Low.
IACK
tIKA
IAL
tIALP
IS
tIASU
tIAH
IAD 15–0
tIALS
IRD OR
IWR
Figure 28. IDMA Address Latch
–26–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Min
Max
Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
tIWP
Duration of Write1, 2
tIDSU
IAD15–0 Data Setup before End of Write2, 3, 4
tIDH
IAD15–0 Data Hold after End of Write2, 3, 4
0
15
5
2
ns
ns
ns
ns
Switching Characteristics:
tIKHW
Start of Write to IACK High
15
ns
Max
Unit
ADSP-2183
28.8 MHz
Parameter
Min
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
tIWP
Duration of Write1, 2
tIDSU
IAD15–0 Data Setup before End of Write2, 3, 4
tIDH
IAD15–0 Data Hold after End of Write2, 3, 4
0
15
5
2
Switching Characteristics:
tIKHW
Start of Write to IACK High
17
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
IAD 15–0
tIDH
DATA
Figure 29. IDMA Write, Short Write Cycle
REV. 0
ns
ns
ns
ns
–27–
ns
ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Min
Max
Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
tIKSU
IAD15–0 Data Setup before IACK Low2, 3
tIKH
IAD15–0 Data Hold after IACK Low2, 3
0
0.5tCK + 10
2
Switching Characteristics:
Start of Write to IACK Low4
tIKLW
tIKHW
Start of Write to IACK High
ns
ns
ns
1.5tCK
15
ns
ns
Max
Unit
ADSP-2183
28.8 MHz
Parameter
Min
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
tIKSU
IAD15–0 Data Setup before IACK Low2, 3
tIKH
IAD15–0 Data Hold after IACK Low2, 3
0
0.5tCK + 10
2
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW
Start of Write to IACK High
ns
ns
ns
1.5tCK
17
ns
ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD 15–0
Figure 30. IDMA Write, Long Write Cycle
–28–
REV. 0
ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
tIRP
Duration of Read
0
15
Switching Characteristics:
IACK High after Start of Read1
tIKHR
tIKDS
IAD15–0 Data Setup before IACK Low
tIKDH
IAD15–0 Data Hold after End of Read2
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
tIRDH1
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
tIRDH2
IAD15–0 Previous Data Hold after Start of Read (PM2)4
ns
ns
15
0.5tCK –10
0
10
0
15
2tCK –5
tCK–5
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2183
28.8 MHz
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
tIRP
Duration of Read
0
15
Switching Characteristics:
tIKHR
IACK High after Start of Read1
tIKDS
IAD15–0 Data Setup before IACK Low
tIKDH
IAD15–0 Data Hold after End of Read2
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
tIRDH1
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
tIRDH2
IAD15–0 Previous Data Hold after Start of Read (PM2)4
ns
ns
17
0.5tCK –10
0
10
0
15
2tCK –5
tCK–5
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRP
IRD
tIKDS
tIRDE
PREVIOUS
DATA
IAD 15–0
tIKDH
READ
DATA
tIRDV
tIKDD
tIRDH
Figure 31. IDMA Read, Long Read Cycle
REV. 0
–29–
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
tIRP
Duration of Read
0
15
Switching Characteristics:
tIKHR
IACK High after Start of Read1
tIKDH
IAD15–0 Data Hold after End of Read2
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
ns
ns
15
0
10
0
15
ns
ns
ns
ns
ns
ADSP-2183
Parameter
28.8 MHz
Min
Max
Unit
0
15
ns
ns
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
tIRP
Duration of Read
Switching Characteristics:
tIKHR
IACK High after Start of Read1
tIKDH
IAD15–0 Data Hold after End of Read2
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
17
0
10
0
15
ns
ns
ns
ns
ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD 15–0
tIRDV
tIKDD
Figure 32. IDMA Read, Short Read Cycle
–30–
REV. 0
ADSP-2181/ADSP-2183
IS
GND
PF4
PF5
PF6
PF7
IAD0
IAD1
IAD2
IAD3
IAD4
IAD5
GND
VDD
IAD6
IAD7
IAD8
IAD9
IAD10
IAD11
IAD12
IAD13
IAD14
IAD15
IRD
IWR
128-Lead TQFP Package Pinout
128
103
102
1
IAL
PF3
PF2
PF1
PF0
WR
RD
IOMS
BMS
DMS
CMS
GND
VDD
PMS
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
GND
CLKOUT
GND
VDD
A8
A9
A10
A11
A12
A13
IRQE
MMAP
PWD
IRQ2
TOP VIEW
(PINS DOWN)
38
65
64
BMODE
PWDACK
IACK
BGH
VDD
GND
IRQL0
IRQL1
FL0
FL1
FL2
DT0
TFS0
RFS0
DR0
SCLK0
DT1/F0
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/FI
SCLK1
ERESET
RESET
EMS
EE
39
REV. 0
GND
D23
D22
D21
D20
D19
D18
D17
D16
D15
GND
VDD
GND
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
GND
D4
D3
D2
D1
D0
VDD
BG
EBG
BR
EBR
EINT
ELIN
ELOUT
ECLK
–31–
ADSP-2181/ADSP-2183
TQFP Pin Configurations
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IAL
PF3
PF2
PF1
PF0
WR
RD
IOMS
BMS
DMS
CMS
GND
VDD
PMS
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
GND
CLKOUT
GND
VDD
A8
A9
A10
A11
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A12
A13
IRQE
MMAP
PWD
IRQ2
BMODE
PWDACK
IACK
BGH
VDD
GND
IRQL0
IRQL1
FL0
FL1
FL2
DT0
TFS0
RFS0
DR0
SCLK0
DT1/F0
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/FI
SCLK1
ERESET
RESET
EMS
EE
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
ECLK
ELOUT
ELIN
EINT
EBR
BR
EBG
BG
VDD
D0
D1
D2
D3
D4
GND
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
GND
VDD
GND
D15
D16
D17
D18
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
D19
D20
D21
D22
D23
GND
IWR
IRD
IAD15
IAD14
IAD13
IAD12
IAD11
IAD10
IAD9
IAD8
IAD7
IAD6
VDD
GND
IAD5
IAD4
IAD3
IAD2
IAD1
IAD0
PF7
PF6
PF5
PF4
GND
IS
–32–
REV. 0
ADSP-2181/ADSP-2183
OUTLINE DIMENSIONS
128-Lead Metric Thin Plastic Quad Flatpack (TQFP)
D
D1
D3
A
L
103
102
128
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
65
64
38
D
E3 E1 E
39
A1
A2
SYMBOL
B
MILLIMETERS
MIN
TYP
MAX
A
MIN
1.60
A1
0.05
A2
1.30
D
D1
INCHES
TYP
MAX
0.063
0.15
0.002
1.40
1.50
0.051
0.055
0.059
15.75
16.00
16.25
0.620
0.630
0.640
13.90
14.00
14.10
0.547
0.551
0.555
12.50
12.58
0.492
0.495
D3
0.006
E
21.75
22.00
22.25
0.856
0.866
0.876
E1
19.90
20.00
20.10
0.783
0.787
0.792
18.50
18.58
0.728
0.731
E3
L
0.45
0.60
0.75
0.018
0.024
0.030
e
0.42
0.50
0.58
0.017
0.019
0.023
B
0.17
0.22
0.27
0.007
0.009
0.011
D
REV. 0
e
0.10
–33–
0.004
ADSP-2181/ADSP-2183
PF1
PF2
PF3
IAL
IS
GND
PF4
PF5
PF6
PF7
IAD0
IAD1
IAD2
IAD3
IAD4
IAD5
GND
VDD
IAD6
IAD7
IAD8
IAD9
IAD10
IAD11
IAD12
IAD13
IAD14
IAD15
IRD
IWR
GND
D23
128-Lead PQFP Package Pinout
128
97
96
1
PF0
WR
RD
IOMS
BMS
DMS
CMS
GND
VDD
PMS
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
GND
CLKOUT
GND
VDD
A8
A9
A10
A11
A12
A13
IRQE
MMAP
D22
D21
D20
D19
D18
D17
D16
D15
GND
VDD
GND
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
GND
D4
D3
D2
D1
D0
VDD
128L PQFP
(28mm x 28mm)
TOP VIEW
(PINS DOWN)
BG
EBG
BR
EBR
32
65
33
PWD
IRQ2
BMODE
PWDACK
IACK
BGH
VDD
GND
IRQL0
IRQL1
FL0
FL1
FL2
DT0
TFS0
RFS0
DR0
SCLK0
DT1/F0
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/FI
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
64
–34–
REV. 0
ADSP-2181/ADSP-2183
PQFP Pin Configurations
PQFP
Number
Pin
Name
PQFP
Number
Pin
Name
PQFP
Number
Pin
Name
PQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PF0
WR
RD
IOMS
BMS
DMS
CMS
GND
VDD
PMS
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
GND
CLKOUT
GND
VDD
A8
A9
A10
A11
A12
A13
IRQE
MMAP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PWD
IRQ2
BMODE
PWDACK
IACK
BGH
VDD
GND
IRQL0
IRQL1
FL0
FL1
FL2
DT0
TFS0
RFS0
DR0
SCLK0
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/FI
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
EBR
BR
EBG
BG
VDD
D0
D1
D2
D3
D4
GND
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
GND
VDD
GND
D15
D16
D17
D18
D19
D20
D21
D22
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
D23
GND
IWR
IRD
IAD15
IAD14
IAD13
IAD12
IAD11
IAD10
IAD9
IAD8
IAD7
IAD6
VDD
GND
IAD5
IAD4
IAD3
IAD2
IAD1
IAD0
PF7
PF6
PF5
PF4
GND
IS
IAL
PF3
PF2
PF1
REV. 0
–35–
ADSP-2181/ADSP-2183
OUTLINE DIMENSIONS
128-Lead Metric Plastic Quad Flatpack (PQFP)
D
D1
D3
A
L
128
1
SEATING
PLANE
97
96
TOP VIEW
(PINS DOWN)
E3 E1 E
65
64
D
32
33
A1
A2
SYMBOL
B
MILLIMETERS
MIN
TYP
MAX
A
e
MIN
INCHES
TYP
MAX
4.07
0.160
0.25
A2
3.17
3.49
3.67
0.125
0.137
0.144
D, E
30.95
31.20
31.45
1.219
1.228
1.238
D1, E 1
27.90
28.00
28.10
1.098
1.102
1.106
D3, E 3
24.73
24.80
24.87
0.974
0.976
0.979
L
0.65
0.88
1.03
0.031
0.035
0.041
e
0.73
0.80
0.87
0.029
0.031
0.034
B
0.30
0.35
0.45
0.012
0.014
0.018
D
A1
0.010
0.10
–36–
0.004
REV. 0
ADSP-2181/ADSP-2183
ORDERING GUIDE
Part Number
Ambient
Temperature
Range
Instruction
Rate
(MHz)
Package
Description
Package
Option*
ADSP-2181KST-115
ADSP-2181BST-115
ADSP-2181KS-115
ADSP-2181BS-115
ADSP-2181KST-133
ADSP-2181BST-133
ADSP-2181KS-133
ADSP-2181BS-133
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
28.8
28.8
28.8
28.8
33.3
33.3
33.3
33.3
128-Lead TQFP
128-Lead TQFP
128-Lead PQFP
128-Lead PQFP
128-Lead TQFP
128-Lead TQFP
128-Lead PQFP
128-Lead PQFP
ST-128
ST-128
S-128
S-128
ST-128
ST-128
S-128
S-128
ADSP-2183KST-115
ADSP-2183BST-115
0°C to +70°C
–40°C to +85°C
28.8
28.8
128-Lead TQFP
128-Lead TQFP
ST-128
ST-128
*S = Plastic Quad Flatpack (PQFP), ST = Plastic Thin Quad Flatpack (TQFP).
REV. 0
–37–
–38–
–39–
–40–
PRINTED IN U.S.A.
C2144–16–6/96
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