Apple 9500/180MP Personal Computer Product manual

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MHE2064AT, MHE2043AT

MHF2043AT, MHF2021AT

DISK DRIVE

PRODUCT MANUAL

C141-E057-02EN

FOR SAFE OPERATION

Handling of This Manual

This manual contains important information for using this product. Read thoroughly before using the product. Use this product only after thoroughly reading and understanding especially the section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully.

FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.

IMPORTANT NOTE TO USERS

READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT.

INCORRECT USE OF THE PRODUCT MAY RESULT IN INJURY OR DAMAGE TO

USERS, BYSTANDERS OR PROPERTY.

While FUJITSU has sought to ensure the accuracy of all information in this manual, FUJITSU assumes no liability to any party for any damage caused by any error or omission contained in this manual, its updates or supplements, whether such errors or omissions result from negligence, accident, or any other cause. In addition, FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein; including any liability for incidental or consequential damages arising therefrom.

FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION

CONTAINED HEREIN, WHETHER EXPRESSED, IMPLIED, OR STATUTORY.

FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation.

The contents of this manual may be revised without prior notice.

The contents of this manual shall not be disclosed in any way or reproduced in any media without the express written permission of Fujitsu Limited.

All Rights Reserved, Copyright

FUJITSU LIMITED

1998

C141-E057-01EN

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Revision History

Edition Date

01

02

1998-06-20

1998-09-10

Revised section (*1)

(Added/Deleted/Altered)

Details

(1/1)

*1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.

C141-E057-02EN

This page is intentionally left blank.

Preface

This manual describes the MHE Series and MHF Series, 2.5-inch hard disk drives.

These drives have a built-in controller that is compatible with the ATA interface.

This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.

This manual consists of seven chapters and sections explaining the special terminology and abbreviations used in this manual:

Overview of Manual

CHAPTER 1 Device Overview

This chapter gives an overview of the MHE Series and MHF Series and describes their features.

CHAPTER 2 Device Configuration

This chapter describes the internal configurations of the MHE Series and MHF

Series and the configuration of the systems in which they operate.

CHAPTER 3 Installation Conditions

This chapter describes the external dimensions, installation conditions, and switch settings of the MHE Series and MHF Series.

CHAPTER 4 Theory of Device Operation

This chapter describes the operation theory of the MHE Series and MHF Series.

CHAPTER 5 Interface

This chapter describes the interface specifications of the MHE Series and MHF

Series.

CHAPTER 6 Operations

This chapter describes the operations of the MHE Series and MHF Series.

Terminology

This section explains the special terminology used in this manual.

Abbreviation

This section gives the meanings of the definitions used in this manual.

C141-E057-01EN i

Preface

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.

The following are the alert signals and their meanings:

This indicates a hazarous situation could result in

minor or moderate personal injury if the user does not perform the procedure correctly. This alert signal also indicates that damages to the product or other property, may occur if the user does not perform the procedure correctly.

This indicates information that could help the user use the product more efficiently.

In the text, the alert signal is centered, followed below by the indented message. A wider line space precedes and follows the alert message to show where the alert message begins and ends. The following is an example:

(Example)

Operating Environment

This product is designed to be used in offices or computer rooms.

For details regarding the operating environment of use, refer to the

(Cnnn-Xnnn) and the

(Cnnn-Xnnn).

Attention

Data corruption:

Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

The main alert messages in the text are also listed in the “Important Alert Items.”

Please forward any comments you may have regarding this manual.

To make this manual easier for users to understand, opinions from readers are needed. Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet.

ii C141-E057-01EN

Preface

Liability Exception

“Disk drive defects” refers to defects that involve adjustment, repair, or replacement.

Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

C141-E057-01EN iii

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Important Alert Items

Important Alert Messages

The important alert messages in this manual are as follows:

Task

Normal Operation

A hazardous situation could result in minor or moderate personal

injury if the user does not perform the procedure correctly. Also, damage to the predate or other property, may occur if the user does not perform the procedure correctly.

Alert message

Data corruption:

Avoid mounting the disk near strong magnetic soures such as loud speakers. Ensure that the disk drive is not affected by extrnal magnetic fields.

Stastic:

When handling the device, disconnect the body ground (500 k

or greater). Do not touch the printed circuit board, but hold it by the edges.

Page

3-7

C141-E057-02EN v

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Manual Organization

MHE2064AT, MHE2043AT

MHF2043AT, MHF2021AT

DISK DRIVE

PRODUCT MANUAL

(C141-E057)

<This manual>

• Device Overview

• Device Configuration

• Installation Conditions

• Theory of Device Operation

• Interface

• Operations

MHE2064AT, MHE2054AT

MHF2043AT, MHF2032AT

MHF2021AT

DISK DRIVE

MAINTENANCE MANUAL

(C141-F031)

• Maintenance and Diagnosis

• Removal and Replacement Procedure

C141-E057-02EN vii

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Contents

CHAPTER 1 Device Overview........................................................................ 1-1

1.1

Features 1-2

1.1.1

Functions and performance 1-2

1.1.2

Adaptability 1-2

1.1.3

Interface 1-3

1.2

Device Specifications 1-4

1.2.1

Specifications summary 1-4

1.2.2

Model and product number 1-6

1.3

Power Requirements 1-6

1.4

Environmental Specifications 1-8

1.5

Acoustic Noise 1-9

1.6

Shock and Vibration 1-9

1.7

Reliability 1-10

1.8

Error Rate 1-11

1.9

Media Defects 1-11

CHAPTER 2 Device Configuration................................................................ 2-1

2.1

Device Configuration 2-2

2.2

System Configuration 2-4

2.2.1

ATA interface 2-4

2.2.2

1 drive connection 2-4

2.2.3

2 drives connection 2-4

C141-E057-01EN ix

Contents

CHAPTER 3 Installation Conditions..............................................................3-1

3.1

Dimensions 3-2

3.2

Mounting 3-4

3.3

Cable Connections 3-8

3.3.1

Device connector 3-8

3.3.2

Cable connector specifications 3-9

3.3.3

Device connection 3-9

3.3.4

Power supply connector (CN1) 3-10

3.4

Jumper Settings 3-10

3.4.1

Location of setting jumpers 3-10

3.4.2

Factory default setting 3-11

3.4.3

Master drive-slave drive setting 3-11

3.4.4

CSEL setting 3-12

CHAPTER 4 Theory of Device Operation......................................................4-1

4.1

Outline 4-2

4.2

Subassemblies 4-2

4.2.1

Disk 4-2

4.2.2

Head 4-2

4.2.3

Spindle 4-3

4.2.4

Actuator 4-3

4.2.5

Air filter 4-3

4.3

Circuit Configuration 4-4

4.4

Power-on Sequence 4-6

4.5

Self-calibration 4-7

4.5.1

Self-calibration contents 4-7

4.5.2

Execution timing of self-calibration 4-8

4.5.3

Command processing during self-calibration 4-9

4.6

Read/write Circuit 4-9 x C141-E057-01EN

Contents

4.6.1

Read/write preamplifier (PreAMP) 4-9

4.6.2

Write circuit 4-10

4.6.3

Read circuit 4-12

4.6.4

Digital PLL circuit 4-13

4.7

Servo Control 4-14

4.7.1

Servo control circuit 4-14

4.7.2

Data-surface servo format 4-18

4.7.3

Servo frame format 4-18

4.7.4

Actuator motor control 4-19

4.7.5

Spindle motor control 4-20

CHAPTER 5 Interface ..................................................................................... 5-1

5.1

Physical Interface 5-2

5.1.1

Interface signals 5-2

5.1.2

Signal assignment on the connector 5-3

5.2

Logical Interface 5-6

5.2.1

I/O registers 5-7

5.2.2

Command block registers 5-8

5.2.3

Control block registers 5-13

5.3

Host Commands 5-13

5.3.1

Command code and parameters 5-14

5.3.2

Command descriptions 5-16

5.3.3

Error posting 5-71

5.4

Command Protocol 5-73

5.4.1

Data transferring commands from device to host 5-73

5.4.2

Data transferring commands from host to device 5-75

5.4.3

Commands without data transfer 5-77

5.4.4

Other commands 5-78

5.4.5

DMA data transfer commands 5-78

5.5

Ultra DMA Feature Set 5-80

5.5.1

Overview 5-80

C141-E057-01EN xi

Contents

xii

5.5.2

Phases of operation 5-81

5.5.2.1 Ultra DMA burst initiation phase 5-81

5.5.2.2 Data transfer phase 5-82

5.5.2.3 Ultra DMA burst termination phase 5-82

5.5.3

Ultra DMA data in commands 5-83

5.5.3.1 Initiating an Ultra DMA data in burst 5-83

5.5.3.2 The data in transfer 5-84

5.5.3.3 Pausing an Ultra DMA data in burst 5-84

5.5.3.4 Terminating an Ultra DMA data in burst 5-85

5.5.4

Ultra DMA data out commands 5-88

5.5.4.1 Initiating an Ultra DMA data out burst 5-88

5.5.4.2 The data out transfer 5-88

5.5.4.3 Pausing an Ultra DMA data out burst 5-89

5.5.4.4 Terminating an Ultra DMA data out burst 5-90

5.5.5

Ultra DMA CRC rules 5-92

5.5.6

Series termination required for Ultra DMA 5-94

5.6

Timing 5-95

5.6.1

PIO data transfer 5-95

5.6.2

Single word DMA data transfer 5-97

5.6.3

Multiword DMA data transfer 5-98

5.6.4

Transfer of Ultra DMA data 5-99

5.6.4.1 Starting of Ultra DMA data In Burst 5-99

5.6.4.2 Ultra DMA data burst timing requirements 5-100

5.6.4.3 Sustained Ultra DMA data in burst 5-102

5.6.4.4 Host pausing an Ultra DMA data in burst 5-103

5.6.4.5 Device terminating an Ultra DMA data in burst 5-104

5.6.4.6 Host terminating an Ultra DMA data in burst 5-105

5.6.4.7 Initiating an Ultra DMA data out burst 5-106

5.6.4.8 Sustained Ultra DMA data out burst 5-107

5.6.4.9 Device pausing an Ultra DMA data out burst 5-108

5.6.4.10 Host terminating an Ultra DMA data out burst 5-109

5.6.4.11 Device terminating an Ultra DMA data in burst 5-110

5.6.5

Power-on and reset 5-111

C141-E057-01EN

Contents

CHAPTER 6 Operations ................................................................................. 6-1

Glossary

6.1

Device Response to the Reset 6-2

6.1.1

Response to power-on 6-2

6.1.2

Response to hardware reset 6-4

6.1.3

Response to software reset 6-5

6.1.4

Response to diagnostic command 6-6

6.2

Address Translation 6-7

6.2.1

Default parameters 6-7

6.2.2

Logical address 6-8

6.3

Power Save 6-9

6.3.1

Power save mode 6-9

6.3.2

Power commands 6-11

6.4

Defect Management 6-11

6.4.1

Spare area 6-12

6.4.2

Alternating defective sectors 6-12

6.5

Read-Ahead Cache 6-14

6.5.1

Data buffer configuration 6-14

6.5.2

Caching operation 6-14

6.5.3

Usage of read segment 6-16

6.5.3.1 Mis-hit (no hit) 6-16

6.5.3.2 Sequential read 6-17

6.5.3.3 Full hit (hit all) 6-20

6.5.3.4 Partially hit 6-21

6.6

Write Cache 6-22

................................................................................................. GL-1

Acronyms and Abbreviations ........................................................................ AB-1

Index ...................................................................................................IN-1

C141-E057-01EN xiii

Contents

Illustrations

Figures

xiv

Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-7

Figure 2.1 Disk drive outerview (the MHE Series and MHF Series) 2-2

Figure 2.2 Configuration of disk media heads 2-3

Figure 2.3 1 drive system configuration 2-4

Figure 2.4 2 drives configuration 2-4

Figure 3.1 Dimensions (MHE/MHF series) 3-2

Figure 3.2 Orientation (Sample: MHE2064AT) 3-4

Figure 3.3 Mounting frame structure 3-5

Figure 3.4 Surface temperature measurement points (Sample: MHE2064AT)

3-6

Figure 3.5 Service area (Sample: MHE2064AT) 3-7

Figure 3.6 Connector locations (Sample: MHE2064AT) 3-8

Figure 3.7 Cable connections 3-9

Figure 3.8 Power supply connector pins (CN1) 3-10

Figure 3.9 Jumper location 3-10

Figure 3.10 Factory default setting 3-11

Figure 3.11 Jumper setting of master or slave device 3-11

Figure 3.12 CSEL setting 3-12

Figure 3.13 Example (1) of Cable Select 3-12

Figure 3.14 Example (2) of Cable Select 3-13

Figure 4.1 Head structure 4-3

Figure 4.2 Circuit Configuration 4-5

Figure 4.3 Power-on operation sequence 4-7

Figure 4.4 Read/write circuit block diagram 4-11

Figure 4.5 Frequency characteristic of programmable filter 4-12

Figure 4.6 Block diagram of servo control circuit 4-14

Figure 4.7 Physical sector servo configuration on disk surface 4-16

Figure 4.8 Servo frame format 4-18

Figure 5.1 Interface signals 5-2

Figure 5.2 Execution example of READ MULTIPLE command 5-20

Figure 5.3 Read Sector(s) command protocol 5-74

Figure 5.4 Protocol for command abort 5-75

C141-E057-01EN

Contents

Figure 5.5 WRITE SECTOR(S) command protocol 5-76

Figure 5.6 Protocol for the command execution without data transfer 5-

78

Figure 5.7 Normal DMA data transfer 5-79

Figure 5.8 An example of generation of parallel CRC 5-93

Figure 5.9 Ultra DMA termination with pull-up or pull-down 5-94

Figure 5.10 Data transfer timing 5-96

Figure 5.11 Single word DMA data transfer timing (mode 2) 5-97

Figure 5.12 Multiword DMA data transfer timing (mode 2) 5-98

Figure 5.13 Starting of Ultra DMA data In Burst transfer 5-99

Figure 5.14 Sustained Ultra DMA data in burst 5-102

Figure 5.15 Host pausing an Ultra DMA data in burst 5-103

Figure 5.16 Device terminating an Ultra DMA data in burst 5-104

Figure 5.17 Host terminating an Ultra DMA data in burst 5-105

Figure 5.18 Initiating an Ultra DMA data out burst 5-106

Figure 5.19 Sustained Ultra DMA data out burst 5-107

Figure 5.20 Device pausing an Ultra DMA data out burst 5-108

Figure 5.21 Host terminating an Ultra DMA data out burst 5-109

Figure 5.22 Device terminating an Ultra DMA data out burst 5-110

Figure 5.23 Power on Reset Timing 5-111

Figure 6.1 Response to power-on 6-3

Figure 6.2 Response to hardware reset 6-4

Figure 6.3 Response to software reset 6-5

Figure 6.4 Response to diagnostic command 6-6

Figure 6.5 Address translation (example in CHS mode) 6-8

Figure 6.6 Address translation (example in LBA mode) 6-9

Figure 6.7 Sector slip processing 6-12

Figure 6.8 Alternate cylinder assignment 6-13

Figure 6.9 Data buffer configuration 6-14

Tables

C141-E057-02EN

Table 1.1

Specifications (MHE2064AT/MHE2043AT) 1-4

Table 1.2

Specifications (MHF2043AT/MHF2021AT) 1-5

Table 1.3

Specifications (MHE2064AT/2043AT/MHF2043AT/2021AT)

1-6

Table 1.4

Model names and product numbers 1-6

Table 1.5

Current and power dissipation 1-7

Table 1.6

Environmental specifications 1-8

Table 1.7

Acoustic noise specification 1-9

Table 1.8

Shock and vibration specification 1-9 xv

Contents

Table 3.1

Surface temperature measurement points and standard values

3-6

Table 3.2

Cable connector specifications 3-9

Table 4.1

Self-calibration execution timechart 4-9

Table 4.2

Write precompensation algorithm 4-10

Table 5.1

Signal assignment on the interface connector 5-3

Table 5.2

I/O registers 5-7

Table 5.3

Command code and parameters 5-14

Table 5.4

Information to be read by IDENTIFY DEVICE command 5-

32

Table 5.5

Features register values and settable modes 5-39

Table 5.6

Diagnostic code 5-46

Table 5.7

Features Register values (subcommands) and functions 5-57

Table 5.8

Format of device attribute value data 5-59

Table 5.9

Format of insurance failure threshold value data 5-60

Table 5.10 Contents of security password 5-64

Table 5.11 Contents of SECURITY SET PASSWORD data 5-68

Table 5.12 Relationship between combination of Identifier and Security level, and operation of the lock function 5-69

Table 5.13 Command code and parameters 5-71

Table 5.14 Parallel generation equation of CRC polynomial 5-93

Table 5.15 Recommended series termination for Ultra DMA 5-94

Table 5.16 Ultra DMA data burst timing requirements 5-100

Table 6.1

Default parameters 6-7 xvi C141-E057-01EN

CHAPTER 1 Device Overview

1.5

1.6

1.7

1.8

1.9

1.1

1.2

1.3

1.4

Features

Device Specifications

Power Requirements

Environmental Specifications

Acoustic Noise

Shock and Vibration

Reliability

Error Rate

Media Defects

Overview and features are described in this chapter, and specifications and power requirement are described.

The MHE Series and MHF Series are 2.5-inch hard disk drives with built-in disk controllers. These disk drives use the AT-bus hard disk interface protocol and are compact and reliable.

C141-E057-01EN 1-1

Device Overview

1.1 Features

1.1.1 Functions and performance

The fillowing features of the MHE Series and MHF Series are described.

(1) Compact

The MHE2064AT and MHE2043AT have 3 disks, and its height is 12.5 mm

(0.492 inch). The MHF2043AT and MHF2021AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch).

(2) Large capacity

The disk drive can record up to 2.16 GB (formatted) on one disk using the (16/17)

EPR4ML recording method and 14 recording zone technology. The MHE Series and MHF Series have a formatted capacity of 6.49 GB (MHE2064AT), 4.32 GB

(MHE2043AT), 4.32 GB (MHF2043AT), 2.16 GB (MHF2021AT) respectively.

(3) High-speed Transfer rate

The disk drives (the MHE Series and MHF Series) have an internal data rate up to

13.6 MB/s. The disk drive supports an external data rate up to 33.3 MB/s (U-

DMA mode 2).

(4) Average positioning time

Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 13 ms (at read).

1.1.2 Adaptability

(1) Power save mode

The power save mode feature for idle operation, stand by and sleep modes makes

The disk drives (the MHE Series and MHF Series) ideal for applications where power consumption is a factor.

(2) Wide temperature range

The disk drives (the MHE Series and MHF Series) can be used over a wide temperature range (5°C to 55°C).

(3) Low noise and vibration

In Ready status, the noise of the disk drives (the MHE Series and MHF Series) is only about 30 dBA (measured at 1 m apart from the drive under the idle mode).

1-2 C141-E057-02EN

1.1 Features

1.1.3 Interface

(1) Connection to interface

With the built-in ATA interface controller, the disk drives (the MHE Series and

MHF Series) can be connected to an ATA interface of a personal computer.

(2) 512-KB data buffer

The disk drives (the MHE Series and MHF Series) uses a 512-KB data buffer to transfer data between the host and the disk media.

In combination with the read-ahead cache system described in item (3) and the write cache described in item (7), the buffer contributes to efficient I/O processing.

(3) Read-ahead cache system

After the execution of a disk read command, the disk drive automatically reads the subsequent data block and writes it to the data buffer (read ahead operation). This cache system enables fast data access. The next disk read command would normally cause another disk access. But, if the read ahead data corresponds to the data requested by the next read command, the data in the buffer can be transferred instead.

(4) Master/slave

The disk drives (the MHE Series and MHF Series) can be connected to ATA interface as daisy chain configuration. Drive 0 is a master device, drive 1 is a slave device.

(5) Error correction and retry by ECC

If a recoverable error occurs, the disk drives (the MHE Series and MHF Series) themselves attempt error recovery. The ECC has improved buffer error correction for correctable data errors.

(6) Self-diagnosis

The disk drives (the MHE Series and MHF Series) have a diagnostic function to check operation of the controller and disk drives. Executing the diagnostic command invokes self-diagnosis.

(7) Write cache

When the disk drives (the MHE Series and MHF Series) receive a write command, the disk drives post the command completion at completion of transferring data to the data buffer completion of writing to the disk media. This feature reduces the access time at writing.

C141-E057-01EN 1-3

Device Overview

1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specfications of the disk drives (MHE2064AT/MHE2043AT).

Table 1.1 Specifications (MHE2064AT/MHE2043AT)

Format Capacity (*1)

Number of Heads

Number of Cylinders (User)

Bytes per Sector

Recording Method

Track Density

Bit Density

Rotational Speed

Average Latency

Positioning time (read and seek)

• Minimum (Track to Track)

• Average

• Maximum (Full)

Start/Stop time

• Start (0 rpm to Drive Read)

• Stop (at Power Down)

Interface

Data Transfer Rate

• To/From Media

• To/From Host

MHE2064AT

6.49 GB

6

8,647

512

(16/17) EPR4ML

14,200 TPI

237.8 Kbpi

4,200 rpm ± 1%

7.14 ms

MHE2043AT

4.32 GB

4

1.5 ms (typ.)

Read: 13 ms (typ.)

23 ms (typ.)

Typ.: 5 sec

Typ.: 5 sec

ATA-4 (Max. Cable length: 0.46 m)

Data Buffer Size

Physical Dimensions

(Height

×

Width

×

Depth)

Weight

7.7 to 13.6 MB/s

33.3 MB/s Max.

(U-DMA mode 2)

512 KB

12.5 mm

×

100.0 mm

×

70.0 mm

145 g

1-4 C141-E057-02EN

1.2 Device Specifications

Format Capacity (*1)

Number of Heads

Number of Cylinders (User)

Bytes per Sector

Recording Method

Track Density

Bit Density

Rotational Speed

Average Latency

Positioning time (read and seek)

• Minimum (Track to Track)

• Average

• Maximum (Full)

Start/Stop time

• Start (0 rpm to Drive Read)

• Stop (at Power Down)

Interface

Data Transfer Rate

• To/From Media

• To/From Host

Table 1.2 shows the specfications of the disk drives (MHF2043AT/MHF2021AT).

Table 1.2 Specifications (MHF2043AT/MHF2021AT)

MHF2043AT

4.32 GB

4

8,647

512

(16/17) EPR4ML

14,200 TPI

237.8 Kbpi

4,200 rpm ± 1%

7.14 ms

MHF2021AT

2.16 GB

2

1.5 ms (typ.)

Read: 13 ms (typ.)

23 ms (typ.)

Typ.: 5 sec

Typ.: 5 sec

ATA-4 (Max. Cable length: 0.46 m)

Data Buffer Size

Physical Dimensions

(Height

×

Width

×

Depth)

Weight

*1: Capacity under the LBA mode.

7.7 to 13.6 MB/s

33.3 MB/s Max.

(U-DMA mode 2)

512 KB

9.5 mm

×

100.0 mm

×

70.0 mm

98 g

C141-E057-02EN 1-5

Device Overview

Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows.

Table 1.3 Specifications (MHE2064AT/2043AT/MHF2043AT/2021AT)

Model

MHE2064AT

MHE2043AT

MHF2043AT

MHF2021AT

Formatted Capacity No. of Cylinder

6,495.06 MB

4,327.46 MB

4,327.46 MB

2,167.60 MB

13,424

8,944

8,944

4,200

No. of Heads

15

15

15

16

No. of Sectors

63

63

63

63

1.2.2 Model and product number

Table 1.4 lists the model names and product numbers of the MHE Series and

MHF Series.

Table 1.4 Model names and product numbers

Model Name Mounting screw Order No.

MHE2064AT

MHE2043AT

MHF2043AT

MHF2021AT

Capacity

(user area)

6.49 GB

4.32 GB

4.32 GB

2.16 GB

M3, depth 3

M3, depth 3

M3, depth 3

M3, depth 3

CA01757-B060

CA01757-B040

CA01758-B040

CA01758-B020

1.3 Power Requirements

(1) Input Voltage

• + 5 V ± 5 %

(2) Ripple

Maximum

Frequency

+5 V

100 mV (peak to peak)

DC to 1 MHz

1-6 C141-E057-02EN

1.3 Power Requirements

(3) Current Requirements and Power Dissipation

Table 1.5 lists the current and power dissipation.

Spin up (*1)

Idle

R/W (*2)

Standby

Sleep

Energy

Consumption

Efficiency (*4)

Table 1.5 Current and power dissipation

Typical RMS Current

MHE Series MHF Series

0.9 A

190 mA

430 mA

0.9 A

190 mA

430 mA

70 mA

26 mA

70 mA

26 mA

Typical Power (*3)

MHE Series

4.5 W

0.95 W

2.15 W

0.35 W

0.13 W

0.0001 W/MB

MHF Series

4.5 W

0.95 W

2.15 W

0.35 W

0.13 W

0.0004 W/MB

*1 Current at starting spindle motor.

*2 Power requirements reflect nominal values for +5V power.

*3 At 30% disk accessing.

*4 Energy Consumption Efficiency =

Idle power dissipation / Total record capacity (MB)

(4) Current fluctuation (Typ.) at +5V when power is turned on

Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on

C141-E057-01EN 1-7

Device Overview

(5) Power on/off sequence

The voltage detector circuits (the MHE Series and MHF Series) monitor +5 V.

The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

1.4 Environmental Specifications

Table 1.6 lists the environmental specifications.

Item

Temperature

• Operating

Table 1.6 Environmental specifications

Specification

5°C to 55°C (ambient)

5°C to 60°C (disk enclosure surface)

–40°C to 65°C

20°C/h or less

• Non-operating

• Thermal Gradient

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

Altitude (relative to sea level)

• Operating

• Non-operating

8% to 90% RH (Non-condensing)

5% to 95% RH (Non-condensing)

29°C

–300 to 3,000 m

–300 to 12,000 m

1-8 C141-E057-01EN

1.6 Shock and Vibration

1.5 Acoustic Noise

Table 1.7 lists the acoustic noise specification.

Table 1.7 Acoustic noise specification

Item Specification

Sound Pressure

• Idle mode (DRIVE READY) 30 dBA typical at 1 m

Note:

Measure the noise from the cover top surface.

1.6 Shock and Vibration

Table 1.8 lists the shock and vibration specification.

Table 1.8 Shock and vibration specification

Item

Vibration (swept sine, one octave per minute)

• Operating

• Non-operating

Specification

5 to 500 Hz, 1.0G0-peak (MHE series)

5 to 400 Hz, 1.0G0-peak (MHF series)

(without non-recovered errors) (9.8 m/s

2

0-peak)

5 to 500 Hz, 5G0-peak (MHE series)

5 to 400 Hz, 5G0-peak (MHF series)

(no damage) (49 m/s

2

0-peak)

Shock (half-sine pulse)

• Operating

• Non-operating

125G0-peak

(without non-recovered errors) (1,225 m/s

2

0-peak)

600G0-peak (MHE series) (5,880 m/s

2

0-peak)

2 ms duration

600G0-peak (MHF series) (5,880 m/s

2

0-peak)

1 ms duration (no damage)

C141-E057-02EN 1-9

Device Overview

1.7 Reliability

(1) Mean time between failures (MTBF)

Conditions of 300,000 h Current time 250H/month or less 3000H/years or less

Operating time 20% or less of current time

CSS operations 50/day or less

Total 50,000 or less

Power on/off 1/day or more needed.

Environment 5 to 55°C/8 to 90%

But humidity bulb temperature

29°C or less

MTBF is defined as follows:

Total operation time in all fields

MTBF= number of device failure in all fields

(H)

“Disk drive defects” refers to defects that involve repair, readjustment, or replacement. Disk drive defects do not include failures caused by external factors, such as damage caused by handling, inappropriate operating environments, defects in the power supply host system, or interface cable.

(2) Mean time to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance staff member.

(3) Service life

In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C.

When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first. Refer to item (3) in Subsection 3.2 for the measurement point of the DE surface temperature. Also the operating conditions except the environment temperature are based on the MTBF conditions.

(4) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment).

1-10 C141-E057-01EN

1.9 Media Defects

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media.

(1) Unrecoverable read error

Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading data of 10

14

bits. Read retries are executed according to the disk drive’s error recovery procedure, and include read retries accompanying head offset operations.

(2) Positioning error

Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in 10

7

seek operations.

1.9 Media Defects

Defective sectors are replaced with alternates when the disk (the MHE Series and

MHF Series) are formatted prior to shipment from the factory (low level format).

Thus, the hosts see a defect-free devices.

Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors.

C141-E057-02EN 1-11

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CHAPTER 2 Device Configuration

2.1

2.2

Device Configuration

System Configuration

This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate.

C141-E057-01EN 2-1

Device Configuration

2.1 Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter.

(1) Disk

MHE20xxAT MHF20xxAT

Figure 2.1 Disk drive outerview (the MHE Series and MHF Series)

The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. The number of disks used varies with the model, as described below. The disks are rated at over 50,000 start/stop operations.

MHE2064AT: 3 disks MHE2043AT: 2 disks

MHF2043AT: 2 disks MHF2021AT: 1 disks

(2) Head

The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts.

Figure 2.2 illustrates the configuration of the disks and heads of each model. In the disk surface, servo information necessary for controlling positioning and read/write and user data are written. Numerals 0 to 5 indicate read/write heads.

2-2 C141-E057-02EN

2.1 Device Configuration

3

2

Head

5

4

1

0

MHE2064AT

1

0

Head

3

2

MHE2043AT

Head

3

2

1

0

MHF2043AT

Head

1

0

MHF2021AT

Figure 2.2 Configuration of disk media heads

(3) Spindle motor

The disks are rotated by a direct drive Hall-less DC motor.

(4) Actuator

The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head. If the power is not on or if the spindle motor is stopped, the head assembly stays in the specific CSS zone on the disk and is fixed by a mechanical lock.

(5) Air circulation system

The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure.

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The highspeed microprocessor unit (MPU) achieves a high-performance AT controller.

C141-E057-02EN 2-3

Device Configuration

2.2 System Configuration

2.2.1 ATA interface

Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 44-pin PC AT interface connector and supports the PIO transfer at 16.6 MB/s

(ATA-3, Mode 4), the DMA transfer at 16.6 MB/s (ATA-3, Multiword mode 2) and also the U-DMA at 33.3 MB/s (ATA-3, Mode 2).

2.2.2 1 drive connection

MHE2064AT

MHC2032AT

MHC2040AT

MHF2021AT

Figure 2.3 1 drive system configuration

2.2.3 2 drives connection

(Host adaptor)

MHE2064AT

MHF2021AT

MHE2064AT

MHC2032AT

MHC2040AT

MHF2021AT

Note:

When the drive that is not conformed to ATA is connected to the disk drive above configuration, the operation is not guaranteed.

Figure 2.4 2 drives configuration

2-4 C141-E057-02EN

2.2 System Configuration

HA (host adaptor) consists of address decoder, driver, and receiver.

ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-4 interface.

At high speed data transfer (PIO mode 3, mode 4, or DMA mode 2

U-DMA mode 2), occurence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability. Thus, it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA-4 standard, and the cable length between the HA and the disk drive should be as short as possible.

No need to push the top cover of the disk drive. If the over-power worked, the cover could be contacted with the spindle motor. Thus, that could be made it the cause of failure.

C141-E057-01EN 2-5

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CHAPTER 3 Installation Conditions

3.1

3.2

3.3

3.4

Dimensions

Mounting

Cable Connections

Jumper Settings

This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives.

C141-E057-01EN 3-1

Installation Conditions

3.1 Dimensions

Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm.

3-2

Figure 3.1 Dimensions (MHE series) (1/2)

C141-E057-01EN

3.1 Dimensions

C141-E057-01EN

Figure 3.1 Dimensions (MHF series) (2/2)

3-3

Installation Conditions

3.2 Mounting

(1) Orientation

Figure 3.2 illustrates the allowable orientations for the disk drive.

gravity

(a) Horizontal –1 (b) Horizontal –1 gravity

(c) Vertical –1 (d) Vertical –2 gravity

(e) Vertical –3 (f) Vertical –4

Figure 3.2 Orientation (Sample: MHE2064AT)

3-4 C141-E057-01EN

3.2 Mounting

(2) Frame

The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG.

Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3.

The tightening torque must not exceed 3 kgcm.

When attaching the HDD to the system frame, do not allow the system frame to touch parts (cover and base) other than parts to which the HDD is attached.

(3) Limitation of side-mounting

Do not use the center hole. For screw length, see Figure 3.3.

Note) These dimensions are recommended values; if it is not possible to satisfy them, contact us.

2

Bottom surface mounting

A

Frame of system cabinet

DE

2.5

2.5

2.5

Frame of system cabinet

PCA

Side surface mounting

B

2.5

3.0 or less

Details of A

Screw

3.0 or less

Details of B

Screw

Figure 3.3 Mounting frame structure

C141-E057-01EN 3-5

Installation Conditions

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60

°

C.

Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling. To check the cooling efficiency, measure the surface temperatures of the DE. Regardless of the ambient temperature, this surface temperature must meet the standards listed in Table 3.1. Figure 3.4 shows the temperature measurement point.

1

3-6

Figure 3.4 Surface temperature measurement points (Sample: MHE2064AT)

Table 3.1 Surface temperature measurement points and standard values

No.

1

Measurement point

DE cover

Temperature

60°C max

C141-E057-01EN

3.2 Mounting

(5) Service area

Figure 3.5 shows how the drive must be accessed (service areas) during and after installation.

Mounting screw hole

Cable connection

Mounting screw hole

Figure 3.5 Service area (Sample: MHE2064AT)

Data corruption:

Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

Also, do not press the cover of the disk drive. Pressing it too much, the cover and the spindle motor contacts and it is fear of causes of the trouble being.

Stastic:

When handling the device, disconnect the body ground

(500 k

or greater). Do not touch the printed circuit board, but hold it by the edges.

C141-E057-02EN 3-7

Installation Conditions

3.3 Cable Connections

3.3.1 Device connector

The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.6 shows the locations of these connectors and terminals.

3-8

PCA

Connector, setting pins

Figure 3.6 Connector locations (Sample: MHE2064AT)

C141-E057-01EN

3.3 Cable Connections

3.3.2 Cable connector specifications

Table 3.2 lists the recommended specifications for the cable connectors.

Table 3.2 Cable connector specifications

ATA interface and power supply cable (44-pin type)

Name

Cable socket

(44-pin type)

Model

89361-144

Manufacturer

BERG

For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines. This is because the interface is designed for ribbon cables and not for cables carrying differential signals.

3.3.3 Device connection

Figure 3.7 shows how to connect the devices.

Figure 3.7 Cable connections

C141-E057-01EN 3-9

Installation Conditions

3.3.4 Power supply connector (CN1)

Figure 3.8 shows the pin assignment of the power supply connector (CN1).

Figure 3.8 Power supply connector pins (CN1)

3.4 Jumper Settings

3.4.1 Location of setting jumpers

Figure 3.9 shows the location of the jumpers to select drive configuration and functions.

3-10

Figure 3.9 Jumper location

C141-E057-01EN

3.4.2 Factory default setting

Figure 3.10 shows the default setting position at the factory.

3.4 Jumper Settings

Open

Figure 3.10 Factory default setting

3.4.3 Master drive-slave drive setting

Master device (device #0) or slave device (device #1) is selected.

1 C

Open

A

2

D B

Open

(a) Master drive

1

Open

C A

Short

2 D B

(b) Slave drive

Figure 3.11 Jumper setting of master or slave device

Note:

Pins A and C should be open.

C141-E057-02EN 3-11

Installation Conditions

3.4.4 CSEL setting

Figure 3.12 shows the cable select (CSEL) setting.

1 C

Open

A

2 D

Short

B

Note:

The CSEL setting is not depended on setting between pins Band D.

Figure 3.12 CSEL setting

Figure 3.13 and 3.14 show examples of cable selection using unique interface cables.

By connecting the CSEL of the master device to the CSEL Line (conducer) of the cable and connecting it to ground further, the CSEL is set to low level. The device is identified as a master device. At this time, the CSEL of the slave device does not have a conductor. Thus, since the slave device is not connected to the

CSEL conductor, the CSEL is set to high level. The device is identified as a slave device.

Figure 3.13 Example (1) of Cable Select

3-12 C141-E057-02EN

Figure 3.14 Example (2) of Cable Select

3.4 Jumper Settings

C141-E057-01EN 3-13

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CHAPTER 4 Theory of Device Operation

4.5

4.6

4.7

4.1

4.2

4.3

4.4

Outline

Subassemblies

Circuit Configuration

Power-on Sequence

Self-calibration

Read/write Circuit

Servo Control

This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

C141-E057-01EN 4-1

Theory of Device Operation

4.1 Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method.

4.2 Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly

(PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle, actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.

The PCA contains the control circuits for the disk drive. The disk drive has one

PCA. For details, see Sections 4.3.

4.2.1 Disk

The DE contains disks with an outer diameter of 65 mm and an inner diameter of

20 mm. The MHE2064AT have three disks and MHE2043AT have two disks and

MHF2043AT have two disks and MHF2021AT have one disk.

The head contacts the disk each time the disk rotation stops; the life of the disk is

50,000 contacts or more. Servo data is recorded on top disk.

Servo data is recorded on each cylinder (total 60). Servo data written at factory is read out by the read/write head. For servo data, see Section 4.7.

4.2.2 Head

Figure 4.1 shows the read/write head structures. MHE2064AT has 6 read/write heads and MHE2043AT has 4 read/write heads and MHF2043AT has 4 read/write heads and MHF2021AT has 2 read/write head. These heads are raised from the disk surface as the spindle motor the rated rotation speed.

4-2 C141-E057-02EN

4.2 Subassemblies

3

2

Head

5

4

1

0

MHE2064AT

1

0

Head

3

2

MHE2043AT

Head

3

2

1

0

MHF2043AT

Figure 4.1 Head structure

Head

1

0

MHF2021AT

4.2.3 Spindle

The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm

±

1%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting.

4.2.4 Actuator

The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the head carriage along the inner or outer edge of the disk. The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read/write head.

4.2.5 Air filter

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk.

C141-E057-02EN 4-3

Theory of Device Operation

4.3 Circuit Configuration

Figure 4.2 shows the disk drive circuit configuration.

(1) Read/write circuit

The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC).

The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

The RDC is the read demodulation circuit using the extended partial response class 4 (EPR4), and contains the Viterbi detector, programmable filter, adaptable transversal filter, times base generator, and data separator circuits. The RDC also contains the 16/17 group coded recording (GCR) encoder and decoder and servo demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by 2 closed-loop servo using the servo information recorded on the data surface. The servo information is an analog signal converted to digital for processeing by a MPU and then reconverted to an analog signal for control of the voice coil motor.

The MPU precisely sets each head on the track according on the servo information on the media surface.

(3) Spindle motor driver circuit

The circuit measures the interval of a PHASE signal generated by counterelectromotive voltage of a motor at the MPU and controls the motor speed comparing target speed.

(4) Controller circuit

Major functions are listed below.

• Data buffer (512 KB) management

• ATA interface control and data transfer control

• Sector format control

Defect management

ECC control

Error recovery and self-diagnosis

4-4 C141-E057-01EN

16 bit

4.3 Circuit Configuration

C141-E057-01EN

Figure 4.2 Circuit Configuration

4-5

Theory of Device Operation

4.4 Power-on Sequence

Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below.

a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to the ATA bus.

c) After confirming that the spindle motor has reached rated speed, the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM. This unlocks the heads which are parked at the inner circumference of the disks.

d) The disk drive positions the heads onto the SA area and reads out the system information.

e) The disk drive executes self-seek-calibration. This collects data for VCM tarque and mechanical external forces applied to the actuator, and updates the calibrating value.

f) The drive becomes ready. The host can issue commands.

4-6 C141-E057-01EN

4.5 Self-calibration

Figure 4.3 Power-on operation sequence

4.5 Self-calibration

The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM tarque. This enables precise seek and read/write operations.

4.5.1 Self-calibration contents

(1) Sensing and compensating for external forces

The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned. To execute stable fast seek operations, external forces are occasionally sensed.

The firmware of the drive measures and stores the force (value of the actuator motor drive current) that balances the torque for stopping head stably. This includes the current offset in the power amplifier circuit and DAC system.

C141-E057-01EN 4-7

Theory of Device Operation

The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control.

To compensate torque varing by the cylinder, the disk is divided into 8 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration. The measured values are stored in the SA cylinder. In the self-calibration, the compensating value is updated using the value in the SA cylinder.

(2) Compensating open loop gain

Torque constant value of the VCM has a dispersion for each drive, and varies depending on the cylinder that the head is positioned. To realize the high speed seek operation, the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder. The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio.

For compensating, the direction current value to the power amplifier is multiplied by the compensation value. By this compensation, loop gain becomes constant value and the stable servo control is realized.

To compensate torque constant value change depending on cylinder, whole cylinders from most inner to most outer cylinder are divided into 8 partitions at calibration in the factory, and the compensation data is measured for representive cylinder of each partition. This measured value is stored in the SA area. The compensation value at self-calibration is calculated using the value in the SA area.

4.5.2 Execution timing of self-calibration

Self-calibration is executed when:

• The power is turned on.

• The disk drive receives the RECALIBRATE command from the host.

• The self-calibration execution timechart of the disk drive specifies selfcalibration.

The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. The timechart is shown in Table 4.1. After poweron, self-calibration is performed about every five or ten or fifteen minutes for the first 60 minutes or six RECALIBRATE command executions, and about every 30 minutes after that.

4-8 C141-E057-01EN

4.6 Read/write Circuit

3

4

5

6

1

2

7

8

.

.

.

.

Table 4.1 Self-calibration execution timechart

Time elapsed

At power-on

About 5 minutes

About 5 minutes

About 10 minutes

About 10 minutes

About 15 minutes

About 15 minutes

Every about 30 minutes

Time elapsed

(accumulated)

Initial calibration

About 5 minutes

About 10 minutes

About 20 minutes

About 30 minutes

About 45 minutes

About 60 minutes

4.5.3 Command processing during self-calibration

If the disk drive receives a command execution request from the host while executing self-calibration according to the timechart, the disk drive terminates self-calibration and starts executing the command precedingly. In other words, if a disk read or write service is necessary, the disk drive positions the head to the track requested by the host, reads or writes data, and restarts calibration.

This enables the host to execute the command without waiting for a long time, even when the disk drive is performing self-calibration. The command execution wait time is about maximum 100 ms.

4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC).

Figure 4.4 is a block diagram of the read/write circuit.

4.6.1 Read/write preamplifier (PreAMP)

One PreAMP is mounted on the FPC. The PreAMP consists of an read preamplifier and a write current switch and senses a write error. Each channel is connected to each data head. The head IC switches the heads by the chip select signals (*CS) and the head select signals. The IC generates a write error sense

C141-E057-01EN 4-9

Theory of Device Operation

signal (WUS) when a write error occurs due to head short-circuit or head disconnection.

The Pre AMP sets the write current and bias current which flows through MR devices.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC. The NRZ write data is converted from 16-bit data to 17-bit data by the encoder circuit then sent to the

PreAMP, and the data is written onto the media.

(1) 16/17 GCR

The disk drive converts data using the 16/17 (0, 12, 8) group coded recording

(GCR) algorithm. This code follows a format in which 0 to 12 “0”s are inserted while the code bit is “1” and 0 to 8 “0”s are inserted while the 0DD/EVEN bit is

“1”.

(2) Write precompensation

Write precompensation compensates, during a write process, for write nonleneartiry generated at reading. Table 4.2 shows the write precompensation algorithm.

Table 4.2 Write precompensation algorithm

Bits

111001

111010

:

111111

000000

000001

:

010000

:

100000

Compensation

–7

–6

–1

±

0

+1

+16

+32

4-10 C141-E057-01EN

4.6 Read/write Circuit

C141-E057-01EN

Figure 4.4 Read/write circuit block diagram

4-11

Theory of Device Operation

4.6.3 Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control

(AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

(2) Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from the register in read channel by an instruction of the serial data signal from MPU (M5).

The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

Figure 4.5 shows the frequency characteristic sample of the programmalbe filter.

-3 dB

4-12

Figure 4.5 Frequency characteristic of programmable filter

C141-E057-01EN

4.6 Read/write Circuit

(3) Flash digitizer circuit

This circuit is 10-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the partial response class 4 (EPR4) waveform.

(4) Viterbi detection circuit

The sample hold waveform output from the flash digitizer circuit is sent to the

Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

(5) 16/17 GCR decoder

This circuit converts the 17-bit read data into the 16-bit NRZ data.

4.6.4 Digital PLL circuit

The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 14 zones to set the data transfer rate.

The MPU transfers the data transfer rate setup data (SD/SC) to the RDC that includes the Digital PLL circuit to change the data transfer rate.

C141-E057-01EN 4-13

Theory of Device Operation

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.

4.7.1 Servo control circuit

Figure 4.6 is the block diagram of the servo control circuit. The following describes the functions of the blocks:

(3)

(4)

Power

Amp

(7)

(5) (6)

Figure 4.6 Block diagram of servo control circuit

(1) Microprocessor unit (MPU)

The MPU includes the DSP unit, and the MPU starts the spindle motor, moves the heads to the reference cylinders, seeks the specified cylinder, and executes calibration according to the internal operations of the MPU. Main internal operation of the MPU are shown below.

4-14 C141-E057-01EN

4.7 Servo Control

The major internal operations are listed below.

a.

Spindle motor start

Starts the spindle motor and accelerates it to normal speed when power is applied.

b.

Move head to reference cylinder

Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).

c.

Seek to specified cylinder

Drives the VCM to position the head to the specified cylinder.

d.

Calibration

Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value.

C141-E057-01EN 4-15

Theory of Device Operation

Servo frame

(60 servo frames revolution)

4-16

CYL-n (n: even number)

Diameter direction

Circumference direction

Erase: DC erase area

Figure 4.7 Physical sector servo configuration on disk surface

C141-E057-01EN

4.7 Servo Control

(2) Servo burst capture circuit

The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B,

SERVO C and SERVO D burst signals shown in Figure 4.8 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head. The servo signals A/D-converts the amplitudes of the POSA, POSB, POSC and POSD signals at the peak hold circuit in the servo burst capture circuit at the timing of the STROB signal. At that time the AGC circuit is in hold mode. The A/D converted data is recognized by the MPU as position information with A-B and C-D processed.

(3) D/A converter (DAC)

The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.

(4) Power amplifier

The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM.

(5) Spindle motor control circuit

The spindle motor control circuit controls the sensor-less spindle motor. This circuit detects number of revolution of the motor by the interrupt generated periodically, compares with the target revolution speed, then flows the current into the motor coil according to the differentation (abberration).

(6) Driver circuit

The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor.

(7) VCM current sense resistor (CSR)

This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back.

C141-E057-01EN 4-17

Theory of Device Operation

4.7.2 Data-surface servo format

Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below.

(1) Inner guard band

The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

(2) Data area

This area is used as the user data area SA area.

(3) Outer guard band

This area is located at outer position of the user data area, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

4.7.3 Servo frame format

As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction.

The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code, servo A to D, and PAD. Figure 4.8 shows the servo frame format.

4-18

Figure 4.8 Servo frame format

C141-E057-01EN

4.7 Servo Control

(1) Write/read recovery

This area is used to absorb the write/read transient and to stabilize the AGC.

(2) Servo mark

This area gererates a timing for demodulating the gray code and positiondemodulating the servo A to D by detecting the servo mark.

(3) Gray code (including index bit)

This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit

(4) Servo A, servo B, servo C, servo D

This area is used as position signals between tracks, and the IDD control at ontrack so that servo A level equals to servo B level.

(5) PAD

This area is used as a gap between servo and data.

4.7.4 Actuator motor control

The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the

VCM drive current.

The servo control of the actuator includes the operation to move the head to the reference cylinder, the seek operation to move the head to the target cylinder to read or write data, and the track-following operation to position the head onto the target track.

(1) Operation to move the head to the reference cylinder

The MPU moves the head to the reference cylinder when the power is turned. The reference cylinder is in the data area.

When power is applied the heads are moved from the inner circumference shunt zone to the normal servo data zone in the following sequence: a) Micro current is fed to the VCM to press the head against the inner circumference.

b) Micro current is fed to the VCM to move the head toward the outer circumference.

c) When the servo mark is detected the head is moved slowly toward the outer circumference at a constant speed.

C141-E057-01EN 4-19

Theory of Device Operation

d) If the head is stopped at the reference cylinder from there. Track following control starts.

(2) Seek operation

Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read/write instruction is issued, the MPU seeks the desired track.

The MPU feeds the VCM current via the D/A converter and power amplifier to move the head. The MPU calculates the difference (speed error) between the specified target position and the current position for each sampling timing during head moving. The MPU then feeds the VCM drive current by setting the calculated result into the D/A converter. The calculation is digitally executed by the firmware. When the head arrives at the target cylinder, the track is followed.

(3) Track following operation

Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed, the MPU does track following control. To position the head at the center of a track, the DSP drives the VCM by feeding micro current. For each sampling time, the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data. The filtering includes servo compensation. These are digitally controlled by the firmware.

4.7.5 Spindle motor control

Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3phase full/half-wave analog current control circuit is used as the spindle motor driver (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the

MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence: a) After the power is turned on, the MPU sends a signal to the SVC to charge the charge pump capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC to the motor start mode. Then, a current (approx. 0.7 A) flows into the spindle motor.

c) The SVC generates a phase switching signal by itself, and changes the phase of the current flowed in the motor in the order of (V-phase to U-phase), (Wphase to U-phase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to

W-phase), and (V-phase to W-phase) (after that, repeating this order).

4-20 C141-E057-01EN

4.7 Servo Control

d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection.

e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a sepcific period, the MPU resets the SVC and starts from the beginning.

When a PHASE signal is sent, the SVC enters the acceleration mode.

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SVC. The

SVC starts a phase switching by itself based on the counter electromotive force.

Then, rotation of the spindle motor accelerates. The MPU calcurates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 4,200 rpm. When the rotational speed reaches 4,200 rpm, the SVC enters the stable rotation mode.

(3) Stable rotation mode

The MPU calcurates a time for one revolution of the spindle motor based on the

PHASE signal from the SVC. The MPU takes a difference between the current time and a time for one revolution at 4,200 rpm that the MPU already recognized.

Then, the MPU keeps the rotational speed to 4,200 rpm by charging or discharging the charge pump for the different time. For example, when the actual rotational speed is 4,000 rpm, the time for one revolution is 15.000 ms. And, the time for one revolution at 4,200 rpm is 14.286 ms. Therefore, the MPU charges the charge pump for 0.714 ms

×

k (k: constant value). This makes the flowed current into the motor higher and the rotational speed up. When the actual rotational speed is faster than 4,200 rpm, the MPU discharges the pump the other way. This control (charging/discharging) is performed every 1 revolution.

C141-E057-01EN 4-21

This page is intentionally left blank.

CHAPTER 5 Interface

5.1

5.2

5.3

5.4

5.5

5.6

Physical Interface

Logical Interface

Host Commands

Command Protocol

Ultra DMA Feature Set

Timing

This chapter gives details about the interface, and the interface commands and timings.

C141-E057-01EN 5-1

Interface

5.1 Physical Interface

5.1.1 Interface signals

Figure 5.1 shows the interface signals.

DIOW-: I/O WRITE

STOP: STOP DURING ULTRA DMA DATA BURSTS

DIOR-: I/O READ

HDMARDY: DMA READY DURING ULTRA DMA DATA IN BURSTS

HSTROBE: DATA STROBE DURING ULTRA DMA DATA OUT BURSTS

INTRQ: INTERRUPT REQUEST

IOCS16-: 16-BIT I/O

PDIAG: PASSED DIAGNOSTICS

DASP-: DEVICE ACTIVE/SLAVE PRESENT

IORDY: I/O READY

DDMARDY: DMA READY DURING ULTRA DMA DATA OUT BURSTS

DSTROBE: DATA STROBE DURING ULTRA DMA DATA IN BURSTS

5-2

Figure 5.1 Interface signals

C141-E057-01EN

5.1 Physical Interface

5.1.2 Signal assignment on the connector

Table 5.1 shows the signal assignment on the interface connector.

Table 5.1 Signal assignment on the interface connector

29

31

33

35

37

39

41

43

Pin No.

7

9

11

3

5

13

15

A

C

E

1

17

19

21

23

25

27

Signal

ENCSEL

ENCSEL

(KEY)

RESET–

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

GND

DMARQ

DIOW-, STOP

DIOR-, HDMRDY,

HSTROBE

IORDY, DDMARDY,

DSTROBE

DMACK–

INTRQ

DA1

DA0

CS0–

DASP–

+5 VDC

GND

Pin No.

8

10

12

4

6

14

16

B

D

F

2

18

20

22

24

26

Signal

GND

MSTR

(KEY)

GND

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

(KEY)

GND

GND

GND

28

30

32

34

36

38

40

42

44

CSEL

GND

IOCS16–

PDIAG

DA2

CS1–

GND

+5 VDC unused

C141-E057-01EN 5-3

Interface

[signal]

ENCSEL

MSTR

[I/O]

I

I

[Description]

This signal is used to set master/slave using the CSEL signal (pin 28).

Pins A and C Open: Sets master/slave by the MSTR signal without using the CSEL signal.

Short: Sets master/slave using the CSEL signal.

The MSTR signal is ignored.

MSTR, I, Master/slave setting

1: Master 0: Slave

RESETI Reset signal from the host. This signal is low active and is asserted for a minimum of 25

µ s during power on.

DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the device. These signals are used for data transfer

DIOWI

STOP

DIOR-

I

I

Signal asserted by the host to write to the device register or data port.

DIOW- must be negated by the host before starting the Ultra

DMA transfer. The STOP signal must be negated by the host before data is transferred during the Ultra DMA transfer. During data transfer in Ultra DMA mode, the assertion of the STOP signal asserted by the host later indicates that the transfer has been suspended.

Read strobe signal from the host to read the device register or data port

HDMARDYI Flow control signal for Ultra DMA data In transfer (READ DMA command). This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer. The host can negate the HDMARDY- signal to suspend the Ultra DMA data In transfer.

HSTROBE

INTRQ

I Data Out Strobe signal from the host during Ultra DMA data Out transfer (WRITE DMA command). Both the rising and falling edges of the HSTROBE signal latch data from Data 15-0 into the device. The host can suspend the inversion of the HSTROBE signal to suspend the Ultra DMA data Out transfer.

O Interrupt signal to the host.

This signal is negated in the following cases:

− assertion of RESET- signal

Reset by SRST of the Device Control register

Write to the command register by the host

− Read of the status register by the host

Completion of sector data transfer

(without reading the Status register)

The signal output line has a high impedance when no devices are selected or interruption is disabled.

5-4 C141-E057-01EN

5.1 Physical Interface

[signal]

IOCS16-

CS0-

CS1-

DA 0-2

KEY

PDIAG-

DASP-

IORDY

DDMARDY

-

DSTROBE

CSEL

DMACK-

[I/O] [Description]

O This signal indicates 16-bit data bus is addressed in PIO data transfer.

This signal is an open collector output.

When IOCS16- is not asserted:

8 bit data is transferred through DATA0 to DATA7 signals.

− When IOCS16- is asserted:

I

16 bit data is transferred through DATA0 to DATA15 signals.

Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers.

I

I

Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

Binary decoded address signals asserted by the host to access task file registers.

Key pin for prevention of erroneous connector insertion -

I/O This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration. This signal indicates that the slave device has been completed self diagnostics.

This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This is a time-multiplexed signal that indicates that the device is active and a slave device is present.

This signal is pulled up to +5 V through 10 k

Ω resistor at each device.

O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system.

O Flow control signal for Ultra DMA data Out transfer (WRITE

DMA command). This signal is asserted by the device to inform the host that the device is ready to receive the Ultra DMA data

Out transfer. The device can negate the DDMARDY- signal to suspend the Ultra DMA data Out transfer.

O Data In Strobe signal from the device during Ultra DMA data In transfer. Both the rising and falling edges of the DSTROBE signal latch data from Data 15-0 into the host. The device can suspend the inversion of the DSTROBE signal to suspend the

Ultra DMA data In transfer.

I This signal to configure the device as a master or a slave device.

When CSEL signal is grounded,, the IDD is a master device.

I

When CSEL signal is open,, the IDD is a slave device.

This signal is pulled up with 240 k

resistor at each device.

The host system asserts this signal as a response that the host system receive data or to indicate that data is valid.

C141-E057-01EN 5-5

Interface

[signal]

DMARQ

+5 VDC

GND

[I/O] [Description]

O This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system

(at reading) or from the host system (at writing).

I

-

The direction of data transfer is controlled by the DIOR and

DIOW signals. This signal hand shakes with the DMACK-signal.

In other words, the device negates the DMARQ signal after the host system asserts the DMACK signal. When there is other data to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCS16-, CS0- and

CS1- signals are not asserted. The DMA data transfer is a 16-bit data transfer.

+5 VDC power supplying to the device.

Grounded signal at each signal wire.

Note:

“I” indicates input signal from the host to the device.

“O” indicates output signal from the device to the host.

“I/O” indicates common output or bi-directional signal between the host and the device.

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinder-head-sector (CHS) or Logical block address (LBA) mode. The

IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the

Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder

Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the

INITIALIZE DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.)

×

(Number of head) + (Head No.))

×

(Number of sector/track)] + (Sector No.)

1

5-6 C141-E057-01EN

5.2 Logical Interface

5.2.1 I/O registers

Communication between the host system and the device is done through inputoutput (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to

DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

CS0– CS1– DA2 DA1

Table 5.2 I/O registers

DA0

I/O registers

Read operation Write operation

Host I/O address

Command block registers

L H L

L H L

L

L

L

L

H

H

H

H

L

L

H

H

L

L

L

H

H

L

Control block registers

H L H

H L H

H

H

X

H

H

H

H

X

L

L

L

L

H

H

L

H

L

H

L

H

L

H

X

L

H

Data

Error Register

Alternate Status

Data

Features

Sector Count Sector Count

Sector Number Sector Number

Cylinder Low Cylinder Low

Cylinder High Cylinder High

Device/Head

Status

(Invalid)

Device/Head

Command

(Invalid)

Device Control

X’3F6’

X’3F7’

X’1F0’

X’1F1’

X’1F2’

X’1F3’

X’1F4’

X’1F5’

X’1F6’

X’1F7’

Notes:

1.

The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15).

2.

The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

3.

When reading the Drive Address register, bit 7 is high-impedance state.

4.

H indicates signal level High and L indicates signal level Low.

And the LBA mode is specified, the Device/Head, Cylinder High, Cylinder

Low, and Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.

C141-E057-01EN 5-7

Interface

5.2.2 Command block registers

(1) Data register (X’1F0’)

The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode.

(2) Error register (X’1F1’)

The Error register indicates the status of the command executed by the device.

The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the

EXECUTIVE DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7

ICRC

Bit 6

UNC

Bit 5

X

Bit 4

IDNF

Bit 3

X

Bit 2 Bit 1 Bit 0

ABRT TK0NF AMNF

X: Unused

- Bit 7: Interface CRC Error (ICRC). This bit indicates that a CRC error occurred during Ultra DMA transfer.

- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error has been encountered.

- Bit 5: Unused

- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad sector, uncorrectable error and SB not found.

- Bit 3: Unused

- Bit 2: Aborted Command (ABRT). This bit indicates that the requested command was aborted due to a device status error (e.g. Not Ready,

Write Fault) or the command code was invalid.

- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution.

- Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not

Found error occurred.

5-8 C141-E057-01EN

5.2 Logical Interface

[Diagnostic code]

X’01’: No Error Detected.

X’02’: HDC Register Compare Error

X’03’: Data Buffer Compare Error.

X’05’: ROM Sum Check Error.

X’80’: Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X’01’ to

X’05’).

However, when the host system selects the slave device, the diagnostic code of the slave device is posted.

(3) Features register (X’1F1’)

The Features register provides specific feature to a command. For instance, it is used with SET FEATURES command to enable or disable caching.

(4) Sector Count register (X’1F2’)

The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device. When the value in this register is X’00’, the sector count is 256.

When this register indicates X’00’ at the completion of the command execution, this indicates that the command is completed succefully. If the command is not completed scuccessfully, this register indicates the number of sectors to be transferred to complete the request from the host system. That is, this register indicates the number of remaining sectors that the data has not been transferred due to the error.

The contents of this register has other definition for the following commands;

INITIALIZE DEVICE PARAMETERS, SET FEATURES, IDLE, STANDBY and SET MULTIPLE MODE.

(5) Sector Number register (X’1F3’)

The contents of this register indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

C141-E057-01EN 5-9

Interface

(6) Cylinder Low register (X’1F4’)

The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access.

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indcates LBA bits 15 to 8.

(7) Cylinder High register (X’1F5’)

The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the

Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

(8) Device/Head register (X’1F6’)

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.).

Bit 7

X

Bit 6

L

Bit 5

X

Bit 4

DEV

Bit 3

HS3

Bit 2

HS2

Bit 1

HS1

Bit 0

HS0

- Bit 7: Unused

- Bit 6: L. 0 for CHS mode and 1 for LBA mode.

- Bit 5: Unused

- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.

- Bit 3: HS3 CHS mode head address 3 (2

3

). LBA bit 27.

- Bit 2: HS2 CHS mode head address 2 (2

2

). LBA bit 26.

- Bit 1: HS1 CHS mode head address 1 (2

1

). LBA bit 25.

- Bit 0: HS0 CHS mode head address 0 (2

0

). LBA bit 24.

5-10 C141-E057-01EN

5.2 Logical Interface

(9) Status register (X’1F7’)

The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the

BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt

Acknowledge (the host system acknowledges the interrupt). Any pending interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6

BSY DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed.

However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers. If the host system reads any command block register when BSY bit is 1, the contents of the Status register are posted. This bit is set by the device under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the

Device Control register, the BSY bit is set. the BSY bit is cleared, when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

(b) Within 400 ns from the host system starts writing to the

Command register.

(c) Within 5

µ s following transfer of 512 bytes data during execution of the READ SECTOR(S), WRITE SECTOR(S), or WRITE

BUFFER command.

Within 5

µ s following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ

LONG or WRITE LONG command.

- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is capable to respond to a command.

The IDD checks its status when it receives a command. If an error is detected (not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is cleared until the rotational speed of the spindle motor reaches the steady speed.

C141-E057-01EN 5-11

Interface

- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault

(write fault) condition has been detected.

If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is completed.

- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device.

- Bit 2: Always 0.

- Bit 1: Always 0.

- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error.

(10) Command register (X’1F7’)

The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the neccesary parameters for each command which are written to certain registers before the Command register is written.

5-12 C141-E057-01EN

5.3 Host Commands

5.2.3 Control block registers

(1) Alternate Status register (X’3F6’)

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7 Bit 6

BSY DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

(2) Device Control register (X’3F6’)

The Device Control register contains device interrupt and software reset.

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

SRST

Bit 1 nIEN

Bit 0

0

- Bit 2: SRST is the host software reset bit. When this bit is set, the device is held reset state. When two device are daisy chained on the interface, setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this bit is 0 and the device is selected, an interruption

(INTRQ signal) can be enabled through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ signal is in the highimpedance state.

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the

Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

C141-E057-01EN 5-13

Interface

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed.

5.3.1 Command code and parameters

Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.

Table 5.3 Command code and parameters (1 of 2)

Command code (Bit) Parameters used

Command name

7 6 5 4 3 2 1 0 FR SC SN CY DH

READ SECTOR(S)

READ MULTIPLE

READ DMA

READ VERIFY SECTOR(S)

WRITE MULTIPLE

WRITE DMA

WRITE VERIFY

0 0 1 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 0 N Y Y Y Y

1 1 0 0 1 0 0 R N Y Y Y Y

0 1 0 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 1 N Y Y Y Y

1 1 0 0 1 0 1 R N Y Y Y Y

0 0 1 1 1 1 0 0 N Y Y Y Y

WRITE SECTOR(S)

RECALIBRATE

0 0 1 1 0 0 0 R N Y Y Y Y

0 0 0 1 X X X X N N N N D

SEEK 0 1 1 1 X X X X N N Y Y Y

INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

SET MULTIPLE MODE

SET MAX ADDRESS

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

0

0

1

0

0

1

N

N

Y

N

N

N*

N

N

N

N

N

N

D

D

D

1 1 0 0 0 1 1 0 N Y N N D

1 1 1 1 1 0 0 1 N Y Y Y Y

READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N N N D

EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D*

READ LONG

WRITE LONG

0

0

0

0

1

1

0

1

0

0

0

0

1

1

R

R

N

N

Y

Y

Y

Y

Y

Y

Y

Y

READ BUFFER

WRITE BUFFER

IDLE

1

1

1

1

1

1

0

1

1

1

0

1

0

0

1

0

0

1

0

0

1

0

1

0

0

0

1

1

0

0

1

1

N

N

N

N

N

Y

N

N

N

N

N

N

D

D

D

5-14 C141-E057-01EN

5.3 Host Commands

Table 5.3 Command code and parameters (2 of 2)

Command code (Bit) Parameters used

Command name

7 6 5 4 3 2 1 0 FR SC SN CY DH

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

1

1

1

1

1

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

0

0

0

0

0

0

1

0

1

0

1

0

1

1

0

0

0

0

0

0

1

1

0

0

N

N

N

N

Y

N

N

N

N

N

N

N

D

D

D

SLEEP

CHECK POWER MODE 1

1

1

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

0

1

0

1

0

0

0

1

0

1

1

0

N

N

N

N

N

N

N

N

D

D

SMART 1 0 1 1 0 0 0 0 Y Y Y Y D

SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

0

N

N

N

N

N

N

N

N

D

D

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

FLUSH CACHE

1 1 1 1 0 1 0 1 N N N N D

1 1 1 1 0 0 0 1 N N N N D

1 1 1 1 0 0 1 0 N N N N D

1 1 1 0 0 1 1 1 N N N N D

Notes:

FR: Features Register

CY: Cylinder Registers

SC: Sector Count Register

DH: Drive/Head Register

SN: Sector Number Register

R: Retry at error

1 = Without retry

0 = With retry

Y: Necessary to set parameters

C141-E057-01EN 5-15

Interface

Y*: Necessary to set parameters under the LBA mode.

N: Not necessary to set parameters (The parameter is ignored if it is set.)

N*: May set parameters

D: The device parameter is valid, and the head parameter is ignored.

D*: The command is addressed to the master device, but both the master device and the slave device execute it.

X: Do not care

5.3.2 Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command conpletion are shown as following in this subsection.

Example: READ SECTOR(S) WITH RETRY

At command issuance (I/O registers setting contents)

Bit 7 6 5 4 3 2 1 0

1F7

H

(CM)

1F6

H

(DH)

0

×

0

L

1 0 0 0 0 0

×

DV Head No. / LBA [MSB]

1F5

H

(CH) Start cylinder address [MSB] / LBA

1F4

H

(CL) Start cylinder address [LSB] / LBA

1F3

H

(SN) Start sector No. / LBA [LSB]

1F2

H

(SC) Transfer sector count

1F1

H

(FR) xx

At command completion (I/O registers contents to be read)

Bit 7 6 5 4 3 2 1 0

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV Head No. / LBA [MSB]

1F5

H

(CH) End cylinder address [MSB] / LBA

1F4

H

(CL) End cylinder address [LSB] / LBA

1F3

H

(SN) End sector No. / LBA [LSB]

1F2

H

(SC) X’00’

1F1

H

(ER) Error information

5-16 C141-E057-01EN

5.3 Host Commands

CM: Command register FR: Features register

DH: Device/Head register ST: Status register

CH: Cylinder High register ER: Error register

CL: Cylinder Low register L: LBA (logical block address) setting bit

SN: Sector Number register DV: Device address. bit

SC: Sector Count register x, xx: Do not care (no necessary to set)

Note:

1.

When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).

2.

At error occurrance, the SC register indicates the remaining sector count of data transfer.

3.

In the table indicating I/O registers contents in this subsection, bit indication is omitted.

(1) READ SECTOR(S) (X’20’ or X’21’)

This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and

Sector Number registers. Number of sectors can be specified to 256 sectors in maximum. To specify 256 sectors reading, ‘00’ is specified. For the DRQ,

INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the specified track, the device reads the target sector.

If an error occurs, retry reads are attempted to read the target sector before reporting an error, irrespective of the R bit setting.

The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition.

Upon the completion of the command execution, command block registers contain the cylinder, head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the last sector read.

If an unrecoverable error occurs in a sector, the read operation is terminated at the sector where the error occured.

C141-E057-01EN 5-17

Interface

Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0

×

L

1 0 0 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

0

R = 0

→ with Retry

R = 1

→ without Retry

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV End head No. /LBA [MSB]

End cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X’C4’)

This command operates similarly to the READ SECTOR(S) command. The device does not generate an interrupt (assertion of the INTRQ signal) on each every sector. An interrupt is generateed after the transfer of a block of sectors for which the number is specified by the SET MULTIPLE MODE command.

5-18 C141-E057-01EN

C141-E057-01EN

5.3 Host Commands

The implementation of the READ MULTIPLE command is identical to that of the

READ SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the

Status register is set only at the start of the data block, and is not set on each sector.

The number of sectors (block count) to be transferred without interruption is specifed by the SET MULTIPLE MODE command. The SET MULTIPLE

MODE command should be executed prior to the READ MULTIPLE command.

When the READ MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector Count register is less than the defined block count (the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors [block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”).

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ MULTIPLE command with an ABORTED COMMAND error.

If an unrecoverable error occurs, reading sector is stopped at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred, and remaining number of sectors that had not transferred after the sector where the error occurred.

An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block.

Figure 5.2 shows an example of the execution of the READ MULTIPLE command.

• Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block)

READ MULTIPLE command specifies;

Number of requested sectors = 9 (Sector Count register = 9)

Number of sectors in incomplete block = remainder of 9/4 =1

5-19

Interface

5-20

Figure 5.2 Execution example of READ MULTIPLE command

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

×

L

0 0 0 1 0 0

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

1

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV End head No. /LBA [MSB]

End cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00

(*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.

C141-E057-01EN

5.3 Host Commands

(3) READ DMA (X’C8’ or X’C9’)

This command operates similarly to the READ SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

• The device controls the assertion or negation timing of the DMARQ signal.

• The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No., and first sector No. fields. At command completion, the logical block address of the last sector and remaining number of sectors of which data was not transferred, like in the CHS mode, are set.

The host system can select the DMA transfer mode by using the SET FEATURES command.

1) Single word DMA transfer mode 0 to 2

2) Multiword DMA transfer mode 0 to 2

3) Ultra DMA transfer mode 0 to 2

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

×

L

0 0 1 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

1

R = 0

with Retry

R = 1

without Retry

C141-E057-01EN 5-21

Interface

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X’40’ or X’41’)

This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt. Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector number of the last sector verified.

If an unrecoverable error occurs, the verify operation is terminated at the sector where the error occurred. The command block registers contain the cylinder, the head, and the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. The Sector Count register indicates the number of sectors that have not been verified.

If a correctable error is found, the device sets the CORR bit of the Status register to 1 after the command is completed (before the device generates an interrupt).

5-22 C141-E057-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0

×

L

0 0 0 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

1

R = 0

→ with Retry

R = 1

→ without Retry

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

×

L

×

DV End head No. /LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X’30’ or X’31’)

This command writes data of sectors from the address specified in the

Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified to 256 sectors in maximum. Data transfer begins at the sector specified in the

Sector Number register. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the the specified track, the device writes the target sector.

If an error occurs when writing to the target sector, retries are attempted before reporting the error, irrespective of the R bit setting.

C141-E057-01EN 5-23

Interface

The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.

If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occured. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred.

Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred.

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0

×

L

1 1 0 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

0

R = 0

→ with Retry

R = 1

→ without Retry

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV End head No. /LBA [MSB]

End cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

5-24 C141-E057-01EN

5.3 Host Commands

(6) WRITE MULTIPLE (X’C5’)

This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.

The implementation of the WRITE MULTIPLE command is identical to that of the WRITE SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE command operation, the DRQ bit of the

Status register is required to set only at the start of the data block, not on each sector.

The number of sectors (block count) to be transferred without interruption is specifed by the SET MULTIPLE MODE command. The SET MULTIPLE

MODE command should be executed prior to the WRITE MULTIPLE command.

When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors [block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”).

If the WRITE MULTIPLE command is issued before the SET MULTIPLE

MODE command is executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE MULTIPLE command with an ABORTED

COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred.

Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block. If an error occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block.

The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual request.

C141-E057-01EN 5-25

Interface

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

×

L

0 0 0 1 0 1

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

1

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV End head No. /LBA [MSB]

End cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00

Error information

(7) WRITE DMA (X’CA’ or X’CB’)

This command operates similarly to the WRITE SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

The device controls the assertion or negation timing of the DMARQ signal.

The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device.

• The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the WRITE SECTOR(S) command.

5-26 C141-E057-01EN

5.3 Host Commands

A host system can select the following transfer mode using the SET FEATURES command.

1) Single word DMA transfer mode 0 to 2

2) Multiword DMA transfer mode 0 to 2

3) Ultra DMA transfer mode 0 to 2

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

×

L

0 0 1 0 1 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

1

R = 0

→ with Retry

R = 1

→ without Retry

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

×

L

×

Error information

DV End head No. /LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(8) WRITE VERIFY (X’3C’)

This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted.

C141-E057-01EN 5-27

Interface

After all sectors are verified, the last interruption (INTRQ for command termination) is generated.

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0

×

L

1 1 1 1 0 0

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

0

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV End head No. /LBA [MSB]

End cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(9) RECALIBRATE (X’1x’, x: X’0’ to X’F’)

This command performs the calibration. Upon receipt of this command, the device sets BSY bit of the Status register and performs a calibration. When the device completes the calibration, the device updates the Status register, clears the

BSY bit, and generates an interrupt.

This command can be issued in the LBA mode.

5-28 C141-E057-01EN

5.3 Host Commands

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0

× xx xx xx xx xx

0

×

0

×

1

DV x xx x x x

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

Note:

Also executable in LBA mode.

(10) SEEK (X’7x’, x : X’0’ to X’F’)

This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt.

The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.

In the LBA mode, this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address.

C141-E057-01EN 5-29

Interface

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0

×

L

1 1 x x x

×

DV Head No. /LBA [MSB] x

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB] xx xx

1

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB] xx

Error information

(11) INITIALIZE DEVICE PARAMETERS (X’91’)

The host system can set the number of sectors per track and the maximum head number (maximum head number is “number of heads minus 1”) per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of

Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.

When the SC register is specified to X’00’, an ABORTED COMMAND error is posted. Other than X’00’ is specified, this command terminates normally.

The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting.

In LBA mode

The device ignores the L bit specification and operates with the CHS mode specification. An accessible area of this command within head moving in the LBA mode is always within a default area. It is recommended that the host system refers the addressable user sectors (total number of sectors) in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command.

5-30 C141-E057-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx

1

×

0

×

0

×

1

DV xx

Number of sectors/track xx

0 0

Max. head No.

0 1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× xx xx xx

× ×

Error infomation

DV

Number of sectors/track

Max. head No.

(12) IDENTIFY DEVICE (X’EC’)

The host system issues the IDENTIFY DEVICE command to read parameter information (512 bytes) from the device. Upon receipt of this command, the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer. The device then sets the DRQ bit of the Status register, and generates an interrupt. After that, the host system reads the information out of the sector buffer. Table 5.4 shows the arrangements and values of the parameter words and the meaning in the buffer.

C141-E057-01EN 5-31

Interface

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

× xx xx xx xx xx

1

×

1

×

0

DV

1 xx

1 0 0

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx

Error information

Word

7-9

10-19

20-21

22

2

3

0

1

4-5

6

Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 7)

Value

X’045A’

*2

X’0000’

*2

X’0000’

*2

X’0000’

Set by a device

X’0000’

X’0004’

Description

General Configuration *1

Number of cylinders *2

Reserved

Number of Heads *2

Undefined

Number of sectors per track *2

Undefined

Serial number (ASCII code, 20 characters, right)

Undefined

Number of ECC bytes transferred at READ LONG or

WRITE LONG command

5-32 C141-E057-01EN

5.3 Host Commands

52

53

54

55

48

49

50

51

56

57-58

59

60-61

62

63

64

65

Word

23-26

27-46

47

Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 7)

66

67

68

69-79

80

81

82

X’0000’

X’0B00’

X’0000’

X’0200’

X’0000’

X’0007’

(Variable)

(Variable)

(Variable)

(Variable)

*6

Value

Set by a device

X’8010’

*2

X’0000’

X’xx07’

X’0003’

X’0078’

X’0078’

X’00F0’

X’0078’

X’0000’

X’001E’

X’0000’

X’346B’

Description

Firmware revision (ASCII code, 8 characters, left)

Model name (ASCII code, 40 characters, left)

Maximum number of sectors per interrupt on

READ/WRITE MULTIPLE command

Reserved

Capabilities *3

Reserved

PIO data transfer mode *4

Reserved

Enable/disable setting of words 54-58 and 64-70, 88 *5

Number of current Cylinders

Number of current Head

Number of current sectors per track

Total number of current sectors

Transfer sector count currently set by READ/WRITE

MULTIPLE command *6

Total number of user addressable sectors (LBA mode only)

*2

Reserved

Multiword DMA transfer mode *7

Advance PIO transfer mode support status *8

Minimum multiword DMA transfer cycle time per word :

120 [ns]

Manufacturer’s recommended DMA transfer cycle time :

120 [ns]

Minimum PIO transfer cycle time without IORDY flow control : 240 [ns]

Minimum PIO transfer cycle time with IORDY flow control

: 120 [ns]

Reserved

Major version number *9

Minor version number (not reported)

Support of command sets *10

C141-E057-01EN 5-33

Interface

Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 7)

Word

83

84

85

86

87

88

89-127

128

129-159

160-255

Value

X’4008’

X’4000’

*12

*13

X’4000’

X’xx07’

X’0000’

(Variable)

X’0000’

X’0000’

Valid of command sets/function *12

Valid of command sets/function *13

Default of command sets/function

Ultra DMA transfer mode *14

Reserved

Security status *15

Undefined

Reserved

Description

Support of command sets *11

Support of command sets/function

Table 5.4 Information to be read by IDENTIFY DEVICE command (4 of 7)

*1 Word 0: General configuration

Bit 15: ATA device = 0, ATAPI device = 1

Bit 14-8: Undefined

Bit 7:

Bit 6:

Removable disk drive = 1

Fixed drive = 1

Bit 5-1: Undefined

Bit 0: Reserved

*2 Word 1, 3, 6, 60-61

Word 01

Word 03

Word 06

Word 60-01

MHE2064AT MHE2043AT MHF2043AT

X’3470’

X’0F’

X’22F0’

X’0F’

X’22F0’

X’0F’

X’3F’

X’80F7F0’

X’3F’

X’80F7F0’

X’3F’

X’80F7F0’

*3 Word 49: Capabilities

Bit 15-14: Reserved

Bit 13: Standby timer value. Factory default is 0.

Bit 12:

Bit 11:

Reserved

IORDY support

Bit 10: IORDY inhibition

Bit 9-0: Undefined

1=Supported

0=Disable inhibition

MHF2021AT

X’1068’

X’10’

X’3F’

X’409980’

5-34 C141-E057-02EN

5.3 Host Commands

Table 5.4 Information to be read by IDENTIFY DEVICE command (5 of 7)

Bit 9, 8: Always 1

*4 Word 51: PIO data transfer mode

Bit 15-8: PIO data transfer mode

Bit 7-0: Undefined

X’02’=PIO mode 2

*5 Word 53: Enable/disable setting of word 54-58 and 64-70

Bit 15-3: Reserved

Bit 2:

Bit 1:

Bit 0:

Enable/disable setting of word 88

Enable/disable setting of word 64-70

Enable/disable setting of word 54-58

1=Enable

1=Enable

1=Enable

*6 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command

Bit 15-9: Reserved

Bit 8: Multiple sector transfer 1=Enable

Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE command without interrupt supports 2, 4, 8 and 16 sectors.

*7 Word 63: Multiword DMA transfer mode

Bit 15-8: Currently used multiword DMA transfer mode

Bit 7-0: Supportable multiword DMA transfer mode

Bit 2=1 Mode 2

Bit 1=1 Mode 1

Bit 0=1 Mode 0

*8 Word 64: Advance PIO transfer mode support status

Bit 15-8: Reserved

Bit 7-0: Advance PIO transfer mode

Bit 1 = 1 Mode 4

Bit 0 = 1 Mode 3

*9 WORD 80

Bit 15-5: Reserved

Bit 4:

Bit 3:

ATA/ATAPI-4 supported = 1

ATA-3 supported = 1

C141-E057-01EN 5-35

Interface

Table 5.4 Information to be read by IDENTIFY DEVICE command (6 of 7)

Bit 2:

Bit 1:

ATA-2 supported = 1

ATA-1 supported = 1

Bit 0:

*10 WORD 82

Undefined

Bit 15: Undefined

Bit 14:

Bit 13:

Bit 12:

Bit 11:

Bit 10:

Bit 9:

Bit 8:

Bit 7:

Bit 6:

'1' = Supports the NOP command.

'1' = Supports the READ BUFFER command.

'1' = Supports the WRITE BUFFER command.

Undefined

'1' = Supports the Host Protected Area feature set.

'1' = Supports the DEVICE RESET command.

'1' = Supports the SERVICE interrupt.

'1' = Supports the release interrupt.

'1' = Supports the read cache function.

Bit 5:

Bit 4:

Bit 3:

Bit 2:

'1' = Supports the write cache function.

'1' = Supports the PACKET command feature set.

'1' = Supports the power management feature set.

'1' = Supports the Removable Media feature set.

Bit 1:

Bit 0:

'1' = Supports the Security Mode feature set.

'1' = Supports the SMART feature set.

*11 WORD 83

Bits 15-5: Undefined

Bit 4:

Bit 3:

Bit 2:

Bit 1:

Bit 0:

'1' = Supports the Removable Media Status Notification feature

set.

'1' = Supports the Advanced Power Management feature set.

'1' = Supports the CFA (Compact Flash Association) feature set.

'1' = Supports the READ/WRITE DMA QUEUED command.

'1' = Supports the DOWNLOAD MICROCODE command.

5-36 C141-E057-01EN

5.3 Host Commands

Table 5.4 Information to be read by IDENTIFY DEVICE command (7 of 7)

*12 WORD 85

Bits 15-9 : Same definition as WORD 82.

Bit 8 : '1' = Enables the SERVICE interrupt.

Bit 7: '1' = Enables the release interrupt.

Bit 6: '1' = Enables the read cache function.

Bit 5: '1' = Enables the write cache function.

Bits 4-2: '1' = Same definition as WORD 82.

Bit 1:

Bit 0:

'1' = Enables the Security Mode function.

'1' = Enables the SMART function.

*13 WORD 86

Bits 15-5: '1' = Reserved

Bit 4:

Bit 3:

'1' = Enables the Removable Media Status Notification function.

'1' = Enables the Advanced Power Management function.

Bits 2-0: Same definition as WORD 83.

*14 WORD 88

Bit 15-8: Currently used Ultra DMA transfer mode

Bit 7-0: Supportable Ultra DMA transfer mode

Bit 2 = ‘1’: Mode 2

Bit 1 = ‘1’: Mode 1

Bit 0 = ‘1’: Mode 0

*15 WORD 128

Bit 15-9: Reserved

Bit 8: Security level. 0: High, 1: Maximum

Bit 7-5: Reserved

Bit 4:

Bit 3:

1: Security counter expired

1: Security frozen

Bit 2:

Bit 1:

Bit 0:

1: Security locked

1: Security enabled

1: Security supported

C141-E057-01EN 5-37

Interface

(13) IDENTIFY DEVICE DMA (X’EE’)

When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

× xx xx xx xx xx

1

×

1

×

0

DV

1 xx

1 1 0

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx

Error information

(14) SET FEATURES (X’EF’)

The host system issues the SET FEATURES command to set parameters in the

Features register for the purpose of changing the device features to be executed.

For the transfer mode (Feature register = 03), detail setting can be done using the

Sector Count register.

Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register. Then, the device clears the BSY bit, and generates an interrupt.

If the value in the Features register is not supported or it is invalid, the device posts an ABORTED COMMAND error.

Table 5.5 lists the available values and operational modes that may be set in the

Features register.

5-38 C141-E057-01EN

5.3 Host Commands

Table 5.5 Features register values and settable modes

Features Register

X’02’

X’03’

X’05’

X’55’

X’66’

X’82’

X’85’

X’AA’

X’BB’

X’CC’

Drive operation mode

Enables the write cache function.

Transfer mode depends on the contents of the Sector Count register.

(Details are given later.)

Enables the advanced power management function.

Disables read cache function.

Disables the reverting to power-on default settings after software reset.

Disables the write cache function.

Disables the advanced power management function.

Enables the read cache function.

Specifies the transfer of 4-byte ECC for READ LONG and WRITE

LONG commands.

Enables the reverting to power-on default settings after software reset.

At power-on or after hardware reset, the default mode is the same as that is set with a value greater than X’85’ (except for write cache). If X’66’ is specified, it allows the seting value greater than X’AA’ which may have been modified to a new value since power-on, to remain the same even after software reset.

C141-E057-01EN 5-39

Interface

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx

1

×

1

×

1 0 1

×

DV xx xx xx or transfer mode

[See Table 5.5]

1 1 1

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx

Error information

The host sets X’03’ to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected.

Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value.

The IDD supports following values in the Sector Count register value. If other value than below is specified, an ABORTED COMMAND error is posted.

PIO default transfer mode

PIO flow control transfer mode X

00000 000 (X’00’)

00001 000 (X’08’: Mode 0)

00001 001 (X’09’: Mode 1)

00001 010 (X’0A’: Mode 2)

00001 011 (X’0B’: Mode 3)

00001 100 (X’0C’: Mode 4)

5-40 C141-E057-01EN

5.3 Host Commands

Single word DMA transfer mode X 00010 000 (X’10’: Mode 0)

Multiword DMA transfer mode X

00010 001 (X’11’: Mode 1)

00010 010 (X’12’: Mode 2)

00100 000 (X’20’: Mode 0)

Ultra DMA transfer mode X

00100 001 (X’21’: Mode 1)

00100 010 (X’22’: Mode 2)

01000 000 (X’40’: Mode 0)

01000 001 (X’41’: Mode 1)

01000 010 (X’42’: Mode 2)

The host writes the Sector Count register with the desired power management level and executes this command with the Features register X’05’, and then

Advanced Power Management is enabled.

Level

Power management without standby

Power management with standby

Reserved

Sector Count register

80h-FEh

01h-7Fh

FFh, 00h

(15) SET MULTIPLE MODE (X’C6’)

This command enables the device to perform the READ MULTIPLE and

WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command.

The number of sectors per block is written into the Sector Count register. The

IDD supprots 2, 4, 8, 16 and 32 (sectors) as the block counts.

Upon receipt of this command, the device sets the BSY bit of the Status register and checks the contents of the Sector Count register. If the contents of the Sector

Count register is valid and is a supported block count, the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands. Execution of these commands is then enabled. If the value of the Sector Count register is not a supported block count, an ABORTED COMMAND error is posted and the

READ MULTIPLE and WRITE MULTIPLE commands are disabled.

If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued, the READ MULTIPLE and WRITE MULTIPLE commands are disabled.

C141-E057-02EN 5-41

Interface

When the SET MULTIPLE MODE command operation is completed, the device clears the BSY bit and generates an interrupt.

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx

1

×

1

×

0 0 0

×

DV xx xx

Sector count/block xx

1 1 0

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx

Sector count/block

Error information

After power-on or after hardware reset, the READ MULTIPLE and WRITE

MULTIPLE command operation are disabled as the default mode.

The mode established before software reset is retained if disable default (Features

Reg. = 66h setting) has been defined by the SET FEATURES command. If disable default has not been defined after the software is the READ MULTIPLE and WRITE MULTIPLE commands are disabled.

The parameters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below. See

Subsection 5.32 for the IDENTIFY DEVICE command.

5-42 C141-E057-01EN

5.3 Host Commands

Word 47

Bit 7-0 = 10:

Word 59 = 0000:

= 00xx:

Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are

16 (fixed).

The READ MULTIPLE and WRITE MULTIPLE commands are disabled.

The READ MULTIPLE and WRITE MULTIPLE commands are enabled. “xx” indicates the current setting for number of sectors that can be transferred per interrupt by the READ MULTIPLE and

WRITE MULTIPLE commands.

e.g. 0010 = Block count of 16 has been set by the SET

MULTIPLE MODE command.

(16) SET MAX ADDRESS (F9)

This command allows the maximum address accessible by the user to be set in

LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers.

Then, it clears BSY and generates an interrupt.

The new address information set by this command is reflected in Words 1, 54, 57,

58, 60 and 61 of IDENTIFY DEVICE information. If an attempt is made to perform a read or write operation for an address beyond the new address space, an

ID Not Found error will result.

When SC register bit 0, VV (Value Volatile), is 1, the value set by this command is held even after power on and the occurrence of a hard reset. When the VV bit is

0, the value set by this command becomes invalid when the power is turned on or a hard reset occurs, and the maximum address returns to the value (default value if not set) most lately set when VV bit = 1.

After power on and the occurrence of a hard reset, the host can issue this command only once when VV bit = 1. If this command with VV bit = 1 is issued twice or more, any command following the first time will result in an Aborted

Command error.

C141-E057-01EN 5-43

Interface

At command issuance (I/O registers setting contents)

1F7

1F6

H

H

(CM)

(DH)

1

×

1

L

1 1 1 0 0

×

DV Max head/LBA [MSB]

1

1F5

H

(CH) Max. cylinder [MSB]/Max. LBA

1F4

H

(CL) Max. cylinder [MSB]/Max. LBA

1F3

H

(SN) Max. sector/Max. LBA [LSB]

1F2

H

(SC) xx

1F1

H

(FR) xx

VV

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV Max head/LBA [MSB]

1F5

H

(CH) Max. cylinder [MSB]/Max. LBA

1F4

H

(CL) Max. cylinder [MSB]/Max. LBA

1F3

H

(SN) Max. sector/Max. LBA [LSB]

1F2

H

(SC) xx

1F1

H

(ER) Error information

(17) READ NATIVE MAX ADDRESS (F8)

This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command. Upon receipt of this command, the device sets the BSY bit and indicates the maximum address in the DH, CH, CL and SN registers. Then, it clears BSY and generates an interrupt.

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

× xx xx xx xx xx

1

L

1 1 1

×

DV xx

0 0 1

5-44 C141-E057-01EN

5.3 Host Commands

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× × ×

DV Max head/LBA [MSB]

Max. cylinder [MSB]/Max. LBA

Max. cylinder [MSB]/Max. LBA

Max. sector/Max. LBA [LSB] xx

Error information

(18) EXECUTE DEVICE DIAGNOSTIC (X’90’)

This command performs an internal diagnostic test (self-diagnosis) of the device.

This command usually sets the DRV bit of the Drive/Head register is to 0

(however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis.

If device 1 is present:

Both devices shall execute self-diagnosis.

• The device 0 waits for up to 5 seconds until device 1 asserts the PDIAGsignal.

If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall append X’80’ to its own diagnostic status.

• The device 0 clears the BSY bit of the Status register and generates an interrupt. (The device 1 does not generate an interrupt.)

A diagnostic status of the device 0 is read by the host system. When a diagnostic failure of the device 1 is detected, the host system can read a status of the device 1 by setting the DV bit (selecting the device 1).

When device 1 is not present:

• The device 0 posts only the results of its own self-diagnosis.

• The device 0 clears the BSY bit of the Status register, and generates an interrupt.

Table 5.6 lists the diagnostic code written in the Error register which is 8-bit code.

If the device 1 fails the self-diagnosis, the device 0 “ORs” X’80’ with its own status and sets that code to the Error register.

C141-E057-01EN 5-45

Interface

Code

X’01’

X’03’

X’05’

X’8x’

Table 5.6 Diagnostic code

Result of diagnostic

No error detected.

Data buffer compare error

ROM sum check error

Failure of device 1 attention: The device responds normally to this command without excuting internal diagnostic test.

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

× xx xx xx xx xx

0

×

0 1 0 0 0 0

×

DV

Head No. /LBA

[

MSB]

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV

Head No. /LBA

[

MSB] xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx

01

01

H

H

(*1)

Diagnostic code

*1 This register indicates X’00’ in the LBA mode.

5-46 C141-E057-01EN

5.3 Host Commands

(19) READ LONG (X’22’ or X’23’)

This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE

LONG command.

Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command.

The READ LONG command supports only single sector operation.

At command issuance (I/O registers setting contents)

1F7

1F6

H

H

(CM)

(DH)

0

×

0

L

1 0 0 0 1 R

×

DV Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Sector No. / LBA [LSB]

01 xx

R = 0

→ with Retry

R = 1

→ without Retry

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

×

00 (*1)

L

×

Error information

DV

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB]

Head No. /LBA [MSB]

*1 If the command is terminated due to an error, this register indicates 01.

C141-E057-01EN 5-47

Interface

(20) WRITE LONG (X’32’ or X’33’)

This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE

LONG command supports only single sector operation.

The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command.

This command is operated under the following conditions:

The command is issued in a sequence of the READ LONG or WRITE LONG

(to the same address) command issuance. (WRITE LONG command can be continuously issued after the READ LONG command.)

If above condition is not satisfied, the command operation is not guaranteed.

At command issuance (I/O registers setting contents)

1F7

1F6

H

H

(CM)

(DH)

0

×

0

L

1 1 0 0 1 R

×

DV Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Sector No. / LBA [LSB]

01 xx

R = 0

→ with Retry

R = 1

→ without Retry

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

×

L

×

DV Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, this register indicates 01.

5-48 C141-E057-01EN

5.3 Host Commands

(21) READ BUFFER (X’E4’)

The host system can read the current contents of the sector buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up the sector buffer for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer.

At command issuance (I/O registers setting contents)

1 0 1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx

1

× xx

1

×

1 1 0

×

DV xx

0

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

(22) WRITE BUFFER (X’E8’)

The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data. After that, 512 bytes of data is transferred from the host and the device writes the data to the sector buffer, then generates an interrupt.

C141-E057-01EN 5-49

Interface

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

× xx xx xx xx xx

1

×

1

×

1

DV

1 xx

0 0 0

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx

Error information

(23) IDLE (X’97’ or X’E3’)

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.

By using this command, the automatic power-down function is enabled and the timer immediately starts the countdown. When the timer reaches the specified value, the device enters standby mode.

Enabling the automatic power-down function means that the device automatically enters the standby mode after a certain period of time. When the device enters the idle mode, the timer starts countdown. If any command is not issued while the timer is counting down, the device automatically enters the standby mode. If any command is issued while the timer is counting down, the timer is initialized and the command is executed. The timer restarts countdown after completion of the command execution.

The period of timer count is set depending on the value of the Sector Count register as shown below.

5-50 C141-E057-01EN

C141-E057-01EN

5.3 Host Commands

Sector Count register value Point of timer

0 [X’00’] 30 minutes

1 to 3

4 to 240

[X’01’ to X’03’]

[X’04’ to X’F0’]

15 seconds

(Value

×

5) seconds

241 to 251 [X’F1’ to X’FB’] 30 minutes

252 [X’FC’] 21 minutes

253 [X’FD’] 30 minutes

254 to 255 [X’FE’ to X’FF’] 21 minutes 15 seconds attention: The automatic power-down is excuted if no command is coming for

30 min.

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’97’ or X’E3’

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx

Period of timer xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

5-51

Interface

(24) IDLE IMMEDIATE (X’95’ or X’E1’)

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function.

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’95’ or X’E1’

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx

Error information

(25) STANDBY (X’96’ or X’E2’)

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.

By using this command, the automatic power-down function is enabled and the timer starts the countdown when the device returns to idle mode.

When the timer value reaches 0 (a specified time has padded), the device enters standby mode.

5-52 C141-E057-01EN

5.3 Host Commands

Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as the READ SECTOR(s) command is received, the device processes the command after driving the spindle motor.

attention: The automatic power-down is excuted if no command is coming for

30 min.

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’96’ or X’E2’

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx

Period of timer xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

(26) STANDBY IMMEDIATE (X’94’ or X’E0’)

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the automatic power-down sequence.

C141-E057-01EN 5-53

Interface

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’94’ or X’E0’

1F6

H

(DH)

× × ×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx

Error information

(27) SLEEP (X’99’ or X’E6’)

This command is the only way to make the device enter the sleep mode.

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the sleep mode.

In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. All I/O register outputs are in high-impedance state.

The only way to release the device from sleep mode is to execute a software or hardware reset.

5-54 C141-E057-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’99’ or X’E6’

1F6

H

(DH)

× × ×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

(28) CHECK POWER MODE (X’98’ or X’E5’)

The host checks the power mode of the device with this command.

The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers.

The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt.

Power save mode

• During moving to standby mode

• Standby mode

• During returning from the standby mode

• Idle mode

• Active mode

Sector Count register

X’00’

X’FF’

X’FF’

C141-E057-01EN 5-55

Interface

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’98’ or X’E5’

1F6

H

(DH)

× × ×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH)

× × ×

DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx

X’00’ ,X’80’ or X’FF’

Error information

(29) SMART (X’B0)

This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted Command error is posted.

It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command. If the keys are set incorrectly, the

Aborted Command error is posted.

In the default setting, the failure prediction feature is enabled.

The device collects or updates several items to forecast failures. In the following sections, the values of items collected or updated by the device to forecast failures are referred to as attribute values.

5-56 C141-E057-01EN

5.3 Host Commands

Table 5.7 Features Register values (subcommands) and functions

Features Resister

X’D0’

X’D1’

X’D2’

X’D3’

X’D8’

X’D9’

Function

SMART Read Attribute Values:

A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the

BSY bit and transfers 512-byte attribute value information to the host.

* For infomation about the format of the attribute value information, see Table 5.8.

SMART Read Attribute Thresholds:

This subcommand is used to transfer 512-byte insurance failure threshold value data to the host.

* For infomation about the format of the insurance failure threshold value data, see Table 5.9.

SMART Enable-Disable Attribute AutoSave:

This subcommand is used to enable (SC register

00h) or disable

(SC register = 00h) the setting of the automatic saving feature for the device attribute data. The setting is maintained every time the device is turned off and then on. When the automatic saving feature is enabled, the attribute values are saved before the device enters the power saving mode. However, if the failure prediction feature is disabled, the attribute values are not automatically saved.

When the device receives this subcommand, it asserts the BSY bit, enables or disables the automatic saving feature, then clears the

BSY bit.

SMART Save Attribute Values:

When the device receives this subcommand, it asserts the BSY bit, saves device attribute value data, then clears the BSY bit.

SMART Enable Operations:

This subcommand enables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, enables the failure prediction feature, then clears the BSY bit.

SMART Disable Operations:

This subcommand disables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, disables the failure prediction feature, then clears the BSY bit.

C141-E057-01EN 5-57

Interface

Features Resister

X’DA’

Function

SMART Return Status:

When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values. If there is an attribute value exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers. If there are no attribute values exceeding the thresholds, 4Fh and C2h are loaded into the CL and CH registers. After the settings for the CL and CH registers have been determined, the device clears the BSY bit

The host must regularly issue the SMART Read Attribute Values subcommand

(FR register = D0h), SMART Save Attribute Values subcommand (FR register =

D3h), or SMART Return Status subcommand (FR register = DAh) to save the device attribute value data on a medium.

Alternative, the device must issue the SMART Enable-Disable Attribute

AutoSave subcommand (FR register = D2h) to use a feature which regularly save the device attribute value data to a medium.

The host can predict failures in the device by periodically issuing the SMART

Return Status subcommand (FR register = DAh) to reference the CL and CH registers.

If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of its life . In this case, the host recommends that the user quickly backs up the data.

1F7

H

At command issuance (I-O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

×

0

×

Key (C2h)

Key (4Fh) xx xx

Subcommand

1

×

1

DV

0 xx

0 0 0

5-58 C141-E057-01EN

5.3 Host Commands

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

× × ×

DV xx

Key-failure prediction status (C2h-2Ch)

Key-failure prediction status (4Fh-F4h) xx xx

Error information

The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is

512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Thresholds subcommand (FR register =

D1h).

Table 5.8 Format of device attribute value data

Byte

00

01

02

03

04

05

06

Data format version number

Attribute 1

07 to 0C

0D

0E to 169 Attribute 2 to attribute 30

16A

16B

16C, 16D

Off-line data collection

Attribute ID

Status flag

Item

Current attribute value

Attribute value for worst case so far

Raw attribute value

Reserved

(The format of each attribute value is the same as that of bytes 02 to 0D.)

Off-line data collection status

Number of off-line data collection segments

Time required for next segments [sec].

16E

16F

170

171

172 to 181 Reserved

182 to 1FE Vendor unique

1FF Check sum

Current segment pointer

Off-line data collection capability

Failure prediction capability flag

C141-E057-01EN 5-59

Interface

5-60

Table 5.9 Format of insurance failure threshold value data

Byte Item

00

01

02

03

Data format version number

Attribute 1

04 to 0D Threshold 1

(Threshold of attribute 1)

0E to 169 Threshold 2 to threshold 30

Attribute ID

Insurance failure threshold

Reserved

(The format of each threshold value is the same as that of bytes 02 to 0D.)

16A to 17B Reserved

17C to 1FE Unique to vendor

1FF Check sum

Data format version number

The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated.

Attribute ID

The attribute ID is defined as follows:

Attribute ID

9

10

7

8

2

3

4

5

0

1

Attribute name

(Indicates unused attribute data.)

Read error rate

Throughput performance

Spin up time

Start/stop count

Re-allocated sector count

Seek error rate

Seek time performance

Power-on time

Number of retries made to activate the spindle motor

C141-E057-01EN

5.3 Host Commands

Attribute ID Attribute name

12 Number of power-on-power-off times

13 to 198 (Reserved)

199

200

Ultra ATA CRC error rate

Write error rate

201 to 255 (Unique to vendor)

Status Flag

Bit

0

1

2

3

4

5

6 to 15

Meaning

If this bit 1, it indicates that if the attribute exceeds the threshold, it is the attribute covered by the drive warranty.

If this bit is 1 (0), it indicates the attribute only updated by an online test (off-line test).

If this bit 1, it indicates the attribute that represents performance.

If this bit 1, it indicates the attribute that represents an error rate.

If this bit 1, it indicates the attribute that represents the number of occurrences.

If this bit 1, it indicates the attribute that can be collected/saved even if the drive fault prediction function is disabled.

Reserve bit

• Current attribute value

The current attribute value is the normalized raw attribute data. The value varies between 01h and 64h. The closer the value gets to 01h, the higher the possibility of a failure. The device compares the attribute values with thresholds. When the attribute values are larger than the thresholds, the device is operating normally.

• Attribute value for the worst case so far

This is the worst attribute value among the attribute values collected to date.

This value indicates the state nearest to a failure so far.

Raw attribute value

Raw attributes data is retained.

• Off-line data collection status

Bits 0 to 6: Indicates the situation of off-line data collection according to the table below.

C141-E057-01EN 5-61

Interface

5-62

Bit 7:

Status Byte

0

2

3

4

5

6

If this bit is 1, it indicates that the automatic off-line data collection function is enabled.

Meaning

Off-line data collection is not started.

Off-line data collection has been completed normally.

Off-line data collection is in progress.

Off-line data collection has been suspended by a command interrupt.

Off-line data collection has been aborted by a command interrupt.

Off-line data collection has been aborted by a fatal error.

Number of off-line data collection segments

Indicates the number of segments required to terminate off-line data collection.

• Time required for next segment [sec]

Indicates the time required to terminate the next segment.

Current segment pointer

Indicates the number of the next segment to be executed.

Off-line data collection capability

Indicates the method of off-line data collection carried out by the drive. If the off-line data collection capability is 0, it indicates that off-line data collection is not supported.

Bit

0

1

2

Meaning

Indicates that Execute Off-Line Immediate is supported.

Vendor unique

Indicates that off-line data collection being executed is aborted when a new command is received.

Failure prediction capability flag

Bit 0: The attribute value data is saved to a media before the device enters power saving mode.

Bit 1: The device automatically saves the attribute value data to a media after the previously set operation.

Bits 2 to 15: Reserved bits

C141-E057-01EN

5.3 Host Commands

Check sum

Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning.

Insurance failure threshold

The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure.

(30) SECURITY DISABLE PASSWORD (F6h)

This command invalidates the user password already set and releases the lock function.

The host transfers the 512-byte data shown in Table 5.10 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET

PASSWORD command and reset the user password.

If the user password or master password transferred from the host does not match, the Aborted Command error is returned.

Issuing this command while in LOCKED MODE or FROZEN MODE returns the

Aborted Command error.

(The section about the SECURITY FREEZE LOCK command describes

LOCKED MODE and FROZEN MODE.)

C141-E057-01EN 5-63

Interface

Table 5.10 Contents of security password

Word

0

Contents

Control word

Bit 0: Identifier

0 = Compares the user passwords.

1 = Compares the master passwords.

Bits 1 to 15: Reserved

1 to 16 Password (32 bytes)

17 to 255 Reserved

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents))

1

×

1

×

1

DV

0 xx

1 xx xx xx xx

1

× xx

1 0

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

(31) SECURITY ERASE PREPARE (F3h)

The SECURITY ERASE UNIT command feature is enabled by issuing the

SECURITY ERASE PREPARE command and then the SECURITY ERASE

UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command.

Issuing this command during FROZEN MODE returns the Aborted Command error.

5-64 C141-E057-01EN

5.3 Host Commands

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1

×

1

×

1

DV

0 xx

0 xx xx xx xx xx

1

×

1 1

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

(32) SECURITY ERASE UNIT (F4h)

This command erases all user data. This command also invalidates the user password and releases the lock function.

The host transfers the 512-byte data shown in Table 5.10 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set. The device erases user data, invalidates the user password, and releases the lock function if the passwords are the same.

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET

PASSWORD command and reset the user password.

If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned.

Issuing this command while in FROZEN MODE returns the Aborted Command error.

C141-E057-01EN 5-65

Interface

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1

×

1

×

1

DV

0 xx

1 xx xx xx xx xx

1

×

0 0

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

(33) SECURITY FREEZE LOCK (F5h)

This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.

SECURITY SET PASSWORD

SECURITY UNLOCK

• SECURITY DISABLE PASSWORD

• SECURITY ERASE UNIT

FROZEN MODE is canceled when the power is turned off. If this command is reissued in FROZEN MODE, the command is completed and FROZEN MODE remains unchanged.

Issuing this command during LOCKED MODE returns the Aborted Command error.

The following medium access commands return the Aborted Command error when the device is in LOCKED MODE:

5-66 C141-E057-01EN

5.3 Host Commands

READ DMA

READ LONG

WRITE DMA

WRITE LONG

SECURITY DISABLE PASSWORD

SECURITY FREEZE LOCK

READ MULTIPLE

WRITE MULTIPLE

SECURITY SET PASSWORD

READ SECTORS

WRITE SECTORS

WRITE VERIFY

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1

×

1

×

1

DV

0 xx

1 xx xx xx xx

1

× xx

0 1

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

C141-E057-01EN 5-67

Interface

(34) SECURITY SET PASSWORD (F1h)

This command enables a user password or master password to be set.

The host transfers the 512-byte data shown in Table 1.2 to the device. The device determines the operation of the lock function according to the specifications of the

Identifier bit and Security level bit in the transferred data. (Table 1.3)

Issuing this command in LOCKED MODE or FROZEN MODE returns the

Aborted Command error.

Table 5.11 Contents of SECURITY SET PASSWORD data

Word Contents

0 Control word

Bit 0 Identifier

0 = Sets a user password.

1 = Sets a master password.

Bits 1 to 7 Reserved

Bit 8 Security level

0 = High

1 = Maximum

Bits 9 to 15 Reserved

1 to 16 Password (32 bytes)

17 to 255 Reserved

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5.3 Host Commands

Table 5.12 Relationship between combination of Identifier and Security level, and operation of the lock function

Indentifier

User

Master

User

Master

Level Description

High

High

The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password or the master password already set.

The specified password is saved as a new master password.

The lock function is not enabled.

Maximum The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password only. The master password already set cannot cancel

LOCKED MODE.

Maximum The specified password is saved as a new master password.

The lock function is not enabled.

(35) SECURITY UNLOCK

This command cancels LOCKED MODE.

The host transfers the 512-byte data shown in Table 1.1 to the device. Operation of the device varies as follows depending on whether the host specifies the master password.

When the master password is selected

When the security level is LOCKED MODE is high, the password is compared with the master password already set. If the passwords are the same, LOCKED MODE is conceled. Otherwise, the Aborted Command error is returned. If the security level in LOCKED MODE is set to the highest level, the Aborted Command error is always returned.

When the user password is selected

The password is compared with the user password already set. If the passwords are the same, LOCKED MODE is conceled. Otherwise, the

Aborted Command error is returned.

If the password comparison fails, the device decrements the UNLOCK counter.

The UNLOCK counter initially has a value of five. When the value of the

UNLOCK counter reaches zero, this command or the SECURITY ERASE UNIT command causes the Aborted Command error until te device is turned off and then on, or until a hardware reset is executed. Issuing this command with

LOCKED MODE conceled (in UNLOCK MODE) has no affect on the UNLOCK counter.

C141-E057-01EN 5-69

Interface

Issuing this command in FROZEN MODE returns the Aborted Command error.

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1

× xx xx xx xx xx

1

×

1

×

1

DV

0 xx

0 0

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

1

(36) FLUSH CACHE (E7)

This command is used to order to write every write cache data stored by the device into the medium. BSY bit is held at "1" until every data has been written normally or a error has occurred. The device performs every error recovery so that the data are read correctly.

When executing this command, the reading of the data may take several seconds if much data are to be read.

In case a non-recoverable error has occurred while the data is being read, the error generation address is put into the command block register before ending the command. This error sector is deleted from the write cache data, and the remaining cache data is written into the medium by the execution of the next

Flush Cache command.

5-70 C141-E057-01EN

5.3 Host Commands

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1

× xx

1

×

1

×

0

DV

0 xx

1 xx xx xx xx

1 1

At command completion (I-O register contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information

× xx xx xx xx

× ×

Error information

DV xx

5.3.3 Error posting

Table 5.7 lists the defined errors that are valid for each command.

Table 5.13 Command code and parameters (1 of 2)

Command name

READ SECTOR(S)

WRITE SECTOR(S)

READ MULTIPLE

WRITE MULTIPLE

READ DMA

WRITE DMA

WRITE VERIFY

READ VERIFY SECTOR(S)

V: Valid on this command

Error register (X’1F1’) Status register (X’1F7’)

BBK UNC INDF ABRT TK0NF DRDY DWF ERR

V

V

V V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

*: See the command descriptioms.

C141-E057-01EN 5-71

Interface

Table 5.13 Command code and parameters (2 of 2)

Command name

RECALIBRATE

SEEK

INITIALIZE DEVICE PARAMETERS

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

SET MULTIPLE MODE

SET MAX ADDRESS

READ NATIVE MAX ADDRESS

EXECUTE DEVICE DIAGNOSTIC

READ LONG

WRITE LONG

READ BUFFER

WRITE BUFFER

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

SLEEP

CHECK POWER MODE

SMART

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

FLUSH CACHE

Invalid command

V: Valid on this command

*: See the command descriptioms.

Error register (X’1F1’) Status register (X’1F7’)

BBK UNC INDF ABRT TK0NF DRDY DWF ERR

V

V

V

V V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

*

V

V

* *

V

V

V

V

V

V

V

V

V

V

V

V

* *

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

5-72 C141-E057-01EN

5.4 Command Protocol

5.4 Command Protocol

The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.

Commands can be executed only when the DRDY bit of the Status register is 1.

However, the following commands can be executed even if DRDY bit is 0.

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

5.4.1 Data transferring commands from device to host

The execution of the following commands involves data transfer from the device to the host.

• IDENTIFY DEVICE.

IDENTIFY DEVICE DMA

READ SECTOR(S)

READ LONG

READ BUFFER

SMART

The execution of these commands includes the transfer one or more sectors of data from the device to the host. In the READ LONG command, 516 bytes are transferred. Following shows the protocol outline.

a) The host writes any required parameters to the Features, Sector Count, Sector

Number, Cylinder, and Device/Head registers.

b) The host writes a command code to the Command register.

c) The device sets the BSY bit of the Status register and prepares for data transfer.

d) When one sector of data is available for transfer to the host, the device sets

DRQ bit and clears BSY bit. The drive then asserts INTRQ signal.

e) After detecting the INTRQ signal assertion, the host reads the Status register.

The host reads one sector of data via the Data register. In response to the

Status register being read, the device negates the INTRQ signal.

f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the BSY bit and steps d) and after are repeated.

Even if an error is encountered, the device prepares for data transfer by setting the

DRQ bit. Whether or not to transfer the data is determined for each host. In other

C141-E057-01EN 5-73

Interface

words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting.

Figure 5.3 shows an example of READ SECTOR(S) command protocol, and

Figure 5.4 shows an example protocol for command abort.

Figure 5.3 Read Sector(s) command protocol

Note:

For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the

DRQ setting by the device to 50 ms after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last

5-74 C141-E057-01EN

5.4 Command Protocol

sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.

When the host new command even if the device requests the data transfer (setting in DRQ bit), the correct device operation is not guaranteed.

Figure 5.4 Protocol for command abort

5.4.2 Data transferring commands from host to device

The execution of the following commands involves Data transfer from the host to the drive.

WRITE SECTOR(S)

• WRITE LONG

• WRITE BUFFER

WRITE VERIFY

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

SECURITY SET PASSWORD

SECURITY UNCLOK

The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline.

a) The host writes any required parameters to the Features, Sector Count, Sector

Number, Cylinder, and Device/Head registers.

C141-E057-01EN 5-75

Interface

b) The host writes a command code in the Command register. The drive sets the

BSY bit of the Status register.

c) When the device is ready to receive the data of the first sector, the device sets

DRQ bit and clears BSY bit.

d) The host writes one sector of data through the Data register.

e) The device clears the DRQ bit and sets the BSY bit.

f) When the drive completes transferring the data of the sector, the device clears

BSY bit and asserts INTRQ signal. If transfer of another sector is requested, the drive sets the DRQ bit.

g) After detecting the INTRQ signal assertion, the host reads the Status register.

h) The device resets INTRQ (the interrupt signal).

I) If transfer of another sector is requested, steps d) and after are repeated.

Figure 5.5 shows an example of WRITE SECTOR(S) command protocol.

5-76

Figure 5.5 WRITE SECTOR(S) command protocol

C141-E057-01EN

5.4 Command Protocol

Note:

For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the

DRQ setting by the device to 50

µ s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred. If the timing to read the Status register does not meet above condition, normal data transfer operation is not assured guaranteed.

When the host issues the command even if the drive requests the data transfer (DRQ bit is set), or when the host executes resetting, the device correct operation is not guaranteed.

5.4.3 Commands without data transfer

Execution of the following commands does not involve data transfer between the host and the device.

• RECABLIBRATE

• SEEK

READY VERIFY SECTOR(S)

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

SET FEATURES

SET MULTIPLE MODE

SET MAX ADDRESS

• READ NATIVE MAX ADDRESS

• IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

CHECK POWER MODE

SECURITY ERASE PREPARE

SECURITY FREEZE LOCK

• FLUSH CACHE

Figure 5.6 shows the protocol for the command execution without data transfer.

C141-E057-01EN 5-77

Interface

Figure 5.6 Protocol for the command execution without data transfer

5.4.4 Other commands

• READ MULTIPLE

• SLEEP

• WRITE MULTIPLE

See the description of each command.

5.4.5 DMA data transfer commands

• READ DMA

• WRITE DMA

Starting the DMA transfer command is the same as the READ SECTOR(S) or

WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issurance.

Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed.

The following outlines the protocol:

The interrupt processing for the DMA transfer differs the following point.

The interrupt processing for the DMA transfer differs the following point.

a) The host writes any parameters to the Features, Sector Count, Sector Number,

Cylinder, and Device/Head register.

b) The host initializes the DMA channel c) The host writes a command code in the Command register.

d) The device sets the BSY bit of the Status register.

e) The device asserts the DMARQ signal after completing the preparation of data transfer. The device asserts either the BSY bit or DRQ bit during DMA data transfer.

5-78 C141-E057-01EN

5.4 Command Protocol

f) When the command execution is completed, the device clears both BSY and

DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register.

g) The host resets the DMA channel.

Figure 5.7 shows the correct DMA data transfer protocol.

f g d d e f d e

Figure 5.7 Normal DMA data transfer

f

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Interface

5.5 Ultra DMA Feature Set

5.5.1 Overview

Ultra DMA is a data transfer protocol used with the READ DMA and WRITE

DMA commands. When this protocol is enabled it shall be used instead of the

Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command

Block Register access).

Several signal lines are redefined to provide new functions during an Ultra DMA burst. These lines assume these definitions when 1) an Ultra DMA Mode is selected, and 2) a host issues a READ DMA or a WRITE DMA, command requiring data transfer, and 3) the host asserts DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of

DMACK- by the host at the termination of an Ultra DMA burst. All of the control signals are unidirectional. DMARQ and DMACK- retain their standard definitions.

With the Ultra DMA protocol, the control signal (STROBE) that latches data from

DD (15:0) is generated by the same agent (either host or device) that drives the data onto the bus. Ownership of DD (15:0) and this data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an Ultra

DMA data out burst.

During an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of

STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data. The highest fundamental frequency on the cable shall be 16.67 million transitions per second or 8.33 MHz (the same as the maximum frequency for PIO Mode 4 and DMA Mode 2).

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates. The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only the Ultra DMA Mode shall be selected at any given time.

All timing requirements for a selected Ultra DMA Mode shall be satisfied.

Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and 1. Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA

Mode 0.

An Ultra DMA capable device shall retain its previously selected Ultra DMA

Mode after executing a Software reset sequence. An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non-

Ultra DMA Modes after executing a Power on or hardware reset.

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5.5 Ultra DMA Feature Set

Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

5.5.2 Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6.4 defines the specific timing requirements). In the following rules DMARDY- is used in cases that could apply to either

DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or HSTROBE. The following are general Ultra DMA rules.

a) An Ultra DMA burst is defined as the period from an assertion of DMACKby the host to the subsequent negation of DMACK-.

b) A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst.

5.5.2.1 Ultra DMA burst initiation phase

a) The Ultra DMA burst initiation phase is started by the assertion of DMARQ signal by the device, and is ended when the transmitting side has inverted

STROBE signal for transmitting the first data.

b) The Ultra DMA burst requires the assertion of DMARQ signal by the device.

c) The host asserts DMACK-signal when it is able to start the requested burst.

d) The host always asserts DMACK signal after detecting the first assertion of

DMARQ signal.

e) Ultra DMA data in burst

The device starts transmission of the data to DD (15 : 0) when;

DMACK-signal assertion has been detected,

STOP signal negation has been detected, or

HDMARDY-signal assertion has been detected.

f) Ultra DMA data out burst

The device should not invert the state of this signal in the period from the moment of DMARQ signal assertion or DDMARDY-signal assertion to the moment of inversion of the first STROBE signal.

C141-E057-01EN 5-81

Interface

g) Ultra DMA data in burst

The device should not invert the state of this signal in the period from the moment of STOP signal negation or HDMARDY-signal assertion to the moment of inversion of the first STROBE signal.

5.5.2.2 Data transfer phase

a) The Data transfer phase is defined as the period from The Ultra DMA burst initiation phase to Ultra DMA burst termination phase.

b) The receiving side stops the Ultra DMA burst temporarily by negating

DMARDY-signal, and then restarts the Ultra DMA burst by asserting again.

c) The transmitting side stops the Ultra DMA burst temporarily by notperforming inversion of STROBE signal, and then restarts the Ultra DMA burst by restarting the inversion.

d) When the transmitting side has stopped the inversion of STROBE signal, the receiving side should not output termination request signal immediately.

The receiving side should negate DMARDY signal when no termination request signal has been received from the transmission side, and then should output the termination request signal when a certain wait time has elapsed.

e) The transmitting side is allowed to send STROBE signal at a transfer speed that is lower than the one in the transferable fastest Ultra DMA mode, but is not allowed to send the STROBE signal at a higher speed than this.

The receiving side should be able to receive the data in the transferable fastest

Ultra DMA mode.

5.5.2.3 Ultra DMA burst termination phase

a) The transmitting side or receiving side is allowed to end the Ultra DMA burst.

b) The Ultra DMA burst termination is not the end of the command execution.

When the Ultra DMA burst termination has occurred before the ending of the command, the command should be ended by starting a new Ultra DMA burst, or the host should issue command abort by outputting hard reset or soft reset to the device.

c) The Ultra DMA burst should be stopped temporarily before the receiving side outputs the ending request.

d) The host outputs the ending request by asserting STOP signal, and then the device negates DMARQ signal to confirm it.

e) The device outputs the ending request by negating DMARQ signal, and then the host asserts STOP signal to confirm it.

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5.5 Ultra DMA Feature Set

f) Once the transmitting side has outputted the ending request, the output state of STROBE signal should not be changed unless the receiving side has confirmed it. Then, if the STROBE signal is not in asserted state, The transmitting side should assert the STROBE signal. However, the assertion of the STROBE signal should not cause the data transfer to occur.

g) The transmitting side should return the STROBE signal to its asserted state immediately after receiving the ending request from the receiving side.

However, the returning of the STROBE signal to its asserted state should not cause the data transfer to occur and CRC to be perform.

h) Once the receiving side has outputted the ending request, the negated state of the DMARDY signal should not be changed for the remaining Ultra DMA burst to be performed.

i) The receiving side should neglect the inversion of the STROBE signal if

DMARQ signal has been negated or STOP signal has been asserted.

5.5.3 Ultra DMA data in commands

5.5.3.1 Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.1 and 5.6.4.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.

3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert STOP.

4) The host shall negate HDMARDY-.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep

CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4) and (5) shall have occurred at least t

ACK

before the host asserts

DMACK-. The host shall keep DMACK- asserted until the end of an Ultra

DMA burst.

7) The host shall release DD (15:0) within t

AZ

after asserting DMACK-.

8) The device may assert DSTROBE t

ZIORDY

after the host has asserted DMACK-.

Once the device has driven DSTROBE the device shall not release

DSTROBE until after the host has negated DMACK- at the end of an Ultra

DMA burst.

C141-E057-01EN 5-83

Interface

9) The host shall negate STOP and assert HDMARDY- within t

ENV

after asserting DMACK-. After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).

10) The device shall drive DD (15:0) no sooner than t

ZAD

after the host has asserted DMACK-, negated STOP, and asserted HDMARDY-.

11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10).

12) To transfer the first word of data the device shall negate DSTROBE within t

FS after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than t

DVS

after driving the first word of data onto

DD (15:0).

5.5.3.2 The data in transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.3 and 5.6.4.2):

1) The device shall drive a data word onto DD (15:0).

2) The device shall generate a DSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of DD (15:0). The device shall generate a

DSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA

Mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than 2t

CYC

for the selected Ultra DMA mode.

3) The device shall not change the state of DD (15:0) until at least t

DVH

after generating a DSTROBE edge to latch the data.

4) The device shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.

5.5.3.3 Pausing an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.4 and 5.6.4.2 for specific timing requirements).

a) Device pausing an Ultra DMA data in burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.

NOTE - The host shall not immediately assert STOP to initiate Ultra

DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate

ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t

RP

before asserting STOP.

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5.5 Ultra DMA Feature Set

3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.

b) Host pausing an Ultra DMA data in burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by negating HDMARDY-.

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.

5.5.3.4 Terminating an Ultra DMA data in burst

a) Device terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.5 and 5.6.4.2 for specific timing requirements):

1) The device shall initiate termination of an Ultra DMA burst by not generating DSTROBE edges.

2) The device shall negate DMARQ no sooner than t

SS

after generating the last DSTROBE edge. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

3) The device shall release DD (15:0) no later than t

AZ

after negating

DMARQ.

4) The host shall assert STOP within t

LI

after the device has negated

DMARQ. The host shall not negate STOP again until after the Ultra

DMA burst is terminated.

5) The host shall negate HDMARDY- within t

LI

after the device has negated

DMARQ. The host shall continue to negate HDMARDY- until the Ultra

DMA burst is terminated. Steps (4) and (5) may occur at the same time.

6) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5):

C141-E057-01EN 5-85

Interface

5-86

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.

DSTROBE shall remain asserted until the Ultra DMA burst is terminated.

8) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (6), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted DSTROBE and negated DMARQ and the host has asserted

STOP and negated HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DSTROBE within t

IORDYZ

after the host negates

DMACK-.

13) The host shall not negate STOP no assert HDMARDY- until at least t

ACK after negating DMACK-.

14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

b) Host terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.6 and 5.6.4.2 for specific timing requirements):

1) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall initiate Ultra DMA burst termination by negating

HDMARDY-. The host shall continue to negate HDMARDY- until the

Ultra DMA burst is terminated.

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

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5.5 Ultra DMA Feature Set

5) The host shall assert STOP no sooner than t

RP

after negating

HDMARDY-. The host shall not negate STOP again until after the Ultra

DMA burst is terminated.

6) The device shall negate DMARQ within t

LI

after the host has asserted

STOP. The device shall not assert DMARQ again until after the Ultra

DMA burst is terminated.

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.

DSTROBE shall remain asserted until the Ultra DMA burst is terminated.

8) The device shall release DD (15:0) no later than t

AZ

after negating

DMARQ.

9) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5).

10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).

11) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted DSTROBE and negated DMARQ and the host has asserted

STOP and negated HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

12) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

13) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

14) The device shall release DSTROBE within t

IORDYZ

after the host negates

DMACK-.

15) The host shall neither negate STOP nor assert HDMARDY- until at least t

ACK

after the host has negated DMACK-.

16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

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Interface

5.5.4 Ultra DMA data out commands

5.5.4.1 Initiating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.7 and 5.6.4.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst.

3) Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert STOP.

4) The host shall assert HSTROBE.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep

CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4), and (5) shall have occurred at least t

ACK

before the host asserts

DMACK-. The host shall keep DMACK- asserted until the end of an Ultra

DMA burst.

7) The device may negate DDMARDY- t

ZIORDY

after the host has asserted

DMACK-. Once the device has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK- at the end of an Ultra DMA burst.

8) The host shall negate STOP within t

ENV

after asserting DMACK-. The host shall not assert STOP until after the first negation of HSTROBE.

9) The device shall assert DDMARDY- within t

LI

after the host has negated

STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host.

10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

11) To transfer the first word of data: the host shall negate HSTROBE no sooner than t

LI

after the device has asserted DDMARDY-. The host shall negate

HSTROBE no sooner than t

DVS

after the driving the first word of data onto

DD (15:0).

5.5.4.2 The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.8 and 5.6.4.2 for specific timing requirements):

1) The host shall drive a data word onto DD (15:0).

2) The host shall generate an HSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of DD (15:0). The host shall generate an

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5.5 Ultra DMA Feature Set

HSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA

Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t

CYC

for the selected Ultra DMA mode.

3) The host shall not change the state of DD (15:0) until at least t

DVH

after generating an HSTROBE edge to latch the data.

4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.

5.5.4.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.9 and 5.6.4.2 for specific timing requirements).

a) Host pausing an Ultra DMA data out burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by not generating an

HSTROBE edge.

Note: The device shall not immediately negate DMARQ to initiate Ultra

DMA burst termination when the host stops generating HSTROBE edges. If the host does not assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate DDMARDY- and wait t

RP before negating DMARQ.

3) The host shall resume an Ultra DMA burst by generating an HSTROBE edge.

b) Device pausing an Ultra DMA data out burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by negating DDMARDY-.

3) The host shall stop generating HSTROBE edges within t

RFS

of the device negating DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.

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Interface

5.5.4.4 Terminating an Ultra DMA data out burst

a) Host terminating an Ultra DMA data out burst

The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.10 and 5.6.4.2 for specific timing requirements):

1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.

2) The host shall assert STOP no sooner than t

SS

after it last generated an

HSTROBE edge. The host shall not negate STOP again until after the

Ultra DMA burst is terminated.

3) The device shall negate DMARQ within t

LI

after the host asserts STOP.

The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

4) The device shall negate DDMARDY- with t

LI

after the host has negated

STOP. The device shall not assert DDMARDY- again until after the

Ultra DMA burst termination is complete.

5) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE.

HSTROBE shall remain asserted until the Ultra DMA burst is terminated.

6) The host shall place the result of its CRC calculation on DD (15:0) (see

5.5.5)

7) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted HSTROBE and STOP and the device has negated DMARQ and

DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

8) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

10) The device shall release DDMARDY- within t

IORDYZ

after the host has negated DMACK-.

11) The host shall neither negate STOP nor negate HSTROBE until at least t

ACK

after negating DMACK-.

12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

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5.5 Ultra DMA Feature Set

b) Device terminating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing requirements):

1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall initiate Ultra DMA burst termination by negating

DDMARDY-.

3) The host shall stop generating an HSTROBE edges within t

RFS

of the device negating DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall negate DMARQ no sooner than t

RP

after negating

DDMARDY-. The device shall not assert DMARQ again until after the

Ultra DMA burst is terminated.

6) The host shall assert STOP with t

LI

after the device has negated DMARQ.

The host shall not negate STOP again until after the Ultra DMA burst is terminated.

7) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE.

HSTROBE shall remain asserted until the Ultra DMA burst is terminated.

8) The host shall place the result of its CRC calculation on DD (15:0) (see

5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted HSTROBE and STOP and the device has negated DMARQ and

DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DDMARDY- within t

IORDYZ

after the host has negated

DMACK-.

5-91

Interface

13) The host shall neither negate STOP nor HSTROBE until at least t

ACK

after negating DMACK-.

14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

5.5.5

Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a) Both the host and the device shall have a 16-bit CRC calculation function.

b) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d) For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e) At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of

DMACK-.

f) The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a

CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command. If a miscompare error occurs during one or more Ultra

DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g) For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h) A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

i) The CRC generator polynomial is : G (X) = X

16

+ X

12

+ X

5

+ 1.

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5.5 Ultra DMA Feature Set

Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.

DD0–DD15

16

CRCIN

Combination logic

F1–f16

16

16

Word clock

Latch

CRCOUT

16

Figure 5.8 An example of generation of parallel CRC

Table 5.14 Parallel generation equation of CRC polynomial

CRCINO=f

16

CRCIN1=f

15

CRCIN2=f

14

CRCIN3=f

13

CRCIN4=f

12

CRCIN5=f

11

XOR f

CRCIN6=f

10

XOR f

15

CRCIN7=f

9

XOR f

14

CRCIN8 = f

8

XOR f

13

CRCIN9 = f

7

XOR f

12

CRCIN10 = f

6

XOR f

11

CRCIN11 = f

5

XOR f

10

CRCIN12 = f

4

XOR f

9

XOR f

16

CRCIN13 = f

3

XOR f

8

XOR f

15

CRCIN14 = f

2

XOR f

7

XOR f

14

CRCIN15 = f

1

XOR f

6

XOR f

13 f

1

= DD0 XOR CRCOUT

15 f

2

= DD1 XOR CRCOUT

14 f

3

= DD2 XOR CRCOUT

13 f

4

= DD3 XOR CRCOUT

12 f

5

= DD4 XOR CRCOUT

11

XOR f

1 f

6

= DD5 XOR CRCOUT

10

XOR f

2 f

7

= DD6 XOR CRCOUT

9

XOR f

3 f

8

= DD7 XOR CRCOUT

8

XOR f

4 f

9

= DD8 XOR CRCOUT7 XOR f

5 f

10

= DD9 XOR CRCOUT6 XOR f

6 f

11

= DD10 XOR CRCOUT5 XOR f

7 f

12

= DD11 XOR CRCOUT4 XOR f

1

XOR f

8 f

13

= DD12 XOR CRCOUT3 XOR f

2

XOR f

9 f

14

= DD13 XOR CRCOUT2 XOR f

3

XOR f

10 f

15

= DD14 XOR CRCOUT1 XOR f

4

XOR f

11 f

16

= DD15 XOR CRCOUT0 XOR f

5

XOR f

12

DD : Data from bust f : Feedback

CRCIN : Output of combination logic (the next CRC)

CROUT : Result of 16 bit latch (current CRC)

C141-E057-01EN 5-93

Interface

5.5.6 Series termination required for Ultra DMA

Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device.

Table 5.15 Recommended series termination for Ultra DMA

Signal Host Termination Device Termination

DIOR-:HDMARDY-:HSTROBE

DIOW-:STOP

CS0-, CS1-

DA0, DA1, DA2

DMACK-

DD15 through DD0

DMARQ

INTRQ

33 ohm

33 ohm

33 ohm

33 ohm

33 ohm

33 ohm

82 ohm

82 ohm

82 ohm

82 ohm

82 ohm

82 ohm

82 ohm

240 ohm (100 MHz)

33 ohm

33 ohm

IORDY:DDMARDY-:DSTROBE 82 ohm 22 ohm

Note: Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA Mode.

For signals also requiring a pull-up or pull-down resistor at the host see Figure 5.9.

5-94

IORDY

DMARQ

Figure 5.9 Ultra DMA termination with pull-up or pull-down

Configuration of cable

For the configuration of the cable (common use of primary port and secondary port), DMACK signal should not be used in common. It is not recommended to use DIOR-, DIOW- and IORDY signal in common.

C141-E057-01EN

5.6 Timing

5.6 Timing

5.6.1 PIO data transfer

Figure 5.10 shows of the data transfer timing between the device and the host system.

C141-E057-01EN 5-95

Interface

5-96

Figure 5.10 Data transfer timing

C141-E057-01EN

5.6 Timing

5.6.2 Single word DMA data transfer

Figure 5.9 show the single word DMA data transfer timing between the device and the host system.

Figure 5.11 Single word DMA data transfer timing (mode 2)

C141-E057-01EN 5-97

Interface

5.6.3 Multiword DMA data transfer

Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system.

Delay time from DIOR-/DIOW- assertion to DMARQ negation

5-98

Figure 5.12 Multiword DMA data transfer timing (mode 2)

C141-E057-01EN

5.6 Timing

5.6.4 Transfer of Ultra DMA data

Figures 5.13 to 5.22 define the timings concerning every phase for the Ultra DMA

Burst.

Table 5.13 includes the timing for each Ultra DMA mode.

5.6.4.1 Starting of Ultra DMA data In Burst

The timing for each Ultra DMA mode is included in 5.6.4.2.

Note : The definitions of STOP, HDMARDY- and DSTROBE signals are valid before the assertion of DMACK signal.

Figure 5.13 Starting of Ultra DMA data In Burst transfer

C141-E057-01EN 5-99

Interface

5.6.4.2 Ultra DMA data burst timing requirements

Table 5.16 Ultra DMA data burst timing requirements (1 of 2)

NAME MODE 0

(in ns) t2 t t t t t t t t

DS

DH

DVS

DVH t

CYC

CYC

FS

LI t

MLI t

UI t

AZ

ZAH

ZAD

MODE 1

(in ns)

MODE 2

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX

114 75 55 Cycle time (from STROBE edge to

STROBE edge)

235 156 117 Two cycle time (from rising edge to next rising edge or from falling edge to next falling edge of STROBE)

15

3

70

6

10

3

48

6

7

3

34

6

Data setup time (at recipient)

Data hold time (at recipient)

Data valid setup time at sender (from data bus being valid until STROBE edge)

Data valid hold time at sender (from

STROBE edge until data may become invalid)

0 230 0 200 0

0

20

0

20

0

150

10

0

20

0

20

0

150

10

0

20

0

20

0

170 First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)

150 Limited interlock time (see Note 1)

Interlock time with minimum (see Note 1)

Unlimited interlock time (see Note 1)

10 Maximum time allowed for output drivers to release (from being asserted or negated)

Minimum delay time required for output drivers to assert or negate (from released state) t

ENV t

SR

20 70

50

20 70

30

20 70 Envelope time (from DMACK- to STOP and HDMARDY- during data in burst initiation and from DMACK to STOP during data out burst initiation)

20 STROBE-to-DMARDY-time (if DMARDYis negated before this long after STROBE edge, the recipient shall receive no more than one additional data word)

5-100 C141-E057-01EN

5.6 Timing

Table 5.16 Ultra DMA data burst timing requirements (2 of 2)

NAME MODE 0

(in ns) t t t

RFS

RP

IORDYZ

20

MODE 1

(in ns)

20

MODE 2

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX

75 60 50 Ready-to-final-STROBE time (no

STROBE edges shall be sent this long after negation of DMARDY)

160 125 100 Ready-to-pause time (that recipient shall wait to initiate pause after negating

DMARDY-)

20 Pull-up time before allowing IORDY to be released t

ZIORDY

0 0 0 t t

ACK

SS

20

50

20

50

20

50

Minimum time device shall wait before driving IORDY

Setup and hold times for DMACK- (before assertion or negation)

Time from STROBE edge to negation of

DMARQ or assertion of STOP (when sender terminates a burst)

Notes:

1) t

UI

, t

MLI

and t

LI

indicate sender -to-recipient or recipient-to-sender interlocks, that is, one agent

(either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.

t

UI

is an unlimited interlock, that has no maximum time value. t

MLI

is a limited time-out that has a defined minimum. t

LI

is a limited time-out, that has a defined maximum.

2) All timing parameters are measured at the connector of the device to which the parameter applies.

For example, the sender shall stop generating STROBE edges t

RFS

after the negation of DMARDY-.

Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.

3) All timing measurement switching points (low to high and high to low) are to be taken at 1.5 V.

C141-E057-01EN 5-101

Interface

5.6.4.3 Sustained Ultra DMA data in burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

Figure 5.14 Sustained Ultra DMA data in burst

5-102 C141-E057-01EN

5.6 Timing

5.6.4.4 Host pausing an Ultra DMA data in burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

Notes:

1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t

RP

after HDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the host may receive zero, one or two more data words from the device.

Figure 5.15 Host pausing an Ultra DMA data in burst

C141-E057-01EN 5-103

Interface

5.6.4.5 Device terminating an Ultra DMA data in burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

5-104

Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.16 Device terminating an Ultra DMA data in burst

C141-E057-01EN

5.6 Timing

5.6.4.6 Host terminating an Ultra DMA data in burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.17 Host terminating an Ultra DMA data in burst

C141-E057-01EN 5-105

Interface

5.6.4.7 Initiating an Ultra DMA data out burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

5-106

Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

Figure 5.18 Initiating an Ultra DMA data out burst

C141-E057-01EN

5.6 Timing

5.6.4.8 Sustained Ultra DMA data out burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

Figure 5.19 Sustained Ultra DMA data out burst

C141-E057-01EN 5-107

Interface

5.6.4.9 Device pausing an Ultra DMA data out burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

5-108

Notes:

1) The device may negate DMARQ to request termination of the Ultra

DMA burst no sooner than t

RP

after DDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the device may receive zero, one or two more data words from the host.

Figure 5.20 Device pausing an Ultra DMA data out burst

C141-E057-01EN

5.6 Timing

5.6.4.10 Host terminating an Ultra DMA data out burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.21 Host terminating an Ultra DMA data out burst

C141-E057-01EN 5-109

Interface

5.6.4.11 Device terminating an Ultra DMA data in burst

5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

5-110

Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.22 Device terminating an Ultra DMA data out burst

C141-E057-01EN

5.6 Timing

5.6.5 Power-on and reset

Figure 5.11 shows power-on and reset (hardware and software reset) timing.

(1) Only master device is present

Power-on Reset

RESET–

(2) Master and slave devices are present (2-drives configulation)

C141-E057-01EN

PDIAG- negation

Figure 5.23 Power on Reset Timing

31

5-111

This page is intentionally left blank.

CHAPTER 6 Operations

6.1

6.2

6.3

6.4

6.5

6.6

Device Response to the Reset

Address Translation

Power Save

Defect Management

Read-Ahead Cache

Write Cache

C141-E057-01EN 6-1

Operations

6.1 Device Response to the Reset

This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command.

6.1.1 Response to power-on

After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal. Then, the master device checks a

PDIAG- signal to see if the slave device has sucessfully completed the power-on diagnostics.

If the master device cannot confirm assertion of the DASP- signal within 450 ms, the master device recognizes that no slave device is connected.

After the slave device (device 1) releases its own power-on reset state, the slave device shall report its presence and the result of power-on diagnostics to the master device as described below:

DASP- signal: Asserted within 400 ms.

PDIAG- signal: Negated within 1 ms and asserted within 30 seconds.

6-2 C141-E057-01EN

C141-E057-01EN

31 sec.

6.1 Device Response to the Reset

30 sec.

Figure 6.1 Response to power-on

6-3

Operations

6.1.2 Response to hardware reset

Response to RESET- (hardware reset through the interface) is similar to the power-on reset.

Upon receipt of hardware reset, the master device checks a DASP- signal for up to

450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.

Then the master device checks a PDIAG- signal to see if the slave device has successfully completed the self-diagnostics.

If the master device cannot confirm assertion of the DASP- signal within 450 ms, the master device recognizes that no slave device is connected.

After the slave device receives the hardware reset, the slave device shall report its presense and the result of the self-diagnostics to the master device as described below:

DASP- signal: Asserted within 400 ms.

PDIAG- signal: Negated within 1 ms and asserted within 30 seconds.

6-4

30 sec.

Figure 6.2 Response to hardware reset

C141-E057-01EN

6.1 Device Response to the Reset

6.1.3 Response to software reset

The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.

After the slave device receives the software reset, the slave device shall report its presense and the result of the self-diagnostics to the master device as described below:

PDIAG- signal: negated within 1 ms and asserted within 30 seconds

When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the PDIAG- signal, and negates the DASP- signal when asserting the

PDIAG- signal.

If the slave device is preset, PDIAG- is checked for up to 31 seconds.

30 sec.

Figure 6.3 Response to software reset

C141-E057-01EN 6-5

Operations

6.1.4 Response to diagnostic command

When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAGsignal for up to 6 seconds to see if the slave device has completed the selfdiagnosis successfully.

The master device does not check the DASP- signal.

After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command, it shall report the result of the self-diagnostics to the master device as described below:

PDIAG- signal: negated within 1 ms and asserted within 5 seconds

When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the PDIAG- signal, and negates the DASP- signal when asserting the

PDIAG- signal.

If the slave device is preset, PDIAG- is checked for up to

6 seconds.

6-6

Figure 6.4 Response to diagnostic command

C141-E057-01EN

6.2 Address Translation

6.2 Address Translation

When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation).

Following subsections explains the CHS translation mode.

6.2.1 Default parameters

In the logical to physical address translation, the logical cylinder, head, and sector addresses are translated to the physical cylinder, head, and sector addresses based on the number of heads and the number of sectors per track which are specified with an INITIALIZE DEVICE PARAMETERS command. This is called as the current translation mode.

If the number of heads and the number of sectors are not specified with an

INITIALIZE DEVICE PARAMETERS command, the default values listed in

Table 6.1 are used. This is called sa the default translation mode. The parameters in Table 6.1 are called BIOS specification.

Table 6.1 Default parameters

Parameters

(logical)

Number of cylinders

Number of heads

Number of sectors/track

Formatted capacity (MB)

MHE2064AT

13,424

15

63

6,495.06

MHE2043AT

8,944

15

63

4,327.46

MHF2043AT

8,944

15

63

4,327.46

MHF2021AT

4,200

16

63

2,167.60

As long as the formatted capacity of the IDD does not exceed the value shown on

Table 6.1, the host can freely specify the number of cylinders, heads, and sectors per track.

Generally, the device recognizes the number of heads and sectors per track with the INITIALIZE DEVICE PARAMETER command. However, it cannot recognizes the number of cylinders. In other words, there is no way for the device to recognize a host access area on logical cylinders. Thus the host should manage cylinder access to the device.

The host can specify a logical address freely within an area where an address can be specified (within the specified number of cylinders, heads, and sectors per track) in the current translation mode.

The host can read an addressable parameter information from the device by the

IDENTIFY DEVICE command (Words 54 to 56).

C141-E057-02EN 6-7

Operations

6.2.2 Logical address

(1) CHS mode

Logical address assignment starts from physical cylinder (PC) 0, physical head

(PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track that is specified by the INITIALIZE DEVICE PARAMETERS command. If the last sector in a zone of a physical head is used, the track is switched and the next logical sector is placed in the initial sector in the same zone of the subsequent physical head.

After the last physical sector of the last physical head is used in the zone, the subsequent zone is used and logical sectors are assigned from physical head 0 in the same way.

Figure 6.5 shows an example of 6 heads configuration. (assuming there is no track skew).

LH2, LH3

229 230

40 41

22 23

42 43

6

5

230

Figure 6.5 Address translation (example in CHS mode)

6-8 C141-E057-01EN

6.3 Power Save

(2) LBA mode

Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. If the last sector in a zone of a physical head is used, the track is switched and the next LBA is assigned to the initial sector in the same zone of the subsequent physical head.

After the last physical sector of the last physical head is used in the zone, the subsequent zone is used and LBA is assigned from physical head 0 in the same way.

Figure 6.6 shows an example of 4 heads configuration (assuming there is no track skew).

229 230

228 229

230 231 232

6

5

230

Figure 6.6 Address translation (example in LBA mode)

229 230

458 459

6.3 Power Save

The host can change the power consumption state of the device by issuing a power command to the device.

6.3.1 Power save mode

There are four types of power consumption state of the device including active mode where all circuits are active.

In the power save mode, power supplying to the part of the circuit is turned off.

There are three types of power save modes:

• Idle mode

C141-E057-01EN 6-9

Operations

Standby mode

• Sleep mode

The drive moves from the Active mode to the idle mode by itself.

Regardless of whether the power down is enabled, the device enters the idle mode.

The device also enters the idle mode in the same way after power-on sequence is completed.

And, the automatic power-down is executed if no command is coming for 30 min.

(default)

(1) Active mode

In this mode, all the electric circuit in the device are active or the device is under seek, read or write operation.

A device enters the active mode under the following conditions:

A command other than power commands is issued.

• A reset command is received.

(2) Idle mode

In this mode, circuits on the device is set to power save mode.

The device enters the Idle mode under the following conditions:

After completion of power-on sequence.

After completion of the command execution other than SLEEP and STANDBY commands.

After completion of the reset sequence

(3) Standby mode

In this mode, the VCM circuit is turned off and the spindle motor is stopped.

The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately.

The drive enters the standby mode under the following conditions:

• A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode.

When automatic power down sequence is enabled, the timer has elapsed.

A reset is issued in the sleep mode.

6-10 C141-E057-01EN

6.4 Defect Management

When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode.

Reset (hardware or software)

STANDBY command

• STANDBY IMMEDIATE command

• INITIALIZE DEVICE PARAMETERS command

• CHECK POWER MODE command

(4) Sleep mode

The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset.

The drive enters the sleep mode under the following condition:

A SLEEP command is issued.

Issued commands are invalid (ignored) in this mode.

6.3.2 Power commands

The following commands are available as power commands.

• IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

SLEEP

CHECK POWER MODE

6.4 Defect Management

Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatting at the factory shipment.

All the user space area are formatted at shipment from the factory based on the default parameters listed in Table 6.1.

C141-E057-01EN 6-11

Operations

6.4.1 Spare area

Following two types of spare area are provided for every physical head.

1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (4 cylinders)

2) Spare cylinder for alternative assignment: used for automatic alternative assignment at read error occurrence.

(4 cylinders)

6.4.2 Alternating defective sectors

The two alternating methods described below are available:

(1) Sector slip processing

A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector (physically adjacent sector to the defective sector).

When defective sector is present, the sector slip processing is performed in the formatting.

Figure 6.7 shows an example where (physical) sector 5 is defective on head 0 in cylinder 0.

1 2 3 4 5 6 7 8

228 229 230

1 2 3 4 (unused) 5 6 7 227 228 229

If an access request to physical sector 5 is specified, the device accesses physical sector 6 instead of sector 5.

Note: If an access request to physical sector 5 is specified, the device accesses physical sector 6 instead of sector 5.

Figure 6.7 Sector slip processing

6-12 C141-E057-01EN

6.4 Defect Management

(2) Alternate cylinder assignment

A defective sector is assigned to the spare sector in the alternate cylinder.

This processing is performed when the alternate assignment is specified in the

FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence.

Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0.

1 2 3 4

6 7

229 230

229 230

Figure 6.8 Alternate cylinder assignment

4 alternate cylinders are provided for each head in zone 13 (inner side).

When an access request to physical sector 5 is specified, the device accesses the alternated sector in the alternate cylinder instead of sector 5. When an access request to sectors next to sector 5 is specified, the device seeks to cylinder 0, head

0, and continues the processing.

(3) Automatic alternate assignment

The device performs the automatic alternate assignment when ECC correction performance is increased during read error retry, a read error is recovered. Before automatic alternate assignment, the device performs rewriting the corrected data to the erred sector and rereading. If no error occurs at rereading, the automatic alternate assignment is not performed.

An unrecoverable write error occurs during write error retry, automatic alternate assignment is performed.

C141-E057-01EN 6-13

Operations

6.5 Read-Ahead Cache

After read command which involes read data from the disk medium is completed, the read-ahead cache function reads the subsequent data blocks automatically and stores the data to the data buffer.

When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium. The host can thus access data at higher speed.

6.5.1 Data buffer configuration

The drive has a 512-KB data buffer. The buffer is used by divided into three parts; for read commands, for write commands, and for MPU work (see Figure

6.9).

512 MB (524,288 bytes) for read commands for write commands for MPU work

262,144 byte (512 sector)

131,072 byte (256 sector)

131,072 byte

Figure 6.9 Data buffer configuration

The read-ahead operation is performed at execution of the READ SECTOR(S),

READ MULTIPLE, or READ DMA command, and read-ahead data is stored in the buffer for read commands.

6.5.2 Caching operation

Caching operation is performed only at issurance of the following commands.

The device transfers data from the data buffer to the host system at issurance of following command if following data exist in the data buffer.

• All sectors to be processed by the command

• A part of data including load sector to be processed by the command

When a part of data to be processed exist in the data buffer, remaining data are read from the medium and are transferred to the host system.

(1) Commands that are object of caching operation

Follow commands are object of caching operation.

6-14 C141-E057-01EN

6.5 Read-Ahead Cache

READ SECTOR (S)

• READ MULTIPLE

• READ DMA

When caching operation is disabled by the SET FEATURES command, no caching operation is performed.

(2) Data that are object of caching operation

Follow data are object of caching operation.

1) Read-ahead data read from the medium to the data buffer after completion of the command that are object of caching operation.

2) Data transferred to the host system once by requesting with the command that are object of caching operation (except for the cache invalid data by some reasons).

3) Remaining data in the data buffer (for write command) transferred from the host system by the command that writes data onto the disk medium, such as the WRITE SECTOR (S), WRITE DMA, WRITE MULTIPLE.

Followings are definition of in case that the write data is treated as a cache data.

However, since the hit check at issurance of read command is performed to the data buffer for read command prioritily, caching write data is limited to the case that the hit check is missed at the data buffer for read command.

When all data requested by the read command are stored in the data buffer for write command (hit all), the device transfers data from the data buffer for write command. At this time, the read-ahead operation to the data subsequent to the requested data is not performed.

• Even if a part of data requested by the read command are stored in the data buffer for write command (hit partially), all data are read from the disk medium without transferring from the data buffer for write command.

(3) Invalidating caching data

Caching data in the data buffer is invalidated in the following case.

1) Following command is issued to the same data block as caching data.

WRITE SECTOR(S)

WRITE DMA

WRITE MULTIPLE

2) Command other than following commands is issued (all caching data are invalidated)

READ SECTOR (S)

READ DMA

C141-E057-01EN 6-15

Operations

READ MULTIPLE

WRITE SECTOR(S)

WRITE MULTIPLE

WRITE VERIFY SECTOR(S)

3) Caching operation is inhibited by the SET FEATURES command.

4) Issued command is terminated with an error.

5) Soft reset or hard reset occurs, or power is turned off.

6) The device enters the sleep mode.

7) Under the state that the write data is kept in the data buffer for write command as a caching data, new write command is issued. (write data kept until now are invalidated)

6.5.3 Usage of read segment

This subsection explains the usage of the read segment buffer at following cases.

6.5.3.1 Mis-hit (no hit)

A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media.

The read-ahead operation is performed only when the last sector address of the previous read command and the lead sector address of this read command is sequential (see item (2)).

1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the lead of segment.

HAP

Segment only for read

DAP

6-16 C141-E057-01EN

6.5 Read-Ahead Cache

2) Transfers the requested data that already read to the host system with reading the requested data from the disk media.

HAP

Stores the read-requested data upto this point

Read-requested data

Cache enabled data

Empty area

DAP

3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation.

HAP

(stopped)

Read-requested data

Empty area

(stopped)

DAP

4) Following shows the cache enabled data for next read command.

Empty area

Start LBA Last LBA

6.5.3.2 Sequential read

When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive starts the read-ahead operation.

a.

Sequential command just after non-sequential command

When the previously executed read command is an non-sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive assumes the received command is a sequential command and performs the read-ahead operation after reading the requested data.

C141-E057-01EN 6-17

Operations

1) At receiving the sequential read command, the disk drive sets the DAP and

HAP to the start address of the segment and reads the requested data from the load of the segment.

HAP

Mis-hit data Empty area

DAP

2) The disk drive transfers the requested data that is already read to the host system with reading the requested data.

HAP

Requested data Mis-hit data Empty area

DAP

3) After completion of the reading and transferring the requested data to the host system, the disk drive performs the read-ahead operation continuously.

HAP (Completion of transferring requested data)

Requested data

Read-ahead data

Empty area

DAP

4) The disk drive performs the read-ahead operation for all area of segment with overwriting the requested data. Finally, the cache data in the buffer is as follows.

HAP

Read-ahead data

Last LBA Start LBA

DAP

6-18 C141-E057-01EN

HAP

6.5 Read-Ahead Cache

b.

Sequential hit

When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system.

The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.

1) In the case that the contents of buffer is as follows at receiving a read command;

HAP (Continued from the previous read request data)

Read-ahead data Hit data

DAP

Last LBA Start LBA

2) The disk drive starts the read-ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data.

HAP

Read-ahead data New read-ahead data Hit data

DAP

3) After completion of data transfer of hit data, the disk drive performs the readahead operation for the data area of which the disk drive transferred hit data.

Read-ahead data

DAP

C141-E057-01EN 6-19

Operations

4) Finally, the cache data in the buffer is as follows.

Read-ahead data

Start LBA Last LBA c.

Non-sequential command immediately after sequential command

When a sequential read command (first read) has been executed, the first read operation should be stopped if a non-sequential read command has been received and then, ten or more of the non-sequential read commands have been received. (Refer to 6.5.3.1.)

The figure that describes the first read operation is the same as that shown in the sub-section a.

6.5.3.3 Full hit (hit all)

All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the readahead operation.

1) In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command, the disk drive sets the

HAP to the address of which the hit data is stored.

HAP

Last position at previous read command

HAP (set to hit position for data transfer)

Cache data Full hit data Cache data

Last position at previous read command

DAP

2) The disk drive transfers the requested data but does not perform the readahead operation.

Cache data Full hit data

HAP

(stopped)

Cache data

6-20 C141-E057-01EN

6.5 Read-Ahead Cache

3) The cache data for next read command is as follows.

Cache data

Start LBA

Last LBA

6.5.3.4 Partially hit

A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly. The disk drive does not perform the read-ahead operation after data transfer.

Following is an example of partially hit to the cache data.

Cache data

Start LBA

Last LBA

1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data.

HAP

Partially hit data Lack data

DAP

2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time. However, the disk drive does not perform the read-ahead operation newly.

Requested data to be transferred

HAP

(stopped)

Partially hit data Lack data

DAP

(stopped)

C141-E057-01EN 6-21

Operations

3) The cache data for next read command is as follows.

Cache data

Start LBA Last LBA

6.6 Write Cache

The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed.

When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium. After transferring data of sectors requested by the host system, the drive generates the interrupt of command complete. Also, the drive sets the normal end status in the

Status register.

The drive continues writing data on the disk medium. When all data requested by the host are written on the disk medium, actual write operation is completed.

The drive receives the next command continuously. If the received command is a

“sequential write” (data to be written by a command is physically sequent to data of previous command), the drive starts data transfer and receives data of sectors requested by the host system. At this time, if the write operation of the previous command is still been executed, the drive continuously executes the write operation of the next command from the sector next to the last sector of the previous write operation. Thus, the latency time for detecting a target sector of the next command is eliminated. This shortens the access time.

The drive generates an interrupt of command complete after completion of data transfer requested by the host system as same as at previous command.

When the write operation of the previous command had been completed, the latency time occurs to search the target sector.

If the received command is not a “sequential write”, the drive receives data of sectors requested by the host system as same as “sequential write”. The drive generates the interrupt of command complete after completion of data transfer requested by the host system. Received data is processed after completion of the write operation to the disk medium of the previous command.

Even if a hard reset or soft reset is received or the write cache function is disabled by the SET FEATURES command during unwritten data is kept, the instruction is not enabled until remaining unwritten data is written onto the disk medium.

6-22 C141-E057-01EN

C141-E057-01EN

6.6 Write Cache

The drive uses a cache data of the last write command as a read cache data. When a read command is issued to the same address after the write command (cache hit), the read operation to the disk medium is not performed.

If an error occurs during the write operation, the device retries the processing. If the error cannot be recovered by retry, automatic alternate assignment is performed. For details about automate alternate assignment, see item (3) of Section 6.4.2.

The write cache function is operated with the following command.

• WRITE SECTOR(S)

• WRITE MULTIPLE

• WRITE DMA

When Write Cache is permitted, the writing of the data transferred from the host by the abovementioned Write Cache permit command into the disk medium may not be completed at the moment a normal ending interrupt has occurred.

In case a non-recoverable error has occurred during receiving more than one write command, it is difficult for the host to identify a command that caused the error.

(However, the error is not reported to the hose if an error at writing has been processed normally.)

Therefore, note that it is difficult for the host to retry an operation that caused a non-recoverable error.

6-23

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Glossary

Actuator

Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head.

AT bus

A bus between the host CPU and adapter board

ATA (AT Attachment) standard

The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors. Interfaces based on this standard are called ATA interfaces.

BIOS standard for drives

The BIOS standard collectively refers to the parameters defined by the host, which, for example, include the number of cylinders, the number of heads, and the number of sectors per track in the drive. The physical specifications of the drive do not always correspond to these parameters.

The BIOS of a PC AT cannot make full use of the physical specifications of these drivers. To make the best use of these drives, a BIOS that can handle the standard parameters of these drives is required.

Command

Commands are instructions to input data to and output data from a drive.

Commands are written in command registers.

Data block

A data block is the unit used to transfer data. A data block normally indicates a single sector.

DE

Disk enclosure. The DE includes the disks, built-in spindle motor, actuator, heads, and air filter. The DE is sealed to protect these components from dust.

Master (Device 0)

The master is the first drive that can operate on the AT bus. The master is daisychained with the second drive which can operate in conformity with the ATA standard.

C141-E057-01EN GL-1

Glossary

MTBF

Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation.

MTTR

PIO (Programmed input-output)

Mode to transfer data under control of the host CPU

Positioning

Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.

Sum of the seek time and mean rotational delay

Power save mode

The power save modes are idle mode, standby mode, and sleep mode.

In idle mode, the drive is neither reading, writing, nor seeking data. In standby mode, the spindle motor is stopped and circuits other than the interface control circuit are sleeping. The drive enters sleep mode when the host issues the SLEEP command.

Reserved

Rotational delay

Time delay due to disk rotation. The mean delay is the time required for half a disk rotation. The mean delay is the average time required for a head to reach a sector after the head is positioned on a track.

Seek time

Reserved bits, bytes, and fields are set to zero and unusable because they are reserved for future standards.

The seek time is the time required for a head to move from the current track to another track. The seek time does not include the mean rotational delay.

Slave (Device 1)

The slave is a second drive that can operate on the AT bus. The slave is daisychained with the first drive operating in conformity with the ATA standard.

GL-2 C141-E057-01EN

Status

VCM

Glossary

The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state.

Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.

C141-E057-01EN GL-3

This page is intentinally left blank.

A

ABRT Abored command

AIC Automatic idle control

AMNF Address mark not found

ATA AT attachment

AWG American wire gage

B

BBK Bad block detected

BIOS Basic input-output system

C

CORR Corrected data

CH Cylinder high register

CL

CM

Cylinder low register

Command register

CSR Current sense register

CSS

CY

Current start/stop

Cylinder register

D

dBA

DE

DH dB A-scale weighting

Disk enclosure

Device/head register

DRDY Drive ready

DRQ Ddata request bit

DSC Drive seek complete

DWF Drive write fault

E

ECC Error checking and correction

ER Error register

ERR Error

FR

HA

F

Feature register

H

Host adapter

Acronyms and Abbreviations

HDD Hard disk drive

I

IDNF ID not found

IRQ14 Interrupt request 14

LED

L

Light emitting diode

M

MB Mega-byte

MB/S Mega-byte per seconds

MPU Micro processor unit

PCA

PIO

RLL

P

Printed circuit assembly

Programed input-output

R

Run-lrnght-limited

SA

SC

SG

SN

ST

S

System area

Sector count register

Signal ground

Sector number register

Status register

T

TPI Track per inches

TRONF Track 0 not found

Typ Typical

U

UNC Uncorrectable ECC error

V

VCM Voice coil motor

C141-E057-01EN AB-1

This page is intentionally left blank.

Index

1-drive connection 2-4

2-drive connection 2-5

8/8 GCR 4-10

8/9 GCR decoder 4-13

A

Acceleration mode 4-21

Acoustic noise 1-7

Acoustic noise specification 1-7

Active mode 6-10

Actuator 2-3, 4-3

Actuator motor control 4-19

Adaptability 1-2

Adaptive equalizer circuit 4-12

ADC 4-17

A/D converter 4-17

Address translation 6-7, 6-8

AGC circuit 4-12

Air circulation system 2-4

Air filter 4-3

Alternate assignment, automatic 6-13

Alternate cylinder assignment 6-13

Alternate Status register 5-13

Alternating defective sector 6-12

Ambient temperature 3-5

ATA 2-5

ATA interface 2-4

Attribute ID 5-56

Attribute value for worst case so far 5-61

Automatic alternate assignment 6-13

Average positioning time 1-2

B

Block diagram of servo control circuit 4-14

Blower 4-3

Blower effect 2-4

Breather filter 4-3

BSY 5-11

C

Cable connection 3-7, 3-8

Cable connector specification 3-8

Caching operation 6-14

Calibration 4-15

CHECK POWER MODE 5-55

Check sum 5-61

C141-E057-01EN

CHS mode 6-8

Circuit configuration 4-4, 4-5

Circulation filter 2-4, 4-3

Combination of Identifier and Security level

5-69

Command block register 5-8

Command code 5-14, 5-71

Command description 5-16

Command processing 4-9

Command protocol 5-73

Command register 5-12

Command that is object of caching operation

6-14

Command without data transfer 5-77

Compact 1-2

Compensating open loop gain 4-8

Connection to interface 1-2

Connector location 3-7

Content of security password 5-63

Content of SECURITY SET PASSWORD data 5-68

Control block register 5-13

Controller circuit 2-4, 4-4

CORR 5-12

CSEL setting 3-11

Current attribute value 5-62

Current fluctuation 1-6

Current fluctuation when power is turned on

1-6

Current requirement 1-6

Cylinder High register 5-10

Cylinder Low register 5-10

D

DAC 4-17

D/A converter 4-17

Data area 4-18

Data assurance in event of power failure

1-9

Data buffer 1-3

Data buffer configuration 6-14

Data corruption 3-6

Data format version number 5-60

Data register 5-8

Data separator circuit 4-13

Data-surface servo format 4-18

IN-1

Index

Data that is object of caching operation

6-15

Data transfer rate 4-13

Data transferring command 5-73, 5-75

Data transfer timing 5-81

DE 2-4

Default parameter 6-7

Defect management 6-11

Device configuration 2-1

Device connection 3-8

Device connector 3-7

Device Control register 5-13

Device/Head register 5-10

Device overview 1-1

Device response to reset 6-2

DF 5-12

Diagnostic code 5-9

Dimension 3-2

Disk 2-2, 4-2

Disk enclosure 2-4

Disk media 2-3

DMA data transfer command 5-78

DMA data transfer protocol 5-78

DRDY 5-11

Driver 4-17

Driver circuit 4-17

DRQ 5-12

DSC 5-12

E

Environmental specification 1-7

ERR 5-12

Error correction by ECC 1-3

Error correction by retry 1-3

Error posting 5-71

Error rate 1-9

Error register 5-8

EXECUTE DEVICE DIAGNOSTIC 5-45

Execution example of READ MULTIPLE command 5-20

Execution timing of self-calibration 4-8

External magnetic field 3-6

F

Factory default setting 3-10

Failure prediction capability flag 5-62

Feature register function 5-57

Feature register value 5-39, 5-57

Features 1-2

Features register 5-9

Format of device attribute value data 5-59

IN-2

Format of insurance failure threshold value data 5-60

Frame 3-4

Frequency characteristics of programmable filter 4-12

Full hit 6-20

Functions and performance 1-2

G

Gray code 4-19

H

HA 2-5

Head 2-2, 4-2

Head carriage 4-3

Head structure 4-3

High-speed transfer rate 1-2

Hit all 6-20

Host command 5-13

I

IDENTIFY DEVICE 5-31

IDENTIFY DEVICE DMA 5-38

IDLE 5-50

IDLE IMMEDIATE 5-52

Idle mode 6-10

INITIALIZE DEVICE PARAMETERS

5-30

Inner guard band 4-18

Input voltage 1-5

Installation condition 3-1

Insurance failure threshold 5-58

Interface 1-2, 5-1

Interface signal 5-2

Invalidating caching data 6-15

I/O register 5-6

J

Jumper location 3-9

Jumper setting 3-9

L

Large capacity 1-2

LBA mode 6-9

Limitation of side-mounting 3-4

Logical address 6-8

Logical interface 5-6

C141-E057-01EN

M

Master 1-3

Master drive setting 3-10

Master password 5-68

Mean time between failures 1-8

Mean time to repair 1-8

Media defect 1-9

Microprocessor unit 4-14

Mis-hit 6-16

Model and product number 1-5

Model name and product number 1-5

Mounting 3-3

Move head to reference cylinder 4-15

MPU 4-14

MTBF 1-8

MTTR 1-8

Multiword DMA data transfer 5-80

Multiword DMA data transfer timing 5-80

Multiword mode 2 2-4

N

NIEN 5-13

No hit 6-16

Noise and vibration 1-2

O

Operation 6-1

Operation sequence 4-7

Operation to move head to reference cylinder 4-19

Orientation 3-3

Other command 5-78

Outer guard band 4-18

Outerview 2-2

Outline 4-2

P

PAD 4-19

Parameter 5-14, 5-71

Partially hit 6-21

Physical interface 5-2

PIO data transfer 5-78

PIO Mode 4 2-4

Positioning error 1-9

Power amplifier 4-17

Power commands 6-11

Power dissipation 1-6

Power-on 5-83

Power on/off sequence 1-6

Power-on sequence 4-6

C141-E057-01EN

Index

Power on timing 5-80

Power on timing 5-84

Power requirement 1-5

Power save 6-9

Power save mode 1-2, 6-9

Power supply connector 3-9

PreAMP 4-9

Programmable filter 4-12

Programmable filter circuit 4-12

Protocol for command abort 5-75

Protocol for command execution without data transfer 5-77

R

Raw attribute value 5-58

Read-ahead cache 6-14

Read-ahead cache system 1-3

READ BUFFER 5-45

Read circuit 4-12

READ DMA 5-21

READ LONG 5-47

READ MULTIPLE 5-18

READ SECTOR(S) 5-17

READ SECTOR(S) WITH RETRY 5-16

Read Sector(s) command protocol 5-74

READ VERIFY SECTOR(S) 5-22

Read/write circuit 2-4, 4-4, 4-9

Read/write circuit block diagram 4-11

Read/write preamplifier 4-9

RECALIBRATE 5-28

Reliability 1-8

Reset 5-83

Reset timing 5-84

Response to diagnostic command 6-6

Response to hardware reset 6-4

Response to power-on 6-2

Response to software reset 6-5

Ripple 1-5

S

SA area 4-18

Sector Count register 5-9

Sector Number register 5-9

Sector servo configuration 4-16

Sector slip processing 6-12

SECURITY DISABLE PASSWORD 5-63

SECURITY ERASE PREPARE 5-64

SECURITY ERASE UNIT 5-65

SECURITY FREEZE LOCK 5-66

SECURITY SET PASSWORD 5-68

SECURITY UNLOCK 5-69

IN-3

Index

SEEK 5-29

Seek operation 4-20

Seek to specified cylinder 4-15

Self-calibration 4-7

Self-calibration content 4-7

Self-diagnosis 1-3

Sensing and compensating for external force

4-7

Sequential command 6-17

Sequential hit 6-19

Sequential read 6-17

Service area 3-6

Service life 1-9

Servo A 4-19

Servo B 4-19

Servo burst capture 4-17

Servo burst capture circuit 4-17

Servo C 4-19

Servo circuit 4-4

Servo control 4-14

Servo control circuit 4-14

Servo D 4-19

Servo format, data-surface 4-18

Servo frame format 4-18

Servo mark 4-19

SET FEATURES 5-38

SET MULTIPLE MODE 5-41

Shock 1-8

Signal assignment on connector 5-2

Single word DMA data transfer 5-82

Single word DMA data transfer timing

5-82

Slave 1-3

Slave drive setting 3-10

SLEEP 5-54

Sleep mode 6-11

SMART 5-54

Spare area 6-12

Specification summary 1-4

Spindle 4-3

Spindle motor 2-3

Spindle motor control 4-17, 4-20

Spindle motor control circuit 4-17

Spindle motor driver circuit 4-4

Spindle motor start 4-15

SRST 5-13

Stable rotation mode 4-21

Standard value, surface 3-5

STANDBY 5-52

STANDBY IMMEDIATE 5-53

Standby mode 6-10

Start, spindle motor 4-15

Start mode 4-20

Status at completion of command execution

5-8

Status flag 5-62

Status register 5-11

Subassembly 4-2

Surface standard value 3-5

Surface temperature measurement point 3-5

System configuration 2-4

T

Temperature range 1-2

Theory of device operation 4-1

Time base generator circuit 4-13

Timing 5-76

Track following operation 4-20

U

Unrecoverable read error 1-9

Usage of read segment 6-16

User password 5-68

V

VCM 4-3

VCM current sense resistor (CSR) 4-17

Vibration 1-8

Viterbi detection circuit 4-13

Voice coil motor 4-3

W

WRITE BUFFER 5-49

Write cache 1-3, 6-22

Write circuit 4-10

WRITE DMA 5-26

WRITE LONG 5-48

WRITE MULTIPLE 5-25

Write precompiled 4-10

Write precompiled algorithm 4-10

Write/read recovery 4-19

WRITE SECTOR(S) 5-23

WRITE SECTOR(S) command protocol

5-76

WRITE VERIFY 5-27

IN-4 C141-E057-01EN

This page is intentinally left blank.

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C141-E057-02EN

MHE2064AT, MHE2043AT, MHF2043AT, MHF2021AT DISK DRIVE

PRODUCT MANUAL

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C141-E057-02EN

MHE2064/2043AT, MHF2043/2021AT DISK DRIVE

PRODUCT MANUAL

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PRODUCT MANUAL

C141-E057-02EN

C141-E057-02EN

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Key Features

  • Capacity of up to 2.0 GB
  • Fast data transfer rate of up to 16.6 MB/s
  • Compatible with a wide range of computers and operating systems

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Frequently Answers and Questions

What is the capacity of the Fujitsu MHE2043AT?
The Fujitsu MHE2043AT has a capacity of up to 2.0 GB.
How fast is the data transfer rate of the Fujitsu MHE2043AT?
The Fujitsu MHE2043AT has a data transfer rate of up to 16.6 MB/s.
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The Fujitsu MHE2043AT is compatible with a wide range of computers and operating systems.
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