Compaq 4000S Personal Computer User Manual

Technical
Reference
Guide
for
Compaq Deskpro 4000N and 4000S Personal Computers
This hardcopy is designed to be placed into a standard 3-ring binder. Provided below is a title block that
can be copied and cut out and placed into the slip or taped onto the edge of the binder.
Deskpro 4000N and 4000S Personal Computers TRG
Technical Reference Guide
NOTICE
The information in this document is subject to change without notice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR
EDITORIAL ERRORS OR OMISSIONS HEREIN; NOR FOR INCIDENTAL OR
CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE,
OR USE OF THIS MATERIAL. IT IS THE RESPONSIBILITY OF MANUFACTURERS TO
ENSURE THAT DEVICES DESIGNED TO BE USED WITH COMPAQ PRODUCTS
COMPLY WITH FCC CLASS B EMISSIONS REQUIREMENTS.
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photocopied or reproduced in any form without prior written consent from Compaq Computer
Corporation.
1997 Compaq Computer Corporation
All rights reserved. Printed in the USA
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Technical Reference Guide for
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Document Number DSK-109A/0907
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
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Technical Reference Guide
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Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION.............................................................................................................
1.1
ABOUT THIS GUIDE ........................................................................................................... 1-1
1.1.1
USING THIS GUIDE ..................................................................................................... 1-1
1.1.2
ADDITIONAL INFORMATION SOURCES.................................................................. 1-1
1.2
NOTATIONAL CONVENTIONS.......................................................................................... 1-2
1.2.1
VALUES........................................................................................................................ 1-2
1.2.2
RANGES........................................................................................................................ 1-2
1.2.3
SIGNAL LABELS.......................................................................................................... 1-2
1.2.4
REGISTER NOTATION AND USAGE ......................................................................... 1-2
1.2.5
BIT NOTATION ............................................................................................................ 1-2
1.3
COMMON ACRONYMS AND ABBREVIATIONS.............................................................. 1-3
CHAPTER 2 SYSTEM OVERVIEW.....................................................................................................
2.1
INTRODUCTION.................................................................................................................. 2-1
2.2
FEATURES ........................................................................................................................... 2-2
2.2.1
STANDARD FEATURES .............................................................................................. 2-2
2.2.2
MODEL DIFFERENCES ............................................................................................... 2-3
2.2.3
OPTIONS....................................................................................................................... 2-3
2.3
MECHANICAL DESIGN ...................................................................................................... 2-4
2.3.1
CABINET LAYOUT...................................................................................................... 2-4
2.3.2
CHASSIS LAYOUT....................................................................................................... 2-6
2.3.3
SYSTEM BOARD LAYOUT ......................................................................................... 2-7
2.4
SYSTEM ARCHITECTURE.................................................................................................. 2-8
2.4.1
MICROPROCESSOR................................................................................................... 2-10
2.4.2
MEMORY.................................................................................................................... 2-10
2.4.3
SUPPORT CHIPSET .................................................................................................... 2-11
2.4.4
MASS STORAGE ........................................................................................................ 2-11
2.4.5
SERIAL AND PARALLEL INTERFACES .................................................................. 2-11
2.4.6
UNIVERSAL SERIAL BUS INTERFACE ................................................................... 2-12
2.4.7
GRAPHICS SUBSYSTEM ........................................................................................... 2-12
2.5
SPECIFICATIONS .............................................................................................................. 2-13
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM ........................................................................
3.1
INTRODUCTION.................................................................................................................. 3-1
3.2
PENTIUM MMX-BASED PROCESSOR/MEMORY SUBSYSTEM..................................... 3-2
3.2.1
PENTIUM MMX MICROPROCESSOR......................................................................... 3-3
3.2.2
BUS/PROCESSING SPEED SELECT............................................................................ 3-4
3.2.3
SECONDARY (L2) CACHE MEMORY ........................................................................ 3-4
3.2.4
SYSTEM MEMORY...................................................................................................... 3-5
3.2.5
SUBSYSTEM CONFIGURATION................................................................................. 3-8
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CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1
INTRODUCTION.................................................................................................................. 4-1
4.2
PCI BUS OVERVIEW ........................................................................................................... 4-2
4.2.1
PCI CONNECTOR......................................................................................................... 4-3
4.2.2
PCI BUS MASTER ARBITRATION.............................................................................. 4-4
4.2.3
PCI BUS TRANSACTIONS........................................................................................... 4-5
4.2.4
OPTION ROM MAPPING ............................................................................................. 4-8
4.2.5
PCI INTERRUPT MAPPING ......................................................................................... 4-9
4.2.6
PCI CONFIGURATION............................................................................................... 4-10
4.3
ISA BUS OVERVIEW......................................................................................................... 4-11
4.3.1
ISA CONNECTOR ...................................................................................................... 4-12
4.3.2
ISA BUS TRANSACTIONS......................................................................................... 4-13
4.3.3
DIRECT MEMORY ACCESS...................................................................................... 4-15
4.3.4
INTERRUPTS.............................................................................................................. 4-18
4.3.5
INTERVAL TIMER..................................................................................................... 4-22
4.3.6
ISA CONFIGURATION............................................................................................... 4-22
4.4
SYSTEM CLOCK DISTRIBUTION .................................................................................... 4-23
4.5
REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-24
4.5.1
CONFIGURATION MEMORY BYTE DEFINITIONS ................................................ 4-25
4.6
I/O MAP AND REGISTER ACCESSING............................................................................ 4-41
4.6.1
SYSTEM I/O MAP ...................................................................................................... 4-41
4.6.2
87307 I/O CONTROLLER CONFIGURATION ........................................................... 4-42
4.7
SYSTEM MANAGEMENT SUPPORT ............................................................................... 4-44
4.7.1
FLASH ROM WRITE PROTECT ................................................................................ 4-44
4.7.2
PASSWORD PROTECTION........................................................................................ 4-45
4.7.3
I/O SECURITY ............................................................................................................ 4-46
4.7.4
USER SECURITY........................................................................................................ 4-46
4.7.5
TEMPERATURE SENSING ........................................................................................ 4-47
4.7.6
POWER MANAGEMENT ........................................................................................... 4-48
CHAPTER 5 INPUT/OUTPUT INTERFACES .....................................................................................
5.1
INTRODUCTION.................................................................................................................. 5-1
5.2
ENHANCED IDE INTERFACE ............................................................................................ 5-1
5.2.1
IDE PROGRAMMING................................................................................................... 5-1
5.2.2
IDE CONNECTORS ...................................................................................................... 5-8
5.3
DISKETTE DRIVE INTERFACE........................................................................................ 5-10
5.3.1
DISKETTE DRIVE PROGRAMMING ........................................................................ 5-11
5.3.2
DISKETTE DRIVE CONNECTOR.............................................................................. 5-14
5.4
SERIAL INTERFACES ....................................................................................................... 5-15
5.4.1
RS-232 INTERFACE ................................................................................................... 5-15
5.4.2
SERIAL INTERFACE PROGRAMMING .................................................................... 5-16
5.5
PARALLEL INTERFACE ................................................................................................... 5-21
5.5.1
STANDARD PARALLEL PORT MODE ..................................................................... 5-21
5.5.2
ENHANCED PARALLEL PORT MODE ..................................................................... 5-22
5.5.3
EXTENDED CAPABILITIES PORT MODE ............................................................... 5-22
5.5.4
PARALLEL INTERFACE PROGRAMMING .............................................................. 5-23
5.5.5
PARALLEL INTERFACE CONNECTOR ................................................................... 5-27
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5.6
KEYBOARD/POINTING DEVICE INTERFACE ............................................................... 5-28
5.6.1
KEYBOARD INTERFACE OPERATION ................................................................... 5-28
5.6.2
POINTING DEVICE INTERFACE OPERATION ....................................................... 5-30
5.6.3
KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING ......................... 5-30
5.6.4
KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR................................ 5-34
5.7
ETHERNET INTERFACE................................................................................................... 5-35
5.7.1
NIC CONFIGURATION/CONTROL ........................................................................... 5-36
5.7.2
NIC CONNECTORS.................................................................................................... 5-36
5.8
UNIVERSAL SERIAL BUS INTERFACE........................................................................... 5-37
5.8.1
USB CONFIGURATION.............................................................................................. 5-37
5.8.2
USB CONTROL........................................................................................................... 5-38
5.8.3
USB CONNECTOR ..................................................................................................... 5-38
CHAPTER 6 GRAPHICS SUBSYSTEM...............................................................................................
6.1
INTRODUCTION.................................................................................................................. 6-1
6.2
SUBSYSTEM DESCRIPTION .............................................................................................. 6-2
6.2.1
S3 TRIO64V2/GX GRAPHICS CONTROLLER ........................................................... 6-2
6.2.2
S3 TRIO64V2/GX GRAPHICS CONFIGURATIONS ................................................... 6-3
6.2.3
S3 TRIO64V2/GX GRAPHICS SUBSYSTEM PROGRAMMING................................. 6-4
6.2.4
MONITOR POWER CONTROL .................................................................................... 6-5
6.2.5
CONNECTORS ............................................................................................................. 6-6
CHAPTER 7 POWER SUPPLY AND DISTRIBUTION.......................................................................
7.1
INTRODUCTION.................................................................................................................. 7-1
7.2
POWER SUPPLY ASSEMBLY/CONTROL .......................................................................... 7-1
7.2.1
POWER SUPPLY ASSEMBLY...................................................................................... 7-2
7.2.2
POWER CONTROL....................................................................................................... 7-3
7.3
POWER DISTRIBUTION...................................................................................................... 7-4
7.3.1
3.5/5/12 VDC DISTRIBUTION...................................................................................... 7-4
7.3.2
LOW VOLTAGE DISTRIBUTION................................................................................ 7-5
7.4
SIGNAL DISTRIBUTION ..................................................................................................... 7-6
CHAPTER 8 BIOS ROM .......................................................................................................................
8.1
INTRODUCTION.................................................................................................................. 8-1
8.2
BOOT FUNCTIONS.............................................................................................................. 8-2
8.2.1
BOOT BLOCK............................................................................................................... 8-2
8.2.2
QUICKBOOT................................................................................................................. 8-2
8.2.3
SILENTBOOT ............................................................................................................... 8-2
8.3
ACCESSING CONFIGURATION MEMORY ....................................................................... 8-3
8.3.1
ACCESSING CMOS...................................................................................................... 8-3
8.3.2
SETTING DEFAULT PARAMETERS .......................................................................... 8-3
8.3.3
ACCESSING CMOS FEATURE BITS........................................................................... 8-4
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8.4
CLIENT MANAGEMENT SUPPORT................................................................................... 8-5
8.4.1
SYSTEM ID................................................................................................................... 8-7
8.4.2
SYSTEM INFORMATION TABLE ............................................................................... 8-7
8.4.3
TEMPERATURE SENSOR.......................................................................................... 8-12
8.4.4
DRIVE FAULT PREDICTION..................................................................................... 8-12
8.4.5
DIMM SUPPORT......................................................................................................... 8-13
8.4.6
SECURITY FUNCTIONS ............................................................................................ 8-15
8.4.7
ACCESSING CMOS FEATURE BITS......................................................................... 8-16
8.5
PNP SUPPORT .................................................................................................................... 8-17
8.6
POWER MANAGEMENT SUPPORT ................................................................................. 8-18
APPENDIX A ERROR MESSAGES AND CODES.............................................................................A
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
A.12
A.13
A.14
A.15
A.16
A.17
A.18
A.19
A.20
A.21
INTRODUCTION................................................................................................................. A-1
POWER-ON MESSAGES..................................................................................................... A-1
BEEP CODE MESSAGES.................................................................................................... A-1
POWER-ON SELF TEST (POST) MESSAGES.................................................................... A-2
PROCESSOR ERROR MESSAGES (1XX-XX) ...................................................................... A-3
MEMORY ERROR MESSAGES (2XX-XX)........................................................................... A-4
KEYBOARD ERROR MESSAGES (30X-XX) ....................................................................... A-4
PRINTER ERROR MESSAGES (4XX-XX) ............................................................................ A-5
VIDEO (GRAPHICS) ERROR MESSAGES (5XX-XX) .......................................................... A-5
DISKETTE DRIVE ERROR MESSAGES (6XX-XX) ......................................................... A-6
SERIAL INTERFACE ERROR MESSAGES (11XX-XX) ................................................... A-6
MODEM COMMUNICATIONS ERROR MESSAGES (12XX-XX).................................... A-7
HARD DRIVE ERROR MESSAGES (17XX-XX) ............................................................... A-8
HARD DRIVE ERROR MESSAGES (19XX-XX) ............................................................... A-9
VIDEO (GRAPHICS) ERROR MESSAGES (24XX-XX) .................................................... A-9
AUDIO ERROR MESSAGES (3206-XX)......................................................................... A-10
NETWORK INTERFACE ERROR MESSAGES (60XX-XX) ........................................... A-10
SCSI INTERFACE ERROR MESSAGES (65XX-XX, 66XX-XX, 67XX-XX) ....................... A-11
POINTING DEVICE INTERFACE ERROR MESSAGES (8601-XX).............................. A-11
CEMM PRIVILEDGED OPS ERROR MESSAGES........................................................ A-12
CEMM EXCEPTION ERROR MESSAGES ................................................................... A-12
APPENDIX B ASCII CHARACTER SET .............................................................................................
B.1
INTRODUCTION..................................................................................................................B-1
APPENDIX C KEYBOARD ...................................................................................................................
C.1
INTRODUCTION..................................................................................................................C-1
C.2
KEYSTROKE PROCESSING................................................................................................C-2
C.2.1
TRANSMISSIONS TO THE SYSTEM ..........................................................................C-3
C.2.2
KEYBOARD LAYOUTS ...............................................................................................C-4
C.2.3
KEYS.............................................................................................................................C-7
C.2.4
KEYBOARD COMMANDS.........................................................................................C-10
C.2.5
SCAN CODES .............................................................................................................C-10
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C.3
SCANNER DESCRIPTION .................................................................................................C-14
C.3.1
SCANNER OPERATION.............................................................................................C-15
C.3.2
SCANNER INTERFACE .............................................................................................C-18
C.3.3
SCANNER SPECIFICATIONS/REQUIREMENTS......................................................C-20
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LIST OF FIGURES
FIGURE 2–1. COMPAQ DESKPRO 4000S PERSONAL COMPUTER WITH MONITOR ....................................... 2-1
FIGURE 2–2. CABINET LAYOUT, FRONT VIEW ....................................................................................... 2-4
FIGURE 2–3. CABINET LAYOUT, REAR VIEW ......................................................................................... 2-5
FIGURE 2–4. CHASSIS LAYOUT, TOP VIEW ............................................................................................ 2-6
FIGURE 2–5. SYSTEM BOARD LAYOUT, COMPONENT SIDE ..................................................................... 2-7
FIGURE 2–6. COMPAQ DESKPRO 4000N AND 4000S SYSTEM ARCHITECTURE, BLOCK DIAGRAM .............. 2-9
FIGURE 2–7. MICROPROCESSOR ARCHITECTURAL DIAGRAM ................................................................ 2-10
FIGURE 3–1. PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE ............................................................ 3-2
FIGURE 3–2. PENTIUM MMX MICROPROCESSOR INTERNAL ARCHITECTURE ........................................... 3-3
FIGURE 3–3. SYSTEM MEMORY MAP ....................................................................................................... 3-7
FIGURE 4–1. PCI BUS DEVICES AND FUNCTIONS ..................................................................................... 4-2
FIGURE 4–2. 32-BIT PCI BUS CONNECTOR (32-BIT TYPE) ..................................................................... 4-3
FIGURE 4–3. TYPE 0 CONFIGURATION CYCLE ........................................................................................ 4-6
FIGURE 4–4. PCI CONFIGURATION SPACE MAP...................................................................................... 4-7
FIGURE 4–5. ISA BUS BLOCK DIAGRAM ................................................................................................ 4-11
FIGURE 4–6. ISA EXPANSION CONNECTOR.......................................................................................... 4-12
FIGURE 4–7. MASKABLE INTERRUPT PROCESSING, BLOCK DIAGRAM .................................................... 4-18
FIGURE 4–8. CONFIGURATION MEMORY MAP ...................................................................................... 4-24
FIGURE 5–1. 40-PIN IDE CONNECTOR. ................................................................................................. 5-8
FIGURE 5–1. 50-PIN IDE CONNECTOR. ................................................................................................. 5-9
FIGURE 5–2. 34-PIN DISKETTE DRIVE CONNECTOR.............................................................................. 5-14
FIGURE 5–3. SERIAL INTERFACES BLOCK DIAGRAM ............................................................................. 5-15
FIGURE 5–4. SERIAL INTERFACE CONNECTOR (MALE DB-9 AS VIEWED FROM REAR OF CHASSIS) ........... 5-15
FIGURE 5–5. PARALLEL INTERFACE CONNECTOR (FEMALE DB-25 AS VIEWED FROM REAR OF CHASSIS) .. 5-27
FIGURE 5–6. 8042-TO-KEYBOARD TRANSMISSION OF CODE EDH, TIMING DIAGRAM ............................ 5-28
FIGURE 5–7. KEYBOARD OR POINTING DEVICE INTERFACE CONNECTOR ............................................... 5-34
FIGURE 5–8. ETHERNET INTERFACE BLOCK DIAGRAM ......................................................................... 5-35
FIGURE 5–9. ETHERNET AUI CONNECTOR (DB-15, VIEWED FROM REAR) ............................................. 5-36
FIGURE 5–10. ETHERNET RJ-45 CONNECTOR ...................................................................................... 5-36
FIGURE 5–11. UNIVERSAL SERIAL BUS CONNECTOR (ONE OF TWO AS VIEWED FROM REAR OF CHASSIS)... 5-38
FIGURE 6–1. S3 TRIO64V2/GX-BASED GRAPHICS SUBSYSTEM, BLOCK DIAGRAM................................... 6-2
FIGURE 6–2. VGA MONITOR CONNECTOR, (FEMALE DB-15, AS VIEWED FROM THE REAR OF CHASSIS). ... 6-6
FIGURE 7–1. POWER SUPPLY ASSEMBLY, BLOCK DIAGRAM.................................................................... 7-1
FIGURE 7–2. POWER CABLE DIAGRAM .................................................................................................. 7-4
FIGURE 7–3. LOW VOLTAGE SUPPLY, BLOCK DIAGRAM ......................................................................... 7-5
FIGURE 7–4. SIGNAL DISTRIBUTION DIAGRAM....................................................................................... 7-6
FIGURE C–1. KEYSTROKE PROCESSING ELEMENTS, BLOCK DIAGRAM ....................................................C-2
FIGURE C–2. KEYBOARD-TO-SYSTEM TRANSMISSION OF CODE 58H, TIMING DIAGRAM ..........................C-3
FIGURE C–3. U.S. ENGLISH (101-KEY) KEYBOARD KEY POSITIONS .......................................................C-4
FIGURE C–4. NATIONAL (102-KEY) KEYBOARD KEY POSITIONS ............................................................C-4
FIGURE C–5. U.S. ENGLISH WINDOWS (101W-KEY) KEYBOARD KEY POSITIONS ...................................C-5
FIGURE C–6. NATIONAL WINDOWS (102W-KEY) KEYBOARD KEY POSITIONS ........................................C-5
FIGURE C–7. U.S. ENGLISH WINDOWS (101WE-KEY) KEYBOARD KEY POSITIONS .................................C-6
FIGURE C–8. NATIONAL WINDOWS (102WE-KEY) KEYBOARD KEY POSITIONS ......................................C-6
FIGURE C–9. SCANNER ELEMENTS, BLOCK DIAGRAM ..........................................................................C-14
FIGURE C–10. SCANNER OPERATION FLOW CHART ..............................................................................C-16
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LIST OF TABLES
TABLE 1–1. ACRONYMS AND ABBREVIATIONS ....................................................................................... 1-3
TABLE 2–1. ARCHITECTURAL COMPARISON............................................................................................. 2-8
TABLE 2–2. SUPPORT CHIPSETS .......................................................................................................... 2-11
TABLE 2–3. GRAPHICS SUBSYSTEM OVERVIEW .................................................................................... 2-12
TABLE 2–4. ENVIRONMENTAL SPECIFICATIONS.................................................................................... 2-13
TABLE 2–5. ELECTRICAL SPECIFICATIONS ........................................................................................... 2-13
TABLE 2–6. PHYSICAL SPECIFICATIONS ............................................................................................... 2-13
TABLE 2–7. DISKETTE DRIVE SPECIFICATIONS ..................................................................................... 2-14
TABLE 2–8. 8X CD-ROM DRIVE SPECIFICATIONS................................................................................ 2-14
TABLE 2–9. HARD DRIVE SPECIFICATIONS ........................................................................................... 2-15
TABLE 3–1. PROCESSOR/MEMORY ARCHITECTURAL HIGHLIGHTS ............................................................ 3-1
TABLE 3–2. PENTIUM MMX MICROPROCESSOR BUS/CORE SPEED SWITCH SETTINGS ............................. 3-4
TABLE 3–3. SW1 BUS/CORE SPEED POSITIONS TO GPIO ASSIGNMENTS ................................................... 3-4
TABLE 3–4. SDRAM PERFORMANCE TIMES ............................................................................................ 3-5
TABLE 3–5. SPD ADDRESS MAP (SDRAM DIMM)................................................................................. 3-6
TABLE 3–6. HOST/PCI BRIDGE CONFIGURATION REGISTERS (VT82C595) .............................................. 3-8
TABLE 4–1. 32-BIT PCI BUS CONNECTOR PINOUT ................................................................................. 4-3
TABLE 4–2. PCI BUS MASTERING DEVICES ........................................................................................... 4-4
TABLE 4–3. PCI DEVICE CONFIGURATION ACCESS ................................................................................ 4-6
TABLE 4–4. PCI FUNCTION CONFIGURATION ACCES.............................................................................. 4-7
TABLE 4–5. PCI DEVICE IDENTIFICATION ............................................................................................. 4-8
TABLE 4–6. PCI/ISA BRIDGE CONFIGURATION REGISTERS FOR THE VT82C586 (P55C-BASED SYSTEMS)4-10
TABLE 4–7. ISA EXPANSION CONNECTOR PINOUT............................................................................... 4-12
TABLE 4–8. DEFAULT DMA CHANNEL ASSIGNMENTS ......................................................................... 4-15
TABLE 4–9. DMA PAGE REGISTER ADDRESSES ................................................................................... 4-16
TABLE 4–10. DMA CONTROLLER REGISTERS...................................................................................... 4-17
TABLE 4–11. MASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS .................................................... 4-19
TABLE 4–12. MASKABLE INTERRUPT CONTROL REGISTERS .................................................................. 4-19
TABLE 4–13. INTERVAL TIMER FUNCTIONS ......................................................................................... 4-22
TABLE 4–14. INTERVAL TIMER CONTROL REGISTERS........................................................................... 4-22
TABLE 4–15. CLOCK GENERATION AND DISTRIBUTION (PENTIUM-BASED SYSTEM)............................... 4-23
TABLE 4–16. CONFIGURATION MEMORY (CMOS) MAP ....................................................................... 4-25
TABLE 4–17. SYSTEM I/O MAP ........................................................................................................... 4-41
TABLE 4–18. 87307 I/O CONTROLLER PNP STANDARD CONTROL REGISTERS ........................................ 4-42
TABLE 4–19. SYSTEM MANAGEMENT CONTROL REGISTERS ................................................................... 4-44
TABLE 5–1. IDE PCI CONFIGURATION REGISTERS ................................................................................ 5-2
TABLE 5–2. IDE BUS MASTER CONTROL REGISTERS ............................................................................. 5-2
TABLE 5–3. IDE ATA CONTROL REGISTERS ......................................................................................... 5-3
TABLE 5–4. IDE CONTROLLER COMMANDS .......................................................................................... 5-6
TABLE 5–5. 40-PIN IDE CONNECTOR PINOUT ....................................................................................... 5-8
TABLE 5–6. 40-PIN IDE CONNECTOR PINOUT ....................................................................................... 5-9
TABLE 5–7. DISKETTE DRIVE CONTROLLER CONFIGURATION REGISTERS ............................................. 5-11
TABLE 5–8. DISKETTE DRIVE CONTROLLER REGISTERS ....................................................................... 5-12
TABLE 5–9. 34-PIN DISKETTE DRIVE CONNECTOR PINOUT ................................................................... 5-14
TABLE 5–10. DB-9 SERIAL CONNECTOR PINOUT ................................................................................. 5-15
TABLE 5–11. SERIAL INTERFACE CONFIGURATION REGISTERS.............................................................. 5-16
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TABLE 5–12.
TABLE 5–13.
TABLE 5–14.
TABLE 5–15.
TABLE 5–16.
TABLE 5–17.
TABLE 5–18.
TABLE 5–19.
TABLE 5–20.
TABLE 5–21.
TABLE 5–22.
SERIAL INTERFACE CONTROL REGISTERS ........................................................................ 5-17
PARALLEL INTERFACE CONFIGURATION REGISTERS ......................................................... 5-23
PARALLEL INTERFACE CONTROL REGISTERS ................................................................... 5-24
DB-25 PARALLEL CONNECTOR PINOUT .......................................................................... 5-27
8042-TO-KEYBOARD COMMANDS .................................................................................. 5-29
KEYBOARD/MOUSE INTERFACE CONFIGURATION REGISTERS ........................................... 5-30
CPU COMMANDS TO THE 8042...................................................................................... 5-32
KEYBOARD/POINTING DEVICE CONNECTOR PINOUT ........................................................ 5-34
USB INTERFACE CONFIGURATION REGISTERS ................................................................. 5-37
USB CONTROL REGISTERS ............................................................................................. 5-38
USB CONNECTOR PINOUT .............................................................................................. 5-38
TABLE 6–1.
TABLE 6–2.
TABLE 6–3.
TABLE 6–4.
TABLE 6–5.
TABLE 6–6.
TABLE 6–7.
GRAPHICS SUBSYSTEM COMPARISON .................................................................................. 6-1
S3 TRIO64V2/GX-BASED SUBSYSTEM EXTENDED VGA MODES ......................................... 6-3
GD5436 PCI CONFIGURATION SPACE REGISTERS ............................................................... 6-4
STANDARD VGA MODE I/O MAPPING ................................................................................ 6-4
S3-SPECIFIC CONTROL REGISTER MAPPING......................................................................... 6-5
MONITOR POWER MANAGEMENT CONDITIONS .................................................................... 6-5
DB-15 MONITOR CONNECTOR PINOUT ............................................................................... 6-6
TABLE 7–1. POWER SUPPLY SPECIFICATIONS ......................................................................................... 7-2
TABLE 8–1. PNP CLIENT MANAGEMENT FUNCTIONS (INT15)................................................................ 8-5
TABLE 8–1. PNP BIOS FUNCTIONS ..................................................................................................... 8-17
TABLE 8–2. APM BIOS FUNCTIONS (INT15) ..................................................................................... 8-19
TABLE A–1. POWER-ON MESSAGES ..................................................................................................... A-1
TABLE A–2. BEEP CODE MESSAGES ..................................................................................................... A-1
TABLE A–3. POWER-ON SELF TEST (POST) MESSAGES ........................................................................ A-2
TABLE A–4. PROCESSOR ERROR MESSAGES ......................................................................................... A-3
TABLE A–5. MEMORY ERROR MESSAGES ............................................................................................. A-4
TABLE A–6. KEYBOARD ERROR MESSAGES .......................................................................................... A-4
TABLE A–7. PRINTER ERROR MESSAGES .............................................................................................. A-5
TABLE A–8. VIDEO (GRAPHICS) ERROR MESSAGES .............................................................................. A-5
TABLE A–9. DISKETTE DRIVE ERROR MESSAGES.................................................................................. A-6
TABLE A–10. SERIAL INTERFACE ERROR MESSAGES ............................................................................. A-6
TABLE A–11. SERIAL INTERFACE ERROR MESSAGES ............................................................................. A-7
TABLE A–12. HARD DRIVE ERROR MESSAGES ...................................................................................... A-8
TABLE A–13. HARD DRIVE ERROR MESSAGES ...................................................................................... A-9
TABLE A–14. HARD DRIVE MESSAGES ................................................................................................. A-9
TABLE A–15. AUDIO ERROR MESSAGES ............................................................................................. A-10
TABLE A–16. NETWORK INTERFACE ERROR MESSAGES ...................................................................... A-10
TABLE A–17. SCSI INTERFACE ERROR MESSAGES ............................................................................. A-11
TABLE A–18. POINTING DEVICE INTERFACE ERROR MESSAGES........................................................... A-11
TABLE A–19. CEMM PRIVILEGED OPS ERROR MESSAGES.................................................................. A-12
TABLE A–20. CEMM EXCEPTION ERROR MESSAGES ......................................................................... A-12
TABLE B–1. ASCII CHARACTER SET ....................................................................................................B-1
TABLE C–1.
TABLE C–2.
TABLE C–3.
TABLE C–4.
TABLE C–5.
x
KEYBOARD-TO-SYSTEM COMMANDS ...............................................................................C-10
KEYBOARD SCAN CODES .................................................................................................C-11
SCANNER PERFORMANCE CHART .....................................................................................C-17
SCANNER I/F SIGNALS .....................................................................................................C-18
SCANNER SPECIFICATIONS ...............................................................................................C-20
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
Chapter 1
INTRODUCTION
1. Chapter 1 INTRODUCTION
1.1
ABOUT THIS GUIDE
This guide provides technical information about the Compaq Deskpro 4000N and 4000S
Personal Computers. This document includes information regarding system design, function, and
features that can be used by programmers, engineers, technicians, and system administrators.
1.1.1
USING THIS GUIDE
This guide consists of chapters and appendices. The chapters primarily describe the hardware
and firmware elements contained within the chassis and specifically deal with the system board
and the power supply assembly. The appendices contain general information about standard
peripheral devices such as the keyboard as well as separate audio or other interface cards, as well
as other general information in tabular format.
1.1.2
ADDITIONAL INFORMATION SOURCES
This guide does not describe in detail other manufacturer’s components used in the product
covered. For more information on individual commercial-off-the-shelf (COTS) components refer
to the indicated manufacturers’ documentation. The products covered by this guide use
architecture based on industry-standard specifications that can be referenced for detailed
information.
Hardcopy documentation sources:
♦
♦
♦
♦
The Lotus/Intel/Microsoft Expanded Memory Specification, Ver. 4.0
PCI Local Bus Specification Revision 2.1
Extended Industry Standard Architecture Expansion Bus Technical Reference Guide,
p/n 130584, Second Edition, Compaq Computer Corporation
Compaq Basic Input/Out System (BIOS) Technical Reference Guide
Doc.# 074A/0693, Fourth Edition, Compaq Computer Corporation
Online information sources:
♦
♦
♦
♦
♦
Compaq Computer Corporation: http://www.compaq.com
Intel Corporation: http://www.intel.com
VIA Technologies Incorporated: http://www.via.com
National Semiconductor: http://www.national.com
S3 Incorporated: http://www.S3.com
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
1-1
Chapter 1 Introduction
1.2
NOTATIONAL CONVENTIONS
1.2.1
VALUES
Hexadecimal values are indicated by the letter “h” following an alpha-numerical value. Binary
values are indicated by the letter “b” following a value of ones and zeros. Memory addresses
expressed as “SSSS:OOOO” (SSSS = 16-bit segment, OOOO = 16-bit offset) can be assumed as
a hexadecimal value. Values that have no succeeding letter can be assumed to be decimal.
1.2.2
RANGES
Ranges or limits for a parameter are shown as a pair of values separated by two dots:
Example: Bits <7..4> = bits 7, 6, 5, and 4.
1.2.3
SIGNAL LABELS
Signal names are indicated using abbreviations, acronyms, or, if possible, the full signal name in
all capital letters. Signals that are meant to be active low are indicated with a dash immediately
following the name.
1.2.4
REGISTER NOTATION AND USAGE
This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing
scheme are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.
1.2.5
BIT NOTATION
Bit values are labeled with bit <0> representing the least-significant bit (LSb) and bit <7>
representing the most-significant bit (MSb) of a byte. Bytes, words, double words, and quad
words are typically shown with most-significant portions on the left or top and the leastsignificant portions on the right or bottom respectively.
1-2 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
1.3
COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1–1. Acronyms and Abbreviations
Table 1-1.
Acronyms and Abbreviations
Acronym/Abbreviation
A
AC
ACPI
A/D
AGP
API
APM
ASIC
AT
ATA
AVI
AVGA
BCD
BIOS
bis
BitBLT
BNC
bps or b/s
BSP
CAS
CD
CD-ROM
CDS
CF
CGA
Ch
CLUT
cm
CMC
CMOS
Cntlr
codec
CPQ
CPU
CRT
CSM
DAA
DAC
db
DC
DCH
DDC
DF
Description
ampere
alternating current
Advanced Configuration and Power Interface
analog-to-digital
advanced graphics port
application programming interface
advanced power management
application-specific integrated circuit
1. attention (commands) 2. 286-based PC architecture
AT attachment (mode)
audio-video interleaved
Advanced VGA
binary-coded decimal
basic input/output system
second/new revision
bit block transfer
Bayonet Neill-Concelman (connector)
bits per second
Bootstrap processor
column address strobe
compact disk
compact disk read-only memory
compct disk system
carry flag
color graphics adapter
channel
color look-up table (pallete)
centimeter
cache/memory controller
complimentary metal-oxide semiconductor (configuration memory)
controller
compressor/decompressor
Compaq
central processing unit
cathode ray tube
Compaq system management / Compaq server management
direct access arrangement
digital-to-analog converter
decibel
direct current
DOS compatibility hole
Display Data Channel
direction flag
Continued
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
1-3
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
DIMM
DIN
DIP
DMA
dpi
DRAM
DRQ
EDID
EDO
EEPROM
EGA
EIA
EISA
EPP
EIDE
ESCD
EV
ExCA
FIFO
FL
FM
FPM
FPU
ft
GB
GND
GPIO
GPOC
GUI
h
HW
hex
Hz
IDE
IEEE
IF
I/F
in
INT
I/O
IPL
IrDA
IRQ
ISA
JEDEC
Kb / KB
Kb/s
kg
KHz
kv
Description
dual inline memory module
Deutche IndustriNorm (connector standard)
dual inline package
direct memory access
dots per inch
dynamic random access memory
data request
extended display identification data
extended data out (RAM type)
electrically eraseable PROM
enhanced graphics adapter
Electronic Industry Association
extended ISA
enhanced parallel port
enhanced IDE
Extended System Configuration Data (format)
Environmental Variable (data)
Exchangeable Card Architecture
first in / first out
flag (register)
frequency modulation
fast page mode (RAM type)
Floating point unit (numeric or math coprocessor)
foot
gigabyte
ground
general purpose I/O
general purpose open-collector
graphics user interface
hexadecimal
hardware
hexadecimal
hertz
integrated drive element
Institute of Electrical and Electronic Engineers
interrupt flag
interface
inch
interrupt
input/output
initial program loader
InfraRed Data Association
interrupt request
industry standard architecture
Joint Electron Device Engineering Council
kilobits / kilobytes (x 1024 bits / x 1024 bytes)
kilobits per second
kilogram
kilohertz
kilovolt
Continued
1-4 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
lb
LCD
LED
LIF
LSI
LSb / LSB
LUN
MMX
MPEG
MOSFET
ms
MSb / MSB
mux
MVA
MVW
n
NIC
NiCad
NiMH
NMI
ns
NT
NTSC
NVRAM
OEM
OS
PAL
PC
PCI
PCM
PCMCIA
PF
PIN
POST
PROM
PTR
RAM
RAS
rcvr
RF
RGB
RH
RMS
ROM
RPM
RTC
R/W
Description
pound
liquid crystal display
light-emitting diode
low insertion force (socket)
large scale integration
least significant bit / least significant byte
logical unit (SCSI)
multimedia extensions
Motion Picture Experts Group
Metal oxide silicon field effect transistor
millisecond
most significant bit / most significant byte
multiplex
motion video acceleration
motion video window
variable parameter/value
network interface card/controller
nickel cadmium
nickel-metal hydride
non-maskable interrupt
nanosecond
nested task flag
National Television Standards Committee
non-volatile random access memory
original equipment manufacturer
operating system
1. programmable array logic 2. phase altering line
personal computer
peripheral component interconnect
pulse code modulation
Personal Computer Memory Card International Association
parity flag
personal identification number
power-on self test
programmable read-only memory
pointer
random access memory
row address strobe
receiver
resume flag
red/green/blue
Relative humidity
root mean square
read-only memory
revolutions per minute
real time clock
read/write
Continued
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
1-5
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
SCSI
SDRAM
SEC
SECAM
SF
SGRAM
SIMM
SIT
SMI
SMM
SMRAM
SPD
SPP
SRAM
STN
SVGA
SW
TAD
TAM
TCP
TF
TFT
TIA
TPE
TPI
TTl
TV
TX
UART
us / µs
USB
UTP
V
VESA
VGA
vib
VLSI
VRAM
W
WRAM
ZF
ZIF
Description
small computer system interface
Synchronous Dynamic RAM
Single Edge-Connector
sequential colour avec memoire (sequential color with memory)
sign flag
Synchronous Graphics RAM
single in-line memory module
system information table
system management interrupt
system management mode
system management RAM
serial presence detect
standard parallel port
static RAM
super twist pneumatic
super VGA
software
telephone answering device
telephone answering machine
tape carrier package
trap flag
thin-film transistor
Telecommunications Information Administration
twisted pair ethernet
track per inch
transistor-transistor logic
television
transmit
universal asynchronous receiver/transmitter
microsecond
Universal Serial Bus
unshielded twisted pair
volt
Video Electronic Standards Association
video graphics adapter
vibrato
very large scale integration
Video RAM
watt
Windows RAM
zero flag
zero insertion force (socket)
1-6 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Chapter 2
SYSTEM OVERVIEW
2.
2.1
Chapter 2 SYSTEM OVERVIEW
INTRODUCTION
The Compaq Deskpro 4000N and 4000S Personal Computers are based on Pentium
microprocessors featuring MMX technology and designed with an emphasis on speed, storage
capacity, and multimedia compatibility to meet the requirements of the business environment.
These models feature architectures incorporating the PCI and ISA buses. All models are easily
upgradeable and expandable to keep pace with the needs of the office or home.
Figure 2–1. Compaq Deskpro 4000S Personal Computer with Monitor
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition -September
2-1
Chapter 2 System Overview
2.2
FEATURES
This section describes the standard and distinguishing features.
2.2.1
STANDARD FEATURES
The following standard features are included on all models:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Pentium microprocessor with MMX technology
256-KB second-level cache
16 or 32 megabytes of SDRAM, with support for ECC and SDP memory
Integrated S3 Trio64V2/GX graphics controller with 2-MB frame
Enhanced IDE controller supporting Ultra ATA (UDMA) modes 0-2
Hard drive fault prediction
PCI connector
Two serial interfaces
Parallel interface
Two universal serial bus ports
Integrated network interface controller (RJ-45/AUI ports)
Compaq Space Saver keyboard w/Windows support
Compaq PS/2-type mouse
APM 1.2 power management support
Plug ’n Play compatible (with ESCD support)
Energy Star compliant
76-watt, surge-tolerant power supply
The Deskpro 4000N and 4000S support the Intelligent Manageability features listed below:
Configuration
Management
Remote ROM Flash
Remote Security
Remote Wakeup
Remote Shutdown
Replicated Setup
ACPI-Ready
Dual-State Power Sw.
Failsafe Boot Block ROM
Asset
Management
RAM Type Data
DMI BIOS
Asset Tag
Sys. Serial #
Sys. Manuf./Model
Sys. Board Rev. Level
ROM rev.
Hard Drive Type Data
Monitor Type Data
Compaq Insight Edition
Fault
Management
ECC RAM Fault Prediction
SMART II Hard Drive
Monitor Fault Diag.
UDMA Integrity Log.
Proactive Backup
Thermal Sensor
Security
Management
Memory Change Alert
Ownership Tag
Config. Cntrl. Hardware
Setup Password
Power-On Password
QuickLock/QuickBlank
Diskette Boot Cntrl.
Diskette Write Cntrl.
I/O Port En/Dis. Cntrl.
Cable Lock Provision
The Intelligent Manageability features provide support for DMI 2.0, Compaq Insight Manager,
and Management Solutions Partners.
2-2
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
2.2.2
MODEL DIFFERENCES
Deskpro 4000N
PCI connector:
1
ISA connector:
none
OS installed:
Windows NT 4.0
Remote boot support:
Yes
Diskette drive installed:
No
Hard drive size:
1.6 or 2.1 GB
CD-ROM support:
No
2.2.3
Deskpro 4000S
1 (shared slot)
1 (shared slot)
Windows 95
No
Yes
2.1 GB
Yes
OPTIONS
Options that are specific to the Compaq Deskpro 4000N and 4000S Series Personal Computers
include:
♦
System Memory: 8-MB DIMM
16-MB DIMM
32-MB DIMM
64-MB DIMM
128-MB DIMM
Compaq Deskpro Computers are easily upgraded and enhanced with peripheral devices designed
to meet PCI and ISA standards. The Compaq Deskpro Personal Computers are compatible with
peripherals design for Plug ’n Play operation.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition -September
2-3
Chapter 2 System Overview
2.3
MECHANICAL DESIGN
This section illustrates the layout used by the formfactor. In addition, this section includes the
layout of the system board.
2.3.1
CABINET LAYOUT
4
5
6
1
2
3
Item
1
2
3
4
5
6
Function
Power Switch
Power-On Light
Hard Drive Activity Light
1.44 MB Diskette Drive (3.5” Drive) [1]
1/3 Height Drive Bay (3.5” or 5.25” Drive) [2]
1/3 Height Drive Bay (3.5” or 5.25” Drive)
NOTES:
[1] Deskpro 4000S only
[2] Front panel access on 4000S only.
Figure 2–2. Cabinet Layout, Front View
2-4
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
2
1
Item
1
2
3
4
5
6
7
8
9
10
11
12
4
3
6
5
7
8
9
10
12
11
Function
AC Line In Connector
Line Voltage Select Switch
Universal Serial Bus Interface port 1
Universal Serial Bus Interface port 2
Parallel Interface Connector
Serial Interface Connector B
Serial Interface Connector A
Network Interface AUI Connector
Network Interface RJ-45 Connector
Mouse Connector
Keyboard Connector
Monitor Interface
Figure 2–3. Cabinet Layout, Rear View
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition -September
2-5
Chapter 2 System Overview
2.3.2
CHASSIS LAYOUT
ISA Combo Slot 1 [1]
PCI Combo Slot 1
Slots On Riser Card,
Rear View
Back
Power Supply
System Board
Drive Bays
Front
NOTES:
[1] Deskpro 4000S only
Figure 2–4. Chassis Layout, Top View
2-6
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
2.3.3
SYSTEM BOARD LAYOUT
1
2
3
4
5
6
7
8
9
20
10
11
12
19
13
14
18
15
16
17
System Board
p/n 006582-xxx (4000S)
or
p/n 007602-xxx (4000N)
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function
Graphics monitor connector (J2)
Top, Mouse interface connector; Bottom, keyboard connector (J9)
NIC AUI connector header (P15)
NIC RJ-45 connector (J5)
Serial interface connector (P24)
Parallel interface connector (J3)
Universal serial bus connectors (J6)
Power supply connector (P17)
RTC/CMOS Battery
RTC/CMOS battery replacement header (P14)
Power switch, PWR/HD LED cable connector (P16)
Processing frequency configuration switch (SW1)
CD-ROM connector (P25)
Secondary IDE connector (P21)
Primary IDE connector (P20)
Diskette drive connector (J1)
Microprocessor (in type 7 socket)
DIMM sockets (J7, J8)
CD-ROM drive connector P25 audio out (J11)
Riser card connector (J4)
Figure 2–5. System Board Layout, Component Side
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition -September
2-7
Chapter 2 System Overview
2.4
SYSTEM ARCHITECTURE
The Compaq Deskpro 4000N and 4000S Personal Computers featuring MMX technology are
based on a Pentium MXX microprocessor matched with a support chipset that is complimentary
in design. Both the “N” and “S” systems share the same basic architecture (Figure 2-7), which
utilizes three main buses: the Host bus, the Peripheral Component Interconnect (PCI) bus, and
the Industry Standard Architecture (ISA) bus.
The Host bus provides high performance support for CPU, cache and system memory accesses,
and on these systems is set to operate at 66 MHz. The 32-bit PCI bus provides support for the
graphics subsystem, the EIDE controllers, and expansion devices designed for high performance.
The PCI bus operates at 33 MHz. The ISA bus provides a standard 8-MHz interface for the
input/output (I/O) devices such as the keyboard, diskette drive, serial and parallel interfaces, as
well as the addition of 16- or 8-bit expansion devices.
The CPU/PCI and PCI/ISA bridge functions are handled by the specific support chipset matched
with the microprocessor employed. The support chipset also provides memory controller and data
buffering functions as well as bus control and arbitration functions.
The I/O port functions and diskette drive controller are integrated into the PC87307 I/O
Controller. This component also includes the real time clock and battery-backed configuration
memory (CMOS).
Table 2-1 lists the architectural highlights.
Table 2–1. Architectural Comparison
Table 2-1.
Architectural Overview
Type
Pentium MMX
VIA VP2
Microprocessor
Support Chipset
System Memory
Standard installed:
Expandable to:
Cache Memory
L1:
L2:
Graphics Subsystem
16/32 MB [1]
256 MB
32 KB [2]
256 KB
S3 TrioV2-based
integrated on board
NOTES:
[1] Depending on model
[2] Integrated with the microprocessor
The following subsections provide a description of the key functions and subsystems.
2-8
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
64-Bit Host Bus
Mem. Bus
System
Memory
North
Bridge
Microprocessor
and Cache Memory
Graphics
Subsystem
32-Bit
PCI Bus 0
PCI Connector
Pri.
IDE I/F
EIDE
Hard Drive
Sec.
IDE I/F
CD-ROM
South
Bridge
8-/16-Bit
ISA Bus
USB
I/F (2)
X-Bus
BIOS
ROM
ISA Connector [1]
EIDE
Hard Drive
PC 87307 I/O Controller
Keyboard/
Mouse I/F
Diskette
I/F
Serial
I/F (2)
Parallel
I/F
Power
Supply
NOTES:
CD models only.
[1] Deskpro 4000S only.
Figure 2–6. Compaq Deskpro 4000N and 4000S System Architecture, Block diagram
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition -September
2-9
Chapter 2 System Overview
2.4.1
MICROPROCESSOR
The Compaq Deskpro 4000N and 4000S Personal Computers feature the Pentium MMX
microprocessor that is backward-compatible with software written for x86-type processors. The
Pentium MMX microprocessor includes a 32 KB L1 cache and extensions to the instruction set
that provide higher performance for processing graphics and video code. The microprocessor is
mounted in a ZIF type-7 socket that allows replacing and/or upgrading.
Pentium MMX Microprocessor
Dual-ALU
CPU w/MMX
32-KB
Cache
Branch
Prediction
Dual Pipeline
Math Coproc.
(Mounted in Type 7 Connector)
Figure 2–7. Microprocessor Architectural Diagram
2.4.2
MEMORY
This system includes 256 kilobytes of SRAM for secondary (L2) cache support of the
microprocessor’s primary (L1) cache. The L2 cache is arranged as direct-mapped, write-through
using synchronous pipelined burst SRAMs.
For system memory two 168-pin DIMM sockets are provided with 16 or 32 megabytes of unbuffered SDRAM installed depending on model. System memory can be expanded up to 256
megabytes using 8-, 16-, 32-,64-, and 128-MB DIMMs. Both EDO and SDRAM DIMMs are
supported (SDRAM DIMMs are recommended). The system supports the use of ECC memory as
well.
The system ROM utilizes a flash ROM component that contains the BIOS and stores PCI, ESCD,
and EV data. The BIOS is updateable by remote or local flashing of the ROM, which includes
boot block ROM support.
2-10 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
2.4.3
SUPPORT CHIPSET
Table 2-2 shows the chipsets used for the Deskpro 4000N and 4000S systems.
Table 2–2. Support Chipsets
Table 2-2.
Support Chipsets
Function
Host/PCI (North) Bridge:
System Controller
Data Buffer
PCI/ISA (South) Bridge:
EIDE Controller
DMA Controller
Interrupt Controller
Timer/Counter
NMI Registers
Reset Control Reg.
USB I/F
I/O Controller:
Keyboard I/F
Diskette I/F
Serial I/F
Parallel I/F
RTC/CMOS Mem.
GPIO Ports
2.4.4
Component
VT82C595
“
“
VT82C586
“
“
“
“
“
“
“
87307
“
“
“
“
“
“
MASS STORAGE
A 1.6- or 2.1-GB EIDE hard drive may be installed, depending on series/model. All models
include a PCI bus mastering Enhanced IDE (EIDE) controller that provides two EIDE interfaces
supporting two IDE devices. Master/slave drive selection is determined using the cable-select
method, eliminating the need to move jumpers when re-configuring drives. The mass storage
drive bay capacity is determined by the form factor (refer to Section 2.3, Mechanical Design). All
Deskpro 4000S models include a 3.5 inch 1.44-MB diskette drive installed.
2.4.5
SERIAL AND PARALLEL INTERFACES
All models include two serial and one parallel port available at the rear of the unit chassis. The
serial and parallel ports are integrated into a PC87307 I/O Controller component. The serial
ports use 16550/16450-equivalent logic and are RS-232-C compatible and operate at baud rates
up to 115,200. The parallel interface is Enhanced Parallel Port (EPP1.9) and Enhanced
Capability Port (ECP) compatible, and supports bi-directional data transfers.
Compaq Deskpro 4000N and 4000S Personal Computers 2-11
First Edition -September
Chapter 2 System Overview
2.4.6
UNIVERSAL SERIAL BUS INTERFACE
Two Universal Serial Bus (USB) ports are included, each providing a high speed interface for
future systems and/or peripherals. The USB interface operates at 12 Mbps and provides hot
plugging/unplugging (Plug ’n Play) functionality.
2.4.7
GRAPHICS SUBSYSTEM
The graphics subsystem is integrated on the system board and operates off the PCI bus. The
subsystem is based on the S3 Trio64 V2/GX controller and includes two megabytes of SGRAM.
The subsystem provides a maximum resolution of 1280 x 1024 with 256 colors.
NOTE: The graphics subsystem is not upgradeable.
Table 2–3. Graphics Subsystem Overview
Table 2-3.
Graphics Subsystem Overview
Parameter
Graphics Controller
Graphics Memory
Maximum Resolution
Type
S3 Trio64V2
2 MB SGRAM
1280x1024 @ 256 colors
2-12 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
2.5
SPECIFICATIONS
This section includes the environmental, electrical, and physical specifications for the Compaq
Deskpro 4000N and 4000S Series Personal Computers.
Table 2–4. Environmental Specifications
Table 2-4.
Environmental Specifications
Parameter
Operating
o
o
o
o
Air Temperature
50 to 95 F (10 to 35 C)
Shock
N/A
Vibration
0.000215g^ 2/Hz, 10-300 Hz [1]
o
Humidity
80% RH @ 36 C (no hard drive)
Maximum Altitude
10,000 ft (3048 m)
NOTE:
Values are subject to change without notice.
[1] 0.5 grms nominal.
Nonoperating
o
o
o
o
-24 to 140 F (-30 to 60 C)
60.0 g for 2 ms half-sine pulse
0.0005g^ 2/Hz, 10-500 Hz [1]
o
95% RH @ 36 C
30,000 ft (9,144 m)
Table 2–5. Electrical Specifications
Table 2-5.
Electrical Specifications
Parameter
Input Line Voltage:
Nominal:
Maximum:
Input Line Frequency Range:
Nominal:
Maximum:
Power Supply
Maximum Continuous Power:
Maximum Line Current Draw:
Domestic
International
100 - 120 VAC
90 - 132 VAC
200 - 240 VAC
180 - 264 VAC
50 - 60 Hz
47 - 63 Hz
50 - 60 Hz
47 - 63 Hz
75 watts
5.5 A
75 watts
?? watts
3.0 A
Table 2–6. Physical Specifications
Table 2-6.
Physical Specifications
Dimension
Height
Width
Depth
Weight
NOTE:
Metric measurements shown in parenthesis.
Measurement
3.56 in (9.00 cm)
112.50 in (31.80 cm)
14.60 in (37.10 cm)
20 lb (9.08 kg)
Compaq Deskpro 4000N and 4000S Personal Computers 2-13
First Edition -September
Chapter 2 System Overview
Table 2–7. Diskette Drive Specifications
Table 2-7.
Diskette Drive Specifications
Paramemter
Media Type
Height
Bytes per Sector
Sectors per Track:
High Density
Low Density
Tracks per Side:
High Density
Low Density
Read/Write Heads
Average Access Time:
Track-to-Track (high/low)
Average (high/low)
Settling Time
Latency Average
Measurement
3.5 in 1.44 MB/720 KB diskette
1/3
512
18
9
80
80
2
3 ms/3 ms
94 ms/94ms
15 ms
100 ms
Table 2–8. 8x CD-ROM Drive Specifications
Table 2-8.
20x CD-ROM Drive Specifications
Paramemter
Media Type
Center Hole Diameter
Disc Diameter
Disc Thickness
Track Pitch
Laser
Beam Divergence
Output Power
Typr
Wave Length
Average Access Time:
Random
Full Stroke
Audio Output Level
Cache Buffer
Data Transfer Time
Sustained
Startup Time
Measurement
Mode 1,2, Mixed Mode, CD-DA,
Photo CD, Cdi, CD-XA
15 mm
8/12 cm
1.2 mm
1.6 um
53.5 +/- 1.5 °
53.6 0.14 mW
GaAs
790 +/- 25 nm
150 ms
600 ms
0.7 Vrms
128 KB (min)
3000 KB/s
7 secs (nom)
2-14 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Table 2–9. Hard Drive Specifications
Table 2-9.
Hard Drive Specifications
Parameter
Interface:
Drive Type:
Drive Size:
Transfer Rate
Heads:
Interface:
Seek Time (w/settling)
Single Track:
Average:
Full Stroke:
Disk RPM:
EDMA Support:
PIO Support:
Power Mode Command Support:
Drive Fault Prediction:
1.6 GB
EIDE
65
5.25 in
2.1 GB
EIDE
65
5.25 in
94.0 Mb/s
16.7 MB/s
27.2-55 Mb/s
16.7 MB/s
2.0 ms
11.0 ms
25.0 ms
4500
Mode 2
Mode 4
Yes
SMART II
2.0 ms
12.0 ms
22.0 ms
4500
Mode 2
Mode 4
Yes
SMART II
Compaq Deskpro 4000N and 4000S Personal Computers 2-15
First Edition -September
Chapter 2 System Overview
This page is intentionally blank.
2-16 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Chapter 3
PROCESSOR/
MEMORY SUBSYSTEM
3.
Chapter 3 PROCESSOR/MEMORY SUBSYSTEM
3.1
INTRODUCTION
This chapter describes the processor/cache memory subsystem of the Compaq Deskpro 4000N
and 4000S Series of Personal Computers.
This chapter includes the following topics:
♦
♦
Pentium MMX-based processor/memory subsystem [3.2]
page 3-2
Klamath-based processor/memory subsystem [3.4]
page 3-12
Table 3-1 lists the highlights of the processor/memory architecture.
Table 3–1. Processor/Memory Architectural Highlights
Table 3-1.
Processor/Memory
Architectural Highlights
Feature
Support Chipset
System Memory
Standard installed:
Expandable to:
Cache Memory
L1:
L2:
NOTES:
[1] Integrated into the microprocessor
Type/Amount
VT82C595
16 or 32 MB SDRAM
256 MB
32 KB [1]
256 KB
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
3-1
Chapter 3 Processor/Memory Subsystem
3.2
PENTIUM MMX-BASED PROCESSOR/MEMORY SUBSYSTEM
The processor/memory subsystem is based on the Pentium MMX microprocessor, a 512-KB or 1MB secondary cache, and a VT82C595 system controller (Figure 3-1).
Pentium MMX
Microprocessor
Memory/PCI
Data Buffer
()
256-KB
Secondary
Cache
64-Bit Host Bus
Cntl
Cntl
System Memory
J7
J8
16-MB
DIMM
DIMM
Mem.
Data Bus
Cache/
Memory/PCI
Controller
(VT82C595)
Mem. Addr.
32-bit PCI Bus
Optional module
Figure 3–1. Processor/Memory Subsystem Architecture
The microprocessor is mounted in a ZIF type 7 socket that facilitates easy changing/upgrading.
The system supports both 2.8V and 3.3V core processors. Replacing the microprocessor may
require reconfiguring a DIP switch to select the correct bus frequency/core frequency
combination. Frequency selection is described in detail later in this section.
The VT82C595 system controller provides the Host/PCI bridge functions and controls transfers
with the 64-bit memory data bus. The system includes 256 kilobytes of SRAM controlled by the
system controller as a direct-mapped, write-through L2 cache to the L1 cache integrated into the
microprocessor. The system supports synchronous, pipelined burst SRAM/DRAM for the L2
cache, providing 3-1-1-1 read/write cycles at 60 and 66 MHz on a cache hit.
The standard system memory configuration consists of 16 or 32 megabytes of SDRAM system
memory. The system memory can be expanded to 256 megabytes.
3-2 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
3.2.1
PENTIUM MMX MICROPROCESSOR
The Pentium MMX microprocessor is software-compatible with earlier generation x86
microprocessors but provides significantly higher performance due to both higher processing
speed and enhanced design (Figure 3-2.).
Pentium MMX Microprocessor
CPU
w/MMX
32-KB
Cache
Branch
Prediction
Dual Pipeline
Math Coproc.
Figure 3–2. Pentium MMX Microprocessor Internal Architecture
The Pentium MMX microprocessor contains a dual-ALU CPU, branch prediction logic, dualpipeline math coprocessor, and a 32-KB cache that is split into two 16-KB 4-way, set-associative
caches for handling code and data separately. The microprocessor is mounted in a ZIF type 7
socket for easy changing/upgrading of the microprocessor. Replacing the microprocessor may
require reconfiguring the settings of DIP switch SW1 to properly set the speed of the Host bus
and the core (processing) frequencies.
3.2.1.1 MMX Technology
The CPU of the Pentium MMX supports 57 additional instructions specifically designed for
accelerating multimedia and communications applications. Such applications often involve
compute-intensive loops that can take up as much as 90 percent of CPU execution time. The
MMX logic, using a parallel processing technique called Single Instruction-Multiple Data
(SIMD), operates on 64 bits at a time. The MMX instructions are designed to take advantage of
the dual-pipeline CPU as well as help the programmer in avoiding branches in code. Specific
applications that benefit from MMX technology include 2D/3D graphics, audio, speech
recognition, video codecs, and data compression .
NOTE: MMX operations utilize a portion of the floating point registers of the
integrated math coprocessor. Programmers should take note that mixing MMX code
with that of floating point operations can result in reduced performance and should
therefore be avoided.
.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
3-3
Chapter 3 Processor/Memory Subsystem
3.2.2
BUS/PROCESSING SPEED SELECT
The Pentium MMX-based system board includes a four-position DIP switch (SW1) that is used to
select the Host bus frequency and the processing frequency of the system. The SW1 positions 2
and 3 control the Bus Fraction (BF0, BF1) signals to the CPU, which determines the bus-to-core
speed ratio. Position 5 of SW1 determines the bus frequency generated by the clock generator
(refer to Chapter 4, “System Support” for more information on clock frequency generation).
Table 3-2 shows the switch configurations to be used with a particular microprocessor.
Table 3–2. Pentium MMX Microprocessor Bus/Core Speed Switch Settings
Table 3-2.
Pentium MMX Microprocessor
Bus/Core Speed Switch (SW1) Settings
DIP SW1 Settings [1]
Microprocessor
2
3
5
Bus/Core Speed (in MHz)
Off
Off
Off
60/210
Off
Off
On
66/233
Off
On
Off
60/180
Off
On
On
66/200
On
Off
Off
60/120
On
Off
On
66/133
On
On
Off
60/150
On
On
On
66/166
NOTES:
Shipping configurations are unshaded
NOTE:
SW1 should be set to match
the specified core speed of the
microprocessor. Configuring
for a core speed lower or
higher than that for which the
CPU is designed can result in
unstable or possibly
destructive operation.
The status of SW1-2, -3, and -5 is readable through general-purpose I/O (GPIO) port 78h bits
<2..0>, allowing BIOS and/or diagnostic software to check an installed microprocessor with the
switch configuration. Table 3-3 shows the switch position-to-GPIO-to-I/O port 78h input wiring.
Table 3–3. SW1 Bus/Core Speed Positions to GPIO Assignments
Table 3-3.
SW1 Bus/Core Speed Positions
to GPIO Assignments
Switch Position
Signal Name
GPIO Number
SW1-2
BF0
10
SW1-3
BF1
11
SW1-5
SPD6612
SPD = Bus frequency select BF = Bus/core fraction
3.2.3
I/O Port 78h
bit <0>
bit <1>
bit <2>
SECONDARY (L2) CACHE MEMORY
The system board comes with 256 kilobytes of SRAM implemented as the secondary (L2) cache
to the integrated L1 cache of the Pentium MMX microprocessor. This L2 cache uses two 32K x
32 synchronous pipelined burst SRAMs (with one 32K x 8 TAG RAM) arranged as a directmapped, write-back. The L2 cache provides a typical cycle time (in Host clocks) of 3-1-1-1 for
burst reads (cache hit) and writes (write back). The L2 controller allows the full system memory
range to be cached.
3-4 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
3.2.4
SYSTEM MEMORY
The system board contains two 168-pin DIMM sockets for system memory. This system is
designed for using SDRAM DIMMs. As shipped from the factory the standard configuration may
be 16 or 32 megabytes installed. The addition of 16-, or 32-, 64-, or 128-MB DIMMs allows the
expansion of system memory up to a maximum of 256 megabytes. Single or double-sided
DIMMs may be used. It is strongly recommended to use DIMMs with gold-plated contacts.
The system memory uses the following RAS line assignments:
RAS#0
RAS#1
RAS#2
RAS#3
DIMM 1, Bank A
DIMM 1, Bank B
DIMM 2, Bank A
DIMM 2, Bank B
This system does not use parity but does support ECC, and the memory is unbuffered. The
performance times of the SDRAM is listed as follows:
Table 3–4. SDRAM Performance Times
Table 3-4.
SDRAM Performance Times
Parameter
Burst Read Page Hit:
Read Row Miss
Read Page Miss
Bk-to-Bk Burst Reads (Pg Hit )
Write Page Hit
Write Row Miss
Write Page Miss
Posted Write
CAS Latency = 2 CLKs
6-1-18-1-1-1
10-1-1-1
6-1-1-1, 3-1-1-1
3
6
9
3-1-1-1
In addition to the supplied (and recommended) SDRAM, the system supports EDO and ECC
RAM, with error logging/alerting supported. The RAM type (as well as other information) is
detected during power-up by the system BIOS using the serial presence detect (SPD) method,
which reads the EEPROM on each DIMM to obtain identification data such as the type and
operating parameters. The supported format complies to the JEDEC specification for 128-byte
EEPROMs. This system also provides support for 256-byte EEPROMs to include additional
Compaq-added features such as the part number, serial number, and error logging. The SPD
format as supported in this system is shown in Table 3-5.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
3-5
Chapter 3 Processor/Memory Subsystem
Table 3–5. SPD Address Map (SDRAM DIMM)
Table 3-5.
SPD Address Map (SDRAM DIMM)
Byte
0
1
2
3
4
5
6, 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30, 31
32..61
NOTES:
Description
No. of Bytes Written Into EEPROM
Total Bytes (#) In EEPROM
Memory Type
No. of Row Addresses On DIMM
No. of Column Addresses On DIMM
No. of Module Banks On DIMM
Data Width of Module
Voltage Interface Standard of DIMM
Cycletime @ Max CAS Latency (CL)
Access From Clock
Config. Type (Parity, Nonparity, etc.)
Refresh Rate/Type
Width, Primary DRAM
Error Checking Data Width
Min. Clock Delay
Burst Lengths Supported
No. of Banks For Each Mem. Device
CAS Latencies Supported
CS# Latency
Write Latency
DIMM Attributes
Memory Device Attributes
Min. Clock Cycle Time at CL X-1
Max. Acc. Time From CLK at CL X-1
Min. Clock Cycle Time at CL X-2
Max. Acc. Time From CLK at CL X-2
Min. Row Precharge Time
Min. Row Active To Row Active Delay
Min. RAS to CAS Delay
Reserved
Superset Data For Future Use
Notes
[1]
[2]
[3]
[4]
[4]
[4] [5]
[6]
[4]
[4]
[4]
[4]
Byte
62
63
64-71
72
73-90
91, 92
93, 94
95-98
99-125
126, 127
128-135
136-150
151-152
153-165
166
167-189
190-221
222
223-253
254
255
Description
SPD Revision
Checksum Bytes 0-62
JEP-106E ID Code
DIMM OEM Location
OEM’s Part Number
OEM’s Rev. Code
Manufacture Date
OEM’s Assembly S/N
OEM Specific Data
Reserved
Sys. Integrator’s ID
Sys. Integrator’s P/N
Sys. Integrator’s D/C
Sys. Integrator’s S/N
Chksm Bytes 128-165
Top Level Sys. S/N
Avaiable for use
Chksm Bytes 167-221
Available for use
Chksm Bytes 223-253
Chksm Byes 0-128
Notes
[7]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[1] Programmed as 128 bytes by the DIMM’s OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be
re-sent as highest order CAS# address.
[4] Refer to memory manufacturer’s datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] Field format proposed to JEDEC. This system requires that the DIMM’s EEPROM have this
space available for reads/writes.
Access to the DIMM’s EEPROM is through an I2C-type bus interface using BIOS call INT 15,
AX-E827h (discussed in Chapter 8, “BIOS ROM”).
If the BIOS finds an installed module that is not supported then the memory controller is
programmed to indicate empty rows as appropriate.
3-6 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Figure 3-3 shows the system memory map.
FFFF FFFFh
FFFC 0000h
FFFB FFFFh
8100 0000h
80FF FFFFh
8000 0000h
7FFF FFFFh
Host,
PCI Area
1000 0000h
FFDF FFFFh
1000 0000h
0FFF FFFFh
0400 0000h
03FF FFFFh
0100 0000h
Host, PCI,
ISA Area
00FF FFFFh
0010 0000h
000F FFFFh
000F 0000h
000E FFFFh
000E 0000h
000D FFFFh
4 GB
High BIOS Area
(256 KB)
PCI Memory
(2130 MB)
ISA Memory-Mapped
Devices (16 MB)
PCI Memory
(1792 MB)
Op.TSEG (Cacheable)
(.1, .25, .5, 1 MB)
Op. Hi SMRAM
(384 KB)
Cacheable in L1
(192 MB)
64 MB
Extended Memory
(48 MB)
16 MB
Extended Memory
(15 MB)
Upper BIOS Area
(64 KB)
Lower BIOS Area
(64 KB)
000C 6800h
000C 6000h
000C 5FFFh
000C 0000h
000B FFFFh
000A 0000h
0009 FFFFh
960 KB
896 KB
Unused 96 KB
000C 8000h
DOS Compatibility
Area
1 MB
Graphics ROM
(6 KB)
Unused 2 KB
Graphics ROM
(24 KB)
Graphics/SMM Area
(128 KB)
800 KB
792 KB
768 KB
640 KB
Base Memory
(640 KB)
0000 0000h
NOTE: All locations in the 256 megabytes of system memory are cacheable in the L2 cache.
Figure 3–3. System Memory Map
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
3-7
Chapter 3 Processor/Memory Subsystem
3.2.5
SUBSYSTEM CONFIGURATION
The VT82C595 component provides the configuration function for the processor/memory
subsystem. Table 3-6 lists the configuration registers used for setting and checking such
parameters as cache (L2) control, system memory control, and PCI bus operation. These registers
reside in the PCI Configuration Space and accessed using the methods described in Chapter 4,
section 4.2.
Table 3–6. Host/PCI Bridge Configuration Registers (VT82C595)
Table 3-6.
Host/PCI Bridge Configuration Registers (VT82C595)
PCI Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
09-0Bh
0Dh
0Eh
0Fh
50h
51h
52h
53h
54, 55h
56, 57h
58h
59h
5A..5Fh
60h
61..63h
Register
Vender ID
Device ID
Command
Status
Revision ID
Class Code
Latency Timer
Header Type
BIST (read only)
Cache Control Reg. 1
Cache Control Reg. 2
Non-Cacheable Control
Misc. Control
Non-Cacheable Area 1
Non-Cacheable Area 2
DRAM Configuration
DRAM Configuration
DRAM ROW End Addr.
DRAM Type
Shadow RAM Control
Reset
Value
1106h
0595h
0007h
00h
00h
00h
00h
02h
00h
00h
00h
40h
05h
01h
00h
00h
PCI Config.
Addr.
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
--
Register
DRAM Timing
DRAM Control Reg. 1
DRAM Control Reg. 2
DRAM Width
UMA Control Reg. 1
UMA Control Reg. 2
Refresh Control
Misc. Cointrol
SDRAM Control
DRAM Control Drive Strength
ECC Control Reg.
ECC Status Reg.
PCI Buffer Control
CPU-to-PCI Flow Cntl. Reg. 1
CPU-to-PCI Flow Cntl. Reg. 2
PCI Master Control Reg.1
PCI Master Control Reg. 2
PCI Arbitration
Extension (PCI Arbitration)
--
NOTE:
Refer to VIA Technologies, Inc. documentation for detailed description of registers.
Assume unmarked locations/gaps as reserved.
3-8 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Reset
Value
ABh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
--
Technical Reference Guide
Chapter 4
SYSTEM SUPPORT
4. Chapter 4 SYSTEM SUPPORT
4.1
INTRODUCTION
This chapter covers subjects dealing with basic system architecture and covers the following
topics:
♦
♦
♦
♦
♦
♦
PCI bus overview (4.2)
page 4-2
ISA bus overview (4.3)
page 4-11
System clock distribution (4.4)
page 4-23
Real-time clock and configuration memory (4.5) page 4-24
I/O map and register accessing (4.6)
page 4-41
System management support (4.7)
page 4-44
This chapter covers functions provided by off-the-shelf chipsets and therefore describes only basic
aspects of these functions as well as information unique to the Compaq Deskpro 4000 Personal
Computers. For detailed information on specific components, refer to the applicable
manufacturer’s documentation.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-1
Chapter 4 System Support
4.2
PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus
implementation in this particular system. For detailed information regarding PCI bus
operation, refer to the PCI Local Bus Specification Revision 2.1.
This system implements a 32-bit Peripheral Component Interconnect (PCI) bus. The PCI bus
uses a shared address/data bus design. On the first clock cycle of a PCI bus transaction the bus
carries address information. On subsequent cycles, the bus carries data. PCI transactions occur
synchronously with the Host bus at a rate of up to 33 MHz, depending on the speed of the
microprocessor used. All I/O transactions involve the PCI bus. All ISA transactions involving the
microprocessor, cache, and memory also involve the PCI bus. Memory cycles will involve the
PCI if the access is initiated by a device or subsystem other than the microprocessor.
The PCI bus handles address/data transfers through the identification of devices and functions on
the bus (Figure 4-1). A device is defined as a component or slot that resides on the PCI bus. A
function is defined as the end source or target of the bus transaction. A device (component or
slot) may contain one or more functions (i.e., in this system the PCI/ISA Bridge function, EIDE
controller function, USB function, and ACPI function are contained within the South Bridge
component).
Host Bus
Graphics
Controller
Host/PCI
Bridge Function
PCI Connector
32-Bit PCI Bus 0
PCI/ISA Bridge
Function
EIDE Cntlr.
Function
USB
Function
ACPI Cntlr.
Function
ISA Bus
Figure 4–1. PCI Bus Devices and Functions
4-2
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
NIC
Function
Technical Reference Guide
4.2.1
PCI CONNECTOR
B94
B62
B1
A1
A62
A94
NOTE: See caution below.
Figure 4–2. 32-Bit PCI Bus Connector (32-Bit Type)
Table 4–1. 32-Bit PCI Bus Connector Pinout
Table 4-1.
PCI Bus Connector Pinout
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-NOTE:
B Signal
-12 VDC
TCK
GND
TDO
+5 VDC
+5 VDC
INTBINTDPRSNT1RSVD
PRSNT2GND
GND
RSVD
GND
CLK
GND
REQ+5 VDC
AD31
AD29
GND
AD27
AD25
+3.3 VDC
C/BE3AD23
GND
AD21
AD19
+3.3 VDC
--
A Signal
TRST+12 VDC
TMS
TDI
+5 VDC
INTAINTC+5 VDC
Reserved
+5 VDC
Reserved
GND
GND
Reserved
RST+5 VDC
GNTGND
Reserved
AD30
+3.3 VDC
AD28
AD26
GND
AD24
IDSEL
+3.3 VDC
AD22
AD20
GND
AD18
--
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
--
B Signal
AD17
C/BE2GND
IRDY+3.3 VDC
DEVSELGND
LOCKPERR+3.3 VDC
SERR+3.3 VDC
C/BE1AD14
GND
AD12
AD10
GND
Key
Key
AD08
AD07
+3.3 VDC
AD05
AD03
GND
AD01
+5 VDC
ACK64- [1]
+5 VDC
+5 VDC
--
A Signal
AD16
+3.3 VDC
FRAMEGND
TRDYGND
STOP+3.3 VDC
SDONE
SBOGND
PAR
AD15
+3.3 VDC
AD13
AD11
GND
AD09
Key
Key
C/BE0+3.3 VDC
AD06
AD04
GND
AD02
AD00
+5 VDC
REQ64- [1]
+5 VDC
+5 VDC
--
Pin
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
B Signal
Reserved
GND
C/BE6C/BE4GND
AD63
AD61
+5 VDC
AD59
AD57
GND
AD55
AD53
GND
AD51
AD49
+5 VDC
AD47
AD45
GND
AD43
AD41
GND
AD39
AD37
+5 VDC
AD35
AD33
GND
Reserved
Reserved
GND
A Signal
GND
C/BE7C/BE5+5 VDC
PAR64
AD62
GND
AD60
AD58
GND
AD56
AD54
+5 VDC
AD52
AD50
GND
AD48
AD46
GND
AD44
AD42
+5 VDC
AD40
AD38
GND
AD36
AD34
GND
AD32
Reserved
GND
Reserved
[1] The REQ64- and ACK64- signals are pulled high, allowing the use of 64-bit PCI cards
in 32-bit mode.
CAUTION: The maximum length for an expansion card (PCI or ISA) installed in this system is
7 inches. Longer cards may be damaged or cause damage to the system.
Compaq Deskpro 4000N and 4000S Personal Computers
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Chapter 4 System Support
4.2.2
PCI BUS MASTER ARBITRATION
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. Request (REQ), Grant (GNT), and FRAME signals are used by
PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter
(a function of the system controller component). If the bus is available, the arbiter asserts the
GNTn signal to the requesting device, which then asserts FRAME and conducts the address
phase of the transaction with a target. If the PCI device already owns the bus, a request is not
needed and the device can simply assert FRAME and conduct the transaction. Table 4-1 shows
the grant and request signals assignments for the devices on the PCI bus.
Table 4–2. PCI Bus Mastering Devices
Table 4-2.
PCI Bus Mastering Devices
REQ/GNT Line
REQ1/GNT1
REQ2/GNT2
REQ3/GNT3
Device
PCI Connector
Graphics Controller
Network I/F Controller
PCI bus control is granted according to a Least Recently Used (LRU) algorithm. During times
that the bus is not used or requested, bus control is given to the Host/PCI bridge. After a device
has given up control of the bus or has not executed a transaction for 16 PCI clock cycles
(PCICLKs) after gaining bus control, it loses access and is placed on the bottom of the priority
list.
The PCI/ISA bridge is given special consideration. If the PCI/ISA bridge gains control of the PCI
bus but does not execute a transaction after 16 PCICLKs, the PCI/ISA bridge retains ownership
of the PCI bus until the current ISA bus master relinquishes the ISA bus. The PCI/ISA bridge is
then placed on the bottom of the priority list.
PCI bus priority can be altered in two ways: by a master needing to perform a retry of a data
cycle, or by the master locking the bus. When a master is retried, it releases the bus and negates
its REQn- line for a minimum of two PCICLKs and then requests the bus again. If the master is
granted the bus before the condition that caused the retry is resolved, the master is retried again,
which may result in bus “thrashing.” Bus thrashing is minimized by masking the REQn- line of a
particular device that has had a transaction retried.
If a master locks the PCI bus, it retains top priority, allowing it to quickly finish a lock sequence.
The PCI/ISA bridge cannot become master until the locking device unlocks the bus.
Consequently, a master should not lock the bus for long periods of time or latency problems could
occur.
4-4
Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
4.2.3
PCI BUS TRANSACTIONS
The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for
handling both address and data transfers. A bus transaction consists of an address cycle and one
or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is
realized during burst modes in which a transaction with contiguous memory locations requires
that only one address cycle be conducted and subsequent data cycles are completed using autoincremented addressing. Four types of address cycles can take place on the PCI bus; I/O,
memory, configuration, and special. Address decoding is distributed (left up to each device on
the PCI bus).
4.2.3.1 I/O and Memory Cycles
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addressing
is handled by the appropriate PCI device. For memory addressing, PCI devices decode the
AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linearincrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with
addressing assumed to increment accordingly (four bytes at a time).
4.2.3.2 Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device
by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI
device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the configuration data.
PCI Configuration Address Register
I/O Port 0CF8h, R/W, (32-bit access only)
Bit
Function
31
Configuration Enable
0 = Disabled
1 = Enable
30..24
Reserved - read/write 0s
23..16
Bus Number. Selects PCI bus
15..11
PCI Device Number. Selects PCI
device for access
10..8
Function Number. Selects function of
selected PCI device.
7..2
Register Index. Specifies config. reg.
1,0
Configuration Cycle Type ID.
00 = Type 0
01 = Type 1
PCI Configuration Data Register
I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
Bit
Function
31..0
Configuration Data.
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Chapter 4 System Support
Figure 4-3 shows how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI
bus. The Device Number (bits <15..11> determines which one of the AD31..11 lines is to be
asserted high for the IDSEL signal, which acts as a “chip select” function for the PCI device to be
configured.
31 30
24 23
Reserved
Register 0CF8h
16 15
11 10
8 7
2 1 0
Bus
Device
Function
Register
0 0
Number
Number
Number
Index
Results in:
31
AD31..0
w/Type 0
Config. Cycle
IDSEL (only one signal line asserted)
11 10
8 7
2 1 0
Function
Register
Number
Index
Figure 4–3. Type 0 Configuration Cycle
Type 0 configuration cycles are used for configuring devices on PCI bus # 0. Type 1
configuration cycles (reg. 0CF8h bits <1,0> = 01b) are passed on to PCI bus # 1 (if present).
Table 4-3 shows the standard configuration of device numbers and IDSEL connections for
components and slots residing on a PCI bus.
Table 4–3. PCI Device Configuration Access
Table 4-3.
PCI Device Configuration Access
PCI Device
North Bridge (82C595)
PCI Connector
South Bridge (82C586)
Graphics Controller
Network Interface Controller
Device No.
(CF8h <15..11>)
0
2
7
15
16
IDSEL
Wired to:
AD11
AD13
AD31
AD26
AD27
The function number (CF8h, bits <10..8>) is used to select a particular function within a
multifunction device as shown in Table 4-4.
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Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
Table 4–4. PCI Function Configuration Acces
Table 4-4.
PCI Function Configuration Access
PCI Function
Host/PCI Bridge
PCI/ISA Bridge
IDE Interface
USB Interface
ACPI Cntlr.
Graphics Controller
Network Interface Controller
Device No.
0
7
7
7
7
15
16
Function No.
0
0
1
2
3
0
0
The register index (CF8h, bits <7..2>)identifies the 32-bit location within the configuration
space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of
configuration data (see Figure 4-4), of which the first 64 bytes comprise the configuration space
header.
31
24 23
16 15
8
7
0
Register
Index
FCh
Device-Specific Area
Min_Lat
Min_GNT
Interrupt Pin
Interrupt Line
40h
3Ch
Base Address Registers and Exp. ROM Address
Configuration
Space
Header
Header Type
Class Code
BIST
Latency Timer
Cache Line Size
Revision ID
Command
Vender ID
Status
Device ID
Data required by PCI protocol
0Ch
08h
04h
00h
Not required
Figure 4–4. PCI Configuration Space Map
Each PCI device is identified with a vender ID (assigned to the vender by the PCI Special Interest
Group) and a device ID (assigned by the vender). The device and vender IDs for the devices used
in these systems are listed in Table 4-5.
Compaq Deskpro 4000N and 4000S Personal Computers
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Chapter 4 System Support
Table 4–5. PCI Device Identification
Table 4-5.
PCI Device Identification
PCI Device
VT82C595 (North Bridge)
VT82C586 (South Bridge):
PCI/ISA Bridge (Function 0)
EIDE Controller (Function 1)
USB I/F (Function 2)
ACPI Cntlr (Function 3)
Network Interface Controller
Graphics Controller
Vender ID
1106h
Device ID
0595h
1106h
1106h
1106h
1106h
0E11h
5333h
0586h
0571h
3038h
3040h
B011h
8901h
4.2.3.3 Special Cycles
There are two types of special cycles that may occur on the PCI bus. The first type is initiated by
the host and is used to perform the following functions: Shutdown, Flush, Halt, Write Back,
Flush Acknowledge, Branch Trace Message, and Stop/Grant. These cycles start like all other PCI
cycles and terminate with a master abort.
The second type of special cycle is initiated by writing to 0CF8h, Bus # = all 0s, Device = all 1s,
Function # all 1s, and Register = all 0s) and 0CFCh to generate a Type 0 configuration cycle.
This type 0 cycle, however, does not assert any of the IDSEL lines and therefore results in a
master abort with FFFFh returned to the microprocessor.
4.2.4
OPTION ROM MAPPING
During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility
area (refer to the system memory map shown in chapter 3).
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Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
4.2.5
PCI INTERRUPT MAPPING
The PCI bus provides for four interrupt signals; INTA-, INTB-, INTC-, and INTD-. These
signals may be generated by on-board PCI devices or by devices installed in the PCI slots. In
order to minimize latency, INTA-..INTD- signal routing from the PCI slot to the system board is
distributed by the riser card (backplane) as shown below:
System Board
INTAINTBINTCINTD-
PCI Slot
INTDINTA- [1]
INTBINTC- [2]
NOTES:
[1] Shared with network interface controller
[2] Shared with graphic controller
Interrupts generated by PCI devices can be configured to share the standard AT (IRQn) interrupt
lines. Two devices that share a single PCI interrupt must also share the corresponding AT
interrupt. Example: If a PCI card is installed in slot 5 and wants to use INTA- then it must share
INTA- as well as the corresponding AT interrupt with the on-board network interface controller.
Three PCI configuration registers of the 82C586 are used to route the INTA-..INTD- signals to
the IRQn signal lines (refer to section 4.3.4.1 for information on IRQn routing). The power up
(default) configuration has PCI interrupt redirection disabled.
PCI Configuration Register 55h, IRQ Routing Reg. 1
Default Value = 00h
Bit
Function
7..4
INTD- Routing:
0000 = Reserved
1000 = Reserved
0001 = IRQ1
1001 = IRQ9
0010 = Reserved
1010 = IRQ10
0011 = IRQ3
1011 = IRQ11
0100 = IRQ4
1100 = IRQ12
0101 = IRQ5
1101 = Reserved
0110 = IRQ6
1110 = IRQ14
0111 = IRQ7
1111 = IRQ15
3..0
MIRQ0- Routing (Same as PIRQD-)
PCI Configuration Register 56h, IRQ Routing Reg. 2
Default Value = 00h
Bit
Function
7..4
INTA- Routing: (Same as PIRQD-)
3..0
INTB- Routing (Same as PIRQD-)
PCI Configuration Register 57h, IRQ Routing Reg. 3
Default Value = 00h
Bit
Function
7..4
INTC- Routing: (Same as PIRQD-)
3..0
MIRQ1 Routing (Same as PIRQD-)
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Chapter 4 System Support
4.2.6
PCI CONFIGURATION
PCI bus operations, especially those that involve ISA bus interaction, require the configuration of
certain parameters such as PCI IRQ routing, top of memory accessable by ISA, SMI generation,
and clock throttling characteristics. These parameters are handled by the PCI/ISA bridge
function (PCI function #0) of the South Bridge component and configured through the PCI
configuration space registers listed in Table 4-6. Configuration is provided by BIOS at power-up
but re-configurable by software .
Table 4–6. PCI/ISA Bridge Configuration Registers for the VT82C586 (P55C-Based Systems)
Table 4-6.
PCI/ISA Bridge Configuration Registers
(VT82C586 Function 0)
PCI Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
09-0Bh
0Eh
40h
41h
42h
43h
44
45h
46, 47h
48h
4Ah
Register
Vender ID
Device ID
Command
Status
Revision ID
Class Code
Header Type
ISA Bus Control
Refresh & Port 92 Control
ISA Clock Control
ROM Decoding Cntl.
Keyboard Controller Control
Type F DMA Control
Misc. Control
Misc. Control
IDE Interrupt Routing
Reset
Value
1106h
0586h
00h
00h
00h
00h
00h
00h
00h
01h
04h
PCI Config.
Addr.
4C..4Eh
4Fh
50h
54h
55..57h
80h
82h
84, 85h
86, 87h
88..8Bh
8Ch
8Dh
8Eh
90..93h
94h
95, 96h
NOTE: Assume unmarked locations/gaps as reserved.
4-10 Compaq Deskpro 4000N and 4000S Personal Computers
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Register
ISA DMA/Master Mem. Acc.
ISA DMA/Master Mem. Acc.
PnP DRQ Routing
PCI Interrupt Polarity
PCI Interrupt Routing
Primary Activity Detect En.
Primary Activity Detect Sts.
Reserved
Reserved
Timer Control Registers
Conserve Mode/Sec. Event
Miscellaneous Control
STPCLK- Duty Cycle
ISA INT. As Primary Event
Ext. SMI Pin Status
Power-Up Strap Options
Reset
Value
00h
03h
24h
00h
00h
00h
00h
00h
00h
00h
00h
(RO)
(RO)
Technical Reference Guide
4.3
ISA BUS OVERVIEW
NOTE: This section describes the ISA bus in general and highlights bus
implementation in this particular system. For detailed information regarding ISA bus
operation, refer to the Compaq Extended Industry Standard Architecture (EISA)
Technical Reference Guide.
The industry standard architecture (ISA) bus provides an 8-/16-bit path for standard I/O
peripherals as well as for an optional device that can be installed in the ISA expansion slot (if
present). Figure 4-5 shows the key functions and devices that reside on the ISA bus.
PCI Bus
PCI/ISA
Bridge Function
ISA Connector [1]
8-/16-Bit ISA Bus
PC 87307 I/O Controller
Keyboard/
Mouse I/F
Diskette
I/F
Serial
I/F (2)
Parallel
I/F
IrDA
I/F
NOTE:
[1] Deskpro 4000S only
Figure 4–5. ISA Bus Block Diagram
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Chapter 4 System Support
4.3.1
ISA CONNECTOR
16-Bit ISA Connection
8-Bit ISA Connection
D1
B1
C1
A1
NOTE: See caution below.
Figure 4–6. ISA Expansion Connector
Table 4–7. ISA Expansion Connector Pinout
Table 4-7.
ISA Expansion Connector Pinout
16-Bit ISA Interface
Pin
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
8-Bit ISA Interface
Signal
Pin
Signal
GND
A01
I/O CHKRESDRV
A02
SD7
+5 VDC
A03
SD6
IRQ9
A04
SD5
-5 VDC
A05
SD4
DRQ2
A06
SD3
-12 VDC
A07
SD2
NOWSA08
SD1
+12 VDC
A09
SD0
GND
A10
BUSRDY
SMWTCA11
DMA
SMRDCA12
SA19
IOWCA13
SA18
IORCA14
SA17
DAK3A15
SA16
DRQ3
A16
SA15
DAK1
A17
SA14
DRQ1
A18
SA13
REFRESHA19
SA12
BCLK
A20
SA11
IRQ7
A21
SA10
IRQ6
A22
SA9
IRQ5
A23
SA8
IRQ4
A24
SA7
IRQ3
A25
SA6
DAK2A26
SA5
T-C
A27
SA4
BALE
A28
SA3
+5 VDC
A29
SA2
OSC
A30
SA1
GND
A31
SA0
Pin
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
Signal
M16I/O16IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DAK0DRQ0
DAK5DRQ5
DAK6DRQ6
DAK7DRQ7
+5 VDC
GRABGND
Pin
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
Signal
SBHELA23
LA22
LA21
LA20
LA19
LA18
LA17
MRDCMWTCSD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CAUTION: The maximum length for an
expansion card (PCI or ISA) installed in
this system is 7 inches. Longer cards may
be damaged or cause damage to the
system.
4-12 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
4.3.2
ISA BUS TRANSACTIONS
The ISA bus supports 8- and 16-bit transfers at an 8-MHz rate. Devices limited to 8-bit transfers
use the lower byte portion (data lines 7..0) while 16-bit transfers use the full bandwidth (data
lines 15..0). Addressing is handled by two classifications of address signals: latched and
latchable. Latched address signals ( SA19..0) select the specific byte within the 1-MB section of
memory defined by address lines LA23..17. Latchable address lines (LA23..17) provide a longer
setup time for pre-chip selection or for pre-address decoding for high-speed memory and allow
access to up to 16-MB of physical memory on the ISA bus. The SA19..17 signals have the same
values as the LA19..17 signals for all memory cycles. The I/O cycles use only the SA15..0
signals.
The key control signals are described as follows:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
MRDC- (Memory Read Cycle): MRDC- is active on all ISA memory reads accessing
memory from 000000h to FFFFFFh.
SMEMR- (System Memory Read): SMEMR- is asserted by the PCI/ISA bridge to request an
ISA memory device to drive data onto the data lines for accesses below one megabyte.
SMEMR- is a delayed version of MRDC-.
MWTC- (Memory Write Cycle): MWTC- is active on all ISA memory write cycles accessing
memory from 000000h to FFFFFFh.
SMEMW- (System Memory Write): SMEMW- is asserted by the PCI/ISA bridge to request
an ISA memory device to accept data from the data lines for access below one megabyte.
SMEMW- is a delayed version of MWTC-.
IORC- (Input/Output Read Cycle): IORC- commands an ISA I/O device to drive data onto
the data lines.
IOWC- (Input/Output Write Cycle): IOWC- commands an ISA I/O device to accept data
from the data lines.
SBHE- (System Byte High Enable): SBHE- indicates that a byte is being transferred on the
upper half (D15..8) of the data lines.
SA0- (System Address Bit <0>): This bit is the complement of SBHE- and indicates that a
byte is being transferred on the lower half (D7..0) of the data lines.
M16- (16-bit Memory Cycle): M16- is asserted by 16-bit ISA devices to indicate 16-bit
memory cycle capability.
IO16- (16-bit I/O Cycle): IO16- is asserted by 16-bit ISA devices to indicate 16-bit I/O cycle
transfer capability.
If the address on the SA lines is above one megabyte, SMRDC- and SMWTC- will not be active.
The MRDC- and MWTC- signals are active for memory accesses up to 16 megabytes and can be
used by any device that uses the full 16-bit ISA bus. To request a 16-bit transfer, a device asserts
either the M16- (memory) or IO16- (I/O) signal when the device is addressed.
When another device (such as a DMA device or another bus master) takes control of the ISA, the
Bus Address Latch Enable (BALE) signal is held active for the duration of the operation. As a
result , signals LA23..17 are always enabled and must be held stable for the duration of each bus
cycle.
When the address changes, devices on the bus may decode the latchable address (LA23..17) lines
and then latch them. This arrangement allows devices to decode chip selects and M16- before the
next cycle actually begins.
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Chapter 4 System Support
The following guidelines apply to optional ISA devices installed in the system:
♦
♦
♦
♦
On bus lines that can be driven by a controller board, the driver should be able to sink a
minimum of 20 ma at 0.5 VDC and source 2 ma at 3.75 VDC.
On bus lines that are driven in the low direction only (open collector), the driver should be
able to sink 20 ma at 0.5 VDC.
The load on any logic line from a single bus slot should not exceed 2.0 ma in the low state
(at 0.5 VDC) or 0.1 ma in the high state (at 3.75 VDC).
The logic-high voltage at the bus ranges from 3.75 VDC to 5.5 VDC. The logic low voltage
ranges from 0 VDC to 0.8 VDC.
4-14 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
4.3.3
DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a method by which an ISA device accesses system memory
without involving the microprocessor. DMA is normally used to transfer blocks of data to or from
an ISA I/O device. DMA reduces the amount of CPU interactions with memory, freeing the CPU
for other processing tasks.
NOTE: This section describes DMA in general. For detailed information regarding
DMA operation, refer to the Compaq Extended Industry Standard Architecture (EISA)
Technical Reference Guide. Note, however, that EISA enhancements as described in the
referenced document are not supported in this (ISA only) system.
The South Bridge component includes the equivalent of two 8237 DMA controllers cascaded
together to provide eight DMA channels. Table 4-8 lists the default configuration of the DMA
channels.
Table 4–8. Default DMA Channel Assignments
Table 4-8.
Default DMA Channel Assignments
DMA Channel
Controller 1 (byte transfers)
0
1
2
3
Controller 2 (word transfers)
4
5
6
7
Device ID
Spare & ISA conn. pins D8, D9
Audio subsystem & ISA conn. pins B17, B18
Diskette drive & ISA conn. pins B6, B26
ECP LPT1 & ISA conn. pins B15, B16
Cascade for controller 1
Spare & ISA conn. pins D10, D11
Spare & ISA conn. pins D12, D13
Spare & ISA conn. pins. D14, D15
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note
that channel 4 is not available for use other than its cascading function for controller 1. The
DMA controller 2 can transfer words only on an even address boundary. The DMA controller
and page register define a 24-bit address that allows data transfers within the address space of
the CPU. The DMA controllers operate at 8 MHz.
The DMA logic is accessed through two types of I/O mapped registers; page registers and
controller registers. The mapping is the same regardless of the support chipset used.
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Chapter 4 System Support
4.3.3.1 Page Registers
The DMA page register contains the eight most significant bits of the 24-bit address and works
in conjunction with the DMA controllers to define the complete (24-bit)address for the DMA
channels. Table 4-9 lists the page register port addresses.
Table 4–9. DMA Page Register Addresses
Table 4-9.
DMA Page Register Addresses
DMA Channel
Page Register I/O Port
Controller 1 (byte transfers)
087h
Ch 0
083h
Ch 1
081h
Ch 2
082h
Ch 3
Controller 2 (word transfers)
n/a
Ch 4
08Bh
Ch 5
089h
Ch 6
08Ah
Ch 7
Refresh
08Fh [see note]
NOTE:
The DMA memory page register for the refresh channel must be
programmed with 00h for proper operation.
The memory address is derived as follows:
24-Bit Address - Controller 1 (Byte Transfers)
8-Bit Page Register
8-Bit DMA Controller
A23..A16
A15..A00
24-Bit Address - Controller 2 (Word Transfers)
8-Bit Page Register
16-Bit DMA Controller
A23..A17
A16..A01, (A00 = 0)
Note that address line A16 from the DMA memory page register is disabled when DMA
controller 2 is selected. Address line A00 is not connected to DMA controller 2 and is always 0
when word-length transfers are selected.
By not connecting A00, the following applies:
♦
♦
The size of the the block of data that can be moved or addressed is measured in 16-bits
(words) rather than 8-bits (bytes).
The words must always be addressed on an even boundary.
DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can
move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only
possible between 16-bit memory and 16-bit peripherals.
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Technical Reference Guide
The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses
in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit
memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08.
Address lines LA23..17, SA18,19 are driven low.
The remaining address lines are in an undefined state during the refresh cycle. The refresh
operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The
refresh rate is 128 refresh cycles in 2.038 ms.
4.3.3.2 DMA Controller Registers
Table 4-10 lists the DMA Controller Registers and their I/O port addresses. Note that there is a
set of registers for each DMA controller.
Table 4–10. DMA Controller Registers
Table 4-10.
DMA Controller Registers
Register
Controller 1
Controller 2
R/W
Status
008h
0D0h
R
Command
008h
0D0h
W
Mode
00Bh
0D6h
W
Write Single Mask Bit
00Ah
0D4h
W
Write All Mask Bits
00Fh
0DEh
W
Software DRQx Request
009h
0D2h
W
Base and Current Address - Ch 0
000h
0C0h
W
Current Address - Ch 0
000h
0C0h
R
Base and Current Word Count - Ch 0
001h
0C2h
W
Current Word Count - Ch 0
001h
0C2h
R
Base and Current Address - Ch 1
002h
0C4h
W
Current Address - Ch 1
002h
0C4h
R
Base and Current Word Count - Ch 1
003h
0C6h
W
Current Word Count - Ch 1
003h
0C6h
R
Base and Current Address - Ch 2
004h
0C8h
W
Current Address - Ch 2
004h
0C8h
R
Base and Current Word Count - Ch 2
005h
0CAh
W
Current Word Count - Ch 2
005h
0CAh
R
Base and Current Address - Ch 3
006h
0CCh
W
Current Address - Ch 3
006h
0CCh
R
Base and Current Word Count - Ch 3
007h
0CEh
W
Current Word Count - Ch 3
007h
0CEh
R
Temporary (Command)
00Dh
0DAh
R
Reset Pointer Flip-Flop (Command)
00Ch
0D8h
W
Master Reset (Command)
00Dh
0DAh
W
Reset Mask Register (Command)
00Eh
0DCh
W
NOTE:
For a detailed description of the DMA registers, refer to the Compaq EISA Technical Reference Guide.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-17
Chapter 4 System Support
4.3.4
INTERRUPTS
The microprocessor uses two types of interrupts; maskable and nonmaskable. A maskable
interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI
instructions. A nonmaskable interrupt cannot be masked off within the microprocessor but may
be inhibited by hardware or software means external to the microprocessor.
4.3.4.1 Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-D
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the
interrupt (INTR) input to the microprocessor. The microprocessor halts execution to determine
the source of the interrupt and then services the peripheral as appropriate.
ISA Peripherals
& SM Functions
IRQ1,3..7,
9..12,
14,15
IRQ1,3..7
IRQ9..12,
14,15
PIRQA-..DPCI Peripherals
South Bridge Component
Interrupt
Cntlr. 2
IRQ2
Interrupt
Cntlr. 1
INTR
Microprocessor
PCI IRQ
Routing
Figure 4–7. Maskable Interrupt Processing, Block Diagram
The South Bridge component, which includes the equivalent of two 8259 interrupt controllers
cascaded together, handles the standard AT-type (ISA) interrupt signals (IRQn). The South
Bridge also receives the PCI interrupt signals (PIRQA-..PIRQD-) from PCI devices. The PCI
interrupts can be configured by PCI Configuration Registers 55h..57h to share the standard ISA
interrupts (IRQn). The power-up default configuration has the PIRQn disabled. Table 4-11 lists
the standard source configuration for maskable interrupts and their priorities. If more than one
interrupt is pending, the highest priority (lowest number) is processed first.
4-18 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
Table 4–11. Maskable Interrupt Priorities and Assignments
Table 4-11.
Maskable Interrupt Priorities and Assignments
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-NOTE:
Signal Label
IRQ0
IRQ1
IRQ8IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ2
Source (Typical)
Interval timer 1, counter 0
Keyboard
Real-time clock
Spare and ISA connector pin B04
Spare and ISA connector pin D03
Spare and ISA connector pin D04
Mouse and ISA connector pin D05
Coprocessor (math)
IDE primary I/F and ISA connector pin D07
IDE secondary I/F and ISA connector pin D06
Serial port (COM2) and ISA connector pin B25
Serial port (COM1) and ISA connector pin B24
Audio subsystem and ISA connector pin B23
Diskette drive controller and ISA connector pin B22
Parallel port (LPT1)
NOT AVAILABLE (Cascade from interrupt controller 2)
Notes
[3] Alternate available interrupts: IRQ5, 9,10,11,14, or 15
Interrupts generated by PCI devices can be configured to share the standard AT (IRQn) interrupt
lines. Refer to section 4.2.5 “PCI Interrupt Mapping” for information on PCI interrupts.
Maskable Interrupt processing is controlled and monitored through standard AT-type I/Omapped registers. These registers are listed in Table 4-12.
Table 4–12. Maskable Interrupt Control Registers
Table 4-12.
Maskable Interrupt Control Registers
I/O Port
020h
021h
0A0h
0A1h
Register
Base Address, Int. Cntlr. 1
Initialization Command Word 2-4, Int. Cntlr. 1
Base Address, Int. Cntlr. 2
Initialization Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-19
Chapter 4 System Support
4.3.4.2 Non-Maskable Interrupts
Non-maskble interrupts cannot be masked (inhibited) within the microprocessor itself but may be
maskable by software using logic external to the microprocessor. There are two nonmaskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
♦
♦
♦
Parity errors detected on the ISA bus (activating IOCHK-).
Parity errors detected on a PCI bus (activating SERR- or PERR-).
Microprocessor internal error (activating IERRA or IERRB)
The IOCHK-, SERR-, and PERR- signals are routed through the south bridge component, which
in turn activates the NMI to the microprocessor.
The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
NMI Status Register 61h
Bit
7
6
5
4
3
2
1
0
Function
NMI Status:
0 = No NMI from system board parity error.
1 = NMI requested, read only
IOCHK- NMI:
0 = No NMI from IOCHK1 = IOCHK- is active (low), NMI requested, read only
Interval Timer 1, Counter 2 (Speaker) Status
Refresh Indicator (toggles with every refresh)
IOCHK- NMI Enable/Disable:
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and cleared (R/W)
System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
1 = Parity error NMI disabled and cleared (R/W)
Speaker Data (R/W)
Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
Functions not related to NMI activity.
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2>
or <3> respectively.
The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to
this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h
affect RTC operation and should be considered when changing NMI- generation status.
4-20 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with
the APM BIOS to service the SMI- according to the cause of the timeout.
Although the SMI- is primarily used for power managment the interrupt is also employed for the
QuickLock/QuickBlank functions as well.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-21
Chapter 4 System Support
4.3.5
INTERVAL TIMER
The interval timer generates pulses at software (programmable) intervals. A 8254-compatible
timer is integrated into the South Bridge chip. The timer function provides three counters, the
functions of which are listed in Table 4-13.
Table 4–13. Interval Timer Functions
Table 4-13.
Interval Timer Functions
Counter
0
1
2
Function
System Clock
Refresh
Speaker Tone
Gate
Always on
Always on
Port 61, bit<0>
Clock In
1.193 MHz
1.193 MHz
1.193 MHz
Clock Out
IRQ0
Refresh Req.
Speaker Input
The interval timer is controlled through the I/O mapped registers listed in Table 4-14.
Table 4–14. Interval Timer Control Registers
Table 4-14.
Interval Timer Control Registers
I/O Port
040h
041h
042h
043h
Register
Read or write value, counter 0
Read or write value, counter 1
Read or write value, counter 2
Control Word
Interval timer operation follows standard AT-type protocol. For a detailed description of timer
registers and operation, refer to the Compaq Extended Industry Standard Architecture Expansion
Bus Technical Reference Guide.
4.3.6
ISA CONFIGURATION
The working relationship between the PCI and ISA buses requires that certain parameters be
configured. The PC/ISA bridge function of the South Bridge component includes configuration
registers to set parameters such as PCI IRQ routing and top-of-memory available to ISA/DMA
devices. These parameters are programmed by BIOS during power-up, using registers listed
previously in Table 4-6.
4-22 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
4.4
SYSTEM CLOCK DISTRIBUTION
The system uses an ICS9147-08 or compatible part for generation of most clock signals. Tables
4-15 lists the clock signals and to which components they are distributed.
Table 4–15. Clock Generation and Distribution (Pentium-Based System)
Table 4-15.
Clock Generation and Distribution
Signal
CPUCLK
CACHE_CLKn
DIMMn_CLKn
PCICLK
LRU_CLK
TLAN_CLK
PCI Bridge Clock
SIO/USB CLK
PHYCLK
TLAN
Crystal CLK
CLK_14
BCLK
NOTES:
Frequency
60/66 MHz [1]
CPUCLK
CPUCLK
CPUCLK/2
CPUCLK/2
CPUCLK/2
CPUCLK/2
48 MHz
25 MHz
20 MHz
14.318 MHz
14 MHz
Source
ICS9147
“
“
“
“
“
“
“
Crystal
“
Crystal
ICS9147 [2]
PCICLK/4 [3]
VT82C586
Destination
CPU, VT82C595
L2 SRAMs
DIMMs
PCI slots
Compaq ASIC
TLAN ASIC
VT82C595, VT82C586
87307, VT82C586
LXT970
TLAN ASIC
ICS9147
ISA bus, VT82C586,
ESS1868
ISA bus
[1] Depending on speed configuration (refer to Chapter 3, “Processor/Memory Subsystem”).
[2] Routed through buffer before destination.
[3] 8.33 MHz if PCICLK = 33 MHz, 7.5 MHz if PCICLK = 30 MHz
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-23
Chapter 4 System Support
4.5
REAL-TIME CLOCK AND CONFIGURATION MEMORY
The Real-time clock (RTC) and configuration memory functions are provided by the PC87307
I/O controller. The RTC uses the first 14 of 256 bytes of configuration memory and is
MC146818-compatible. As shown in the following figure, the 87307 controller provides 256
bytes of configuration memory, divided into two 128-byte banks. The RTC/configuration memory
can be accessed using conventional OUT and IN assembly language instructions using I/O ports
70h/71h, although the suggested method is to use the INT15 AX=E823h BIOS call.
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
Register D
Register C
Register B
Register A
Year
Month
Date of Month
Day of Week
Hours (Alarm)
Hours (Timer)
Minutes (Alarm)
Minutes (Timer)
Seconds (Alarm)
Seconds (Timer)
87307
FFh
Upper Config.
Memory Area
(128 bytes)
80h
7Fh
Lower Config.
Memory Area
(114 bytes)
RTC Area
(14 bytes)
0Eh
0Dh
00h
CMOS
Figure 4–8. Configuration Memory Map
NOTE: Non-volatile (NVRAM) storage of PCI, ESCD, and Environmental Variable (EV) data
is provided by portions of the 256-KB system BIOS ROM component.
A 3-VDC battery is used for maintaining the RTC and configuration memory while the system is
powered down. This battery is soldered on the system board and is designed to last from 5-7
years. Once expired, the soldered battery is by-passed by connecting a replacement battery
(Compaq p/n 160274-001 or equivalent 4.5 VDC @ 660 ma alkaline battery) to header P14 pins
9-12. On-board logic regulates the external battery voltage to 3 VDC.
The configuration memory (including the password) can be cleared by moving the jumper from
P14 pins 1 and 2 to pins 2 and 3 for at least one minute while unit power ids off. The password
can be disabled by switching DIP SW1-1 on.
4-24 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
4.5.1
CONFIGURATION MEMORY BYTE DEFINITIONS
Table 4-16 lists the mapping of the configuration memory.
Table 4–16. Configuration Memory (CMOS) Map
Table 4-16.
Configuration Memory (CMOS) Map
Location
Function
00-0Dh
Real-rime clock
0Eh
Diagnostic status
0Fh
System reset code
10h
Diskette drive type
11h
Reserved
12h
Hard drive type
13h
Security functions
14h
Equipment installed
15h
Base memory size, low byte/KB
16h
Base memory size, high byte/KB
17h
Extended memory, low byte/KB
18h
Extended memory, high byte/KB
19h
Hard drive 1, primary controller
1Ah
Hard drive 2, primary controller
1Bh
Hard drive 1, secondary controller
1Ch
Hard drive 2, secondary controller
1Dh
Enhanced hard drive support
1Eh
Reserved
1Fh
Power management functions
24h
System board ID
25h
System architecture data
26h
Auxiliary peripheral configuration
27h
Speed control external drive
28h
Expanded/base mem. size, IRQ12
29h
Miscellaneous configuration
2Ah
Hard drive timeout
2Bh
System inactivity timeout
2Ch
Monitor timeout, Num Lock Cntrl
2Dh
Additional flags
2Eh-2Fh
Checksum of locations 10h-2Dh
30h-31h
Total extended memory tested
32h
Century
33h
Miscellaneous flags set by BIOS
34h
International language
35h
APM status flags
36h
ECC POST test single bit
37h-3Fh
Power-on password
40h
Miscellaneous Disk Bits
NOTE: Assume unmarked gaps are reserved.
Location
41h-44h
45h
46h
47h
48h-4Bh
4Ch-4Fh
51h
52h
53h
54h
55h
56h
57h-76H
77h-7Fh
80h
81h-82h
83h
84h
85h
86h
87h
8Dh-8Fh
90h-91h
92h
93h
94h
97h
9Bh
9Ch
9Dh
9Eh
9Fh-AFh
B0h-C3h
C7h
C8h
C9h
DEh-DFh
E0h-FFh
Function
Hoof Removal Time Stamp
Keyboard snoop byte
Diskette drive status
Last IPL device
IPL priority
BVC priority
ECC DIMM status
Board revision (from boot block)
SWSMI command
SWSMI data
APM command
Erase-Ease keyboard byte
Saved CMOS location 10h-2Fh
Administrator password
ECMOS diagnostic byte
Total super ext. memory tested good
Microprocessor chip ID
Microprocessor chip revision
Hood removal status byte
Fast boot date
Fast boot status byte
POST error logging
Total super extended memory configured
Miscellaneous configuration byte
Miscellaneous PCI features
ROM flash/power button status
Asset/test prompt byte
Ultra-33 DMA enable byte
Mode-2 Configuration
ESS audio configuration
ECP DMA configuration
Serial number
Custom drive types 65, 66, 68, 15
Serial port 1 address
Serial port 2 address
COM1/COM2 port configuration
Checksum of locations 90h to DDh
Client Management error log
Default values (where applicable) are given for a standard system as shipped from the factory.
The contents of configuration memory can be cleared by the following jumper positioning:
RTC using internal battery:
Move jumper on header E50 from pins 1 and 2 to pins 2 and 3.
RTC using external battery:
Move jumper on header E50 from pins 2 and 3 to pins 1 and 2.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-25
Chapter 4 System Support
RTC Control Register A, Byte 0Ah
Bit
7
6..4
3..0
Function
Update in Progress. Read only.
0 = Time update will not occur before 2444 us
1 = Time update will occur within 2444 us
Divider Chain Control. R/W.
00x = Oscillator disabled.
010 = Normal operation (time base frequency = 32.768 KHz).
11x = Divider chain reset.
Periodic Interrupt Control. R/W. Specifies the periodic interrupt interval.
0000 = none
1000 = 3.90625 ms
0001 = 3.90625 ms
1001 = 7.8125 ms
0010 = 7.8125 ms
1010 = 15. 625 ms
0011 = 122.070 us
1011 = 31.25 ms
0100 = 244.141 us
1100 = 62.50 ms
0101 = 488.281 us
1101 = 125 ms
0110 = 976.562 us
1110 = 250 ms
0111 = 1.953125 ms
1111 = 500 ms
RTC Control Register B, Byte 0Bh
Bit
7
6
5
4
3
2
1
0
Function
Time Update Enable/disable
0 = Normal operation, 1 = Disable time updating for time set
Periodic Interrupt Enable/Disable.
0 = Disable,
1 = Enable interval specified by Register A
Alarm Interrupt Enable/disable
0 = Disabled, 1 = Enabled
End-of-Update Interrupt Enable/Disable
0 = Disabled, 1 = Enabled
Reserved (read 0)
Time/Date Format Select
0 = BCD format, 1 = Binary format
Time Mode
0 = 12-lhour mode, 1 = 24-hour mode
Automatic Daylight Savings Time Enable/Disable
0 = Disable
st
1 = Enable (Advance 1 hour on 1 Sunday in April, retreat 1 hour on last Sunday in October).
RTC Status Register C, Byte 0Ch
Bit
7
6
5
4
3..0
Function
If set, interrupt output signal active (read only)
If set, indicates periodic interrupt flag
If set, indicates alarm interrupt
If set, indicates end-of-update interrupt
Reserved
RTC Status Register D, Byte 0Dh
Bit
7
6..0
Function
RTC Power Status
0 = RTC has lost power
1 = RTC has not lost power
Reserved
4-26 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
Configuration Byte 0Eh, Diagnostic Status
Default Value = 00h
This byte contains diagnostic status data.
Configuration Byte 0Fh, System Reset Code
Default Value = 00h
This byte contains the system reset code.
Configuration Byte 10h, Diskette Drive Type
Bit
Function
7..4
Primary (Drive A) Diskette Drive Type
3..0
Secondary (Drive B) Diskette Drive Type
Valid values for bits <7..4> and bits <3..0>:
0000 = Not installed
0001 = 360-KB drive
0010 = 1.2-MB drive
0011 = 720-KB drive
0100 = 1.44-MB/1.25-MB drive
0110 = 2.88-MB drive
(all other values reserved)
Configuration Byte 12h, Hard Drive Type
Bit
7..4
3..0
Function
Primary Controller 1, Hard Drive 1 Type:
0000 = none
1000 = Type 8
0001 = Type 1
1001 = Type 9
0010 = Type 2
1010 = Type 10
0011 = Type 3
1011 = Type 11
0100 = Type 4
1100 = Type 12
0101 = Type 5
1101 = Type 13
0110 = Type 6
1110 = Type 14
0111 = Type 7
1111 = other (use bytes 19h)
Primary Controller 1, Hard Drive 2 Type:
0000 = none
1000 = Type 8
0001 = Type 1
1001 = Type 9
0010 = Type 2
1010 = Type 10
0011 = Type 3
1011 = Type 11
0100 = Type 4
1100 = Type 12
0101 = Type 5
1101 = Type 13
0110 = Type 6
1110 = Type 14
0111 = Type 7
1111 = other (use bytes 1Ah)
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-27
Chapter 4 System Support
Configuration Byte 13h, Security Functions
Default Value = 00h
Bit
Function
7
Reserved
6
QuickBlank Enable After Standby:
0 = Disable
1 = Enable
5
Administrator Password:
0 = Not present
1 = Present
4
Reserved
3
Diskette Boot Enable:
0 = Enable
1 = Disable
2
QuickLock Enable:
0 = Disable
1 = Enable
1
Network Server Mode/Security Lock Override:
0 = Disable
1 = Enable
0
Password State (Set by BIOS at Power-up)
0 = Not set
1 = Set
Configuration Byte 14h, Equipment Installed
Default Value (standard configuration) = 03h
Bit
Function
7,6
No. of Diskette Drives Installed:
00 = 1 drive
10 = 3 drives
01 = 2 drives
11 = 4 drives
5..2
Reserved
1
Coprocessor Present
0 = Coprocessor not installed
1 = Coprocessor installed
0
Diskette Drives Present
0 = No diskette drives installed
1 = Diskette drive(s) installed
Configuration Bytes 15h and 16h, Base Memory Size
Default Value = 280h
Bytes 15h and 16h hold a 16-bit value that specifies the base memory size in increments of 1-KB
(1024) bytes. Valid base memory sizes are 512-KB and 640-KB.
Configuration Bytes 17h and 18h, Extended Memory Size
Bytes 17h and 18h hold a 16-bit value that specifies the extended memory size in increments of
1-KB (1024) bytes.
4-28 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
Configuration Bytes 19h-1Ch, Hard Drive Types
Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4>
hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte
12h bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and
2 of the secondary controller.
Configuration Byte 1Dh, Enhanced IDE Hard Drive Support
Default Value = F0h
Bit
Function
7
EIDE - Drive C (83h)
6
EIDE - Drive D (82h)
5
EIDE - Drive E (81h)
4
EIDE - Drive F (80h)
3..0
Reserved
Values for bits <7..4> :
0 = Disable
1 = Enable for auto-configure
Configuration Byte 1Fh, Power Management Functions
Default Value = 00h
Bit
Function
7..4
Reserved
3
Slow Processor Clock for Low Power Mode
0 = Processor runs at full speed
1 = Processor runs at slow speed
2
Reserved
1
Monitor Off Mode
0 = Turn monitor power off after 45 minutes in standby
1 = Leave monitor power on
0
Energy Saver Mode Indicator (Blinking LED)
0 = Disable
1 = Enable
Configuration Byte 24h, System Board Identification
Default Value = 7Eh
Configuration memory location 24h holds the system board ID.
Configuration Byte 25h, System Architecture Data
Default Value = 0Bh
Bit
Function
7..4
Reserved
3
Unmapping of ROM:
0 = Allowed
1 = Not allowed
2
Reserved
1,0
Diagnostic Status Byte Address
00 = Memory locations 80C00000h-80C00004h
01 = I/O ports 878h-87Ch
11 = neither place
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-29
Chapter 4 System Support
Configuration Byte 26h, Auxiliary Peripheral Configuration
Default Value = 00h
Bit
Function
7,6
I/O Delay Select
00 = 420 ns (default)
01 = 300 ns
10 = 2600 ns
11 = 540 ns
5
Alternative A20 Switching
0 = Disable port 92 mode
1 = Enable port 92 mode
4
Bi-directional Print Port Mode
0 = Disabled
1 = Enabled
3
Graphics Type
0 = Color
1 = Monochrome
2
Hard Drive Primary/Secondary Address Select:
0 = Primary
1 = Secondary
1
Diskette I/O Port
0 = Primary
1 = Secondary
0
Diskette I/O Port Enable
0 = Primary
1 = Secondary
Configuration Byte 27h, Speed Control/External Drive
Default Value = 00h
Bit
Function
7
Boot Speed
0 = Max MHz
1 = Fast speed
6..0
Reserved
Configuration Byte 28h, Expanded and Base Memory, IRQ12 Select
Default Value = 00h
Bit
Function
7
IRQ12 Select
0 = Mouse
1 = Expansion bus
6,5
Base Memory Size:
00 = 640 KB
01 = 512 KB
10 = 256 KB
11 = Invalid
4..0
Internal Compaq Memory:
00000 = None
00001 = 512 KB
00010 = 1 MB
00011 = 1.5 MB
.
.
11111 = 15.5 MB
Configuration Byte 29h, Miscellaneous Configuration Data
4-30 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
Default Value = 00h
Bit
Function
7..5
Reserved
4
Primary Hard Drive Enable (Non-PCI IDE Controllers)
0 = Disable
1 = Enable
3..0
Reserved
Configuration Byte 2Ah, Hard Drive Timeout
Default Value = 02h
Bit
Function
7..5
Reserved
4..0
Hard Drive Timeout
00000 = Disabled
00001 = 1 minute
00010 = 2 minutes
.
.
10101 = 21 minutes
Configuration Byte 2Bh, System Inactivity Timeout
Default Value = 23h
Bit
Function
7
Reserved
6,5
Power Conservation Boot
00 = Reserved
01 = PC on
10 = PC off
11 = Reserved
4..0
System Inactive Timeout. (Index to SIT system timeout record)
00000 = Disabled
Configuration Byte 2Ch, ScreenSave and NUMLOCK Control
Default Value = 00h
Bit
Function
7
Reserved
6
Numlock Control
0 = Numlock off at power on
1 = Numlock on at power on
5
Screen Blank Control:
0 = No screen blank
1 = Screen blank w/QuickLock
4..0
ScreenSave Timeout. (Index to SIT monitor timeout record)
000000 = Disabled
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September1997
4-31
Chapter 4 System Support
Configuration Byte 2Dh, Additional Flags
Default Value = 00h
Bit
Function
7..5
Reserved
4
Memory Test
0 = Test memory on power up only
1 = Test memory on warm boot
3
POST Error Handling (BIOS Defined)
0 = Display “Press F1 to Continue” on error
1 = Skip F1 message
2..0
Reserved
Configuration Byte 2Eh, 2Fh, Checksum
These bytes hold the checksum of bytes 10h to 2Dh.
Configuration Byte 30h, 31h, Total Extended Memory Tested
This location holds the amount of system memory that checked good during the POST.
Configuration Byte 32h, Century
This location holds the Century value in a binary coded decimal (BCD) format.
Configuration Byte 33h, Miscellaneous Flags
Default Value = 80h
Bit
Function
7
Memory Above 640 KB
0 = No, 1 = Yes
6
Reserved
5
Weitek Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
4
Standard Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
3..0
Reserved
Configuration Byte 34h, International Language Support
Default Value = 00h
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Configuration Byte 35h, APM Status Flags
Default Value = 11h
Bit
Function
7..6
Power Conservation State:
00 = Ready
01 = Standby
10 = Suspend
11 = Off
5,4
Reserved
3
32-bit Connection:
0 = Disconnected, 1 = Connected
2
16-bit Connection
0 = Disconnected, 1 = Connected
1
Real Mode Connection
0 = Disconnected, 1 = Connected
0
Power Management Enable:
0 = Disabled
1 = Enabled
Configuration Byte 36h, ECC POST Test Single Bit Errors
Default Value = 01h
Bit
Function
7
Row 7 Error Detect
6
Row 6 Error Detect
5
Row 5 Error Detect
4
Row 4 Error Detect
3
Row 3 Error Detect
2
Row 2 Error Detect
1
Row 1 Error Detect
0
Row 0 Error Detect
0 = No single bit error detected.
1 = Single bit error detected.
Configuration Byte 37h-3Fh, Power-On Password
These eight locations hold the power-on password.
Configuration Byte 40h, Miscellaneous Disk Data
Configuration Bytes 41h-44h, Hood Removal Time Stamp
These four bytes record the time at which the hood of the system was removed:
Byte 41h, month & day
Byte 42h, year and month
Byte 43h, minutes and seconds
Byte 44h, removal flag and minutes
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Configuration Byte 45h, Keyboard Snoop Data
Default Value = xxh
Bit
Function
7
Cntrl/F10 Key Status:
0 = Cntrl & F10 keys not pressed
1 = Cntrl & F10 keys pressed
6
F10 Key Status:
0 = F10 key not pressed
1 = F10 key pressed
5..1
Reserved
0
Key Pressed Flag:
0 = Key not pressed
1 = Key pressed
Configuration Byte 46h, Diskette/Hard Drive Status
Default Value = xxh
Bit
Function
7,6
Reserved
5
Partition On HD:
0 = Not set, 1 = Set
4
Setup Disk:
0 = Not present, 1 = Present
3
ROMPAQ or DIAGS Diskette:
0 = Not present, 1 = Present
2
Boot Diskette in Drive A:
0 = No, 1 = Yes
1
Drive B: Present:
0 = Not present, 1 = Present
0
Drive A: Present:
0 = Not present, 1 = Present
Configuration Bytes 47h-4Fh, IPL Data
These bytes hold initial program load (IPL) data for boot purposes:
Byte 47h, last IPL device
Bytes 48h-4Bh, IPL priority
Byte 4Ch-4Fh, BCV priority
Configuration Byte 51h, ECC Status Byte
Default Value = xxh
Bit
Function
7
ECC Status for DIMM 3
6
ECC Status for DIMM 2
5
ECC Status for DIMM 1
4
ECC Status for DIMM 0
3..0
Reserved
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Configuration Byte 52h, Board Revision
This byte holds the board revision as copied from the boot block sector.
Configuration Byte 53h, 54h, SW SMI Command/Data Bytes
Configuration Byte 55h, APM Command Byte
Configuration Byte 56h, Miscellaneous Flags Byte
Bit
7
6
5
4
3..1
0
Function
CAS Latency:
0 = 2, 1 = 3
IR Port Enable Flag:
0 = Disabled (COM2 config. for standard serial port)
1 = Enabled (COM2 config. for IrDA)
Warm Boot Enable Flag:
0 = Disable, 1 = Enable
POST Terse/Verbose Mode
0 = Verbose, 1 = Terse
Erase Ease Keyboard Mode:
000 = Backspace/Spacebar
001 = Spacebar/Backspace
010 = Spacebar/Spacebar
011-111 = Invalid
Configurable Power Supply:
0 = Power switch active
1 = Power switch inhibited
Configuration Byte 57h-76h, CMOS Copy
Configuration Bytes 77h-7Fh, Administrator Password
Configuration Byte 80h, CMOS Diagnostic Flags Byte
Default Value = 00h. Set bit indicates function is valid.
Bit
Function
7
CMOS Initialization (Set CMOS to Default)
6
Setup password locked
5
PnP should not reject SETs because Diags is active
4
Reserved
3
Manufacturing diagnostics diskette found
2
Invalid electronic serial number
1
Boot maintenance partition once
0
Invalid CMOS checksum
Configuration Byte 81h, 82h, Total Super Extended Memory Tested
This byte holds the value of the amount of extended system memory that tested good during
POST. The amount is given in 64-KB increments.
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Configuration Byte 83h, Microprocessor Identification
This byte holds the component ID and chip revision of the microprocessor.
Configuration Byte 84h, Microprocessor Revision
Configuration Byte 85h, Hood Lock/Administration Mode
Bit
7,6
5
4
3
2
1
0
Function
Reserved
ESCD Buffering:
0 = No buffering, 1 = ESCD buffered at F000h.
Hood Lock Enable:
0 = Disabled, 1 = Enabled
User Mode Flag
Administration Mode Flag
Level Support:
0 = Level 1, 1 = Level 2
Feature Support Bit
0 = Disabled, 1 = Enabled
Configuration Byte 86h, Fast Boot Date
Configuration Byte 87h, Fast Boot Select
Bit
7..3
2
1
0
Function
Configuration Byte 88h, Fast Boot Date (Year/Century)
Configuration Byte 89h, APM Resume Timer
Bit <7> indicates the timer status: 0 = disabled, 1 = timer set.
Configuration Byte 8Ah-8Fh, APM Resume Timer
These bytes hold the APM timer values:
Byte 8Ah, minutes
Byte 8Bh, hours
Byte 8Ch, day
Byte 8Dh, month
Byte 8Eh, year
Byte 8Fh, century
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Configuration Byte 90h, 91h, Total Super Extended Memory Configured
This byte holds the value of the amount of extended system memory that is configured.
The amount is given in 64-KB increments.
Configuration Byte 92h, Miscellaneous Configuration Byte
Default Value = 18h
Bit
Function
7..5
Reserved
4
Diskette Write Control:
0 = Disable
1 = Enable
3..1
Reserved
0
Diskette Drive Swap Control:
0 = Don’t swap
1 = Swap drive A: and B:
Configuration Byte 93h, PCI Configuration Byte
Default Value = 00h
Bit
Function
7
Onboard SCSI Status:
0 = Hidden
1 = Active
6
Onboard NIC Status:
0 = Hidden
1 = Active
5
Onboard USB Status:
0 = Hidden
1 = Active
3
Reserved
2
ISA Passive Release:
0 = Enabled
1 = Disabled
1
PCI Bus Master Enable
0 = Enabled
1 = Disabled
0
PCI VGA Palette Snoop
0 = Disable
1 = Enable
If palette snooping is enabled, then a primary PCI graphics card may share a common palette
with the ISA graphics card. Palette snooping should only be enabled if all of the following
conditions are met:
♦
♦
♦
♦
An ISA card connects to a PCI graphics card through the VESA connector.
The ISA card is connected to a color monitor.
The ISA card uses the RAMDAC on the PCI card
The palette snooping feature (sometimes called “RAMDAC shadowing”) on the PCI card is
enabled and functioning properly.
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Configuration Byte 94h, ROM Flash/Power Button Status
Default Value = 00h
Bit
Function
7..5
Reserved
4
ROM Flash In Progress (if set)
3
Reserved
2
Power Button Inhibited (ifset)
1
User-Forced Bootblock (if set)
0
ROM Flash In Progress (if set)
Configuration Byte 97h, Asset/Test Prompt Byte
Default Value = 00h
Bit
Function
7,6
Test Prompt:
01 = Fake F1
10 = Fake F2
11 = Fake F10
5..0
Asset Value
Configuration Byte 9Bh, Ultra-33 DMA Enable Byte
Default Value = 00h
Bit
Function
7..4
Reserved
3
Secondary Slave Enabled for U-33 if Set
2
Secondary Master Enabled for U-33 if Set
1
Primary Slave Enabled for U-33 if Set
0
Primary Master Enabled for U-33 if Set
Configuration Byte 9Ch, Mode-2 Configuration Byte
Default Value = 1Ch
Bit
Function
7,6
Reserved
5
Mode 2 Support
0 = Disable
1 = Enable
4
Secondary Hard Drive Controller
0 = Disable
1 = Enable
3,2
Secondary Hard Drive Controller IRQ
00 = IRQ10
01 = IRQ11
10 = IRQ12
11 = IRQ15
1,0
Reserved
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Configuration Byte 9Dh, ESS Audio Configuration Byte
Default Value = 12h
Bit
Function
7
Reserved for Game Port Enable
6,5
Audio Address
00 = 22xh
01 = 23xh
10 = 24xh
11 = 25xh
4,3
DMA Channel
00 = Disabled
01 = DMA0
10 = DMA1
11 = DMA3
2,1
IRQ Select
00 = IRQ9
01 = IRQ5
10 = IRQ7
11 = IRQ10
0
ESS Audio Chip Enable
0 = Enabled
1 = Disabled
Configuration Byte 9Eh, ECP DMA Configuration Byte
Default Value = 03h
Bit
Function
7..4
Reserved
3
SafeStart Control:
0 = Disable
1 = Enable
2..0
ECP DMA Channel
000 = Invalid
100 = Disabled
All other values (001-011, 101-111) refer to channel no.
Configuration Byte 9Fh-AFh, Asset Tag Serial Number
Configuration Bytes B0h-C3h; Custom Hard Drive Information
These bytes contain the number of cylinders, heads, and sectors per track for hard drives C, D, E,
and F respectively. The mapping for each drive is as follows:
Drive 65 (C)
B0h
B1h
B2h
B3h
B4h
Drive 66 (D)
B5h
B6h
B7h
B8h
B9h
Drive 68 (E)
BAh
BBh
BCh
BDh
BEh
Drive 15 (F)
BFh
C0h
C1h
C2h
C3h
Function
No. of Cylinders, Low Byte
No. of Cylinders, High Byte
No. of Heads
Max ECC Bytes
No. of Sectors Per Track
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Configuration Byte C7h, C8h, Serial Ports 1 and 2 (Respectively) Configuration Bytes
Default Value = FEh, 7Dh
Bit
Function
7..2
Base I/O Address (in packed format)
(Algorithm: [Addr. - 200h] / 8)
(i.e., 3Fh = 3F8h, 1Fh = 2F8h, 00 = 200h)
1..0
Reserved
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4.6
I/O MAP AND REGISTER ACCESSING
This section describes the system I/O map and methods of accessing various system functions.
4.6.1
SYSTEM I/O MAP
Table 4–17. System I/O Map
Table 4-17.
System I/O Map
I/O Port
Function
0000..000Fh
DMA Controller 1
0020..0021h
Interrupt Controller 1
0040..0043h
Timer 1
0060h
Keyboard Controller Data Byte
0061h
NMI, Speaker Control
0064h
Keyboard Controller Command/Status Byte
0070h
NMI Enable, RTC Address
0071h
RTC Data
0078h..007Bh
General Purpose I/O Port 1
007Ch..007Fh
General Purpose I/O Port 2
0080..008Fh
DMA Page Registers
0092h
Port A, Fast A20/Reset
00A0..00A1h
Interrupt Controller 2
00B2h, 00B3h
APM Control/Status Ports
00C0..00DFh
DMA Controller 2
00F0h
Math Coprocessor Busy Clear
015C, 015Dh
87307 I/O Controller Configuration Registers (Index, Data)
0170..0177h
Hard Drive (IDE) Controller 2
01F0..01FFh
Hard Drive (IDE) Controller 1
0201..024Fh
Reserved.
0278..027Bh
Parallel Port (LPT2)
02F8..02FFh
Serial Port (COM2)
0371.. 0375h
Diskette Drive Controller Alternate Addresses
0376h
IDE Controller Alternate Address
0377h
IDE Controller Alternate Address, Diskette Drive Controller Alternate Address
0378..037Fh
Parallel Port (LPT1)
0388..038Bh
FM synthesizer (alias addresses)
03B0..03DFh
Graphics Controller
03E8..03EFh
Serial Port (COM3)
03F0..03F5h
Diskette Drive Controller Primary Addresses
03F6, 03F7h
Diskette Drive Controller Primary Addresses, Hard Drive Controller Primary Addresses
03F8..03FFh
Serial Port (COM1)
04D0, 04D1h
Master, Slave Edge/Level INTR Control Register
0C06, 0C07h
Reserved - Compaq proprietary use only
0C50, 0C51h
System Management Configuration Registers (Index, Data)
0C70..0C77h
ACPI
0C82h
Auto Rev Data (not used)
0CF8h
PCI Configuration Address (dword access)
0CFCh
PCI Configuration Data (byte, word, or dword access)
F800..F83Fh
ACPI & GPIOs
NOTE: Assume unmarked gaps are reserved/unused.
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Chapter 4 System Support
4.6.2
87307 I/O CONTROLLER CONFIGURATION
The 87307 I/O controller contains various functions such as the keyboard/mouse interfaces,
diskette interface, serial interfaces, and parallel interface. Software control of these interfaces
uses standard AT-type I/O addressing. Firmware configuration of these functions uses indexed
ports unique to the 87307. In this system, hardware strapping selects I/O addresses 015Ch and
015Dh at reset as the Index/Data ports for accessing the configuration registers of the logical
devices within the 87307. The hardware strapping also places the 87307 into PnP motherboard
mode. Table 4-18 lists the PnP standard configuration registers for the devices within the 87307.
Table 4–18. 87307 I/O Controller PnP Standard Control Registers
Table 4-18.
87307 I/O Controller PnP Standard Configuration Registers
Index
00h
01h
02h
03h
04h
05h
06h
07h
20h
21h
22h
23h
24h
30h
31h
60,61h
62,63h
70h
71h
74,75h
F0h
F1h
Function
Set RD_DATA Port
Serial Isolation
Configuration Control
Wake (CSN)
Resource Data
Status
Card Select Number (CSN)
Logical Device Select:
00h = 8042 Controller (Keyboard I/F)
01h = 8042 Controller (Mouse I/F)
02h = RTC/APC Configuration
03h = Diskette Controller
04h = Parallel Port
05h = UART 2 (Serial Port B / IrDA)
06h = UART 1 (Serial Port A)
07h = GPIO Ports
08h = Power Management
Super I/O ID Register (SID)
SIO Configuration 1 Register
SIO Configuration 1 Register
Programmable Chip Select Configuration Index
Programmable Chip Select Configuration Data
Logical Device Activate
Logical Device I/O Range Check
Logical Device Data Base Address
Logical Device Command Base Address
Logical Device Interrupt Select
Logical Device Interrupt Type
Logical Device DMA Assignment
Logical Device Configuration
Drive ID (Logical Device 03 only)
Reset Value
00h
00h
00h
00h
A0h
D6h
02h
00h
00h
----------
The configuration registers are accessed by writing the appropriate logical device’s number to
index 07h and writing the desired offset to the index register. The data is then either written to or
read from the data register.
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The 87307 I/O Controller provides 11 general purpose pins that can be individually configured as
either inputs or outputs. These pins are mapped as two general purpose ports and softwareaccessable through the registers shown below.
GPIO Port 1 Data, I/O Addr. 078h, (87307 I/O Controller)
Bit
7..4
3
2
1,0
Function
GPIO17..GPIO14: Not used.
GPIO13 (config. as input). Bus Fraction (BF2)
GPIO12 (config. as input): CPU Bus Speed
Read 0, 60 MHz
Read 1, 66 MHz
GPIO11,10 (config. as inputs): Bus Fraction (ratio) BF1,0
Read 00, 2/5 bus/core speed ratio
Read 10, 1/3 bus/core speed ratio
Read 01, ½ bus/core speed ratio
Read 11, 2/7 bus/core speed ratio
GPIO Port 1 Direction, I/O Addr. 079h, (87307 I/O Controller)
GPIO Port 1 Output Type, I/O Addr. 07Ah, (87307 I/O Controller)
GPIO Port 1 Pullup Control, I/O Addr. 07Bh, (87307 I/O Controller)
GPIO Port 2 Data, I/O Addr. 07Ch, (87307 I/O Controller)
Bit
7..4
3
2
1,0
Function
GPIO27..24 (config. as I/O): X bus bits <5..2>
GPIO23 (config. as input): Ring Wake Up (Serial Modem)
Read 0, Ring indicate active
Read 1, Ring indicate inactive
GPIO22 (config. as output): NIC I/F Enable.
Write 0 to enable.
Write 1 to disable.
GPIO21 Not used.
GPIO Port 2 Direction, I/O Addr. 07Dh, (87307 I/O Controller)
GPIO Port 2 Output Type, I/O Addr. 07Eh, (87307 I/O Controller)
GPIO Port 2 Pullup Control, I/O Addr. 07Fh, (87307 I/O Controller)
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Chapter 4 System Support
4.7
SYSTEM MANAGEMENT SUPPORT
This section describes the hardware support of functions involving security, safety, identification,
and power consumption of the system. System management functions are handled largely
through a Compaq-proprietary ASIC. Most functions are controlled through registers (Table 419) accessed using the indexed method through I/O ports 0C50h (index) and 0C51h (Data).
Table 4–19. System Management Control Registers
Table 4-19.
System Management Control Registers
Index
00h
02h
03h
05h
12h
13h
20h
21h
22h
30h
80h-89h
Function
Identification
Temperature Status / Clear
Temperature Interrupt / SMI Enable
Power On LED Blink Control
General Purpose Open Collector (GPOC) Bits
Secured GPOC Bits
Power Button Control
SMI / SCI Source
SMI / SCI Mapping
REQ/GNT Control
Reserved
NOTE: System management functions are handled by BIOS and the Setup utility. The
information in the following subsections is intended only for clarification of system operations.
4.7.1
FLASH ROM WRITE PROTECT
The system BIOS firmware is contained in a flash ROM device that can be re-written with
updated code if necessary. The ROM is write-protected with a Black Box* security feature. The
Black Box feature uses the Administrator password to protect against unauthorized writes to the
flash ROM. During the boot sequence, the BIOS checks for the presence of the ROMPAQ
diskette. If ROMPAQ is detected and the password is locked into the Black Box with the Protect
Resources command, an Access Resources command followed by Administrator password entry
must occur before the ROM can be flashed. If the Permanently Lock Resources command has
been invoked, the power must be cycled before the ROM can be flashed. The system ROM is
write-protected as follows:
Start Addr.
C0000h
F0000h
F8000h
FA000h
End Addr.
EFFFFh
F7FFFh
F9FFFh
FFFFFh
Data Type
Option ROM
System BIOS
ESCD
Boot Block
Protection
Password write-protected
Password write-protected
Never write-protected
Always write-protected
The flashing functions are handled using the INT15 AX-E822h BIOS interface.
* Black Box logic Compaq-proprietary and controlled exclusively through firmware in the BIOS ROM.
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4.7.2
PASSWORD PROTECTION
When enabled, the user is prompted to enter the power-on password during POST. If an
incorrect entry is made, the system halts and does not boot. The Power-On password is stored in
eight bytes at configuration memory locations 37h-3Fh. These locations are physically located
within the 87307. At the time a new password is written into 37h-3Fh, the password is also
written into Black Box* logic. The Black Box logic is used for power-on password protection
support instead of the port 92 sequence used on other systems. The Black Box logic prevents
inadvertent or unauthorized access to the password bytes of the 87307 by monitoring I/O ports
70/71h for access to the 37h-3Fh CMOS range and inhibiting the AEN signal to the 87307 if
such access is detected. Slot 1 of the Black Box logic can be written to at runtime, allowing the
user to change the power on password without cycling power and going through the F10 method.
The Black Box password cannot be read.
The power-on password function can be disabled by setting DIP SW1 position 1 to on (closed).
The administrator password is stored in eight bytes at configuration memory locations 77h-7Fh.
If the administrator password function is enabled, the user is prompted to enter the password
before running F10-Setup or before booting from a ROMPAQ diskette. If an incorrect entry is
made, the system boots although system administration functions are inhibited. The
administrator password is also stored in the Black Box* logic. Black Box logic acting as the
sentry for the administrator password by preventing inadvertent or unauthorized writing to the
Flash ROM.
* Black Box logic is Compaq-proprietary and controlled exclusively through firmware in BIOS ROM.
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Chapter 4 System Support
4.7.3
I/O SECURITY
The 87307 I/O controller allows various I/O functions to be disabled through configuration
registers. In addition, the configuration registers of the 87307 are further protected by Client
Management (CM) logic, which can be set (using BIOS call INT 15 AX=E829h) to block access
to the 87307 configuration registers of the following functions:
♦
♦
♦
Diskette drive
Serial port
Parallel port
In blocking 87307 functions, the CM logic monitors ISA I/O cycles and can detect, through
index address-matching, when an attempt is made to access a function provided by the 87307. If
the CM logic has been set to block access, then ISA bus signal AEN or IOWC-, both which the
CM logic provides to the 87307, is disabled, effectively inhibiting the I/O access.
The NIC controller can also be blocked from access by the CM logic. In this case the CM logic
can be set to block the routing of the IDSEL signal to the NIC controller, thereby disabling the
interface.
4.7.4
USER SECURITY
The QuickLock feature allows, if enabled in F10-Setup through CMOS location 13h bit <2>, the
user to lock the keyboard and mouse by invoking the Ctrl-Alt-L keystrokes. This initiates an SMI
and the SMI handler then takes the action required to lock the keyboard. If the QuickBlank
feature is enabled at that time then the screen will be blanked as well. The user then must enter
the power-on password to re-activate the keyboard and/or display .
NOTE: Although the SMI is used for initiating QuickLock/QuickBlank functions, these
functions are not considered power management features.
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4.7.5
TEMPERATURE SENSING
Two components (one programmable LM75 and one TC623) are used in monitoring the internal
temperature of the system. The LM75 sensor is mounted in the cavity of the microprocessor
socket to detect microprocessor temperature. The LM75 is programmed for two temperature
levels:
a. Tos - Overtemperature shutdown value (level at which the LM75’s output becomes
active)
b. Thyst - Hysterious value (level at which the LM75’s output is negated)
In the standard configuration the BIOS programs Tos for 60°C and Thyst for 58°C. Detection by
the LM75 sensor results in a warning being issued to the user and/or the power supply fan being
turned on. Note that upgrading to particular microprocessor step with unique operating
temperature characteristics may require that the BIOS be upgraded as well in order to set the
LM75 to the proper detection levels.
The following two indexed registers are used by BIOS and available to software for controlling
the temperature sense function.
I/O Port C51.02h, Temperature Status/Clear Register
Bit
Function
7..2
Reserved
1
Temperature Deadly (RO)
0 = Normal
1 = Critical temperature detected
0
Temperature Caution for Processor 1 (RO)
0 = Normal
1 = High temperature detected at P1
NOTE: Bits 2..0 are cleared when read but will be instantly reset if condition remains.
I/O Port C51.03h, Temperature Interrupt/SMI Enable Register
Bit
Function
7..3
Reserved
2
Temperature Deadly Shutdown Disable:
0 = Initiate shutdown w/deadly condition.
1 = Do not initiate shutdown.
1
Temperature SMI Enable:
0 = Do not generate SMI- w/caution condition.
1 = Generate SMI- upon caution condition.
0
Temperature IRQ Enable:
0 = Do not generate IRQ w/ caution condition.
1 = Generate IRQ w/caution condition.
A second sensor (TC623) is used to detect a deadly temperature condition. This sensor, which is
non-programmable (fixed), activates a signal that disables the ICS9147 clock generator,
effectively shutting down the system.
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Chapter 4 System Support
4.7.6
POWER MANAGEMENT
This system includes hardware support of Advanced Power Management (APM ver. 1.2)
firmware and software and is Energy Star-compliant.
4.7.6.1 HARD DRIVE SPINDOWN CONTROL
The timeout parameter stored in the SIT record 04h and indexed through CMOS location 2Ah
(bits <4..0>) represents the period of hard drive inactivity required to elapse before the hard drive
is allowed to spin down. The timeout value is downloaded from CMOS to a timer on the hard
drive. The timeout period can be set in incremental values of 0 (timeout disabled), 10, 15
(default), 20, 30, and 60 minutes. A timed-out and spun-down hard drive will automatically spin
back up upon the next drive access. It is normal for the user to detect a certain amount of access
latency in this situation.
4.7.6.2 DISPLAY MONITOR POWER MANAGEMENT CONTROL
This system supports monitor power control for graphics controllers and display monitors that
conform to the VESA display power management signaling (DPMS) protocol. This protocol
defines different power consumption conditions and uses the HSYNC and VSYNC signals to
select a monitor’s power condition This operation is described in chapter 6, “Graphics
Subsystem.”
The timeout parameter set in the SIT record 03h and indexed at CMOS location 2Ch (bits
<4..0>) represents the period of system I/O inactivity required to elapse before the monitor is
placed into Suspend mode.
A separate timer function (enabled through CMOS location 1Fh, bit <1>) can be enabled to place
the monitor into the Off mode after 45 minutes of being in Suspend mode.
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Chapter 5
INPUT/OUTPUT INTERFACES
5.
5.1
Chapter 5 INPUT/OUTPUT INTERFACES
INTRODUCTION
This chapter describes the system’s interfaces that provide input and output (I/O) porting of data
and specifically discusses interfaces that are controlled through I/O-mapped registers. The I/O
interfaces are integrated functions of the support chipset and the 87307 I/O controller. The
following I/O interfaces are covered in this chapter:
♦
♦
♦
♦
♦
♦
♦
5.2
Enhanced IDE (EIDE) interface (5.2)
Diskette drive interface (5.3)
Serial interfaces (5.4)
Parallel interface (5.5)
Keyboard/pointing device interface (5.6)
Ethernet interface (5.7)
Universal serial bus interface (5.8)
page 5-1
page 5-10
page 5-15
page 5-21
page 5-28
page 5-35
page 5-37
ENHANCED IDE INTERFACE
The enhanced IDE (EIDE) interface consists of primary and secondary interfaces that can
support two IDE devices each. Devices that may connect to an IDE interface include hard drives,
CD-ROM drives, power (writeable CD-ROM) drives, and 120-MB floptical drives.
Two 40-pin keyed IDE data connectors and one 50-pin keyed connector are provided on the
system board. Each 40-pin connector can support two devices* and can be configured
independently for PIO or bus master (DMA) operation. In the standard configuration the hard
drive is attached to the primary connector and the CD-ROM (if installed) is attached to the 50pin secondary connector.
The system ROM supports PIO modes 1-4 and Ultra ATA (UATA) modes 0-2, although the type
of drive connected will determine the final transfer speed.
NOTE: For UATA mode 2 operation an 80-conductor cable must be used. A 40conductor cable will result in the BIOS limiting IDE operation to a maximum transfer
of 25 MB/s (UATA mode 1).
5.2.1
IDE PROGRAMMING
The IDE interface is configured as a PCI device and controlled through standard I/O mapped
registers.
*
Refer to chapter 2 for possible physical limitations on drive accommodations.
Compaq Deskpro 4000N and 4000S Personal Computers 5-1
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.2.1.1 IDE Configuration Registers
The IDE interface is handled by the 82586 component and configured as a PCI device with bus
mastering capability. The PCI configuration registers for the IDE controller function (PCI device
#20, function #1) are listed in Table 5-1.
Table 5–1. IDE PCI Configuration Registers
Table 5-1.
EIDE PCI Configuration Registers (82586, Function 1)
PCI
Conf.
Addr.
00-01h
02-03h
04-05h
06-07h
08h
09h
0Ah
0Bh
0Dh
0Eh
10-13h
14-17h
18-1Bh
1C-1Fh
20-23h
24-27h
3Ch
3Dh
3Eh
3Fh
NOTE:
Register
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming
Sub-Class
Base Class Code
Master Latency Timer
Header Type
Pri. Data/Cmd Base Addr.
Pri. Cntrl./Sts. Base Addr.
Sec. Data/Cmd Base Addr.
Sec. Cntrl./Sts. Base Addr.
Bus Mstr. Cntrl. Reg. Base Addr.
Mem. Base Addr. for MM I/O
Interrupt Line
Interrupt Pin
Min_GNT
Min_LAT
Value
on
Reset
1106h
0586h
0000h
0000h
0Ah
xxxxh
01h
01h
0000h
80h
1F0h
3F4h
170h
374h
0Eh
PCI
Conf.
Addr.
40h
41h
42h
43h
44h
45h
46h
48h
49h
4Ah
4Bh
4Ch
4E, 4Fh
50h
51h
52h
53h
54-5Fh
60, 61h,
68, 69h
Register
Chip Enable reg.
IDE Configuration
Miscellaneous Control
FIFO Configuration
Miscellaneous Control
Miscellaneous Control
Miscellaneous Control
Sec. IDE Drv.1 Timing Cntrl.
Sec. IDE Drv.0 Timing Cntrl
Pri. IDE Drv.1 Timing Cntrl.
Pri. IDE Drv.0 Timing Cntrl
Address Setup Time
Non-1F0h Port Drive Timing
Sec. Drive 1 Ext. Timing
Sec. Drive 0 Ext. Timing
Pri. Drive 1 Ext. Timing
Pri. Drive 0 Ext. Timing
Reserved
Sector Size for Pri. IDE
Sector Size for Sec. IDE
Value
on
Reset
00h
C0h
A8h
A8h
A8h
A8h
00FFh
00h
00h
00h
00h
200h
200h
Assume unmarked gaps are reserved and/or not used.
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the I/O mapped control registers
listed in Table 5-2.
Table 5–2. IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
00h
02h
04h
08h
0Ah
0Ch
5-2
Size
(Bytes)
2
2
4
2
2
4
Register
Bus Master IDE Command (Primary)
Bus Master IDE Status (Primary)
Bus Master IDE Descriptor Ptr (Pri.)
Bus Master IDE Command (Secondary)
Bus Master IDE Status (Secondary)
Bus Master IDE Descriptor Ptr (Sec.)
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Default
Value
00h
00h
0000 0000h
00h
00h
0000 0000h
Technical Reference Guide
5.2.1.3 IDE ATA Control Registers
The IDE controller of the 82586 decodes the addressing of the standard AT attachment (ATA)
registers for the connected drive, which is where the ATA control registers actually reside. The
primary and secondary interface connectors are mapped as shown in Table 5-3.
Table 5–3. IDE ATA Control Registers
Table 5-3.
IDE ATA Control Registers
Primary
I/O Addr.
1F0h
1F1h
1F1h
1F2h
1F3h
1F4h
1F5h
1F6h
1F7h
1F7h
3F6h
3F6h
3F7h
3F7h
Secondary
I/O Addr.
170h
171h
171h
172h
173h
174h
175h
176h
177h
177h
376h
376h
377h
377h
Register
Data
Error
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status
Command
Alternate Status
Drive Control
Drive Address
n/a for hard drive
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R
W
R
W
R
W
The following paragraphs describe the IDE ATA control registers.
Data Register, I/O Port 1F0h/170h
This register is used for transferring all data to and from the hard drive controller. This register
is also used for transferring the sector table during format commands. All transfers are highspeed 16-bit I/O operation except for Error Correction Code (ECC) bytes during Read/Write
Long commands.
Error Register, I/O Port 1F1h/171h (Read Only)
The Error register contains error status from the last command executed by the hard drive
controller. The contents of this register are valid when the following conditions exist:
♦
♦
Error bit is set in the Status register
Hard drive controller has completed execution of its internal diagnostics
Compaq Deskpro 4000N and 4000S Personal Computers 5-3
First Edition - September 1997
Chapter 5 Input/Output Interfaces
The contents of the Error register are interpreted as a diagnostic status byte after the execution of
a diagnostic command or when the system is initialized.
Bit
7
6
5
4
3
2
1
0
Function
Bad Block Mark Detected in Requested Sector ID Field (if set)
Non-correctable Data Error (if set)
Reserved
Requested Sector ID Field Not Found (if set)
Reserved
Requested Command Aborted Due To Invalid Hard Drive
Status or Invalid Command Code (if set)
Track 0 Not Found During Re-calibration Command (if set)
Data Address Mark Not Found After Correct ID Field (if set)
Set Features Register, I/O Port 1F1h/171h (Write Only)
This register is command-specific and may be used to enable and disable features of the interface.
Sector Count Register, I/O Port 1F2h/172h
This register defines either:
♦ the number of sectors of data to be read or written
or
♦ the number of sectors per track for format commands
If the value in this register is zero, a count of 256 sectors is specified. The sector count is
decremented as each sector is accessed, so that the value indicates the number of sectors left to
access when an error occurs in a multi-sector operation. During the Initialize Drive Parameters
command, this register contains the number of sectors per track.
Sector Number Register, I/O Port 1F3h/173h
The Sector Number register contains the starting sector number for a hard drive access.
Cylinder Low, Cylinder High Registers, I/O Port 1F4h, 1F5h/174h, 175h
These registers contain the starting cylinder number for each hard drive access. The three mostsignificant bits of the value are held in byte address 1F5h (bits <2..0>) while the remaining bits
are held in location 1F4h.
5-4
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
Drive Select/Head Register, I/O Port 1F6h/176h
Bit
7
6,5
4
3..0
Function
Reserved
Sector Size:
00 = Reserved
01 = 512 bytes/sector
10, 11 = Reserved
Drive Select:
0 = Drive 1
1 = Drive 2
Head Select Number:
0000 = 0
1000 = 8
0001 = 1
1001 = 9
0010 = 2
1010 = 10
0011 = 3
1011 = 11
0100 = 4
1100 = 12
0101 = 5
1101 = 13
0110 = 6
1110 = 14
0111 = 7
1111 = 15
NOTE:
Setting bit <4> to 1 when Drive 2 is not present may cause remaining
controller registers to not respond until Drive 1 is selected again.
Status Register, I/O Port 1F7h/177h (Read Only)
The contents of this register are updated at the completion of each command. If the Busy bit is
set, no other bits are valid. Reading this register clears the IRQ14 interrupt.
Bit
7
6
5
4
3
2
1
0
Function
Controller Busy. If set, controller is executing a command.
READY- Signal Active (if set).
WRITE FAULT- Signal Active (if set).
SEEK COMPLETE- Signal Active (if set)
Data Request. If set, the controller is ready for a byte or wordlength data transfer. Bit should be verified before each transfer.
Correctable Data Error Flag. If set, data error has occurred and
has been corrected.
INDEX- Signal Active (if set).
Error Detected. When set, indicates error has occurred. O.ther
bits in register should be checked to determine error source.
NOTE:
Register status of an error condition does not change
until register is read.
The alternate Status register at location 3F6h holds the same status data as location 1F7h but
does not clear hardware conditions when read.
Compaq Deskpro 4000N and 4000S Personal Computers 5-5
First Edition - September 1997
Chapter 5 Input/Output Interfaces
Command Register, I/O Port 1F7h/177h (Write Only)
The IDE controller commands are written to this register. The command write action should be
prefaced with the loading of data into the appropriate registers. Execution begins when the
command is written to 1F7h/177h. Table 5-4 lists the standard IDE commands.
Table 5–4. IDE Controller Commands
Table 5-4.
IDE Controller Commands
Command
Initialize Drive Parameters
Seek
Recalibrate
Read Sectors with Retries
Read Long with Retries
Write Sectors with Retries
Write Long with Retries
Verify Sectors with Retries
Format Track
Execute Controller Diagnostic
Idle
Idle Immediate
Enter Low Power and Enable/Disable Timeout
Enter Idle and Enable/Disable Timeout
Check Status
Identify
Read Buffer
Write Buffer
NOP
Read DMA with Retry
Read DMA without Retry
Read Multiple
Set Features
Set Multiple Mode
Sleep
Standby
Standby Immediate
Write DMA with Retry
Write DMA without Retry
Write Multiple
Write Same
Write Verify
* Without retries, add one to the value.
Value
91h
7xh
1xh
20h*
22h*
30h*
32h*
40h
50h
90h
97h, E3h
95h, E1h
96h
97h
98h
ECh
E4h
E8h
00h
C8h
C9h
C4h
EFh
C6h
99h, E6h
96h, E2h
94h, E0h
CAh
CBh
C5h
E9h
3Ch
Alternate Status Register, I/O Port 3F6h/376h (Read Only)
The alternate Status register at location 3F6h holds the same status data as location 1F7h but
does not clear hardware conditions when read.
5-6
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
Drive Control Register, I/O Port 3F6h/376h (Write Only)
Bit
7..3
2
1
0
Function
Reserved
Controller Control:
0 = Re-enable
1 = Reset
Interrupt Enable/Disable
0 = Disable interrupts
1 = Enable interrupts
Reserved
Drive Access Register, I/O Port 3F7h/377h (Read Only)
Bit
7
6
5..2
1,0
Function
Reserved
WRITE GATE- Signal Active (if set)
Head Select:
0000 = 15
1000 = 7
0001 = 14
1001 = 6
0010 = 13
1010 = 5
0011 = 12
1011 = 4
0100 = 11
1100 = 3
0101 = 10
1101 = 2
0110 = 9
1110 = 1
0111 = 8
1111 = 0
Drive Select:
00 = Disabled
01 = Drive 1 selected
10 = Drive 0 selected
11 = Invalid
Compaq Deskpro 4000N and 4000S Personal Computers 5-7
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.2.2
IDE CONNECTORS
This system includes two standard 40-pin connectors and one 50-pin connector for IDE devices.
Devices attached to the 40-pin connectors obtain power through a separate connector. The 40-pin
connector is shown in the illustration below followed by the connector’s pinout.
Figure 5–1. 40-Pin IDE Connector.
Table 5–5. 40-Pin IDE Connector Pinout
Table 5-5.
40-Pin IDE Connector Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NOTES:
Signal
RESETGND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
--
Description
Reset
Ground
Data Bit <7>
Data Bit <8>
Data Bit <6>
Data Bit <9>
Data Bit <5>
Data Bit <10>
Data Bit <4>
Data Bit <11>
Data Bit <3>
Data Bit <12>
Data Bit <2>
Data Bit <13>
Data Bit <1>
Data Bit <14>
Data Bit <0>
Data Bit <15>
Ground
Key
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal
DRQ
GND
IOWGND
IORGND
IORDY
CSEL
DAKGND
IRQn
IO16DA1
DSKPDIAG
DA0
DA2
CS0CS1HDACTIVEGND
Description
DMA Request
Ground
I/O Write
Ground
I/O Read
Ground
I/O Channel Ready
Cable Select
DMA Acknowledge
Ground
Interrupt Request [1]
16-bit I/O
Address 1
Pass Diagnostics
Address 0
Address 2
Chip Select
Chip Select
Drive Active (front panel LED) [2]
Ground
[1] Primary connector wired to IRQ14, secondary connector wired to IRQ15.
[2] Pin 39 is used for spindle sync and drive activity (becomes SPSYNC/DACT-)
when synchronous drive are connected.
5-8
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
The 50-pin connector is intended for a CD-ROM drive that operates as a slave on the secondary
IDE interface. This interface includes power and audio signals. The 50-pin connector is
illustrated below followed by the pinout.
P2
P50
P1
P49
Figure 5–1. 50-Pin IDE Connector.
Table 5–6. 40-Pin IDE Connector Pinout
Table 5-5.
50-Pin IDE Connector Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NOTES:
Signal
RESDRVGND
SHD07
SHD08
SHD06
SHD09
SHD05
SHD10
SHD04
SHD11
SHD03
SHD12
SHD02
SHD13
SHD01
SHD14
SHD00
SHD15
GND
-DRQ
GND
IOWGND
IOR-
Description
Reset
Ground
Data Bit <7>
Data Bit <8>
Data Bit <6>
Data Bit <9>
Data Bit <5>
Data Bit <10>
Data Bit <4>
Data Bit <11>
Data Bit <3>
Data Bit <12>
Data Bit <2>
Data Bit <13>
Data Bit <1>
Data Bit <14>
Data Bit <0>
Data Bit <15>
Ground
(Key Space)
DMA Request
Ground
I/O Write
Ground
I/O Read
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal
GND
CHRDY
ALE
DAKGND
IRQ
IO16A1
PDIAGA0
A2
CS1FXCS3FXDASFGND
AUD L
AUD R
AUD R RTN
AUD L RTN
+5 VDC
+5 VDC
+5 VDC
+5 VDC
+5 VDC
+5 VDC
Description
Ground
I/O Channel Ready
Cable Select [1]
DMA Acknowledge
Ground
Interrupt Request [1]
16-bit I/O
Address 1
Pass Diagnostics
Address 0
Address 2
Chip Select
Chip Select
Drive Active
Ground
Left Channel Audio
Right Channel Audio
Right Channel Audio Return
Left Channel Audio Return
Motor Power
Motor Power
Motor Power
Motor Power
Log Power
Log Power
[1] Pin is left floating to make CD-ROM always slave.
Compaq Deskpro 4000N and 4000S Personal Computers 5-9
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.3
DISKETTE DRIVE INTERFACE
The diskette drive interface supports up to two diskette drives through a standard 34-pin diskette
drive connector. All Deskpro 4000S models include a 3.5 inch 1.44-MB diskette drive installed
as drive A. There is no physical provision for a second drive (B).
The diskette drive interface function is integrated into the 87307 I/O controller component. The
internal logic of the I/O controller is software-compatible with standard 82077-type logic. The
diskette drive controller has three operational phases in the following order:
♦
♦
♦
Command phase - The controller receives the command from the system.
Execution phase - The controller carries out the command.
Results phase - Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the
parameters of the command. The Main Status register (3F4h/374h) provides data flow control
for the diskette drive controller and must be polled between each byte transfer during the
Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2
and DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as
the Idle phase.
5-10 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
5.3.1
DISKETTE DRIVE PROGRAMMING
5.3.1.1 Diskette Drive Interface Configuration
The diskette drive controller must be configured for a specific address and also must be enabled
before it can be used. Address selection and enabling of the diskette drive interface are affected
by firmware through the PnP configuration registers of the 87307 I/O controller.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). The diskette drive I/F is initiated by firmware selecting logical device 3 of the 87307. This
is accomplished by the following sequence:
1.
2.
3.
4.
Write 07h to I/O register 15Ch.
Write 03h to I/O register 15Dh (this selects the diskette drive I/F).
Write 30h to I/O register 15Ch.
Write 01h to I/O register 15Dh (this activates the interface).
The diskette drive I/F configuration registers are listed in the following table:
Table 5–7. Diskette Drive Controller Configuration Registers
Table 5-6.
Diskette Drive Interface Configuration Registers
Index
Address
30h
31h
60h
61h
70h
71h
74h
75h
F0h
F1h
Function
Activate
I/O Range Check
Base Address MSB
Base Address LSB
Interrupt Select
Interrupt Type
DMA Channel Select
Report DMA Assignment
Configuration Data
Drive ID
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
Reset
Value
01h
00h
03h
F0h
06h
03h
02h
04h
---
Compaq Deskpro 4000N and 4000S Personal Computers 5-11
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.3.1.2 Diskette Drive Interface Control
The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette
drive interface can be controlled by software through I/O-mapped registers listed in Table 5-7.
Table 5–8. Diskette Drive Controller Registers
Table 5-7.
Diskette Drive Interface Control Registers
Primary
Address
3F1h
3F2h
3F4h
3F5h
3F7h
Alternate
Address
371h
372h
374h
375h
377h
Register
Media ID
Drive Control
Main Status
Data
Drive Status
Data Transfer Rate
R/W
R
W
R
R/W
R
W
The base address (3F1h or 371h) and enabling of the diskette drive controller is selected through
the Function Enable Register (FER, addr. 399.00h) of the 87307 I/O controller. Address selection
and enabling is automatically done by the BIOS during POST but can also be accomplished with
the Setup utility and other software.
The following paragraphs describe the diskette drive interface control registers.
Media ID Register, I/O Port 3F1h/371h (Read Only)
Bit
7..5
4..2
1,0
Function
Media Type:
xx1 = Invalid
000 = 5.25 inch drive
010 = 2.88 MB (3.5 inch drive)
100 = 1.44 MB (3.5 inch drive)
110 = 720 KB (3.5 inch drive)
Reserved
Tape Select:
00 = None
10 = Drive 2
01 = Drive 1
11 = Drive 3
Drive Control Register, I/O Port 3F2h/372h (Write Only)
Bit
7,6
5
4
3
2
1,0
Function
Reserved
Drive 2 Motor
0 = Off, 1 = On
Drive 1 Motor
0 = Off, 1 = On
Interrupt / DMA Enable
0 = Disabled, 1 = Enabled
Controller Enable
0 = Reset controller, 1 = Enable controller
Drive Select
00 = Drive 1
01 = Drive 2
10 = Reserved
11 = Tape drive
5-12 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
Main Status Register, I/O Port 3F4h/374h (Read Only)
Bit
7
6
5
4
3..0
Function
Request for Master. When set, indicates the controller is ready
to send or receive data from the CPU. Cleared immediately
after a byte transfer. Indicates interrupt pin status during nonDMA phase.
Data I/O Direction.
0 = Expecting a write
1 = Expecting a read
Non-DMA Execution. When set, indicates controller is in the
execution phase of a byte transfer in non-DMA mode.
Command In Progress. When set, indicates that first byte of
command phase has been received. Cleared when last byte in
result phase is read.
Drive Busy Indicators. Bit is set after the last byte of the
command phase of a seek or recalibrate command is given by
the corresponding drive:
<3>, Drive 3
<2>, Drive 2
<1>, Drive 1
<0>, Drive 0
Data Register, I/O Port 3F5h/375h
Data commands are written to, and data and status bytes are read from this register.
Data Transfer Rate Register, I/O Port 3F7h/377h (Write Only)
Bit
7
6
5
4..2
1,0
Function
Software Reset
Low Power Mode (if set)
Reserved
Write Precompensation Delay
000 = Default values for selected data rate (default)
Data Rate Select:
00 = 500 Kb/s
01 = 300 Kb/s
10 = 250 Kb/s
11 = 1 or 2 Mb/s (depending on TUP reg. Bit <1>)
Compaq Deskpro 4000N and 4000S Personal Computers 5-13
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.3.2
DISKETTE DRIVE CONNECTOR
This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-8 for the pinout)
for diskette drives. Drive power is supplied through a separate connector.
2
4
1
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33
Figure 5–2. 34-Pin Diskette Drive Connector.
Table 5–9. 34-Pin Diskette Drive Connector Pinout
Table 5-8.
34-Pin Diskette Drive Connector Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Signal
GND
LOW DEN--MEDIA IDGND
DRV 4 SELGND
INDEXGND
MTR 1 ONGND
DRV 2 SELGND
DRV 1 SELGND
MTR 2 ONGND
Description
Ground
Low density select
(KEY)
Media identification
Ground
Drive 4 select
Ground
Media index is detected
Ground
Activates drive motor
Ground
Drive 2 select
Ground
Drive 1 select
Ground
Activates drive motor
Ground
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal
DIRGND
STEPGND
WR DATAGND
WR ENABLEGND
TRK 00GND
WR PRTKGND
RD DATAGND
SIDE SELGND
DSK CHG-
5-14 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Description
Drive head direction control
Ground
Drive head track step control
Ground
Write data
Ground
Enable for WR DATAGround
Heads at track 00 indicator
Ground
Media write protect status
Ground
Data and clock read off disk
Ground
Head select (side 0 or 1)
Ground
Drive door opened indicator
Technical Reference Guide
5.4
SERIAL INTERFACES
The serial interfaces transmit and receive asynchronous serial data with external devices. The
serial interface function is provided by the 87307 I/O controller component, which integrates two
16550/16450-compatible UARTs. One UART(1) is dedicated to support DB-9 connector (A) on
the rear of the chassis while the second UART(2) can be configured to support the second DB-9
connector (B).
87307
UART1
(Log. Dev. 6)
DB-9 A (RS-232)
TX/RX/CNTRL
DB-9 B (RS-232)
TX/RX/CNTRL
UART2
(Log. Dev. 5)
Figure 5–3. Serial Interfaces Block Diagram
5.4.1
RS-232 INTERFACE
The DB-9 connector-based interface complies with EIA standard RS-232-C, which includes
modem control signals and supports baud rates up to 115.2 Kbps. The DB-9 connector is shown
in the following figure and the pinout of the connector is listed in Table 5-9.
Figure 5–4. Serial Interface Connector (Male DB-9 as viewed from rear of chassis)
Table 5–10. DB-9 Serial Connector Pinout
Table 5-9.
DB-9 Serial Connector Pinout
Pin
1
2
3
4
5
Signal
CD
RX Data
TX Data
DTR
GND
Description
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Ground
Pin
6
7
8
9
--
Signal
DSR
RTS
CTS
RI
--
Description
Data Set Ready
Request To Send
Clear To Send
Ring Indicator
--
Each DB-9 port is independently configurable as to it’s COMn (address) designation.
Compaq Deskpro 4000N and 4000S Personal Computers 5-15
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.4.2
SERIAL INTERFACE PROGRAMMING
5.4.2.1 Serial Interface Configuration
The serial interfaces must be configured for a specific address range (COM1, COM2, etc.) and
also must be activated before it can be used. Address selection and activation of the serial
interface are affected through the PnP configuration registers of the 87307 I/O controller.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). Each serial interface is initiated by firmware selecting logical device 5 or 6 of the 87307.
This is accomplished by the following sequence:
1. Write 07h to I/O register 15Ch.
2. Write 05h or 06h to I/O register 15Dh (for selecting UART2 or UART1).
3. Write 30h to I/O register 15Ch.
4. Write 01h to I/O register 15Dh (this activates the interface).
The serial interface configuration registers are listed in the following table:
Table 5–11. Serial Interface Configuration Registers
Table 5-11.
Serial Interface Configuration Registers
Index
Address
Function
30h
Activate
31h
I/O Range Check
60h
Base Address MSB
61h
Base Address LSB
70h
Interrupt Select
71h
Interrupt Type
74h
DMA Channel Select
75h
Report DMA Assignment
F0h
Configuration Data
NOTES:
[1] Device 5 (UART2) / Device 6 (UART1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
5-16 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Reset
Value [1]
00h / 00h
00h / 00h
02h / 03h
F8h / F8h
03h / 04h
03h / 03h
04h / 04h
04h / 04h
--
Technical Reference Guide
5.4.2.2 Serial Interface Control
The BIOS function INT 14 provides basic control of the serial interface. The serial interface can
be controlled by software through the registers listed in Table 5-12.
Table 5–12. Serial Interface Control Registers
Table 5-12.
Serial Interface Control Registers
Address
Register
Base
Receive Buffer / Transmit Holding [1]
Base, Base + 1
Baud Rate Divisor Latch [2]
Base + 1
Interrupt Enable
Base + 2
Interrupt ID
Base + 3
Line Control
Base + 4
Modem Control
Base + 5
Line Status
Base + 6
Modem Status
Base + 7
Scratch Pad
NOTES:
Base Address:
COM1 = 3F8h
COM2 = 2F8h
R/W
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
[1] This register holds receive data when read from and transmit data when written to.
[2] When bit <7> of the Line Control register is set (1), writing to 3F8h and 3F9h
programs the divisor rate for the baud rate generator.
Receive Buffer / Transmit Holding Register, I/O Port 3F8h/2F8h
When read by the CPU, this byte contains receive data. When written to by the CPU, the byte
contains data to be transmitted.
Compaq Deskpro 4000N and 4000S Personal Computers 5-17
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Chapter 5 Input/Output Interfaces
Baud Rate Divisor Latch Register, I/O Port 3F8h, 3F9h/2F8, 2F9h
When bit <7> of the Line Control register is set (1), a write to this pair of locations loads the
decimal value used to divide the 1.8462-MHz clock to create the desired baud rate for serial
transmission. The possible baud rates are shown as follows:
Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
Decimal Divisor
2304
1536
1047
857
768
384
192
96
64
58
Baud Rate
2400
3600
4800
7200
9600
19200
38400
57600
115200
Decimal Divisor
48
32
24
16
12
6
3
2
1
Divisor = 1846200 / (Desired baud rate X 16)
Interrupt Enable Register, I/O Port 3F9h/2F9h
Bits <3..0> of this register are used for enabling interrupt sources. A set bit enables interrupt
generation by the associated source.
Bit
7..4
3
2
1
0
Function
Reserved
Modem Status Interrupt Enable (if set) (CTS, DSR, RI, CD)
Receiver Line Status Interrupt Enable (if set) (Overrun error,
parity error, framing error, break)
Transmitter Holding Register Empty Interrupt Enable (if set)
Baud Rate Divisor Interrupt Enable (if set)
Interrupt ID Register, I/O Port 3FAh/2FAh (Read Only)
This read-only register indicates the serial controller as the source of the interrupt (bit <0>) as
well as the reason (bits <3..1>) for the interrupt. Reading this register clears the interrupt and
sets bit <0>.
Bit
7,6
5,4
3..1
0
Function
FIFO Enable/Disable
0 = Disabled
1 = Enabled
Reserved
Interrupt Source:
000 = Modem status (lowest priority)
001 = Transmitter holding reg. Empty
010 = Received data available
011 = Receiver line status reg.
100,101 = Reserved
110 = Character time-out (highest priority)
111 = Reserved
Interrupt Pending (if cleared)
5-18 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
FIFO Control Register, I/O Port 3FAh/2FAh (Write Only)
This write-only register enables and clears the FIFOs and set the trigger level and DMA mode.
Bit
7,6
5..3
2
1
0
Function
Receiver Trigger Level
00 = 1 byte
10 = 8 bytes
01 = 4 bytes
11 = 14 bytes
Reserved
Transmit FIFO Reset (if set)
Receive FIFO Reset (if set)
FIFOs Enable/Disable
0 = Disable TX/RX FIFOs, 1 = Enable TX/RX FIFOs
Line Control Register, I/O Port 3FBh/2FBh
This register specifies the data transmission format.
Bit
7
6
5
4
3
2
1,0
Function
RX Buffer / TX Holding Reg. And Divisor Rate Reg. Access
0 = RX buffer, TX holding reg., and Interrupt En. Reg. Are accessable.
1 = Divisor Latch reg. is accessable.
Break Control (forces SOUT signal low if set)
Stick Parity. If set, even parity bit is logic 0, odd parity bit is logic 1
Parity Type
0 = Odd, 1 = Even
Parity Enable:
0 = Disabled,
1 = Enabled
Stop Bit:
0 = 1 stop bit,
1 = 2 stop bits
Word Size:
00 = 5 bits
10 = 7 bits
01 = 6 bits
11 = 8 bits
Modem Control Register, I/O Port 3FCh/2FCh
This register controls the modem signal lines
Bit
7..5
4
3
2
1
0
Function
Reserved
Internal Loopback Enabled (if set)
Serial Interface Interrupts Enabled (if set)
Reserved
RTS Signal Active (if set)
DTR Signal Active (if set)
Compaq Deskpro 4000N and 4000S Personal Computers 5-19
First Edition - September 1997
Chapter 5 Input/Output Interfaces
Line Status Register, I/O Port 3FDh/2FDh (Read Only)
This register contains the status of the current data transfer. Bits <2..0> are cleared when read.
Bit
7
6
5
4
3
2
1
0
Function
Parity Error, Framing Error, or Break Cond. Exists (if set)
TX Holding Reg. and Transmitter Shift Reg. Are Empty (if set)
TX Holding Reg. Is Empty (if set)
Break Interrupt Has Occurred (if set)
Framing Error Has Occurred (if set
Parity Error Has Occurred (if set)
Overrun Error Has Occurred (if set)
Data Register Ready To Be Read (if set)
Modem Status Register, I/O Port 3FEh/2FEh (Read Only)
This register contains the status of the modem signal lines. A set bit indicates that the associated
signal is active.
Bit
7
6
5
4
3
2
1
0
Function
DCD- Active
RI- Active
DSR Active
CTS Active
DCD- Changed Since Last Read
RI- Changed From Low to High Since Last Read
DSR- Has Changed State Since Last Read
CTS- Has Changed State Since Last Read
Scratch Pad Register, I/O Port 3FFh/2FFh
This register is not used in this system.
5-20 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
5.5
PARALLEL INTERFACE
The parallel interface provides connection to a peripheral device that has a compatible interface,
the most common being a printer. The parallel interface function is integrated into the 87307 I/O
controller component and provides bi-directional 8-bit parallel data transfers with a peripheral
device. The parallel interface supports three modes of operation:
♦
♦
♦
Standard Parallel Port (SPP) mode
Enhanced Parallel Port (EPP) mode
Extended Capabilities Port (ECP) mode
These three modes provide complete support as specified for an IEEE 1284 parallel port.
5.5.1
STANDARD PARALLEL PORT MODE
The Standard Parallel Port (SPP) mode uses software-based protocol and includes two sub-modes
of operation, compatible and extended, both of which can provide data transfers up to 150 KB/s.
In the compatible mode, CPU write data is simply presented on the eight data lines. A CPU read
of the parallel port yields the last data byte that was written.
The following steps define the standard procedure for communicating with a printing device:
1.
2.
3.
The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals
are indicated as being active, the system either waits for a status change or generates an error
message.
The system sends a byte of data to the Printer Data register, then pulses the printer STROBE
signal (through the Printer Control register) for at least 500 ns.
The system then monitors the Printer Status register for acknowledgment of the data byte
before sending the next byte.
In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output
data while allowing a CPU read to fetch data present on the data lines, thereby providing bidirectional parallel transfers to occur.
The SPP mode uses three registers for operation: the Data register (DTR), the Status register
(STR) and the Control register (CTR). Address decoding in SPP mode includes address lines A0
and A1.
Compaq Deskpro 4000N and 4000S Personal Computers 5-21
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.5.2
ENHANCED PARALLEL PORT MODE
In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due
to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7
and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a
negotiation phase is entered to detect whether or not the connected peripheral is compatible with
EPP mode. If compatible, then EPP mode can be used. In EPP mode, system timing is closely
coupled to EPP timing. A watchdog timer is used to prevent system lockup.
Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with
the parallel interface. Address decoding includes address lines A0, A1, and A2.
5.5.3
EXTENDED CAPABILITIES PORT MODE
The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based
design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as
well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode
includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or
programmed I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is
entered to detect whether or not the connected peripheral is compatible with ECP mode. If
compatible, then ECP mode can be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO
is cleared and not used, and DMA and RLE are inhibited.
5-22 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
5.5.4
PARALLEL INTERFACE PROGRAMMING
5.5.4.1 Parallel Interface Configuration
The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and
also must be enabled before it can be used. When configured for EPP or ECP mode, additional
considerations must be taken into account. Address selection, enabling, and EPP/ECP mode
parameters of the parallel interface are affected through the PnP configuration registers of the
87307 I/O controller. Address selection and enabling are automatically done by the BIOS during
POST but can also be accomplished with the Setup utility and other software.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). The parallel interface is initiated by firmware selecting logical device 4 of the 87307. This
is accomplished by the following sequence:
1. Write 07h to I/O register 15Ch.
2. Write 04h to I/O register 15Dh (for selecting the parallel interface).
3. Write 30h to I/O register 15Ch.
4. Write 01h to I/O register 15Dh (this activates the interface).
The parallel interface configuration registers are listed in the following table:
Table 5–13. Parallel Interface Configuration Registers
Table 5-13.
Parallel Interface Configuration Registers
Index
Address
30h
31h
60h
61h
70h
71h
74h
75h
F0h
Function
Activate
I/O Range Check
Base Address MSB
Base Address LSB
Interrupt Select
Interrupt Type
DMA Channel Select
Report DMA Assignment
Configuration Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
Reset
Value
01h
00h
02h
78h
07h
00h
04h
04h
--
Compaq Deskpro 4000N and 4000S Personal Computers 5-23
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.5.4.2 Parallel Interface Control
The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions
such as initialization, character printing, and printer status are provide by subfunctions of INT
17. The parallel interface is controllable by software through a set of I/O mapped registers. The
number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-14
lists the parallel registers and associated functions based on mode.
Table 5–14. Parallel Interface Control Registers
Table 5-14.
Parallel Interface Control Registers
Register
Data
Status
Control
Address
Data Port 0
Data Port 1
Data Port 2
Data Port 3
Parallel Data FIFO
ECP Data FIFO
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
I/O
Address
Base
Base + 1h
Base + 2h
Base + 3h
Base + 4h
Base + 5h
Base + 6h
Base + 7h
Base + 400h
Base + 400h
Base + 400h
Base + 400h
Base + 401h
Base + 402h
SPP Mode
Ports
LPT1,2,3
LPT1,2,3
LPT1,2,3
------------
EPP Mode
Ports
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
-------
ECP Mode
Ports
LPT1,2,3
LPT1,2,3
LPT1,2,3
-----LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
Base Address:
LPT1 = 378h
LPT2 = 278h
LPT3 = 3BCh
The following paragraphs describe the individual registers. Note that only the LPT1-based
addresses are given in these descriptions.
Data Register, I/O Port 378h
Data written to this register is presented to the data lines D0-D7. A read of this register when in
SPP-compatible mode yields the last byte written. A read while in SPP-extended or ECP mode
yields the status of data lines D0-D7 (i.e., receive data).
In ECP mode in the forward (output) direction, a write to this location places a tagged command
byte into the FIFO and reads have no effect.
5-24 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
Status Register, I/O Port 379h, Read Only
This register contains the current printer status. Reading this register clears the interrupt
condition of the parallel port.
Bit
7
6
5
4
3
2
1
0
Function
Printer Busy (if 0)
Printer Acknowledgment Of Data Byte (if 0)
Printer Out Of Paper (if 1)
Printer Selected/Online (if 1)
Printer Error (if 0)
Reserved
EPP Interrupt Occurred (if set while in EPP mode)
EPP Timeout Occurred (if set while in EPP mode)
Control Register, I/O Port 37Ah
This register provides the printer control functions.
Bit
7,6
5
4
3
2
1
0
Function
Reserved
Direction Control for PS/2 and ECP Modes:
0 = Forward. Drivers enabled. Port writes to peripheral (default)
1 = Backward. Tristates drivers and data is read from peripheral
Acknowledge Interrupt Enable
0 = Disable ACK interrupt
1 = Enable interrupt on rising edge of ACK
Printer Select (if 0)
Printer Initialize (if 1)
Printer Auto Line Feed (if 0)
Printer Strobe (if 0)
Address Register, I/O Port 37Bh (EPP Mode Only)
This register is used for selecting the EPP register to be accessed.
Data Port Registers 0-3, I/O Ports 37C-Fh (EPP Mode Only)
These registers are used for reading/writing data. Port 0 is used for all transfers. Ports 1-3 are
used for transferring the additional bytes of 16- or 32-bit transfers through port 0.
Compaq Deskpro 4000N and 4000S Personal Computers 5-25
First Edition - September 1997
Chapter 5 Input/Output Interfaces
FIFO Register, I/O Port 7F8h (ECP Mode Only)
While in ECP/forward mode, this location is used for filling the 16-byte FIFO with data bytes.
Reads have no effect (except when used in Test mode). While in ECP/backward mode, reads
yield data bytes from the FIFO.
Configuration Register A, I/O Port 7F8h (ECP Mode Only)
A read of this location yields 10h, while writes have no effect.
Configuration Register B, I/O Port 7F9h (ECP Mode, Read Only)
A read of this location yields the status defined as follows:
Bit
7
6
5,4
3
2..0
Function
Reserved (always 0)
Status of Selected IRQn.
Selected IRQ Indicator:
00 = IRQ7
11 = IRQ5
All other values invalid.
Reserved (always 1)
Reserved (always 000)
Extended Control Register B, I/O Port 7FAh (ECP ModeOnly)
This register defines the ECP mode functions.
Bit
7..5
4
3
2
1
0
Function
ECP Submode Select:
000 = Standard forward mode (37Ah <5> forced to 0). Writes are
controlled by software and FIFO is reset.
001 = PS/2 mode. Reads and writes are software controlled and
FIFO is reset.
010 = Parallel Port FIFO forward mode (37Ah <5> forced to 0). Writes are
hardware controlled.
011 = ECP FIFO mode. Direction determined by 37Ah, <5>. Reads and
writes are hardware controlled.
ECP Interrupt Mask:
0 = Interrupt is generated on ERR- assertion.
1 = Interrupt is inhibited.
ECP DMA Enable/Disable.
0 = Disabled
1 = Enabled
ECP Interrupt Generation with DMA
0 = Enabled
1 = Disabled
FIFO Full Status (Read Only)
0 = Not full (at least 1 empty byte
1 = Full
FIFO Empty Status (Read Only)
0 = Not empty (contains at least 1 byte)
1 = Empty
5-26 Compaq Deskpro 4000N and 4000S Personal Computers
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Technical Reference Guide
5.5.5
PARALLEL INTERFACE CONNECTOR
Figure 5-4 and Table 5-15 show the connector and pinout of the parallel inrteface connector.
Figure 5–5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis)
Table 5–15. DB-25 Parallel Connector Pinout
Table 5-15.
DB-25 Parallel Connector Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Signal
STBD0
D1
D2
D3
D4
D5
D6
D7
ACKBSY
PE
SLCT
Description
Strobe
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Acknowledge
Busy
Paper End
Select
Pin
14
15
16
17
18
19
20
21
22
23
24
25
--
Signal
LFERRINITSLCTINGND
GND
GND
GND
GND
GND
GND
GND
--
Description
Line Feed
Error
Initialize Paper
Select In
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
--
Compaq Deskpro 4000N and 4000S Personal Computers 5-27
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.6
KEYBOARD/POINTING DEVICE INTERFACE
The keyboard/pointing device interface provides the connection of an enhanced keyboard and a
mouse using PS/2-type connections. The keyboard/pointing device interface function is provided
by the 87307 I/O controller component, which integrates 8042-compatible keyboard controller
logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing
device using bi-directional serial data transfers. The 8042 handles scan code translation and
password lock protection for the keyboard as well as communications with the pointing device.
This section describes the interface itself. The keyboard is discussed in the Appendix C.
5.6.1
KEYBOARD INTERFACE OPERATION
The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1
and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in
Appendix C). This section describes Mode 2 (the default) mode of operation.
Communication between the keyboard and the 8042 consists of commands (originated by either
the keyboard or the 8042) and scan codes from the keyboard. A command can request an action
or indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.
The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a
command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the
keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is
ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to
respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-5). An odd parity bit is
sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line
low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line
is pulled low to inhibit the keyboard and allow it to process the data.
Start
Bit
0
D0
(LSb)
1
D1
D2
D3
D4
D5
D6
0
1
1
0
1
1
D7
(MSb)
1
Parity
1
Stop
Bit
0
Data
Clock
Th
Tcy
Tcl Tch
Parameter
Minimum
Tcy (Cycle Time)
0 us
Tcl (Clock Low)
25 us
Tch (clock High)
25 us
Th (Data Hold)
0 us
Tss (Stop Bit Setup) 8 us
Tsh (Stop Bit Hold)
15 us
Tss
Maximum
80 us
35 us
45 us
25 us
20 us
25 us
Figure 5–6. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram
5-28 Compaq Deskpro 4000N and 4000S Personal Computers
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Tsh
Technical Reference Guide
Control of the data and clock signals is shared by the 8042and the keyboard depending on the
originator of the transferred data. Note that the clock signal is always generated by the keyboard.
After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a
parity error or timeout occurs, a Resend command is sent to the 8042.
Table 5-16 lists and describes commands that can be issued by the 8042 to the keyboard.
Table 5–16. 8042-To-Keyboard Commands
Table 5-16.
8042-To-Keyboard Commands
Command
Set/Reset Status Indicators
Echo
Invalid Command
Select Alternate Scan Codes
Value
EDh
EEh
EFh/F1h
F0h
Read ID
F2h
Set Typematic Rate/Display
F3h
Enable
F4h
Default Disable
F5h
Set Default
F6h
Set Keys - Typematic
Set Keys - Make/Brake
Set Keys - Make
Set Keys - Typematic/Make/Brake
Set Type Key - Typematic
Set Type Key - Make/Brake
Set Type Key - Make
Resend
Reset
Note:
[1] Used in Mode 3 only.
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Description
Enables LED indicators. Value EDh is followed by an option
byte that specifies the indicator as follows:
Bits <7..3> not used
Bit <2>, Caps Lock (0 = off, 1 = on)
Bit <1>, NUM Lock (0 = off, 1 = on)
Bit <0>, Scroll Lock (0 = off, 1 = on)
Keyboard returns EEh when previously enabled.
These commands are not acknowledged.
Instructs the keyboard to select another set of scan codes
and sends an option byte after ACK is received:
01h = Mode 1
02h = Mode 2
03h = Mode 3
Instructs the keyboard to stop scanning and return two
keyboard ID bytes.
Instructs the keyboard to change typematic rate and delay
to specified values:
Bit <7>, Reserved - 0
Bits <6,5>, Delay Time
00 = 250 ms
01 = 500 ms
10 = 750 ms
11 = 1000 ms
Bits <4..0>, Transmission Rate:
00000 = 30.0 ms
00001 = 26.6 ms
00010 = 24.0 ms
00011 = 21.8 ms
:
11111 = 2.0 ms
Instructs keyboard to clear output buffer and last typematic
key and begin key scanning.
Resets keyboard to power-on default state and halts
scanning pending next 8042 command.
Resets keyboard to power-on default state and enable
scanning.
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and prepare to receive key ID. [1]
Clears keyboard buffer and prepare to receive key ID. [1]
Clears keyboard buffer and prepare to receive key ID. [1]
8042 detected error in keyboard transmission.
Resets program, runs keyboard BAT, defaults to Mode 2.
Compaq Deskpro 4000N and 4000S Personal Computers 5-29
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.6.2
POINTING DEVICE INTERFACE OPERATION
The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical
to the keyboard connector both physically and electrically. The operation of the interface (clock
and data signal control) is the same as for the keyboard. The pointing device interface uses the
IRQ12 interrupt.
5.6.3
KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING
5.6.3.1 8042 Configuration
The keyboard/pointing device interface must be enabled and configured for a particular speed
before it can be used. Enabling and speed parameters of the 8042 logic are affected through the
PnP configuration registers of the 87307 I/O controller. Enabling and speed control are
automatically set by the BIOS during POST but can also be accomplished with the Setup utility
and other software.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). The keyboard and mouse interfaces are initiated by firmware selecting logical device 0 or
1 of the 87307. This is accomplished by the following sequence:
1. Write 07h to I/O register 15Ch.
2. Write 00h or 01h to I/O register 15Dh (for selecting the keyboard or mouse interface).
3. Write 30h to I/O register 15Ch.
4. Write 01h to I/O register 15Dh (this activates the interface).
The parallel interface configuration registers are listed in the following table:
Table 5–17. Keyboard/Mouse Interface Configuration Registers
Table 5-17.
Keyboard/Mouse Interface Configuration Registers
Index
Address
Function
30h
Activate
31h
I/O Range Check [1]
60h
Base Address MSB [1]
61h
Base Address LSB [1]
62h
Command Base Address MSB [1]
63h
Command Base Address LSB [1]
70h
Interrupt Select
71h
Interrupt Type
74h
DMA Channel Select
75h
Report DMA Assignment
F0h
Configuration Data [1]
NOTES:
[1] Keyboard I/F only.
[2] Keyboard I/F / Mouse I/F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
5-30 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Reset
Value [2]
01h / 00h
00h / na
02h / na
78h / na
00h / na
00h / na
01h / 0Ch
01h / 01h
04h / 04h
04h / 04h
-- / na
Technical Reference Guide
5.6.3.2 8042 Control
The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Subfunctions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the
keyboard’s scan codes into ASCII codes). The keyboard/pointing device interface is accessed by
the CPU through I/O mapped ports 60h and 64h, which provide the following functions:
♦
♦
♦
♦
Output buffer reads
Input buffer writes
Status reads
Command writes
Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction
for a write. Prior to reading data from port 60h, the “Output Buffer Full” status bit (64h, bit <0>)
should be checked to ensure data is available. Likewise, before writing a command or data, the
“Input Buffer Empty” status bit (64h, bit <1>) should also be checked to ensure space is
available.
I/O Port 60h
I/O port 60h is used for accessing the input and output buffers. This register is used to send and
receive data from the keyboard and the pointing device. This register is also used to send the
second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for
commands that require a response.
A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data
that has been received from the keyboard and is to be transferred to the system.
A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of
the Status register to DATA. The input buffer is used for transferring data from the system to the
keyboard. All data written to this port by the CPU will be transferred to the keyboard except
bytes that follow a multibyte command that was written to 64h
I/O Port 64h
I/O port 64h is used for reading the status register and for writing commands. A read of 64h by
the CPU will yield the status byte defined as follows:
Bit
7..4
3
2
1
0
Function
General Purpose Flags.
CMD/DATA Flag (reflects the state of A2 during a CPU write).
0 = Data
1 = Command
General Purpose Flag.
Input Buffer Full. Set (to 1) upon a CPU write. Cleared by
IN A, DBB instruction.
Output Buffer Full (if set). Cleared by a CPU read of the buffer.
A CPU write to I/O port 64h places a command value into the input buffer and sets the
CMD/DATA bit of the status register (bit <3>) to CMD.
Compaq Deskpro 4000N and 4000S Personal Computers 5-31
First Edition - September 1997
Chapter 5 Input/Output Interfaces
Table 5-18 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for
gaining the attention of the CPU.
Table 5–18. CPU Commands To The 8042
Table 5-18.
CPU Commands To The 8042
Value
20h
60h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ADh
AEh
Command Description
Put current command byte in port 60h.
Load new command byte. This is a two-byte operation described as follows:
1. Write 60h to port 64h.
2. Write the command byte to port 60h as follows:
Bit <7> Reserved
<6> Keyboard Code Conversion
0 = Do not convert codes
1 = Convert codes to 9-bit 8088/8086-compatible format
Bit <5> Pointing Device Enable
0 = Enable pointing device
1 = Disable pointing device
Bit <4> Keyboard Enable
0 = Enable keyboard
1 = Disable keyboard
Bit <3> Reserved
Bit <2> System Flag
0 = Cold boot
1 = CPU reset (exit from protected mode)
Bit <1> Pointing Device Interrupt Enable
0 = Disable interrupt
1 = Enable interrupt
Bit <0> Keyboard Interrupt Enable
0 = Disable interrupt
1 = Enable interrupt
Test password installed. Tests whether or not a password is installed in the 8042:
If FAh is returned, password is installed.
If F1h is returned, no password is installed.
Load password. This multi-byte operation places a password in the 8042 using the following manner:
1. Write A5h to port 64h.
2. Write each character of the password in 9-bit scan code (translated) format to port 60h.
3. Write 00h to port 60h.
Enable security. This command places the 8042 in password lock mode following the A5h command.
The correct password must then be entered before further communication with the 8042 is allowed.
Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock line
of the pointing device interface low.
Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the clock
line of the pointing device interface.
Test the clock and data lines of the pointing device interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and places
55h into the output buffer.
Test the clock and data lines of the keyboard interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
Disable keyboard command (sets bit <4> of the 8042 command byte).
Enable keyboard command (clears bit <4> of the 8042 command byte).
Continued
5-32 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Technical Reference Guide
Table 5-18. CPU Commands To The 8042 (Continued)
Value
C0h
C2h
C3h
D0h
D1h
D2h
D3h
D4h
E0h
F0hFFh
Command Description
Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port
to the output buffer so that they can be read at port 60h. The contents are as follows:
Bit <7> Password Enable:
0 = Disabled
1 = Enabled
Bit <6> External Boot Enable:
0 = Enabled
1 = Disabled
Bit <5> Setup Enable:
0 = Enabled
1 = Disabled
Bit <4> VGA Enable:
0 = Enabled
1 = Disabled
Bit <3> Diskette Writes:
0 = Disabled
1 = Enabled
Bit <2> Reserved
Bit <1> Pointing Device Data Input Line
Bit <0> Keyboard Data Input Line
Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the
upper half of the status byte on a continous basis until another command is received.
Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the lower
half of the status byte on a continous basis until another command is received.
Read output port. This command directs the 8042 to transfer the contents of the output port to the
output buffer so that they can be read at port 60h. The contents are as follows:
Bit <7> Keyboard data stream
Bit <6> Keyboard clock
Bit <5> IRQ12 (pointing device interrupt)
Bit <4> IRQ1 (keyboard interrupt)
Bit <3> Pointing device clock
Bit <2> Pointing device data
Bit <1> A20 Control:
0 = Hold A20 low
1 = Enable A20
Bit <0> Reset Line Status;
0 = Inactive
1 = Active
Write output port. This command directs the 8042 to place the next byte written to port 60h into the
output port (only bit <1> can be changed).
Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h as if
it originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt (IRQ1) is
generated if enabled.
Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port 60h
as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.
Write to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing device.
Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output buffer.
Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don’t pulse).
Note that pulsing bit <0> will reset the system.
Compaq Deskpro 4000N and 4000S Personal Computers 5-33
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.6.4
KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR
There are separate connectors for the keyboard and pointing device. Both connectors are identical
both physically and electrically. Figure 5-6 and Table 5-19 show the connector and pinout of the
keyboard/pointing device interface connectors.
Figure 5–7. Keyboard or Pointing Device Interface Connector
(as viewed from rear of chassis)
Table 5–19. Keyboard/Pointing Device Connector Pinout
Table 5-19.
Keyboard/Pointing Device Connector Pinout
Pin
1
2
3
Signal
DATA
NC
GND
Description
Data
Not Connected
Ground
Pin
4
5
6
Signal
+ 5 VDC
CLK
NC
5-34 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Description
Power
Clock
Not Connected
Technical Reference Guide
5.7
ETHERNET INTERFACE
The system board integrates an Ethernet interface that supports both 10 and 100 Mbps Ethernet
communications using IEEE 802.3 (ISO 8802-3) protocol. Two connection options are available;
an RJ-45 jack for twisted-pair Ethernet (TPE) systems (10BaseT and 100BaseTX) and an AUI
connector for a direct 10BaseT connection or to a 10Base2 connection through and AUI-to-BNC
adapter. The Ethernet interface (Figure 5-9) is based on the Texas Instruments TLAN3.1
component, which operates off the PCI bus and features auto-switching between 10 and 100 Mb/s
interfaces.
AUI Connector
TX/RX
PCI Bus
INT Cntlr.
PINTA& Power
Control
Logic
TLAN3.1
Ethernet
Controller
TX/RX
Filter
+12 VDC
TX/RX,
Cntrl
RJ-45 Connector
PHY
TX/RX
Filter
TX/RX
Link
Active
(Yellow) (Green)
Figure 5–8. Ethernet Interface Block Diagram
The RJ-45 connctor is the default port, which is the required connection if Remote Wakeup
operation or 10/100 autosensing is desired. Note also that the LED indicators are operational
only for the RJ-45 interface. The LEDs provide the following indications:
Link LED (yellow) - Indicates reception of link pulses in 10 Mbs mode, indicates scrambler lock
and valid idle code reception during 100 Mbs mode.
Active LED (green) - Indicates network activity.
The network interface controller supports Remote Wakeup using the Magic Packet method of
waking up a system unit that is powered down (the NIC logic is powered by +5 AUX, which is
active as long as the system is receiving AC line voltage). With Remote Wakeup feature enabled,
a received Magic Packet results in the PINTA- signal being asserted (low) and routed to power
control logic, which in turn activates the power supply (refer to Chapter 7, “Power and Signal
Distribution” for a discussion of the power control logic).
Compaq Deskpro 4000N and 4000S Personal Computers 5-35
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.7.1
NIC CONFIGURATION/CONTROL
The NIC is a PCI device and configured through PCI configuration space registers. The NIC is
controlled through I/O registers mapped in the 300h-30Fh range.
5.7.2
NIC CONNECTORS
The network interface provides two choices of connection to a LAN system as shown in the
following figures.
1
15
Pin
1
2
3
4
5
6
7
8
Description
Ground
Control In
TX Data
Ground
RX Data
Ground
n/c
Ground
Figure 5–9. Ethernet AUI Connector (DB-15, viewed from rear)
Pin
1
2
3
6
8 7 6 5 4 3 2 1
Figure 5–10. Ethernet RJ-45 Connector
5-36 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Description
Transmit
Transmit Low
Receive
Receive Low
Pin
9
10
11
12
13
14
15
Description
Control In RTN
TX Data RTN
Ground
RX Data RTN
+12 VDC
Ground
n/c
Technical Reference Guide
5.8
UNIVERSAL SERIAL BUS INTERFACE
The Universal Serial Bus (USB) interface provides up to 12 Mb/s data transfers between the host
system and peripherals designed with a compatible USB interface. This high speed interface
supports hot-plugging of compatible devices, making possible system configuration changes
without powering down or even rebooting systems. The USB interface supports both
isochronous and asynchronous communications, and integrates a 5 VDC power bus that can
eliminate the need for external powering of small remote peripherals.
5.8.1
USB CONFIGURATION
The USB interface functions as a PCI device (20) within the 82586 component (function 2) and
is configured using PCI Configuration Registers as listed in Table 5-20.
Table 5–20. USB Interface Configuration Registers
Table 5-20.
USB PCI Configuration Registers (82586, Function 2)
PCI Config.
Addr.
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h
0Ah
0Bh
0Dh
0Eh
24h-27h
3Ch
3Dh
40h
41h
60h
C0-C1h
Register
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming I/F
Sub Class Code
Base Class Code
Latency Timer
Header Type
I/O Space Base Address
Interrupt Line
Interrupt Pin
Miscellaneous Control 1
Miscellaneous Control 2
Serial Base Release Number
Legacy Support Reg. (compliant w/UHCI v1.1)
Reset
Value
1106h
3038h
0000h
0280h
00h
00h
03h
0Ch
00h
80h
All 0’s
00h
04h
00h
2000h
Compaq Deskpro 4000N and 4000S Personal Computers 5-37
First Edition - September 1997
Chapter 5 Input/Output Interfaces
5.8.2
USB CONTROL
The USB is controlled through I/O registers as listed in table 5-21.
Table 5–21. USB Control Registers
Table 5-21.
USB Control Registers
I/O Addr.
00, 01h
02, 03h
04, 05h
06, 07
08, 0B
0Ch
10, 11h
12, 13h
5.8.3
Register
Command
Status
Interupt Enable
Frame No.
Frame List Base Address
Start of Frame Modify
Port 1 Status/Control
Port 2 Status/Control
USB CONNECTOR
The USB interface provides two connectors.
1
2
3
4
Figure 5–11. Universal Serial Bus Connector (one of two as viewed from rear of chassis)
Table 5–22. USB Connector Pinout
Table 5-22.
USB Connector Pinout
Pin
1
2
Signal
Vcc
USB-
Description
+5 VDC
Data (minus)
Pin
3
4
Signal
USB+
GND
5-38 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
Description
Data (plus)
Ground
Technical Reference Guide
Chapter 6
GRAPHICS SUBSYSTEM
6. Chapter 6 GRAPHICS SUBSYSTEM
6.1
INTRODUCTION
This chapter describes the graphics subsystem. The graphics subsystem is integrated onto the
system board and operates as a PCI peripheral device. Topics covered in this chapter include:
♦
♦
Subsystem overview (6.2)
S3 Trio64V2/GX-based subsystem (6.3)
page 6-1
page 6-2
Table 6-1 provides an overview of the graphics subsystem.
Table 6–1. Graphics Subsystem Comparison
Table 6-1.
Graphics Subsystem Overview
Graphics Controller:
Graphics Memory:
Maximum Resolution:
S3 Trio64 V2-GX
2 MB SGRAM
1280x1024 w/256 colors @ 85 Hz
The standard graphics controller used in the Deskpro 4000N/4000S Series is a PCI peripheral
that can be identified by software reading the “Vendor ID” and “Device ID” words in PCI
configuration address space locations 00h and 02h respectively. The values are as follows:
Vendor ID
5333h
????h
Device ID
8901h
????h
Graphics ASIC
S3 Trio64V2-GX
Matrox Cyclone
System
Pentium MMX-based
Pentium II-based
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
6-1
Chapter 6 Graphics Subsystem
6.2
SUBSYSTEM DESCRIPTION
The graphics subsystem consists of the S3 Trio64V2/GX graphics controller and two megabytes
of SGRAM for the frame buffer memory. The graphics BIOS code is included in the system
BIOS ROM. This subsystem provides full multimedia support (with software MPEG
acceleration) for a maximum resolution of 1024x768 with 256 colors @ 85 Hz, non-interlaced.
2-MB
SGRAM
Processor/
Memory
Subsystems
Graphics
Memory Bus
(63..00)
32-Bit PCI Bus
S3 Trio64 V2/GX
Graphics
Controller
RGB Data
Figure 6–1. S3 Trio64V2/GX-Based Graphics Subsystem, Block diagram
6.2.1
S3 TRIO64V2/GX GRAPHICS CONTROLLER
The S3 Trio64V2/GX graphics controller provides most of the functionality of the integrated
graphics subsystem and contains the features listed below:
♦
♦
♦
♦
♦
♦
♦
♦
♦
6-2
Quick Draw support
DCI and DirectX video support
MS DirectDraw support
Horizontal and vertical interpolation
On-the-fly stretching/blending of video streams
Double-buffering for seamless video
170-MHz 24-bit (true color) RAMDAC
Designed for SGRAM operation
VESA DDC1 and DDC2B support
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Monitor
Technical Reference Guide
6.2.2
S3 TRIO64V2/GX GRAPHICS CONFIGURATIONS
The Trio64V2/GX-based graphics subsystem directly supports standard CGA, EGA, and VGA
modes. Using the supplied drivers, the controller with this system supports the extended VGA
modes listed in the table below. All modes are supported by the Win NT3.51 and 4.0, Win 3.1
and 95, and OS/2 operating systems unless otherwise noted.
Table 6–2. S3 Trio64V2/GX-Based Subsystem Extended VGA Modes
Table 6-2.
S3 Trio64V2/GX-Based Subsystem
Extended VGA Display Modes
Color
Pixel Resolutiun
Bits Per Pixel
Depth
640 x 480
8
256
640 x 480
16
65 K
640 x 480
24
16.7 M
640 x 480
32
16.7 M
800 x 600
8
256
800 x 600
16
65 K
800 x 600
32
16.7 M
1024 x 768
8
256
1024 x 768
16
65 K
1152 x 864
8
256
1280 x 1024
8
256
NOTES:
Operation is non-lnterleaved for all modes with a refresh rate of up to 85 Hz.
[1] Mode not supported by OS/2.
[2] Mode not supported by Win 3.1.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Notes
[1]
[1]
[1] [2]
[2]
6-3
Chapter 6 Graphics Subsystem
6.2.3
S3 TRIO64V2/GX GRAPHICS SUBSYSTEM PROGRAMMING
The S3 Trio64V2/GX is compatible with software written for VGA, EGA, and CGA modes.
Drivers are supplied for control of graphics (GUI) accelerator engines used in extended VGA
modes.
6.2.3.1 Subsystem Configuration
The graphics subsystem works off the PCI bus and is configured through the Trio64V2’s PCI
configuration space registers (listed in Table 6-3) using PCI protocol. These registers are
configured by BIOS during POST to the default configuration.
Table 6–3. GD5436 PCI Configuration Space Registers
Table 6-3.
S3 Trio64V2/GX PCI Configuration Space Registers
PCI Config.
Address
00h-03h
04h, 05h
08h, 09h
Function
Vender ID (5333h)/Device ID (8901h)
PCI Command
Status
PCI Config.
Address
10h-13h
30h, 31h
3Ch, 3Dh
Function
I/O Base Address
Expansion ROM Base Address
Interrupt Line / Interrupt Pin
For a discussion of accessing PCI configuration space registers refer to chapter 4. For a detailed
description of registers refer to the S3 Trio64V2-GX Manual.
6.2.3.2 Subsystem Control
Tables 6-4 and 6-5 list the control registers of the S3 Trio64V2/GX. For a detailed discription of
the control registers refer to appropriate S3 documentation.
Table 6–4. Standard VGA Mode I/O Mapping
Table 6-4.
Standard VGA Mode I/O Mapping
I/O
I/O
Address
Function
Address
3B5.00..26h*
CRT Controller (mono)
3C6h..3C9h
3BAh
VSYNC Control, Display Status
3CAh
3C1.00..14h*
Attribute Controller
3CCh
3C2h
Misc. Control / Status
3CF.00..08h
3C5h.00..04h*
Sequencer
3D5.00..26h*
--3DAh
* Index at base minus 1 (i.e., if base is 3B5h, index is at 3B4h.
6-4
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Function
RAMDAC
Read VSYNC Status
Misc. Control, Read
Graphics Controller
CRT Controller (color)
VSYNC Control, Display Status (color)
Technical Reference Guide
Table 6–5. S3-Specific Control Register Mapping
Table 6-5.
S3-Specific Control Register Mapping
I/O
Address
Function
3x5.2D..3Ch [1]
Extended VGA Registers
3x5.40..4Fh [1]
Control Registers
3x5.50..6Fh [1]
Extension Registers
--x = B, Monochrome
x = C, Color
[1] Index at 3x4h
[2] Addresses not contiguously used through range.
6.2.4
I/O
Address
42E8h, 4AE8h
8180h-81FCh
82E8h-E2EAh
FF00h-FF40h
Function
Enhanced Command Registers
Streams Processor Registers
Enhanced Command Registers [2]
Local Peripheral Bus Registers
MONITOR POWER CONTROL
This system provides monitor power control for monitors that conform to the VESA display
power management signaling protocol. This protocol defines different power consumption
conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition.
Table 6-6 lists the monitor power conditions.
Table 6–6. Monitor Power Management Conditions
Table 6-6.
Monitor Power Management Conditions
HSYNC
Active
VSYNC
Active
Power Mode
On
Active
Inactive
Suspend
Inactive
Inactive
Off
Description
Monitor is completely powered up. If activated, the inactivity
counter counts down during system inactivity and if allowed to
tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode
inactivity timer counts down from the preset value and if allowed to
timeout, another SMI is generated and serviced, resulting in the
monitor being placed into the Off mode. Wake up from Suspend
mode is typically a few seconds.
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
The timeout parameter set in the SIT record 03h and indexed at CMOS location 2Ch (bits
<4..0>) represents the period of system I/O inactivity required to elapse before the monitor is
placed into Suspend mode.
A separate timer function (enabled through CMOS location 1Fh, bit <1>) can be enabled to place
the monitor into the Off mode after 45 minutes of being in Suspend mode.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
6-5
Chapter 6 Graphics Subsystem
6.2.5
CONNECTORS
The graphics subsystem provides a VGA monitor connector described in the following figure and
table.
Figure 6–2. VGA Monitor Connector, (Female DB-15, as viewed from the rear of chassis).
Table 6–7. DB-15 Monitor Connector Pinout
Table 6-7.
DB-15 Monitor Connector Pinout
Pin
1
2
3
4
5
6
7
8
6-6
Signal
R
G
B
Mon ID
GND
R GND
G GND
B GND
Description
Red Analog
Blue Analog
Green Analog
Monitor Identification
Ground
Red Analog Ground
Blue Analog Ground
Green Analog Ground
Pin
9
10
11
12
13
14
15
--
Signal
NC
GND
Mon. ID
SDA
HSync
VSync
SCL
--
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Description
Not Connected
Ground
Monitor Identification
DDC2-B Data
Horizontal Sync
Vertical Sync
DDC2-B Clock
--
Technical Reference Guide
Chapter 7
POWER and SIGNAL
DISTRIBUTION
7. Chapter 7 POWER SUPPLY AND DISTRIBUTION
7.1
INTRODUCTION
This chapter describes the power supply and method of general power and signal distribution in
the Compaq Deskpro 4000N and 4000S Personal Computers. All models use a 76-watt power
supply assembly. Power distribution is basically similar in all models. Topics covered in this
chapter include:
♦
♦
♦
7.2
Power supply assembly/control (7.2)
Power distribution (7.3)
Signal distribution (7.4)
page 7-1
page 7-4
page 7-6
POWER SUPPLY ASSEMBLY/CONTROL
This system features a power supply that is controlled through programmable logic (Figure 7-1).
This allows several options for how and when the system can be powered up.
Power
Button
Power On
System Board
SW1 -6
Power
Control
Logic
PS On
Fan Off-
PINTA
On Cntrl
NIC
I/O Controller
+5 AUX
Fan Pwr
+3.5 VDC
AC Input
Power Supply
Assembly
+5 VDC
-5 VDC
+12 VDC
Fan
To
System
Board &
Drives
-12 VDC
Figure 7–1. Power Supply Assembly, Block Diagram
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
7-1
Chapter 7 Power and Signal Distribution
7.2.1
POWER SUPPLY ASSEMBLY
The 76-watt power supply assembly is contained in a single unit that features a selectable input
voltage of 90-132 VAC and 180-264 VAC. The power supply assembly provides +3.5 VDC, +5
VDC, -5 VDC, +12 VDC, and -12 VDC potentials for the system board, expansion board(s), and
installed drives. These voltages are controlled by the PS On signal from the Power Control Logic.
A fault-detection circuit automatically shuts down the power supply when certain faults are
detected. Faults that can trigger the protection circuitry include:
♦
♦
Overvoltage - The +5 VDC output will activate the overvoltage crowbar circuit that triggers
the protection circuit when the output exceeds +5.60 VDC to +6.80 VDC. The +3.5 VDC
output will activate the overvoltage crowbar circuit when the output is sensed to be in the
+3.7 VDC to +5.0 VDC range.
Short Circuit - The protection circuit triggers if any power supply output is shorted to
ground or to another output. This function reduces shock or fire hazard
In addition to the previously mentioned voltages, auxiliary +5 VDC (+5 AUX) is produced by the
power supply assembly as long as the unit is plugged into a live AC outlet. The +5 AUX voltage
is used by power control logic and the network interface controller.
Table 7-1 shows the specifications for the power supply.
Table 7–1. Power Supply Specifications
Table 7-1.
Power Supply Assembly Specifications
Tolerance/
Min. Current
Max.
Surge
Parameter
Range
Loading [1]
Current
Current [2]
Input Line Voltage:
110 VAC Setting:
90 - 132 VAC
---220 VAC Setting:
180-264 VAC
---Line Frequency
47 - 63 Hz
---Steady State Input (VAC) Current:
--5.5 A
-+3.5 VDC Output
+/- 1%
0.6 A
7.0 A
7.0 A
+5 VDC Output
+/- 5 %
0.5 A
5.0 A
5.0 A
+5 AUX Output
+/- 5 %
0.1 A
1.2 A
1.2 A
+12 VDC Output
+/- 5 %
0.0 A
1.5 A
3.0 A
-12 VDC Output
+/- 10 %
0.0 A
0.2 A
0.2 A
NOTES:
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds and +12 tolerance +/- 10%.
Max.
Ripple
----50 mV
50 mV
80 mV
120 mV
200 mV
The system fan is physically attached to and driven by the power supply. Fan speed is adjusted in
a linear fashion (5.5-13.6 VDC) by the power supply. The power control logic also controls fan
operation through an LM75 temperature sensor. This sensor controls the FAN OFF signal that
indicates to the power supply to shut off the fan. A temperature sensor within the power supply
can cause the power supply to override the FAN OFF signal if the ambient temperature of the
power supply is too warm.
7-2
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
7.2.2
POWER CONTROL
The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On
is asserted (high), the Power Supply Assembly is activated. When PS On is de-asserted, the
Power Supply Assembly (and the rest of the system) is off. The PS On signal is typically
controlled through the Power Button, which can be set by software (Windows 95) to operate as
either a standard On/Off button or as a Suspend button. The resultant action of pressing the
power button depends on the programmed state of the power button.at that time and is described
as follows:
System State
Off
Pressed Power Button Results In:
Negative pulse, of which the falling edge results in power control logic asserting
PS On signal to Power Supply Assembly, which then initializes. Four-second
counter is not active.
On,
Advd. Power Disabled
Negative pulse, of which the rising edge causes power control logic to de-assert
the PS On signal. Four-second counter is not active.
On,
Advd. Power Enabled
Pressed and Released Under Four Seconds:
Negative pulse, of which the falling edge causes power control logic to
generate SMI-, set a bit in the SMI source register, set a bit for button status,
and start four-second counter. Software should clear the button status bit
within four seconds and the Suspend state is entered. If the status bit is
not cleared by software in four seconds PS On is de-asserted and the
power supply assembly shuts down (this condition is meant as a guard in
case the OS is hung).
Pressed and Held At least Four Seconds Before Release:
If the button is held in for at least four seconds and then released, PS On is
negated, de-activating the power supply.
The PS On signal can also be activated with a power “wake-up” of the system due to the
following events:
Magic Packet - If the network interface controller is enabled for remote wake-up, reception of a
“Magic Packet” results in the NIC component asserting the PINTA- signal to the power control
logic, which in turn asserts the PS On signal and turns on the power supply assembly.
RTC Alarm/Modem Ring - These events (within the 87307 I/O controller) are programmable for
power wake-up and can affect the assertion of the PS On signal through the power control logic.
NOTE: The PS On signal can be configured to be asserted whenever the power supply
assembly is connected to live AC by setting DIP SW1 position 6 to the “On” (closed or
grounding) position. This condition overrides all other settings.
The power LED is normally on in a steady state with the system on. When the system is in a low
power (suspend) condition the power LED is pulsed, causing it to blink at approximately a rate of
1-Hz. The blinking is affected through the power control logic
The power button can be inhibited by invoking BIOS call INT 15, AX=E828h, which is
discussed in Chapter 8, “BIOS ROM.”
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
7-3
Chapter 7 Power and Signal Distribution
7.3
POWER DISTRIBUTION
7.3.1
3.5/5/12 VDC DISTRIBUTION
The power supply assembly includes a connector (P1) that mates directly with the system board
connector (P17) when the assembly is installed. The power supply assembly also includes a cable
assembly that routes +3.5 VDC, +5 VDC, -5 VDC, +12 VC, and -12 VDC to the individual drive
assemblies.
Power Supply
Assembly
P3
P2
P1 [1]
P3
P1
Drive
Assemblies
P2
8 9 10 11 12 13 14
1 2 3 4 5 6 7
1
Connector
P1
P1 [2]
P2
P3
2
3
4
1
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
+3.5
+3.5RS
RTN
+5
RTN
+5
RTN
+3.5
PS On
+5AUX
RS rtn
+12
RTN
RSRTN
RTN
-5
+5
GND
GND
+12
+12
GND
GND
+5
NOTES:
[1] Connector P1 mates directly with connector P17 on the system board.
[2] This row represents pins 11-14 of connector P1.
All + and - values are VDC.
RTN = Return (signal ground)
GND = Power ground
RS = Remote sense
FO = Fan off
Figure 7–2. Power Cable Diagram
7-4
4 3 2
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Pin 9
-12
+5
Pin 10
FO
+5
Technical Reference Guide
7.3.2
LOW VOLTAGE DISTRIBUTION
The system board includes a provision for producing 2.5 VDC for microprocessors that require
such a level for core power. The low voltage circuitry (Figure 7-3) consists of a power MOSFET
and regulator components that produce 2.8 VDC, plus or minus 3.57%.
2SK1388
+3.3 VDC
+2.8 VDC
Microprocessor
Power Supply
Assembly
Regulator
Circuit
+12 VDC
2.5 V Proc. Detect
Microprocessor
Figure 7–3. Low Voltage Supply, Block Diagram
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
7-5
Chapter 7 Power and Signal Distribution
7.4
SIGNAL DISTRIBUTION
Figure 7-4 shows general signal distribution between the main subassemblies of the system unit.
32-Bit PCI Bus
PCI Connector
Riser
Card
Conn
J4
Riser Card
16-Bit ISA Bus
HD Activity
ISA Connector [1]
P16
System
Board
SW/LED
Conn
Power
P17
Conn
P20
IDE
Conn
PWR SW, PWR LED, HD LED
+3.5, +/- 5,
+/- 12 VDC [2]
Power
Supply
Assembly
IDE I/F
IDE
Hard Drive
IDE
P21 Conn
IDE I/F
CD-ROM
Dsk.
Conn
Dsk I/F
Diskette Drive
J1
J14
Mouse
Conn
J13
Kybd
Conn
Power On
Power Button
5, 12 VDC
5, 12 VDC
5, 12 VDC
Mouse
Keyboard
NOTES:
[1] Deskpro 4000S only
[2] No cable used for interface; direct connection between PS assembly and system board.
CD Models only. An audio card must be added by the user if audio is desired.
Figure 7–4. Signal Distribution Diagram
7-6
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Chapter 8
BIOS ROM
8. Chapter 8 BIOS ROM
8.1
INTRODUCTION
The Basic Input/Output System (BIOS) of the computer is a collection of machine language
programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such
functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power
management activities, and Setup. This chapter includes the following topics:
♦
♦
♦
♦
♦
Boot Functions (8.2)
Accessing configuration memory (8.3)
Client management support (8.4)
PnP support (8.5)
Power management support (8.6)
page 8-2
page 8-3
page 8-5
page 8-17
page 8-18
The firmware contained in the BIOS ROM supports the following operating systems:
♦
♦
♦
♦
♦
♦
♦
♦
DOS 6.2
Windows 3.1
Windows for Workgroups 3.11
Windows 95
Windows NT 3.5
OS/2 ver 2.1
OS/2 Warp
SCO Unix
The microprocessor accesses the BIOS ROM as a 128-KB block from E0000h to FFFFFh. The
BIOS data is shadowed in a 64-KB block in the upper memory area. The BIOS segments are
dynamically paged in and out of the 64-KB block as they are needed.
NOTE: This chapter describes BIOS in general and focuses on aspects of BIOS unique
to this particular system. For detailed information regarding the BIOS, refer to the
Compaq Basic Input/Output System Technical Reference Guide.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-1
Chapter 8 BIOS ROM
8.2
BOOT FUNCTIONS
The system supports new system boot functions to support remote ROM flashing and PC97
requirements. This system also supports the EL Torito specification for bootable CDs.
NOTE: This system will not boot CDs intended for use in Compaq ProLiant and
ProSignia products.
8.2.1
BOOT BLOCK
This system includes 24 KB of boot block ROM that provides a way to recover from a failed
remote flashing of the system BIOS ROM. Early during the boot process, the boot block code
checks the system ROM. If validated, the system BIOS continues the boot sequence. If the
system ROM fails the check, the boot block code provides the minimum amount of support
necessary to allow booting the system from the diskette drive (bypassing the security measures)
and re-flash the system ROM with a ROMPAQ diskette. Since video is not available during the
initial boot sequence the boot block routine uses the keyboard LEDs to communicate status as
follows:
Num Lock
LED
Off
On
Off
On
Caps Lock
LED
On
Off
Off
On
Scroll Lock
LED
Off
Off
On
On
Meaning
Administrator password required.
Boot failed. Reset required for retry.
Flash failed (set by ROMPAQ).
Flash complete (set by ROMPAQ).
The boot block area of ROM is always write-protected.
8.2.2
QUICKBOOT
The QuickBoot mode (programmable through the INT 15, AX=E845h call) skips certain portions
of the POST (such as the memory count) during the boot process unless the hood has been
detected as being removed. The QuickBoot mode is programmable as to be invoked always, never
(default) or every x-number of days.
8.2.3
SILENTBOOT
When in the SilentBoot mode, the boot process skips certain audio and visual aspects of POST
(such as the speed beeps and screen messages). Error messages are still displayed. The
QuickBoot mode is programmable (through the INT 15, AX=E845h call) as to either TERSE
(default) or VERBOSE mode.
8-2
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
8.3
ACCESSING CONFIGURATION MEMORY
Configuration memory (CMOS and NVRAM) should be accessed using the appropriate BIOS
function. The following subsections describe several BIOS functions available to applications for
accessing the system’s non-volatile memory.
8.3.1
ACCESSING CMOS
For accessing CMOS bytes, the calling application should use INT 15 AX=E823h, which is
described as follows:
INPUT:
EAX
BH
BL
CX
OUTPUT:
(Successful)
CF
AH
AL
(Failure)
CF
AH
8.3.2
= E823h
= 0, read
= 1, write
= Value to write (if a write is specified)
= Byte number (zero-based)
=0
= 00h
= Byte Value (if a read was specified)
=1
= 86h, Function not supported
= FFh, Byte does not exist
SETTING DEFAULT PARAMETERS
The BIOS function INT 15, AX=E841h is used for setting various system parameters to the
default settings on the next system boot. This function is intended for Plug ‘n Play (PnP) support
(refer to section 8.5 “Plug ‘n Play” for more information. Two variances of the function are
available and described as follows:
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-3
Chapter 8 BIOS ROM
8.3.2.1 INT 15, AX=E841h, BL=00h - Set CMOS Defaults
This function sets a bit in NVRAM that instructs the BIOS to load NVRAM with default values
during the next system boot. The user will not be prompted when the default values are set. Note
that the ESCD area of NVRAM is not affected by this function. Any required changes to the
ESCD area must be made by the calling application invoking PnP BIOS functions.
INPUT:
EAX
BH
OUTPUT:
(Successful)
CF
AH
(Failure)
CF
AH
= E841h
= 00h
=0
= 00h
=1
= 86h, Function not supported
8.3.2.2 INT 15, AX=E841h, BL=01h - Set System Board Device Defaults
This function performs a PnP Set System Device Node call for all system board “devnnodes.” On
the next boot following execution of this function, each device is configured with the factory
default settings. In addition to this call, an application may choose to also remove non-system
board devices from ESCD area. The function is described as follows:
INPUT:
EAX
BH
OUTPUT:
(Successful)
CF
AH
(Failure)
CF
AH
8.3.3
= E841h
= 00h
=0
= 00h
=1
= 86h, Function not supported
ACCESSING CMOS FEATURE BITS
The BIOS function INT 15, AX=E845h is used for accessing areas in non-volatile memory used
to store variables for various features. This is a Client Management function and is described in
section 8.4.
8-4
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
8.4
CLIENT MANAGEMENT SUPPORT
Client Management deals with issues of security, identification, and system management
functions. A group of BIOS INT 15 functions are provided to support Client Management. These
functions are listed Table 8-2.
Table 8–1. PnP Client Management Functions (INT15)
Table 8-2.
Client Management Functions (INT15)
AX
E800h
E807h
E813h
E814h
E816h
E817h
E818h
E819h
E81Ah
E81Bh
E81Ch
E81Dh
E81Eh
E822h
E827h
E828h
E829h
E845h
Function
Get system ID
Get System Information Table
Get monitor information
Get system revision
Get temperature status
Get drive attribute
Get drive off-line test
Get chassis serial number
Write chassis serial number
Get drive threshold
Write network error log
Read network error log
Get drive ID
Flash ROM/Sys. Admin. Fnc.
DIMM EEPROM Access
Inhibit power button
Remote Security Functions
Access CMOS Feature Bits
Mode
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real
Real
Real, 16-, & 32-bit Prot.
Real
Real
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
All 32-bit protected mode calls are accessed by using the industry-standard BIOS32 Service
Directory. Using the service directory involves three steps:
1.
2.
3.
Locating the service directory.
Using the service directory to obtain the entry point for the client management functions.
Calling the client management service to perform the desired function.
The BIOS32 Service Directory is a 16-byte block that begins on a 16-byte boundary between the
physical address range of 0E0000h-0FFFFFh. The format is as follows:
Offset
00h
04h
08h
09h
0Ah
0Bh
No. Bytes
4
4
1
1
1
5
Description
Service identifier (four ASCII characters)
Entry point for the BIOS32 Service Directory
Revision level
Length of data structure (no. of 16-byte units)
Checksum (should add up to 00h)
Reserved (all 0s)
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-5
Chapter 8 BIOS ROM
To support Windows NT an additional table to the BIOS32 table has been defined to contain 32bit pointers for the DDC and SIT locations. The Windows NT extension table is as follows:
; Extension to BIOS SERVICE directory table (next paragraph)
db
db
db
dd
dw
db
dd
dw
db
dd
dw
“32OS”
2
“$DDC”
?
?
“$SIT”
?
?
“$ERB”
?
?
; sig
; number of entries in table
; DDC POST buffer sig
; 32-bit pointer
; byte size
; SIT sig
; 32-bit pointer
; byte size
; ESCD sig
; 32-bit pointer
; bytes size
The service identifier for Client Management functions is “$CLM.” Once the service identifier is
found and the checksum verified, a FAR call is invoked using the value specified at offset 04h to
retrieve the CM services entry point. The following entry conditions are used for calling the
Client Management service directory:
INPUT:
EAX
EBX (31..8)
EBX (7..0)
CS
= Service Identifier [$CLM]
= Reserved
= Must be set to 00h
= Code selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
It must have the same base. CS is execute/read.
DS
= Data selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
It must have the same base. DS is read only.
SS
= Stack selector must provide at least 1K of stack space and be 32-bit.
(I/O permissions must be provided so that the BIOS can support as necessary)
OUTPUT:
AL
EBX
ECX
EDX
= Return code:
00h, requested service is present
80h, requested service is not present
81h, un-implemented function specified in BL
86h and CF=1, function not supported
= Physical address to use as the selector BASE for the service
= Value to use as the selector LIMIT for the service
= Entry point for the service relative to the BASE returned in EBX
The following subsections describe aspects of Client Management unique to this system. For a
general description of these BIOS functions refer to the Compaq BIOS Technical Reference
Guide.
8-6
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
8.4.1
SYSTEM ID
The INT 15, AX=E800h BIOS function can be used by software to identify the system. The
system ID will be returned in the BX register as follows:
Series
Deskpro 4000N
Deskpro 4000S
8.4.2
System ID
03D8h
038Ch
SYSTEM INFORMATION TABLE
The System Information Table (SIT) is a comprehensive list of fixed configuration information
arranged into records. The INT 15 AX=E807h BIOS function accesses the SIT by returning a
pointer in ES:BX to indicate the location of the SIT. This section lists the default values that
should be read from the SIT. For specific bit descriptions and more detailed information on the
SIT refer to the Compaq Basic Input/Output System (BIOS) Technical Reference Guide.
Power Conservation Record, SIT Record 01h
Byte
Function
00h
Record ID
01h
No. of Data Bytes in Record
02h
Volume, CPU Speed, Screensave, PWR Consv. Mode
03h
LED Blink, Popup, APM, PC Level, MAXBRIGHT Control
04h
SW Power Cntrl., Screensave/Hard Drive Timeouts, PWR
05h
Magic Packet Flag, SMI, Modem Installed
06h-0Bh
Popup Location
0Ch
Qick Energy Save, Magic Packet PWR, Suspend, CPU Sp.
NOTES:
[1] Will be determined at runtime
[2] Unsupported function - read all 0s.
Default
Value
01h
0Bh
07h
C4h
10h
[1]
[2]
1Ch
Timeout Counter Record (System Standby), SIT Record 02h
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
Function
Record ID for System Standby Timeout
No. of Data Bytes in Record
First Value
Last Value
Default
Value
02h
08h
0
15
20
30
40
45
60
75
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-7
Chapter 8 BIOS ROM
Timeout Counter Record (Video Screensave), SIT Record 03h
Byte [1]
Function
0Ah
Record ID for Video Screensave Timeout
0Bh
No. of Data Bytes in Record
0Ch
First Value
0Dh
0Eh
0Fh
10h
11h
12h
13h
14H
Last Value
NOTE:
[1] Offset from byte 00h of timeout record 02h.
Default
Value
03h
09h
0
5
10
15
20
30
40
50
60
Timeout Counter Record (Hard Drive), SIT Record 04h
Byte [1]
Function
15h
Record ID for Hard Drive Timeout
16h
No. of Data Bytes in Record
17h
First Value
18h
19h
1Ah
1Bh
1Ch
Last Value
NOTE:
[1] Offset from byte 00h of timeout record 02h.
Default
Value
04h
06h
0
10
15
20
30
60
Security Record, SIT Record 05h
Byte
00h
01h
02h
03h
04h
05h
NOTE:
Function
Record ID
No. of Data Bytes in Record
NVRAM/HD Lock, QuickLock/QuickBlank, FD Boot, PWR Pwd
Virus Detect, Serial/Parallel Cntrl., FD Drive Cntl., Stby Cntrl.
Diskette Drive Fnct., Password Functions
Password Locking, Ownership Tag Length
Default
Value
05h
04h
7Fh
1Eh
7Ah
[1]
[1] Determined by system at runtime.
Processor/Memory/Cache Record, SIT Record 06h
Byte
Function
00h
Record ID
01h
No. of Data Bytes in Record
02h, 03h
Installed Microprocessor Speed
04h
Cache Configuration
05h
L2 Cache Size
06h
L2 Cache Speed
07h
Total Memory Amount Adjustment
08h, 09h
Total Soldered Memory
0Ah, 0Bh Maximum Memory Installable
0Ch, 0Dh Reserved
0Eh
Processor Designer
0Fh
System Cache Error Correction
NOTE: [1] Determined by system at runtime.
8-8
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Default
Value
06h
0Eh
[1]
07h
20h
00h
06h
0000h
0100h
0000h
00h
01h
Technical Reference Guide
Peripheral and Input Device Record, SIT Record 07h
Byte
00h
01h
02h
03h
04h
05h
06h
07h-0Ah
0Bh
0Ch
0Dh
0Eh
0Fh, 10h
11h, 12h
13h
14h, 15h
16h
17h
18h
19h
1Ah
1Bh
1Ch, 1Dh
1Eh, 1Fh
20h, 21h
22h, 23h
24h
25h
26h
27h
28h-2Bh
2Ch-2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
Function
Record ID
No. of Data Bytes in Record
DMA Functions, SCSI Support, Flashable ROM, Setup
Partition, 101 Keyboard
Erase-Eaze Kybd. Support in ROM, El Torito CD Boot
Support, QuickBoot, ROM Functions
Formfactor
Softdrive 1 & 2 Data
Softdrive 3 & 4 Data
Softdrive 1-4 Starting Address
Panel ID
Integrated Monitor, ROM Socket, No. of Prog. Serial Ports
Parallel Port Mode, Modem Type
Drive Fault Prediction Support for Drives 0-3
PCI Bus Master CMOS Data
VGA Palette Snoop Function
Misc. PCI Information
2
I/O Address for I C Device
2
I C Information Byte
ATAPI Device Information (Logical Devices 1 & 2)
ATAPI Device Information (Logical Devices 3 & 4)
3-D Audio Support
BIOS Supported Features
Misc. Features (Power Inhibit Support)
Back-to-Back I/O Delay Index 0
Back-to-Back I/O Delay Index 1
Back-to-Back I/O Delay Index 2
Back-to-Back I/O Delay Index 3
Back-to-Back I/O Delay NVRAM Location
Bit Mask for Byte 24h
O/S Boot NVRAM Location
Bit Mask for Byte 26h
IDE Drive 0-3 Max DMA/PIO Mode
Offset Address in EBDA for Bezel Button
Processor Upgrade Mounting
Parallel Port Connector Type/Pinout
Serial Port Connector Type
Serial Port Maximum Speed
Serial Port Maximum Speed
Serial Port Maximum Speed
DMA Burst Mode Support
Keyboard Connector Type
Default
Value
07h
34h
07h
53h
04h, DT
05h, MT
FFh
FFh
all 0s
00h
12h
00h
F1h
0000h
0000h
01h
00h
00h
00h
00h
00h
00h
01h
0420h
0300h
0660h
0780h
n/a
n/a
n/a
n/a
n/a
n/a
01h
41h
01h
16h
E3h
60h
0Bh
13h
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-9
Chapter 8 BIOS ROM
Memory Module Information Record, SIT Record 08h
Byte
Function
00h
Record ID
01h
No. of Data Bytes in Record
02h
No. of Sockets
03h
Memory Socket Location 0
04h
Memory Installed In Location 0
05h
Memory Speed In Location 0
06h
Memory Form Factor 0
07h
Memory Socket Location 1
08h
Memory Installed In Location 1
09h
Memory Speed In Location 1
0Ah
Memory Form Factor 1
0Bh
Memory Socket Location 2
0Ch
Memory Installed In Location 2
0Dh
Memory Speed In Location 2
0Eh
Memory Form Factor 2
NOTE: [1] Determined at runtime.
Default
Value
08h
0Dh
03h
00h
[1]
[1]
03h
01h
[1]
[1]
03h
02h
[1]
[1]
03h
Timeout Default Record, SIT Record 09h
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
Function
Record ID
No. of Data Bytes in Record
High Power - Standby
High Power - Hard Drive/System Idle
High Power - Screensave
High Power - Maximum Brightness
High Power - Processor Speed
Medium Power - Standby
Medium Power - Hard Drive/System Idle
Medium Power - Screensave
Medium Power - Maximum Brightness
Medium Power - Processor Speed
Default
Value
09h
0Ah
15 min
15 min
15 min
100 min
100 min
15 min
15 min
15 min
100 min
100 min
CMOS/NVRAM Information Record, SIT Record 0Ah
Byte
00h
01h
02h
03h
04h
05h
06h
Function
Record ID
No. of Data Bytes in Record
Size of EISA NVRAM or Extended CMOS (Low Byte)
Size of EISA NVRAM or Extended CMOS (High Byte)
Size of High CMOS (Low Byte)
Size of High CMOS (High Byte)
NVRAM Storage Device Access Type
Automatic Server Recovery Record, SIT Record 0Bh (Not Used)
Memory Banks Information Record, SIT Record 0Ch (Not Used)
Multiprocessor Feature Information Record, SIT Record 0Dh (Not Used)
8-10 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Default
Value
0Ah
0Ah
00h
00h
00h
00h
00h
Technical Reference Guide
Extended Disk Support Record, SIT Record 0Eh
Default
Value
0Eh
02h
[1]
[1]
Byte
Function
00h
Record ID
01h
No. of Data Bytes in Record
02h
Pointer To Extended Disk table (High Byte)
03h
Pointer To Extended Disk table (Low Byte)
NOTE: [1] Determined at runtime.
System Record, SIT Record 0Fh (Not Used)
Product Name Header Record, SIT Record 10h
Byte
00h
01h
02h-14
15h
Function
Record ID
No. of Data Bytes in Record
Product Name
Terminator Byte
Default
Value
10h
14h
“Compaq Deskpro 4000”
00h
DC-DC Converter Record, SIT Record 11h (Not Used)
Processor Microcode Patch Record, SIT Record 12h
Byte
00h
01h
02h-05h
06h-09h
0Ah-0Dh
Function
Record ID
No. of Data Bytes in Record
Patch 1 Version
Patch 1 Date
Patch 1 Family/Model/Stepping
Patch 2 Version
Patch 2 Date
Patch 2 Family/Model/Stepping
Default
Value
12h
02h
00000020h
09031996h
00000632h
System Hood Removal Record, SIT Record 13h
Byte
Function
00h
Record ID
01h
No. of Data Bytes in Record
02h-05h
Hood Removed Time Stamp (Year/Month/Day/Hours/Min/Sec
06h
Hood Removal Support CMOS Byte Offset
07h
Hood Removal Support Bit Location
08h
Hood Removal NOBOOT CMOS Byte Offset
09h
Hood Removal NOBOOT CMOS Bit Location
0Ah
Software Hood Lock
NOTE: [1] Determined at runtime.
Default
Value
13h
09h
[1]
00h
00h
00h
00h
[1]
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-11
Chapter 8 BIOS ROM
8.4.3
TEMPERATURE SENSOR
A temperature sensor component is mounted in the cavity of the microprocessor socket. This
sensor component detects when the microprocessor has reached a programmed temperature level
and initiates appropriate action. The sensor is programmed by BIOS for two temperature levels; a
level for initiating a caution to the user and another level to initiate a system shutdown. Detection
of a temperature level results in asserting an IRQ and/or the SMI- for initiating action.
The sensing feature is set up by BIOS during POST. A particular microprocessor step will have
peculiar operating temperature optimums so that a processor upgrade may require that the BIOS
be upgraded as well. The status of the temperature condition (caution, critical) may be retrieved
using the INT 15, AX=E816h call.
8.4.4
DRIVE FAULT PREDICTION
The Compaq BIOS provides direct Drive Fault Prediction support for IDE-type hard drives. This
feature is provided through two BIOS calls. Function INT 15, AX=E817h is used to retrieve a
512-byte block of drive attribute data while the INT 15, AX=E81Bh is used to retrieve the drive’s
warranty threshold data. If data is returned indicating possible failure then the following
message is displayed:
“1720-Intellisafe Hard Drive detects imminent failure”
8-12 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
8.4.5
DIMM SUPPORT
The BIOS includes DIMM support consisting of the following:
♦
♦
♦
Access control with the serial (I2C) EEPROM of the DIMM
Runtime information on ECC-correctable single bit errors
POST message if ECC-correctable errors are detectable during POST memory test
DIMMs with 128 bytes of EEPROM can be used although 256-byte EEPROM DIMMs are
recommended for full support of Compaq intelligent manageability features. The following BIOS
functions have been added to provide specific support of DIMMs:
INT 15h AX=E827h, BH=00h; Read DIMM EEPROM
ENTRY:
AX = E827h
BH = 00h
BL =
DIMM No. (0-3)
CX = Number of bytes to read
DX = Offset of first byte to read
DS: (E) SI = Address of data buffer to receive data
RETURN:
CX =
CF =
No. of bytes read
0 (Success)
AH = 0
1 (Failure)
AH = Error Code:
01h, No DIMM EEPROM or socket empty
02h, Boundary error (offset or no. of bytes to read exc. cap)
86h, Not supported
INT 15h AX=E827h, BH=01h; Write DIMM EEPROM
ENTRY:
AX = E827h
BH = 01h
BL =
DIMM No. (0-3)
CX = Number of bytes to be written
DX = Offset of first byte to be written
DS: (E) SI = Address of data buffer holding write data
RETURN:
CX =
CF =
No. of bytes written
0 (Success)
AH = 0
1 (Failure)
AH = Error Code:
01h, No DIMM EEPROM or socket empty
02h, Boundary error (offset or no. of bytes to read exc. cap)
86h, Not supported
INT 15h AX=E827h, BH=02h; Get ECC-Corrected Single Bit Error Status
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-13
Chapter 8 BIOS ROM
ENTRY:
AX =
BH =
E827h
02h
RETURN:
CF =
0 (Success)
AH = 0
0000h (if no single bit ECC corrected error has occurred)
bit <0>, Error occurred on DIMM/SIMM pair 0
bit <1>, Error occurred on DIMM/SIMM pair 1
bit <2>, Error occurred on DIMM/SIMM pair 2
bit <3>, Error occurred on DIMM/SIMM pair 3
1 (Failure)
AH = 86h (Not supported)
BX =
CF =
The POST memory test checks for ECC-corrected single bit errors after each 64K of memory
tested in a similar fashion as is done with parity. The errors are counted on a per DIMM basis
and notify the user at the end of the test in the following format:
“207-ECC Corrected Single Bit Errors in DIMM/SIMM Pair(s) x,x…”
x = DIMM/SIMM pair numbers 0 through 3.
8-14 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
8.4.6
SECURITY FUNCTIONS
The INT 15 AX=E829h BIOS function is used to control various security features of the system.
This function may be issued remotely (over a network) by a driver. A request buffer must be built
(by the driver) for each security feature prior to making the call. This system supports the
following security features:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
QuickLock
QuickBlank
Diskette drive boot disable
Diskette drive write disable
IDE controller disable
Serial ports disable
Parallel port disable
Change administrator password
Hood removal sensor
Ownership tag
Asset tag
USB disable
The write-protect function that determines diskette write control is extended to cover all drives
that use removable read/write media (i.e., if diskette write protect is invoked, then any diskette
drive, power drive (SCSI and/or ATAPI), and floptical drive installed will be inaccessible for
(protected from) writes). Client management software should check the following bytes of SIT
record 07h for the location and access method for this bit:
System Information Table, Peripheral and Input Device Record (07h) (partial listing)
Byte
Bit
Function
1Fh
7-0
Removable Read/Write Media Write Protect Enable Byte Offset (0-255)
Removable Read/Write Media Write Protect Enable Bit Location:
20h
CMOS Type:
7..4
0000 = CMOS
0001 = High CMOS
0010 = NVRAM
0011 = Flat model NVRAM
Bit Location:
3..0
0000 = Bit 0
0100 = Bit 4
0001 = Bit 1
0101 = Bit 5
0010 = Bit 2
0110 = Bit 6
0011 = Bit 3
0111 = Bit 7
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-15
Chapter 8 BIOS ROM
8.4.7
ACCESSING CMOS FEATURE BITS
The BIOS function INT 15, AX=E845h is a tri-modal call for accessing areas in non-volatile
memory used to store variables for various features.
INPUT:
EAX
BL
BH
CX
DS:SI
OUTPUT:
(Successful)
CF
EAX
BH
(Failure)
CF
AH
CX
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
NOTE:
= E845h
= 0, Read
= 1, Write
= Value Read/to Write
= Feature Bits Number (refer to description box below)
= Pointer to buffer passing multiple byte features
=0
= Reserved
= Value read (if a read was specified)
=1
= 86h, Function not supported
Function
PCI 2.1 Mode (Enabled)
Erase Eaze Keyboard (off)
Comm/IR Port Designation (Comm port)
No Rejection of SETs By PnP (reject SETs)
PCI VGA Snoop (snoop disabled)
PCI Bus Mastering BIOS Support (disabled)
Auto Prompt for Auto Setup (prompt for F1, F2, F10)
Mode 2 Configuration Support (enabled)
Secondary Hard Drive Controller Enabled (enabled)
Secondary Hard Drive Controller IRQ (IRQ15)
Custom Drive Type #1
Custom Drive Type #2
Custom Drive Type #3
Custom Drive Type #4
POST Verbose/Terse or “Silent Boot” Mode (Terse)
Drive Translation Mode (translate)
Mfg. Process Number Bytes
Administrator Password
Power-On Password
Ownership Tag
Warm Boot Password Mode (disabled)
Hood Lock (enabled)
Hood Removal (disabled)
USB Security (disabled)
Configurable Power Supply (legacy mode)
QuickBoot Mode (full boot always)
BBS IPL Order
Default
Value
1b
00b
0b
0b
0b
0b
00b
1b
1b
11b
40 bits, all 0s
40 bits, all 0s
40 bits, all 0s
40 bits, all 0s
1b
0b
30 bits, [1]
72 bits, [1]
32 bits, [1]
640 bits, [1]
0b
1b
00b
0b
0b
00000b
76543210h
For full bit definitions refer to the Compaq BIOS Technical Reference Guide.
[1] Determined at runtime.
8-16 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
8.5
PNP SUPPORT
The BIOS includes Plug ’n Play (PnP) support for PnP version 1.0A.
NOTE: For full PnP functionality to be realized, all peripherals used in the system must
be designed as “PnP ready.” Any installed ISA peripherals that are not “PnP ready” can
still be used in the system, although configuration parameters may need to be considered
(and require intervention) by the user.
Table 8-1 shows the PnP functions supported (for detailed PnP information refer to the Compaq
BIOS Technical Reference Guide):
Table 8–1. PnP BIOS Functions
Table 8-1.
PnP BIOS Functions
Function
00h
01h
02h
03h
04h
Register
Get number of system device nodes
Get system device node
Set system device node
Get event
Send message
The BIOS call INT 15, AX=E841h, BH=01h (described earlier in section 8.3) can be used by an
application to retrieve the default settings of PnP devices for the user. The application should use
the following steps for the display function:
1.
2.
3.
4.
Call PnP function 01(get System Device Node) for each devnode with bit 1 of the control
flag set (get static configuration) and save the results.
Call INT 15, AX=E841h, BH=01h.
Call PnP “Get Static Configuration” for each devnode and display the defaults.
If the user chooses to save the configuration, no further action is required. The system board
devices will be configured at the next boot. If the user wants to abandon the changes, then
the application must call PnP function 02 (Set System Device Node) for each devnode (with
bit 1 of the control flag set for static configuration) with the results from the calls made prior
to invoking this function.
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-17
Chapter 8 BIOS ROM
8.6
POWER MANAGEMENT SUPPORT
The Compaq Deskpro 2000 system includes Advanced Power Management (APM) BIOS support
that provides, if so configured, for the automatic shutdown of certain areas within a system after
a specified time of inactivity has elapsed. When activity is detected, APM brings the system back
up to full power to provide complete user support.
For maximum energy-conservation benefit, APM functionality should be implemented using the
following three layers:
♦
♦
♦
BIOS layer (APM BIOS (ver. 1.2, 1.1, 1.0))
Operating system (OS) layer (APM driver)
Application layer (APM-aware application or device driver)
The BIOS layer informs the OS or driver when hardware events occur (or don’t occur) so that a
transition to another power state should take place. The process starts with the OS or driver
making a connection with the BIOS through an APM BIOS call. In a DOS environment
POWER.EXE makes a Real mode connection. In Windows 3.1 and in Windows 95, a 32-bit
connection is made. Currently Windows NT does not make an APM connection.
With power management enabled, inactivity timers are monitored. When an inactivity timer
times out, an SMI is sent to the microprocessor to invoke the SMI handler. The SMI handler
works with the APM driver and APM BIOS to take appropriate action based on which inactivity
timer timed out.
Two I/O ports are used for APM communication with the SMI handler:
Port Address
0B2h
0B3h
Name
APM Control
APM Status
Three power states are defined under power management:
On - The computer is running, all subsystems are on and drawing full power. Any activity in the
following subsystems will reset the activity timer, which has a default setting of 15 minutes
before Standby entered:
a. Keyboard
b. Mouse
c. Serial port
d. Diskette drive
e. Hard drive
8-18 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Standby - The computer is in a low power state: video is off, some subsystems may be drawing
less power, and the microprocessor is halted except for servicing interrupts. Video graphics
controller is under driver control and/or VSYNC is off and the power supply fan is turned off.
Any of the following activities will generate a wake-up SMI and return the system to On:
a. Keyboard
b. Mouse
c. Serial port
d. Diskette drive
e. Hard drive
f. RTC Alarm
If no APM connection is present, the BIOS will set an APM timer to 45 minutes, at which
time the Suspend will be entered if no activity has occurred. This function can be defeated (so
that Suspend will not be achieved). If an APM connection is present, the BIOS APM timer is
not used and Suspend is entered only by user request either through an icon in Windows 95 or
by pressing and releasing the power button under 4 seconds.
Suspend - The computer is in a low power state: video graphics controller is under driver control
and/or HSYNC and VSYNC are off, some subsystems may be drawing less power, and the
microprocessor is halted except for servicing interrupts. Any of the following activities will
generate a wake-up SMI and return the system to On:
a. Keyboard
b. Mouse
c. Serial port
d. Diskette drive
e. Hard drive
f. RTC Alarm
g. Network interface controller
The APM BIOS for this system supports APM 1.2 as well as previous versions 1.1 and 1.0. The
APM BIOS functions are listed in Table 8-3.
Table 8–2. APM BIOS Functions (INT15)
Table 8-3.
APM BIOS Functions (INT15)
AX
5300h
5301h
5302h
5303h
5304h
5305h
5306h
5307h
5308h
5309h
530Ah
530Bh
530Ch
530Dh
530Eh
530Fh
5380h
Function
APM Installation Check
APM Connect (Real Mode)
APM Connect (16-bit Protected Mode)
APM Connect (32-bit Protected Mode)
Interface Disconnect
CPU Idle
CPU Busy
Set Power State [1]
Enable/Disable Power Management
Restore Power On Defaults
Get Power Status
Get PM Event
Get Power State
Enable/Disable Device Power Management
APM Driver Version
Engage/Disengage Power Management
OEM (Compaq) Specific APM Function
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
8-19
Chapter 8 BIOS ROM
This page is intentionally blank.
8-20 Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
Technical Reference Guide
Appendix A
ERROR MESSAGES AND CODES
A. Appendix A ERROR MESSAGES AND CODES
A.1
INTRODUCTION
This appendix lists the error codes and a brief description of the probable cause of the error. Note
that not all errors listed in this appendix may be applicable to a particular system depending on
the model and/or configuration.
A.2
POWER-ON MESSAGES
Table A–1. Power-On Messages
Table A-1.
Power-On Messages
Message
CMOS Time and Date Not Set
(none)
Run Setup
A.3
Beeps
(None)
2 short
(None)
Probable Cause
Invalid time or date
Power-On successful
Any failure
BEEP CODE MESSAGES
Table A–2. Beep Code Messages
Table A-2.
Beep Code Messages
Beeps
1
3
4
5
6
Error
Refresh Failure
Base 64-KB Memory Failure
Timer Not Operational
Processor Error
8042 Gate A20 Failure
7
8
Processor Exception Interrupt Error
Display Memory R/W Error
9
10
11
ROM Checksum Error
CMOS Shutdown Register R/W Error
Cache Error
Probable Cause
Faulty memory refresh circuitry.
Memory failure in first 64-KB.
Same as above or timer 1 not functioning.
CPU-generated error.
Keyboard controller faulty, BIOS cannot switch to
protected mode.
CPU-generated exception interrupt.
Missing graphics/video adapter or faulty video memory
(system still boots).
Checksum value does not match value in BIOS.
CMOS RAM shutdown register failure.
Faulty cache.
Compaq Personal Computers
Changed - Septembe 1997
A-1
Appendix A Error Messages and Codes
A.4
POWER-ON SELF TEST (POST) MESSAGES
Table A–3. Power-On Self Test (POST) Messages
Table A-3.
Power-On Self Test (POST) Messages
Error Message
Bad PnP Serial ID Checksum
Address Lines Short!
Cache Memory Failure, Do Not Enable
Cache!
CMOS Battery Failed
CMOS Checksum Invalid
CMOS System Options Not Set
CMOS Display Type Mismatch
CMOS Memory Size Mismatch
CMOS Time and Date Not Set
Diskette Boot Failure
DMA Bus Timeout
DMA Controller Error
Drive Not Ready Error
Diskette Drive Controller Failure
Diskette Drive Controller Resource
Conflict
Diskette Drive A: Failure
Diskette Drive B: Failure
Gate A20 Failure
Invalid Boot Diskette
Keyboard Controller Error
Keyboard is Locked…Please Unlock It
Keyboard Stuck Key Detected
Master DMA Controller Error
Master Interrupt Controller Error
Memory Size Decreased
NVRAM Checksum Error, NVRAM
Cleared
NVRAM Cleared By Jumper
NVRAM Data Invalid, NVRAM Cleared
Off Board Parity Error Addr. (HEX) = X
Parallel Port Resource Conflict
PCI Error Log is Full
PCI I/O Port Conflict
PCI Memory Conflict
Primary Boot Device Not Found
Primary IDE Cntrl. Resource Conflict
Primary Input Device Not Found
Secondary IDE Controller Resource
Serial Port 1 Resource Conflict
Serial Port 2 Resource Conflict
Slave DMA Controller Error
Slave Interrupt Controller Error
Static Device Resource Conflict
System Board Device Resource
Conflict
System Memory Size Mismatch
Probable Cause
Serial ID checksum of PnP card was invalid.
Error in address decoding circuitry on system board.
Defective cache memory, CPU has failed.
Low RTC/CMOS battery
Previous and current checksum value mismatch.
Corrupt or non-existant CMOS values.
Graphics/video type in CMOS does not match type detected by
BIOS.
Memory amount detected does not match value stored in CMOS.
Time and date are invalid.
Boot disk in drive A: is corrupt.
Bus driven by device for more than 7.8 us
Error in one or both DMA controllers.
BIOS cannot access the diskette drive.
BIOS cannot communicate with diskette drive controller.
Diskette drive controller has requested a resource already in use.
BIOS cannot access drive A:.
BIOS cannot access drive B:
Gate A20 of keyboard controller not working.
BIOS can read but cannot boot system from drive A:.
Keyboard controller failure.
Locked keyboard.
Key pressed down.
Error exists in master DMA controller.
Master interrupt controller failure.
Amount of memory detected is less than stated value in CMOS.
ESCD data was re-initialized due to NVRAM checksum error.
NVRAM has been cleared by removal of jumper.
Invalid entry in ESCD.
Parity error occurred in expansion memory, x= address of error.
Parallel port has requested a resource already in use.
PCI conflict error limit (15) has been reached.
Two devices requested the same resource.
Two devices requested the same resource.
Designated primary boot device could not be found.
Primary IDE controller requested a resource already in use.
Designated primary input device could not be found.
Secondary IDE controller has requested a resource already in use.
Serial port 1 requested a resource already in use.
Serial port 2 requested a resource already in use.
Error exists in slave DMA controller.
Slave interrupt controller failure.
A non-PnP ISA card has requested a resource already in use.
A non-PnP ISA card has requested a resource already in use.
Amount of memory detected on system board is different from
amount indicated in CMOS.
NOTE:
PCI and PnP messages are displayed with bus, device, and function information.
A-2
Compaq Personal Computers
Changed - September 1997
Technical Reference Guide
A.5
PROCESSOR ERROR MESSAGES (1xx-xx)
Table A–4. Processor Error Messages
Table A-4.
Processor Error Messages
Message
101-01
101-02
101-91..94
102-01
102-02
102-03
102-04
102-05
102-06
102-07
102-08
102-09
102-10
102-11
102-12
102-15
102-16
102-17
102-18
102-19
102-20
102-21
103-01
103-02
103-03
104-01
104-02
104-03
105-01
105-02
105-03
105-04
105-05
105-06
105-07
Probable Cause
CPU test failed
32-bit CPU test failed
Multiplication test failed
FPU initial sts. word incorrect
FPU initial cntrl. Word incorrect
FPU tag word not all ones
FPU tag word not all zeros
FPU exchange command failed
FPU masked exception error
FPU unmasked exception error
FPU wrong mask status bit set
FPU unable to store real number
FPU real number calc test failed
FPU speed test failed
FPU pattern test failed
FPU is inoperative or not present
Weitek not responding
Weitek failed register trnsfr. Test
Weitek failed arithemetic ops test
Weitek failed data conv. Test
Weitek failed interrupt test
Weitek failed speed test
DMA page registers test failed
DMA byte controller test failed
DMA word controller test failed
Master int. cntlr. test fialed
Slave int. cntlr. test failed
Int. cntlr. SW RTC inoperative
Port 61 bit <6> not at zero
Port 61 bit <5> not at zero
Port 61 bit <3> not at zero
Port 61 bit <1> not at zero
Port 61 bit <0> not at zero
Port 61 bit <5> not at one
Port 61 bit <3> not at one
Message
105-08
105-09
105-10
105-11
105-12
105-13
105-14
106-01
107-01
108-02
108-03
109-01
109-02
109-03
110-01
110-02
110-03
111-01
112-01
112-02
112-03
112-04
112-05
112-06
112-07
112-08
112-09
112-10
112-11
112-12
113-01
114-01
116-xx
199-00
--
Probable Cause
Port 61 bit <1> not at one
Port 61 bit <0> not at one
Port 61 I/O test failed
Port 61 bit <7> not at zero
Port 61 bit <2> not at zero
No interrupt generated by failsafe timer
NMI not triggered by failsafe timer
Keyboard controller test failed
CMOS RAM test failed
CMOS interrupt test failed
CMOS not properly initialized (interrupt test)
CMOS clock load data test failed
CMOS clock rollover test failed
CMOS not properly initialized (clock test)
Programmable timer load data test failed
Programmable timer dynamic test failed
Program timer 2 load data test failed
Refresh detect test failed
Speed test Slow mode out of range
Speed test Mixed mode out of range
Speed test Fast mode out of range
Speed test unable to enter Slow mode
Speed test unable to enter Mixed mode
Speed test unable to enter Fast mode
Speed test system error
Unable to enter Auto mode in speed test
Unable to enter High mode in speed test
Speed test High mode out of range
Speed test Auto mode out of range
Speed test variable speed mode inoperative
Protected mode test failed
Speaker test failed
Way 0 read/write test failed
Installed devices test failed
--
Compaq Personal Computers
Changed - Septembe 1997
A-3
Appendix A Error Messages and Codes
A.6
MEMORY ERROR MESSAGES (2xx-xx)
Table A–5. Memory Error Messages
Table A-5.
Memory Error Messages
Message
200-04
200-05
200-06
200-07
200-08
201-01
202-01
202-02
202-03
203-01
203-02
203-03
204-01
204-02
204-03
204-04
204-05
205-01
205-02
205-03
206-xx
210-01
210-02
210-03
211-01
211-02
211-03
213-xx
214-xx
215-xx
A.7
Probable Cause
Real memory size changed
Extended memory size changed
Invalid memory configuration
Extended memory size changed
CLIM memory size changed
Memory machine ID test failed
Memory system ROM checksum failed
Failed RAM/ROM map test
Failed RAM/ROM protect test
Memory read/write test failed
Error while saving block in read/write test
Error while restoring block in read/write test
Memory address test failed
Error while saving block in address test
Error while restoring block in address test
A20 address test failed
Page hit address test failed
Walking I/O test failed
Error while saving block in walking I/O test
Error while restoring block in walking I/O test
Increment pattern test failed
Memory increment pattern test
Error while saving memory during increment pattern test
Error while restoring memory during increment pattern test
Memory random pattern test
Error while saving memory during random memory pattern test
Error while restoring memory during random memory pattern test
Incompatible DIMM in slot x
Noise test failed
Random address test
KEYBOARD ERROR MESSAGES (30x-xx)
Table A–6. Keyboard Error Messages
Table A-6.
Keyboard Error Messages
Message
300-xx
301-01
301-02
301-03
301-04
301-05
302-xx
302-01
303-01
303-02
303-03
303-04
A-4
Probable Cause
Failed ID test
Kybd short test, 8042 self-test failed
Kybd short test, interface test failed
Kybd short test, echo test failed
Kybd short test, kybd reset failed
Kybd short test, kybd reset failed
Failed individual key test
Kybd long test failed
LED test, 8042 self-test failed
LED test, reset test failed
LED test, reset failed
LED test, LED command test failed
Message
303-05
303-06
303-07
303-08
303-09
304-01
304-02
304-03
304-04
304-05
304-06
--
Compaq Personal Computers
Changed - September 1997
Probable Cause
LED test, LED command test failed
LED test, LED command test failed
LED test, LED command test failed
LED test, command byte restore test failed
LED test, LEDs failed to light
Keyboard repeat key test failed
Unable to enter mode 3
Incorrect scan code from keyboard
No Make code observed
Cannot /disable repeat key feature
Unable to return to Normal mode
--
Technical Reference Guide
A.8
PRINTER ERROR MESSAGES (4xx-xx)
Table A–7. Printer Error Messages
Table A-7.
Printer Error Messages
Message
401-01
402-01
402-02
402-03
402-04
402-05
402-06
402-07
402-08
402-09
A.9
Probable Cause
Printer failed or not connected
Printer data register failed
Printer control register failed
Data and control registers failed
Loopback test failed
Loopback test and data reg. failed
Loopback test and cntrl. reg. failed
Loopback tst, data/cntrl. reg. failed
Interrupt test failed
Interrupt test and data reg. failed
Message
402-10
402-11
402-12
402-13
402-14
402-15
402-16
402-01
498-00
--
Probable Cause
Interrupt test and control reg. failed
Interrupt test, data/cntrl. reg. failed
Interrupt test and loopback test failed
Int. test, LpBk. test., and data register failed
Int. test, LpBk. test., and cntrl. register failed
Int. test, LpBk. test., and data/cntrl. reg. failed
Unexpected interrupt received
Printer pattern test failed
Printer failed or not connected
--
VIDEO (GRAPHICS) ERROR MESSAGES (5xx-xx)
Table A–8. Video (Graphics) Error Messages
Table A-8.
Video (Graphics) Error Messages
Message
501-01
502-01
503-01
504-01
505-01
506-01
507-01
Probable Cause
Video controller test failed
Video memory test failed
Video attribute test failed
Video character set test failed
80x25 mode, 9x14 cell test failed
80x25 mode, 8x8 cell test failed
40x25 mode test failed
Message
508-01
509-01
510-01
511-01
512-01
514-01
516-01
Probable Cause
320x200 mode, color set 0 test failed
320x200 mode, color set 1 test failed
640x200 mode test failed
Screen memory page test failed
Gray scale test failed
White screen test failed
Noise pattern test failed
Compaq Personal Computers
Changed - Septembe 1997
A-5
Appendix A Error Messages and Codes
A.10
DISKETTE DRIVE ERROR MESSAGES (6xx-xx)
Table A–9. Diskette Drive Error Messages
Table A-9.
Diskette Drive Error Messages
Message
Probable Cause
6xx-01
Exceeded maximum soft error limit
6xx-02
Exceeded maximum hard error limit
6xx-03
Previously exceeded max soft limit
6xx-04
Previously exceeded max hard limit
6xx-05
Failed to reset controller
6xx-06
Fatal error while reading
6xx-07
Fatal error while writing
6xx-08
Failed compare of R/W buffers
6xx-09
Failed to format a tract
6xx-10
Failed sector wrap test
600-xx = Diskette drive ID test
601-xx = Diskette drive format
602-xx = Diskette read test
603-xx = Diskette drive R/W compare test
604-xx = Diskette drive random seek test
605-xx = Diskette drive ID media
606-xx = Diskette drive speed test
607-xx = Diskette drive wrap test
A.11
Message
Probable Cause
6xx-20
Failed to get drive type
6xx-21
Failed to get change line status
6xx-22
Failed to clear change line status
6xx-23
Failed to set drive type in ID media
6xx-24
Failed to read diskette media
6xx-25
Failed to verify diskette media
6xx-26
Failed to read media in speed test
6xx-27
Failed speed limits
6xx-28
Failed write-protect test
--608-xx = Diskette drive write-protect test
609-xx = Diskette drive reset controller test
610-xx = Diskette drive change line test
694-00 = Pin 34 not cut on 360-KB drive
697-00 = Diskette type error
698-00 = Drive speed not within limits
699-00 = Drive/media ID error (run Setup)
SERIAL INTERFACE ERROR MESSAGES (11xx-xx)
Table A–10. Serial Interface Error Messages
Table A-10.
Serial Interface Error Messages
Message
1101-01
1101-02
1101-03
1101-04
1101-05
1101-06
1101-07
1101-08
1101-09
1101-10
1101-11
A-6
Probable Cause
Port test, UART DLAB bit failure
Port test, line input or UART fault
Port test, address line fault
Port test, data line fault
Port test, UART cntrl. signal failure
Port test, UART THRE bit failure
Port test, UART Dta RDY bit failure
Port test, UART TX/RX buffer failure
Port test, interrupt circuit failure
Port test, COM1 set to invalid INT
Port test, COM2 set to invalid INT
Message
1101-12
1101-13
1101-14
1109-01
1109-02
1109-03
1109-04
1109-05
1109-06
1150-xx
--
Compaq Personal Computers
Changed - September 1997
Probable Cause
Port test, DRVR/RCVR cntrl. signal failure
Port test, UART cntrl. signal interrupt failure
Port test, DRVR/RCVR data failure
Clock register initialization failure
Clock register rollover failure
Clock reset failure
Input line or clock failure
Address line fault
Data line fault
Comm port setup error (run Setup)
--
Technical Reference Guide
A.12
MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx)
Table A–11. Serial Interface Error Messages
Table A-11.
Serial Interface Error Messages
Message
Probable Cause
1201-XX
Modem internal loopback test
1201-01
UART DLAB bit failure
1201-02
Line input or UART failure
1201-03
Address line failure
1201-04
Data line fault
1201-05
UART control signal failure
1201-06
UART THRE bit failure
1201-07
UART DATA READY bit failure
1201-08
UART TX/RX buffer failure
1201-09
Interrupt circuit failure
1201-10
COM1 set to invalid inturrupt
1201-11
COM2 set to invalid
1201-12
DRVR/RCVR control signal failure
1201-13
UART control signal interrupt failure
1201-14
DRVR/RCVR data failure
1201-15
Modem detection failure
1201-16
Modem ROM, checksum failure
1201-17
Tone detect failure
1202-XX
Modem internal test
1202-01
Time-out waiting for SYNC [1]
1202-02
Time-out waiting for response [1]
1202-03
Data block retry limit reached [1]
1202-11
Time-out waiting for SYNC [2]
1202-12
Time-out waiting for response [2]
1202-13
Data block retry limit reached [2]
1202-21
Time-out waiting for SYNC [3]
1202-22
Time-out waiting for response [3]
1202-23
Data block retry limit reached [3]
1203-XX
Modem external termination test
1203-01
Modem external TIP/RING failure
1203-02
Modem external data TIP/RING fail
1203-03
Modem line termination failure
1204-XX
Modem auto originate test
1204-01
Time-out waiting for SYNC [4]
1204-02
Time-out waiting for response [4]
NOTES:
[1] Local loopback mode
[2] Analog loopback originate mode
[3] Analog loopback answer mode
[4] Modem auto originate test
[5] Modem auto answer test
[6] Modem direct connect test
Message
1204-03
1204-04
1204-05
1204-06
1204-07
1204-08
1204-09
1204-10
1204-11
1205-XX
1205-01
1205-02
1205-03
1205-04
1205-05
1205-06
1205-07
1205-08
1205-09
1205-10
1205-11
1206-XX
1206-17
1210-XX
1210-01
1210-02
1210-03
1210-04
1210-05
1210-06
1210-07
1210-08
1210-09
1210-10
1210-11
Probable Cause
Data block retry limit reached [4]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
Modem auto answer test
Time-out waiting for SYNC [5]
Time-out waiting for response [5]
Data block retry limit reached [5]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
Dial multi-frequency tone test
Tone detection failure
Modem direct connect test
Time-out waiting for SYNC [6]
Time-out waiting for response [6]
Data block retry limit reached [6]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
Compaq Personal Computers
Changed - Septembe 1997
A-7
Appendix A Error Messages and Codes
A.13
HARD DRIVE ERROR MESSAGES (17xx-xx)
Table A–12. Hard Drive Error Messages
Table A-12.
Hard Drive Error Messages
Message
Probable Cause
17xx-01
Exceeded max. soft error limit
17xx-02
Exceeded max. Hard error limit
17xx-03
Previously exceeded max. soft error limit
17xx-04
Previously exceeded max.hard error limit
17xx-05
Failed to reset controller
17xx-06
Fatal error while reading
17xx-07
Fatal error while writing
17xx-08
Failed compare of R/W buffers
17xx-09
Failed to format a track
17xx-10
Failed diskette sector wrap during read
17xx-19
Cntlr. failed to deallocate bad sectors
17xx-40
Cylinder 0 error
17xx-41
Drive not ready
17xx-42
Failed to recalibrate drive
17xx-43
Failed to format a bad track
17xx-44
Failed controller diagnostics
17xx-45
Failed to get drive parameters from ROM
17xx-46
Invalid drive parameters from ROM
17xx-47
Failed to park heads
17xx-48
Failed to move hard drive table to RAM
17xx-49
Failed to read media in file write test
17xx-50
Failed I/O write test
1700-xx = Hard drive ID test
1701-xx = Hard drive format test
1702-xx = Hard drive read test
1703-xx = Hard drive read/write compare test
1704-xx = Hard drive random seek test
1705-xx = Hard drive controller test
1706-xx = Hard drive ready test
1707-xx = Hard drive recalibrate test
1708-xx = Hard drive format bad track test
1709-xx = Hard drive reset controller test
A-8
Message
Probable Cause
17xx-51
Failed I/O read test
17xx-52
Failed file I/O compare test
17xx-53
Failed drive/head register test
17xx-54
Failed digital input register test
17xx-55
Cylinder 1 error
17xx-56
Failed controller RAM diagnostics
17xx-57
Failed controller-to-drive diagnostics
17xx-58
Failed to write sector buffer
17xx-59
Failed to read sector buffer
17xx-60
Failed uncorrectable ECC error
17xx-62
Failed correctable ECC error
17xx-63
Failed soft error rate
17xx-65
Exceeded max. bad sectors per track
17xx-66
Failed to initialize drive parameter
17xx-67
Failed to write long
17xx-68
Failed to read long
17xx-69
Failed to read drive size
17xx-70
Failed translate mode
17xx-71
Failed non-translate mode
17xx-72
Bad track limit exceeded
17xx-73
Previously exceeded bad track limit
--1710-xx = Hard drive park head test
1714-xx = Hard drive file write test
1715-xx = Hard drive head select test
1716-xx = Hard drive conditional format test
1717-xx = Hard drive ECC test
1719-xx = Hard drive power mode test
1721-xx = SCSI hard drive imminent failure
1724-xx = Net work preparation test
1736-xx = Drive monitoring test
1799-xx = Invalid hard drive type
Compaq Personal Computers
Changed - September 1997
Technical Reference Guide
A.14
HARD DRIVE ERROR MESSAGES (19xx-xx)
Table A–13. Hard Drive Error Messages
Table A-13.
Hard Drive Error Messages
Message
Probable Cause
19xx-01
Drive not installed
19xx-02
Cartridge not installed
19xx-03
Tape motion error
19xx-04
Drive busy erro
19xx-05
Track seek error
19xx-06
Tape write-protect error
19xx-07
Tape already Servo Written
19xx-08
Unable to Servo Write
19xx-09
Unable to format
19xx-10
Format mode error
19xx-11
Drive recalibration error
19xx-12
Tape not Servo Written
19xx-13
Tape not formatted
19xx-14
Drive time-out error
19xx-15
Sensor error flag
19xx-16
Block locate (block ID) error
19xx-17
Soft error limit exceeded
19xx-18
Hard error limit exceeded
19xx-19
Write (probably ID ) error
19xx-20
NEC fatal error
1900-xx = Tape ID test failed
1901-xx = Tape servo write failed
1902-xx = Tape format failed
1903-xx = Tape drive sensor test failed
A.15
Message
Probable Cause
19xx-21
Got servo pulses second time but not first
19xx-22
Never got to EOT after servo check
19xx-23
Change line unset
19xx-24
Write-protect error
19xx-25
Unable to erase cartridge
19xx-26
Cannot identify drive
19xx-27
Drive not compatible with controller
19xx-28
Format gap error
19xx-30
Exception bit not set
19xx-31
Unexpected drive status
19xx-32
Device fault
19xx-33
Illegal command
19xx-34
No data detected
19xx-35
Power-on reset occurred
19xx-36
Failed to set FLEX format mode
19xx-37
Failed to reset FLEX format mode
19xx-38
Data mismatch on directory track
19xx-39
Data mismatch on track 0
19xx-40
Failed self-test
19xx-91
Power lost during test
1904-xx = Tape BOT/EOT test failed
1905-xx = Tape read test failed
1906-xx = Tape R/W compare test failed
1907-xx = Tape write-protect failed
VIDEO (GRAPHICS) ERROR MESSAGES (24xx-xx)
Table A–14. Hard Drive Messages
Table A-14.
Hard Drive Error Messages
Message
2402-01
2403-01
2404-01
2405-01
2406-01
2407-01
2408-01
2409-01
2410-01
2411-01
2412-01
2414-01
2416-01
2417-01
2417-02
2417-03
2417-04
2418-01
Probable Cause
Video memory test failed
Video attribute test failed
Video character set test failed
80x25 mode, 9x14 cell test failed
80x25 mode, 8x8 cell test failed
40x25 mode test failed
320x200 mode color set 0 test failed
320x200 mode color set 1 test failed
640x200 mode test failed
Screen memory page test failed
Gray scale test failed
White screen test failed
Noise pattern test failed
Lightpen text test failed, no response
Lightpen text test failed, invalid response
Lightpen graphics test failed, no resp.
Lightpen graphics test failed, invalid resp.
EGA memory test failed
Message
2418-02
2419-01
2420-01
2421-01
2422-01
2423-01
2424-01
2425-01
2431-01
2432-01
2448-01
2451-01
2456-01
2458-xx
2468-xx
2477-xx
2478-xx
2480-xx
Probable Cause
EGA shadow RAM test failed
EGA ROM checksum test failed
EGA attribute test failed
640x200 mode test failed
640x350 16-color set test failed
640x350 64-color set test failed
EGA Mono. text mode test failed
EGA Mono. graphics mode test failed
640x480 graphics mode test failed
320x200 256-color set test failed
Advanced VGA controller test failed
132-column AVGA test failed
AVGA 256-color test failed
AVGA BitBLT test failed
AVGA DAC test failed
AVGA data path test failed
AVGA BitBLT test failed
AVGA linedraw test failed
Compaq Personal Computers
Changed - Septembe 1997
A-9
Appendix A Error Messages and Codes
A.16
AUDIO ERROR MESSAGES (3206-xx)
Table A–15. Audio Error Messages
Table A-15.
Audio Error Message
Message
3206-xx
A.17
Probable Cause
Audio subsystem internal error
NETWORK INTERFACE ERROR MESSAGES (60xx-xx)
Table A–16. Network Interface Error Messages
Table A-16.
Network Interface Error Messages
Message
6000-xx
6014-xx
6016-xx
6028-xx
6029-xx
Probable Cause
Pointing device interface error
Ethernet configuration test failed
Ethernet reset test failed
Ethernet int. loopback test failed
Ethernet ext. loopback test failed
Message
6054-xx
6056-xx
6068-xx
6069-xx
6089-xx
A-10 Compaq Personal Computers
Changed - September 1997
Probable Cause
Token ring configuration test failed
Token ring reset test failed
Token ring int. loopback test failed
Token ring ext. loopback test failed
Token ring open
Technical Reference Guide
A.18
SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx)
Table A–17. SCSI Interface Error Messages
Table A-17.
SCSI Interface Error Messages
Message
Probable Cause
6nyy-02
Drive not installed
6nyy-03
Media not installed
6nyy-05
Seek failure
6nyy-06
Drive timed out
6nyy-07
Drive busy
6nyy-08
Drive already reserved
6nyy-09
Reserved
6nyy-10
Reserved
6nyy-11
Media soft error
6nyy-12
Drive not ready
6nyy-13
Media error
6nyy-14
Drive hardware error
6nyy-15
Illegal drive command
6nyy-16
Media was changed
6nyy-17
Tape write-protected
6nyy-18
No data detected
6nyy-21
Drive command aborted
6nyy-24
Media hard error
6nyy-25
Reserved
6nyy-30
Controller timed out
6nyy-31
Unrecoverable error
6nyy-32
Controller/drive not connected
n = 5, Hard drive
= 6, CD-ROM drive
= 7, Tape drive.
Message
6nyy-33
6nyy-34
6nyy-35
6nyy-36
6nyy-39
6nyy-40
6nyy-41
6nyy-42
6nyy-43
6nyy-44
6nyy-50
6nyy-51
6nyy-52
6nyy-53
6nyy-54
6nyy-60
6nyy-61
6nyy-65
6nyy-90
6nyy-91
6nyy-92
6nyy-99
Probable Cause
Illegal controller command
Invalid SCSI bus phase
Invalid SCSI bus phase
Invalid SCSI bus phase
Error status from drive
Drive timed out
SSI bus stayed busy
ACK/REQ lines bad
ACK did not deassert
Parity error
Data pins bad
Data line 7 bad
MSG, C/D, or I/O lines bad
BSY never went busy
BSY stayed busy
Controller CONFIG-1 register fault
Controller CONFIG-2 register fault
Media not unloaded
Fan failure
Over temperature condition
Side panel not installed
Autoloader reported tape not loaded properly
yy = 00, ID
= 03, Power check
= 05, Read
= 06, SA/Media
= 08, Controller;
= 23, Random read
= 28, Media load/unload
A.19
POINTING DEVICE INTERFACE ERROR MESSAGES (8601-xx)
Table A–18. Pointing Device Interface Error Messages
Table A-18.
Pointing Device Interface Error Messages
Message
8601-01
8601-02
8601-03
8601-04
8601-05
Probable Cause
Mouse ID fails
Left mouse button is inoperative
Left mouse button is stuck closed
Right mouse button is inoperative
Right mouse button is stuck closed
Message
8601-06
8601-07
8601-08
8601-09
8601-10
Probable Cause
Left block not selected
Right block not selected
Timeout occurred
Mouse loopback test failed
Pointing device is inoperative
Compaq Personal Computers A-11
Changed - Septembe 1997
Appendix A Error Messages and Codes
A.20
CEMM PRIVILEDGED OPS ERROR MESSAGES
Table A–19. CEMM Privileged Ops Error Messages
Table A-19.
CEMM Privileged Ops Error Messages
Message
00
01
02
03
A.21
Probable Cause
LGDT instruction
LIDT instruction
LMSW instruction
LL2 instruction
Message
04
05
06
07
Probable Cause
LL3 instruction
MOV CRx instruction
MOV DRx instruction
MOV TRx instruction
CEMM EXCEPTION ERROR MESSAGES
Table A–20. CEMM Exception Error Messages
Table A-20.
CEMM Exception Error Messages
Message
00
01
02
03
04
05
06
07
08
09
Probable Cause
Divide
Debug
NMI or parity
INT 0 (arithmetic overflow)
INT 3
Array bounds check
Invalid opcode
Coprocessor device not available
Double fault
Coprocessor segment overrun
Message
10
11
12
13
14
16
32
33
34
--
A-12 Compaq Personal Computers
Changed - September 1997
Probable Cause
Invalid TSS
Segment not present
Stack full
General protection fault
Page fault
Coprocessor
Attempt to write to protected area
Reserved
Invalid software interrupt
--
Technical Reference Guide
Appendix B
ASCII CHARACTER SET
B. Appendix B ASCII CHARACTER SET
B.1
INTRODUCTION
This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and
hexadecimal values. All ASCII symbols may be called while in DOS or using standard textmode editors by using the combination keystroke of holding the Alt key and using the Numeric
Keypad to enter the decimal value of the symbol. The extended ASCII characters (decimals 128255) can only be called using the Alt + Numeric Keypad keys.
NOTE: Regarding keystrokes, refer to notes at the end of the table. Applications may interpret
multiple keystroke accesses differently or ignore them completely.
Table B–1. ASCII Character Set
Table B-1.
ASCII Character Set
Dec
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Symbol
Blank
♥
♦
♣
♠
●
❍
↕
!!
¶
§
↕
↑
↓
→
←
↔
▲
▼
Dec
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Hex
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Symbol
Space
!
“
#
$
%
&
‘
(
)
*
+
`
.
/
0
1
2
3
4
5
6
7
8
9
:
;
<
=
>
?
Dec
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
Symbol
@
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
[
\
]
^
_
Dec
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Hex
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Symbol
‘
a
b
c
d
e
f
g
h
I
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
{
|
}
~
[1]
Continued
Compaq Personal Computers
Original - July 1996
B-1
Appendix B ASCII Character Set
Table B-1. ASCII Code Set (Continued)
Dec
Hex
Symbol Dec
Hex
Symbol Dec
Hex
Symbol
Dec
Hex
Symbol
Ç
á
•
•
128
80
160
A0
192
C0
224
E0
ü
í
•
ß
129
81
161
A1
193
C1
225
E1
é
ó
•
•
130
82
162
A2
194
C2
226
E2
â
ú
•
•
131
83
163
A3
195
C3
227
E3
ä
ñ
•
•
132
84
164
A4
196
C4
228
E4
à
Ñ
•
•
133
85
165
A5
197
C5
229
E5
å
ª
•
µ
134
86
166
A6
198
C6
230
E6
ç
º
•
•
135
87
167
A7
199
C7
231
E7
ê
¿
•
•
136
88
168
A8
200
C8
232
E8
ë
•
•
•
137
89
169
A9
201
C9
233
E9
è
¬
•
•
138
8A
170
AA
202
CA
234
EA
ï
½
•
•
139
8B
171
AB
203
CB
235
EB
î
¼
•
•
140
8C
172
AC
204
CC
236
EC
ì
¡
•
•
141
8D
173
AD
205
CD
237
ED
Ä
«
•
•
142
8E
174
AE
206
CE
238
EE
Å
»
•
•
143
8F
175
AF
207
CF
239
EF
É
•
•
•
144
90
176
B0
208
D0
240
F0
æ
•
•
±
145
91
177
B1
209
D1
241
F1
Æ
•
•
•
146
92
178
B2
210
D2
242
F2
ô
•
•
•
147
93
179
B3
211
D3
243
F3
ö
•
•
•
148
94
180
B4
212
D4
244
F4
ò
•
•
•
149
95
181
B5
213
D5
245
F5
û
•
•
÷
150
96
182
B6
214
D6
246
F6
ù
•
•
•
151
97
183
B7
215
D7
247
F7
ÿ
•
•
°
152
98
184
B8
216
D8
248
F8
Ö
•
•
·
153
99
185
B9
217
D9
249
F9
Ü
•
•
·
154
9A
186
BA
218
DA
250
FA
¢
•
•
•
155
9B
187
BB
219
DB
251
FB
£
•
•
•
156
9C
188
BC
220
DC
252
FC
¥
•
•
²
157
9D
189
BD
221
DD
253
FD
•
•
•
•
158
9E
190
BE
222
DE
254
FE
ƒ
•
•
159
9F
191
BF
223
DF
255
FF
Blank
NOTES:
[1] Symbol not displayed.
Keystroke Guide:
Dec #
Keystroke(s)
0
Ctrl 2
1-26
Ctrl A thru Z respectively
27
Ctrl [
28
Ctrl
29
Ctrl ]
30
Ctrl 6
31
Ctrl 32
Space Bar
33-43
Shift and key w/corresponding symbol
44-47
Key w/corresponding symbol
48-57
Key w/corresponding symbol, numerical keypad w/Num Lock active
58
Shift and key w/corresponding symbol
59
Key w/corresponding symbol
60
Shift and key w/corresponding symbol
61
Key w/corresponding symbol
62-64
Shift and key w/corresponding symbol
65-90
Shift and key w/corresponding symbol or key w/corresponding symbol and
Caps Lock active
91-93
Key w/corresponding symbol
94, 95
Shift and key w/corresponding symbol
96
Key w/corresponding symbol
97-126 Key w/corresponding symbol or Shift and key w/corresponding symbol
and Caps Lock active
127
Ctrl 128-255 Alt and decimal digit(s) of desired character
B-2 Compaq Personal Computers
Original - July 1996
Technical Reference Guide
Appendix C
KEYBOARD
C. Appendix C KEYBOARD
C.1
INTRODUCTION
This appendix describes the Compaq keyboard that is included as standard with the system unit.
The keyboard complies with the industry-standard classification of an “enhanced keyboard” and
includes a separate cursor control key cluster, twelve “function” keys, and enhanced
programmability for additional functions.
This appendix covers the following keyboard types (some of which may be available only as an
option):
♦
The Windows-version keyboard includes three additional keys for specific support of the
Windows operating system.
♦
The Erase-Ease keyboard features a split spacebar that can be user-programmed to provide
easy access to the backspace function or set to operate as the normal spacebar.
♦
The scanner keyboard includes a built-in document scanner for scanning loose-leaf
hardcopy.
NOTE: This appendix discusses only the keyboard unit. The keyboard interface is a
function of the system unit and is discussed in Chapter 5, Input/Output Interfaces.
Topics covered in this appendix include the following:
♦
♦
Keystroke processing (C.2)
Scanner description (C.3)
page C-2
page C-14
Compaq Personal Computers
Changed - November 1996
C-1
Appendix C Keyboard
C.2
KEYSTROKE PROCESSING
A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power
(+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a
Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms
for pressed keys while at the same time monitoring communications with the keyboard interface
of the system unit. When a key is pressed, a Make code is generated. A Break code is generated
when the key is released. The Make and Break codes are collectively referred to as scan codes.
All keys generate Make and Break codes with the exception of the Pause key, which generates a
Make code only.
Num
Lock
Keyswitch
Matrix
Caps
Lock
Matrix
Drivers
Matrix
Receivers
Keyboard
Processor
Scroll
Lock
Data/
CLK
Keyboard
Interface
(System Unit)
Figure C–1. Keystroke Processing Elements, Block Diagram
When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal
after a period of 150 ms to 2 seconds. The keyboard undergoes a Basic Assurance Test (BAT)
that checks for shorted keys and basic operation of the keyboard processor. The BAT takes from
300 to 500 ms to complete.
If the keyboard fails the BAT, an error code is sent to the CPU and the keyboard is disabled until
an input command is received. After successful completion of the POR and BAT, a completion
code (AAh) is sent to the CPU and the scanning process begins.
The keyboard processor includes a 16-byte FIFO buffer for holding scan codes until the system is
ready to receive them. Response and typematic codes are not buffered. If the buffer is full (16
bytes held) a 17th byte of a successive scan code results in an overrun condition and the overrun
code replaces the scan code byte and any additional scan code data (and the respective key
strokes) are lost. Multi-byte sequences must fit entirely into the buffer before the respective
keystroke can be registered.
C-2
Compaq Personal Computers
Changed - November 1996
Technical Reference Guide
C.2.1
TRANSMISSIONS TO THE SYSTEM
The keyboard processor sends two main types of data to the system; commands (or responses to
system commands) and keystroke scan codes. Before the keyboard sends data to the system
(specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data
lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and
loads the data into a buffer. Once the inhibited state is removed, the data is sent to the system.
Keyboard-to-system transfers consist of 11 bits as shown in Figure C-2.
Start
Bit
0
D0
(LSb)
0
D1
D2
D3
D4
D5
D6
0
0
1
1
1
1
D7
(MSb)
1
Parity
0
Stop
Bit
0
Data
Clock
Ts
Tcy
Th
Tcl Tch
Parameter
Tcy (Cycle Time)
Tcl (Clock Low)
Tch (clock High)
Th (Data Hold)
Ts (Data Setup)
Minimum
60 us
30 us
30 us
45 us
8 us
Maximum
80 us
35 us
45 us
62 us
14 us
Figure C–2. Keyboard-To-System Transmission of Code 58h, Timing Diagram
The system can halt keyboard transmission by setting the clock signal low. The keyboard checks
the clock line every 60 us to verify the signal state. If a low is detected, the keyboard will finish
the current transmission if the rising edge of the clock pulse for the parity bit has not occurred.
The enhanced keyboard has three operating modes:
♦
♦
♦
Mode 1 - PC-XT compatible
Mode 2 - PC-AT compatible (default)
Mode 3 - Select mode (keys are programmable as to make-only, break-only, typematic)
Modes can be selected by the user or set by the system. Mode 2 is the default mode. Each mode
produces a different set of scan codes. When a key is pressed, the keyboard processor sends that
key’s make code to the 8042 logic of the system unit. The When the key is released, a release
code is transmitted as well (except for the Pause key, which produces only a make code). The
8042-type logic of the system unit responds to scan code reception by asserting IRQ1, which is
processed by the interrupt logic and serviced by the CPU with an interrupt service routine. The
service routine takes the appropriate action based on which key was pressed.
Compaq Personal Computers
Changed - November 1996
C-3
Appendix C Keyboard
C.2.2
KEYBOARD LAYOUTS
C.2.2.1
Standard Enhanced Keyboards
1
18
17
2
3
4
5
19
20
21
22
40
39
59
41
60
75
61
76
92
42
43
62
77
6
23
44
63
78
24
45
64
79
7
25
46
65
80
93
8
26
47
66
81
9
27
48
67
82
11
28
29
50
49
68
83
10
30
51
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
71
85
94
13
31
70
69
84
12
87
86
96
95
100
38
58
91
97
98
99
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
101
Figure C–3. U.S. English (101-Key) Keyboard Key Positions
1
17
39
59
75
92
18
2
3
4
5
19
20
21
22
40
41
60
42
61
104 76
77
43
62
78
6
23
44
63
79
7
24
45
64
80
93
8
25
46
65
81
94
9
26
47
66
82
27
48
67
83
10
11
28
29
50
49
68
84
69
85
12
13
31
51
70 103
71
87
86
95
96
Figure C–4. National (102-Key) Keyboard Key Positions
C-4
Compaq Personal Computers
Changed - November 1996
97
98
99
100
38
58
91
101
Technical Reference Guide
C.2.2.2
Windows Enhanced Keyboards
1
18
17
39
2
3
4
5
19
20
21
22
59
8
47
46
27
48
67
66
81
80
9
26
25
65
64
93
110
24
45
44
79
78
7
23
63
62
77
76
43
42
61
60
75
92
41
40
6
94
11
28
29
50
49
68
83
82
10
95
13
31
30
51
70
69
84
12
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
71
85
87
86
96
111 112
97
98
99
100
38
58
91
101
Figure C–5. U.S. English Windows (101W-Key) Keyboard Key Positions
1
17
39
18
2
3
4
5
19
20
21
22
40
41
42
43
6
7
23
44
24
45
8
25
46
9
26
47
27
48
10
11
28
29
50
49
12
13
31
51
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
71
59
75
92
60
104 76
110
61
77
93
62
78
63
79
64
65
80
94
81
66
82
67
83
68
84
95
69
70 103
85
87
86
111 112
96
97
98
99
100
38
58
91
101
Figure C–6. National Windows (102W-Key) Keyboard Key Positions
Compaq Personal Computers
Changed - November 1996
C-5
Appendix C Keyboard
C.2.2.3
Windows Enhanced Keyboards w/Erase-Ease
1
18
17
39
2
3
4
5
19
20
21
22
59
93
110
45
44
8
47
46
113
27
48
67
66
81
80
9
26
25
65
64
79
78
7
24
23
63
62
77
76
43
42
61
60
75
92
41
40
6
94
11
28
29
50
49
68
83
82
10
95
13
31
30
51
70
69
84
12
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
71
85
87
86
96
111 112
97
98
99
100
38
58
91
101
Figure C–7. U.S. English Windows (101WE-Key) Keyboard Key Positions
1
17
39
18
2
3
4
5
19
20
21
22
40
41
42
43
6
23
44
7
24
45
8
25
46
9
26
47
27
48
10
11
28
29
50
49
12
13
31
51
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
71
59
75
92
60
104 76
110
61
77
93
62
78
63
79
64
80
113
65
81
66
82
94
67
83
68
84
95
69
70 103
85
87
86
111 112
96
97
98
Figure C–8. National Windows (102WE-Key) Keyboard Key Positions
C-6
Compaq Personal Computers
Changed - November 1996
99
100
38
58
91
101
Technical Reference Guide
C.2.3
KEYS
All keys generate a make code (when pressed) and a break code (when released) with the
exception of the Pause key (pos. 16), which produces a make code only. All keys, again, with
the exception of the Pause key, are also typematic, although the typematic action of the Shift,
Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the BIOS.
Typematic keys, when held down, send the make code repetitively at a predetermined rate until
the key is released. If two keys are held down, the last key pressed will be typematic.
C.2.3.1
Special Single-Keystroke Functions
The following keys provide the intended function in most applications and environments.
Caps Lock - The Caps Lock key (pos. 59), when pressed and released, invokes a BIOS
routine that turns on the caps lock LED and shifts into upper case key positions 40-49, 60-68,
and 76-82. When pressed and released again, these keys revert to the lower case state and the
LED is turned off. Use of the Shift key will reverse which state these keys are in based on the
Caps Lock key.
Num Lock - The Num Lock key (pos. 32), when pressed and released, invokes a BIOS routine
that turns on the num lock LED and shifts into upper case key positions 55-57, 72-74, 88-90,
100, and 101. When pressed and released again, these keys revert to the lower case state and the
LED is turned off.
The following keys provide special functions that require specific support by the application.
Print Scrn - The Print Scrn (pos. 14) key can, when pressed, generate an interrupt that
initiates a print routine. This function may be inhibited by the application.
Scroll Lock - The Scroll Lock key (pos. 15) when pressed and released, , invokes a BIOS
routine that turns on the scroll lock LED and inhibits movement of the cursor. When pressed and
released again, the LED is turned off and the function is removed. This keystroke is always
serviced by the BIOS (as indicated by the LED) but may be inhibited or ignored by the
application.
Pause - The Pause (pos. 16) key, when pressed, can be used to cause the keyboard interrupt to
loop, i.e., wait for another key to be pressed. This can be used to momentarily suspend an
operation. The key that is pressed to resume operation is discarded. This function may be ignored
by the application.
The Esc, Fn (function), Insert, Home, Page Up/Down, Delete, and End keys operate at the
discretion of the application software.
Compaq Personal Computers
Changed - November 1996
C-7
Appendix C Keyboard
C.2.3.2
Multi-Keystroke Functions
Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys
in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is
toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower
(normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of
key positions 55-57, 72, 74, 88-90, 100, and 101.
Ctrl - The Ctrl keys (pos. 92/96) can be used in conjunction with keys in positions 1-13, 16, 1734, 39-54, 60-71, and 76-84. The application determines the actual function. Both Ctrl key
positions provide identical functionality. The pressed combination of Ctrl and Break (pos. 16)
results in the generation of BIOS function INT 1Bh. This software interrupt provides a method of
exiting an application and generally halts execution of the current program.
Alt - The Alt keys (pos. 93/95) can be used in conjunction with the same keys available for use
with the Ctrl keys with the exception that position 14 (SysRq) is available instead of position
16 (Break). The Alt key can also be used in conjunction with the numeric keypad keys (pos. 5557, 72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255. The
application determines the actual function of the keystrokes. Both Alt key positions provide
identical functionality.
The combination keystroke of Alt and SysRq results in software interrupt 15h, AX=8500h
being executed. It is up to the application to use or not use this BIOS function.
The Ctrl and Alt keys can be used together in conjunction with keys in positions 1-13, 17-34, 3954, 60-71, and 76-84. The Ctrl and Alt key positions used and the sequence in which they are
pressed make no difference as long as they are held down at the time the third key is pressed. The
Ctrl, Alt, and Delete keystroke combination (required twice if in the Windows environment)
initiates a system reset (warm boot) that is handled by the BIOS.
C-8
Compaq Personal Computers
Changed - November 1996
Technical Reference Guide
C.2.3.3
Windows Keystrokes
Windows-enhanced keyboards include three additional key positions. Key positions 110 and 111
(marked with the Windows logo
) have the same functionality and are used by themselves
or in combination with other keys to perform specific “hot-key” type functions for the Windows
operating system. The defined functions of the Windows logo keys are listed as follows:
Keystroke
Window Logo
Window Logo + F1
Window Logo + TAB
Window Logo + E
Window Logo + F
Window Logo + CTRL + F
Window Logo + M
Shift + Window Logo + M
Window Logo + R
Window Logo + PAUSE
Window Logo + 1-0
Function
Open Start menu
Display pop-up menu for the selected object
Activate next task bar button
Explore my computer
Find document
Find computer
Minimize all
Undo minimize all
Display Run dialog box
Perform system function
Reserved for OEM use (see following text)
The combination keystroke of the Window Logo + 1-0 keys are reserved for OEM use for
auxiliary functions (speaker volume, monitor brightness, password, etc.).
Key position 112 (marked with an application window icon
other keys for invoking Windows application functions.
C.2.3.4
) is used in combination with
Erase-Ease Keystrokes
The Erase-Ease keyboards feature a split space-bar key that operates as two separate keys
(positions 113 and 94). The two keys can be configured for one of three modes:
Mode A:
(Power-on default)
Mode B:
Mode C:
113
94
Backspace
Spacebar
113
94
Spacebar
Backspace
113
94
Spacebar
Spacebar
To switch between modes the user holds down the left ALT, left CTRL, and left Shift keys while
pressing the Erase-Ease (pos. 113) key once.
Compaq Personal Computers
Changed - November 1996
C-9
Appendix C Keyboard
C.2.4
KEYBOARD COMMANDS
Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042type logic).
Table C–1. Keyboard-to-System Commands
Table C-1.
Keyboard-to-System Commands
Command
Key Detection Error/Over/run
BAT Completion
BAT Failure
Echo
Acknowledge (ACK)
Resend
Keyboard ID
Value
00h [1]
FFh [2]
AAh
FCh
EEh
FAh
FEh
83ABh
Description
Indicates to the system that a switch closure couldn’t be
identified.
Indicates to the system that the BAT has been successful.
Indicates failure of the BAT by the keyboard.
Indicates that the Echo command was received by the
keyboard.
Issued by the keyboard as a response to valid system
inputs (except the Echo and Resend commands).
Issued by the keyboard following an invalid input.
Upon receipt of the Read ID command from the system, the
keyboard issues the ACK command followed by the two IDS
bytes.
Note:
[1] Modes 2 and 3.
[2] Mode 1 only.
C.2.5
SCAN CODES
The scan codes generated by the keyboard processor are determined by the mode the keyboard is
operating in.
♦
Mode 1:
In Mode 1 operation, the keyboard generates scan codes compatible with 8088/8086-based systems. To enter Mode 1, the scan code translation function of the keyboard
controller must be disabled. Since translation is not performed, the scan codes generated in
Mode 1 are identical to the codes required by BIOS. Mode 1 is initiated by sending command
F0h with the 01h option byte. Applications can obtain system codes and status information
by using BIOS function INT 16h with AH=00h, 01h, and 02h.
♦
Mode 2:
Mode 2 is the default mode for keyboard operation. In this mode, the 8042 logic
translates the make codes from the keyboard processor into the codes required by the BIOS.
This mode was made necessary with the development of the Enhanced III keyboard, which
includes additional functions over earlier standard keyboards. Applications should use BIOS
function INT 16h, with AH=10h, 11h, and 12h for obtaining codes and status data. In Mode
2, the keyboard generates the Break code, a two-byte sequence that consists of a Make code
immediately preceded by F0h (i.e., Break code for 0Eh is “F0h 0Eh”).
♦
Mode 3:
Mode 3 generates a different scan code set from Modes 1 and 2. Code
translation must be disabled since translation for this mode cannot be done.
C-10 Compaq Personal Computers
Changed - November 1996
Technical Reference Guide
Table C–2. Keyboard Scan Codes
Table C-2.
Keyboard Scan Codes
Key
Pos.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
Esc
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
Print Scrn
15
16
Scroll Lock
Pause
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
`
1
2
3
4
5
6
7
8
9
0
=
\
Backspace
Insert
33
Home
34
Page Up
35
36
Num Lock
/
37
38
39
40
*
Tab
Q
Mode 1
01/81
3B/BB
3C/BC
3D/BD
3E/BE
3F/BF
40/C0
41/C1
42/C2
43/C3
44/C4
57/D7
58/D8
E0 2A E0 37/E0 B7 E0 AA
E0 37/E0 B7 [1] [2]
54/84 [3]
46/C6
E1 1D 45 E1 9D C5/na
E0 46 E0 C6/na [3]
29/A9
02/82
03/83
04/84
05/85
06/86
07/87
08/88
09/89
0A/8A
0B/8B
0C/8C
0D/8D
2B/AB
0E/8E
E0 52/E0 D2
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 52/E0 D2 E0 AA [6]
E0 47/E0 C7
E0 AA E0 52/E0 C7 E0 2A [4]
E0 2A E0 47/E0 C7 E0 AA [6]
E0 49/E0 C9
E0 AA E0 49/E0 C9 E0 2A [4]
E0 2A E0 49/E0 C9 E0 AA [6]
45/C5
E0 35/E0 B5
E0 AA E0 35/E0 B5 E0 2A [1]
37/B7
4A/CA
0F/8F
10/90
Make / Break Codes (Hex)
Mode 2
76/F0 76
05/F0 05
06/F0 06
04/F0 04
0C/F0 0C
03/F0 03
0B/F0 0B
83/F0 83
0A/F0 0A
01/FO 01
09/F0 09
78/F0 78
07/F0 07
E0 2A E0 7C/E0 F0 7C E0 F0 12
E0 7C/E0 F0 7C [1] [2]
84/F0 84 [3]
7E/F0 7E
E1 14 77 E1 F0 14 F0 77/na
E0 7E E0 F0 7E/na [3]
0E/F0 E0
16/F0 16
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5D/F0 5D
66/F0 66
E0 70/E0 F0 70
E0 F0 12 E0 70/E0 F0 70 E0 12 [5]
E0 12 E0 70/E0 F0 70 E0 F0 12 [6]
E0 6C/E0 F0 6C
E0 F0 12 E0 6C/E0 F0 6C E0 12 [5]
E0 12 E0 6C/E0 F0 6C E0 F0 12 [6]
E0 7D/E0 F0 7D
E0 F0 12 E0 7D/E0 F0 7D E0 12 [5]
E0 12 E0 7D/E0 F0 7D E0 F0 12 [6]
77/F0 77
E0 4A/E0 F0 4A
E0 F0 12 E0 4A/E0 F0 4A E0 12 [1]
7C/F0 7C
7B/F0 7B
0D/F0 0D
15/F0 15
Mode 3
08/na
07/na
0F/na
17/na
1F/na
27/na
2F/na
37/na
3F/na
47/na
4F/na
56/na
5E/na
57/na
5F/na
62/na
0E/F0 0E
46/F0 46
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5C/F0 5C
66/F0 66
67/na
6E/na
6F/na
76/na
77/na
7E/na
84/na
0D/na
15/na
Continued
([x] Notes listed at end of table.)
Compaq Personal Computers
Changed - November 1996
C-11
Appendix C Keyboard
Table C-2. Keyboard Scan Codes (Continued)
Key
Pos
41
42
43
44
45
46
47
48
49
50
51
52
Legend
W
E
R
T
Y
U
I
O
P
[
]
Delete
53
End
54
Page Down
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
7
8
9
+
Caps Lock
A
S
D
F
G
H
J
K
L
;
‘
Enter
4
5
6
Shift (left)
Z
X
C
V
B
Make / Break Codes (Hex)
Mode 1
Mode 2
11/91
1D/F0 1D
12/92
24/F0 24
13/93
2D/F0 2D
14/94
2C/F0 2C
15/95
35/F0 35
16/96
3C/F0 3C
17/97
43/F0 43
18/98
44/F0 44
19/99
4D/F0 4D
1A/9A
54/F0 54
1B/9B
5B/F0 5B
E0 71/E0 F0 71
E0 53/E0 D3
E0 F0 12 E0 71/E0 F0 71 E0 12 [5]
E0 AA E0 53/E0 D3 E0 2A [4]
E0 12 E0 71/E0 F0 71 E0 F0 12 [6]
E0 2A E0 53/E0 D3 E0 AA [6]
E0 69/E0 F0 69
E0 4F/E0 CF
E0 F0 12 E0 69/E0 F0 69 E0 12 [5]
E0 AA E0 4F/E0 CF E0 2A [4]
E0 12 E0 69/E0 F0 69 E0 F0 12 [6]
E0 2A E0 4F/E0 CF E0 AA [6]
E0 7A/E0 F0 7A
E0 51/E0 D1
E0 F0 12 E0 7A/E0 F0 7A E0 12 [5]
E0 AA E0 51/E0 D1 E0 2A [4]
E0 12 E0 7A/E0 F0 7A E0 F0 12 [6]
E0 @a E0 51/E0 D1 E0 AA [6]
47/C7 [6]
6C/F0 6C [6]
48/C8 [6]
75/F0 75 [6]
49/C9 [6]
7D/F0 7D [6]
4E/CE [6]
79/F0 79 [6]
3A/BA
58/F0 58
1E/9E
1C/F0 1C
1F/9F
1B/F0 1B
20/A0
23/F0 23
21/A1
2B/F0 2B
22/A2
34/F0 34
23/A3
33/F0 33
24/A4
3B/F0 3B
25/A5
42/F0 42
26/A6
4B/F0 4B
27/A7
4C/F0 4C
28/A8
52/F0 52
1C/9C
5A/F0 5A
4B/CB [6]
6B/F0 6B [6]
4C/CC [6]
73/F0 73 [6]
4D/CD [6]
74/F0 74 [6]
2A/AA
12/F0 12
2C/AC
1A/F0 1A
2D/AD
22/F0 22
2E/AE
21/F0 21
2F/AF
2A/F0 2A
30/B0
32/F0 32
Mode 3
1D/F0 1D
24/F0 24
2D/F0 2D
2C/F0 2C
35/F0 35
3C/F0 3C
43/F0 43
44/F0 44
4D/F0 4D
54/F0 54
5B/F0 5B
64/F0 64
65/F0 65
6D/F0 6D
6C/na [6]
75/na [6]
7D/na [6]
7C/F0 7C
14/F0 14
1C/F0 1C
1B/F0 1B
23/F0 23
2B/F0 2B
34/F0 34
33/F0 33
3B/F0 3B
42/F0 42
4B/F0 4B
4C/F0 4C
52/F0 52
5A/F0 5A
6B/na [6]
73/na [6]
74/na [6]
12/F0 12
1A/F0 1A
22/F0 22
21/F0 21
2A/F0 2A
32/F0 32
Continued
([x] Notes listed at end of table.)
C-12 Compaq Personal Computers
Changed - November 1996
Technical Reference Guide
Table C-2. Keyboard Scan Codes (Continued)
Key
Pos.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
Legend
N
M
,
.
/
Shift (right)
1
2
3
Enter
Ctrl (left)
Alt (left)
(Space)
Alt (right)
Ctrl (right)
98
99
100
101
102
103
104
110
0
.
na
na
na
(Win95) [7]
111
(Win95) [7]
112
(Win Apps)
[7]
113
(EraseEase) [8]
Make / Break Codes (Hex)
Mode 1
Mode 2
31/B1
31/F0 31
32/B2
3A/F0 3A
33/B3
41/F0 41
34/B4
49/F0 49
35/B5
4A/F0 4A
36/B6
59/F0 59
E0 75/E0 F0 75
E0 48/E0 C8
E0 F0 12 E0 75/E0 F0 75 E0 12 [5]
E0 AA E0 48/E0 C8 E0 2A [4]
E0 12 E0 75/E0 F0 75 E0 F0 12 [6]
E0 2A E0 48/E0 C8 E0 AA [6]
4F/CF [6]
69/F0 69 [6]
50/D0 [6]
72/F0 72 [6]
51/D1 [6]
7A/F0 7A [6]
E0 1C/E0 9C
E0 5A/F0 E0 5A
1D/9D
14/F0 14
38/B8
11/F0 11
39/B9
29/F0 29
E0 38/E0 B8
E0 11/F0 E0 11
E0 1D/E0 9D
E0 14/F0 E0 14
E0 6B/Eo F0 6B
E0 4B/E0 CB
E0 F0 12 E0 6B/E0 F0 6B E0 12[5]
E0 AA E0 4B/E0 CB E0 2A [4]
E0 12 E0 6B/E0 F0 6B E0 F0 12[6]
E0 2A E0 4B/E0 CB E0 AA [6]
E0 72/E0 F0 72
E0 50/E0 D0
E0 F0 12 E0 72/E0 F0 72 E0 12[5]
E0 AA E0 50/E0 D0 E0 2A [4]
E0 12 E0 72/E0 F0 72 E0 F0 12[6]
E0 2A E0 50/E0 D0 E0 AA [6]
E0 74/E0 F0 74
E0 4D/E0 CD
E0 F0 12 E0 74/E0 F0 74 E0 12[5]
E0 AA E0 4D/E0 CD E0 2A [4]
E0 12 E0 74/E0 F0 74 E0 F0 12[6]
E0 2A E0 4D/E0 CD E0 AA [6]
52/D2 [6]
70/F0 70 [6]
53/D3 [6]
71/F0 71 [6]
7E/FE
6D/F0 6D
2B/AB
5D/F0 5D
36/D6
61/F0 61
E0 1F/E0 F0 1F
E0 5B/E0 DB
E0 F0 12 E0 1F/E0 F0 1F E0 12 [5]
E0 AA E0 5B/E0 DB E0 2A [4]
E0 12 E0 1F/E0 F0 1F E0 F0 12 [6]
E0 2A E0 5B/E0 DB E0 AA [6]
E0 2F/E0 F0 27
E0 5C/E0 DC
E0 F0 12 E0 27/E0 F0 27 E0 12 [5]
E0 AA E0 5C/E0 DC E0 2A [4]
E0 12 E0 27/E0 F0 27 E0 F0 12 [6]
E0 2A E0 5C/E0 DC E0 AA [6]
E0 2F/E0 F0 2F
E0 5D/E0 DD
E0 F0 12 E0 2F/E0 F0 2F E0 12 [5]
E0 AA E0 5D/E0 DD E0 2A [4]
E0 12 E0 2F/E0 F0 2F E0 F0 12 [6
E0 2A E0 5D E0 DD E0 AA [6]
0E/8E
66/F0 66
Mode 3
31/F0 31
3A/F0 3A
41/F0 41
49/F0 49
4A/F0 4A
59/F0 59
63/F0 63
69/na [6]
72/na [6]
7A/na [6]
79/F0 79[6]
11/F0 11
19/F0 19
29/F0 29
39/na
58/na
61/F0 61
60/F0 60
6A/F0 6A
70/na [6]
71/na [6]
7B/F0 7B
53/F0 53
13/F0 13
8B/F0 8B
8C/F0 8C
8D/F0 8D
66/na
NOTES:
All codes assume Shift, Ctrl, and Alt keys inactive unless otherwise noted.
NA = Not applicable
[1] Shift (left) key active.
[2] Ctrl key active.
[3] Alt key active.
[4] Left Shift key active. For active right Shift key, substitute AA/2A make/break codes for B6/36 codes.
[5] Left Shift key active. For active right Shift key, substitute F0 12/12 make/break codes
for F0 59/59 codes.
[6] Num Lock key active.
[7] Windows keyboards only
[8] Erase-Ease keyboards only
Compaq Personal Computers
Changed - November 1996
C-13
Appendix C Keyboard
C.3
SCANNER DESCRIPTION
The scanner keyboard, available as an option, integrates a scanner with a SpaceSaver Windows
’95 keyboard, providing the ability to scan hardcopy looseleaf documents for faxing or electronic
storage. The scanner provides resolutions up to 400 dpi and 256 shades of gray and outputs
through a standard serial interface to the system unit. Using optical character recognition (OCR)
support software, printed textual data can be converted into editable files.
Operation of the scanner starts automatically when a sheet is inserted into the Contact Image
Sensor (CIS). A button on the left side of the keyboard allows then operator to open a menu, halt
scanning in progress, or invoke a serial port test. Figure C-9 shows a block diagram of the key
scanner elements.
CIS
and Paper Drive
Analog
Video
Data
M64290FP
Analog
Processor
Clocks & LED
Motor Cntrl.
32 KB
RAM
Digital
Processor
Serial Data
COM Port
(System Unit)
Digital Video Data
Cntrl.
24 VDC
24 VDC
Power
Supply
Keyboard Unit
Figure C–9. Scanner Elements, Block Diagram
The Contact Image Sensor (CIS) and paper drive unit handles the hardcopy input. As each sheet
is placed into the input slot, the sheet activates the mechanism and is drawn through and scanned
by an LED illumination/photodiode sensor array. The drive motor provides 96 steps per
revolution (3.75 degress per step) and is geared for 0.005 inch document movement per step for a
resolution of 200 dpi. Half-stepping provides 400 dpi vertical resolution.
An analog video data stream is developed and routed to the Digital-to-Analog (D/A) Processor
for conversion to digital video data that is routed to the Digital Processor. The Digital Processor
provides most of the control of the scanner operation. A 32-KB RAM provides storage of
executable code, pixel-to-pixel correction values, image processing line/diffusion data, and
transmission data buffering.
The scanner elements are powered from an external 24 VDC power supply. Internal components
use +5, +9, and -12 VDC.
C-14 Compaq Personal Computers
Changed - November 1996
Technical Reference Guide
C.3.1
SCANNER OPERATION
The scanner requires minimum user interface for normal operation. Insertion of a sheet of
hardcopy activates the scanner. Operating parameters such as resolution, brightness, and motor
speed are programmable for optimum performance. Other characteristics such as gamma
correction, modulation transfer function (MTF), image compression, and pixel normalization are
optimized through the use of pre-computed tables that are downloaded for image correction and
adjustments when necessary.
The user interface is provided through a button located to the left of the sheet insertion tray. This
normally-open switch provides the following functions depending on when pressed:
When Pressed
During Power-Up
Function
Scanner enters communications loopback mode. Mode remains in
effect until the next power cycle (cold boot).
Scanner at idle
Actives a menu for changing/viewing parameters.
During a scan
Aborts the scan and reverses the motor, backing the document out
of the scanner.
An inserted document activates one or more of five sensing fingers mounted on a shaft. The shaft
begins rotation, turning an opaque flag that breaks an opto-interrupter beam between an LED
and a phototransistor. The paper sensor signal goes active high, initiating the Digital Processor
to begin the scanning process.
An LED/phototransistor assembly similar to the paper sensor is used for skew control. Sensing
fingers on each side of the paper path check for misalignment (skew) of the document as it is
pulled through the scan area. If the document comes in contact with one of the sensor fingers, an
opaque flag is engaged to rotate, blocking an opto-interrupter beam and initiating an abort
sequence. The skew LEDs , along with the LEDs used for scanning, are only powered up during
the scan operation (i.e., while a document is in the scanner).
A flow chart of the scanning operation is shown in Figure C-10. Photo-Response Non-Uniformity
(PRNU) refers to the fact that not every photosensor in the CIS has the same sensitivity. The
PRNU correction stage adjusts for each photosensor’s sensistivity level by applying a unique
offset and gain value for it. A calibration procedure (initially done at the factory) is used to
determine the compensation values for the photo array of the CIS. This data is stored in the
CALIBRAT.DAT file on the installation disk and copied to the system unit’s hard drive. The
data is downloaded to the scanner after power up.
The modulation transfer function (MTF) of the optical system and document motion is corrected
by downloading the MTF compensation parameters from the system unit to improve the quality
of the scanned image.
Compaq Personal Computers
Changed - November 1996
C-15
Appendix C Keyboard
Start
Scan Image
(Image Aquisition)
PRNU
Correction
MTF
Correction
Resolution
Conversion
Threshold
Output
Desired?
Yes
Threshold (Intel.)
Algorithm
No
Gamma
Conversion
Halftone
Output
Desired?
No
Grayscale
Compensation
Yes
Type
of
Halftone
Error
Diffusion
Error Diffusion
Algorithm
Pattern Dither
Pattern Dither
Algorithm
Packetized &
Sent to Host
Finish
Figure C–10. Scanner operation Flow Chart
C-16 Compaq Personal Computers
Changed - November 1996
Bi-Level
Compensation
Technical Reference Guide
C.3.1.1
Resolution/Shade Depth
The drive motor mechanism of the CIS supports a vertical resolution of 400 dpi. The CIS
provides a maximum horizontal resolution of 200 dpi. These factors provide true spatial
resolutions of 100 and 200 dpi. Using horizontal interpolation, pseudo 300 and 400 dpi spatial
resolutions are possible. Shade depth is determined by the number of bits used to control each
pixel. The bits per pixel (bpp) parameter can be set to one (for black and white), two, four, or
eight (for 256 shades of gray).
The selected resolution/shade depth determines the scanning time of a given sheet. Table C-3
lists the approximate scanning times for a standard 11 inch sheet using specified resolution/shade
depths based on the line integration time of 2.5 ms.
Table C–3. Scanner Performance Chart
Table C-3.
Scanner Performance Chart
Scan Time for 11” Page
X/Y
DPI
1 bpp
4 bpp
8 bpp
100 / 100
100
7 sec
11 sec
14 sec
200 / 200
200
7 sec
27 sec
36 sec
200 / 300
300 (Pseudo)
12 sec
60 sec
60 sec
200 / 400
400 (Pseudo)
17 sec
62 sec
80 sec
NOTE:
Scan times measured on a Pentium/90-based system with 16 MB RAM.
C.3.1.2
Image Quality
Brightness is fully programmable and independently adjustable using either normal or intelligent
methods. The normal method slices each gray scale pixel into either black or white depending
on the threshold value selected. The intelligent method automatically adjusts the pixel to the
background for the best detail.
The grayscale transfer function can be tailored by gamma correction values that are downloaded
from the system. This function can be disabled if desired.
Compensation for the Modulation Transfer Function (MTF) of the optical system and document
motion is provided for improving image quality. The MTF parameters are /downloaded from the
host if (if enabled).
Image compression is provided through a table-driven compressor. Compression values are
loadable from the host and used by one of two types of algorithms: Huffman DPCM for 2- to 8-bit
grayscale images, and a proprietary 1-bit compression.
Compaq Personal Computers
Changed - November 1996
C-17
Appendix C Keyboard
C.3.2
SCANNER INTERFACE
The scanner communicates with the system unit (host) using a serial port as the primary choice
of connection. The scanner interface is adaptable to several types of host connections as shown in
Table C-4 (unshaded portion describes standard scanner interface with Compaq system unit).
Table C–4. Scanner I/F Signals
Table C-4.
Scanner I/F Signals
Scanner Signals
Pnyb
Mser
Mode
Mode
P0
SCLK
P1
P2
P3
PCLK
DTR
SOUT
TXD
GND
-PnP
RXD
Serial Port (PC)
RS232
DB9
DB25
Signal
Pin
Pin
CTS
8
5
DSR
6
6
RI
9
22
DCD
1
8
DTR
4
20
RTS
7
4
GND
5
7
-2
3
Parallel Port
DB25
Signal
Pin
Select
13
Paper Out
12
Ack
10
Busy
11
Strobe
1
Init
16
GND
18
---
Serial Port (MacIntosh)
DIN8
Signal
Pin
HSKIn
2
------HSKOut
1
TXD
6
GND/RXD+
4/8
RXD5
Optional interface configuration.
The scanner uses one of two communication modes; Pnyb and Mser. The scanner selects the
mode based on the idle status of the DTR/PCLK signal. If detected in a low state, the scanner
uses the Pnyb mode. If PCLK is detected in a high state at idle, then the Mser mode is used.
Switching between the Pnyb and Mser modes is automatic and transparent to the operating
system and application. This allows the scanner to be configured through an A/B box to two
systems using different interfaces. The system unit (host) must drive the DTR signal at the
appropriate level for at least 20 us before transmitting data packets.
A packet consists of an exchange of one or more bytes between the scanner and the host. A
session is an exchange of packets between the scanner and the host. A session begins with a
single-byte packet called a wakeup code and ends with the transfer of an acknowledgment (ACK)
of the last packet received. Either the scanner or the host can initiate a session, and a session can
be ended or cancelled by the scanner or the host, regardless of which initiated the session. A
session is restricted to the action specified in the wakeup code.
C-18 Compaq Personal Computers
Changed - November 1996
Technical Reference Guide
C.3.2.1
Pnyb Mode
In the parallel nibble or “Pnyb” mode, the scanner transfers scanned information to the system
unit (host) four bits (a nibble) at a time using the P3..P0 signals, which conform to RS-232
voltage and timing specifications. The P3..P0 signals are mapped to bits <7..4> respectively of
the Modem Status Register (primary address 3FEh). The nibbles are clocked into the host with
each transition of the PCLK signal. PCLK transitions from low to high clock in a high nibble,
which transitions from high to low clock in a low nibble. The host can assume a nibble from the
scanner is ready to be read 3.3 us after the PCLK transition requesting it. At the end of a
scanner-to-host packet transfer, the host toggles the PCLK signal an extra time (0-to-1-to-0).
This extra toggle indicates to the scanner that the last nibble has been read and sets the P3..P0
lines signals to a waiting state.
Data from the system unit (host) is transferred serially (bit-by-bit) as the SO signal along with the
PCLK signal. A data bit is clocked with each transition of the PCLK signal so that a byte is
transferred with four PCLK cycles. These signals also conform to RS-232 voltage and timing
specifications and are mapped at bits <1,0> of the Modem Control Register (primary address
3FCh). The scanner can read data as long as the setup time is at least 1 us and the hold time is at
least 3.3 us. The host must allow an additional 50 us after sending the LSb of each of the first
five bytes of a multi-byte packet to the scanner. During host-to-scanner transfers, the scanner
uses the P3..P0 lines for indicating transmission status to the host.
In the Pnyb mode, the host must insure that the high state of the first PCLK cycle of a session
completes in less than 10 us so that the scanner does not interpret a Mser mode transfer.
C.3.2.2
Mser Mode (MacIntosh Connection Only)
The MacIntosh Serial or “Mser” mode uses bit-serial transfers for both scanner-to-host (RXD
signal) as well as host-to-scanner (TXD signal) transfers. Transfers are accomplished using 10bit frames that consist of a start bit, a data byte (LSb first), and a stop bit. The clock (SCLK)
signal is provided by the scanner. The Mser mode is similar to isochronous transmission.
Compaq Personal Computers
Changed - November 1996
C-19
Appendix C Keyboard
C.3.3
SCANNER SPECIFICATIONS/REQUIREMENTS
Table C–5. Scanner Specifications
Table C-5.
Scanner Specifications
Parameter
Specification [1]
Dimensions (Complete keyboard unit):
20.5 in (52.07 cm)
Width
2.5 in (6.35 cm)
Height
9 in (22.86 cm)
Depth
Weight (Complete keyvoard unit)
10.1 lb (4.58 kg)
Scanner Paper Sizes:
Minimum
2.0 x 3.0 in (5.1 x 7.6 cm)
Maximum
8.5 x 30 in 21.6 x 76.2 cm)
Maximum Scanned Resolution (input)
2400 x 2400 dpi
Maximum Scanning Resolution (output)
400 dpi
Maximum Scan Time (8.5 x 11” sheet)
6 seconds [2]
Power Requirements (Scanner only):
Input Voltage
24 VDC
Maximum Current Drain (scanning)
990 ma
Environmental Conditions:
50°-104° F (10°-40° C)
Tempurature, operating
-4°-140° F (-20°-60° C)
Tempurature, non-operating
20-80% RH
Humidity, operating
5-95% RH
Humidity, non-operating
NOTE:
[1] Metric numbers shown in parenthesis.
[2] Based on Pentium/90-based system w/16 MB RAM
The scanner imposes the following requirements on the host system:
♦
♦
♦
♦
♦
486 or better microprocessor
Serial port
Windows 3.1, Windows for Workgroups 3.11, or Windows 95 or later
4 megabytes of RAM (8 megabytes recommended)
50 megabytes free disk space
C-20 Compaq Personal Computers
Changed - November 1996
Technical Reference Guide
INDEX
I.
abbreviations, 1-3
acronyms, 1-3
administrator password, 4-44
analog-to-digital converter (ADC), D-4
APM BIOS functions, 8-19
architecture, system, 2-8
ASCII character set, B-1
AT attachment (ATA), 5-3
audio card, D-1
battery replacement, 4-25
BIOS ROM, 2-10
BIOS, graphics, 6-2
BIOS, ROM, 8-1
boot block ROM, 8-2
bus frequency, 3-4
Bus Masters (PCI), 4-3
bus/core speed configuration, 3-4
bus/core speed ratio, 3-4
cache, L1, L2, 2-10
cache, secondary (L2), 3-5
Client Management BIOS function, 8-5
clock distribution, 4-23
CMOS, 4-24
CMOS, accessing, 8-3
configuration (ISA), 4-22
Configuration Cycle, 4-5
configuration memory, 4-24
Connector
Audio, CD, D-3
Audio, Headphone Out, D-2
Audio, Line In, D-2
Audio, Line Out, D-2
Audio, Mic In, D-2
Audio, Speaker, D-3
diskette drive interface, 5-13
display (monitor), 6-6
IDE interface, 5-8
IDE/diskette drive power, 7-3
ISA bus, 4-12
keyboard/pointing device interface, 5-33
parallel interface, 5-26
PCI bus, 4-10
serial interface (RS-232), 5-14
Universal Serial Bus interface, 5-35
VGA pass-through (feature), 6-4, 6-5
digital-to-analog converter (DAC), D-5
DIMM sockets, 3-2
DIMM support, 8-13
diskette drive interface, 5-9
DMA, 4-15
drive fault prediction, 8-12
EIDE interface, 5-1
Enhanced Parallel Port (EPP), 5-21
error codes, A-1
error messages, A-1
expansion module, graphics memory, 6-5
Extended Capabilities Port (ECP), 5-21
features, standard, 2-2
flash ROM, 4-44
floating point unit (math coprocessor), 3-3
FM synthesis, D-7
GPIO, 3-4
graphics controller, 6-2
graphics subsystem, 6-1
hard drive spindown, 4-45
Host bus, 2-8
I/O map, 4-41
I2C bus, 3-6
IDE interface, 5-1
index addressing, 1-2
integrated graphics controller, 6-2
interrupts
maskable (IRQn), 4-18
nonmaskable (NMI, SMI), 4-20
interrupts, PCI, 4-8
interval timer, 4-22
ISA bus, 2-8
ISA bus, overview, 4-11
jumper, power-on password disable, 4-44
key (keyboard) functions, C-7
keyboard, C-1
keyboard (micro)processor, C-2
keyboard layouts, C-4
keyboard/pointing device interface, 5-27
math coprocessor, 3-3
media write protect function (BIOS), 8-15
memory map
586-based system, 3-8
Compaq Deskpro 2000 Personal Computers
with MMX Technology
First Edition – July 1997
I-1
Index
scan codes (keyboard), C-10
scanner keyboard, C-14
SCSI adapter, 5-34
SDRAM performance times, 3-6
security features, 4-44
serial interface, 5-14
serial presence detect (SPD), 3-6
SGRAM, 6-2
signal distribution, 7-5
SilentBoot, 8-2
sockets, DIMM, 3-2
special cycles (PCI), 4-7
specifications
electrical, 2-13
environmental, 2-13
physical, 2-13
power supply, 7-5
scanner (keyboard), C-20
Specifications
8x CD-ROM Drive, 2-14
Diskette Drive, 2-14, D-11
Hard Drive, 2-16
system board, 2-7
system ID, 8-7
system information table (SIT), 8-7
system management, 4-44
system memory, 2-10
system ROM, 2-10, 8-1
temperature sensor, 8-12
timer, interval, 4-22
UART, 5-14
Universal Serial Bus (USB) interface, 5-34
ZIF socket, 3-2, 3-3
memory, cache (SRAM), 2-10
memory, ROM (BIOS), 2-10
memory, system (RAM), 2-10
microprocessor, Pentium MMX, 3-3
MMX technology, 3-3
monitor power control, 4-46
MPEG, 6-2
notational conventions, 1-2
Options, 2-3
parallel interface, 5-20
password, administrator, 4-44
password, power-on, 4-44
PCI bus, 2-8, 2-11
PCI bus, overview, 4-2
PCI Configuration Space, 4-6
PCI interrupts, 4-8
PCI/ISA bridge, 4-3
PCM audio processing, D-4
Pentium MMX microprocessor, 3-3
Plug ’n Play, 2-2, 2-3, 2-12, 8-17
Plug 'n Play BIOS function, 8-17
power distribution, 7-3
power management, 4-45
Power Management BIOS function, 8-18
power supply, 7-1
power-on password, 4-44
processing speed, selecting, 3-4
QuickBoot, 8-2
QuickLock/QuickBlank, 4-45
RAM, 2-10
reference sources, 1-1
remote flashing, 8-2
ROM BIOS, 8-1
RTC, 4-24
I-2 Compaq Deskpro 2000 Personal Computers
with MMX Technology
First Edition – July 1997