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MCF548x Reference Manual
Devices Supported:
MCF5485
MCF5484
MCF5483
MCF5482
MCF5481
MCF5480
Document Number: MCF5485RM
Rev. 3
01/2006
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© Freescale Semiconductor, Inc. 2006. All rights reserved.
MCF5485RM
Rev. 3
01/2006
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Memory Management Unit (MMU)
Floating-Point Unit (FPU)
Local Memory
Debug Support
System Integration Unit (SIU)
Internal Clocks and Bus Architecture
General Purpose Timers (GPT)
Slice Timers (SLT)
Interrupt Controller (INTC)
Edge Port Module (EPORT)
General Purpose I/O (GPIO)
System SRAM
FlexBus
SDRAM Controller (SDRAMC)
PCI Bus Controller (PCI)
PCI Bus Arbiter (PCIARB)
FlexCAN
Integrated Secuity Engine (SEC)
IEEE 1149.1 Test Access Port (JTAG)
Multichannel DMA (MCD)
Comm Timer Module (CTM)
Programmable Serial Controller (PSC)
I2C interface
DMA Serial Peripheral Interface (DSPI)
USB 2.0 Device Controller
Fast Ethernet Controller (FEC)
Mechanical Data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Register Memory Map Quick Reference
Index
A
IND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
IND
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Memory Management Unit (MMU)
Floating-Point Unit (FPU)
Local Memory
Debug Support
System Integration Unit (SIU)
Internal Clocks and Bus Architecture
General Purpose Timers (GPT)
Slice Timers (SLT)
Interrupt Controller (INTC)
Edge Port Module (EPORT)
General Purpose I/O (GPIO)
System SRAM
FlexBus
SDRAM Controller (SDRAMC)
PCI Bus Controller (PCI)
PCI Bus Arbiter (PCIARB)
FlexCAN
Integrated Secuity Engine (SEC)
IEEE 1149.1 Test Access Port (JTAG)
Multichannel DMA (MCD)
Comm Timer Module (CTM)
Programmable Serial Controller (PSC)
I2C interface
DMA Serial Peripheral Interface (DSPI)
USB 2.0 Device Controller
Fast Ethernet Controller (FEC)
Mechanical Data
Register Memory Map Quick Reference
Index
Contents
Paragraph
Number
Title
Page
Number
Chapter 1
Overview
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.4.1
1.4.4.2
1.4.5
1.4.6
1.4.6.1
1.4.6.2
1.4.6.3
1.4.6.4
1.4.6.5
1.4.6.6
1.4.6.7
1.4.7
1.4.8
1.4.9
1.4.10
1.4.11
1.4.11.1
1.4.11.2
1.4.11.3
MCF548x Family Overview ........................................................................................... 1-1
MCF548x Block Diagram .............................................................................................. 1-2
MCF548x Family Products ............................................................................................. 1-3
MCF548x Family Features ............................................................................................. 1-3
ColdFire V4e Core Overview ..................................................................................... 1-5
Debug Module (BDM) ................................................................................................ 1-6
JTAG ........................................................................................................................... 1-6
On-Chip Memories ..................................................................................................... 1-7
Caches ..................................................................................................................... 1-7
System SRAM ........................................................................................................ 1-7
PLL and Chip Clocking Options ................................................................................ 1-7
Communications I/O Subsystem ................................................................................ 1-8
DMA Controller ...................................................................................................... 1-8
10/100 Fast Ethernet Controller (FEC) ................................................................... 1-8
USB 2.0 Device (Universal Serial Bus) ................................................................. 1-8
Programmable Serial Controllers (PSCs) ............................................................... 1-9
I2C (Inter-Integrated Circuit) ................................................................................. 1-9
DMA Serial Peripheral Interface (DSPI) ................................................................ 1-9
Controller Area Network (CAN) .......................................................................... 1-10
DDR SDRAM Memory Controller ........................................................................... 1-10
Peripheral Component Interconnect (PCI) ............................................................... 1-10
Flexible Local Bus (FlexBus) ................................................................................... 1-10
Security Encryption Controller (SEC) ...................................................................... 1-11
System Integration Unit (SIU) .................................................................................. 1-11
Timers ................................................................................................................... 1-11
Interrupt Controller ............................................................................................... 1-12
General Purpose I/O ............................................................................................. 1-12
Chapter 2
Signal Descriptions
2.1
2.1.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
Introduction ..................................................................................................................... 2-1
Block Diagram ............................................................................................................ 2-1
MCF548x External Signals ........................................................................................... 2-16
FlexBus Signals ........................................................................................................ 2-16
Address/Data Bus (AD[31:0]) .............................................................................. 2-16
Chip Select (FBCS[5:0]) ....................................................................................... 2-17
Address Latch Enable (ALE) ................................................................................ 2-17
MCF548x Reference Manual, Rev. 3
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v
Contents
Paragraph
Number
2.2.1.4
2.2.1.5
2.2.1.6
2.2.1.7
2.2.1.8
2.2.1.9
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.2.5
2.2.2.6
2.2.2.7
2.2.2.8
2.2.2.9
2.2.2.10
2.2.2.11
2.2.2.12
2.2.2.13
2.2.2.14
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
2.2.3.6
2.2.3.7
2.2.3.8
2.2.3.9
2.2.3.10
2.2.3.11
2.2.3.12
2.2.3.13
2.2.3.14
2.2.3.15
2.2.3.16
2.2.4
2.2.4.1
2.2.5
Title
Page
Number
Read/Write (R/W) ................................................................................................. 2-17
Transfer Burst (TBST) .......................................................................................... 2-17
Transfer Size (TSIZ[1:0]) ..................................................................................... 2-17
Byte Selects (BE/BWE[3:0]) ................................................................................ 2-18
Output Enable (OE) .............................................................................................. 2-18
Transfer Acknowledge (TA) ................................................................................. 2-18
SDRAM Controller Signals ...................................................................................... 2-18
SDRAM Data Bus (SDDATA[31:0]) ................................................................... 2-18
SDRAM Address Bus (SDADDR[12:0]) ............................................................. 2-18
SDRAM Bank Addresses (SDBA[1:0]) ............................................................... 2-19
SDRAM Row Address Strobe (RAS) ................................................................... 2-19
SDRAM Column Address Strobe (CAS) ............................................................. 2-19
SDRAM Chip Selects (SDCS[3:0]) ...................................................................... 2-19
SDRAM Write Data Byte Mask (SDDM[3:0]) .................................................... 2-19
SDRAM Data Strobe (SDDQS[3:0]) .................................................................... 2-19
SDRAM Clock (SDCLK[1:0]) ............................................................................. 2-19
Inverted SDRAM Clock (SDCLK[1:0]) ............................................................... 2-19
SDRAM Write Enable (SDWE) ........................................................................... 2-19
SDRAM Clock Enable (SDCKE) ......................................................................... 2-19
SDR SDRAM Data Strobe (SDRDQS) ................................................................ 2-19
SDRAM Reference Voltage (VREF) ................................................................... 2-20
PCI Controller Signals .............................................................................................. 2-20
PCI Address/Data Bus (PCIAD[31:0]) ................................................................. 2-20
Command/Byte Enables (PCICXBE[3:0]) ........................................................... 2-20
Device Select (PCIDEVSEL) ............................................................................... 2-20
Frame (PCIFRM) .................................................................................................. 2-20
Initialization Device Select (PCIIDSEL) .............................................................. 2-20
Initiator Ready (PCIIRDY) ................................................................................... 2-20
Parity (PCIPAR) ................................................................................................... 2-20
Parity Error (PCIPERR) ....................................................................................... 2-20
Reset (PCIRESET) ............................................................................................... 2-21
System Error (PCISERR) ..................................................................................... 2-21
Stop (PCISTOP) ................................................................................................... 2-21
Target Ready (PCITRDY) .................................................................................... 2-21
External Bus Grant (PCIBG[4:1]) ........................................................................ 2-21
External Bus Grant/Request Output (PCIBG0/PCIREQOUT) ............................ 2-21
External Bus Request (PCIBR[4:0]) ..................................................................... 2-21
External Request/Grant Input (PCIBR0/PCIGNTIN) .......................................... 2-21
Interrupt Control Signals .......................................................................................... 2-21
Interrupt Request (IRQ[7:1]) ................................................................................ 2-21
Clock and Reset Signals ........................................................................................... 2-22
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
2.2.5.1
2.2.5.2
2.2.5.3
2.2.6
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.4
2.2.6.5
2.2.6.6
2.2.7
2.2.7.1
2.2.7.2
2.2.7.3
2.2.7.4
2.2.7.5
2.2.7.6
2.2.7.7
2.2.7.8
2.2.7.9
2.2.7.10
2.2.7.11
2.2.7.12
2.2.7.13
2.2.7.14
2.2.8
2.2.8.1
2.2.8.2
2.2.8.3
2.2.8.4
2.2.8.5
2.2.9
2.2.9.1
2.2.9.2
2.2.9.3
2.2.9.4
2.2.9.5
2.2.9.6
2.2.10
2.2.10.1
2.2.10.2
Title
Page
Number
Reset In (RSTI) ..................................................................................................... 2-22
Reset Out (RSTO) ................................................................................................. 2-22
Clock In (CLKIN) ................................................................................................. 2-22
Reset Configuration Pins .......................................................................................... 2-22
AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0]) ................................ 2-22
AD5—FlexBus Size Configuration (FBSIZE) ..................................................... 2-23
AD4—32-bit FlexBus Configuration (FBMODE) ............................................... 2-23
AD3—Byte Enable Configuration (BECONFIG) ................................................ 2-23
AD2—Auto Acknowledge Configuration (AACONFIG) .................................... 2-24
AD[1:0]—Port Size Configuration (PSCONFIG) ................................................ 2-24
Ethernet Module Signals ........................................................................................... 2-24
Management Data (E0MDIO, E1MDIO) ............................................................. 2-24
Management Data Clock (E0MDC, E1MDC) ...................................................... 2-25
Transmit Clock (E0TXCLK, E1TXCLK) ............................................................ 2-25
Transmit Enable (E0TXEN, E1TXEN) ................................................................ 2-25
Transmit Data 0 (E0TXD0, E1TXD0) ................................................................. 2-25
Collision (E0COL, E1COL) ................................................................................. 2-25
Receive Clock (E0RXCLK, E1RXCLK) ............................................................. 2-25
Receive Data Valid (E0RXDV, E1RXDV) .......................................................... 2-25
Receive Data 0 (E0RXD0, E1RXD0) .................................................................. 2-25
Carrier Receive Sense (E0CRS, E1CRS) ............................................................. 2-25
Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1]) .................................................. 2-25
Transmit Error (E0TXER, E1TXER) ................................................................... 2-26
Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1]) ................................................... 2-26
Receive Error (E0RXER, E1RXER) .................................................................... 2-26
Universal Serial Bus (USB) ...................................................................................... 2-26
USB Differential Data (USBD+, USBD–) ........................................................... 2-26
USBVBUS ............................................................................................................ 2-26
USBRBIAS ........................................................................................................... 2-26
USBCLKIN .......................................................................................................... 2-26
USBCLKOUT ...................................................................................................... 2-26
DMA Serial Peripheral Interface (DSPI) Signals ..................................................... 2-26
DSPI Synchronous Serial Data Output (DSPISOUT) .......................................... 2-26
DSPI Synchronous Serial Data Input (DSPISIN) ................................................. 2-27
DSPI Serial Clock (DSPISCK) ............................................................................. 2-27
DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 2-27
DSPI Chip Selects (DSPICS[2:3]) ........................................................................ 2-27
DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 2-27
FlexCAN Signals ...................................................................................................... 2-27
FlexCAN Transmit (CANTX0, CANTX1) .......................................................... 2-27
FlexCAN Receive (CANRX0, CANRX1) ........................................................... 2-27
MCF548x Reference Manual, Rev. 3
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vii
Contents
Paragraph
Number
2.2.11
2.2.11.1
2.2.11.2
2.2.12
2.2.12.1
2.2.12.2
2.2.12.3
2.2.12.4
2.2.13
2.2.13.1
2.2.13.2
2.2.14
2.2.14.1
2.2.14.2
2.2.15
2.2.15.1
2.2.15.2
2.2.15.3
2.2.15.4
2.2.15.5
2.2.15.6
2.2.15.7
2.2.16
2.2.16.1
2.2.17
2.2.17.1
2.2.17.2
2.2.17.3
2.2.17.4
2.2.17.5
2.2.17.6
2.2.17.7
2.2.17.8
2.2.17.9
2.2.17.10
2.2.17.11
Title
Page
Number
I2C I/O Signals .......................................................................................................... 2-27
Serial Clock (SCL) ............................................................................................... 2-28
Serial Data (SDA) ................................................................................................. 2-28
PSC Module Signals ................................................................................................. 2-28
Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD) .. 2-28
Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD) ..... 2-28
Clear-to-Send (PSCnCTS/PSCBCLK) ................................................................. 2-28
Request-to-Send (PSCnRTS/PSCFSYNC) ........................................................... 2-28
DMA Controller Module Signals ............................................................................. 2-28
DMA Request (DREQ[1:0]) ................................................................................. 2-28
DMA Acknowledge (DACK[1:0]) ....................................................................... 2-28
Timer Module Signals .............................................................................................. 2-29
Timer Inputs (TIN[3:0]) ....................................................................................... 2-29
Timer Outputs (TOUT[3:0]) ................................................................................. 2-29
Debug Support Signals ............................................................................................. 2-29
Processor Clock Output (PSTCLK) ...................................................................... 2-29
Processor Status Debug Data (PSTDDATA[7:0]) ............................................... 2-29
Development Serial Clock/Test Reset (DSCLK/TRST) ...................................... 2-29
Breakpoint/Test Mode Select (BKPT/TMS) ........................................................ 2-30
Development Serial Input/Test Data Input (DSI/TDI) ......................................... 2-30
Development Serial Output/Test Data Output (DSO/TDO) ................................. 2-30
Test Clock (TCK) ................................................................................................. 2-30
Test Signals ............................................................................................................... 2-30
Test Mode (MTMOD[3:0]) .................................................................................. 2-30
Power and Reference Pins ........................................................................................ 2-31
Positive Pad Supply (EVDD) ............................................................................... 2-31
Positive Core Supply (IVDD) ............................................................................... 2-31
Ground (VSS) ....................................................................................................... 2-31
USB Power (USBVDD) ....................................................................................... 2-31
USB Oscillator Power (USB_OSCVDD) ............................................................. 2-31
USB PHY Power (USB_PHYVDD) .................................................................... 2-31
USB Oscillator Analog Power (USB_OSCAVDD) ............................................. 2-31
USB PLL Analog Power (USB_PLLVDD) ......................................................... 2-31
SDRAM Memory Supply (SDVDD) .................................................................... 2-31
PLL Analog Power (PLLVDD) ............................................................................ 2-31
PLL Analog Ground (PLLVSS) ........................................................................... 2-31
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
Title
Page
Number
Chapter 3
ColdFire Core
3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.2
3.3.2.1
3.3.2.2
3.3.3
3.3.4
3.3.5
3.3.5.1
3.3.5.2
3.3.5.3
3.3.5.4
3.3.5.5
3.3.5.6
3.3.6
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.2
3.4.2.1
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.3
Core Overview ................................................................................................................ 3-1
Features ........................................................................................................................... 3-1
Enhanced Pipelines ..................................................................................................... 3-2
Instruction Fetch Pipeline (IFP) .............................................................................. 3-3
Operand Execution Pipeline (OEP) ........................................................................ 3-4
Harvard Memory Architecture ............................................................................... 3-6
Debug Module Enhancements .................................................................................... 3-6
Programming Model ....................................................................................................... 3-7
User Programming Model .......................................................................................... 3-9
Data Registers (D0–D7) ......................................................................................... 3-9
Address Registers (A0–A6) .................................................................................... 3-9
User Stack Pointer (A7) ............................................................................................. 3-9
Program Counter (PC) ............................................................................................ 3-9
Condition Code Register (CCR) ............................................................................. 3-9
EMAC Programming Model .................................................................................... 3-10
FPU Programming Model ......................................................................................... 3-10
Supervisor Programming Model ............................................................................... 3-11
Status Register (SR) .............................................................................................. 3-12
Vector Base Register (VBR) ................................................................................ 3-12
Cache Control Register (CACR) .......................................................................... 3-13
Access Control Registers (ACR0–ACR3) ............................................................ 3-13
RAM Base Address Registers (RAMBAR0 and RAMBAR1) ............................ 3-13
Module Base Address Register (MBAR) ............................................................. 3-13
Programming Model Table ....................................................................................... 3-13
Data Format Summary .................................................................................................. 3-15
Data Organization in Registers ................................................................................. 3-15
Integer Data Format Organization in Registers .................................................... 3-15
Integer Data Format Organization in Memory ..................................................... 3-16
EMAC Data Representation ..................................................................................... 3-17
Floating-Point Data Formats and Types ............................................................... 3-17
Addressing Mode Summary ......................................................................................... 3-18
Instruction Set Summary .............................................................................................. 3-19
Additions to the Instruction Set Architecture ........................................................... 3-19
Instruction Set Summary .......................................................................................... 3-22
Instruction Execution Timing ....................................................................................... 3-27
MOVE Instruction Execution Timing ...................................................................... 3-28
One-Operand Instruction Execution Timing ............................................................ 3-30
Two-Operand Instruction Execution Timing ............................................................ 3-31
MCF548x Reference Manual, Rev. 3
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ix
Contents
Paragraph
Number
3.7.4
3.7.5
3.7.6
3.7.7
3.8
3.8.1
3.8.2
3.9
Title
Page
Number
Miscellaneous Instruction Execution Timing ........................................................... 3-32
Branch Instruction Execution Timing ....................................................................... 3-33
EMAC Instruction Execution Times ........................................................................ 3-34
FPU Instruction Execution Times ............................................................................. 3-35
Exception Processing Overview ................................................................................... 3-36
Exception Stack Frame Definition ............................................................................ 3-38
Processor Exceptions ................................................................................................ 3-39
Precise Faults ................................................................................................................ 3-42
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.1.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
Introduction ..................................................................................................................... 4-1
MAC Overview ........................................................................................................... 4-2
General Operation ....................................................................................................... 4-2
Memory Map/Register Definition .................................................................................. 4-5
MAC Status Register (MACSR) ................................................................................. 4-5
Fractional Operation Mode ..................................................................................... 4-8
Mask Register (MASK) ............................................................................................ 4-10
EMAC Instruction Set Summary .................................................................................. 4-11
EMAC Instruction Execution Timing ....................................................................... 4-11
Data Representation .................................................................................................. 4-12
EMAC Opcodes ........................................................................................................ 4-13
Chapter 5
Memory Management Unit (MMU)
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
5.2.3.6
5.2.3.7
5.2.3.8
Features ........................................................................................................................... 5-1
Virtual Memory Management Architecture ................................................................... 5-1
MMU Architecture Features ....................................................................................... 5-1
MMU Architecture Location ...................................................................................... 5-2
MMU Architecture Implementation ........................................................................... 5-3
Precise Faults .......................................................................................................... 5-4
MMU Access .......................................................................................................... 5-4
Virtual Mode ........................................................................................................... 5-4
Virtual Memory References ................................................................................... 5-4
Instruction and Data Cache Addresses ................................................................... 5-4
Supervisor/User Stack Pointers .............................................................................. 5-5
Access Error Stack Frame ...................................................................................... 5-5
Expanded Control Register Space .......................................................................... 5-5
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
5.2.3.9
5.2.3.10
5.2.3.11
5.3
5.4
5.4.1
5.4.2
5.4.3
5.5
5.5.1
5.5.2
5.5.3
5.5.3.1
5.5.3.2
5.5.3.3
5.5.3.4
5.5.3.5
5.5.3.6
5.5.3.7
5.5.4
5.5.5
5.6
5.6.1
5.6.2
5.6.3
5.7
Title
Page
Number
Changes to ACRs and CACR ................................................................................. 5-5
ACR Address Improvements .................................................................................. 5-6
Supervisor Protection .............................................................................................. 5-7
Debugging in a Virtual Environment .............................................................................. 5-7
Virtual Memory Architecture Processor Support ........................................................... 5-7
Precise Faults .............................................................................................................. 5-7
Supervisor/User Stack Pointers ................................................................................. 5-7
Access Error Stack Frame Additions .......................................................................... 5-8
MMU Definition ............................................................................................................. 5-9
Effective Address Attribute Determination ................................................................ 5-9
MMU Functionality .................................................................................................. 5-10
MMU Organization ................................................................................................... 5-10
MMU Base Address Register (MMUBAR) ......................................................... 5-10
MMU Memory Map ............................................................................................. 5-11
MMU Control Register (MMUCR) ..................................................................... 5-11
MMU Operation Register (MMUOR) .................................................................. 5-12
MMU Status Register (MMUSR) ......................................................................... 5-14
MMU Fault, Test, or TLB Address Register (MMUAR) ..................................... 5-15
MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR) ...... 5-16
MMU TLB ................................................................................................................ 5-18
MMU Operation ....................................................................................................... 5-19
MMU Implementation .................................................................................................. 5-20
TLB Address Fields .................................................................................................. 5-20
TLB Replacement Algorithm ................................................................................... 5-21
TLB Locked Entries .................................................................................................. 5-22
MMU Instructions ......................................................................................................... 5-23
Chapter 6
Floating-Point Unit (FPU)
6.1
6.1.1
6.1.1.1
6.2
6.2.1
6.2.2
6.2.3
6.2.3.1
6.2.3.2
6.2.3.3
6.2.3.4
Introduction ..................................................................................................................... 6-1
Overview ..................................................................................................................... 6-1
Notational Conventions .......................................................................................... 6-1
Operand Data Formats and Types .................................................................................. 6-3
Signed-Integer Data Formats ...................................................................................... 6-3
Floating-Point Data Formats ....................................................................................... 6-3
Floating-Point Data Types .......................................................................................... 6-4
Normalized Numbers .............................................................................................. 6-4
Zeros ....................................................................................................................... 6-4
Infinities .................................................................................................................. 6-4
Not-A-Number ........................................................................................................ 6-5
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Paragraph
Number
6.2.3.5
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.1.3
6.6.1.4
6.6.1.5
6.6.1.6
6.6.1.7
6.6.1.8
6.6.2
6.7
6.7.1
6.7.2
6.7.3
Title
Page
Number
Denormalized Numbers .......................................................................................... 6-5
Register Definition .......................................................................................................... 6-7
Floating-Point Data Registers (FP0–FP7) .................................................................. 6-7
Floating-Point Control Register (FPCR) .................................................................... 6-7
Floating-Point Status Register (FPSR) ....................................................................... 6-9
Floating-Point Instruction Address Register (FPIAR) .............................................. 6-10
Floating-Point Computational Accuracy ...................................................................... 6-11
Intermediate Result ................................................................................................... 6-11
Rounding the Result .................................................................................................. 6-12
Floating-Point Post-Processing ..................................................................................... 6-14
Underflow, Round, and Overflow ............................................................................ 6-14
Conditional Testing ................................................................................................... 6-15
Floating-Point Exceptions ............................................................................................. 6-17
Floating-Point Arithmetic Exceptions ...................................................................... 6-18
Branch/Set on Unordered (BSUN) ....................................................................... 6-19
Input Not-A-Number (INAN) ............................................................................... 6-20
Input Denormalized Number (IDE) ...................................................................... 6-20
Operand Error (OPERR) ....................................................................................... 6-21
Overflow (OVFL) ................................................................................................. 6-21
Underflow (UNFL) ............................................................................................... 6-22
Divide-by-Zero (DZ) ............................................................................................ 6-22
Inexact Result (INEX) .......................................................................................... 6-23
Floating-Point State Frames ...................................................................................... 6-23
Instructions .................................................................................................................... 6-25
Floating-Point Instruction Overview ........................................................................ 6-25
Floating-Point Instruction Execution Timing ........................................................... 6-27
Key Differences between ColdFire and M68000 FPU Programming Models ......... 6-28
Chapter 7
Local Memory
7.1
7.2
7.3
7.4
7.4.1
7.5
7.5.1
7.6
7.7
7.8
Interactions between Local Memory Modules ............................................................... 7-1
SRAM Overview ............................................................................................................ 7-1
SRAM Operation ............................................................................................................ 7-2
SRAM Register Definition ............................................................................................. 7-2
SRAM Base Address Registers (RAMBAR0/RAMBAR1) ....................................... 7-2
SRAM Initialization ........................................................................................................ 7-4
SRAM Initialization Code .......................................................................................... 7-5
Power Management ........................................................................................................ 7-6
Cache Overview .............................................................................................................. 7-6
Cache Organization ......................................................................................................... 7-7
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Paragraph
Number
7.8.1
7.8.2
7.9
7.9.1
7.9.1.1
7.9.1.2
7.9.2
7.9.2.1
7.9.2.2
7.9.2.3
7.9.2.4
7.9.3
7.9.4
7.9.4.1
7.9.4.2
7.9.5
7.10
7.10.1
7.10.2
7.11
7.12
7.12.1
7.12.2
7.13
Title
Page
Number
Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8
The Cache at Start-Up ................................................................................................. 7-8
Cache Operation ........................................................................................................... 7-10
Caching Modes ......................................................................................................... 7-12
Cacheable Accesses .............................................................................................. 7-12
Cache-Inhibited Accesses ..................................................................................... 7-13
Cache Protocol .......................................................................................................... 7-14
Read Miss ............................................................................................................. 7-14
Write Miss (Data Cache Only) ............................................................................. 7-14
Read Hit ................................................................................................................ 7-15
Write Hit (Data Cache Only) ................................................................................ 7-15
Cache Coherency (Data Cache Only) ....................................................................... 7-15
Memory Accesses for Cache Maintenance ............................................................... 7-15
Cache Filling ......................................................................................................... 7-15
Cache Pushes ........................................................................................................ 7-16
Cache Locking .......................................................................................................... 7-17
Cache Register Definition ............................................................................................. 7-19
Cache Control Register (CACR) .............................................................................. 7-19
Access Control Registers (ACR0–ACR3) ................................................................ 7-22
Cache Management ....................................................................................................... 7-23
Cache Operation Summary ........................................................................................... 7-26
Instruction Cache State Transitions .......................................................................... 7-26
Data Cache State Transitions .................................................................................... 7-27
Cache Initialization Code .............................................................................................. 7-30
Chapter 8
Debug Support
8.1
8.1.1
8.2
8.2.1
8.3
8.3.1
8.3.2
8.3.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
Introduction ..................................................................................................................... 8-1
Overview ..................................................................................................................... 8-1
Signal Descriptions ......................................................................................................... 8-2
Processor Status/Debug Data (PSTDDATA[7:0]) ..................................................... 8-3
Real-Time Trace Support ................................................................................................ 8-5
Begin Execution of Taken Branch (PST = 0x5) ......................................................... 8-6
Processor Stopped or Breakpoint State Change (PST = 0xE) .................................... 8-7
Processor Halted (PST = 0xF) .................................................................................... 8-8
Memory Map/Register Definition .................................................................................. 8-9
Revision A Shared Debug Resources ....................................................................... 8-11
Configuration/Status Register (CSR) ........................................................................ 8-11
PC Breakpoint ASID Control Register (PBAC) ....................................................... 8-14
BDM Address Attribute Register (BAAR) ............................................................... 8-15
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Paragraph
Number
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10
8.4.11
8.4.11.1
8.5
8.5.1
8.5.2
8.5.2.1
8.5.2.2
8.5.3
8.5.3.1
8.5.3.2
8.5.3.3
8.6
8.6.1
8.6.1.1
8.6.2
8.7
8.7.1
8.7.2
8.8
8.8.1
8.8.2
8.8.3
8.8.3.1
8.9
Title
Page
Number
Address Attribute Trigger Registers (AATR, AATR1) ............................................ 8-16
Trigger Definition Register (TDR) ........................................................................... 8-17
Program Counter Breakpoint and Mask Registers (PBRn, PBMR) ......................... 8-20
Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ........................... 8-21
Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1) .................... 8-22
PC Breakpoint ASID Register (PBASID) ................................................................ 8-24
Extended Trigger Definition Register (XTDR) ........................................................ 8-25
Resulting Set of Possible Trigger Combinations .................................................. 8-27
Background Debug Mode (BDM) ................................................................................ 8-28
CPU Halt ................................................................................................................... 8-28
BDM Serial Interface ................................................................................................ 8-30
Receive Packet Format ......................................................................................... 8-30
Transmit Packet Format ........................................................................................ 8-31
BDM Command Set .................................................................................................. 8-31
ColdFire BDM Command Format ........................................................................ 8-33
Command Sequence Diagrams ............................................................................. 8-33
Command Set Descriptions .................................................................................. 8-35
Real-Time Debug Support ............................................................................................ 8-51
Theory of Operation .................................................................................................. 8-51
Emulator Mode ..................................................................................................... 8-53
Concurrent BDM and Processor Operation .............................................................. 8-53
Debug C Definition of PSTDDATA Outputs .............................................................. 8-54
User Instruction Set .................................................................................................. 8-54
Supervisor Instruction Set ......................................................................................... 8-60
ColdFire Debug History ................................................................................................ 8-61
ColdFire Debug Classic: The Original Definition .................................................... 8-61
ColdFire Debug Revision B ...................................................................................... 8-62
ColdFire Debug Revision C ...................................................................................... 8-62
Debug Interrupts and Interrupt Requests (Emulator Mode) ................................. 8-62
Freescale-Recommended BDM Pinout ........................................................................ 8-63
Chapter 9
System Integration Unit (SIU)
9.1
9.2
9.3
9.3.1
9.3.1.1
9.3.1.2
9.3.1.3
Introduction ..................................................................................................................... 9-1
Features ........................................................................................................................... 9-1
Memory Map/Register Definition .................................................................................. 9-1
Module Base Address Register (MBAR) ................................................................... 9-2
System Breakpoint Control Register (SBCR) ........................................................ 9-3
SEC Sequential Access Control Register (SECSACR) ......................................... 9-4
Reset Status Register (RSR) ................................................................................... 9-5
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Paragraph
Number
9.3.1.4
Title
Page
Number
JTAG Device Identification Number (JTAGID) .................................................... 9-5
Chapter 10
Internal Clocks and Bus Architecture
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1.6.1
10.1.6.2
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.3
10.3.3.1
10.3.3.2
10.3.3.3
10.3.3.4
10.3.3.5
10.3.3.6
10.3.3.7
10.3.3.8
10.3.3.9
10.3.3.10
10.3.3.11
Introduction ................................................................................................................... 10-1
Block Diagram .......................................................................................................... 10-1
Clocking Overview ................................................................................................... 10-2
Internal Bus Overview .............................................................................................. 10-2
XL Bus Features ....................................................................................................... 10-3
Internal Bus Transaction Summaries ........................................................................ 10-3
XL Bus Interface Operations .................................................................................... 10-3
Basic Transfer Protocol ........................................................................................ 10-3
Address Pipelines .................................................................................................. 10-4
PLL ............................................................................................................................... 10-5
PLL Memory Map/Register Descriptions ................................................................. 10-5
System PLL Control Register (SPCR) ..................................................................... 10-5
XL Bus Arbiter ............................................................................................................. 10-6
Features ..................................................................................................................... 10-6
Arbiter Functional Description ................................................................................. 10-6
Prioritization ......................................................................................................... 10-6
Bus Grant Mechanism .......................................................................................... 10-7
Watchdog Functions ............................................................................................. 10-8
XLB Arbiter Register Descriptions .......................................................................... 10-8
Arbiter Configuration Register (XARB_CFG) .................................................... 10-9
Arbiter Version Register (XARB_VER) ............................................................ 10-10
Arbiter Status Register (XARB_SR) .................................................................. 10-11
Arbiter Interrupt Mask Register (XARB_IMR) ................................................. 10-11
Arbiter Address Capture Register (XARB_ADRCAP) ...................................... 10-13
Arbiter Bus Signal Capture Register (XARB_SIGCAP) ................................... 10-13
Arbiter Address Tenure Time Out Register (XARB_ADRTO) ......................... 10-14
Arbiter Data Tenure Time Out Register (XARB_DATTO) ............................... 10-15
Arbiter Bus Activity Time Out Register (XARB_BUSTO) ............................... 10-16
Arbiter Master Priority Enable Register (XARB_PRIEN) ................................. 10-16
Arbiter Master Priority Register (XARB_PRI) .................................................. 10-17
Chapter 11
General Purpose Timers (GPT)
11.1
Introduction ................................................................................................................... 11-1
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Paragraph
Number
11.1.1
11.1.2
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
Title
Page
Number
Overview ................................................................................................................... 11-1
Modes of Operation .................................................................................................. 11-1
External Signals ............................................................................................................ 11-2
Memory Map/Register Definition ................................................................................ 11-2
GPT Enable and Mode Select Register (GMSn) ...................................................... 11-3
GPT Counter Input Register (GCIRn) ...................................................................... 11-5
GPT PWM Configuration Register (GPWMn) ........................................................ 11-6
GPT Status Register (GSRn) .................................................................................... 11-7
Functional Description .................................................................................................. 11-8
Timer Configuration Method .................................................................................... 11-8
Programming Notes .................................................................................................. 11-8
Chapter 12
Slice Timers (SLT)
12.1
12.1.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
Introduction ................................................................................................................... 12-1
Overview ................................................................................................................... 12-1
Memory Map/Register Definition ................................................................................ 12-1
SLT Terminal Count Register (STCNTn) ................................................................ 12-2
SLT Control Register (SCRn) ................................................................................... 12-2
SLT Timer Count Register (SCNTn) ........................................................................ 12-3
SLT Status Register (SSRn) ..................................................................................... 12-4
Chapter 13
Interrupt Controller
13.1
13.1.1
13.1.1.1
13.2
13.2.1
13.2.1.1
13.2.1.2
13.2.1.3
13.2.1.4
13.2.1.5
13.2.1.6
13.2.1.7
Introduction ................................................................................................................... 13-1
68K/ColdFire Interrupt Architecture Overview ....................................................... 13-1
Interrupt Controller Theory of Operation ............................................................. 13-2
Memory Map/Register Descriptions ............................................................................. 13-4
Register Descriptions ................................................................................................ 13-5
Interrupt Pending Registers (IPRH, IPRL) ........................................................... 13-5
Interrupt Mask Register (IMRH, IMRL) .............................................................. 13-7
Interrupt Force Registers (INTFRCH, INTFRCL) ............................................... 13-8
Interrupt Request Level Register (IRLR) ........................................................... 13-10
Interrupt Acknowledge Level and Priority Register (IACKLPR) ...................... 13-10
Interrupt Control Registers 1–63 (ICRn) ............................................................ 13-11
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) ......... 13-13
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Paragraph
Number
Title
Page
Number
Chapter 14
Edge Port Module (EPORT)
14.1
14.2
14.3
14.3.1
14.3.2
14.3.2.1
14.3.2.2
14.3.2.3
14.3.2.4
14.3.2.5
14.3.2.6
Introduction ................................................................................................................... 14-1
Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 14-1
Memory Map/Register Definition ................................................................................ 14-2
Memory Map ............................................................................................................ 14-2
Register Descriptions ................................................................................................ 14-2
EPORT Pin Assignment Register (EPPAR) ......................................................... 14-3
EPORT Data Direction Register (EPDDR) .......................................................... 14-3
Edge Port Interrupt Enable Register (EPIER) ...................................................... 14-4
Edge Port Data Register (EPDR) .......................................................................... 14-4
Edge Port Pin Data Register (EPPDR) ................................................................. 14-5
Edge Port Flag Register (EPFR) ........................................................................... 14-5
Chapter 15
GPIO
15.1
15.1.1
15.1.2
15.2
15.3
15.3.1
15.3.2
15.3.2.1
15.3.2.2
15.3.2.3
15.3.2.4
15.3.2.5
15.3.2.6
15.3.2.7
15.3.2.8
15.3.2.9
15.3.2.10
15.3.2.11
15.3.2.12
15.3.2.13
15.3.2.14
15.3.2.15
15.3.2.16
Introduction ................................................................................................................... 15-1
Overview ................................................................................................................... 15-2
Features ..................................................................................................................... 15-3
External Pin Description ............................................................................................... 15-3
Memory Map/Register Definition ................................................................................ 15-7
Register Overview .................................................................................................... 15-7
Register Descriptions ................................................................................................ 15-8
Port x Output Data Registers (PODR_x) .............................................................. 15-8
Port x Data Direction Registers (PDDR_x) ........................................................ 15-11
Port x Pin Data/Set Data Registers (PPDSDR_x) ............................................. 15-14
Port x Clear Output Data Registers (PCLRR_x) ................................................ 15-18
Port x Pin Assignment Registers (PAR_x) ......................................................... 15-21
FlexBus Chip Select Pin Assignment Register (PAR_FBCS) ........................... 15-22
DMA Pin Assignment Register (PAR_DMA) ................................................... 15-23
FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ) ........................... 15-23
PCI Grant Pin Assignment Register (PAR_PCIBG) .......................................... 15-25
PCI Request Pin Assignment Register (PAR_PCIBR) ...................................... 15-26
PSC3 Pin Assignment Register (PAR_PSC3) .................................................... 15-27
PSC2 Pin Assignment Register (PAR_PSC2) .................................................... 15-28
PSC1 Pin Assignment Register (PAR_PSC1) .................................................... 15-28
PSC0 Pin Assignment Register (PAR_PSC0) .................................................... 15-29
DSPI Pin Assignment Register (PAR_DSPI) ..................................................... 15-30
General Purpose Timer Pin Assignment Register (PAR_TIMER) .................... 15-31
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Paragraph
Number
15.4
15.4.1
Title
Page
Number
Functional Description ................................................................................................ 15-32
Overview ................................................................................................................. 15-32
Chapter 16
32-Kbyte System SRAM
16.1
16.1.1
16.1.2
16.1.3
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
16.3
Introduction ................................................................................................................... 16-1
Block Diagram .......................................................................................................... 16-1
Features ..................................................................................................................... 16-2
Overview ................................................................................................................... 16-2
Memory Map/Register Definition ................................................................................ 16-2
System SRAM Configuration Register (SSCR) ....................................................... 16-3
Transfer Count Configuration Register (TCCR) ..................................................... 16-4
Transfer Count Configuration Register—DMA Read Channel (TCCRDR) ............ 16-5
Transfer Count Configuration Register—DMA Write Channel (TCCRDW) .......... 16-6
Transfer Count Configuration Register—SEC (TCCRSEC) .................................... 16-7
Functional Description .................................................................................................. 16-8
Chapter 17
FlexBus
17.1
17.1.1
17.1.2
17.1.3
17.2
17.3
17.4
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
17.4.6
17.4.7
17.4.8
17.4.9
17.5
17.5.1
17.5.1.1
Introduction ................................................................................................................... 17-1
Overview ................................................................................................................... 17-1
Features ..................................................................................................................... 17-1
Modes of Operation .................................................................................................. 17-1
Byte Lanes .................................................................................................................... 17-2
Address Latch ............................................................................................................... 17-2
External Signals ............................................................................................................ 17-3
Chip-Select (FBCS[5:0]) .......................................................................................... 17-4
Address/Data Bus (AD[31:0]) .................................................................................. 17-4
Address Latch Enable (ALE) .................................................................................... 17-4
Read/Write (R/W) ..................................................................................................... 17-4
Transfer Burst (TBST) .............................................................................................. 17-4
Transfer Size (TSIZ[1:0]) ......................................................................................... 17-4
Byte Selects (BE/BWE[3:0]) .................................................................................... 17-5
Output Enable (OE) .................................................................................................. 17-5
Transfer Acknowledge (TA) ..................................................................................... 17-5
Chip-Select Operation ................................................................................................... 17-6
General Chip-Select Operation ................................................................................. 17-6
8-, 16-, and 32-Bit Port Sizing .............................................................................. 17-6
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Paragraph
Number
17.5.1.2
17.5.2
17.5.2.1
17.5.2.2
17.5.2.3
17.6
17.6.1
17.6.2
17.6.3
17.6.4
17.6.4.1
17.6.5
17.6.5.1
17.6.5.2
17.6.5.3
17.6.5.4
17.6.6
17.6.7
17.6.8
Title
Page
Number
Global Chip-Select Operation ............................................................................... 17-6
Chip-Select Registers ................................................................................................ 17-7
Chip-Select Address Registers (CSAR0–CSAR5) ............................................... 17-8
Chip-Select Mask Registers (CSMR0–CSMR5) .................................................. 17-9
Chip-Select Control Registers (CSCR0–CSCR5) .............................................. 17-10
Functional Description ................................................................................................ 17-12
Data Transfer Operation ......................................................................................... 17-12
Data Byte Alignment and Physical Connections .................................................... 17-12
Address/Data Bus Multiplexing .............................................................................. 17-13
Bus Cycle Execution ............................................................................................... 17-13
Data Transfer Cycle States ................................................................................. 17-14
FlexBus Timing Examples ...................................................................................... 17-15
Basic Read Bus Cycle ......................................................................................... 17-15
Basic Write Bus Cycle ........................................................................................ 17-16
Bus Cycle Multiplexing ...................................................................................... 17-17
Timing Variations ............................................................................................... 17-21
Burst Cycles ............................................................................................................ 17-26
Misaligned Operands .............................................................................................. 17-31
Bus Errors ............................................................................................................... 17-32
Chapter 18
SDRAM Controller (SDRAMC)
18.1
18.2
18.2.1
18.2.2
18.2.3
18.3
18.3.1
18.3.2
18.3.3
18.3.4
18.3.5
18.3.6
18.3.7
18.3.8
18.3.9
18.3.10
18.3.11
18.3.12
Introduction ................................................................................................................... 18-1
Overview ....................................................................................................................... 18-1
Features ..................................................................................................................... 18-1
Terminology .............................................................................................................. 18-1
Block Diagram .......................................................................................................... 18-2
External Signal Description .......................................................................................... 18-2
SDRAM Data Bus (SDDATA[31:0]) ....................................................................... 18-2
SDRAM Address Bus (SDADDR[12:0]) ................................................................. 18-2
SDRAM Bank Addresses (SDBA[1:0]) ................................................................... 18-2
SDRAM Row Address Strobe (RAS) ....................................................................... 18-3
SDRAM Column Address Strobe (CAS) ................................................................. 18-3
SDRAM Chip Selects (SDCS[3:0]) .......................................................................... 18-3
SDRAM Write Data Byte Mask (SDDM[3:0]) ........................................................ 18-3
SDRAM Data Strobe (SDDQS[3:0]) ........................................................................ 18-3
SDRAM Clock (SDCLK[1:0]) ................................................................................. 18-3
Inverted SDRAM Clock (SDCLK[1:0]) ................................................................... 18-3
SDRAM Write Enable (SDWE) ............................................................................... 18-3
SDRAM Clock Enable (SDCKE) ............................................................................. 18-4
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Paragraph
Number
18.3.13
18.3.14
18.3.15
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.5.1
18.5
18.5.1
18.5.1.1
18.5.1.2
18.5.1.3
18.5.1.4
18.5.1.5
18.5.1.6
18.5.1.7
18.5.2
18.5.2.1
18.5.2.2
18.6
18.6.1
18.6.2
18.7
18.7.1
18.7.2
18.7.3
18.7.4
18.7.5
18.7.6
18.8
18.8.1
18.8.2
18.8.3
18.8.4
18.8.5
18.8.6
18.8.7
18.8.8
Title
Page
Number
SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4
SDRAM Memory Supply (SDVDD) ........................................................................ 18-4
SDRAM Reference Voltage (VREF) ....................................................................... 18-4
Interface Recommendations ......................................................................................... 18-4
Supported Memory Configurations .......................................................................... 18-4
SDRAM SDR Connections ...................................................................................... 18-6
SDRAM DDR Component Connections .................................................................. 18-6
SDRAM DDR DIMM Connections ......................................................................... 18-7
DDR SDRAM Layout Considerations ..................................................................... 18-8
Termination Example ........................................................................................... 18-9
SDRAM Overview ....................................................................................................... 18-9
SDRAM Commands ................................................................................................. 18-9
Row and Bank Active Command (ACTV) ......................................................... 18-10
Read Command (READ) .................................................................................... 18-10
Write Command (WRITE) ................................................................................. 18-10
Precharge All Banks Command (PALL) ............................................................ 18-11
Load Mode/Extended Mode Register Command (LMR, LEMR) ...................... 18-11
Auto Refresh Command (REF) .......................................................................... 18-13
Self-Refresh (SREF) and Power-Down (PDWN) Commands ........................... 18-13
Power-Up Initialization ........................................................................................... 18-13
SDR Initialization ............................................................................................... 18-14
DDR Initialization .............................................................................................. 18-14
Functional Overview ................................................................................................... 18-15
Page Management ................................................................................................... 18-15
Transfer Size ........................................................................................................... 18-15
Memory Map/Register Definition .............................................................................. 18-16
SDRAM Drive Strength Register (SDRAMDS) .................................................... 18-17
SDRAM Chip Select Configuration Registers (CSnCFG) ..................................... 18-18
SDRAM Mode/Extended Mode Register (SDMR) ................................................ 18-19
SDRAM Control Register (SDCR) ......................................................................... 18-20
SDRAM Configuration Register 1 (SDCFG1) ....................................................... 18-21
SDRAM Configuration Register 2 (SDCFG2) ....................................................... 18-23
SDRAM Example ....................................................................................................... 18-24
SDRAM Signal Drive Strength Settings ................................................................ 18-25
SDRAM Chip Select Settings ................................................................................. 18-25
SDRAM Configuration 1 Register Settings ............................................................ 18-26
SDRAM Configuration 2 Register Settings ............................................................ 18-27
SDRAM Control Register Settings and PALL command ...................................... 18-27
Set the Extended Mode Register ............................................................................. 18-29
Set the Mode Register and Reset DLL ................................................................... 18-29
Issue a PALL command .......................................................................................... 18-30
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
18.8.9
18.8.10
18.8.11
18.8.12
Title
Page
Number
Perform Two Refresh Cycles .................................................................................. 18-31
Clear the Reset DLL Bit in the Mode Register ...................................................... 18-32
Enable Automatic Refresh and Lock Mode Register ............................................ 18-33
Initialization Code ................................................................................................... 18-34
Chapter 19
PCI Bus Controller
19.1
19.1.1
19.1.2
19.1.3
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.2.7
19.2.8
19.2.9
19.2.10
19.2.11
19.2.12
19.2.13
19.3
19.3.1
19.3.1.1
19.3.1.2
19.3.1.3
19.3.1.4
19.3.1.5
19.3.1.6
19.3.1.7
19.3.1.8
19.3.1.9
19.3.1.10
19.3.1.11
19.3.2
19.3.2.1
Introduction ................................................................................................................... 19-1
Block Diagram .......................................................................................................... 19-1
Overview ................................................................................................................... 19-1
Features ..................................................................................................................... 19-1
External Signal Description .......................................................................................... 19-2
Address/Data Bus (PCIAD[31:0]) ............................................................................ 19-2
Command/Byte Enables (PCICXBE[3:0]) ............................................................... 19-2
Device Select (PCIDEVSEL) ................................................................................... 19-3
Frame (PCIFRAME) ................................................................................................. 19-3
Initialization Device Select (PCIIDSEL) .................................................................. 19-3
Initiator Ready (PCIIRDY) ....................................................................................... 19-3
Parity (PCIPAR) ....................................................................................................... 19-3
PCI Clock (CLKIN) .................................................................................................. 19-3
Parity Error (PCIPERR) ............................................................................................ 19-3
Reset (PCIRESET) .................................................................................................. 19-3
System Error (PCISERR) ........................................................................................ 19-3
Stop (PCISTOP) ...................................................................................................... 19-3
Target Ready (PCITRDY) ....................................................................................... 19-4
Memory Map/Register Definition ................................................................................ 19-4
PCI Type 0 Configuration Registers ......................................................................... 19-6
Device ID/Vendor ID Register (PCIIDR)—PCI Dword Addr 0 .......................... 19-7
PCI Status/Command Register (PCISCR)—PCI Dword Addr 1 ......................... 19-7
Revision ID/Class Code Register (PCICCRIR)—PCI Dword 3 .......................... 19-9
Configuration 1 Register (PCICR1)—PCI Dword 3 .......................................... 19-10
Base Address Register 0 (PCIBAR0)—PCI Dword 4 ........................................ 19-11
Base Address Register 1 (PCIBAR1)—PCI Dword 5 ........................................ 19-12
CardBus CIS Pointer Register PCICCPR—PCI Dword A ................................ 19-12
Subsystem ID/Subsystem Vendor ID Registers PCISID—PCI Dword B .......... 19-12
Expansion ROM Base Address PCIERBAR—PCI Dword C ............................ 19-13
Capabilities Pointer (Cap_Ptr) PCICPR—PCI Dword D ................................... 19-13
Configuration 2 Register (PCICR2)—PCI Dword F .......................................... 19-13
General Control/Status Registers ............................................................................ 19-13
Global Status/Control Register (PCIGSCR) ....................................................... 19-14
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
19.3.2.2
19.3.2.3
19.3.2.4
19.3.2.5
19.3.2.6
19.3.2.7
19.3.2.8
19.3.2.9
19.3.2.10
19.3.2.11
19.3.3
19.3.3.1
19.3.3.2
19.4
19.4.1
19.4.1.1
19.4.1.2
19.4.1.3
19.4.1.4
19.4.1.5
19.4.2
19.4.2.1
19.4.3
19.4.4
19.4.4.1
19.4.4.2
19.4.4.3
19.4.4.4
19.4.4.5
19.4.5
19.4.5.1
19.4.5.2
19.4.5.3
19.4.5.4
19.4.5.5
19.4.6
19.4.6.1
19.4.6.2
19.4.6.3
19.4.6.4
19.4.6.5
Title
Page
Number
Target Base Address Translation Register 0 (PCITBATR0) ............................. 19-15
Target Base Address Translation Register 1 (PCITBATR1) ............................. 19-16
Target Control Register (PCITCR) ..................................................................... 19-16
Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR) ......... 19-17
Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR) ......... 19-18
Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR) ......... 19-19
Initiator Window Configuration Register (PCIIWCR) ....................................... 19-19
Initiator Control Register (PCIICR) ................................................................... 19-20
Initiator Status Register (PCIISR) ...................................................................... 19-21
Configuration Address Register (PCICAR) ....................................................... 19-22
Communication Subsystem Interface Registers ..................................................... 19-23
Comm Bus FIFO Transmit Interface .................................................................. 19-23
Comm Bus FIFO Receive Interface ................................................................... 19-35
Functional Description ................................................................................................ 19-48
PCI Bus Protocol .................................................................................................... 19-48
PCI Bus Background .......................................................................................... 19-48
Basic Transfer Control ........................................................................................ 19-49
PCI Transactions ................................................................................................. 19-49
PCI Bus Commands ............................................................................................ 19-51
Addressing .......................................................................................................... 19-52
Initiator Arbitration ................................................................................................. 19-55
Priority Scheme .................................................................................................. 19-56
Configuration Interface ........................................................................................... 19-56
XL Bus Initiator Interface ....................................................................................... 19-56
Endian Translation .............................................................................................. 19-58
Configuration Mechanism .................................................................................. 19-60
Interrupt Acknowledge Transactions .................................................................. 19-62
Special Cycle Transactions ................................................................................. 19-62
Transaction Termination ..................................................................................... 19-63
XL Bus Target Interface ........................................................................................ 19-63
Reads from Local Memory ................................................................................. 19-64
Local Memory Writes ......................................................................................... 19-64
Data Translation .................................................................................................. 19-64
Target Abort ........................................................................................................ 19-66
Latrule Disable .................................................................................................... 19-66
Communication Subsystem Initiator Interface ....................................................... 19-66
Access Width ...................................................................................................... 19-67
Addressing .......................................................................................................... 19-67
Data Translation .................................................................................................. 19-68
Initialization ........................................................................................................ 19-68
Restart and Reset ................................................................................................ 19-68
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
19.4.6.6
19.4.6.7
19.4.6.8
19.4.6.9
19.4.7
19.4.8
19.4.8.1
19.4.8.2
19.5
19.5.1
19.5.2
19.5.2.1
19.6
Title
Page
Number
PCI Commands ................................................................................................... 19-69
FIFO Considerations ........................................................................................... 19-69
Alarms ................................................................................................................. 19-69
Bus Errors ........................................................................................................... 19-70
PCI Clock Scheme .................................................................................................. 19-70
Interrupts ................................................................................................................. 19-70
PCI Bus Interrupts .............................................................................................. 19-70
Internal Interrupt ................................................................................................. 19-70
Application Information ............................................................................................. 19-70
XL Bus-Initiated Transaction Mapping .................................................................. 19-70
Address Maps ......................................................................................................... 19-71
Address Translation ............................................................................................ 19-72
XL Bus Arbitration Priority ........................................................................................ 19-75
Chapter 20
PCI Bus Arbiter Module
20.1
20.1.1
20.1.2
20.1.3
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
20.2.6
20.2.7
20.3
20.3.1
20.3.2
20.4
20.4.1
20.4.2
20.4.2.1
20.4.2.2
20.4.2.3
20.4.2.4
20.4.3
20.5
Introduction ................................................................................................................... 20-1
Block Diagram .......................................................................................................... 20-1
Overview ................................................................................................................... 20-1
Features ..................................................................................................................... 20-2
External Signal Description .......................................................................................... 20-2
Frame (PCIFRM) ...................................................................................................... 20-2
Initiator Ready (PCIIRDY) ....................................................................................... 20-2
PCI Clock (CLKIN) .................................................................................................. 20-2
External Bus Grant (PCIBG[4:1]) ............................................................................ 20-2
External Bus Grant/Request Output (PCIBG0/PCIREQOUT) ................................ 20-3
External Bus Request (PCIBR[4:1]) ......................................................................... 20-3
External Request/Grant Input (PCIBR0/PCIGNTIN) .............................................. 20-3
Register Definition ........................................................................................................ 20-3
PCI Arbiter Control Register (PACR) ...................................................................... 20-3
PCI Arbiter Status Register (PASR) ......................................................................... 20-5
Functional Description .................................................................................................. 20-5
External PCI Requests .............................................................................................. 20-5
Arbitration ................................................................................................................. 20-6
Hidden Bus Arbitration ......................................................................................... 20-6
Arbitration Scheme ............................................................................................... 20-6
Arbitration Latency ............................................................................................... 20-7
Arbitration Examples ............................................................................................ 20-7
Master Time-Out ....................................................................................................... 20-9
Reset ............................................................................................................................ 20-10
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
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Contents
Paragraph
Number
20.6
Title
Page
Number
Interrupts ..................................................................................................................... 20-10
Chapter 21
FlexCAN
21.1
21.1.1
21.1.2
21.1.3
21.1.4
21.1.4.1
21.1.4.2
21.1.4.3
21.1.4.4
21.1.4.5
21.2
21.2.1
21.2.2
21.3
21.3.1
21.3.2
21.3.2.1
21.3.2.2
21.3.2.3
21.3.2.4
21.3.2.5
21.3.2.6
21.3.2.7
21.3.2.8
21.4
21.4.1
21.4.2
21.4.3
21.4.4
21.4.5
21.4.5.1
21.4.6
21.4.6.1
21.4.6.2
21.4.6.3
21.4.6.4
Introduction ................................................................................................................... 21-1
Block Diagram .......................................................................................................... 21-1
The CAN System ...................................................................................................... 21-2
Features ..................................................................................................................... 21-3
Modes of Operation .................................................................................................. 21-3
Normal Mode ........................................................................................................ 21-3
Freeze Mode ......................................................................................................... 21-3
Module Disabled Mode ........................................................................................ 21-4
Loop-Back Mode .................................................................................................. 21-4
Listen-Only Mode ................................................................................................. 21-4
External Signals ............................................................................................................ 21-5
CANTX[1:0] ............................................................................................................. 21-5
CANRX[1:0] ............................................................................................................. 21-5
Memory Map/Register Definition ................................................................................ 21-5
FlexCAN Memory Map ............................................................................................ 21-5
Register Descriptions ................................................................................................ 21-6
FlexCAN Module Configuration Register (CANMCR) ....................................... 21-6
FlexCAN Control Register (CANCTRL) ............................................................. 21-8
FlexCAN Timer Register (TIMER) .................................................................... 21-10
Rx Mask Registers .............................................................................................. 21-11
FlexCAN Error Counter Register (ERRCNT) .................................................... 21-14
FlexCAN Error and Status Register (ERRSTAT) .............................................. 21-15
Interrupt Mask Register (IMASK) ...................................................................... 21-17
Interrupt Flag Register (IFLAG) ........................................................................ 21-18
Functional Overview ................................................................................................... 21-19
Message Buffer Structure ....................................................................................... 21-19
Message Buffer Memory Map ................................................................................ 21-22
Transmit Process ..................................................................................................... 21-23
Arbitration Process ................................................................................................. 21-24
Receive Process ...................................................................................................... 21-24
Self-Received Frames ......................................................................................... 21-25
Message Buffer Handling ....................................................................................... 21-25
Serial Message Buffers (SMBs) ......................................................................... 21-26
Transmit Message Buffer Deactivation .............................................................. 21-26
Receive Message Buffer Deactivation ................................................................ 21-26
Locking and Releasing Message Buffers ........................................................... 21-27
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
21.4.7
21.4.7.1
21.4.7.2
21.4.8
21.4.9
21.4.9.1
21.4.10
21.5
21.5.1
Title
Page
Number
CAN Protocol Related Frames ............................................................................... 21-27
Remote Frames ................................................................................................... 21-27
Overload Frames ................................................................................................. 21-28
Time Stamp ............................................................................................................. 21-28
Bit Timing ............................................................................................................... 21-28
Configuring the FlexCAN Bit Timing ................................................................ 21-29
FlexCAN Error Counters ....................................................................................... 21-30
FlexCAN Initialization Sequence ............................................................................... 21-31
Interrupts ................................................................................................................. 21-31
Chapter 22
Integrated Security Engine (SEC)
22.1
22.2
22.3
22.4
22.4.1
22.4.2
22.4.2.1
22.4.2.2
22.4.3
22.4.4
22.4.4.1
22.4.4.2
22.4.4.3
22.4.4.4
22.4.4.5
22.5
22.6
22.6.1
22.6.2
22.6.3
22.6.4
22.6.4.1
22.6.4.2
22.6.4.3
22.6.4.4
22.6.4.5
22.6.4.6
22.6.4.7
Features ......................................................................................................................... 22-1
ColdFire Security Architecture ..................................................................................... 22-1
Block Diagram .............................................................................................................. 22-2
Overview ....................................................................................................................... 22-2
Bus Interface ............................................................................................................. 22-2
SEC Controller Unit .................................................................................................. 22-3
Static EU Access ................................................................................................... 22-3
Dynamic EU Access ............................................................................................. 22-3
Crypto-Channels ....................................................................................................... 22-3
Execution Units (EUs) .............................................................................................. 22-4
Data Encryption Standard Execution Unit (DEU) ................................................ 22-4
Arc Four Execution Unit (AFEU) ........................................................................ 22-5
Advanced Encryption Standard Execution Unit (AESU) ..................................... 22-6
Message Digest Execution Unit (MDEU) ............................................................ 22-6
Random Number Generator (RNG) ...................................................................... 22-8
Memory Map/Register Definition ................................................................................ 22-8
Controller .................................................................................................................... 22-10
EU Access ............................................................................................................... 22-11
Multiple EU Assignment ........................................................................................ 22-11
Multiple Channels ................................................................................................... 22-11
Controller Registers ................................................................................................ 22-11
EU Assignment Control Registers (EUACRH and EUACRL) .......................... 22-11
EU Assignment Status Registers (EUASRH and EUASRL) ............................. 22-13
SEC Interrupt Mask Registers (SIMRH and SIMRL) ........................................ 22-14
SEC Interrupt Status Registers (SISRH and SISRL) .......................................... 22-14
SEC Interrupt Control Registers (SICRH and SICRL) ...................................... 22-14
SEC ID Register (SIDR) ..................................................................................... 22-16
SEC Master Control Register (SMCR) ............................................................... 22-17
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
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Contents
Paragraph
Number
22.6.4.8
22.7
22.7.1
22.7.1.1
22.7.1.2
22.7.1.3
22.7.1.4
22.7.1.5
22.8
22.8.1
22.8.2
22.8.3
22.8.4
22.8.5
22.9
22.9.1
22.9.2
22.9.3
22.9.4
22.9.5
22.10
22.10.1
22.10.2
22.10.3
22.10.4
22.10.5
22.11
22.11.1
22.11.2
22.11.3
22.11.4
22.11.5
22.12
22.12.1
22.12.2
22.12.3
22.12.4
22.12.5
22.13
22.13.1
22.13.1.1
Title
Page
Number
Master Error Address Register (MEAR) ............................................................ 22-18
Channels ...................................................................................................................... 22-18
Crypto-Channel Registers ....................................................................................... 22-19
Crypto-Channel Configuration Registers (CCCRn) ........................................... 22-19
Crypto-Channel Pointer Status Registers (CCPSRHn and CCPSRLn) .............. 22-21
Crypto-Channel Current Descriptor Pointer Register (CDPRn) ........................ 22-27
Fetch Register (FRn) ........................................................................................... 22-27
Data Packet Descriptor Buffer (CDBUFn) ......................................................... 22-28
ARC Four Execution Unit (AFEU) ............................................................................ 22-28
AFEU Register Map ............................................................................................... 22-28
AFEU Reset Control Register (AFRCR) ................................................................ 22-28
AFEU Status Register (AFSR) ............................................................................... 22-29
AFEU Interrupt Status Register (AFISR) ............................................................... 22-31
AFEU Interrupt Mask Register (AFIMR) .............................................................. 22-32
Data Encryption Standard Execution Units (DEU) .................................................... 22-34
DEU Register Map .................................................................................................. 22-34
DEU Reset Control Register (DRCR) .................................................................... 22-34
DEU Status Register (DSR) .................................................................................... 22-35
DEU Interrupt Status Register (DISR) ................................................................... 22-37
DEU Interrupt Mask Register (DIMR) ................................................................... 22-39
Message Digest Execution Unit (MDEU) .................................................................. 22-40
MDEU Register Map .............................................................................................. 22-40
MDEU Reset Control Register (MDRCR) ............................................................. 22-41
MDEU Status Register (MDSR) ............................................................................. 22-41
MDEU Interrupt Status Register (MDISR) ............................................................ 22-43
MDEU Interrupt Mask Register (MDIMR) ............................................................ 22-44
RNG Execution Unit (RNG) ...................................................................................... 22-46
RNG Register Map ................................................................................................. 22-46
RNG Reset Control Register (RNGRCR) .............................................................. 22-46
RNG Status Register (RNGSR) .............................................................................. 22-47
RNG Interrupt Status Register (RNGISR) .............................................................. 22-48
RNG Interrupt Mask Register (RNGIMR) ............................................................. 22-49
Advanced Encryption Standard Execution Units (AESU) ....................................... 22-50
AESU Register Map ............................................................................................... 22-50
AESU Reset Control Register (AESRCR) ............................................................. 22-50
AESU Status Register (AESSR) ............................................................................. 22-51
AESU Interrupt Status Register (AESISR) ............................................................ 22-53
AESU Interrupt Mask Register (AESIMR) ............................................................ 22-54
Descriptors .................................................................................................................. 22-56
Descriptor Structure ................................................................................................ 22-56
Descriptor Header ............................................................................................... 22-57
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
22.13.1.2
22.13.1.3
22.13.1.4
22.13.2
22.13.3
22.13.4
22.13.4.1
22.13.4.2
22.14
22.14.1
22.14.1.1
22.14.1.2
22.14.2
22.14.2.1
22.14.2.2
22.14.3
22.14.3.1
22.14.3.2
22.14.3.3
22.14.4
22.14.5
22.14.5.1
22.14.5.2
22.14.5.3
22.14.6
22.14.6.1
22.14.6.2
22.14.6.3
22.14.6.4
Title
Page
Number
Descriptor Length and Pointer Fields ................................................................. 22-60
Null Fields .......................................................................................................... 22-61
Next Descriptor Pointer ...................................................................................... 22-61
Descriptor Chaining ................................................................................................ 22-61
Descriptor Type Formats ....................................................................................... 22-62
Descriptor Classes ................................................................................................... 22-64
Dynamic Descriptors .......................................................................................... 22-64
Static Descriptors ................................................................................................ 22-65
EU Specific Data Packet Descriptors ........................................................................ 22-67
AFEU Mode Options and Data Packet Descriptors ................................................ 22-67
Dynamically Assigned AFEU ............................................................................ 22-68
Statically Assigned AFEU .................................................................................. 22-69
DEU Mode Options and Data Packet Descriptors .................................................. 22-72
Dynamically Assigned DEU ............................................................................... 22-73
Statically Assigned DEU .................................................................................... 22-74
MDEU Mode Options and Data Packet Descriptors .............................................. 22-77
Recommended Settings for MDEU Mode Register ........................................... 22-78
Dynamically Assigned MDEU ........................................................................... 22-78
Statically Assigned MDEU ................................................................................ 22-79
RNG Data Packet Descriptors ................................................................................ 22-82
AESU Mode Options and Data Packet Descriptors ................................................ 22-83
Dynamically Assigned AESU ............................................................................ 22-84
Statically Assigned AESU .................................................................................. 22-85
AESU-CCM Mode Descriptor ........................................................................... 22-88
Multi-Function Data Packet Descriptors ................................................................ 22-90
Snooping ............................................................................................................. 22-91
Dynamic Multi-Function Descriptor Formats .................................................... 22-91
Static Multi-Function Descriptor Formats .......................................................... 22-95
SSLv3.1/TLS 1.0 Processing Descriptors ........................................................ 22-102
Chapter 23
IEEE 1149.1 Test Access Port (JTAG)
23.1
23.1.1
23.1.2
23.1.3
23.2
23.2.1
23.2.1.1
23.2.1.2
Introduction ................................................................................................................... 23-1
Block Diagram .......................................................................................................... 23-1
Features ..................................................................................................................... 23-2
Modes of Operation .................................................................................................. 23-2
External Signal Description .......................................................................................... 23-2
Detailed Signal Description ...................................................................................... 23-2
Test Mode 0 (MTMOD0) ..................................................................................... 23-2
Test Clock Input (TCK) ........................................................................................ 23-3
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
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Contents
Paragraph
Number
23.2.1.3
23.2.1.4
23.2.1.5
23.2.1.6
23.3
23.3.1
23.3.2
23.3.2.1
23.3.2.2
23.3.2.3
23.3.2.4
23.3.2.5
23.3.2.6
23.4
23.4.1
23.4.2
23.4.3
23.4.3.1
23.4.3.2
23.4.3.3
23.4.3.4
23.4.3.5
23.4.3.6
23.4.3.7
23.5
23.5.1
23.5.2
Title
Page
Number
Test Mode Select/Breakpoint (TMS/BKPT) ........................................................ 23-3
Test Data Input/Development Serial Input (TDI/DSI) ......................................... 23-3
Test Reset/Development Serial Clock (TRST/DSCLK) ...................................... 23-4
Test Data Output/Development Serial Output (TDO/DSO) ................................. 23-4
Memory Map/Register Definition ................................................................................ 23-4
Memory Map ............................................................................................................ 23-4
Register Descriptions ................................................................................................ 23-4
Instruction Shift Register (IR) .............................................................................. 23-4
IDCODE Register ................................................................................................. 23-4
Bypass Register .................................................................................................... 23-5
JTAG_CFM_CLKDIV Register ........................................................................... 23-5
TEST_CTRL Register .......................................................................................... 23-5
Boundary Scan Register ....................................................................................... 23-6
Functional Description .................................................................................................. 23-6
JTAG Module ........................................................................................................... 23-6
TAP Controller ......................................................................................................... 23-6
JTAG Instructions ..................................................................................................... 23-7
External Test Instruction (EXTEST) .................................................................... 23-8
IDCODE Instruction ............................................................................................. 23-8
SAMPLE/PRELOAD Instruction ......................................................................... 23-8
ENABLE_TEST_CTRL Instruction .................................................................... 23-9
HIGHZ Instruction ................................................................................................ 23-9
CLAMP Instruction .............................................................................................. 23-9
BYPASS Instruction ............................................................................................. 23-9
Initialization/Application Information .......................................................................... 23-9
Restrictions ............................................................................................................... 23-9
Nonscan Chain Operation ......................................................................................... 23-9
Chapter 24
Multichannel DMA
24.1
24.1.1
24.1.2
24.1.2.1
24.1.2.2
24.1.2.3
24.1.2.4
24.1.2.5
24.1.3
24.2
Introduction ................................................................................................................... 24-1
Block Diagram .......................................................................................................... 24-1
Overview ................................................................................................................... 24-2
Master DMA Engine (MDE) ................................................................................ 24-2
Address and Data Sequencer (ADS) ..................................................................... 24-2
Priority-Task Decoder (PTD) ............................................................................... 24-2
Logic Unit with Redundancy Check (LURC) ...................................................... 24-2
Debug Unit ............................................................................................................ 24-2
Features ..................................................................................................................... 24-2
External Signals ............................................................................................................ 24-3
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
24.2.1
24.2.2
24.3
24.3.1
24.3.1.1
24.3.1.2
24.3.1.3
24.3.1.4
24.3.1.5
24.3.2
24.3.3
24.3.3.1
24.3.3.2
24.3.3.3
24.3.3.4
24.3.3.5
24.3.3.6
24.3.3.7
24.3.3.8
24.3.3.9
24.3.3.10
24.3.3.11
24.3.3.12
24.3.3.13
24.3.3.14
24.3.3.15
24.3.3.16
24.3.4
24.3.4.1
24.3.4.2
24.3.4.3
24.3.4.4
24.4
24.4.1
24.4.2
24.4.3
24.4.4
24.4.5
24.4.6
24.4.7
24.4.8
Title
Page
Number
DREQ[1:0] ............................................................................................................... 24-3
DACK[1:0] .............................................................................................................. 24-3
Memory Map/Register Definitions ............................................................................... 24-3
DMA Task Memory .................................................................................................. 24-3
Task Table ............................................................................................................ 24-3
Task Descriptor Table ........................................................................................... 24-3
Variable Table ...................................................................................................... 24-4
Function Descriptor Table .................................................................................... 24-4
Context Save Space .............................................................................................. 24-4
Memory Structure ..................................................................................................... 24-4
DMA Registers ......................................................................................................... 24-5
DMA Register Map .............................................................................................. 24-5
Task Base Address Register (TaskBAR) .............................................................. 24-6
Current Pointer (CP) ............................................................................................. 24-7
End Pointer (EP) ................................................................................................... 24-8
Variable Pointer (VP) ........................................................................................... 24-8
PTD Control (PTD) .............................................................................................. 24-9
DMA Interrupt Pending (DIPR) ......................................................................... 24-10
DMA Interrupt Mask Register (DIMR) .............................................................. 24-10
Task Control Registers (TCRn) .......................................................................... 24-11
Priority Registers (PRIORn) ............................................................................... 24-12
Initiator Mux Control Register (IMCR) ............................................................. 24-13
Task Size Registers (TSKSZ[0:1]) ..................................................................... 24-14
Debug Comparator Registers (DBGCOMPn) .................................................... 24-16
Debug Control (DBGCTL) ................................................................................. 24-16
Debug Status (DBGSTAT) ................................................................................. 24-18
PTD Debug Registers ......................................................................................... 24-19
External Request Module Registers ........................................................................ 24-20
External Request Module Register Map ............................................................. 24-20
External Request Base Address Register (EREQBAR) ..................................... 24-20
External Request Address Mask Register (EREQMASK) ................................. 24-21
External Request Control Register (EREQCTRL) ............................................. 24-21
Functional Description ................................................................................................ 24-22
Tasks ....................................................................................................................... 24-22
Descriptors .............................................................................................................. 24-23
Task Initialization ................................................................................................... 24-23
Initiators .................................................................................................................. 24-23
Prioritization ........................................................................................................... 24-24
Context Switch ........................................................................................................ 24-24
Data Movement ....................................................................................................... 24-24
Data Manipulation .................................................................................................. 24-24
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
xxix
Contents
Paragraph
Number
24.4.8.1
24.4.9
24.4.9.1
24.4.9.2
24.4.9.3
24.4.10
24.4.11
24.4.12
24.5
24.5.1
24.5.2
24.5.2.1
24.6
24.6.1
24.6.2
24.6.3
Title
Page
Number
LURC Features ................................................................................................... 24-25
Line Buffers ............................................................................................................ 24-26
Combine Write Enable ....................................................................................... 24-26
Read Line Enable ................................................................................................ 24-26
Speculative Prefetch ........................................................................................... 24-26
Termination of Loop ............................................................................................... 24-27
Interrupts ................................................................................................................. 24-27
Debug Unit .............................................................................................................. 24-27
Programming Model ................................................................................................... 24-27
Register Initialization .............................................................................................. 24-27
Task Memory .......................................................................................................... 24-28
Task Table .......................................................................................................... 24-28
Timing Diagrams ........................................................................................................ 24-30
Level-Triggered Requests ....................................................................................... 24-30
Edge-Triggered Requests ........................................................................................ 24-30
Pipelined Requests .................................................................................................. 24-31
Chapter 25
Comm Timer Module (CTM)
25.1
25.1.1
25.1.2
25.1.3
25.2
25.2.1
25.2.2
25.2.2.1
25.2.2.2
25.3
25.3.1
25.3.2
25.3.2.1
25.3.3
25.3.3.1
Introduction ................................................................................................................... 25-1
Block Diagrams ........................................................................................................ 25-1
Overview ................................................................................................................... 25-2
Comm Timer External Clock[7:0] ............................................................................ 25-3
Memory Map/Register Definition ................................................................................ 25-3
Timer Module Register Map ..................................................................................... 25-3
Register Descriptions ................................................................................................ 25-4
Comm Timer Configuration Register (CTCRn)—Fixed Timer Channel ............. 25-4
Comm Timer Configuration Register (CTCRn)—Variable Timer Channel ........ 25-5
Functional Description .................................................................................................. 25-7
Variable Timer in Baud Clock Generator Mode ...................................................... 25-7
Fixed Timer in Initiator Mode .................................................................................. 25-7
Fixed Timer in Initiator Mode Example ............................................................... 25-7
Variable Timer in Initiator Mode .............................................................................. 25-8
Variable Timer in Initiator Mode Example .......................................................... 25-8
Chapter 26
Programmable Serial Controller (PSC)
26.1
Introduction ................................................................................................................... 26-1
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
26.1.1
26.1.2
26.1.3
26.1.4
26.2
26.2.1
26.2.2
26.2.3
26.2.4
26.2.5
26.3
26.3.1
26.3.2
26.3.3
26.3.3.1
26.3.3.2
26.3.3.3
26.3.3.4
26.3.3.5
26.3.3.6
26.3.3.7
26.3.3.8
26.3.3.9
26.3.3.10
26.3.3.11
26.3.3.12
26.3.3.13
26.3.3.14
26.3.3.15
26.3.3.16
26.3.3.17
26.3.3.18
26.3.3.19
26.3.3.20
26.3.3.21
26.3.3.22
26.3.3.23
26.3.3.24
26.3.3.25
26.3.3.26
26.3.3.27
Title
Page
Number
Block Diagram .......................................................................................................... 26-1
Overview ................................................................................................................... 26-1
Features ..................................................................................................................... 26-1
Modes of Operation .................................................................................................. 26-1
Signal Description ......................................................................................................... 26-2
PSCnCTS/PSCBCLK ............................................................................................... 26-2
PScnrts/pscfsync ....................................................................................................... 26-2
PSCnrxd .................................................................................................................... 26-2
pscntxd ...................................................................................................................... 26-3
Signal Properties in Each Mode ................................................................................ 26-3
Memory Map/Register Definition ................................................................................ 26-3
Overview ................................................................................................................... 26-3
Module Memory Map ............................................................................................... 26-3
Register Descriptions ................................................................................................ 26-5
Mode Register 1(PSCMR1n) ................................................................................ 26-5
Mode Register 2 (PSCMR2n) ............................................................................... 26-6
Status Register (PSCSRn) ..................................................................................... 26-8
Clock Select Register (PSCCSRn) ..................................................................... 26-10
Command Register (PSCCRn) ........................................................................... 26-11
Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn) ......................... 26-14
Input Port Change Register (PSCIPCRn) ........................................................... 26-17
Auxiliary Control Register (PSCACRn) ............................................................ 26-18
Interrupt Status Register (PSCISRn) .................................................................. 26-18
Interrupt Mask Register (PSCIMRn) .................................................................. 26-19
Counter Timer Registers (PSCCTURn, PSCCTLRn) ........................................ 26-21
Input Port (PSCIPn) ............................................................................................ 26-21
Output Port Bit Set (PSCOPSETn) ..................................................................... 26-22
Output Port Bit Reset (PSCOPRESETn) ............................................................ 26-22
PSC/IrDA Control Register (PSCSICRn) .......................................................... 26-23
Infrared Control Register 1 (PSCIRCR1n) ......................................................... 26-24
Infrared Control Register 2 (PSCIRCR2n) ......................................................... 26-24
Infrared SIR Divide Register (PSCIRSDRn) ..................................................... 26-25
Infrared MIR Divide Register (PSCIRMDRn) ................................................... 26-25
Infrared FIR Divide Register (PSCIRFDRn) ..................................................... 26-26
Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn) .................... 26-27
Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn) .............................. 26-27
Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn) ............................. 26-28
Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn) .......................... 26-30
Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn) ............................ 26-32
Rx and Tx FIFO Read Pointer (PSCRFRPn, PSCTFRPn) ................................. 26-32
Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn) .............................. 26-33
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
26.3.3.28
26.3.3.29
26.4
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.4.5.1
26.4.5.2
26.4.5.3
26.4.6
26.4.7
26.4.7.1
26.4.7.2
26.4.8
26.4.8.1
26.4.9
26.4.9.1
26.4.9.2
26.4.10
26.4.10.1
26.4.10.2
26.4.10.3
26.5
26.5.1
26.5.2
26.5.2.1
26.5.2.2
26.5.2.3
26.5.2.4
26.6
26.6.1
26.6.1.1
26.7
26.7.1
26.7.2
26.7.2.1
26.7.2.2
26.7.2.3
26.7.2.4
Title
Page
Number
Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn) ......... 26-33
Rx and Tx FIFO Last Write Frame Pointer (PSCRLWFPn, PSCTLWFPn) ...... 26-34
Functional Description ................................................................................................ 26-35
UART Mode ........................................................................................................... 26-35
Multidrop Mode ...................................................................................................... 26-36
Modem8 Mode ........................................................................................................ 26-37
Modem16 Mode ...................................................................................................... 26-38
AC97 Mode ............................................................................................................. 26-39
Transmitter .......................................................................................................... 26-40
Receiver .............................................................................................................. 26-40
Low Power Mode ............................................................................................... 26-40
SIR Mode ................................................................................................................ 26-41
MIR Mode ............................................................................................................... 26-41
Data Format ........................................................................................................ 26-41
Serial Interaction Pulse (SIP) .............................................................................. 26-42
FIR Mode ................................................................................................................ 26-42
Data Format ........................................................................................................ 26-42
PSC FIFO System ................................................................................................... 26-43
RX FIFO ............................................................................................................. 26-44
TX FIFO ............................................................................................................. 26-45
Looping Modes ....................................................................................................... 26-46
Automatic Echo Mode ........................................................................................ 26-46
Local Loopback Mode ........................................................................................ 26-46
Remote Loopback Mode ..................................................................................... 26-47
Resets .......................................................................................................................... 26-47
General .................................................................................................................... 26-47
Description of Reset Operation ............................................................................... 26-47
Reset ................................................................................................................... 26-47
CRSRX ............................................................................................................... 26-47
CRSTX ............................................................................................................... 26-47
CRSES ................................................................................................................ 26-47
Interrupts ..................................................................................................................... 26-48
Description of Interrupt Operation ......................................................................... 26-48
Processor Interrupt .............................................................................................. 26-48
Software Environment ................................................................................................ 26-48
General .................................................................................................................... 26-48
Configuration .......................................................................................................... 26-49
UART Mode ....................................................................................................... 26-49
Modem8 Mode .................................................................................................... 26-50
Modem16 Mode .................................................................................................. 26-51
AC97 Mode ........................................................................................................ 26-51
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
26.7.2.5
26.7.2.6
26.7.2.7
26.7.3
26.7.3.1
26.7.3.2
Title
Page
Number
SIR Mode ............................................................................................................ 26-52
MIR Mode .......................................................................................................... 26-53
FIR Mode ............................................................................................................ 26-54
Programming .......................................................................................................... 26-55
MIR Mode .......................................................................................................... 26-55
FIR Mode ............................................................................................................ 26-56
Chapter 27
DMA Serial Peripheral Interface (DSPI)
27.1
27.2
27.3
27.4
27.4.1
27.4.2
27.5
27.5.1
27.5.2
27.5.2.1
27.5.2.2
27.5.2.3
27.5.2.4
27.5.2.5
27.5.2.6
27.6
27.6.1
27.6.2
27.6.3
27.6.4
27.6.5
27.6.6
27.6.7
27.6.8
27.6.9
27.7
27.7.1
27.7.2
27.7.2.1
27.7.2.2
27.7.2.3
Overview ....................................................................................................................... 27-1
Features ......................................................................................................................... 27-1
Block Diagram .............................................................................................................. 27-2
Modes of Operation ...................................................................................................... 27-2
Master Mode ............................................................................................................. 27-2
Slave Mode ............................................................................................................... 27-2
Signal Description ......................................................................................................... 27-3
Overview ................................................................................................................... 27-3
Detailed Signal Descriptions .................................................................................... 27-3
DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 27-3
DSPI Peripheral Chip Selects 2–3 (DSPICS[2:3]) ............................................... 27-3
DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 27-3
DSPI Serial Input (DSPISIN) ............................................................................... 27-4
DSPI Serial Output (DSPISOUT) ........................................................................ 27-4
DSPI Serial Clock (DSPISCK) ............................................................................. 27-4
Memory Map and Registers .......................................................................................... 27-4
DSPI Module Configuration Register (DMCR) ....................................................... 27-5
DSPI Transfer Count Register (DTCR) .................................................................... 27-7
DSPI Clock and Transfer Attributes Registers 0–7 (DCTARn) ............................... 27-7
DSPI Status Register (DSR) ................................................................................... 27-11
DSPI DMA/Interrupt Request Select Register (DIRSR) ........................................ 27-13
DSPI Tx FIFO Register (DTFR) ............................................................................ 27-15
DSPI Rx FIFO Register (DRFR) ............................................................................ 27-16
DSPI Tx FIFO Debug Registers 0–3 (DTFDRn) ................................................... 27-17
DSPI Rx FIFO Debug Registers 0–3 (DRFDRn) ................................................... 27-17
Functional Description ................................................................................................ 27-18
Start and Stop of DSPI Transfers ............................................................................ 27-19
Serial Peripheral Interface (SPI) ............................................................................ 27-20
Master Mode ....................................................................................................... 27-20
Slave Mode ......................................................................................................... 27-20
FIFO Disable Operation ..................................................................................... 27-21
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
27.7.2.4
27.7.2.5
27.7.3
27.7.3.1
27.7.3.2
27.7.3.3
27.7.3.4
27.7.3.5
27.7.4
27.7.4.1
27.7.4.2
27.7.4.3
27.7.4.4
27.7.4.5
27.7.5
27.7.6
27.7.6.1
27.7.6.2
27.7.6.3
27.7.6.4
27.7.6.5
27.7.6.6
27.8
27.8.1
27.8.2
27.8.3
27.8.4
27.8.4.1
27.8.4.2
Title
Page
Number
Tx FIFO Buffering Mechanism .......................................................................... 27-21
Rx FIFO Buffering Mechanism .......................................................................... 27-22
DSPI Baud Rate and Clock Delay Generation ....................................................... 27-22
Baud Rate Generator ........................................................................................... 27-23
CS to SCK Delay (tCSC) .................................................................................... 27-23
After DSPISCK Delay (tASC) ........................................................................... 27-23
Delay after Transfer (tDT) ................................................................................... 27-23
Peripheral Chip Select Strobe Enable (PCSS) .................................................... 27-24
Transfer Formats ..................................................................................................... 27-25
Classic SPI Transfer Format (CPHA = 0) .......................................................... 27-25
Classic SPI Transfer Format (CPHA = 1) .......................................................... 27-26
Modified SPI Transfer Format (MTFE = 1, CPHA = 0) .................................... 27-27
Modified SPI Transfer Format (MTFE = 1, CPHA = 1) .................................... 27-28
Continuous Selection Format ............................................................................. 27-29
Continuous Serial Communications Clock ............................................................. 27-30
Interrupts/DMA Requests ....................................................................................... 27-31
End of Queue Interrupt Request ......................................................................... 27-32
Transmit FIFO Fill Interrupt or DMA Request .................................................. 27-32
Transfer Complete Interrupt Request ................................................................. 27-32
Transmit FIFO Underflow Interrupt Request ..................................................... 27-32
Receive FIFO Drain Interrupt or DMA Request ................................................ 27-32
Receive FIFO Overflow Interrupt Request ......................................................... 27-32
Initialization and Application Information ................................................................. 27-33
How to Change Queues .......................................................................................... 27-33
Baud Rate Settings .................................................................................................. 27-33
Delay Settings ......................................................................................................... 27-34
Calculation of FIFO Pointer Addresses .................................................................. 27-35
Address Calculation for the First-in Entry and Last-in Entry in the Tx FIFO ... 27-36
Address Calculation for the First-in Entry and Last-in Entry in the Rx FIFO ... 27-36
Chapter 28
Interface
I2C
28.1
28.1.1
28.1.2
28.1.3
28.2
28.3
28.3.1
28.3.2
Introduction ................................................................................................................... 28-1
Block Diagram .......................................................................................................... 28-1
I2C Overview ............................................................................................................ 28-2
Features ..................................................................................................................... 28-2
External Signals ............................................................................................................ 28-2
Memory Map/Register Definition ................................................................................ 28-3
I2C Register Map ...................................................................................................... 28-3
Register Descriptions ................................................................................................ 28-3
MCF548x Reference Manual, Rev. 3
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Contents
Paragraph
Number
28.3.2.1
28.3.2.2
28.3.2.3
28.3.2.4
28.3.2.5
28.3.2.6
28.4
28.4.1
28.4.2
28.4.3
28.4.4
28.4.5
28.4.6
28.4.7
28.4.8
28.5
28.5.1
28.5.2
28.5.3
28.5.4
28.5.5
28.5.6
28.5.7
Title
Page
Number
I2C Address Register (I2ADR) ............................................................................. 28-3
I2C Frequency Divider Register (I2FDR) ............................................................ 28-4
I2C Control Register (I2CR) ................................................................................. 28-5
I2C Status Register (I2SR) .................................................................................... 28-5
I2C Data I/O Register (I2DR) ............................................................................... 28-7
I2C Interrupt Control Register (I2ICR) ................................................................ 28-7
Functional Description .................................................................................................. 28-8
START Signal ........................................................................................................... 28-9
Slave Address Transmission ..................................................................................... 28-9
STOP Signal ............................................................................................................. 28-9
Data Transfer ............................................................................................................ 28-9
Acknowledge .......................................................................................................... 28-10
Repeated Start ......................................................................................................... 28-11
Clock Synchronization and Arbitration .................................................................. 28-11
Handshaking and Clock Stretching ......................................................................... 28-12
Initialization Sequence ................................................................................................ 28-12
Transfer Initiation and Interrupt ............................................................................. 28-13
Post-Transfer Software Response ........................................................................... 28-14
Generation of STOP ................................................................................................ 28-15
Generation of Repeated START ............................................................................. 28-16
Slave Mode ............................................................................................................. 28-16
Arbitration Lost ....................................................................................................... 28-18
Flow Control ........................................................................................................... 28-18
Chapter 29
USB 2.0 Device Controller
29.1
29.1.1
29.1.2
29.1.3
29.1.3.1
29.1.3.2
29.1.3.3
29.1.3.4
29.1.3.5
29.2
29.2.1
29.2.2
29.2.2.1
29.2.2.2
Introduction ................................................................................................................... 29-1
Overview ................................................................................................................... 29-1
Features ..................................................................................................................... 29-1
Block Diagram .......................................................................................................... 29-2
Controller and Synchronization ............................................................................ 29-2
Descriptor RAM ................................................................................................... 29-2
FIFO Controller .................................................................................................... 29-3
FIFO RAM Manager ............................................................................................ 29-3
Integrated USB 2.0 Transceiver ........................................................................... 29-3
Memory Map/Register Definition ................................................................................ 29-4
USB Memory Map .................................................................................................... 29-4
USB Request, Control, and Status Registers ............................................................ 29-9
USB Status Register (USBSR) ............................................................................. 29-9
USB Control Register (USBCR) ........................................................................ 29-10
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
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Contents
Paragraph
Number
29.2.2.3
29.2.2.4
29.2.2.5
29.2.2.6
29.2.2.7
29.2.2.8
29.2.2.9
29.2.2.10
29.2.2.11
29.2.2.12
29.2.2.13
29.2.2.14
29.2.2.15
29.2.2.16
29.2.3
29.2.3.1
29.2.3.2
29.2.3.3
29.2.3.4
29.2.3.5
29.2.3.6
29.2.3.7
29.2.3.8
29.2.4
29.2.4.1
29.2.4.2
29.2.4.3
29.2.4.4
29.2.4.5
29.2.4.6
29.2.4.7
29.2.4.8
29.2.4.9
29.2.4.10
29.2.5
29.2.5.1
29.2.5.2
29.2.5.3
29.2.5.4
29.2.5.5
Title
Page
Number
USB Descriptor RAM Control Register (DRAMCR) ........................................ 29-12
USB Descriptor RAM Data Register (DRAMDR) ............................................ 29-13
USB Interrupt Status Register (USBISR) ........................................................... 29-14
USB Interrupt Mask Register (USBIMR) .......................................................... 29-15
USB Application Interrupt Status Register (USBAISR) .................................... 29-16
USB Application Interrupt Mask Register (USBAIMR) .................................... 29-17
Endpoint Info Register (EPINFO) ...................................................................... 29-18
USB Configuration Value Register (CFGR) ...................................................... 29-19
USB Configuration Attribute Register (CFGAR) .............................................. 29-19
USB Device Speed Register (SPEEDR) ............................................................. 29-20
USB Frame Number Register (FRMNUMR) ..................................................... 29-21
USB Endpoint Transaction Number Register (EPTNR) .................................... 29-21
USB Application Interface Update Register (IFUR) .......................................... 29-22
USB Configuration Interface Register (IFRn) .................................................... 29-22
USB Counter Registers ........................................................................................... 29-23
USB Packet Passed Count Register (PPCNT) .................................................... 29-23
USB Dropped Packet Counter Register (DPCNT) ............................................. 29-24
USB CRC Error Counter Register (CRCECNT) ................................................ 29-24
USB Bitstuffing Error Counter Register (BSECNT) .......................................... 29-24
USB PID Error Counter Register (PIDECNT) ................................................... 29-25
USB Framing Error Counter Register (FRMECNT) .......................................... 29-25
USB Transmitted Packet Counter Register (TXPCNT) ..................................... 29-26
USB Counter Overflow Register (CNTOVR) .................................................... 29-26
Endpoint Context Registers .................................................................................... 29-27
Endpoint n Attribute Control Register (EP0ACR, EPnOUTACR, EPnINACR) 29-27
Endpoint n Max Packet Size Register (EP0MPSR, EPnOUTMPSR, EPnINMPSR)
......................................................................................................................... 29-28
Endpoint n Interface Number Register (EP0IFR, EPnOUTIFR, EPnINIFR) .... 29-29
Endpoint n Status Register (EP0SR, EPnOUTSR, EPnINSR) ........................... 29-30
bmRequest Type Register (BMRTR) ................................................................. 29-31
bRequest Type Register (BRTR) ........................................................................ 29-32
wValue Register (WVALUER) .......................................................................... 29-32
wIndex Register (WINDEXR) ........................................................................... 29-33
wLength Register (WLENGTHR) ...................................................................... 29-33
Endpoint n Sync Frame Register (EPnOUTSFR, EPnINSFR) .......................... 29-33
USB Endpoint FIFO Registers ............................................................................... 29-34
USB Endpoint n Status and Control Register (EPnSTAT) ................................ 29-34
USB Endpoint n Interrupt Status Register (EPnISR) ......................................... 29-35
USB Endpoint n Interrupt Mask Register (EPnIMR) ......................................... 29-37
USB Endpoint n FIFO RAM Configuration Register (EPnFRCFGR) .............. 29-38
USB Endpoint n FIFO Data Register (EPnFDR) ............................................... 29-39
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Contents
Paragraph
Number
29.2.5.6
29.2.5.7
29.2.5.8
29.2.5.9
29.2.5.10
29.2.5.11
29.2.5.12
29.3
29.3.1
29.4
29.4.1
29.4.1.1
29.4.1.2
29.4.1.3
29.4.1.4
29.4.1.5
29.4.2
29.4.2.1
29.4.2.2
29.4.3
29.4.3.1
29.4.3.2
29.4.3.3
29.4.3.4
29.4.3.5
29.4.3.6
29.4.3.7
29.4.3.8
Title
Page
Number
USB Endpoint n FIFO Status Register (EPnFSR) ............................................. 29-40
USB Endpoint n FIFO Control Register (EPnFCR) ........................................... 29-42
USB Endpoint n FIFO Alarm Register (EPnFAR) ............................................ 29-44
USB Endpoint n FIFO Read Pointer (EPnFRP) ................................................. 29-45
USB Endpoint n FIFO Write Pointer (EPnFWP) ............................................... 29-45
USB Endpoint n Last Read Frame Pointer (EPnLRFP) ..................................... 29-46
USB Endpoint n Last Write Frame Pointer (EPnLWFP) ................................... 29-47
Functional Description ................................................................................................ 29-47
Interrupts ................................................................................................................. 29-47
Software Interface ....................................................................................................... 29-47
Device Initialization ................................................................................................ 29-47
USB Descriptor Download ................................................................................. 29-48
USB Interrupt Register ....................................................................................... 29-49
Endpoint Registers .............................................................................................. 29-49
FIFO Sizes ......................................................................................................... 29-50
Enable the Device ............................................................................................... 29-50
Exception Handling ................................................................................................ 29-50
Unable to Fill or Empty FIFO Due to Temporary Problem ............................... 29-50
Catastrophic Error ............................................................................................... 29-50
Data Transfer Operations ........................................................................................ 29-50
USB Packets ....................................................................................................... 29-51
Sending Packets .................................................................................................. 29-51
Receiving Packets ............................................................................................... 29-51
USB Transfers .................................................................................................... 29-52
Control Transfers ................................................................................................ 29-53
Bulk Traffic ........................................................................................................ 29-54
Interrupt Traffic .................................................................................................. 29-54
Isochronous Operations ...................................................................................... 29-55
Chapter 30
Fast Ethernet Controller (FEC)
30.1
30.1.1
30.1.2
30.1.3
30.1.4
30.1.5
30.1.5.1
30.1.5.2
30.1.5.3
Introduction ................................................................................................................... 30-1
MCF548x Family Products ....................................................................................... 30-1
Block Diagram .......................................................................................................... 30-1
Overview ................................................................................................................... 30-2
Features ..................................................................................................................... 30-3
Modes of Operation .................................................................................................. 30-3
Full and Half Duplex Operation ........................................................................... 30-3
Interface Options .................................................................................................. 30-3
Address Recognition Options ............................................................................... 30-4
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Contents
Paragraph
Number
30.1.5.4
30.2
30.2.1
30.2.2
30.2.3
30.2.4
30.2.5
30.2.6
30.2.7
30.2.8
30.2.9
30.2.10
30.2.11
30.2.12
30.3
30.3.1
30.3.2
30.3.3
30.3.3.1
30.3.3.2
30.3.3.3
30.3.3.4
30.3.3.5
30.3.3.6
30.3.3.7
30.3.3.8
30.3.3.9
30.3.3.10
30.3.3.11
30.3.3.12
30.3.3.13
30.3.3.14
30.3.3.15
30.3.3.16
30.3.3.17
30.3.3.18
30.3.3.19
30.3.3.20
30.3.3.21
30.3.3.22
30.3.3.23
Title
Page
Number
Internal Loopback ................................................................................................. 30-4
External Signals ............................................................................................................ 30-4
Transmit Clock (EnTXCLK) .................................................................................... 30-4
Receive Clock (EnRXCLK) ..................................................................................... 30-4
Transmit Enable (EnTXEN) ..................................................................................... 30-4
Transmit Data[3:0] (EnTXD[3:0]) ............................................................................ 30-4
Transmit Error (EnTXER) ........................................................................................ 30-5
Receive Data Valid (EnRXDV) ................................................................................ 30-5
Receive Data[3:0] (EnRXD[3:0]) ............................................................................. 30-5
Receive Error (EnRXER) ......................................................................................... 30-5
Carrier Sense (EnCRS) ............................................................................................. 30-5
Collision (EnCOL) .................................................................................................... 30-5
Management Data Clock (EnMDC) ......................................................................... 30-5
Management Data (EnMDIO) .................................................................................. 30-5
Memory Map/Register Definition ................................................................................ 30-6
Top Level Module Memory Map ............................................................................. 30-6
Detailed Memory Map (Control/Status Registers) ................................................... 30-7
MIB Block Counters Memory Map .......................................................................... 30-8
Ethernet Interrupt Event Register (EIR) ............................................................. 30-10
Interrupt Mask Register (EIMR) ........................................................................ 30-12
Ethernet Control Register (ECR) ........................................................................ 30-13
MII Management Frame Register (MMFR) ....................................................... 30-14
MII Speed Control Register (MSCR) ................................................................. 30-15
MIB Control Register (MIBC) ........................................................................... 30-17
Receive Control Register (RCR) ........................................................................ 30-17
Receive Hash Register (RHR) ............................................................................ 30-18
Transmit Control Register (TCR) ....................................................................... 30-19
Physical Address Low Register (PALR) ............................................................ 30-20
Physical Address High Register (PAHR) ........................................................... 30-21
Opcode/Pause Duration Register (OPD) ............................................................ 30-22
Individual Address Upper Register (IAUR) ....................................................... 30-22
Individual Address Lower Register (IALR) ....................................................... 30-23
Group Address Upper Register (GAUR) ............................................................ 30-24
Group Address Lower Register (GALR) ............................................................ 30-24
FEC Transmit FIFO Watermark Register (FECTFWR) .................................... 30-25
FEC Receive FIFO Data Register (FECRFDR) ................................................. 30-26
FEC Receive FIFO Status Register (FECRFSR) ................................................ 30-26
FEC Receive FIFO Control Register (FECRFCR) ............................................. 30-28
FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP) ............... 30-30
FEC Receive FIFO Last Write Frame Pointer Register (FECRLWFP) ............. 30-30
FEC Receive FIFO Alarm Register (FECRFAR) .............................................. 30-31
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Contents
Paragraph
Number
30.3.3.24
30.3.3.25
30.3.3.26
30.3.3.27
30.3.3.28
30.3.3.29
30.3.3.30
30.3.3.31
30.3.3.32
30.3.3.33
30.3.3.34
30.3.3.35
30.4
30.4.1
30.4.1.1
30.4.1.2
30.4.2
30.4.2.1
30.4.2.2
30.4.3
30.4.4
30.4.5
30.4.6
30.4.7
30.4.8
30.4.9
30.4.10
30.4.11
30.4.12
30.4.12.1
30.4.12.2
30.4.13
30.4.14
Title
Page
Number
FEC Receive FIFO Read Pointer Register (FECRFRP) ..................................... 30-32
FEC Receive FIFO Write Pointer Register (FECRFWP) ................................... 30-33
FEC Transmit FIFO Data Register (FECTFDR) ................................................ 30-33
FEC Transmit FIFO Status Register (FECTFSR) .............................................. 30-34
FEC Transmit FIFO Control Register (FECTFCR) ........................................... 30-36
FEC Transmit FIFO Last Read Frame Pointer Register (FECTLRFP) .............. 30-37
FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP) ............ 30-38
FEC Transmit FIFO Alarm Register (FECTFAR) ............................................. 30-39
FEC Transmit FIFO Read Pointer Register (FECTFRP) ................................... 30-40
FEC Transmit FIFO Write Pointer Register (FECTFWP) ................................. 30-40
FEC FIFO Reset Register (FECFRST) ............................................................... 30-41
FEC CRC and Transmit Frame Control Word Register (FECCTCWR) ............ 30-42
Functional Description ................................................................................................ 30-43
Initialization Sequence ............................................................................................ 30-43
Hardware Controlled Initialization ..................................................................... 30-43
User Initialization (Prior to Asserting ECR[ETHER_EN]) ................................ 30-43
Frame Control/Status Words .................................................................................. 30-44
Receive Frame Status Word (RFSW) ................................................................. 30-44
Transmit Frame Control Word (TFCW) ............................................................. 30-45
Network Interface Options ...................................................................................... 30-46
FEC Frame Transmission ....................................................................................... 30-46
FEC Frame Reception ............................................................................................. 30-47
Ethernet Address Recognition ................................................................................ 30-48
Hash Algorithm ....................................................................................................... 30-49
Full Duplex Flow Control ....................................................................................... 30-52
Inter-Packet Gap (IPG) Time .................................................................................. 30-53
Collision Handling .................................................................................................. 30-53
Internal and External Loopback .............................................................................. 30-53
Ethernet Error-Handling Procedure ........................................................................ 30-54
Transmission Errors ............................................................................................ 30-54
Reception Errors ................................................................................................. 30-55
MII Data Frame ...................................................................................................... 30-55
MII Management Frame Structure ......................................................................... 30-56
Chapter 31
Mechanical Data
31.1
31.2
31.3
31.3.1
Package ......................................................................................................................... 31-1
Pinout ............................................................................................................................ 31-1
Mechanical Diagrams ................................................................................................... 31-8
MCF5485/5484 Mechanical Diagram ...................................................................... 31-8
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Contents
Paragraph
Number
31.3.2
31.4
31.5
31.6
Title
Page
Number
MCF5483/5482 Mechanical Diagram .................................................................... 31-12
MCF5481/5480 Mechanical Diagram ........................................................................ 31-16
Mechanicals 388-pin PBGA Package Outline ............................................................ 31-20
Case Drawing .............................................................................................................. 31-20
Appendix A
MCF548x Memory Map
MCF548x Reference Manual, Rev. 3
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About This Book
The primary objective of this reference manual is to define the functionality of the MCF548x processors
for use by software and hardware developers.
The information in this book is subject to change without notice, as described in the disclaimers on the title
page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are
using the most recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/coldfire.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products for the MCF548x. It is assumed that the reader understands operating systems,
microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire
architecture.
Organization
Following is a summary and a brief description of the major sections of this manual:
• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in
the MCF548x, focussing in particular on new features.
• Chapter 2, “Signal Descriptions,” provides an alphabetical listing of MCF548x signals, including
which are inputs or outputs, how they are multiplexed, and the state of each signal at reset.
• Part I, “Processor Core,” is intended for system designers who need to understand the operation of
the MCF548x ColdFire core and its enhanced multiply/accumulate (EMAC) execution unit. It
describes the programming and exception models, Harvard memory implementation, and debug
module. Part 1 contains the following chapters:
— Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core of the
MCF548x. The chapter begins with a description of enhancements from the V3 ColdFire core,
and then fully describes the V4e programming model as it is implemented on the MCF548x. It
also includes a full description of exception handling, data formats, an instruction set summary,
and a table of instruction timings.
— Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the MCF548x
enhanced multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and
miscellaneous register instructions. The EMAC is integrated into the operand execution
pipeline (OEP).
— Chapter 5, “Memory Management Unit (MMU),” describes describes the ColdFire virtual
memory management unit (MMU), which provides virtual-to-physical address translation and
memory access control.
— Chapter 6, “Floating-Point Unit (FPU),” describes instructions implemented in the
floating-point unit (FPU) designed for use with the ColdFire family of microprocessors.
MCF548x Reference Manual, Rev. 3
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xli
•
•
— Chapter 7, “Local Memory,” describes the MCF548x implementation of the ColdFire V4e
local memory specification.
— Chapter 8, “Debug Support,” describes the Revision C enhanced hardware debug support in the
MCF548x. This revision of the ColdFire debug architecture encompasses earlier revisions.
Part II, “System Integration Unit,” describes the system integration unit, which provides overall
control of the bus and serves as the interface between the ColdFire core processor complex and
internal peripheral devices. It includes a general description of the SIU and individual chapters that
describe components of the SIU, such as the interrupt controller, general purpose timers, slice
timers, and GPIOs. Part II contains the following chapters:
— Chapter 9, “System Integration Unit (SIU),” describes the SIU programming model, bus
arbitration, and system-protection functions for the MCF548x.
— Chapter 10, “Internal Clocks and Bus Architecture,” describes the clocking and internal buses
of the MCF548x and discusses the main functional blocks controlling the XL bus and the XL
bus arbiter.
— Chapter 11, “General Purpose Timers (GPT),” describes the functionality of the four general
purpose timers, GPT0–GPT3.
— Chapter 12, “Slice Timers (SLT),” describes the two slice timers, shorter term periodic
interrupts, used in the MCF548x.
— Chapter 13, “Interrupt Controller,” describes operation of the interrupt controller portion of the
SIU. Includes descriptions of the registers in the interrupt controller memory map and the
interrupt priority scheme.
— Chapter 14, “Edge Port Module (EPORT),” describes EPORT module functionality.
— Chapter 15, “GPIO,” describes the operation and programming model of the parallel port pin
assignment, direction-control, and data registers.
Part III, “On-Chip Integration,” describes the on-chip integration for the MCF548x device. It
includes descriptions of the system SRAM, FlexBus interface, SDRAM controller, PCI, and SEC
cryptography accelerator. Part III contains the following chapters:
— Chapter 16, “32-Kbyte System SRAM,” describes the MCF548x on-chip system SRAM
implementation. It covers general operations, configuration, and initialization.
— Chapter 17, “FlexBus,” describes data transfer operations, error conditions, and reset
operations. It describes transfers initiated by the MCF548x and by an external master, and
includes detailed timing diagrams showing the interaction of signals in supported bus
operations.
— Chapter 18, “SDRAM Controller (SDRAMC),” describes configuration and operation of the
synchronous DRAM controller component of the SIU. It includes a description of signals
involved in DRAM operations, including chip select signals and their address, mask, and
control registers.
— Chapter 19, “PCI Bus Controller,” details the operation of the PCI bus controller for the
MCF548x.
— Chapter 20, “PCI Bus Arbiter Module,” describes the MCF548x PCI bus arbiter module,
including timing for request and grant handshaking, the arbitration process, and the register in
the PCI bus arbiter programing model.
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Suggested Reading
•
•
— Chapter 21, “FlexCAN,” describes the MCF548 implementation of the controller area network
(CAN) protocol. This chapter describes FlexCAN module operation and provides a
programming model.
— Chapter 22, “Integrated Security Engine (SEC),” provides an overview of the MCF548x
security encryption controller.
— Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of
the MCF548x JTAG test implementation. It describes the use of JTAG instructions and
provides information on how to disable JTAG functionality.
Part IV, “Communications Subsystem,” contains chapters that discuss the operation and
configuration of the communications I/O subsystem including the MCF548x multichannel DMA,
communications timer, PSC, FEC, DSPI, and USB2, and I2C.
— Chapter 24, “Multichannel DMA,” provides an overview of the multichannel DMA controller
module including the operation of the external DMA request signals.
— Chapter 25, “Comm Timer Module (CTM),” contains a detailed description of the
communications timer module, which functions as a baud clock generator or as a DMA task
initiator.
— Chapter 26, “Programmable Serial Controller (PSC),” provides an overview of asynchronous,
synchronous, and IrDA 1.1 compliant receiver/transmitter serial communications of the
MCF548x.
— Chapter 27, “DMA Serial Peripheral Interface (DSPI),” describes the use of the DMA serial
peripheral interface (DSPI) implemented on the MCF548x processor, including details of the
DSPI data transfers. The chapter concludes with timing diagrams and the DSPI features that
support Tx and Rx FIFO queue management.
— Chapter 28, “I2C Interface,” describes the MCF548x I2C module, including I2C protocol,
clock synchronization, and the registers in the I2C programing model. It also provides
programming examples.
— Chapter 29, “USB 2.0 Device Controller,” provides an overview of the USB 2.0 device
controller module used in the MCF548x.
— Chapter 30, “Fast Ethernet Controller (FEC),” provides a feature-set overview, a functional
block diagram, and transceiver connection information for both MII (Media Independent
Interface) and 7-wire serial interfaces. It also provides describes operation and the
programming model.
Part V, “Mechanical,” provides a pinout and both electrical and functional descriptions of the
MCF548x signals. It also describes how these signals interact to support the variety of bus
operations shown in timing diagrams.
— Chapter 31, “Mechanical Data,” provides a functional pin listing and package diagram for the
MCF548x.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the ColdFire architecture.
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General Information
The following documentation provides useful information about the ColdFire architecture and computer
architecture in general:
• ColdFire Programmers Reference Manual (CFPRM)
• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross
Bannatyne, Joseph D. Greenfield
• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David
A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.
Patterson and John L. Hennessy.
ColdFire Documentation
The ColdFire documentation is available from the sources listed on the back cover of this manual.
Document order numbers are included in parentheses for ease in ordering.
• ColdFire Programmers Reference Manual, R1.0 (CFPRM)
• Reference manuals—These books provide details about individual ColdFire implementations and
are intended to be used in conjunction with The ColdFire Programmers Reference Manual. These
include the following:
— ColdFire CF4e Core User's Manual (V4ECFUM)
— MCF5475 Reference Manual (MCF5475RM)
— MCF5485 Reference Manual (MCF5485RM)
Additional literature on ColdFire implementations is being released as new processors become available.
For a current list of ColdFire documentation, refer to the World Wide Web at
http://www.freescale.com/coldfire.
Conventions
This document uses the following notational conventions:
MNEMONICS
In text, instruction mnemonics are shown in uppercase.
mnemonics
In code and tables, instruction mnemonics are shown in lowercase.
italics
Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
REG[FIELD]
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.
nibble
A 4-bit data unit
byte
An 8-bit data unit
word
A 16-bit data unit
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Acronyms and Abbreviations
longword
x
n
¬
&
|
A 32-bit data unit
In some contexts, such as signal encodings, x indicates a don’t care.
Used to express an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
Register Conventions
This reference manual uses the register diagram format shown below.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
DFL
W
Reset
Reg
Addr
0
0
0
0x00C
Table i. Example Register Diagram
Acronyms and Abbreviations
Table ii lists acronyms and abbreviations used in this document.
Table ii. . Acronyms and Abbreviated Terms
Term
Meaning
ADC
Analog-to-digital conversion
ALU
Arithmetic logic unit
AVEC
Autovector
BDM
Background debug mode
BIST
Built-in self test
BSDL
Boundary-scan description language
CODEC
Code/decode
comm bus
Internal communications bus
DAC
Digital-to-analog conversion
DMA
Direct memory access
DSP
Digital signal processing
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Table ii. . Acronyms and Abbreviated Terms (continued)
Term
Meaning
EA
Effective address
EDO
Extended data output (DRAM)
FIFO
First-in, first-out
GPIO
General-purpose I/O
2
I C
Inter-integrated circuit
IEEE
Institute for Electrical and Electronics Engineers
IFP
Instruction fetch pipeline
IPL
Interrupt priority level
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LIFO
Last-in, first-out
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
MAC
Multiple accumulate unit
MBAR
Memory base address register
MSB
Most-significant byte
msb
Most-significant bit
Mux
Multiplex
NOP
No operation
OEP
Operand execution pipeline
PC
Program counter
PCLK
Processor clock
PLL
Phase-locked loop
PLRU
Pseudo least recently used
POR
Power-on reset
PQFP
Plastic quad flat pack
RISC
Reduced instruction set computing
Rx
Receive
SIM
System integration module
SOF
Start of frame
TAP
Test access port
TTL
Transistor-to-transistor logic
Tx
Transmit
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Terminology and Notational Conventions
Table ii. . Acronyms and Abbreviated Terms (continued)
Term
Meaning
UART
Universal asynchronous/synchronous receiver transmitter
XLB bus
Internal 64-bit bus
Terminology and Notational Conventions
Table iii shows notational conventions used throughout this document.
Table iii. Notational Conventions
Instruction
Operand Syntax
Opcode Wildcard
cc
Logical condition (example: NE for not equal)
Register Specifications
An
Ay,Ax
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Dn
Any data register n (example: D5 is data register 5)
Dy,Dx
Source and destination data registers, respectively
Rc
Any control register (example VBR is the vector base register)
Rm
MAC registers (ACC, MAC, MASK)
Rn
Any address or data register
Rw
Destination register w (used for MAC instructions only)
Ry,Rx
Xi
Any source and destination registers, respectively
index register i (can be an address or data register: Ai, Di)
Register Names
ACC
MAC accumulator register
CCR
Condition code register (lower byte of SR)
MACSR
MAC status register
MASK
MAC mask register
PC
Program counter
SR
Status register
Port Name
PSTDDATA
Processor status/debug data port
Miscellaneous Operands
#<data>
<ea>
Immediate data following the 16-bit operation word of the instruction
Effective address
MCF548x Reference Manual, Rev. 3
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Table iii. Notational Conventions (continued)
Instruction
<ea>y,<ea>x
<label>
<list>
Operand Syntax
Source and destination effective addresses, respectively
Assembly language program label
List of registers for MOVEM instruction (example: D3–D0)
<shift>
Shift operation: shift left (<<), shift right (>>)
<size>
Operand data size: byte (B), word (W), longword (L)
bc
Both instruction and data caches
dc
Data cache
ic
Instruction cache
# <vector>
<>
<xxx>
Identifies the 4-bit vector number for trap instructions
identifies an indirect data address referencing memory
identifies an absolute address referencing memory
dn
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
+
Arithmetic addition or postincrement indicator
–
Arithmetic subtraction or predecrement indicator
x
Arithmetic multiplication
/
Arithmetic division
~
Invert; operand is logically complemented
&
Logical AND
|
Logical OR
^
Logical exclusive OR
<<
Shift left (example: D0 << 3 is shift D0 left 3 bits)
>>
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→
Source operand is moved to destination operand
←→
Two operands are exchanged
sign-extended
All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition>
then
<operations>
else
<operations>
Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the
optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.
Subfields and Qualifiers
{}
Optional operation
()
Identifies an indirect address
dn
Displacement value, n-bits wide (example: d16 is a 16-bit displacement)
MCF548x Reference Manual, Rev. 3
xlviii
Freescale Semiconductor
Terminology and Notational Conventions
Table iii. Notational Conventions (continued)
Instruction
Address
Operand Syntax
Calculated effective address (pointer)
Bit
Bit selection (example: Bit 3 of D0)
lsb
Least significant bit (example: lsb of D0)
LSB
Least significant byte
LSW
Least significant word
msb
Most significant bit
MSB
Most significant byte
MSW
Most significant word
Condition Code Register Bit Names
C
Carry
N
Negative
V
Overflow
X
Extend
Z
Zero
Table iv. MCF548x Revision History
Section/Page
Substantive Changes
Revision 1.0 (03/2004)
Initial release.
Revision 1.1 (03/2004
Figure 15-1/Page 15-2
Changed instances of FEC2 to FEC1 and FEC1 to FEC0.
30.3.1/30-6–
30.3.3.1/30-10
Changed instances of FEC2 to FEC1 and FEC1 to FEC0.
Revision 1.2 (03/2004)
Revision 2.0 (10/2004)
Many content changes, the biggest being greatly enhancing the MC-DMA chapter and adding Clocks and
Internal Buses chapter. Many editorial changes.
Revision 2.1 (10/2004)
Chapter 17
Took out FlexCan chapter. Fixed timing diagrams in FlexBus chapter.
Revision 3.0 (01/2006)
Throughout
Added all documentation errata from Revision 3 of the MCF5485RMAD document as described below.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
xlix
Table iv. MCF548x Revision History (continued)
Section/Page
Substantive Changes
Table 2-1/2-3
Add column to indicate whether the signal has a pull-up resistor.
These signals have a pull-up resistor at all times:
DSCLK/TRST, BKPT/TMS, DSI/TDI
These signals have a pull-up resistor whenever configured for general-purpose input (default state after
reset):
PCIBR[4:3], PCIGNT[4:3], E1MDIO, E1MDC, E1TXCLK, E1TXEN, E1TXD[3:0], E1COL, E1RXCLK,
E1RXDV, E1RXD[3:0], E1CRS, E1TXER, E1RXER
Table 2-1/2-3
Remove overbars from the following signals: FBADDR1, FBADDR0, SDDATA, SDADDR, SDBA, TIN3,
TOUT3
Table 2-1/2-3
In entry AD6, remove overbar from ALE and change description from “Transfer start” to “Address latch
enable”
Table 2-1/2-3
Add overbars to IRQ[6:5].
Table 2-2/2-10
• Replace PPSCLn entries under the GPIO column with PPSC1PSC0n. There is no PPSCL port.
• Replace PPSCHn entries under the GPIO column with PPSC3PSC2n. There is no PPSCH port.
Table 2-2/2-10
The GPIO bit number for each of the UART control signals are incorrect for Table 2-2. However, they are
correct for Table 2-1:
• Y23/PSC1RTS pin: Change GPIO entry from PPSCL7 to PPSC1PSC06.
• AB23/PSC3RTS pin: Change GPIO entry from PPSCH7 to PPSC3PSC26.
• AB26/PSC0RTS pin: Change GPIO entry from PPSCL3 to PPSC1PSC02.
• AC19/PSC2CTS pin: Change GPIO entry from PPSCH2 to PPSC3PSC23.
• AD26/PSC2RTS pin: Change GPIO entry from PPSCH3 to PPSC3PSC22.
• AE23/PSC0CTS pin: Change GPIO entry from PPSCL2 to PPSC1PSC03.
• AF23/PSC3CTS pin: Change GPIO entry from PPSCH6 to PPSC3PSC27.
• AF25/PSC1CTS pin: Change GPIO entry from PPSCL6 to PPSC1PSC07.
Table 2-2/2-10
Remove overbars from the following signals: IVDD, TCK, PLLVDD, PSTDDATA1, PSTDDATA7, SDDATA21,
PSTDDATA2, E1RXCLK, E1RXD2, SDVDD, SDDATA31, SDADDR4, DSCLK, VSS, EVDD, PCIAD29,
PCIAD30, SCL, SDDATA16, AD17, AD20, E1CRS, E0TXD2, TOUT2, TOUT1, PSC2TXD, ALE, E0TXD3,
SDBA1, SDBA0, USBVDD, PSC3RXD, AD25, USBRBIAS, TIN1, TIN2, TIN0
Table 2-2/2-10
Add overbars to the following signals: IRQ3, IRQ2
Table 2-4/2-22
Replace table with the following:
Table 1. MCF548x Divide Ratio Encodings
AD[12:8]1
00011
1
2
Internal XLB, SDRAM
bus, and PSTCLK
Frequency Range (MHz)
Core Frequency
Range (MHz)
41.6–50.0
83.33–100
166.66–200
100.0–166.66
200
Clock CLKIN–PCI and FlexBus
Ratio Frequency Range (MHz)
1:2
00101
1:2
25.0–41.5
50.0–83.02
01111
1:4
25.0
100
All other values of AD[12:8] are reserved.
Note that DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy
down to 75 MHz. Check with the memory component specifications to verify.
MCF548x Reference Manual, Rev. 3
l
Freescale Semiconductor
Terminology and Notational Conventions
Table iv. MCF548x Revision History (continued)
Section/Page
2.2.6.1/2-22
Substantive Changes
Add the following after Table 2-4:
Figure 1 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
Internal Clock
CLKIN
Core Clock
2x
2x
25.0
50.0
50.0
100.0
100.0
200.0
2x
4x
25.0
100.0
200.0
25 40 50 60 70
30 40 50 60 70 80 90 100
60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
CLKIN (MHz)
Internal Clock (MHz)
Core Clock (MHz)
Figure 1. CLKIN, Internal Bus, and Core Clock Ratios
3.8.1/3-38
Change the second sentence of the first paragraph from “The second holds the 32-bit program counter
address of the faulted instruction.“ to “The second holds the 32-bit program counter address of the faulted
or interrupted instruction.”
Table 3-23/3-40
The “Interrupt exception” entry’s description is outdated. Change from “Interrupt exception processing, with
interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those
where the requesting device supplies the 8-bit interrupt vector. Autovectoring can optionally be configured
through the system interface module (SIM).” to “Please refer to Chapter 13 ‘Interrupt Controller.’”
Table 10-2/10-5
Add missing table using Table 1 from this document.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
li
Table iv. MCF548x Revision History (continued)
Section/Page
Substantive Changes
10.2/10-5
Insert the following section before section 10.2 “XL Bus Arbiter”.
10.2 PLL
10.2.1 PLL Memory Map/Register Descriptions
Table 2. System PLL Memory Map
MBAR Offset
Name
Byte0
0x300
System PLL Control Register
Byte1
Byte2
Byte3
Access
SPCR
R/W
10.2.2 System PLL Control Register (SPCR)
The system PLL control register (SPCR) defines the clock enables used to control clocks to a set of peripherals. Unused peripherals
can have their clock stopped, reducing power consumption. In addition, the SPCR contains a read-only bit for the system PLL lock
status. At reset, the clock enables are set, enabling all system PLL gated output clocks.
31
R PLLK
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
W
Reset
R
1
15
14
13
12
11
10
9
8
7
0
COR
EN
CRY
ENB
CRY
ENA
CAN1
EN
0
PSC
EN
0
USB
EN
0
1
1
1
1
1
1
1
1
W
Reset
Addr
FEC1 FEC0 DMA CAN0
EN
EN
EN
EN
1
1
1
1
2
1
0
FB
EN
PCI
EN
MEM
EN
1
1
1
MBAR + 0x300
Figure 2. System PLL Control Register (SPCR)
Table 3. SPCR Field Descriptions
Bits
Name
31
PLLK
Description
System PLL Lock Status - Read-only lock status of the system PLL.
1 PLL has obtained frequency lock
0 PLL has not locked
30-15
—
14
COREN
Core & Communications Sub-System Clock Enable - Controls clocks for the CF4 Core, System SRAM, CommBus
Arbiter, I2C, Comm Timers, and External DMA modules
13
CRYENB
Crypto Clock Enable B - Controls the fast clock to the SEC
12
CRYENA
Crypto Clock Enable A - Controls the slow clock to the SEC
11
CAN1EN
CAN1 Clock Enable
10
—
9
PSCEN
Reserved, should be cleared.
Reserved, should be cleared.
PSC Clock Enable - Controls clock for all PSC modules.
8
—
7
USBEN
USB Clock Enable
Reserved, should be cleared.
6
FEC1EN
FEC1 Clock Enable
5
FEC0EN
FEC0 Clock Enable
4
DMAEN
Multi-channel DMA Clock Enable
3
CAN0EN
2
FBEN
FlexBus Clock Enable
1
PCIEN
PCI Bus Clock Enable
0
MEMEN
CAN0 Clock Enable
Memory Clock Enable - Controls clocks of the SDRAM controller module
MCF548x Reference Manual, Rev. 3
lii
Freescale Semiconductor
Terminology and Notational Conventions
Table iv. MCF548x Revision History (continued)
Section/Page
Substantive Changes
Table 10-3/10-5
Bits BA, DT, and AT: The 0 and 1 are switched. Setting each bit enables operation, while clearing disables
operation. The 0 and 1 (or the corresponding descriptions) need to be swapped for all three bits.
11.4.2/11-8
Remove all text from bullet item #2 starting with “This scenario works for all pulses except....” This errata
does not apply to this processor.
13.1.1/13-1
Correct the cross-reference link at top of page that reads “Section 3.8.1, ‘Exception Stack Frame
Definition.’”
Table 15-27/15-24
In the bit 7-6, PAR1_E1MDC entry, change ‘11’ bit setting description from: “E1MDC pin configured for
FEC1 MDC function” to “E1MDC pin configured for FEC1 E1MDC function” to be consistent with rest of
section.
Table 15-34/15-30
Remove extraneous “/” from “DSPICS0//SS” in second sentence of the PAR_CS0 bit description.
Table 16-1/16-2
Extend SSCR entry to include bytes 2 & 3 as well as bytes 0 and 1, since it is a 32 bit register.
17.6.5.4.2/17-23
Change “transfer start” to “address latch enable” in second sentence.
21.4.9/21-28
Figure 21-14 and Table 21-18 are missing. Add them as shown below and correct the cross-references to
them.
NRZ Signal
SYNC_SEG
Time Segment 1
(PROP_SEG + PSEG1 + 2)
1
4 ... 16
Time Segment 2
(PSEG2 + 1)
2 ... 8
8 ... 25 Time Quanta
= 1 Bit Time
Transmit Point
Syntax
Sample Point
(single or triple sampling)
Figure 21-14. Segments within the Bit Time
Table 21-18. Time Segment Syntax
Description
SYNC_SEG
System expects transitions to occur on the bus during this period.
Transmit Point
A node in transmit mode transfers a new value to the CAN bus at this point.
Sample Point
A node samples the bus at this point. If the three samples per bit option is selected,
then this point marks the position of the third sample.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
liii
Table iv. MCF548x Revision History (continued)
Section/Page
Substantive Changes
21.4.9/21-28
Add the following table below the note at the end of the section and correct the cross-reference pointing to
it:
Table 21-19. CAN Standard Compliant Bit Time Segment Settings
Table 23-5/23-7
Time Segment 1
Time Segment 2
Re-synchronization
Jump Width
5 .. 10
2
1 .. 2
4 .. 11
3
1 .. 3
5 .. 12
4
1 .. 4
6 .. 13
5
1 .. 4
7 .. 14
6
1 .. 4
8 .. 15
7
1 .. 4
9 .. 16
8
1 .. 4
The JTAG IR codes are incorrect. Replace table with the following:
F
Instruction IR[5:0]
Instruction Summary
EXTEST
000000 Selects boundary scan register while applying fixed values to output
pins and asserting functional reset
SAMPLE
000001 Selects boundary scan register for shifting, sampling, and preloading
without disturbing functional operation
IDCODE
011101 Selects IDCODE register for shift
CLAMP
011111 Selects bypass while applying fixed values to output pins and
asserting functional reset
HIGHZ
111101 Selects bypass register while tri-stating all output pins and asserting
functional reset
ENABLE
000010 Selects TEST_CTRL register
BYPASS
111111 Selects bypass register for data operations
23.4.3/23-7
Remove the TEST_LEAKAGE section, as the instruction is not supported.
23.4.3/23-7
Remove the LOCKOUT_RECOVERY section, as the instruction is not supported.
Table 24-18/24-20
24.3.4.2/24-20
Correct Base Address Mask Register 1 mnemonic from EREQMASK0 to EREQMASK1.
Correct overbar in first sentence. From “After DREQ is asserted, this register contains...” to “After DREQ
is asserted, this register contains...”
MCF548x Reference Manual, Rev. 3
liv
Freescale Semiconductor
Terminology and Notational Conventions
Table iv. MCF548x Revision History (continued)
Section/Page
25.1.2/25-2
Substantive Changes
Add the following section after section 24.1.2:
24.1.3 Comm Timer External Clock[7:0]
The comm timer external clock is the alternate clock signal and is provided by the user. The user must write
a 1 to CTCR[S] in the variable channel and write a 1001 to CTCR[S] within the fixed channel to select this
signal. If this signal is selected, all timing will be with respect to this clock signal. This signal is restricted to
being half the frequency or less of the system bus clock.
Table 0-4. Comm Timers External Clock
Timer Channel
External Signal
0
TIN0
1
TIN1
2
TIN2
3
TIN3
4
PSC3BCLK
5
PSC2BCLK
6
PSC1BCLK
7
PSC0BCLK
Table 25-3/25-5
In the S bit description change the 1001 setting from “Reserved” to “External clock”
Table 25-4/25-6
The S bit field is incorrect. Bits 31-29 should be reserved, and only bit 28 should be the S bit. And the S bit
description should be:
Clock enable source select. Selects the clock rate for the fixed timer channels. The clock rate for the timer
is the internal system clock divided by an 8-bit prescaler.
1 External Clock
0 Sysclk
Note: The external bus clock cannot be an faster than half the frequency of the system clock.
26.1/26-1
Fix broken cross-reference to Figure 26-1.
Table 26-13/26-19
In description of TXRDY change PSCTFALARM to PSCTFAR
Table 26-30/26-29
In description of ALARM change instance of “less than alarm bytes” to “more than alarm bytes” and change
instance of “more than alarm bytes” to “less than alarm bytes”.
26.3.3.24/26-30
Figure 26-22/Page
26-32
26.4/26-35
Figure 28-1/Page 28-1
Change bit 30 to reserved, as the WFR field is only one-bit wide.
Remove shading from W field as the PSCRFARn and PSCTFARn registers are R/W accessible.
Add section 15.3.7 “PSC FIFO System” from the MPC5200 User’s Manual to before section 26.4.9
“Looping Modes.” Change the following text to apply to the MCF548x:
MPC5200 → MCF5478x
BestComm → Multichannel DMA
MR1 → PSCMR1n
SR→ PSCSRn
ORERR → ERR
Change IFDR to I2FDR and IADR to I2ADR in figure.
28.3.2.1/28-3
Change instances of I2AR to I2ADR.
28.3.2.3/28-5
Change I2ICR to I2CR throughout section.
Chapter 28, “I2C
Interface”
After section 27.3.2.4, change instances of R/W to R/W throughout chapter.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
lv
Table iv. MCF548x Revision History (continued)
Section/Page
27.6.1/27-5
Substantive Changes
Remove instances of MDIS bit as it is not present on this version of the DSPI.
Table 29-3/29-11
USBCR[APPLOCK] bit description, the bit setting numbers are incorrrect. When cleared (0), APPLOCK is
deasserted. When set (1), APPLOCK is asserted.
Table 29-29/29-30
Endpoint status register’s PSTALL entry: the last sentence should be “Setting this bit also sets
USBAISR[EPSTALL].” instead of “Setting this bit also sets USBAISR[EPHALT].”
Table 29-37/29-36
EPnISR[EOT] bit description, add a note to the last sentence of the first paragraph stating “The EOT
interrupt will not assert for an isochronous OUT packet that experiences a PID sequencing error.”
29.4.3.1/29-51
Add a section below USB Packets entitled “Handshakes” with the following paragraphs:
“The USB device will return a NYET handshake packet to an OUT transaction if there is already data
present in the FIFO and there are less than 2*MAXPACKETSIZE bytes free in the FIFO.
In cases where the FIFO depth is larger than 2*MAXPACKETSIZE (i.e. 3x or 4x), the following behavior
will occur. If after a transfer that returned a NYET handshake there is at least 1*MAXPACKETSIZE of free
space in the FIFO, the device will ACK the first PING request from the host and accept another
MAXPACKETSIZE transfer from the host. The device will again send a NYET handshake.
The only time the device will NAK a PING is when there is less than 1*MAXPACKETSIZE of free space in
the FIFO.”
Table 30-41/30-42
Change bit description of the FECFRST[SW_RST] bit to “Software Reset - This bit controls the soft reset
of the FEC FIFOs. A soft reset will reset the FIFO pointers and byte counters but not the status and control
registers. To cause a soft reset this bit should be set and then cleared by application software.”
Change bit description of the FECFRST[RST_CTL] bit to “Reset control - Setting this bit allows the FEC
controller to perform a soft reset of the FIFOs when the FEC is disabled (ECR[ETHER_EN] cleared).”
Table 31-1/31-1
Add column to indicate whether the signal has a pull-up resistor.
These signals have a pull-up resistor at all times:
DSCLK/TRST, BKPT/TMS, DSI/TDI
These signals have a pull-up resistor whenever configured for general-purpose input (default state after
reset):
PCIBR[4:3], PCIGNT[4:3], E1MDIO, E1MDC, E1TXCLK, E1TXEN, E1TXD[3:0], E1COL, E1RXCLK,
E1RXDV, E1RXD[3:0], E1CRS, E1TXER, E1RXER
Table 31-1/31-1
Ball P3 should be SD_VDD instead of EVDD.
Table 31-1/31-1
The GPIO bit number for each of the UART control signals are incorrect for Table 31-1. However, they are
correct for Table 2-1:
• Y23/PSC1RTS pin: Change GPIO entry from PPSCL7 to PPSC1PSC06.
• AB23/PSC3RTS pin: Change GPIO entry from PPSCH7 to PPSC3PSC26.
• AB26/PSC0RTS pin: Change GPIO entry from PPSCL3 to PPSC1PSC02.
• AC19/PSC2CTS pin: Change GPIO entry from PPSCH2 to PPSC3PSC23.
• AD26/PSC2RTS pin: Change GPIO entry from PPSCH3 to PPSC3PSC22.
• AE23/PSC0CTS pin: Change GPIO entry from PPSCL2 to PPSC1PSC03.
• AF23/PSC3CTS pin: Change GPIO entry from PPSCH6 to PPSC3PSC27.
• AF25/PSC1CTS pin: Change GPIO entry from PPSCL6 to PPSC1PSC07.
Table 31-1/31-1
Remove overbar from ALE at location AD6.
Table 31-1/31-1
• Replace PPSCLn entries under the GPIO column with PPSC1PSC0n. There is no PPSCL port.
• Replace PPSCHn entries under the GPIO column with PPSC3PSC2n. There is no PPSCH port.
MCF548x Reference Manual, Rev. 3
lvi
Freescale Semiconductor
Terminology and Notational Conventions
Table iv. MCF548x Revision History (continued)
Section/Page
Substantive Changes
Figure 31-3/Page 31-10
Remove overbar from ALE at location AD6.
Figure 31-7/Page 31-14
Remove overbar from ALE at location AD6.
Figure 31-11/Page
31-18
Remove overbar from ALE at location AD6.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
lvii
MCF548x Reference Manual, Rev. 3
lviii
Freescale Semiconductor
Chapter 1
Overview
This chapter provides an overview of the MCF548x microprocessor features, including the major
functional components.
1.1
MCF548x Family Overview
The MCF548x family is based on the ColdFire V4e core, a complex which comprises the ColdFire V4
central processor unit (CPU), an enhanced multiply-accumulate unit (EMAC), a memory management unit
(MMU), a double-precision floating point unit (FPU) conforming to standard IEEE-754, and controllers
for caches and local data memories. The MCF548x family is capable of performing at an operating
frequency of up to 200 MHz or 308 MIPS (Dhrystone 2.1).
To maximize throughput, the MCF548x family incorporates three independent external bus interfaces:
1. The general-purpose local bus (FlexBus) is used for system boot memories and simple peripherals
and has up to six chip selects.
2. Program code and data can be stored in SDRAM connected to a dedicated 32-bit double data rate
(DDR) bus that can run at up to one-half of the CPU core frequency. The glueless DDR SDRAM
controller handles all address multiplexing, input and output strobe timing, and memory bus clock
generation.
3. A 32-bit PCI bus compliant with the version 2.2 specification and running at a typical frequency
of 33 MHz or 66 MHz supports peripherals that require high bandwidth, the ability to arbitrate for
bus mastership, and access to internal MCF548x memory resources.
The MCF548x family provides substantial communications functionality by integrating the following
connectivity peripherals:
• Up to two 10/100 Mbps fast Ethernet controllers (FECs)
• One optional USB 2.0 device (slave) module with seven endpoints and an integrated transceiver
• Up to four UART/USART/IRDA/modem programmable serial controllers (PSCs)
• One DMA serial peripheral interface (DSPI)
• One inter-integrated circuit (I2C™) bus controller
• Two controller area network 2.0B (FlexCAN) interfaces with 16 message buffers each
Additionally, the MCF548x provides hardware support for a range of Internet security standards with an
optional bus-mastering cryptography accelerator. This module incorporates units to speed DES/3DES and
AES block ciphers, the RC4 stream cipher, bulk data hashing (MD5/SHA-1/SHA-256/HMAC), and
random number generation. Hardware acceleration of these functions is critical to avoiding the throughput
bottlenecks associated with software-only implementations of SSH, SSL/TLS, IPsec, SRTP, WEP, and
other security standards. The incorporation of cryptography acceleration makes the MCF548x family a
compelling solution for a wide range of office automation, industrial control, and SOHO networking
devices that must have the ability to securely transmit critical equipment control information across
typically insecure Ethernet data networks.
Additional features of MCF548x products include a watchdog timer, two 32-bit slice timers for RTOS
scheduling and alarm functionality, up to four 32-bit general-purpose timers with capture, compare, and
pulse width modulation capability, a multisource vectored interrupt controller, a phase-locked loop (PLL)
to generate the system clock, 32 Kbytes of SRAM for high-speed local data storage, and multiple
general-purpose I/O ports.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
1-1
With on-chip support for multiple common communications interfaces, MCF548x products require only
the addition of memories and certain physical layer transceivers to be cost-effective system solutions for
many applications. Such applications include industrial routers, high-end POS terminals, building
automation systems, and process control equipment.
MCF548x products require four supply voltages: 1.5V for the high-performance, low power, internal core
logic, 2.5V for the DDR SDRAM bus interface, 1.25V for the DDR SDRAM VREF, and 3.3V for all other
I/O functionality, including the PCI and FlexBus interfaces.
1.2
MCF548x Block Diagram
Figure 1-1 shows a top-level block diagram of the MCF548x products.
ColdFire V4e Core
FPU, MMU
EMAC
32K D-cache
32K I-cache
PLL
DDR SDRAM
Interface
FlexBus
Interface
XL Bus
Arbiter
Memory
Controller
FlexBus
Controller
Cryptography
Accelerator3
XL Bus
Read/Write
Write
DMA
DMA
Bus
Read
32K System
SRAM
GP
Timers x 4
PCI 2.2
Controller
Multichannel DMA
Master Bus Interface and FIFOs
FlexCAN
x2
PCI Interface
& FIFOs
CommBus
DSPI
I2C
PSC x 4
FEC1
FEC22
Perpheral Communications I/O Interface & Ports
USB 2.0
DEVICE1
Communications
I/O Subsystem
Slice
Timers x 2
PCI I/O Interface and Ports
Watchdog
Timer
R/W
Master/Slave
Interface
Crypto
Interrupt
Controller
Slave
Perpheral I/O Interface & Ports
System
Integration Unit
XL Bus
USB 2.0
PHY1
1
Available in MCF5485, MCF5484, MCF5483, and MCF5482 devices.
Available in MCF5485, MCF5484, MCF5481, and MCF5480 devices.
3 Available in MCF5485, MCF5483, and MCF5481 devices.
2
Figure 1-1. MCF548x Block Diagram
MCF548x Reference Manual, Rev. 3
1-2
Freescale Semiconductor
MCF548x Family Products
1.3
MCF548x Family Products
Table 1-1 summarizes the products available within the MCF548x product family. All products are
available in pin-compatible, 388-pin PBGA packaging allowing for ease of migration between products
within the family. A printed circuit board designed using the MCF5485/4 footprint is compatible with any
of the MCF548x family devices.
Table 1-1. MCF548x Family Products
1.4
•
Product
Performance
Features
MCF5485
308 MIPS
200 MHz
Two 10/100 Ethernet Controllers
Two CAN Controllers
USB 2.0 Device with Integrated PHY
v2.2 PCI Controller
DDR Memory Controller
Encryption Accelerator
MCF5484
308 MIPS
200 MHz
Two 10/100 Ethernet Controllers
Two CAN Controllers
USB 2.0 Device with Integrated PHY
v2.2 PCI Controller
DDR Memory Controller
MCF5483
255 MIPS
166 MHz
One 10/100 Ethernet Controller
Two CAN Controllers
USB 2.0 Device with Integrated PHY
v2.2 PCI Controller
DDR Memory Controller
Encryption Accelerator
MCF5482
255 MIPS
166 MHz
One 10/100 Ethernet Controller
Two CAN Controllers
USB 2.0 Device with Integrated PHY
v2.2 PCI Controller
DDR Memory Controller
MCF5481
255 MIPS
166 MHz
Two 10/100 Ethernet Controllers
Two CAN Controllers
v2.2 PCI Controller
DDR Memory Controller
Encryption Accelerator
MCF5480
255 MIPS
166 MHz
Two 10/100 Ethernet Controllers
Two CAN Controllers
v2.2 PCI Controller
DDR Memory Controller
Temperature Range
-40 to 85 ° C
-40 to 85 ° C
-40 to 85 ° C
-40 to 85 ° C
-40 to 85 ° C
-40 to 85 ° C
MCF548x Family Features
ColdFire V4e core
— Limited superscalar V4 ColdFire processor core
— Up to 200 MHz peak internal core frequency (308 Dhrystone 2.1 MIPS)
— Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
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•
•
•
•
•
•
— Memory management unit (MMU)
– Separate, 32-entry, fully-associative instruction and data translation lookahead buffers
— Floating point unit (FPU)
– Double-precision support that conforms to IEEE-754 standard
– Eight floating point registers
Internal master bus (XLB) arbiter
— High performance split address and data transactions
— Support for various parking modes
32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller
— 66–133 MHz operation
— Supports both DDR and SDR DRAM
— Built-in initialization and refresh
— Up to four chip selects enabling up to 1 GB of external memory
Version 2.2 peripheral component interconnect (PCI) bus
— 32-bit target and initiator operation
— Support for up to five external PCI masters
— 33–66 MHz operation with PCI bus to XLB divider ratios of 1:1, 1:2, and 1:4
Flexible multi-function external bus (FlexBus)
— Supports operation with the following:
– Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over
PCI bus–PCI not usable)
– Multiplexed 32-bit address and 32-bit data (PCI usable)
– Multiplexed 32-bit address and 16-bit data
– Multiplexed 32-bit address and 8-bit data
— Provides a glueless interface to boot Flash/ROM, SRAM, and peripheral devices
— Up to six chip selects
— 33–66 MHz operation
Communications I/O subsystem
— Intelligent 16-channel DMA controller
— Dedicated DMA channels for receive and transmit on all subsystem peripheral interfaces
— Up to two 10/100 Mbps fast Ethernet controllers (FECs), each with separate 2-Kbyte receive
and transmit FIFOs
— Universal serial bus (USB) version 2.0 device controller
– Support for one control and six programmable endpoints — interrupt, bulk, or isochronous
– 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM
– Integrated physical layer interface
— Up to four programmable serial controllers (PSCs) each with separate 512-byte receive and
transmit FIFOs for UART, USART, modem, codec, and IrDA 1.1 interfaces
— I2C peripheral interface
— Two FlexCAN controller area network 2.0B controllers each with 16 message buffers
— DMA serial peripheral interface (DSPI)
Optional security encryption controller (SEC) module
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MCF548x Family Features
•
•
•
•
•
•
1.4.1
— Execution units for the following:
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random number generator compliant with FIPS 140-1 standards for randomness and
non-determinism
— Dual-channel architecture permits single-pass encryption and authentication
32-Kbyte system SRAM
— Arbitration mechanism shares bandwidth between internal bus masters (CPU, cryptography
accelerator, PCI, and DMA)
System integration unit (SIU)
— Interrupt controller
— Watchdog timer
— Two 32-bit slice timers for periodic alarm and interrupt generation
— Up to four 32-bit general-purpose timers with capture, compare, and PWM capability
— General-purpose I/O ports multiplexed with peripheral pins
Debug and test features
— Core debug support via ColdFire background debug mode (BDM) port
— Chip debug support via JTAG/ IEEE 1149.1 test access port
PLL and clock generator
— 30–66.67 MHz input frequency range
Operating Voltages
— 1.5V internal logic
— 2.5V DDR SDRAM bus I/O (1.25V VREF)
— 3.3V PCI, FlexBus, and all other I/O
Estimated power consumption
— <1.5W
ColdFire V4e Core Overview
The ColdFire V4e core is a variable-length RISC, clock-multiplied core that includes a Harvard memory
architecture, branch cache acceleration logic, and limited superscalar dual-instruction issue capabilities.
The limited superscalar design approaches dual-issue performance with the cost of a scalar execution
pipeline.
The ColdFire V4e processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The four-stage instruction fetch pipeline (IFP) prefetches the instruction stream,
examines it to predict changes of flow, partially decodes instructions, and packages fetched data into
instructions for the operand execution pipeline (OEP). The IFP can prefetch instructions before the OEP
needs them, minimizing the wait for instructions. The instruction buffer is a 10 instruction, first-in-first-out
(FIFO) buffer that decouples the IFP and OEP by holding prefetched instructions awaiting execution in
the OEP. The OEP includes five pipeline stages: the first stage decodes instructions and selects operands
(DS), and the second stage generates operand addresses (OAG). The third and fourth stages fetch operands
(OC1 and OC2), and the fifth stage executes instructions (EX).
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The ColdFire V4e processor contains a double-precision floating point unit (FPU). The FPU conforms to
the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE)
Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754). The FPU operates on 64-bit,
double-precision floating point data and supports single-precision and signed integer input operands. The
FPU programming model is like that in the MC68060 microprocessor. The FPU is intended to accelerate
the performance of certain classes of embedded applications, especially those requiring high-speed
floating point arithmetic computations.
The ColdFire V4e processor also incorporates the ColdFire memory management unit (MMU), which
provides virtual-to-physical address translation and memory access control. The MMU consists of
memory-mapped control, status, and fault registers that provide access to translation lookaside buffers
(TLBs). Software can control address translation and access attributes of a virtual address by configuring
MMU control registers and loading TLBs. With software support, the MMU provides demand-paged,
virtual addressing.
The ColdFire V4e core implements the ColdFire instruction set architecture revision B with support for
floating Point instructions. Additionally, the ColdFire V4e core includes the enhanced
multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a
4-stage execution pipeline, optimized for 32 x 32-bit operations, with support for four 48-bit accumulators.
Supported operands include 16- and 32-bit signed and unsigned integers, as well as signed fractional
operands and a complete set of instructions to process these data types. The EMAC provides superb
support for execution of DSP operations within the context of a single processor at a minimal hardware
cost.
Refer to Chapter 3, “ColdFire Core,” for detailed information on the ColdFire V4e core architecture.
1.4.2
Debug Module (BDM)
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators.
The MCF548x debug module provides support in three different areas:
• Real-time trace support: The ability to determine the dynamic execution path through an
application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel
output bus that reports processor execution status and data to an external BDM emulator system.
• Background debug mode (BDM): Provides low-level debugging in the ColdFire processor
complex. In BDM, the processor complex is halted and a variety of commands can be sent to the
processor to access memory and registers. The external BDM emulator uses a three-pin, serial,
full-duplex channel.
• Real-time debug support: BDM requires the processor to be halted, which many real-time
embedded applications cannot permit. Debug interrupts let real-time systems execute a unique
service routine that can quickly save key register and variable contents and return the system to
normal operation without halting. External development systems can access saved data, because
the hardware supports concurrent operation of the processor and BDM-initiated commands. In
addition, the option is provided to allow interrupts to occur.
1.4.3
JTAG
The MCF548x family supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting
of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit
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MCF548x Family Features
boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. Test logic, implemented using static logic design, is independent of the device system
logic. The MCF548x implementation can do the following:
• Perform boundary scan operations to test circuit board electrical continuity
• Sample MCF548x system pins during operation and transparently shift out the result in the
boundary scan register
• Bypass the MCF548x for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
1.4.4
1.4.4.1
On-Chip Memories
Caches
There are two independent caches associated with the ColdFire V4e core complex: a 32-Kbyte instruction
cache and a 32-Kbyte data cache. Caches improve system performance by providing single-cycle access
to the instruction and data pipelines. This decouples processor performance from system memory
performance, increasing bus availability for on-chip DMA or external devices.
1.4.4.2
System SRAM
The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 32-Kbyte address boundary within
the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the
system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing
commands from the debug module.
The SRAM module is also accessible by multiple non-core bus masters, such as the DMA controller, the
encryption accelerator, and the PCI Controller.
1.4.5
PLL and Chip Clocking Options
MCF548x products contain an on-chip PLL capable of accepting input frequencies from 30–66.66 MHz.
Table 1-2 contains the frequencies of the system buses for the members of the MCF548x family under
various core/SDRAM/PCI/Flexbus clocking options.
Table 1-2. MCF548x Family Clocking Options
Core
(MHz)
Internal XLB, SDRAM
Bus, and PSTCLK
Frequency (MHz)
CLKIN—PCI and FlexBus
Frequency (MHz)
Clock Ratio
120.0–200
60.0–100
30.0–50.0
1:2
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1-7
1.4.6
1.4.6.1
Communications I/O Subsystem
DMA Controller
The communications subsystem contains an intelligent DMA unit that provides front line interrupt control
and data movement interface via a separate peripheral bus to the on-chip peripheral functions, leaving the
processor core free to handle higher level activities. This concurrent operation enables a significant boost
in overall system performance.
The communications subsystem can support up to 16 simultaneously enabled DMA tasks, with support for
up to two external DMA requests. It uses internal buffers to prefetch reads and post writes such that
bursting is used whenever possible. This optimizes both internal and external bus activity. The following
communications and computer control peripheral functions are integrated and controlled by the
communications subsystem:
• Up to two 10/100 Mbps fast Ethernet controllers (FECs)
• Optional universal serial bus (USB) version 2.0 device controller
• Up to four programmable serial controllers (PSCs)
• I2C peripheral interface
• DMA serial peripheral interface (DSPI)
• Two FlexCAN controller area network 2.0B controllers
1.4.6.2
10/100 Fast Ethernet Controller (FEC)
The FEC supports two standard MAC/PHY interfaces: 10/100 Mbps IEEE 802.3 MII and 10Mbps 7-wire
interface. The controller is full duplex, supports a programmable maximum frame length and
retransmission from the transmit FIFO following a collision.
Support for different Ethernet physical interfaces:
— 100 Mbps IEEE 802.3 MII
— 10 Mbps IEEE 802.3 MII
— 10 Mbps 7-wire interface
• IEEE 802.3 full-duplex flow control.
• Support for full-duplex operation (200 Mbps throughput) with a minimum system clock frequency
of 50 MHz.
• Support for half duplex operation (100 Mbps throughput) with a minimum system clock frequency
of 25 MHz.
• Retransmit from transmit FIFO following collision.
• Internal loopback for diagnostic purposes.
1.4.6.3
USB 2.0 Device (Universal Serial Bus)
The USB module implementation on the MCF548x product family provides all the logic necessary to
process the USB protocol as defined by version 2.0 specification for peripheral devices. It features the
following:
• High-speed operation up to 480 Mbps, full-speed operation at 12 Mbps, and low-speed operation
at 1.5 Mbps
• Physical interface on chip
• Bulk, interrupt, and isochronous transport modes.
• Six programmable in/out endpoints and one control endpoint
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MCF548x Family Features
•
4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM
1.4.6.4
Programmable Serial Controllers (PSCs)
The MCF548x product family supports four PSCs that can be independently configured to operate in the
following modes:
• Universal asynchronous receiver transmitter (UART) mode
— 5,6,7,8 bits of data plus parity
— Odd, even, none, or force parity
— Stop bit width programmable in 1/16 bit increments
— Parity, framing, and overrun error detection
— Automatic PSCCTS and PSCRTS modem control signals
• IrDA 1.0 SIR mode (SIR)
— Baud rate range of 2400–115200 bps
— Selectable pulse width: either 3/16 of the bit duration or 1.6 µs
• IrDA 1.1 MIR mode (MIR)
— Baud rate of 0.576 or 1.152 Mbps
• IrDA 1.1 FIR mode (FIR)
— Baud rate of 4.0 Mbps
• 8-bit soft modem mode (modem8)
• 16-bit soft modem mode (modem16)
• AC97 soft modem mode (AC97)
Each PSC supports synchronous (USART) and asynchronous (UART) protocols. The PSCs can be used to
interface to external full-function modems or external codecs for soft modem support, as well as IrDA 1.1
or 1.0 interfaces. Both 8- and 16-bit data widths are supported. PSCs can be configured to support a
1200-baud plain old telephone system (POTS) modem, V.34 or V.90 protocols. The standard UART
interface supports connection to an external terminal/computer for debug support.
1.4.6.5
I2C (Inter-Integrated Circuit)
The MCF548x product family provides an I2C two-wire, bidirectional serial bus for on-board
communication. It features the following:
• Multimaster operation with arbitration and collision detection
• Calling address recognition and interrupt generation
• Automatic switching from master to slave on arbitration loss
• Software-selectable acknowledge bit
• Start and stop signal generation and detection
• Bus busy status detection
1.4.6.6
DMA Serial Peripheral Interface (DSPI)
The DSPI block operates as a basic SPI block with FIFOs providing support for external queue operation.
Data to be transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed
by host software or by the system DMA controller. The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and slave mode—two peripheral chip selects in master mode
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1-9
•
DMA support
1.4.6.7
Controller Area Network (CAN)
The FlexCAN modules are communication controllers implementing the CAN protocol. The CAN
protocol can be used as an industrial control serial data bus, meeting the specific requirements of real-time
processing and reliable operation in a harsh EMI environment, while maintaining cost-effectiveness. Each
of the two CAN controllers on the MCF548x family products contains sixteen message buffers. The CAN
controllers can be configured to either function as an interface with two separate CAN networks, or as a
single 32 message buffer CAN network.
1.4.7
DDR SDRAM Memory Controller
The DDR SDRAM memory controller is a glueless interface to DDR memories. The module uses a 32-bit
memory port and can address a maximum of 1 Gbyte of data with 16 64M x 8 (512-Mbit) devices, four
per chip select. The controller supplies two clock lines and respective inverted clock lines to help minimize
system complexity when using DDR. The module supports either DDR or SDR, but not both. This is due
to voltage differences between the memory technologies.
The supported memory clock rate is up to 133 MHz. At this memory clock rate, DDR memory can receive
data at an effective rate of up to 266 MHz.
• Support for up to 13 lines of row address, 11 lines of column address, two lines of bank address,
and up to four chip selects
• Memory bus width fixed at 32 bits
• Four chip selects support up to 1 GByte of SDRAM memory
• Support for page mode to maximize the data rate. Page mode remembers active pages for all four
chip selects
• Support for sleep mode and self refresh
• Cache line reads that can use critical word first. These reads can start in the center of a burst and
will wrap to the beginning. This allows the processor quicker access to a needed instruction.
All on-chip bus masters have access to DRAM. This includes PCI, the ColdFire V4e core, the
cryptography accelerator, and the DMA controller.
1.4.8
Peripheral Component Interconnect (PCI)
The PCI controller is a PCI V2.2-compliant bus controller and arbiter. The PCI bus is capable of 66-MHz
operation with a 32-bit address/data bus and support for five external masters.
The PCI module includes an inbound FIFO to increase performance when using an external bus master.
The bus can address all 4 Gbytes of PCI-addressable space.
The PCI bus is also multiplexed with the flexible local bus (FlexBus) address lines. If 32-bit non-muxed
local address and data is required, it can be obtained at the expense of utilizing the PCI bus.
When implemented, the PCI controller acts as the central resource, bus arbiter, and configuring master on
the PCI bus.
1.4.9
Flexible Local Bus (FlexBus)
The FlexBus module is intended to provide the user with basic functionality required to interface to
peripheral devices. The FlexBus interface is a multiplexed or non-multiplexed bus, with an operating
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Freescale Semiconductor
MCF548x Family Features
frequency from 33–66 MHz. The Flexbus is targeted to support external Flash memories, boot ROMs,
gate-array logic, or other simple target interfaces. Up to six chip selects are supported by the FlexBus.
Possible combinations of address and data bits are the following:
• Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over
PCI bus–PCI not usable)
• Multiplexed 32-bit address and 32-bit data (PCI usable)
• Multiplexed 32-bit address and 16-bit data
• Multiplexed 32-bit address and 8-bit data
The non-multiplexed 32-bit address and 32-bit data mode is determined at chip reset. For all other modes,
the full 32-bit address is driven during the address phase. The number of bytes used for data are determined
on a chip select by chip select basis.
1.4.10
Security Encryption Controller (SEC)
As consumers and businesses continue to embrace the Internet, the need for secure point-to-point
communications across what is an entirely insecure network has been met by the development of a range
of standard protocols. Computer cryptography fundamentally involves calculations with very large
numbers. Personal computers have sufficient processing power to implement these algorithms entirely in
software. When placed upon the embedded devices typically used for routing and remote access functions,
this same computational burden can potentially decrease the throughput of a 100 Mbps Ethernet interface
down to 10 Mbps.
Hardware acceleration of common cryptography algorithms is the solution to the computational bandwidth
requirements of Internet security standards. Discrete solutions currently address this problem, but the next
logical step is to integrate a cryptography accelerator on an embedded processor, such as the MCF548x
family.
Freescale has developed the SEC on the MCF548x family for this purpose. This block accelerates the core
cryptography algorithms that underlie standard Internet security protocols like SSL/TLS, IPSec, IKE, and
WTLS/WAP.
• The SEC includes execution units for the following:
— DES/3DES block cipher
— AES block cipher
— RC4 stream cipher
— MD5/SHA-1/SHA-256/HMAC hashing
— Random number generator compliant with FIPS 140-1 standards for randomness and
non-determinism
• Dual-channel architecture permits single-pass encryption and authentication
1.4.11
1.4.11.1
System Integration Unit (SIU)
Timers
The MCF548x family integrates several timer functions required by most embedded systems. Two internal
32-bit slice timers create short cycle periodic interrupts, typically utilized for RTOS scheduling and alarm
functionality. A watchdog timer resets the processor if not regularly serviced, catching software hang-ups.
Four 32-bit general purpose timers can perform input capture, output compare, and PWM functionality.
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1-11
1.4.11.2
Interrupt Controller
The interrupt controller on the MCF548x family can support up to 63 interrupt sources. The interrupt
controller is organized as seven levels with nine interrupt sources per level. Each interrupt source has a
unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7]
and priority within the level.
• Support for up to 63 interrupt sources organized as follows:
— 56 fully-programmable interrupt sources
— 7 fixed-level interrupt sources
• Seven external interrupt signals
• Unique vector number for each interrupt source
• Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
• Support for hardware and software interrupt acknowledge (IACK) cycles
• Combinatorial path to provide wake-up from stop mode
1.4.11.3
General Purpose I/O
All peripheral I/O pins on the MCF548x family are multiplexed with GPIO, adding flexibility and usability
to all signals on the chip.
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Chapter 2
Signal Descriptions
2.1
Introduction
This chapter describes the MCF548x signals.
NOTE
The terms ‘assertion’ and ‘negation’ are used to avoid confusion when
dealing with a mixture of active-low and active-high signals. The term
‘asserted’ indicates that a signal is active, independent of the voltage level.
The term ‘negated’ indicates that a signal is inactive.
Active-low signals, such as RAS and TA, are indicated with an overbar.
2.1.1
Block Diagram
Figure 2-1 displays the signals of the MCF548x.
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Freescale Semiconductor
2-1
FlexBus
AD[31:24]
AD[23:16]
AD15:8]
AD[7:0]
FBCS[5:1] / PFBCS[5:1]
FBCS0
ALE / PFBCTL0 / TBST
R/W / PFBCTL2 / TBST
BE/BWE3 / PFBCTL7 / TSIZ1
BE/BWE2 / PFBCTL6 / TSIZ0
BE/BWE1 / PFBCTL5 / FBADDR1
BE/BWE0 / PFBCTL4 / FBADDR0
OE / PFBCTL3
TA / PFBCTL1
SDRAM
Controller
SDDATA[31:24]
SDDATA[23:16]
SDDATA[15:8]
SDDATA[7:0]
SDADDR[12:0]
SDBA[1:0]
RAS
CAS
SDCS[3:0]
SDDM[3:0]
SDDQS[3:0]
SDCLK[1:0]
SDCLK[1:0]
SDWE
SDCKE
SDRDQS
VREF
PCI
Controller
PSCs
DSPI
PCIAD[31:24] / FBADDR[31:24]
PCIAD[23:16] / FBADDR[23:16]
PCIAD[15:8] / FBADDR[15:8]
PCIAD[7:0] / FBADDR[7:0]
PCICXBE[3:0]
PCIDEVSEL
PCIFRM
PCIIDSEL
PCIIRDY
PCIPAR
PCIPERR
PCIRESET
PCISERR
PCISTOP
PCITRDY
PCIBG4 / PPCIBG4 / TBST
PCIBG[3:0] / PPCIBG[3:0] / TOUT[3:0]
PCIBR4 / PPCIBR4 / IRQ4
PCIBR[3:0] / PPCIBR[3:0] / TIN[3:0]
MCF548x
PCS0TXD / PPSCL0
PSC0RXD / PPSCL1
PSC0CTS / PPSCL2 / PSC0BCLK
PSC0RTS / PPSCL3 / PSC0FSYNC
PSC1TXD / PPSCL4
PSC1RXD / PPSCL5
PSC1CTS / PPSCL6 / PSC1BCLK
PSC1RTS / PPSCL7 / PSC1FSYNC
PSC2TXD / PPSCH0
PSC2RXD / PPSCH1
PSC2CTS / PPSCH2 / PSC2BCLK / CANRX0
PSC2RTS / PPSCH3 / PSC2FSYNC / CANTX0
PSC3TXD / PPSCH4
PSC3RXD / PPSCH5
PSC3CTS / PPSCH6 / PSC3BCLK
PSC3RTS / PPSCH7 / PSC3FSYNC
DSPISOUT / PDSPI0 / PSC3TXD
DSPISIN / PDSPI1 / PSC3RXD
DSPISCK / PDSPI2 / PSC3CTS / PSC3BCLK
DSPICS5/PCSS / PDSPI6
DSPICS3 / PDSPI5 / TOUT3 / CANTX1
DSPICS2 / PDSPI4 / TOUT2 / CANTX1
DSPICS0/SS / PDSPI3 / PSC3RTS / PSC3FSYNC
E0MDIO / PFECI2C3
E0MDC / PFECI2C2
E0TXCLK / PFEC0H7
E0TXEN / PFEC0H6
E0TXD0 / PFEC0H5
E0COL / PFEC0H4
E0RXCLK / PFEC0H3
E0RXDV / PFEC0H2
E0RXD0 / PFEC0H1
E0CRS / PFEC0H0
E0TXD[3:1] / PFEC0L[7:5]
E0TXER / PFEC0L4
E0RXD[3:1] / PFEC0L[3:1]
E0RXER / PFEC0L0
Ethernet
MAC 0
E1MDIO / SDA / CANRX0
E1MDC / SCL / CANTX0
E1TXCLK / PFEC1H7
E1TXEN / PFEC1H6
E1TXD0 / PFEC1H5
E1COL / PFEC1H4
E1RXCLK / PFEC1H3
E1RXDV / PFEC1H2
E1RXD0 / PFEC1H1
E1CRS / PFEC1H0
E1TXD[3:1] / PFEC1L[7:5]
E1TXER / PFEC1L4
E1RXD[3:1] / PFEC1L[3:1]
E1RXER / PFEC1L0
Ethernet
MAC 1
USBD+
USBD–
USBVBUS
USBRBIAS
USBCLKIN
USBCLKOUT
USB
SDA / PFECI2C1
SCL / PFECI2C0
I2C
IRQ7 / PIRQ7
IRQ[6:5] / PIRQ[6:5] / CANRX1
External
Interrupts
Port
DREQ1 / PDMA1 / TIN1 / IRQ1
DREQ0 / PDMA0 / TIN0
DACK[1:0] / PDMA[3:2] / TOUT[1:0]
DMA
Controller
TIN3 / PTIM7 / IRQ3 / CANRX1
TOUT3 / PTIM6 / CANTX1
TIN2 / PTIM5 / IRQ2 / CANRX1
TOUT2 / PTIM4 / CANTX1
TIN1
TOUT1
TIN0
TOUT0
Timer
Module
PSTCLK
PSTDDATA[7:0]
DSCLK / TRST
BKPT / TMS
DSI / TDI
DSO / TDO
TCK
Debug &
JTAG
Test Port
Control
MTMOD[3:0]
RSTI
RSTO
CLKIN
Test /
Reset &
Clock
EVDD
IVDD
VSS
SDVDD
PLLVDD
PLLVSS
USB_OSCVDD
USB_PHYVDD
USB_OSCAVDD
USB_PLLVDD
USBVDD
Power
Supplies
Figure 2-1. MCF548x Signals
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Introduction
Table 2-1 lists the signals for the MCF548x in functional group order.
Drive
Reset
State
Pin Functions
Pull-up
Table 2-1. MCF548x Signal Description
AE2, AF3, AF1,
AE3, AE4, AD5,
AF2, AD4
AD[31:24]
—
—
—
Multiplexed
address/data bus
I/O
16
Hi-Z
AD3, AC3, AD2,
AC2, AA4, AE1,
AC1, AD1
AD[23:16]
—
—
—
Multiplexed
address/data bus
I/O
16
Hi-Z
AB2, AA3, W4,
AB1, AA2, AA1,
Y1, Y2
AD[15:8]
—
—
—
Multiplexed
address/data bus
I/O
16
Hi-Z
W3, W1, W2, V3,
V1, V2, T4, U3
AD[7:0]
—
—
—
Multiplexed
address/data bus
I/O
16
Hi-Z
R1, T2, T3, T1, U2
FBCS[5:1]
PFBCS[5:1]
—
—
Chip selects 5–1
O:I/O
24
High
U1
FBCS0
—
—
—
Chip select 0
O
24
High
AD6
ALE
PFBCTL0
TBST
—
16
High
AE5
R/W
PFBCTL2
TBST
—
Read/write
O:I/O
16
Hi-Z
AF4
BE/BWE3
PFBCTL7
TSIZ1
—
Byte enables
O:I/O
16
High
AF5
BE/BWE2
PFBCTL6
TSIZ0
—
Byte enables
O:I/O
16
High
AC4
BE/BWE1
PFBCTL5
FBADDR1
—
Byte enables
O:I/O
16
High
AE7
BE/BWE0
PFBCTL4
FBADDR0
—
Byte enables
O:I/O
16
High
AE6
OE
PFBCTL3
—
—
Output enable
O:I/O
16
High
AF6
TA
PFBCTL1
—
—
Transfer acknowledge
I:I/O
16
—
PBGA Pin
Primary
GPIO
Secondary
Description
I/O
Tertiary
FlexBus
Address Latch Enable O:I/O
SDRAM Controller
C10, B9, A8, D5,
A6, C8, B7, A5
SDDATA[31:24]
—
—
—
SDRAM data bus
I/O
24
Hi-Z
A4, C7, B6, B4,
C5, B3, C4, D4
SDDATA[23:16]
—
—
—
SDRAM data bus
I/O
24
Hi-Z
E2, D1, G4, E1,
K4, F1, G2, H3
SDDATA[15:8]
—
—
—
SDRAM data bus
I/O
24
Hi-Z
N4, G1, H2, J3,
J1, M4, K3, K2
SDDATA[7:0]
—
—
—
SDRAM data bus
I/O
24
Hi-Z
A13, A12, D10,
B12, C12, A11,
D8, B11, C11,
A10, D7, B10, A9
SDADDR[12:0]
—
—
—
SDRAM address bus
O
24
Low
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-3
Description
I/O
Drive
Reset
State
Pin Functions
Pull-up
Table 2-1. MCF548x Signal Description (Continued)
—
SDRAM bank
addresses
O
24
Low
—
—
SDRAM row address
strobe
O
24
High
—
—
—
SDRAM column
address strobe
O
24
High
SDCS[3:0]
—
—
—
SDRAM chip selects
O
24
High
B8, A3, G3, J2
SDDM[3:0]
—
—
—
SDRAM write data
byte mask
O
24
High
A7, B5, F2, H1
SDDQS[3:0]
—
—
—
SDRAM data strobe
I/O
24
High
L1, N1
SDCLK[1:0]
—
—
—
SDRAM clock
O
24
Low
M1, N2
SDCLK[1:0]
—
—
—
Inverted SDRAM
clock
O
24
Low
K1
SDWE
—
—
—
SDRAM write enable
O
24
Low
E4
SDCKE
—
—
—
SDRAM clock enable
O
24
Low
L2
SDRDQS
—
—
—
SDR SDRAM data
strobe
O
24
Low
D2
VREF
—
—
—
SDRAM reference
voltage
I
—
—
PBGA Pin
Primary
GPIO
Secondary
Tertiary
M2, M3
SDBA[1:0]
—
—
E3
RAS
—
C2
CAS
R2, P2, P1, N3
PCI Controller
V25, V26, U25,
U26, T24, T25,
T26, R24
PCIAD[31:24]
—
FBADDR[31:24]
—
PCI address/data bus
I/O
16
Hi-Z
R25, R26, P26,
P24, P23, P25,
N25, N23
PCIAD[23:16]
—
FBADDR[23:16]
—
PCI address/data bus
I/O
16
Hi-Z
N26, N24, M26,
M25, L26, L25,
K26, K25
PCIAD[15:8]
—
FBADDR[15:8]
—
PCI address/data bus
I/O
16
Hi-Z
J26, K24, J25,
H26, J24, G26,
H25, K23
PCIAD[7:0]
—
FBADDR[7:0]
—
PCI address/data bus
I/O
16
Hi-Z
F26, G25, E26,
G24
PCICXBE[3:0]
—
—
—
PCI command/byte
enables
I/O
16
Hi-Z
J23
PCIDEVSEL
—
—
—
PCI device select
I/O
16
Hi-Z
F25
PCIFRM
—
—
—
PCI frame
I/O
16
Hi-Z
C23
PCIIDSEL
—
—
—
PCI initialization
device select
I
—
—
MCF548x Reference Manual, Rev. 3
2-4
Freescale Semiconductor
Introduction
Description
I/O
Drive
Reset
State
Pin Functions
Pull-up
Table 2-1. MCF548x Signal Description (Continued)
—
PCI initiator ready
I/O
16
Hi-Z
—
—
PCI parity
I/O
16
Hi-Z
—
—
—
PCI parity error
I/O
16
Hi-Z
PCIRESET
—
—
—
PCI reset
O
16
Low
F24
PCISERR
—
—
—
PCI system error
I/O
16
Hi-Z
E25
PCISTOP
—
—
—
PCI stop
I/O
16
Hi-Z
C26
PCITRDY
—
—
—
PCI target ready
I/O
16
Hi-Z
W24
PCIBG4
PPCIBG4
TBST
—
PCI external grant 4
O:I/O
16
GPI
Y26, W25, V24,
W26
PCIBG[3:0]
PPCIBG[3:0]
TOUT[3:0]
—
PCI external grant 3–0 O:I/O
16
GPI
D21
PCIBR4
PPCIBR4
IRQ4
—
PCI external
request 4
I:I/O
Y1
8
GPI
B24
PCIBR3
PPCIBR3
TIN3
—
PCI external
request 3
I:I/O
Y1
8
GPI
A25, B23, A24
PCIBR[2:0]
PPCIBR[2:0]
TIN[2:0]
—
PCI external
request 2–0
I:I/O
8
GPI
PBGA Pin
Primary
GPIO
Secondary
Tertiary
D24
PCIIRDY
—
—
F23
PCIPAR
—
D26
PCIPERR
G23
External Interrupts Port
D14
IRQ7
PIRQ7
—
—
External interrupt
request 7
I:I/O
—
—
B14, A14
IRQ[6:5]
PIRQ[6:5]
CANRX1
—
External interrupt
request 6–5
I:I/O
—
—
I/O
8
GPI
8
GPI
I:I/O
8
GPI
MAC transmit enable O:I/O
8
GPI
Ethernet MAC 0
AF10
E0MDIO
PFECI2C3
—
—
Management channel
serial data
AD11
E0MDC
PFECI2C2
—
—
Management channel O:I/O
clock
AF9
E0TXCLK
PFEC0H7
—
—
AE10
E0TXEN
PFEC0H6
—
—
AD9
E0TXD0
PFEC0H5
—
—
MAC transmit data
O:I/O
8
GPI
AC9
E0COL
PFEC0H4
—
—
MAC collision
I:I/O
8
GPI
AD14
E0RXCLK
PFEC0H3
—
—
MAC receive clock
I:I/O
8
GPI
AE14
E0RXDV
PFEC0H2
—
—
MAC receive enable
I:I/O
8
GPI
AD13
E0RXD0
PFEC0H1
—
—
MAC receive data
I:I/O
8
GPI
AE19
E0CRS
PFEC0H0
—
—
MAC carrier sense
I:I/O
8
GPI
MAC transmit clock
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-5
Description
I/O
Drive
Reset
State
Pin Functions
Pull-up
Table 2-1. MCF548x Signal Description (Continued)
—
MAC transmit data
O:I/O
8
GPI
—
—
MAC transmit error
O:I/O
8
GPI
PFEC0L[3:1]
—
—
MAC receive data
I:I/O
8
GPI
PFEC0L0
—
—
MAC receive error
I:I/O
8
GPI
I/O
Y1
8
—
Y1
8
—
I:I/O
Y1
8
GPI
MAC Transmit enable O:I/O
Y1
8
GPI
O:I/O
Y1
8
GPI
8
GPI
PBGA Pin
Primary
GPIO
Secondary
Tertiary
AD8, AC6, AF7
E0TXD[3:1]
PFEC0L[7:5]
—
AE9
E0TXER
PFEC0L4
AF11, AF12,
AF13
E0RXD[3:1]
AC14
E0RXER
Ethernet MAC 1
AE252
E1MDIO
—
SDA
CANRX0
Management channel
serial data
AD242
E1MDC
—
SCL
CANTX0
Management channel O:I/O
clock
AE132
E1TXCLK
PFEC1H7
—
—
AD252
E1TXEN
PFEC1H6
—
—
AE122
E1TXD0
PFEC1H5
—
—
MAC Transmit clock
MAC Transmit data
AF82
E1COL
PFEC1H4
—
—
MAC Collision
I:I/O
Y1
B222
E1RXCLK
PFEC1H3
—
—
MAC Receive clock
I:I/O
Y1
8
GPI
8
GPI
B252
E1RXDV
PFEC1H2
—
—
MAC Receive enable
I:I/O
Y1
AF242
E1RXD0
PFEC1H1
—
—
MAC Receive data
I:I/O
Y1
8
GPI
8
GPI
AC52
E1CRS
PFEC1H0
—
—
MAC Carrier sense
I:I/O
Y1
AC82, AC112,
AE112
E1TXD[3:1]
PFEC1L[7:5]
—
—
MAC Transmit data
O:I/O
Y1
8
GPI
AE242
E1TXER
PFEC1L4
—
—
MAC Transmit error
O:I/O
Y1
8
GPI
8
GPI
8
GPI
D252,
B262,
AE82
A262
E1RXD[3:1]
PFEC1L[3:1]
—
—
MAC Receive data
I:I/O
Y1
E1RXER
PFEC1L0
—
—
MAC Receive error
I:I/O
Y1
USB
AF163
USBD+
—
—
—
USB differential data
I/O
24
—
AF173
USBD-
—
—
—
USB differential data
I/O
24
—
AC173
USBVBUS
—
—
—
USB Vbus monitor
input
I
—
—
AF18
USBRBIAS
—
—
—
USB bias resistor
I
—
—
AF153
USBCLKIN
—
—
—
USB crystal input
I
—
—
USBCLKOUT
—
—
—
USB crystal output
O
24
—
—
QSPI data out
O:I/O
24
GPI
3
AF14
DSPI
Y24
DSPISOUT
PDSPI0
PSC3TXD
MCF548x Reference Manual, Rev. 3
2-6
Freescale Semiconductor
Introduction
Description
I/O
Drive
Reset
State
Pin Functions
Pull-up
Table 2-1. MCF548x Signal Description (Continued)
—
QSPI data in
I:I/O
24
GPI
PSC3CTS
PSC3BCLK
QSPI clock
I/O
24
GPI
PDSPI6
—
—
QSPI chip select
O:I/O
24
GPI
DSPICS3
PDSPI5
TOUT3
CANTX1
QSPI chip select
O:I/O
24
GPI
AA26
DSPICS2
PDSPI4
TOUT2
CANTX1
QSPI chip select
O:I/O
24
GPI
Y25
DSPICS0/SS
PDSPI3
PSC3RTS
PSC3FSYNC
QSPI chip select
O:I/O
24
GPI
PBGA Pin
Primary
GPIO
Secondary
Tertiary
AC24
DSPISIN
PDSPI1
PSC3RXD
AD22
DSPISCK
PDSPI2
W23
DSPICS5/PCSS
V23
I2C
C24
SDA
PFECI2C1
—
—
I2C Serial data
I/O
8
GPI
C25
SCL
PFECI2C0
—
—
I2C Serial clock
I/O
8
GPI
PSCs
AA25
PSC0TXD
PPSC1PSC00
—
—
PSC0 transmit data
O:I/O
8
GPI
AC21
PSC0RXD
PPSC1PSC01
—
—
PSC0 receive data
I:I/O
8
GPI
AE23
PSC0CTS
PPSC1PSC03
PSC0BCLK
—
PSC0 clear to send
I:I/O
8
GPI
AB26
PSC0RTS
PPSC1PSC02
PSC0FSYNC
—
PSC0 request to send
I/O
8
GPI
AB25
PSC1TXD
PPSC1PSC04
—
—
PSC1 transmit data
O:I/O
8
GPI
AE22
PSC1RXD
PPSC1PSC05
—
—
PSC1 receive data
I:I/O
8
GPI
AF25
PSC1CTS
PPSC1PSC07
PSC1BCLK
—
PSC1 clear to send
I:I/O
8
GPI
Y23
PSC1RTS
PPSC1PSC06
PSC1FSYNC
—
PSC1 request to send
I/O
8
GPI
AC26
PSC2TXD
PPSC3PSC20
—
—
PSC2 transmit data
O:I/O
8
GPI
AD21
PSC2RXD
PPSC3PSC21
—
—
PSC2 receive data
I:I/O
8
GPI
AC19
PSC2CTS
PPSC3PSC23
PSC2BCLK
CANRX0
PSC2 clear to send
I:I/O
8
GPI
AD26
PSC2RTS
PPSC3PSC22
PSC2FSYNC
CANTX0
PSC2 request to send
I/O
8
GPI
AE26
PSC3TXD
PPSC3PSC24
—
—
PSC3 transmit data
O:I/O
8
GPI
AE21
PSC3RXD
PPSC3PSC25
—
—
PSC3 receive data
I:I/O
8
GPI
AF23
PSC3CTS
PPSC3PSC27
PSC3BCLK
—
PSC3 clear to send
I:I/O
8
GPI
AB23
PSC3RTS
PPSC3PSC26
PSC3FSYNC
—
PSC3 request to send
I/O
8
GPI
DMA Controller
AF19
DREQ1
PDMA1
TIN1
IRQ1
DMA request
I:I/O
8
GPI
AF20
DREQ0
PDMA0
TIN0
—
DMA request
I:I/O
8
GPI
AC25, AB24
DACK[1:0]
PDMA[3:2]
TOUT[1:0]
—
DMA acknowledge
O:I/O
8
GPI
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-7
Drive
Reset
State
Pin Functions
Pull-up
Table 2-1. MCF548x Signal Description (Continued)
AD19
TIN3
PTIM7
IRQ3
CANRX1
Timer input
I:I/O
8
GPI
AD23
TOUT3
PTIM6
CANTX1
—
Timer output
O:I/O
8
GPI
AF21
TIN2
PTIM5
IRQ2
CANRX1
Timer input
I:I/O
8
GPI
AC22
TOUT2
PTIM4
CANTX1
—
Timer output
O:I/O
8
GPI
AE20
TIN1
—
—
—
Timer input
I
8
GPI
AC23
TOUT1
—
—
—
Timer output
O
8
GPI
AF22
TIN0
—
—
—
Timer input
I
8
GPI
AF26
TOUT0
—
—
—
Timer output
O
8
GPI
PBGA Pin
Primary
GPIO
Secondary
Description
I/O
Tertiary
Timer Module
Debug and JTAG Test Port Control
D20
PSTCLK
—
—
—
Processor clock
output
O
8
High
A23, B21, D18,
C20, A22, B20,
A21, B19
PSTDDATA[7:0]
—
—
—
Processor status
debug data
O
8
High
C15
DSCLK
—
TRST
—
Debug clock / TAP
reset
I
Y
—
—
B15
BKPT
—
TMS
—
Breakpoint/TAP test
mode select
I
Y
—
—
A15
DSI
—
TDI
—
Debug data in / TAP
data in
I
Y
—
—
D17
DSO
—
TDO
—
Debug data out / TAP
data out
O
8
High
A16
TCK
—
—
—
TAP clock
I
—
—
Test, Reset, and Clock
B17, C14, A18,
B16
MTMOD[3:0]
—
—
—
Test mode pins
I
—
—
B13
RSTI
—
—
—
Reset input
I
—
—
A20
RSTO
—
—
—
Reset output
O
8
Low
A17
CLKIN
—
—
—
Clock input
I
—
—
D15
NC
—
—
—
No Connect
I
—
—
AC15
NC
—
—
—
No Connect
I
—
—
MCF548x Reference Manual, Rev. 3
2-8
Freescale Semiconductor
Introduction
Drive
Reset
State
Pin Functions
Pull-up
Table 2-1. MCF548x Signal Description (Continued)
C16, C22, E24,
H24, M24, R3,
U24, Y3, AA24,
AB3, AD7, AD10,
AD18
EVDD
—
—
—
Positive I/O supply
I
—
—
C18, D11, D12,
D19, D22, H4,
H23, L23, P4,
R23, V4, AA23,
AC12, AC20
IVDD
—
—
—
Positive core supply
I
—
—
A2, B2, C3, C17,
C19, C21, D6, D9,
D13, D16, D23,
E23, F4, J4, L4,
L11, L12, L13,
L14, L15, L16,
L24, M11, M12,
M13, M14, M15,
M16, M23, N11,
N12, N13, N14,
N15, N16, P11,
P12, P13, P14,
P15, P16, R4,
R11, R12, R13,
R14, R15, R16,
T11, T12, T13,
T14, T15, T16,
T23, U4, U23, Y4,
AB4, AC7, AC10,
AC18, AD12,
AD17, AD20,
AE15, AE16,
AE17
VSS
—
—
A1, B1, C1, C6,
C9, C13, D3, F3,
L3, P3
SDVDD
—
—
—
Positive SDRAM
supply
A19
PLLVDD
—
—
—
Positive PLL analog
supply
B18
PLLVSS
—
—
—
PLL ground
AC134
USB_OSCVDD
—
—
—
USB oscillator supply
AC164
USB_PHYVDD
—
—
—
USB PHY supply
AD154
USB_OSCAVDD
—
—
—
USB oscillator analog
supply
PBGA Pin
Primary
GPIO
Secondary
Description
I/O
Tertiary
Power Supplies
Ground
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-9
AD164
AE18
I/O
GPIO
Secondary
Tertiary
USB_PLLVDD
—
—
—
USB PLL supply
USBVDD
—
—
—
USB supply
4
Reset
State
Description
Primary
Drive
Pin Functions
PBGA Pin
Pull-up
Table 2-1. MCF548x Signal Description (Continued)
1
Pull-up resistor when configured for general purpose input (default state after reset).
This pin is a “no connect” on the MCF5483 and MCF5482 devices.
3
This pin is a “no connect” on the MCF5481 and MCF5480 devices.
4
This pin is a “no connect” on the MCF5481 and MCF5480 devices. On MCF5485, MCF5484, MCF5483, and MCF5482 device the pin
should be connected to the appriopriate power rail even is USB is not being used.
2
Table 2-2 lists the MCF548x signals in pin number order for the 388 PBGA package.
Pin Functions
Primary
GPIO
Secondary
Tertiary
A1
SDVDD
—
—
—
A2
VSS
—
—
A3
SDDM2
—
A4
SDDATA23
A5
PBGA Pin
PBGA Pin
Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number
Pin Functions
Primary
GPIO
Secondary
Tertiary
P1
SDCS1
—
—
—
—
P2
SDCS2
—
—
—
—
—
P3
SDVDD
—
—
—
—
—
—
P4
IVDD
—
—
—
SDDATA24
—
—
—
P11
VSS
—
—
—
A6
SDDATA27
—
—
—
P12
VSS
—
—
—
A7
SDDQS3
—
—
—
P13
VSS
—
—
—
A8
SDDATA29
—
—
—
P14
VSS
—
—
—
A9
SDADDR0
—
—
—
P15
VSS
—
—
—
A10
SDADDR3
—
—
—
P16
VSS
—
—
—
A11
SDADDR7
—
—
—
P23
PCIAD19
—
FBADDR19
—
A12
SDADDR11
—
—
—
P24
PCIAD20
—
FBADDR20
—
A13
SDADDR12
—
—
—
P25
PCIAD18
—
FBADDR18
—
A14
IRQ5
PIRQ5
CANRX1
—
P26
PCIAD21
—
FBADDR21
—
A15
DSI
—
TDI
—
R1
FBCS5
PFBCS5
—
—
A16
TCK
—
—
—
R2
SDCS3
—
—
—
A17
CLKIN
—
—
—
R3
EVDD
—
—
—
A18
MTMOD1
—
—
—
R4
VSS
—
—
—
A19
PLLVDD
—
—
—
R11
VSS
—
—
—
A20
RSTO
—
—
—
R12
VSS
—
—
—
MCF548x Reference Manual, Rev. 3
2-10
Freescale Semiconductor
Introduction
Pin Functions
Primary
GPIO
Secondary
Tertiary
A21
PSTDDATA1
—
—
—
A22
PSTDDATA3
—
—
A23
PSTDDATA7
—
A24
PCIBR0
A25
PBGA Pin
PBGA Pin
Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)
Pin Functions
Primary
GPIO
Secondary
Tertiary
R13
VSS
—
—
—
—
R14
VSS
—
—
—
—
—
R15
VSS
—
—
—
PPCIBR0
TIN0
—
R16
VSS
—
—
—
PCIBR2
PPCIBR2
TIN2
—
R23
IVDD
—
—
—
A261
E1RXD1
PFEC1L5
—
—
R24
PCIAD24
—
FBADDR24
—
B1
SDVDD
—
—
—
R25
PCIAD23
—
FBADDR23
—
B2
VSS
—
—
—
R26
PCIAD22
—
FBADDR22
—
B3
SDDATA18
—
—
—
T1
FBCS2
PFBCS2
—
—
B4
SDDATA20
—
—
—
T2
FBCS4
PFBCS4
—
—
B5
SDDQS2
—
—
—
T3
FBCS3
PFBCS3
—
—
B6
SDDATA21
—
—
—
T4
AD1
—
—
—
B7
SDDATA25
—
—
—
T11
VSS
—
—
—
B8
SDDM3
—
—
—
T12
VSS
—
—
—
B9
SDDATA30
—
—
—
T13
VSS
—
—
—
B10
SDADDR1
—
—
—
T14
VSS
—
—
—
B11
SDADDR5
—
—
—
T15
VSS
—
—
—
B12
SDADDR9
—
—
—
T16
VSS
—
—
—
B13
RSTI
—
—
—
T23
VSS
—
—
—
B14
IRQ6
PIRQ6
CANRX1
—
T24
PCIAD27
—
FBADDR27
—
B15
BKPT
—
TMS
—
T25
PCIAD26
—
FBADDR26
—
B16
MTMOD0
—
—
—
T26
PCIAD25
—
FBADDR25
—
B17
MTMOD3
—
—
—
U1
FBCS0
—
—
—
B18
PLLVSS
—
—
—
U2
FBCS1
PFBCS1
—
—
B19
PSTDDATA0
—
—
—
U3
AD0
—
—
—
B20
PSTDDATA2
—
—
—
U4
VSS
—
—
—
B21
PSTDDATA6
—
—
—
U23
VSS
—
—
—
B221
E1RXCLK
PFEC1H3
—
—
U24
EVDD
—
—
—
B23
PCIBR1
PPCIBR1
TIN1
—
U25
PCIAD29
—
FBADDR29
—
B24
PCIBR3
PPCIBR3
TIN3
—
U26
PCIAD28
—
FBADDR28
—
B251
E1RXDV
PFEC1H2
—
—
V1
AD3
—
—
—
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-11
Pin Functions
Primary
GPIO
Secondary
Tertiary
B261
E1RXD2
PFEC1L2
—
—
C1
SDVDD
—
—
C2
CAS
—
C3
VSS
C4
PBGA Pin
PBGA Pin
Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)
Pin Functions
Primary
GPIO
Secondary
Tertiary
V2
AD2
—
—
—
—
V3
AD4
—
—
—
—
—
V4
IVDD
—
—
—
—
—
—
V23
DSPICS3
PDSPI5
TOUT3
CANTX1
SDDATA17
—
—
—
V24
PCIBG1
PPCIBG1
TOUT1
—
C5
SDDATA19
—
—
—
V25
PCIAD31
—
FBADDR31
—
C6
SDVDD
—
—
—
V26
PCIAD30
—
FBADDR30
—
C7
SDDATA22
—
—
—
W1
AD6
—
—
—
C8
SDDATA26
—
—
—
W2
AD5
—
—
—
C9
SDVDD
—
—
—
W3
AD7
—
—
—
C10
SDDATA31
—
—
—
W4
AD13
—
—
—
C11
SDADDR4
—
—
—
W23
DSPICS5/PCSS
PDSPI6
—
—
C12
SDADDR8
—
—
—
W24
PCIBG4
PPCIBG4
TBST
—
C13
SDVDD
—
—
—
W25
PCIBG2
PPCIBG2
TOUT2
—
C14
MTMOD2
—
—
—
W26
PCIBG0
PPCIBG0
TOUT0
—
C15
DSCLK
—
TRST
—
Y1
AD9
—
—
—
C16
EVDD
—
—
—
Y2
AD8
—
—
—
C17
VSS
—
—
—
Y3
EVDD
—
—
—
C18
IVDD
—
—
—
Y4
VSS
—
—
—
C19
VSS
—
—
—
Y23
PSC1RTS
C20
PSTDDATA4
—
—
—
Y24
DSPISOUT
PDSPI0
PSC3TXD
—
C21
VSS
—
—
—
Y25
DSPICS0/SS
PDSPI3
—
—
C22
EVDD
—
—
—
Y26
PCIBG3
PPCIBG3
TOUT3
—
C23
PCIIDSEL
—
—
—
AA1
AD10
—
—
—
C24
SDA
PFECI2C1
—
—
AA2
AD11
—
—
—
C25
SCL
PFECI2C0
—
—
AA3
AD14
—
—
—
C26
PCITRDY
—
—
—
AA4
AD19
—
—
—
D1
SDDATA14
—
—
—
AA23
IVDD
—
—
—
D2
VREF
—
—
—
AA24
EVDD
—
—
—
D3
SDVDD
—
—
—
AA25
PCS0TXD
PPSC1PSC00
—
—
D4
SDDATA16
—
—
—
AA26
DSPICS2
PDSPI4
TOUT2
CANTX1
PPSC1PSC06 PSC1FSYNC
—
MCF548x Reference Manual, Rev. 3
2-12
Freescale Semiconductor
Introduction
Pin Functions
Primary
GPIO
Secondary
Tertiary
D5
SDDATA28
—
—
—
D6
VSS
—
—
D7
SDADDR2
—
D8
SDADDR6
D9
PBGA Pin
PBGA Pin
Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)
Pin Functions
Primary
GPIO
Secondary
Tertiary
AB1
AD12
—
—
—
—
AB2
AD15
—
—
—
—
—
AB3
EVDD
—
—
—
—
—
—
AB4
VSS
—
—
—
VSS
—
—
—
AB23
PSC3RTS
D10
SDADDR10
—
—
—
AB24
DACK0
PDMA2
TOUT0
—
D11
IVDD
—
—
—
AB25
PSC1TXD
PPSC1PSC04
—
—
D12
IVDD
—
—
—
AB26
PSC0RTS
PPSC1PSC02 PSC0FSYNC
D13
VSS
—
—
—
AC1
AD17
—
—
—
D14
IRQ7
PIRQ7
—
—
AC2
AD20
—
—
—
D15
NC
—
—
—
AC3
AD22
—
—
—
D16
VSS
—
—
—
AC4
BE/BWE1
PFBCTL5
FBADDR1
—
E1CRS
PFEC1H0
—
—
PPSC3PSC26 PSC3FSYNC
—
—
D17
DSO
—
TDO
—
AC51
D18
PSTDDATA5
—
—
—
AC6
E0TXD2
PFEC0L6
—
—
D19
IVDD
—
—
—
AC7
VSS
—
—
—
D20
PSTCLK
—
—
—
AC81
E1TXD3
PFEC1L7
—
—
D21
PCIBR4
PPCIBR4
IRQ4
—
AC9
E0COL
PFEC0H4
—
—
D22
IVDD
—
—
—
AC10
VSS
—
—
—
E1TXD2
PFEC1L6
—
—
D23
VSS
—
—
—
AC111
D24
PCIIRDY
—
—
—
AC12
IVDD
—
—
—
USB_OSCVDD
—
—
—
D251
E1RXD3
PFEC1L3
—
—
AC132
D26
PCIPERR
—
—
—
AC14
E0RXER
PFEC0L0
—
—
E1
SDDATA12
—
—
—
AC15
NC
—
—
—
E2
SDDATA15
—
—
—
AC162
USB_PHYVDD
—
—
—
USBVBUS
—
—
—
E3
RAS
—
—
—
AC172
E4
SDCKE
—
—
—
AC18
VSS
—
—
—
E23
VSS
—
—
—
AC19
PSC2CTS
PPSC3PSC23
PSC2BCLK
CANRX0
E24
EVDD
—
—
—
AC20
IVDD
—
—
—
E25
PCISTOP
—
—
—
AC21
PSC0RXD
PPSC1PSC01
—
—
E26
PCICXBE1
—
—
—
AC22
TOUT2
PTIM4
CANTX1
—
F1
SDDATA10
—
—
—
AC23
TOUT1
—
—
—
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-13
Pin Functions
Primary
GPIO
Secondary
Tertiary
F2
SDDQS1
—
—
—
F3
SDVDD
—
—
F4
VSS
—
F23
PCIPAR
F24
PBGA Pin
PBGA Pin
Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)
Pin Functions
Primary
GPIO
Secondary
Tertiary
AC24
DSPISIN
PDSPI1
PSC3RXD
—
—
AC25
DACK1
PDMA3
TOUT1
—
—
—
AC26
PSC2TXD
PPSC3PSC20
—
—
—
—
—
AD1
AD16
—
—
—
PCISERR
—
—
—
AD2
AD21
—
—
—
F25
PCIFRM
—
—
—
AD3
AD23
—
—
—
F26
PCICXBE3
—
—
—
AD4
AD24
—
—
—
G1
SDDATA6
—
—
—
AD5
AD26
—
—
—
G2
SDDATA9
—
—
—
AD6
ALE
PFBCTL0
TBST
—
G3
SDDM1
—
—
—
AD7
EVDD
—
—
—
G4
SDDATA13
—
—
—
AD8
E0TXD3
PFEC0L7
—
—
G23
PCIRESET
—
—
—
AD9
E0TXD0
PFEC0H5
—
—
G24
PCICXBE0
—
—
—
AD10
EVDD
—
—
—
G25
PCICXBE2
—
—
—
AD11
E0MDC
PFECI2C2
—
—
G26
PCIAD2
—
FBADDR2
—
AD12
VSS
—
—
—
H1
SDDQS0
—
—
—
AD13
E0RXD0
PFEC0H1
—
—
H2
SDDATA5
—
—
—
AD14
E0RXLK
PFEC0H3
—
—
H3
SDDATA8
—
—
—
AD152 USB_OSCAVDD
—
—
—
USB_PLLVDD
—
—
—
H4
IVDD
—
—
—
AD162
H23
IVDD
—
—
—
AD17
VSS
—
—
—
H24
EVDD
—
—
—
AD18
EVDD
—
—
—
H25
PCIAD1
—
FBADDR1
—
AD19
TIN3
PTIM7
IRQ3
CANRX1
H26
PCIAD4
—
FBADDR4
—
AD20
VSS
—
—
—
J1
SDDATA3
—
—
—
AD21
PSC2RXD
PPSC3PSC21
—
—
J2
SDDM0
—
—
—
AD22
DSPISCK
PDSPI2
PSC3CTS
PSC3BCLK
J3
SDDATA4
—
—
—
AD23
TOUT3
PTIM6
CANTX1
—
E1MDC
—
SCL
CANTX0
PFEC1H6
—
—
J4
VSS
—
—
—
AD241
J23
PCIDEVSEL
—
—
—
AD251
E1TXEN
J24
PCIAD3
—
FBADDR3
—
AD26
PSC2RTS
J25
PCIAD5
—
FBADDR5
—
AE1
AD18
—
—
—
J26
PCIAD7
—
FBADDR7
—
AE2
AD31
—
—
—
PPSC3PSC22 PSC2FSYNC
CANTX0
MCF548x Reference Manual, Rev. 3
2-14
Freescale Semiconductor
Introduction
Pin Functions
Primary
GPIO
Secondary
Tertiary
K1
SDWE
—
—
—
K2
SDDATA0
—
—
K3
SDDATA1
—
K4
SDDATA11
K23
PBGA Pin
PBGA Pin
Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)
Pin Functions
Primary
GPIO
Secondary
Tertiary
AE3
AD28
—
—
—
—
AE4
AD27
—
—
—
—
—
AE5
R/W
PFBCTL2
TBST
—
—
—
—
AE6
OE
PFBCTL3
—
—
PCIAD0
—
FBADDR0
—
AE7
BE/BWE0
PFBCTL4
FBADDR0
—
K24
PCIAD6
—
FBADDR6
—
AE81
E1RXER
PFEC1L0
—
—
K25
PCIAD8
—
FBADDR8
—
AE9
E0TXER
PFEC0L4
—
—
K26
PCIAD9
—
FBADDR9
—
AE10
E0TXEN
PFEC0H6
—
—
E1TXD1
PFEC1L5
—
—
L1
SDCLK1
—
—
—
AE111
L2
SDRDQS
—
—
—
AE121
E1TXD0
PFEC1h5
—
—
E1TXCLK
PFEC1H7
—
—
L3
SDVDD
—
—
—
AE131
L4
VSS
—
—
—
AE14
E0RXDV
PFEC1H2
—
—
L11
VSS
—
—
—
AE15
VSS
—
—
—
L12
VSS
—
—
—
AE16
VSS
—
—
—
L13
VSS
—
—
—
AE17
VSS
—
—
—
L14
VSS
—
—
—
AE182
USBVDD
—
—
—
L15
VSS
—
—
—
AE19
E0CRS
PFEC0H0
—
—
L16
VSS
—
—
—
AE20
TIN1
—
—
—
L23
IVDD
—
—
—
AE21
PSC3RXD
PPSC3PSC25
—
—
L24
VSS
—
—
—
AE22
PSC1RXD
PPSC1PSC05
—
—
L25
PCIAD10
—
FBADDR10
—
AE23
PSC0CTS
PPSC1PSC03
PSC0BCLK
—
L26
PCIAD11
—
FBADDR11
—
AE241
E1TXER
PFEC1L4
—
—
E1MDIO
—
SCL
CANTX0
M1
SDCLK1
—
—
—
AE251
M2
SDBA1
—
—
—
AE26
PSC3TXD
PPSC3PSC24
—
—
M3
SDBA0
—
—
—
AF1
AD29
—
—
—
M4
SDDATA2
—
—
—
AF2
AD25
—
—
—
M11
VSS
—
—
—
AF3
AD30
—
—
—
M12
VSS
—
—
—
AF4
BE/BWE3
PFBCTL7
TSIZ1
—
M13
VSS
—
—
—
AF5
BE/BWE2
PFBCTL6
TSIZ0
—
M14
VSS
—
—
—
AF6
TA
PFBCTL1
—
—
M15
VSS
—
—
—
AF7
E0TXD1
PFEC0L5
—
—
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-15
PBGA Pin
PBGA Pin
Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)
Pin Functions
Primary
GPIO
Secondary
Tertiary
M16
VSS
—
—
—
M23
VSS
—
—
M24
EVDD
—
M25
PCIAD12
M26
N1
Pin Functions
Primary
GPIO
Secondary
Tertiary
AF81
E1COL
PFEC1H4
—
—
—
AF9
E0TXCLK
PFEC0H7
—
—
—
—
AF10
E0MDIO
PFECI2C3
—
—
—
FBADDR12
—
AF11
E0RXD3
PFEC0L3
—
—
PCIAD13
—
FBADDR13
—
AF12
E0RXD2
PFEC0L2
—
—
SDCLK0
—
—
—
AF13
E0RXD1
PFEC0L1
—
—
3
N2
SDCLK0
—
—
—
AF14
USBCLKOUT
—
—
—
N3
SDCS0
—
—
—
AF153
USBCLKIN
—
—
—
USBD+
—
—
—
N4
SDDATA7
—
—
—
AF163
N11
VSS
—
—
—
AF173
USBD-
—
—
—
N12
VSS
—
—
—
AF18
USBRBIAS
—
—
—
N13
VSS
—
—
—
AF19
DREQ1
PDMA1
TIN1
IRQ1
N14
VSS
—
—
—
AF20
DREQ0
PDMA0
TIN0
—
N15
VSS
—
—
—
AF21
TIN2
PTIM5
IRQ2
CANRX1
N16
VSS
—
—
—
AF22
TIN0
—
—
—
N23
PCIAD16
—
FBADDR16
—
AF23
PSC3CTS
PPSC3PSC27
PSC3BCLK
—
E1RXD0
PFEC1H1
—
—
N24
PCIAD14
—
FBADDR14
—
AF241
N25
PCIAD17
—
FBADDR17
—
AF25
PSC1CTS
PPSC1PSC07
PSC1BCLK
—
N26
PCIAD15
—
FBADDR15
—
AF26
TOUT0
—
—
—
1
This pin is a “no connect” on the MCF5483 and MCF5482 devices.
This pin is a “no connect” on the MCF5481 and MCF5480 devices. On MCF5485, MCF5484, MCF5483, and MCF5482 device the pin
should be connected to the appriopriate power rail even is USB is not being used.
3 This pin is a “no connect” on the MCF5481 and MCF5480 devices.
2
2.2
2.2.1
2.2.1.1
MCF548x External Signals
FlexBus Signals
Address/Data Bus (AD[31:0])
The AD[31:0] bus carries address and data. The full 32-bit address is always driven on the first clock of a
bus cycle (address phase). The number of bytes used for data during the data phase is determined by the
port size associated with the matching chip select.
MCF548x Reference Manual, Rev. 3
2-16
Freescale Semiconductor
MCF548x External Signals
2.2.1.2
Chip Select (FBCS[5:0])
FBCS[5:0] are asserted to indicate which device is being selected. A particular chip select asserts when
the transfer address is within the device’s address space as defined in the base and mask address registers.
Each chip select can be programmed for a base address location, masking addresses, port size,
burst-capability indication, wait-state generation, and internal/external termination.
Reset clears all chip select programming; FBCS0 is the only chip select initialized out of reset. FBCS0 is
also unique because it can function at reset as a global chip select that allows boot ROM to be selected at
any defined address space. Port size and termination (internal vs. external) for boot FBCS0 are configured
by the levels on AD[2:0] on the rising edge of RSTI, as described in Section 2.2.6, “Reset Configuration
Pins.”
2.2.1.3
Address Latch Enable (ALE)
The assertion of ALE indicates that the MCF548x has begun a bus transaction and that the address and
attributes are valid. ALE is asserted for one bus clock cycle. In multiplexed bus mode, ALE is used
externally as an address latch enable to capture the address phase of the bus transfer.
2.2.1.4
Read/Write (R/W)
The MCF548x drives the R/W signal to indicate the direction of the current bus operation. It is driven high
during read bus cycles and driven low during write bus cycles.
2.2.1.5
Transfer Burst (TBST)
Transfer burst indicates that a burst transfer is in progress. A burst transfer can be 2 to 16 beats depending
on the size of the transfer and the port size.
2.2.1.6
Transfer Size (TSIZ[1:0])
For memory accesses, these signals along with TBST, indicate the data transfer size of the current bus
operation. The FlexBus interface supports byte, word, and longword operand transfers and allows accesses
to 8-, 16-, and 32-bit data ports.
For misaligned transfers, TSIZ[1:0] indicates the size of each transfer. For example, if a longword access
through a 32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first (TSIZ[1:0] =
01), a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is transferred at offset 0x4
(TSIZ[1:0] = 01).
For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows:
• If bursting is used, TSIZ[1:0] is driven to the size of transfer.
• If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port
size.
Table 2-3. Data Transfer Size
TSIZ[1:0]
Transfer Size
00
4 bytes (longword)
01
1 byte
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-17
Table 2-3. Data Transfer Size (Continued)
TSIZ[1:0]
Transfer Size
10
2 bytes (word)
11
16 bytes (line)
For burst-inhibited transfers, TSIZ[1:0] changes with each ALE assertion to reflect the next transfer size.
For transfers to port sizes smaller than the transfer size, TSIZ[1:0] indicates the size of the entire transfer
on the first access and the size of the current port transfer on subsequent transfers. For example, for a
longword write to an 8-bit port, TSIZ[1:0] = 2’b00 for the first transaction and 2’b01 for the next three
transactions. If bursting is used and in the case of longword write to an 8-bit port, TSIZ[1:0] is driven to
2’b00 for the entire transfer.
2.2.1.7
Byte Selects (BE/BWE[3:0])
The four byte-enables are multiplexed with the byte-write-enable signals. Each pin can be individually
programmed through the chip select control registers (CSCRs). For each chip select, assertion of
byte-enables for reads and byte-write enables for write cycles can be programmed. Alternatively, users can
program byte-write enables to assert on writes and byte-enable to not assert on reads.
The byte strobe (BE/BWE[3:0]) outputs indicate that data is to be latched or driven onto a byte of the data.
BE/BWE[3:0] signals are asserted only to the memory bytes used during a read or write access.
2.2.1.8
Output Enable (OE)
The output enable signal is sent to the interfacing memory and/or peripheral to enable a read transfer. OE
is asserted only when a chip select matches the current address decode.
2.2.1.9
Transfer Acknowledge (TA)
The external system drives this input to terminate the bus transfer. For write cycles, the processor continues
to drive data at least one clock after FBCSx is negated. During read cycles, the peripheral must continue
to drive data until TA is recognized. The number of wait states is determined either by an internally
programmed auto acknowledgement or the external TA input. If the external TA is used, the peripheral has
total control over the number of wait states.
2.2.2
SDRAM Controller Signals
These signals are used for SDRAM accesses.
2.2.2.1
SDRAM Data Bus (SDDATA[31:0])
SDDATA[31:0] is the bidirectional, non-multiplexed data bus used for SDRAM accesses. Data is sampled
by the MCF548x on the rising edge of SDCLK when in SDR mode, and on both the rising and falling edge
of SDCLK when in DDR mode.
2.2.2.2
SDRAM Address Bus (SDADDR[12:0])
The SDADDR[12:0] signals are the 13-bit address bus used for multiplexed row and column addresses
during SDRAM bus cycles. The address multiplexing supports up to 256 Mbits of SDRAM per chip select.
MCF548x Reference Manual, Rev. 3
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Freescale Semiconductor
MCF548x External Signals
2.2.2.3
SDRAM Bank Addresses (SDBA[1:0])
Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank.
It is also used to select the SDRAM internal mode register during power-up initialization.
2.2.2.4
SDRAM Row Address Strobe (RAS)
This output is the SDRAM synchronous row address strobe.
2.2.2.5
SDRAM Column Address Strobe (CAS)
This output is the SDRAM synchronous column address strobe.
2.2.2.6
SDRAM Chip Selects (SDCS[3:0])
These signals interface to the chip select lines of the SDRAMs within a memory block. Thus, there is one
SDCS line for each memory block (the MCF548x supports up to four SDRAM memory blocks).
2.2.2.7
SDRAM Write Data Byte Mask (SDDM[3:0])
These output signals are sampled by the SDRAM on both edges of SDDQS to determine which byte lanes
of the SDRAM data bus should be latched during a write cycle. In DDR mode, these bits are ignored during
read operations.
2.2.2.8
SDRAM Data Strobe (SDDQS[3:0])
These bidirectional signals indicate when valid data is on the SDRAM data bus when in DDR mode.
2.2.2.9
SDRAM Clock (SDCLK[1:0])
These signals are the output clock for SDRAM cycles.
2.2.2.10
Inverted SDRAM Clock (SDCLK[1:0])
These signals are the inverted version of the SDRAM clock. They are used with SDCLK to provide the
differential clocks for DDR SDRAM.
2.2.2.11
SDRAM Write Enable (SDWE)
The SDRAM write enable (SDWE) is asserted to signify that an SDRAM write cycle is underway. A read
cycle is indicated by the negation of SDWE.
2.2.2.12
SDRAM Clock Enable (SDCKE)
This output is the SDRAM clock enable. SDCKE is negated to put the SDRAM into low-power,
self-refresh mode.
2.2.2.13
SDR SDRAM Data Strobe (SDRDQS)
This signal is connected to SDDQS inputs. It is used in SDR mode only.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-19
2.2.2.14
SDRAM Reference Voltage (VREF)
This is the input reference voltage for differential SSTL_2 inputs. It is used in both DDR and SDR modes.
2.2.3
2.2.3.1
PCI Controller Signals
PCI Address/Data Bus (PCIAD[31:0])
The PCIAD[31:0] lines are a time-multiplexed address data bus. The address is presented on the bus during
the address phase while the data is presented on the bus during one or more data phases.
If the FlexBus is used in 32-bit address or 32-bit data non-multiplexed mode, PCIAD[31:0] are used as a
32-bit address for FlexBus transfers.
2.2.3.2
Command/Byte Enables (PCICXBE[3:0])
The PCICXBE[3:0] lines are time-multiplexed. The PCI command is presented during the address phase,
and the byte enables are presented during the data phase.
2.2.3.3
Device Select (PCIDEVSEL)
The PCIDEVSEL signal is asserted active low when the MCF548x decodes that it is the target of a PCI
transaction from the address presented on the PCI bus during the address phase.
2.2.3.4
Frame (PCIFRM)
The PCIFRM signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is negated
when the initiator is ready to complete the final data phase.
2.2.3.5
Initialization Device Select (PCIIDSEL)
The PCIIDSEL signal is asserted during a PCI type-0 configuration cycle to address the PCI configuration
header.
2.2.3.6
Initiator Ready (PCIIRDY)
The PCIIRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write
operation, assertion indicates that the master is driving valid data on the bus. During a read operation,
assertion indicates that the master is ready to accept data.
2.2.3.7
Parity (PCIPAR)
The PCIPAR signal indicates the parity of data on the PCIAD[31:0] and PCICXBE[3:0] lines.
2.2.3.8
Parity Error (PCIPERR)
The PCIPERR signal is asserted when a data phase parity error is detected if enabled.
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Freescale Semiconductor
MCF548x External Signals
2.2.3.9
Reset (PCIRESET)
The PCIRESET signal is asserted active low by MCF548x to reset the PCI bus. This signal is asserted after
the MCF548x is reset and must be negated to enable usage of the PCI bus.
2.2.3.10
System Error (PCISERR)
The PCISERR signal, if enabled, is asserted when an address phase parity error is detected.
2.2.3.11
Stop (PCISTOP)
The PCISTOP signal is asserted by the currently addressed target to indicate that it wishes to stop the
current transaction.
2.2.3.12
Target Ready (PCITRDY)
The PCITRDY signal is asserted by the currently addressed target to indicate that it is ready to complete
the current data phase.
2.2.3.13
External Bus Grant (PCIBG[4:1])
The PCIBG signal is asserted to an external master to give it control of the PCI bus. If the internal PCI
arbiter is enabled, it asserts one of the PCIBG[4:1] lines to grant ownership of the PCI bus to an external
master. When the PCI arbiter module is disabled, PCIBG[4:1] is driven high and should be ignored.
2.2.3.14
External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
The PCIBG0 signal is asserted to external master device 0 to give it control of the PCI bus. When the PCI
arbiter module is disabled, the signal operates as the PCIREQOUT output. It is asserted when the
MCF548x needs to initiate a PCI transaction.
2.2.3.15
External Bus Request (PCIBR[4:0])
The PCIBR signal is asserted by an external PCI master when it requires access to the PCI bus.
2.2.3.16
External Request/Grant Input (PCIBR0/PCIGNTIN)
The PCIBR0 signal is asserted by external PCI master device 0 when it requires access to the PCI bus.
When the internal PCI arbiter module is disabled, this signal is used as a grant input for the PCI bus,
PCIGNTIN. It is driven by an external PCI arbiter.
2.2.4
Interrupt Control Signals
The interrupt control signals supply the external interrupt level to the MCF548x device.
2.2.4.1
Interrupt Request (IRQ[7:1])
The IRQ[7:1] signals are the external interrupt inputs.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
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2.2.5
Clock and Reset Signals
The clock and reset signals configure the MCF548x and provide interface signals to the external system.
2.2.5.1
Reset In (RSTI)
Asserting RSTI causes the MCF548x to enter reset exception processing. RSTO is asserted automatically
when RSTI is asserted.
2.2.5.2
Reset Out (RSTO)
After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the
PLL regains its lock, RSTO negates again. This signal can be used to reset external devices.
2.2.5.3
Clock In (CLKIN)
CLKIN is the MCF548x input clock frequency to the on-board, phase-locked loop (PLL) clock generator.
CLKIN is used to internally clock or sequence the MCF548x internal bus interface at a selected multiple
of the input frequency used for internal module logic.
CLKIN is used as the clock reference for PCI and FlexBus transfers.
2.2.6
Reset Configuration Pins
This section describes address/data pins, AD[12:0], that are read at reset to configure the MCF548x.
2.2.6.1
AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0])
The clock configuration inputs, CLKCONFIG[4:0], indicate the CLKIN to SDCLK ratio. CLKIN is used
as the external reference for both PCI and FlexBus cycles. The CLKIN to SDCLK ratio is selectable, where
SDCLK is the clock frequency used for SDRAM accesses and the internal XLB bus. The core is always
clocked at twice the SDCLK frequency.
These signals are sampled on the rising edge of RSTI. Table 2-4 shows how the logic levels of AD[12:8]
correspond to the selected clock ratio.
Table 2-4. MCF548x Divide Ratio Encodings
CLKIN—PCI and FlexBus
FB_AD[12:8]1 Clock Ratio
Frequency Range
(MHz)
1
Internal XLB, SDRAM
Bus, and PSTCLK
Frequency Range
(MHz)
Core Frequency Range
(MHz)
00011
1:2
41.6–50.0
83.33–100
166.66–200
00101
1:2
30.0–44.4
60.0–88.8
120.0–177.66
All other values of FB_AD[12:8] are reserved.
Figure 2-2 correlates CLKIN, internal bus, and core clock frequenciesi for the 1x–4x multipliers.
MCF548x Reference Manual, Rev. 3
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Freescale Semiconductor
MCF548x External Signals
CLKIN
Internal Clock
Core Clock
2x
2x
25.0
50.0
50.0
100.0
100.0
200.0
2x
4x
25.0
100.0
200.0
25 40 50 60 70
30 40 50 60 70 80 90 100
60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
CLKIN (MHz)
Internal Clock (MHz)
Core Clock (MHz)
Figure 2-2. CLKIN, Internal Bus, and Core Clock Ratios
2.2.6.2
AD5—FlexBus Size Configuration (FBSIZE)
At reset, the enabling and disabling of BE/BWE[3:0] versus TSIZ[1:0] and ADDR[1:0] is determined by
the logic level driven on AD5 at the rising edge of RSTI. FBSIZE is multiplexed with AD5 and sampled
only at reset. Table 2-5 shows how the AD5 logic level corresponds to the BE/BWE[3:0] function.
Table 2-5. AD5/FBSIZE Selection of BE/BWE[3:0] Signals
AD5
2.2.6.3
FlexBus Byte Enable Mode
0
BE/BWE[3:0] used as byte/byte write
enables.
1
BE/BWE[3:2] configured as TSIZ[1:0].
BE/BWE[1:0] configured as FBADDR[1:0].
AD4—32-bit FlexBus Configuration (FBMODE)
During reset, the FlexBus can be configured to operate in a non-multiplexed 32-bit address with 32-bit data
mode. In this mode, the 32-bit FlexBus AD[31:0] is used for the data bus, and the PCI bus PCIAD[31:0]
is used as the address bus. The FlexBus operating mode is determined by the logic level driven on AD4 at
the rising edge of RSTI. Table 2-6 shows how the logic level of AD4 corresponds to the FlexBus mode.
Table 2-6. AD4/FBMODE Selection of Non-Multiplexed
32-bit Address/32-bit Data Mode
AD4
1
2.2.6.4
FlexBus Operating Mode
0
AD[31:0] used for data.
PCIAD[31:0] used for address1
1
PCIAD[31:0] used for PCI bus.
AD[31:0] used for both address and data.
If the non-multiplexed 32-bit address/32-bit data mode is selected, the PCI bus
cannot be used.
AD3—Byte Enable Configuration (BECONFIG)
The default byte enable mode of the boot FBCS0 is determined by the logic level driven on AD3 at the
rising edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM]. Table 2-7 shows how
the logic level of AD3 corresponds to the byte enable mode for FBCS0 at reset.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-23
Table 2-7. AD3/BECONFIG, BE/BWE[3:0] Boot Configuration
AD3
2.2.6.5
Boot FBCS0 Byte Strobe Configuration
0
BE[3:0] can assert for both read and write cycles.
1
BWE[3:0] are not asserted for reads;
BWE[3:0] only assert for write cycles
AD2—Auto Acknowledge Configuration (AACONFIG)
At reset, the enabling and disabling of auto acknowledge for boot FBCS0 is determined by the logic level
driven on AD2 at the rising edge of RSTI. AACONFIG is multiplexed with AD2 and sampled only at reset.
The AD2 logic level is reflected as the reset value of CSCR0[AA]. Table 2-8 shows how the AD2 logic
level corresponds to the auto acknowledge timing for FBCS0 at reset. Auto acknowledge can be disabled
by driving a logic 0 on AD2 at reset.
Table 2-8. AD2/AA_CONFIG Selection of FBCS0 Automatic Acknowledge
AD2
2.2.6.6
Boot FBCS0 AA Configuration at Reset
0
Disabled
1
Enabled with 63 wait states
AD[1:0]—Port Size Configuration (PSCONFIG)
The default port size value of the boot FBCS0 is determined by the logic levels driven on AD[1:0] at the
rising edge of RSTI, which are reflected as the reset value of CSCR0[PS]. Table 2-9 shows how the logic
levels of AD[1:0] correspond to the FBCS0 port size at reset.
Table 2-9. AD[1:0]/PSCONFIG[1:0] Selection of FBCS0 Port Size
2.2.7
AD[1:0]
Boot FBCS0 Port Size
00
32-bit port
01
8-bit port
1X
16-bit port
Ethernet Module Signals
The following signals are used by the Ethernet module for data and clock signals.
2.2.7.1
Management Data (E0MDIO, E1MDIO)
The bidirectional EMDIO signals transfer control information between the external PHY and the
media-access controller. Data is synchronous to EMDC and applies to MII mode operation. This signal is
an input after reset. When the FEC operates in 10 Mbps 7-wire interface mode, this signal should be
connected to VSS.
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Freescale Semiconductor
MCF548x External Signals
2.2.7.2
Management Data Clock (E0MDC, E1MDC)
EMDC is an output clock that provides a timing reference to the PHY for data transfers on the EMDIO
signal; it applies to MII mode operation.
2.2.7.3
Transmit Clock (E0TXCLK, E1TXCLK)
This is an input clock that provides a timing reference for ETXEN, ETXD[3:0], and ETXER.
2.2.7.4
Transmit Enable (E0TXEN, E1TXEN)
The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the first ETXCLK following the final
nibble of the frame.
2.2.7.5
Transmit Data 0 (E0TXD0, E1TXD0)
ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is
used for 10 Mbps Ethernet data. This signal is also used for MII mode data in conjunction with ETXD[3:1].
2.2.7.6
Collision (E0COL, E1COL)
The ECOL input is asserted upon detection of a collision and remains asserted while the collision persists.
This signal is not defined for full-duplex mode.
2.2.7.7
Receive Clock (E0RXCLK, E1RXCLK)
The receive clock (ERXCLK) input provides a timing reference for ERXDV, ERXD[3:0], and ERXER.
2.2.7.8
Receive Data Valid (E0RXDV, E1RXDV)
Asserting the receive data valid (ERXDV) input indicates that the PHY has valid nibbles present on the
MII. ERXDV should remain asserted from the first recovered nibble of the frame through to the last nibble.
Assertion of ERXDV must start no later than the SFD and exclude any EOF.
2.2.7.9
Receive Data 0 (E0RXD0, E1RXD0)
ERXD0 is the Ethernet input data transferred from the PHY to the media-access controller when ERXDV
is asserted. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode Ethernet
data in conjunction with ERXD[3:1].
2.2.7.10
Carrier Receive Sense (E0CRS, E1CRS)
ECRS is an input signal that, when asserted, signals that transmit or receive medium is not idle, and applies
to MII mode operation.
2.2.7.11
Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1])
These pins contain the serial output Ethernet data and are valid only during assertion of ETXEN in MII
mode.
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Freescale Semiconductor
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2.2.7.12
Transmit Error (E0TXER, E1TXER)
When the ETXER output is asserted for one or more clock cycles while ETXEN is also asserted, the PHY
sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated, and
applies to MII mode operation.
2.2.7.13
Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1])
These pins contain the Ethernet input data transferred from the PHY to the media-access controller when
ERXDV is asserted in MII mode operation.
2.2.7.14
Receive Error (E0RXER, E1RXER)
ERXER is an input signal that, when asserted along with ERXDV, signals that the PHY has detected an
error in the current frame. When ERXDV is not asserted, ERXER has no effect and applies to MII mode
operation.
2.2.8
2.2.8.1
Universal Serial Bus (USB)
USB Differential Data (USBD+, USBD–)
USBD+ and USBD– are the outputs of the on-chip USB 2.0 transceiver. They provide differential data for
the USB 2.0 bus.
2.2.8.2
USBVBUS
This is the USB cable Vbus monitor input.
2.2.8.3
USBRBIAS
This is the connection for external current setting resistor. It should be connected to a 9.1kΩ +/– 1%
pull-down resistor.
For the MCF5481 and MCF5480 devices this pin should be connected to a 9.1kΩ +/– 20% pull-down
resistor.
2.2.8.4
USBCLKIN
This is the input pin for 12-MHz USB crystal circuit.
2.2.8.5
USBCLKOUT
This is the output pin for 12-MHz USB crystal circuit.
2.2.9
2.2.9.1
DMA Serial Peripheral Interface (DSPI) Signals
DSPI Synchronous Serial Data Output (DSPISOUT)
The DSPISOUT output provides the serial data from the DSPI and can be programmed to be driven on the
rising or falling edge of DSPISCK.
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Freescale Semiconductor
MCF548x External Signals
2.2.9.2
DSPI Synchronous Serial Data Input (DSPISIN)
The DSPISIN input provides the serial data to the DSPI and can be programmed to be sampled on the
rising or falling edge of DSPISCK.
2.2.9.3
DSPI Serial Clock (DSPISCK)
DSPISCK is a serial communication clock signal. In master mode, the DSPI generates the DSPISCK. In
slave mode, DSPISCK is an input from an external bus master.
2.2.9.4
DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)
In master mode, the DSPICS0 signal is a peripheral chip select output that selects which slave device the
current transmission is intended for.
In slave mode, the SS signal is a slave select input signal that allows an SPI master to select the DSPI as
the target for transmission.
2.2.9.5
DSPI Chip Selects (DSPICS[2:3])
The synchronous peripheral chip selects (DSPICS[2:3]) outputs provide DSPI peripheral chip selects that
can be programmed to be active high or low.
2.2.9.6
DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe
(DSPICS5/PCSS)
DSPICS5 is a peripheral chip select output signal. When the DSPI is in master mode and the
DMCR[PCSSE] bit is cleared, this signal is used to select which slave device the current transfer is
intended for.
PCSS provides a strobe signal that can be used with an external demultiplexer for deglitching of the
DSPICSn signals. When the DSPI is in master mode and DMCR[PCSSE] is set, the PCSS provides the
appropriate timing for the decoding of the DSPICS[0,2,3] signals which prevents glitches from occurring.
This signal is not used in slave mode.
2.2.10
2.2.10.1
FlexCAN Signals
FlexCAN Transmit (CANTX0, CANTX1)
Controller area network transmit data output.
2.2.10.2
FlexCAN Receive (CANRX0, CANRX1)
Controller area network receive data input.
2.2.11
I2C I/O Signals
The I2C serial interface module uses the signals in this section.
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Freescale Semiconductor
2-27
2.2.11.1
Serial Clock (SCL)
This bidirectional open-drain signal is the clock signal for the I2C interface. It is either driven by the I2C
module when the bus is in master mode, or it becomes the clock input when the I2C is in slave mode.
2.2.11.2
Serial Data (SDA)
This bidirectional open-drain signal is the data input/output for the I2C interface.
2.2.12
PSC Module Signals
The PSC modules use the signals in this section. The baud rate clock inputs are not supported.
2.2.12.1
Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD)
PSCnTXD are the transmitter serial data outputs for the PSC modules. The output is held high (mark
condition) when the transmitter is disabled, idle, or in the local loopback mode. The PSCxTXD pins can
be programmed to be driven low (break status) by a command.
2.2.12.2
Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD)
PSCnRXD are the receiver serial data inputs for the PSC modules. When the PSC clock is stopped for
power-down mode, any transition on the pins restarts them.
2.2.12.3
Clear-to-Send (PSCnCTS/PSCBCLK)
These signals either operate as the clear-to-send input signals in UART mode or the bit clock input signals
in modem modes and IrDA modes. In MIR and FIR mode, the frequency is a multiple of the input bit clock
frequency, and the bit clock frequency should be within +/-0.1% and +/-0.01% of the ideal one,
respectively.
2.2.12.4
Request-to-Send (PSCnRTS/PSCFSYNC)
The PSCnRTS signals act as transmitter request-to-send (RTS) outputs in UART mode, the frame sync
input in modem8 and modem16 modes, or the RTS output (which acts as frame sync) in AC97 modem
mode.
2.2.13
DMA Controller Module Signals
The DMA controller module uses the signals in the following subsections to provide external requests for
either a source or destination.
2.2.13.1
DMA Request (DREQ[1:0])
These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and
memory by either channel 0 or 1 of the on-chip DMA module.
2.2.13.2
DMA Acknowledge (DACK[1:0])
These outputs are asserted to acknowledge that a DMA request has been recognized.
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MCF548x External Signals
2.2.14
Timer Module Signals
The signals in the following sections are external interfaces to the four general-purpose MCF548x timers.
These 32-bit timers can capture timer values, trigger external events or internal interrupts, or count
external events.
2.2.14.1
Timer Inputs (TIN[3:0])
TINn can be programmed as clocks that cause events in the counter and prescalers. They can also cause
captures on the rising edge, falling edge, or both edges.
2.2.14.2
Timer Outputs (TOUT[3:0])
The programmable timer outputs, TOUTn, pulse or toggle on various timer events.
2.2.15
Debug Support Signals
The MCF548x complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are multiplexed
with background debug pins. Except for TCK, these signals are selected by the value of MTMOD0. If
MTMOD0 is high, JTAG signals are chosen; if it is low, debug module signals are chosen. MTMOD0
should be changed only while RSTI is asserted.
2.2.15.1
Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used as the timing
reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the same frequency as the internal
XLB and SDRAM bus frequency. The frequency is one-half the core frequency.
2.2.15.2
Processor Status Debug Data (PSTDDATA[7:0])
Processor status data outputs indicate both processor status and captured address/data values. They operate
at half the processor’s frequency, using PSTCLK. Given that real-time trace information appears as a
sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may
appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant.
2.2.15.3
Development Serial Clock/Test Reset (DSCLK/TRST)
If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to
the debug module. The maximum DSCLK frequency is 1/5 CLKIN.
If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG controller to the
test logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this
occurs, JTAG logic is benign and does not interfere with normal MCF548x functionality.
Although TRST is asynchronous, Freescale recommends that it makes an asserted-to-negated transition
only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to
a logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to EVDD. Tying TRST
to ground places the JTAG controller in test logic reset state immediately. Tying it to EVDD causes the
JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.
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2.2.15.4
Breakpoint/Test Mode Select (BKPT/TMS)
If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug
mode.
If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test
operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising
edge of TCK determine whether the JTAG controller holds its current state or advances to the next state.
This directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up
resistor so that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be
tied to VDD.
2.2.15.5
Development Serial Input/Test Data Input (DSI/TDI)
If MTMOD0 is low, DSI is selected. DSI provides the single-bit communication for debug module
commands.
If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG
boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG
controller state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge.
TDI has an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it
should be tied to EVDD.
2.2.15.6
Development Serial Output/Test Data Output (DSO/TDO)
If MTMOD0 is low, DSO is selected. DSO provides single-bit communication for debug module
responses.
If MTMOD0 is high, TDO is selected. The TDO output provides the serial data port for outputting data
from JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in
the instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test
data, it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices
having a JTAG port.
2.2.15.7
Test Clock (TCK)
TCK is the dedicated JTAG test logic clock independent of the MCF548x processor clock. Various JTAG
operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period
does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground.
2.2.16
2.2.16.1
Test Signals
Test Mode (MTMOD[3:0])
The test mode signals choose between multiplexed debug module and JTAG signals. If MTMOD0 is low,
the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode. All
other MTMOD values are reserved; MTMOD[3:1] should be tied to ground and MTMOD[3:0] should not
be changed while RSTI is negated
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MCF548x External Signals
2.2.17
Power and Reference Pins
These pins provide system power, ground, and references to the device. Multiple pins are provided for
adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
2.2.17.1
Positive Pad Supply (EVDD)
This pin supplies positive power to the I/O pads.
2.2.17.2
Positive Core Supply (IVDD)
This pin supplies positive power to the core logic.
2.2.17.3
Ground (VSS)
This pin is the negative supply (ground) to the chip.
2.2.17.4
USB Power (USBVDD)
This pin supplies positive power to the USB module’s digital logic.
2.2.17.5
USB Oscillator Power (USB_OSCVDD)
This pin supplies positive power to the USB oscillator’s digital logic.
2.2.17.6
USB PHY Power (USB_PHYVDD)
This pin supplies positive power to the USB PHY’s digital logic.
2.2.17.7
USB Oscillator Analog Power (USB_OSCAVDD)
This pin supplies positive power to the USB oscillator’s analog circuits.
2.2.17.8
USB PLL Analog Power (USB_PLLVDD)
This pin supplies positive power to the USB PLL’s circuits.
2.2.17.9
SDRAM Memory Supply (SDVDD)
This pin supplies positive power to the SDRAM module.
2.2.17.10 PLL Analog Power (PLLVDD)
This pin supplies the positive power for the PLL.
2.2.17.11 PLL Analog Ground (PLLVSS)
This pin is the negative supply (ground) to the PLL.
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Part I
Processor Core
Part I is intended for system designers who need to understand the operation of the MCF548x ColdFire
core and its enhanced multiply/accumulate (EMAC) execution unit. It describes the programming and
exception models, Harvard memory implementation, and debug module.
Contents
Part 1 contains the following chapters:
• Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core of the MCF548x.
The chapter begins with a description of enhancements from the V3 ColdFire core, and then fully
describes the V4e programming model as it is implemented on the MCF548x. It also includes a full
description of exception handling, data formats, an instruction set summary, and a table of
instruction timings.
• Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the MCF548x enhanced
multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and
miscellaneous register instructions. The EMAC is integrated into the operand execution pipeline
(OEP).
• Chapter 5, “Memory Management Unit (MMU),” describes the ColdFire virtual memory
management unit (MMU), which provides virtual-to-physical address translation and memory
access control.
• Chapter 6, “Floating-Point Unit (FPU),” describes instructions implemented in the floating-point
unit (FPU) designed for use with the ColdFire family of microprocessors.
• Chapter 7, “Local Memory,” describes the MCF548x implementation of the ColdFire V4e local
memory specification.
• Chapter 8, “Debug Support,” describes the Revision C enhanced hardware debug support in the
MCF548x. This revision of the ColdFire debug architecture encompasses earlier revisions.
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Chapter 3
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF548x. The CF4e implementation
of the Version 4 (V4) core includes the floating-point unit (FPU), enhanced multiply-accumulate unit
(EMAC), and memory management unit (MMU); all are defined as optional in the V4 architecture. This
chapter also includes a full description of exception handling, data formats, an instruction set summary,
and a table of instruction timings.
3.1
Core Overview
The MCF548x is the first standard product to contain a Version 4e ColdFire microprocessor core. To create
this next-generation, high-performance core, many advanced microarchitectural techniques were
implemented. Most notable are a Harvard memory architecture, branch cache acceleration logic, and
limited superscalar dual-instruction issue capabilities, which together provide 308 (Dhrystone 2.1) MIPS
performance at 200 MHz.
The MCF548x core design emphasizes performance and backward compatibility, and represents the next
step on the ColdFire performance roadmap.
3.2
Features
The CF4e includes the following features defined as optional in the V4 core architecture:
• Floating-point unit (FPU)
• Virtual memory management unit (MMU)
• Enhanced multiply-accumulate unit (EMAC) for increased signal processing functionality plus
backward code compatibility with the MAC unit of previous ColdFire processors
V4 architecture features are defined as follows:
• Variable-length RISC, clock-multiplied core
• Revision B of the ColdFire instruction set architecture (ISA_B), providing new instructions to
improve performance and code density
• Two independent, decoupled pipelines—four-stage instruction fetch pipeline (IFP) and five-stage
operand execution pipeline (OEP) for increased performance
• Ten-instruction, FIFO buffer that decouples the IFP and OEP
• Limited superscalar design approaches dual-issue performance with the cost of a scalar execution
pipeline
• Two-level branch acceleration mechanism with a branch cache, plus a prediction table for
increased performance of conditional Bcc instructions
• 32-bit address bus supporting 4 Gbytes of linear address space
• 32-bit data bus
• 16 user-accessible, 32-bit-wide, general-purpose registers
• Supervisor/user modes for system protection
• Two separate stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack
pointer (USP)—that provide the required isolation between operating modes to support the MMU.
• Vector base register to relocate the exception-vector table
• Optimized for high-level language constructs
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3.2.1
Enhanced Pipelines
The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes
the specified function. The two independent, decoupled pipeline structures maximize performance while
minimizing core size. Pipeline stages are shown in Figure 3-1 and are summarized as follows:
• Four-stage IFP (plus optional instruction buffer stage)
— Instruction address generation (IAG) calculates the next prefetch address.
— Instruction fetch cycle 1 (IC1) initiates prefetch on the processor’s local instruction bus.
— Instruction fetch cycle 2 (IC2) completes prefetch on the processor’s local instruction bus.
— Instruction early decode (IED) generates time-critical decode signals needed for the OEP.
— Instruction buffer (IB) stage uses FIFO queue to minimize effects of fetch latency.
• Five-stage OEP with two optional processor bus write cycles
— Decode stage (DS/secDS) decodes and selects for two sequential instructions.
— Operand address generation (OAG) generates the address for the data operand.
— Operand fetch cycle 1 and 2 (OC1 and OC2) fetch data operands.
— Execute (EX) performs prescribed operations on previously fetched data operands.
— Write data available (DA) makes data available for operand write operations only.
— Store data (ST) updates memory element for operand write operations only.
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Features
Instruction Fetch
Pipeline
IAG
Branch
Cache
Instruction
Memory
IC1
IC2
Branch
Accel. IED
IB
Operand Execution
Pipeline
DS
Internal
Bus
secDS
OAG
Data
(Operand)
Memory
OC1
OC2
Misalignment
Module
EX
DA
Debug
DSCLK DSI
DSO
DDATA
PSTDDATA PSTCLK
Figure 3-1. ColdFire Enhanced Pipeline
3.2.1.1
Instruction Fetch Pipeline (IFP)
Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer, the IFP can
prefetch instructions before the OEP needs them, minimizing stalls.
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3.2.1.1.1
Branch Acceleration
To maximize the performance of conditional branch instructions, the IFP implements a sophisticated
two-level acceleration mechanism. The first level is an 8-entry, direct-mapped branch cache with 2 bits for
indicating four prediction states (strongly or weakly; taken or not-taken) for each entry. The branch cache
also provides the association between instruction addresses and the corresponding target address. In the
event of a branch cache hit, if the branch is predicted as taken, the branch cache sources the target address
from the IC1 stage back into the IAG to redirect the prefetch stream to the new location.
The branch cache implements instruction folding, so conditional branch instructions correctly predicted as
taken can execute in zero cycles. For conditional branches with no information in the branch cache, a
second-level, direct-mapped prediction table is accessed. Each of its 128 entries uses the same 2-bit
prediction mechanism as the branch cache.
If a branch is predicted as taken, branch acceleration logic in the IED stage generates the target address.
Other change-of-flow instructions, including unconditional branches, jumps, and subroutine calls, use a
similar mechanism where the IFP calculates the target address. The performance of subroutine return
instruction (RTS) is improved through the use of a four-entry, LIFO hardware return stack. In all cases,
these mechanisms allow the IFP to redirect the fetch stream down the predicted path well ahead of
instruction execution.
3.2.1.2
Operand Execution Pipeline (OEP)
The two instruction registers in the decode stage (DS) of the OEP are loaded from the FIFO instruction
buffer or are bypassed directly from the instruction early decode (IED). The OEP consists of two
traditional, two-stage RISC compute engines with a dual-ported register file access feeding an arithmetic
logic unit (ALU).
The compute engine at the top of the OEP (the address ALU) is used typically for operand address
calculations; the execution ALU at the bottom is used for instruction execution. The resulting structure
provides 4 Gbytes/S operand bandwidth (at 162 MHz) to the two compute engines and supports
single-cycle execution speeds for most instructions, including all load and store operations and most
embedded-load operations. The V4 OEP supports the ColdFire Revision B instruction set, which adds a
few new instructions to improve performance and code density.
The OEP also implements the following advanced performance features:
• Stalls are minimized by dynamically basing the choice between the address ALU or execution
ALU for instruction execution on the pipeline state.
• The address ALU and register renaming resources together can execute heavily used opcodes and
forward results to subsequent instructions with no pipeline stalls.
• Instruction folding involving MOVE instructions allows two instructions to be issued in one cycle.
The resulting microarchitecture approaches full superscalar performance at a much lower silicon
cost.
3.2.1.2.1
Illegal Opcode Handling
To aid in conversion from M68000 code, every 16-bit operation word is decoded to ensure that each
instruction is valid. If the processor attempts execution of an illegal or unsupported instruction, an illegal
instruction exception (vector 4) is taken.
3.2.1.2.2
Enhanced Multiply/Accumulate (EMAC) Unit
The EMAC unit in the Version 4e provides hardware support for a limited set of digital signal processing
(DSP) operations used in embedded code, while supporting the integer multiply instructions in the
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Features
ColdFire microprocessor family. The MAC features a four-stage execution pipeline, optimized for 32 × 32
multiplies. It is tightly coupled to the OEP, which can issue a 32 x 32 multiply with a 32-bit accumulation
and fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires four
cycles before the next instruction can be issued.
Figure 3-2 shows basic functionality of the EMAC. A full set of instructions are provided for signed and
unsigned integers plus signed, fixed-point fractional input operands.
Operand Y
Operand X
X
Shift 0,1,-1
+/-
Accumulator
Figure 3-2. ColdFire Multiply-Accumulate Functionality Diagram
The EMAC provides functionality in the following three related areas, which are described in detail in
Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC):”
• Signed and unsigned integer multiplies
• Multiply-accumulate operations with signed and unsigned fractional operands
• Miscellaneous register operations
3.2.1.2.3
Memory Management Unit (MMU)
The ColdFire memory management architecture provides a demand-paged, virtual-address environment
with hardware address translation acceleration. It supports supervisor/user, read, write, and execute
permission checking on a per-memory request basis.
The architecture defines the MMU TLB, associated control logic, TLB hit/miss logic, address translation
based on the TLB contents, and access faults due to TLB misses and access violations. It intentionally
leaves some virtual environment details undefined to maximize the software-defined flexibility. These
include the exact structure of the memory-resident pointer descriptor/page descriptor tables, the base
registers for these tables, the exact information stored in the tables, the methodology (if any) for
maintenance of access, and written information on a per-page basis.
3.2.1.2.4
Floating Point Unit (FPU)
The floating-point unit (FPU) provides hardware support for floating point math operations. The FPU
conforms to the American National Standards Institute (ANSI)/Institute of Electrical and Electronics
Engineers (IEEE) Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754).
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The hardware unit is optimized for real-time execution with exceptions disabled and default results
provided for specific operations, operands, and number types. The FPU does not support all IEEE-754
number types and operations in hardware. Exceptions can be enabled to support these cases in software.
3.2.1.2.5
Hardware Divide Unit
The hardware divide unit performs the following integer division operations:
• 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder
• 32-bit operand/32-bit operand producing a 32-bit quotient
• 32-bit operand/32-bit operand producing a 32-bit remainder
3.2.1.3
Harvard Memory Architecture
A Harvard memory architecture supports the increased bandwidth requirements of the CF4e processor
pipelines by providing separate configuration, access control, and protection resources for data (operand)
and instruction memory. The CF4e has separate instruction and data buses to processor-local memories,
eliminating conflicts between instruction fetches and operand accesses.
3.2.2
Debug Module Enhancements
The ColdFire processor core debug interface supports system integration in conjunction with low-cost
development tools. Real-time trace and debug information can be accessed through a standard interface,
which allows the processor and system to be debugged at full speed without costly in-circuit emulators.
The CF4e debug unit is a compatible upgrade to MCF52xx and MCF53xx debug modules with added
support for the CF4e MMU module.
The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based
on feedback from customers and third-party developers, enhancements have been added to succeeding
generations of ColdFire cores. For Revision A, CSR[HRL] is 0. See Section 8.4.2, “Configuration/Status
Register (CSR).”
The Version 3 core implements Revision B of the debug architecture, offering more flexibility for
configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent
BDM processing while hardware breakpoint registers are active. For Revision B, CSR[HRL] is 1.
Revision C of the debug architecture more than doubles the on-chip breakpoint registers and provides an
ability to interrupt debug service routines. For Revision C, CSR[HRL] is 2.
Differences between Revision B and C are summarized as follows:
• Debug Revision B has separate PST[3:0] and DDATA[3:0] signals.
• Debug Revision C adds breakpoint registers and supports normal interrupt request service during
debug. It combines debug signals into PSTDDATA[7:0].
The addition of the memory management unit (MMU) to the baseline architecture requires corresponding
enhancements to the ColdFire debug functionality, resulting in Revision D. For Revision D, the revision
level bit, CSR[HRL], is 3.
With software support, the MMU can provide a demand-paged, virtual address environment. To support
debugging in this virtual environment, the debug enhancements are primarily related to the expansion of
the virtual address to include the 8-bit address space identifier (ASID). Conceptually, the virtual address
is expanded to a 40-bit value: the 8-bit ASID plus the 32-bit address.
The expansion of the virtual address affects the following two major debug functions:
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Programming Model
•
•
The ASID is optionally included in the specification of the hardware breakpoint registers. As an
example, the four PC breakpoint registers are each expanded by 8 bits, so that a specific ASID
value may be programmed as part of the breakpoint instruction address. Likewise, each operand
address/data breakpoint register is expanded to include an ASID value. Finally, new control
registers define if and how the ASID is to be included in the breakpoint comparison trigger logic.
The debug module implements the concept of ownership trace in which the ASID value may be
optionally displayed as part of the real-time trace functionality. When enabled, real-time trace
displays instruction addresses on every change-of-flow instruction that is not absolute or
PC-relative. For Revision D, this instruction address display optionally includes the contents of the
ASID, thus providing the complete instruction virtual address on these instructions.
Additionally when a Sync_PC serial BDM command is loaded from the external development
system, the processor optionally displays the complete virtual instruction address, including the
8-bit ASID value.
In addition to these ASID-related changes, the new MMU control registers are accessible by using serial
BDM commands. The same BDM access capabilities are also provided for the EMAC and FPU
programming models.
Finally, a new serial BDM command is implemented to assist debugging when a software error generates
an incorrect memory address that hangs the external bus. The new BDM command attempts to break this
condition by forcing a bus termination.
3.3
Programming Model
The MCF548x programming model consists of two instruction and register groups—user and supervisor,
shown in Figure 3-3. User mode programs are restricted to user, EMAC, and floating point instructions
and programming models. Supervisor-mode system software can reference all user-mode, EMAC, and
floating point instructions and registers and additional supervisor instructions and control registers. The
user or supervisor programming model is selected based on SR[S]. The following sections describe the
registers in the user, EMAC, floating point, and supervisor programming models.
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31
0
31
Data registers
A0
A1
A2
A3
A4
A5
A6
A7
PC
CCR
Address registers
User Registers
0
63
User stack pointer
Program counter
Condition code register
0
31
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FPCR
FPSR
FPIAR
Floating-point data registers
MACSR
ACC0
ACC1
ACC2
ACC3
ACCext01
ACCext23
MASK
MAC status register
MAC accumulator 0
MAC accumulator 1 (EMAC only)
MAC accumulator 2 (EMAC only)
MAC accumulator 3 (EMAC only)
ACC0 and ACC1 extensions
ACC2 and ACC3 extensions
MAC mask register
Floating-point control register
Floating-point status register
Floating-point instruction address register
0
15
31
Supervisor Registers
D0
D1
D2
D3
D4
D5
D6
D7
0
(CCR) SR
OTHER_A7
Must be zeros VBR
CACR
ASID
ACR0
ACR1
ACR2
ACR3
MMUBAR
ROMBAR0
ROMBAR1
RAMBAR0
RAMBAR1
MBAR
19
Status register
Supervisor A7 stack pointer
Vector base register
Cache control register
Address space ID register
Access control register 0 (data)
Access control register 1 (data)
Access control register 2 (instruction)
Access control register 3 (instruction)
MMU base address register
ROM base address register 0
ROM base address register 1
RAM base address register0
RAM base address register 1
Module base address register
Figure 3-3. ColdFire Programming Model
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Programming Model
3.3.1
User Programming Model
The user programming model, shown in Figure 3-3, consists of the following registers:
• 16 general-purpose, 32-bit registers (D7–D0 and A7–A0); A7 is a user stack pointer
• 32-bit program counter
• 8-bit condition code register
• Registers to support the EMAC
• Register to support the floating-point unit (FPU)
3.3.1.1
Data Registers (D0–D7)
Registers D0–D7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit)
operations. They may also be used as index registers.
3.3.1.2
Address Registers (A0–A6)
The address registers (A0–A6) can be used as software stack pointers, index registers, or base address
registers, and may be used for word and longword operations.
3.3.2
User Stack Pointer (A7)
The CF4e architecture supports two unique stack pointer (A7) registers—the supervisor stack pointer
(SSP) and the user stack pointer (USP). This support provides the required isolation between operating
modes as dictated by the virtual memory management scheme provided by the memory management unit
(MMU). The SSP is described in Section 5.4.2, “Supervisor/User Stack Pointers.”
3.3.2.1
Program Counter (PC)
The PC holds the address of the executing instruction. For sequential instructions, the processor
automatically increments PC. When program flow changes, the PC is updated with the target instruction.
For some instructions, the PC specifies the base address for PC-relative operand addressing modes.
3.3.2.2
Condition Code Register (CCR)
The CCR, Figure 3-4, occupies SR[7–0], as shown in Figure 3-3. The CCR[4–0] bits are indicator flags
based on results generated by arithmetic operations.
R
7
6
5
4
3
2
1
0
0
0
0
X
N
Z
V
C
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
Accessed using R/W commands for the status register
Figure 3-4. Condition Code Register (CCR)
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Table 3-1. CCR Field Descriptions
3.3.3
Bits
Name
Description
7–5
—
Reserved, should be cleared.
4
X
Extend condition code bit. Assigned the value of the carry bit for arithmetic operations;
otherwise not affected or set to a specified result. Also used as an input operand for
multiple-precision arithmetic.
3
N
Negative condition code bit. Set if the msb of the result is set; otherwise cleared.
2
Z
Zero condition code bit. Set if the result equals zero; otherwise cleared.
1
V
Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result
cannot be represented in the operand size; otherwise cleared.
0
C
Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition
or if a borrow occurs in a subtraction; otherwise cleared.
EMAC Programming Model
The registers in the EMAC portion of the user programming model are described in Chapter 4, “Enhanced
Multiply-Accumulate Unit (EMAC),” and include the following registers:
• Four 48-bit accumulator registers partitioned as follows:
— Four 32-bit accumulators (ACC0–ACC3)
— Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two
32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC
arithmetic operations generally affect the entire 48-bit destination.
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values for load
and store operations (ACCext01 and ACCext23)
• One 16-bit mask register (MASK)
• One 32-bit status register (MACSR), including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0–PAV3).
These registers are shown in Figure 3-5.
31
0
MACSR
ACC0
ACC1
ACC2
ACC3
ACCext01
ACCext23
MASK
MAC status register
MAC accumulator 0
MAC accumulator 1
MAC accumulator 2
MAC accumulator 3
Extensions for ACC0 and ACC1
Extensions for ACC2 and ACC3
MAC mask register
Figure 3-5. EMAC Register Set
3.3.4
FPU Programming Model
The registers in the FPU portion of the programming model are described in Chapter 6, “Floating-Point
Unit (FPU),” and include the folllowing registers:
MCF548x Reference Manual, Rev. 3
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Programming Model
•
•
•
•
Eight 64-bit floating-point data registers (FP0–FP7)
One 32-bit floating-point control register (FPCR)
One 32-bit floating-point status register (FPSR)
One 32-bit floating-point instruction address register (FPIAR)
Figure 3-6 shows the FPU programming model.
63
31
0
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FPCR
FPSR
FPIAR
Floating-point data registers
Floating-point control register
Floating-point status register
Floating-point instruction address register
Figure 3-6. Floating-Point Programmer’s Model
3.3.5
Supervisor Programming Model
The MCF548x supervisor programming model is shown in Figure 3-3. Typically, system programmers use
the supervisor programming model to implement operating system functions and provide memory and I/O
control. The supervisor programming model provides access to the user registers and additional supervisor
registers, which include the upper byte of the status register (SR), the vector base register (VBR), and
registers for configuring attributes of the address space connected to the Version 4 processor core. Most
supervisor-level registers are accessed by using the MOVEC instruction with the control register
definitions in Table 3-2.
Table 3-2. MOVEC Register Map
Rc[11–0]
Register Definition
0x002
Cache control register (CACR)
0x004
Access control register 0 (ACR0)
0x005
Access control register 1 (ACR1)
0x006
Access control register 2 (ACR2)
0x007
Access control register 3 (ACR3)
0x801
Vector base register (VBR)
0xC04
RAM base address register 0 (RAMBAR0)
0xC05
RAM base address register 1 (RAMBAR1)
0xC0F
Module base address register (MBAR)
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3-11
3.3.5.1
Status Register (SR)
The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software
can read or write the entire SR; user software can read or write only SR[7–0], described in Section 3.3.2.2,
“Condition Code Register (CCR).” The control bits indicate processor states—trace mode (T), supervisor
or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset.
15
14
13
12
11
10
9
8
7
6
System byte
R
T
0
S
M
0
0
0
1
0
0
5
4
3
2
1
0
Condition code register (CCR)
I
0
0
0
X
N
Z
V
C
0
0
0
—
—
—
—
—
W
Reset
1
Reg
Addr
1
1
0x27xx
Figure 3-7. Status Register (SR)
Table 3-3 describes SR fields.
Table 3-3. SR Field Descriptions
Bits
Name
15
T
Trace enable. When T is set, the processor performs a trace exception after every
instruction.
13
S
Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
12
M
Master/interrupt state. Cleared by an interrupt exception. It can be set by software during
execution of the RTE or move to SR instructions so the OS can emulate an interrupt stack
pointer.
10–8
I
Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited
for all priority levels less than or equal to the current priority, except the edge-sensitive
level-7 request, which cannot be masked.
7–0
CCR
3.3.5.2
Description
Condition code register. See Table 3-1.
Vector Base Register (VBR)
The VBR holds the base address of the exception vector table in memory. The displacement of an
exception vector is added to the value in this register to access the vector table. The VBR[19–0] bits are
not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte
boundary.
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Programming Model
31
30
R
29
28
27
26
25
24
Exception vector table base address
23
22
21
20
1
19
18
17
16
0
0
0
0
W
Reset
0
0
0
0
0
0
0
Reg
Addr
0
0
0
0
0
0
0
0
0
0x801
R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
0x801
1
Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from
the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
Figure 3-8. Vector Base Register (VBR)
3.3.5.3
Cache Control Register (CACR)
The CACR controls operation of both the instruction and data cache memory. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. See Section 7.10.1, “Cache Control Register (CACR).”
3.3.5.4
Access Control Registers (ACR0–ACR3)
The access control registers (ACR0–ACR3) define attributes for four user-defined memory regions: ACR0
and ACR1 control data memory space, and ACR2 and ACR3 control instruction memory space. Attributes
include definition of cache mode, write protect and buffer write enables. See Section 7.10.2, “Access
Control Registers (ACR0–ACR3).”
3.3.5.5
RAM Base Address Registers (RAMBAR0 and RAMBAR1)
The RAMBAR registers determine the base address location of the internal SRAM modules and indicate
the types of references mapped to each. Each RAMBAR includes a base address, write-protect bit, address
space mask bits, and an enable. The RAM base address must be aligned on a 0-module-2-Kbyte boundary.
See Section 7.4.1, “SRAM Base Address Registers (RAMBAR0/RAMBAR1).”
3.3.5.6
Module Base Address Register (MBAR)
The module base address register (MBAR) defines the logical base address for the memory-mapped space
containing the control registers for the on-chip peripherals. See Section 9.3.1, “Module Base Address
Register (MBAR).”
3.3.6
Programming Model Table
Table 3-4 lists register names, the CPU space location, whether the register is written from the processor
using the MOVEC instruction, and the complete register name.
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3-13
Table 3-4. ColdFire CPU Registers
Name
CPU Space (Rc) Written with MOVEC
Register Name
Memory Management Control Registers
CACR
0x002
Yes
Cache control register
ASID
0x003
Yes
Address space identifier
ACR0–ACR3 0x004–0x007
Yes
Access control registers 0–3
MMUBAR
Yes
MMU base address register
0x008
Processor General-Purpose Registers
D0–D7
0x(0,1)80–0x(0,1
)87
No
Data registers 0–7 (0 = load, 1 = store)
A0–A7
0x(0,1)88–0x(0,1
)8F
No
Address registers 0–7 (0 = load, 1 = store) A7 is user
stack pointer
Processor Miscellaneous Registers
OTHER_A7
0x800
No
Other stack pointer
VBR
0x801
Yes
Vector base register
MACSR
0x804
No
MAC status register
MASK
0x805
No
MAC address mask register
ACC0–ACC3 0x806–0x80B
No
MAC accumulators 0–3
ACCext01
0x807
No
MAC accumulator 0, 1 extension bytes
ACCext23
0x808
No
MAC accumulator 2, 3 extension bytes
SR
0x80E
No
Status register
PC
0x80F
Yes
Program counter
Processor Floating-Point Registers
FPU0
0x810
No
32 msbs of floating-point data register 0
FPL0
0x811
No
32 lsbs of floating-point data register 0
FPU1
0x812
No
32 msbs of floating-point data register 1
FPL1
0x813
No
32 lsbs of floating-point data register 1
FPU2
0x814
No
32 msbs of floating-point data register 2
FPL2
0x815
No
32 lsbs of floating-point data register 2
FPU3
0x816
No
32 msbs of floating-point data register 3
FPL3
0x817
No
32 lsbs of floating-point data register 3
FPU4
0x818
No
32 msbs of floating-point data register 4
FPL4
0x819
No
32 lsbs of floating-point data register 4
FPU5
0x81A
No
32 msbs of floating-point data register 5
FPL5
0x81B
No
32 lsbs of floating-point data register 5
FPU6
0x81C
No
32 msbs of floating-point data register 6
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Data Format Summary
Table 3-4. ColdFire CPU Registers (Continued)
Name
CPU Space (Rc) Written with MOVEC
Register Name
FPL6
0x81D
No
32 lsbs of floating-point data register 6
FPU7
0x81E
No
32 msbs of floating-point data register 7
FPL7
0x81F
No
32 lsbs of floating-point data register 7
FPIAR
0x821
No
Floating-point instruction address register
FPSR
0x822
No
Floating-point status register
FPCR
0x824
No
Floating-point control register
Local Memory and Module Control Registers
RAMBAR0
0xC04
Yes
RAM base address register 0
RAMBAR1
0xC05
Yes
RAM base address register 1
MBAR
0xC0F
Yes
Primary module base address register (not a core
register)
3.4
Data Format Summary
Table 3-5 lists the operand data formats. Integer operands can reside in registers, memory, or instructions.
The operand size is either explicitly encoded in the instruction or implicitly defined by the instruction
operation.
Table 3-5. Integer Data Formats
Operand Data Format
3.4.1
Size
Bit
1 bit
Byte integer
8 bits
Word integer
16 bits
Longword integer
32 bits
Data Organization in Registers
The following sections describe data organization in data, address, and control registers. Section 6.2.2,
“Floating-Point Data Formats,” describes floating-point formatting.
3.4.1.1
Integer Data Format Organization in Registers
Figure 3-9 shows the integer format for data registers. Each integer data register is 32 bits wide. Byte and
word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. Longword
operands occupy the entire 32 bits of integer data registers. A data register that is either a source or
destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations,
respectively. The remaining high-order portion does not change. Note that the least-significant bit is bit 0
for all data types, whereas the msbs for longword integer is bit 31, the msb of a word integer is bit 15, and
the msb of a byte integer is bit 7.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-15
31
30
1
0
msb
lsb
31
8
Not used
31
msb
6
1
0
msb Lower-order byte lsb
16
Not used
31
7
15
msb
14
1
Byte (8 bits)
0
Lower-order word
30
Bit (0 bit number 31)
lsb
1
Word (16 bits)
0
Longword
lsb
Longword (32 bits)
Figure 3-9. Organization of Integer Data Format in Data Registers
Instruction encodings disallow use of address registers for byte operands. When an address register is a
source operand, either the low-order word or the entire longword operand is used, depending on the
operation size. Word-length source operands are sign-extended to 32 bits and then used in the operation
with an address register destination. When an address register is a destination, the entire register is
affected, regardless of the operation size. Figure 3-10 shows integer formats for address registers.
31
16
Sign-Extended
15
0
16-Bit Address Operand
31
0
Full 32-Bit Address Operand
Figure 3-10. Organization of Integer Data Formats in Address Registers
The size of control registers varies according to function. Some have undefined bits reserved for future
definition by Freescale. Those bits read as zeros and must be written as zeros for future compatibility.
Operations to the SR and CCR are word-sized. The upper CCR byte is read as all zeros and is ignored when
written, regardless of privilege mode.
3.4.1.2
Integer Data Format Organization in Memory
ColdFire processors use big-endian addressing. Byte-addressable memory organization allows lower
addresses to correspond to higher-order bytes. The address N of a longword data item corresponds to the
address of the high-order word. The lower-order word is at address N + 2. The address of a word data item
corresponds to the address of the high-order byte. The lower-order byte is at address N + 1. This
organization is shown in Figure 3-11.
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Data Format Summary
31
24 23
16 15
8
7
0
Longword 0x0000_0000
.
.
.
Word 0x0000_0000
Word 0x0000_0002
Byte 0x0000_0000
Byte 0x0000_0001
Byte 0x0000_0002
Byte 0x0000_0003
Longword 0x0000_0004
Word 0x0000_0004
Word 0x0000_0006
Byte 0x0000_0004
Byte 0x0000_0005
Byte 0x0000_0006
Byte 0x0000_0007
.
.
.
Longword 0xFFFF_FFFC
Word 0xFFFF_FFFC
Word 0xFFFF_FFFE
Byte 0xFFFF_FFFC
Byte 0xFFFF_FFFD
Byte 0xFFFF_FFFE
Byte 0xFFFF_FFFF
.
.
.
Figure 3-11. Memory Operand Addressing
3.4.2
EMAC Data Representation
The EMAC supports the following three modes, where each mode defines a unique operand type.
• Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2(N-1)
< operand < 2(N-1) - 1. The binary point is right of the lsb.
• Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N - 1. The
binary point is right of the lsb.
• Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining
bits signify the first N-1 bits after the binary point. Given an N-bit number, aN-1aN-2aN-3... a2a1a0,
its value is given by the equation in Figure 3-12.
N–2
value = – ( 1 ⋅ a N – 1 ) +
∑
2
(i + 1 – N)
⋅ ai
i=0
Figure 3-12. Two’s Complement, Signed Fractional Equation
This format can represent numbers in the range -1 < operand < 1 - 2(N-1).
For words and longwords, the largest negative number that can be represented is -1, whose internal
representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 – 2-15);
the most positive longword is 0x7FFF_FFFF or (1 – 2-31).
For more information, see Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC).”
3.4.2.1
Floating-Point Data Formats and Types
The FPU supports signed byte, word, and longword integer formats, which are identical to those
supported by the integer unit. The FPU also supports single- and double-precision binary
floating-point formats that fully comply with the IEEE-754 standard.
For more information, see Chapter 6, “Floating-Point Unit (FPU).”
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-17
3.4.2.1.1
Signed-Integer Data Formats
The FPU supports 8-bit byte (B), 16-bit word (W), and 32-bit longword (L) integer data formats.
3.4.2.1.2
Floating-Point Data Formats
Figure 3-13 shows the two binary floating-point data formats.
31
S
63
S
62
30
22
8-Bit Exponent
Sign of Mantissa
51
11-Bit Exponent
52-Bit Fraction
0
23-Bit Fraction
Single
0
Double
Sign of Mantissa
Figure 3-13. Floating-Point Data Formats
Note that, throughout this chapter, a mantissa is defined as the concatenation of an integer bit, the binary
point, and a fraction. A fraction is the term designating the bits to the right of the binary point in the
mantissa.
Mantissa
(integer bit).(fraction)
Figure 3-14. Mantissa
The integer bit is implied to be set for normalized numbers and infinities, clear for zeros and denormalized
numbers. For not-a-numbers (NANs), the integer bit is ignored. The exponent in both floating-point
formats is an unsigned binary integer with an implied bias added to it. Subtracting the bias from exponent
yields a signed, two’s complement power of two. This represents the magnitude of a normalized
floating-point number when multiplied by the mantissa.
By definition, a normalized mantissa always takes values starting from 1.0 and going up to, but not
including, 2.0; that is, [1.0...2.0).
3.5
Addressing Mode Summary
Addressing modes are categorized by how they are used. Data addressing modes refer to data operands.
Memory addressing modes refer to memory operands. Alterable addressing modes refer to alterable
(writable) data operands. Control addressing modes refer to memory operands without an associated size.
These categories sometimes combine to form more restrictive categories. Two combined classifications
are alterable memory (both alterable and memory) and data alterable (both alterable and data). Twelve of
the most commonly used effective addressing modes from the M68000 Family are available on ColdFire
microprocessors. Table 3-6 summarizes these modes and their categories.
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Instruction Set Summary
Table 3-6. ColdFire Effective Addressing Modes
Addressing Modes
Mode
Field
Reg.
Field
Dn
An
000
001
(An)
(An)+
–(An)
(d16, An)
Syntax
Category
Data
Memory
Control
Alterable
reg. no.
reg. no.
X
—
—
—
—
—
X
X
010
011
100
101
reg. no.
reg. no.
reg. no.
reg. no.
X
X
X
X
X
X
X
X
X
—
—
X
X
X
X
X
(d8, An,
Xi*SF)
110
reg. no.
X
X
X
X
Program counter indirect
with displacement
(d16, PC)
111
010
X
X
X
—
Program counter indirect with
scaled index
8-bit displacement
(d8, PC,
Xi*SF)
111
011
X
X
X
—
Absolute data addressing
Short
Long
(xxx).W
(xxx).L
111
111
000
001
X
X
X
X
X
X
—
—
Immediate
#<xxx>
111
100
X
X
—
—
Register direct
Data
Address
Register indirect
Address
Address with
Postincrement
Address with
Predecrement
Address with
Displacement
Address register indirect with
scaled index
8-bit displacement
3.6
Instruction Set Summary
The ColdFire instruction set is a simplified version of the M68000 instruction set. The removed
instructions include BCD, bit field, logical rotate, decrement and branch, and integer multiply with a 64-bit
result.
“About This Book” lists notational conventions used throughout this manual.
3.6.1
Additions to the Instruction Set Architecture
The original ColdFire ISA was derived from M68000 Family opcodes based on extensive analysis of
embedded application code. After the first ColdFire compilers were created, developers identified ISA
additions that would enhance both code density and overall performance. Additionally, as users
implemented ColdFire-based designs into a wide range of embedded systems, they identified frequently
used instruction sequences that could be improved by creating new instructions. This observation was
especially prevalent in environments that used substantial amounts of assembly language code.
The original ISA minimized support for instructions referencing byte and word operands. MOVE.B and
MOVE.W were fully supported; otherwise, only CLR (clear) and TST (test) supported these data types.
Based on input from compiler writers and system users, a set of instruction enhancements was proposed
to address the following:
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-19
•
•
Enhanced support for byte and word-sized operands through new move operations
Enhanced support for position-independent code
For descriptions of the ColdFire instruction set, see the latest version of the ColdFire Programmer’s
Reference Manual.
The following list summarizes new and enhanced instructions of ISA_B:
• New instructions:
— INTOUCH loads blocks of instructions to be locked in the instruction cache.
— MOV3Q.L moves 3-bit immediate data to the destination location.
— MOVE to/from USP loads and stores user stack pointer.
— MVS.{B,W} sign-extends the source operand and moves it to the destination register.
— MVZ.{B,W} zero-fills the source operand and moves it to the destination register.
— SATS.L performs a saturation operation for signed arithmetic and updates the destination
register depending on CCR[V] and bit 31 of the register.
— TAS.B performs an indivisible read-modify-write cycle to test and set the addressed memory
byte.
• Enhancements to existing Revision_A instructions:
— Longword support for branch instructions (Bcc, BRA, BSR)
— Byte and word support for compare instructions (CMP, CMPI)
— Word support for the compare address register instruction (CMPA)
— Byte and longword support for MOVE.x,where the source is immediate data and the
destination is specified by d16(Ax); that is, MOVE.{B,W} #<data>, d16(Ax)
• Floating-point instructions. See Chapter 6, “Floating-Point Unit (FPU).”
• EMAC instructions. See Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” for more
information.
Table 3-7 shows the syntax for the new and enhanced instructions. As Table 3-7 shows, some ISA_B
opcodes were defined in the M68000 family and others are new.
Table 3-7. V4 New Instruction Summary
Instruction
Mnemonic1
Source
Destination
M68000
ISA_B Extensions
Branch Always
bra.l
<label>
Yes
Branch Conditionally
bcc.l
<label>
Yes
Branch to Subroutine
bsr.l
<label>
Yes
Compare
cmp.{b,w,l}
<ea>y
Dx
Yes
cmpa.w
<ea>y
Ax
Yes
cmpi.{b,w}
#<data>
Dx
Yes
Instruction Fetch Touch
intouch
<Ay>
Move 3-Bit Data Quick
mov3q.l
#<data>
<ea>x
move.{b,w}
#<data>
d16(Ax)
Yes
move.l
USP
Ax
Yes
Compare Address
Compare Immediate
Move Data Source to Destination
Move from USP
MCF548x Reference Manual, Rev. 3
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Instruction Set Summary
Table 3-7. V4 New Instruction Summary (Continued)
Mnemonic1
Source
Destination
M68000
move.l
Ay
USP
Yes
Move with Sign Extend
mvs.{b,w}
<ea>y
Dx
Move with Zero-Fill
mvz.{b,w}
<ea>y
Dx
Instruction
Move to USP
Signed Saturate
sats.l
Dx
Test and Set an Operand
tas.b
<ea>x
Yes
EMAC Extensions
Move from an Accumulator and Clear
movclr.l
ACCx
Rx
No
Copy an Accumulator
move.l
ACCy
ACCx
No
Move from Accumulator 0 and 1 Extensions
move.l
ACCext01
Rx
No
Move from Accumulator 2 and 3 Extensions
move.l
ACCext23
Rx
No
Move to Accumulator 0 and 1 Extensions
move.l
Ry
ACCext01
No
Move to Accumulator 2 and 2 Extensions
move.l
Ry
ACCext23
No
FPU Instructions
Floating-Point Absolute Value
fabs.{b,w,l,s,d}
<ea>y
FPx
Yes
Floating-Point Add
fadd.{b,w,l,s,d}
<ea>y
FPx
Yes
<label>
Yes
Floating-Point Branch Conditionally
Floating-Point Compare
fbcc.{w,l}
fcmp.{b,w,l,s,d}
<ea>y
FPx
Yes
Floating-Point Divide
fdiv.{b,w,l,s,d}
<ea>y
FPx
Yes
Floating-Point Integer
fint.{b,w,l,s,d}
<ea>y
FPx
Yes
Floating-Point Integer Round-to-Zero
fintrz.{b,w,l,s,d}
<ea>y
FPx
Yes
Move Floating-Point Data Register
fmove.{b,w,l,s,d}
<ea>y
FPx
Yes
Move from FPCR
fmove.l
FPCR
<ea>x
Yes
Move from FPIAR
fmove.l
FPIAR
<ea>x
Yes
Move from FPSR
fmove.l
FPSR
<ea>x
Yes
Move from FPCR
fmove.l
<ea>y
FPCR
Yes
Move from FPIAR
fmove.l
<ea>y
FPIAR
Yes
Move from FPSR
fmove.l
<ea>y
FPSR
Yes
fmovem.d
#list
<ea>y
<ea>x
#list
Yes
Floating-Point Multiply
fmul.{b,w,l,s,d}
<ea>y
FPx
Yes
Floating-Point Negate
fneg.{b,w,l,s,d}
<ea>y
FPx
Yes
Move Multiple Floating Point Data Registers
Floating-Point No Operation
fnop
Restore Internal Floating Point State
frestore
Yes
<ea>y
Yes
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-21
Table 3-7. V4 New Instruction Summary (Continued)
Mnemonic1
Instruction
Save Internal Floating Point State
Source
Destination
M68000
<ea>x
Yes
fsave
Floating-Point Square Root
fsqrt.{b,w,l,s,d}
<ea>y
FPx
Yes
Floating-Point Subtract
fsub.{b,w,l,s,d}
<ea>y
FPx
Yes
Test Floating-Point Operand
ftst.{b,w,l,s,d}
<ea>y
1
Yes
Operand sizes in this column reflect only newly supported operand sizes for existing instructions (Bcc, BRA,
BSR, CMP, CMPA, CMPI, and MOVE)
3.6.2
Instruction Set Summary
Table 3-8 lists user-mode instructions by opcode.
Table 3-8. User-Mode Instruction Set Summary
Instruction
Operand Syntax
Operand Size
Operation
ADD
L
L
L
Source + Destination → Destination
ADDA
Dy,<ea>x
<ea>y,Dx
<ea>y,Ax
ADDI
ADDQ
#<data>,Dx
#<data>,<ea>x
L
L
Immediate Data + Destination → Destination
ADDX
Dy,Dx
L
Source + Destination + CCR[X] → Destination
AND
<ea>y,Dx
Dy,<ea>x
L
L
Source & Destination → Destination
ANDI
#<data>, Dx
L
Immediate Data & Destination → Destination
ASL
Dy,Dx
#<data>,Dx
L
L
CCR[X,C] ← (Dx << Dy) ← 0
CCR[X,C] ← (Dx << #<data>) ← 0
ASR
Dy,Dx
#<data>,Dx
L
L
msb → (Dx >> Dy) → CCR[X,C]
msb → (Dx >> #<data>) → CCR[X,C
Bcc
<label>
B, W, L
If Condition True, Then PC + dn → PC
BCHG
Dy,<ea>x
#<data>,<ea>x
B, L
B, L
~ (<bit number> of Destination) → CCR[Z] →
<bit number> of Destination
BCLR
Dy,<ea>x
#<data>,<ea>x
B, L
B, L
~ (<bit number> of Destination) → CCR[Z];
0 →<bit number> of Destination
BRA
<label>
B, W, L
BSET
Dy,<ea>x
#<data>,<ea>x
B, L
B, L
BSR
<label>
B, W, L
BTST
Dy,<ea>x
#<data>,<ea>x
B, L
B, L
CLR
<ea>x
B, W, L
PC + dn → PC
~ (<bit number> of Destination) → CCR[Z];
1 → <bit number> of Destination
SP – 4 → SP; nextPC → (SP); PC + dn → PC
~ (<bit number> of Destination) → CCR[Z]
0 → Destination
MCF548x Reference Manual, Rev. 3
3-22
Freescale Semiconductor
Instruction Set Summary
Table 3-8. User-Mode Instruction Set Summary (Continued)
Instruction
Operand Syntax
Operand Size
CMP
CMPA
<ea>y,Dx
<ea>y,Ax
B, W, L
W, L
Destination – Source → CCR
CMPI
#<data>,Dx
B, W, L
Destination – Immediate Data → CCR
DIVS/DIVU
<ea>y,Dx
W, L
Destination / Source → Destination
(Signed or Unsigned)
EOR
Dy,<ea>x
L
Source ^ Destination → Destination
EORI
#<data>,Dx
L
Immediate Data ^ Destination → Destination
EXT
Dx
Dx
Dx
B→W
W→L
B→L
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
FADD
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FBcc
<label>
W, L
FCMP
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FPx - Source
FDABS
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
Absolute Value of Source → FPx; round destination
to double
Absolute Value of FPx → FPx; round destination to
double
FDADD
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
Source + FPx → FPx; round destination to double
FDDIV
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FPx / Source → FPx; round destination to double
FDIV
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FPx / Source → FPx
FDMOVE
FPy,FPx
D
Source → Destination; round destination to double
FDMUL
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
Source * FPx → FPx; round destination to double
FDNEG
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
- (Source) → FPx; round destination to double
FDSQRT
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
Square Root of Source → FPx; round destination to
double
Square Root of FPx → FPx; round destination to
double
FDSUB
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FPx - Source → FPx; round destination to double
EXTB
FABS
Operation
Sign-Extended Destination → Destination
Absolute Value of Source → FPx
Absolute Value of FPx → FPx
Source + FPx → FPx
If Condition True, Then PC + dn → PC
- (FPx) → FPx; round destination to double
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-23
Table 3-8. User-Mode Instruction Set Summary (Continued)
Instruction
Operand Syntax
Operand Size
FINT
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
Integer Part of Source → FPx
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
Integer Part of Source → FPx; round to zero
<ea>y,FPx
FPy,<ea>x
FPy,FPx
FPcr,<ea>x
<ea>y,FPcr
B,W,L,S,D
B,W,L,S,D
D
L
L
Source → Destination
FMOVEM
#list,<ea>x
<ea>y,#list
D
FMUL
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
Source * FPx → FPx
FNEG
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
- (Source) → FPx
FNOP
none
none
FSABS
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
Absolute Value of Source → FPx; round destination
to single
Absolute Value of FPx → FPx; round destination to
single
FSADD
<ea>y,FPx
FPy,FPx
B,W,L,S,D
Source + FPx → FPx; round destination to single
FSDIV
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FPx / Source → FPx; round destination to single
FSMOVE
<ea>y,FPx
B,W,L,S,D
Source → Destination; round destination to single
FSMUL
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
Source * FPx → FPx; round destination to single
FSNEG
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
- (Source) → FPx; round destination to single
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
Square Root of Source → FPx
FSSQRT
<ea>y,FPx
FPy,FPx
FPx
B,W,L,S,D
D
D
Square Root of Source → FPx; round destination to
single
Square Root of FPx → FPx; round destination to
single
FSSUB
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FPx - Source → FPx; round destination to single
FINTRZ
FMOVE
FSQRT
Operation
Integer Part of FPx → FPx
Integer Part of FPx → FPx; round to zero
FPcr can be any floating point control register:
FPCR, FPIAR, FPSR
Listed registers → Destination
Source → Listed registers
- (FPx) → FPx
PC + 2 → PC (FPU Pipeline Synchronized)
- (FPx) → FPx; round destination to single
Square Root of FPx → FPx
MCF548x Reference Manual, Rev. 3
3-24
Freescale Semiconductor
Instruction Set Summary
Table 3-8. User-Mode Instruction Set Summary (Continued)
Instruction
Operand Syntax
Operand Size
FSUB
<ea>y,FPx
FPy,FPx
B,W,L,S,D
D
FTST
<ea>y
B, W, L, S, D
ILLEGAL
none
none
SP – 4 → SP; PC → (SP) → PC; SP – 2 → SP;
SR → (SP); SP – 2 → SP; Vector Offset → (SP);
(VBR + 0x10) → PC
JMP
<ea>y
none
Source Address → PC
JSR
<ea>y
none
SP – 4 → SP; nextPC → (SP); Source → PC
LEA
<ea>y,Ax
L
<ea>y → Ax
LINK
Ay,#<displacement>
W
SP – 4 → SP; Ay → (SP); SP → Ay, SP + dn → SP
LSL
Dy,Dx
#<data>,Dx
L
L
CCR[X,C] ← (Dx << Dy) ← 0
CCR[X,C] ← (Dx << #<data>) ← 0
LSR
Dy,Dx
#<data>,Dx
L
L
0 → (Dx >> Dy) → CCR[X,C]
0 → (Dx >> #<data>) → CCR[X,C]
MAC
Ry,RxSF,ACCx
Ry,RxSF,<ea>y,Rw,ACCx
W, L
W, L
MOV3Q
#<data>,<ea>x
L
Immediate Data → Destination
MOVCLR
ACCy,Rx
L
Accumulator → Destination, 0 → Accumulator
MOVE
<ea>y,<ea>x
MACcr,Dx
<ea>y,MACcr
CCR,Dx
<ea>y,CCR
B,W,L
L
L
W
W
Source → Destination
where MACcr can be any MAC control register:
ACCx, ACCext01, ACCext23, MACSR, MASK
MOVEA
<ea>y,Ax
W,L → L
MOVEM
#list,<ea>x
<ea>y,#list
L
Listed Registers → Destination
Source → Listed Registers
MOVEQ
#<data>,Dx
B→L
Immediate Data → Destination
MSAC
Ry,RxSF,ACCx
Ry,RxSF,<ea>y,Rw,ACCx
W, L
W, L
MULS/MULU
<ea>y,Dx
W*W→L
L*L→L
MVS
<ea>y,Dx
B,W
Source with sign extension → Destination
MVZ
<ea>y,Dx
B,W
Source with zero fill → Destination
NEG
Dx
L
0 – Destination → Destination
NEGX
Dx
L
0 – Destination – CCR[X] → Destination
NOP
none
none
MOVE from
CCR
MOVE to CCR
Operation
FPx - Source → FPx
Source Operand Tested → FPCC
ACCx + (Ry * Rx){<<|>>}SF → ACCx
ACCx + (Ry * Rx){<<|>>}SF → ACCx;
(<ea>y(&MASK)) → Rw
Source → Destination
ACCx - (Ry * Rx){<<|>>}SF → ACCx
ACCx - (Ry * Rx){<<|>>}SF → ACCx;
(<ea>y(&MASK)) → Rw
Source * Destination → Destination
(Signed or Unsigned)
PC + 2 → PC (Integer Pipeline Synchronized)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-25
Table 3-8. User-Mode Instruction Set Summary (Continued)
Instruction
Operand Syntax
Operand Size
Operation
NOT
Dx
L
~ Destination → Destination
OR
<ea>y,Dx
Dy,<ea>x
L
L
Source | Destination → Destination
ORI
#<data>,Dx
L
Immediate Data | Destination → Destination
PEA
<ea>y
L
SP – 4 → SP; <ea>y → (SP)
PULSE
none
none
REMS/REMU
<ea>y,Dw:Dx
L
RTS
none
none
SATS
Dx
L
If CCR[V] == 1;
then if Dx[31] == 0;
then Dx[31:0] = 0x80000000;
else Dx[31:0] = 0x7FFFFFFF;
else Dx[31:0] is unchanged
Scc
Dx
B
If Condition True, Then 1s → Destination;
Else 0s → Destination
SUB
L
L
L
Destination - Source → Destination
SUBA
<ea>y,Dx
Dy,<ea>x
<ea>y,Ax
SUBI
SUBQ
#<data>,Dx
#<data>,<ea>x
L
L
Destination – Immediate Data → Destination
SUBX
Dy,Dx
L
Destination – Source – CCR[X] → Destination
SWAP
Dx
W
MSW of Dx ↔ LSW of Dx
TAS
<ea>x
B
Destination Tested → CCR;
1 → bit 7 of Destination
TPF
none
#<data>
#<data>
none
W
L
PC + 2→ PC
PC + 4 → PC
PC + 6→ PC
TRAP
#<vector>
none
1 → S Bit of SR; SP – 4 → SP; nextPC → (SP);
SP – 2 → SP; SR → (SP)
SP – 2 → SP; Format/Offset → (SP)
(VBR + 0x80 +4*n) → PC, where n is the TRAP
number
TST
<ea>y
B, W, L
UNLK
Ax
none
WDDATA
<ea>y
B, W, L
Set PST = 0x4
Destination / Source → Remainder
(Signed or Unsigned)
(SP) → PC; SP + 4 → SP
Source Operand Tested → CCR
Ax → SP; (SP) → Ax; SP + 4 → SP
Source → DDATA port
Table 3-9 describes supervisor-mode instructions.
MCF548x Reference Manual, Rev. 3
3-26
Freescale Semiconductor
Instruction Execution Timing
Table 3-9. Supervisor-Mode Instruction Set Summary
3.7
Instruction
Operand Syntax
Operand Size
Operation
CPUSHL
ic,(Ax)
dc,(Ax)
bc,(Ax)
none
If data is valid and modified, push cache line; invalidate line
if programmed in CACR (synchronizes pipeline)
FRESTORE
<ea>y
none
FPU State Frame → Internal FPU State
FSAVE
<ea>x
none
Internal FPU State → FPU State Frame
HALT
none
none
Halt processor core
INTOUCH
Ay
none
Instruction fetch touch at (Ay)
MOVE from SR
SR,Dx
W
SR → Destination
MOVE from USP
USP,Dx
L
USP → Destination
MOVE to SR
<ea>y,SR
W
Source → SR; Dy or #<data> source only
MOVE to USP
Ay,USP
L
Source → USP
MOVEC
Ry,Rc
L
Ry → Rc
RTE
none
none
2 (SP) → SR; 4 (SP) → PC; SP + 8 →SP
Adjust stack according to format
STOP
#<data>
none
Immediate Data → SR; STOP
WDEBUG
<ea>y
L
Addressed Debug WDMREG Command Executed
Instruction Execution Timing
The timing data in this section assumes the following:
• Execution times for individual instructions make no assumptions concerning the OEP’s ability to
dispatch multiple instructions in one machine cycle. For sequences where instruction pairs are
issued, the execution time of the first instruction defines the execution time of pair; the second
instruction effectively executes in zero cycles.
• The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP spends no time waiting for the IFP to supply
opwords or extension words.
• The OEP experiences no sequence-related pipeline stalls. For the V4, the most common example
of this type of stall occurs when a register is modified in the EX engine and a subsequent instruction
generates an address that uses the previously modified register. The second instruction stalls in the
OEP until the previous instruction updates the register. For example:
muls.l
move.l
#<data>,d0
(a0,d0.l*4),d1
move.l waits 3 cycles for the muls.l to update d0. If consecutive instructions update a register and
use that register as a base of index value with a scale factor of 1 (Xi.l*1) in an address calculation,
a 2-cycle pipeline stall occurs. If the destination register is used as an index register with any other
scale factor (Xi.l*2, Xi.l*4), a 3-cycle stall occurs.
NOTE
Address register results from postincrement and predecrement modes are
available to subsequent instructions without stalls.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-27
•
The OEP can complete all memory accesses without memory causing any stalls. Thus, these
timings assume an infinite, zero-wait state memory attached to the core.
Operand accesses are assumed to be aligned as follows:
— 16-bit operands are aligned on 0-modulo-2 addresses
— 32-bit operands are aligned on 0-modulo-4 addresses
Operands that do not meet these guidelines are misaligned. Table 3-10 shows how the core
decomposes a misaligned operand reference into a series of aligned accesses.
•
Table 3-10. Misaligned Operand References
1
Additional C(R/W)1
A[1:0]
Size
Bus Operations
x1
Word
Byte, Byte
2(1/0) if read
1(0/1) if write
x1
Long
Byte, Word, Byte
3(2/0) if read
2(0/2) if write
10
Long
Word, Word
2(1/0) if read
1(0/1) if write
Each timing entry is presented as C(r/w), described as follows:
C is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all
internal core cycles required to complete the instruction execution.
r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation performing a
read-modify write function is denoted as (1/1).
3.7.1
MOVE Instruction Execution Timing
The following tables show execution times for the MOVE.{B,W,L} instructions. Table 3-13 shows the
timing for the other generic move operations.
NOTE
In these tables, times using PC-relative effective addressing modes are the
same as using An-relative mode.
ET with {<ea> = (d16,PC)}
equals ET with {<ea> = (d16,An)}
ET with {<ea> = (d8,PC,Xi*SF)}
equals ET with {<ea> = (d8,An,Xi*SF)}
The (xxx).wl nomenclature refers to both forms of absolute addressing,
(xxx).w and (xxx).l.
Table 3-11 lists execution times for MOVE.{B,W} instructions.
Table 3-11. Move Byte and Word Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
–(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
(xxx).wl
Dy
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
Ay
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(Ay)
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
MCF548x Reference Manual, Rev. 3
3-28
Freescale Semiconductor
Instruction Execution Timing
Table 3-11. Move Byte and Word Execution Times (Continued)
Destination
Source
Rx
(Ax)
(Ax)+
–(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
(xxx).wl
(Ay)+
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
-(Ay)
1(1/0)
21/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(d16,Ay)
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,Ay,Xi*SF)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
(xxx).w
1(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(xxx).l
1(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(d16,PC)
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,PC,Xi*SF)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
#<xxx>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
—
—
Table 3-12 lists timings for MOVE.L.
Table 3-12. Move Long Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
–(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
(xxx).wl
Dy
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
Ay
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(Ay)
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(Ay)+
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
-(Ay)
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(d16,Ay)
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,Ay,Xi*SF)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
(xxx).w
1(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(xxx).l
1(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(d16,PC)
1(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,PC,Xi*SF)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
#<xxx>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
—
—
—
Table 3-13 gives timings for MOVE.L instructions accessing program-visible EMAC registers, along with
other MOVE.L timings. Execution times for moving ACC or MACSR contents into a destination location
represent the best-case scenario when the store instruction is executed and no load, MAC, or MSAC
instructions are in the EMAC execution pipeline. In general, these store operations take only 1 cycle to
execute, but if preceded immediately by a load, MAC, or MSAC instruction, the EMAC pipeline depth is
exposed and execution time is 3 cycles.
Table 3-19 lists EMAC execution times.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-29
Table 3-13. MAC and Miscellaneous Move Execution Times
Effective Address
Opcode
<ea>
Rn
(An)
(An)+
–(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
move.l
<ea>,ACC
1(0/0)
—
—
—
—
—
—
1(0/0)
move.l
<ea>,MACSR
6(0/0)
—
—
—
—
—
—
6(0/0)
move.l
<ea>,MASK
5(0/0)
—
—
—
—
—
—
5(0/0)
move.l
ACC,Rx
1(0/0)
—
—
—
—
—
—
—
move.l
MACSR,CCR
1(0/0)
—
—
—
—
—
—
—
move.l
MACSR,Rx
1(0/0)
—
—
—
—
—
—
—
move.l
MASK,Rx
1(0/0)
—
—
—
—
—
—
—
moveq
#imm,Dx
—
—
—
—
—
—
—
1(0/0)
mov3q
#imm,<ea>
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
—
mvs
<ea>,Dx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
mvz
<ea>,Dx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
3.7.2
One-Operand Instruction Execution Timing
Table 3-14 shows standard timings for single-operand instructions.
Table 3-14. One-Operand Instruction Execution Times
Effective Address
Opcode
<ea>
Rn
(An)
(An)+
–(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#xxx
clr.b
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
clr.w
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
clr.l
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
ext.w
Dx
1(0/0)
—
—
—
—
—
—
—
ext.l
Dx
1(0/0)
—
—
—
—
—
—
—
extb.l
Dx
1(0/0)
—
—
—
—
—
—
—
neg.l
Dx
1(0/0)
—
—
—
—
—
—
—
negx.l
Dx
1(0/0)
—
—
—
—
—
—
—
not.l
Dx
1(0/0)
—
—
—
—
—
—
—
sats.l
Dx
1(0/0)
—
—
—
—
—
—
—
scc
Dx
1(0/0)
—
—
—
—
—
—
—
swap
Dx
1(0/0)
—
—
—
—
—
—
—
tas
<ea>
1(1/1)
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
tst.b
<ea>
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
tst.w
<ea>
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
tst.l
<ea>
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
MCF548x Reference Manual, Rev. 3
3-30
Freescale Semiconductor
Instruction Execution Timing
3.7.3
Two-Operand Instruction Execution Timing
Table 3-15 shows standard timings for double operand instructions.
Table 3-15. Two-Operand Instruction Execution Times
Effective Address
Opcode
<ea>
Rn
(An)
(An)+
–(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
add.l
<ea>,Rx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
add.l
Dy,<ea>
—
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
addi.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
addq.l
#imm,<ea>
1(0/0)
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
addx.l
Dy,Dx
1(0/0)
—
—
—
—
—
—
—
and.l
<ea>,Rx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
and.l
Dy,<ea>
—
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
andi.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
asl.l
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
asr.l
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
bchg
Dy,<ea>
2(0/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
—
bchg
#imm,<ea>
2(0/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
—
bclr
Dy,<ea>
2(0/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
—
bclr
#imm,<ea>
2(0/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
—
bset
Dy,<ea>
2(0/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
—
bset
#imm,<ea>
2(0/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
—
btst
Dy,<ea>
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
—
btst
#imm,<ea>
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
—
—
—
cmp.b
<ea>,Rx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
cmp.w
<ea>,Rx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
cmp.l
<ea>,Rx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
cmpi.b
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
cmpi.w
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
cmpi.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
divs.w
<ea>,Dx
20(0/0)
20(1/0)
20(1/0)
20(1/0)
20(1/0)
21(1/0)
20(1/0)
20(0/0)
divu.w
<ea>,Dx
20(0/0)
20(1/0)
20(1/0)
20(1/0)
20(1/0)
21(1/0)
20(1/0)
20(0/0)
divs.l
<ea>,Dx
35(0/0)
35(1/0)
35(1/0)
35(1/0)
35(1/0)
—
—
—
divu.l
<ea>,Dx
35(0/0)
35(1/0)
35(1/0)
35(1/0)
35(1/0)
—
—
—
eor.l
Dy,<ea>
1(0/0)
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
eori.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
lea
<ea>,Ax
—
1(0/0)
—
—
1(0/0)
2(0/0)
1(0/0)
—
lsl.l
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-31
Table 3-15. Two-Operand Instruction Execution Times (Continued)
Effective Address
Opcode
<ea>
Rn
(An)
(An)+
–(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
lsr.l
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
mac.w
Ry,Rx
1(0/0)
—
—
—
—
—
—
—
mac.l
Ry,Rx
3(0/0)
—
—
—
—
—
—
—
msac.w
Ry,Rx
1(0/0)
—
—
—
—
—
—
—
msac.l
Ry,Rx
3(0/0)
—
—
—
—
—
—
—
mac.w
Ry,Rx,ea,Rw
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)
—
—
—
mac.l
Ry,Rx,ea,Rw
—
3(1/0)
3(1/0)
3(1/0)
3(1/0)
—
—
—
msac.w
Ry,Rx,ea,Rw
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)
—
—
—
msac.l
Ry,Rx,ea,Rw
—
3(1/0)
3(1/0)
3(1/0)
3(1/0)
—
—
—
muls.w
<ea>,Dx
3(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
3(0/0)
mulu.w
<ea>,Dx
3(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
3(0/0)
muls.l
<ea>,Dx
5(0/0)
5(1/0)
5(1/0)
5(1/0)
5(1/0)
—
—
—
mulu.l
<ea>,Dx
5(0/0)
5(1/0)
5(1/0)
5(1/0)
5(1/0)
—
—
—
or.l
<ea>,Rx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
or.l
Dy,<ea>
—
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
or.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
rems.l
<ea>,Dx
35(0/0)
35(1/0)
35(1/0)
35(1/0)
35(1/0)
—
—
—
remu.l
<ea>,Dx
35(0/0)
35(1/0)
35(1/0)
35(1/0)
35(1/0)
—
—
—
sub.l
<ea>,Rx
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
1(0/0)
sub.l
Dy,<ea>
—
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
subi.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
subq.l
#imm,<ea>
1(0/0)
1(1/1)
1(1/1)
1(1/1)
1(1/1)
2(1/1)
1(1/1)
—
subx.l
Dy,Dx
1(0/0)
—
—
—
—
—
—
—
3.7.4
Miscellaneous Instruction Execution Timing
Table 3-16 lists timings for miscellaneous instructions.
Table 3-16. Miscellaneous Instruction Execution Times
Effective Address
Opcode
<ea>
Rn
(An)
(An)+
–(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
—
—
—
—
—
—
cpushl
(Ax)
—
9(0/1)
intouch
(Ay)
—
19(1/0)
link.w
Ay,#imm
2(0/1)
—
—
—
—
—
—
—
move.w
CCR,Dx
1(0/0)
—
—
—
—
—
—
—
move.w
<ea>,CCR
1(0/0)
—
—
—
—
—
—
1(0/0)
MCF548x Reference Manual, Rev. 3
3-32
Freescale Semiconductor
Instruction Execution Timing
Table 3-16. Miscellaneous Instruction Execution Times (Continued)
Effective Address
Opcode
<ea>
Rn
(An)
(An)+
–(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
move.w
SR,Dx
1(0/0)
—
—
—
—
—
—
—
move.w
<ea>,SR
4(0/0)
—
—
—
—
—
—
4(0/0)
movec
Ry,Rc
20(0/1)
—
—
—
—
—
—
—
movem.l 1 <ea>,&list
—
n(n/0)
—
—
n(n/0)
—
—
—
movem.l
—
n(0/n)
—
—
n(0/n)
—
—
—
6(0/0)
—
—
—
—
—
—
—
2(0/1)
1(0/1)
—
&list,<ea>
nop
pea
<ea>
pulse
—
1(0/1)
—
—
1(0/1)2
3
1(0/0)
—
—
—
—
—
—
—
stop
#imm
—
—
—
—
—
—
—
6(0/0)4
trap
#imm
—
—
—
—
—
—
—
18(1/2)
tpf
1(0/0)
—
—
—
—
—
—
—
tpf.w
1(0/0)
—
—
—
—
—
—
—
tpf.l
1(0/0)
—
—
—
—
—
—
—
1(1/0)
—
—
—
—
—
—
—
unlk
Ax
wddata.l
<ea>
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
—
wdebug.l
<ea>
—
3(2/0)
—
—
3(2/0)
—
—
—
1
n is the number of registers moved by the MOVEM opcode.
PEA execution times are the same for (d16,PC).
3 PEA execution times are the same for (d8,PC,Xi*SF).
4 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
2
3.7.5
Branch Instruction Execution Timing
Table 3-17 shows general branch instruction timing.
Table 3-17. General Branch Instruction Execution Times
Effective Address
Opcode
<ea>
Rn
(An)
(An)+
–(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
—
—
—
—
—
bra
—
—
—
—
1(0/1)1
bsr
—
—
—
—
1(0/1)1
—
5(0/0)1
jmp
jsr
<ea>
<ea>
rte
rts
—
5(0/0)
—
—
6(0/0)
1(0/0)
1
—
—
—
5(0/1)
—
—
5(0/1)
6(0/1)
1(0/1)1
—
—
15(2/0)
—
—
—
—
—
—
2(1/0)2
—
—
—
—
—
—
9(1/0)3
8(1/0)4
1
Assumes branch acceleration. Depending on the pipeline status, execution times may vary from 1 to 3 cycles.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
3-33
2
If predicted correctly by the hardware return stack.
If mispredicted by the hardware return stack.
4
If not predicted by the hardware return stack.
3
Table 3-18 shows timing for Bcc instructions.
Table 3-18. Bcc Instruction Execution Times
Opcode
Branch Cache
Correctly Predicts
Taken
Prediction Table
Correctly Predicts Taken
Predicted
Correctly as
Not Taken
0(0/0)
1(0/0)
1(0/0)
bcc
3.7.6
Predicted Incorrectly
8(0/0)
EMAC Instruction Execution Times
Table 3-19 specifies instruction execution times associated with the enhanced multiply-accumulate
(EMAC) execute engine.
Table 3-19. EMAC Instruction Execution Times
Effective Address
Opcode
mac.l
<ea>y
Ry,Rx,ACCx
Rn
(An)
(An)+
–(An)
(d16,An)
(d16,PC)
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
xxx.wl
#xxx
1(0/0)
—
—
—
—
—
—
—
1
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)
—
—
—
1(0/0)
—
—
—
—
—
—
—
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)1
—
—
—
<ea>y,ACCx
1(0/0)
—
—
—
—
—
—
1(0/0)
mov.l
ACCy,ACCx
1(0/0)
—
—
—
—
—
—
—
mov.l
<ea>y,MACSR
8(0/0)
—
—
—
—
—
—
8(0/0)
mov.l
<ea>y,MASK
7(0/0)
—
—
—
—
—
—
7(0/0)
mov.l
<ea>y,ACCext01
1(0/0)
—
—
—
—
—
—
1(0/0)
mov.l
<ea>y,ACCext23
1(0/0)
—
—
—
—
—
—
1(0/0)
mov.l
ACCx,<ea>x
1(0/0)2
—
—
—
—
—
—
—
mov.l
MACSR,<ea>x
1(0/0)
—
—
—
—
—
—
—
mov.l
MASK,<ea>x
1(0/0)
—
—
—
—
—
—
—
mov.l
ACCext01,<ea>x
1(0/0)
—
—
—
—
—
—
—
mov.l
ACCext23,<ea>x
1(0/0)
—
—
—
—
—
—
—
msac.l
Ry,Rx,ACCx
1(0/0)
—
—
—
—
—
—
—
—
—
—
mac.l
Ry,Rx,<ea>,Rw,ACCx
mac.w
Ry,Rx,ACCx
mac.w
Ry,Rx,<ea>,Rw,ACCx
mov.l
msac.l
Ry,Rx,<ea>,Rw,ACCx
msac.w
Ry,Rx,ACCx
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)1
1(0/0)
—
—
—
—
—
—
—
—
—
—
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)1
<ea>y,Dx
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
—
—
—
<ea>y,Dx
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
5(1/0)
4(1/0)
4(0/0)
msac.w
Ry,Rx,<ea>,Rw,ACCx
muls.l
muls.w
MCF548x Reference Manual, Rev. 3
3-34
Freescale Semiconductor
Instruction Execution Timing
Table 3-19. EMAC Instruction Execution Times
Effective Address
Opcode
<ea>y
Rn
(An)
(An)+
–(An)
(d16,An)
(d16,PC)
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
xxx.wl
#xxx
mulu.l
<ea>y,Dx
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
—
—
—
mulu.w
<ea>y,Dx
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
5(1/0)
4(1/0)
4(0/0)
1
2
Effective address of (d16,PC) not supported.
Storing the accumulator requires 1 additional clock cycle when saturation is enabled, or fractional rounding is performed
(MACSR[7:4] = 1---, -11-, --11).
Execution times for moving the contents of the ACC, ACCext[01,23], MACSR, or MASK into a
destination location <ea>x in this table represent the best-case scenario when the store is executed and no
load, copy, MAC, or MSAC instructions are in the EMAC execution pipeline. In general, these store
operations require only a single cycle for execution, but if preceded immediately by a load, copy, MAC,
or MSAC instruction, the depth of the EMAC pipeline is exposed and the execution time is 4 cycles.
3.7.7
FPU Instruction Execution Times
Table 3-20 specifies the instruction execution times associated with the FPU execute engine.
Table 3-20. FPU Instruction Execution Times1, 2
Effective Address <ea>
Opcode
Format
FPn
Dn
(An)
(An)+
–(An)
(d16,An)
(d16,PC)
fabs
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
fadd
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
fbcc
<label>
—
—
—
—
—
—
2(0/0) if correct,
9(0/0) if incorrect
fcmp
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
fdiv
<ea>y,FPx
23(0/0) 23(0/0)
23(1/0)
23(1/0) 23(1/0)
23(1/0)
23(1/0)
fint
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
fintrz
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
fmove
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
fmove
FPy,<ea>x
—
2(0/1)
2(0/1)
2(0/1)
2(0/1)
2(0/1)
—
fmove
<ea>y,FP*R
—
6(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
fmove
FP*R,<ea>x
—
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
—
fmovem3
<ea>y,#list
—
—
2n(2n/0)
—
—
2n(2n/0)
2n(2n/0)
fmovem3, 4
#list,<ea>x
—
—
1+2n(0/2n)
—
—
1+2n(0/2n)
—
fmul
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
fneg
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
—
—
—
—
—
—
2(0/0)
—
—
6(4/0)
—
—
6(4/0)
6(4/0)
fnop
frestore
<ea>y
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Table 3-20. FPU Instruction Execution Times1, 2
Effective Address <ea>
Opcode
Format
FPn
Dn
(An)
(An)+
–(An)
(d16,An)
(d16,PC)
—
—
7(0/3)
—
—
7(0/3)
—
fsave
<ea>x
fsqrt
<ea>y,FPx
56(0/0) 56(0/0)
56(1/0)
56(1/0) 56(1/0)
56(1/0)
56(1/0)
fsub
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
ftst
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1
Add 1(1/0) for an external read operand of double-precision format for all instructions except FMOVEM, and
1(0/1) for FMOVE FPy,<ea>x when the destination is double-precision.
2
If the external operand is an integer format (byte, word, or longword), there is a 4-cycle conversion time that
must be added to the basic execution time.
3
For FMOVEM, n refers to the number of registers being moved.
4 If any exceptions are enabled, the execution time for FMOVE FPy,<ea>x increases by 1 cycle. If the BSUN
exception is enabled, the execution time for FBcc increases by one cycle.
3.8
Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. Differences from previous
ColdFire Family processors include the following:
• An instruction restart model for translation (TLB miss) and access faults. This new functionality
extends the existing ColdFire access error fault vector and exception stack frames.
• Use of separate system stack pointers for user and supervisor modes.
Previous ColdFire processors use an instruction restart exception model but require additional software
support to recover from certain access errors.
Exception processing can be defined as the time from the detection of the fault condition until the fetch of
the first handler instruction has been initiated. It consists of the following four major steps:
1. The processor makes an internal copy of the status register (SR) and then enters supervisor mode
by setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an interrupt
exception also clears SR[M] and sets the interrupt priority mask, SR[I] to the level of the current
interrupt request.
2. The processor determines the exception vector number. For all faults except interrupts, the
processor bases this calculation on exception type. For interrupts, the processor performs an
interrupt acknowledge (IACK) bus cycle to obtain the vector number from peripheral. The IACK
cycle is mapped to a special acknowledge address space with the interrupt level encoded in the
address.
The processor saves the current context by creating an exception stack frame on the system stack.
As a result, the exception stack frame is created at a 0-modulo-4 address on top of the system stack
pointed to by the supervisor stack pointer (SSP). As shown in Figure 3-15, the CF4e processor uses
the same fixed-length stack frame as previous ColdFire Versions with additional fault status (FS)
encodings to support the MMU. In some exception types, the program counter (PC) in the
exception stack frame contains the address of the faulting instruction (fault); in others the PC
contains the next instruction to be executed (next). (Note that previous ColdFire processors support
a single stack pointer in the A7 address register.)
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Exception Processing Overview
If the exception is caused by an FPU instruction, the PC contains the address of either the next
floating-point instruction (nextFP) if the exception is pre-instruction, or the faulting instruction
(fault) if the exception is post-instruction.
3. The processor acquires the address of the first instruction of the exception handler. The instruction
address is obtained by fetching a value from the exception table at the address in the vector base
register. The index into the table is calculated as 4 x vector_number. When the index value is
generated, the vector table contents determine the address of the first instruction of the desired
handler. After the fetch of the first opcode of the handler is initiated, exception processing
terminates and normal instruction processing continues in the handler.
The vector base register described in the ColdFire Programmers Reference Manual, holds the base address
of the exception vector table in memory. The displacement of an exception vector is added to the value in
this register to access the vector table. VBR[19–0] are not implemented and are assumed to be zero, forcing
the vector table to be aligned on a 0-modulo-1-Mbyte boundary.
ColdFire processors support a 1,024-byte vector table aligned on any 0-modulo-1 Mbyte address
boundary; see Table 3-21. The table contains 256 exception vectors, the first 64 of which are defined by
Freescale. The rest are user-defined interrupt vectors.
Table 3-21. Exception Vector Assignments
Vector Numbers Vector Offset (Hex)
Stacked Program Counter1
Assignment
0
000
—
Initial supervisor stack pointer
1
004
—
Initial program counter
2
008
Fault
Access error
3
00C
Fault
Address error
4
010
Fault
Illegal instruction
5
014
Fault
Divide by zero
6–7
018–01C
—
8
020
Fault
Privilege violation
9
024
Next
Trace
10
028
Fault
Unimplemented line-a opcode
11
02C
Fault
Unimplemented line-f opcode
12
030
Next
Non-PC breakpoint debug interrupt
13
034
Next
PC breakpoint debug interrupt
14
038
Fault
Format error
15
03C
Next
Uninitialized interrupt
16–23
040–05C
—
24
060
Next
Spurious interrupt
25–31
064–07C
Next
Level 1–7 autovectored interrupts
32–47
080–0BC
Next
Trap #0–15 instructions
Reserved
Reserved
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Table 3-21. Exception Vector Assignments (Continued)
Vector Numbers Vector Offset (Hex)
1
Stacked Program Counter1
Assignment
48
0C0
Fault
Floating-point branch on unordered
condition
49
0C4
NextFP or Fault
Floating-point inexact result
50
0C8
NextFP
Floating-point divide-by-zero
51
0CC
NextFP or Fault
Floating-point underflow
52
0D0
NextFP or Fault
Floating-point operand error
53
0D4
NextFP or Fault
Floating-point overflow
54
0D8
NextFP or Fault
Floating-point input not-a-number (NAN)
55
0DC
NextFP or Fault
Floating-point input denormalized
number
56–60
0E0–0F0
—
61
0F4
Fault
62–63
0F8–0FC
—
64–255
100–3FC
Next
Reserved
Unsupported instruction
Reserved
User-defined interrupts
‘Fault’ refers to the PC of the faulting instruction. ‘Next’ refers to the PC of the instruction immediately after the
faulting instruction. NextFP’ refers to the PC of the next floating-point instruction.
ColdFire processors inhibit sampling for interrupts during the first instruction of all exception handlers.
This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level
in the SR.
3.8.1
Exception Stack Frame Definition
The first longword of the exception stack frame, Figure 3-15, holds the 16-bit format/vector word (F/V)
and 16-bit status register. The second holds the 32-bit program counter address of the faulted or interrupted
instruction.
31
A7→
+ 0x04
28
FORMAT
27
26
25
FS[3–2]
18
VEC
17
16
15
FS[1–0]
0
STATUS REGISTER
PROGRAM COUNTER [31:0]
Figure 3-15. Exception Stack Frame
Table 3-22 describes F/V fields. FS encodings added to support the CF4e MMU are noted.
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Exception Processing Overview
Table 3-22. Format/Vector Word
1
Bits
Name
Description
31–28
FORMAT
Format field. Written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format.
FORMAT records any longword stack pointer misalignment when the exception occurred.
27–26
FS[3:2]
25–18
VEC
17–16
FS[1:0]
A7 at Exception
Bits 1–0
A7 at First Instruction
of Handler
Format
00
Original A7–8
0100
01
Original A7–9
0101
10
Original A7–10
0110
11
Original A7–11
0111
Fault status. Defined for access and address errors and for interrupted debug service routines.
0000 Not an access or address error nor an interrupted debug service routine
0001 Reserved
0010 Interrupt during a debug service routine for faults other than access errors. 1 [
0011 Reserved
0100 Error (for example, protection fault) on instruction fetch
0101 TLB miss on opword of instruction fetch (New in CF4e)
0110 TLB miss on extension word of instruction fetch (New in CF4e)
0111 IFP access error while executing in emulator mode (New in CF4e)
1000 Error on data write
1001 Error on attempted write to write-protected space
1010 TLB miss on data write (New in CF4e)
1011 Reserved
1100 Error on data read
1101 Attempted read, read-modify-write of protected space (New in CF4e)
1110 TLB miss on data read, or read-modify-write (New in CF4e)
1111 OEP access error while executing in emulator mode (New in CF4e)
Vector number. Defines the exception type. It is calculated by the processor for internal faults and is
supplied by the peripheral for interrupts. See Table 3-21.
See bits 27–26.
This generally refers to taking an I/O interrupt during a debug service routine but also applies to other fault types. If an access
error occurs during a debug service routine, FS is set to 0111 if it is due to an instruction fetch or to 1111 for a data access. This
applies only to access errors with the MMU present. If an access error occurs without an MMU, FS is set to 0010.
3.8.2
Processor Exceptions
Table 3-23 describes CF4e exceptions. Note that if a ColdFire processor encounters any fault while
processing another fault, it immediately halts execution with a catastrophic fault-on-fault condition. A
reset is required to force the processor to exit this halted state.
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Table 3-23. Processor Exceptions
Type
Description
Access error
If the MMU is disabled, access errors are reported only in conjunction with an attempted store to
write-protected memory. Thus, access errors associated with instruction fetch or operand read accesses are
not possible. The Version 4 processor, unlike the Version 2 and 3 processors, updates the condition code
register if a write-protect error occurs during a CLR or MOV3Q operation to memory.
accesses that fault (that is, terminated with a transfer error acknowledge) generate an access error
exception. MMU TLB misses and access violations use the same fault. If the MMU is enabled, all TLB misses
and protection violations generate an access error exception. To determine if a fault is due to a TLB miss or
another type of access error, new FS encodings (described in Table 3-22) signal TLB misses on the following:
• Instruction fetch
• Instruction extension fetch
• Data read
• Data write
Address error
An address error is caused by an attempted execution transferring control to an odd instruction address (that
is, if bit 0 of the target address is set), an attempted use of a word-sized index register (Xi.w) or by an
attempted execution of an instruction with a full-format indexed addressing mode.
If an address error occurs on a JSR instruction, the Version 4 processor first pushes the return address onto
the stack and then calculates the target address.
On Version 2 and 3 processors, the target address is calculated then the return address is pushed on stack.
If an address error occurs on an RTS instruction, the Version 4 processor preserves the original return PC
and writes the exception stack frame above this value. On Version 2 and 3 processors, the faulting return PC
is overwritten by the address error stack frame.
Illegal
instruction
The scope of illegal instruction detection is implementation-specific across the generations of ColdFire cores.
For the CF4e core, the complete 16-bit opcode is decoded and this exception is generated if execution of an
unsupported instruction is attempted. Additionally, attempting to execute an illegal line A or line F opcode
generates unique exception types: vectors 10 and 11, respectively. ColdFire processors do not provide illegal
instruction detection on extension words of any instruction, including MOVEC. Attempting to execute an
instruction with an illegal extension word causes undefined results.
Divide-by-zero
Privilege
violation
Attempting to divide by zero causes an exception (vector 5, offset = 0x014).
Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire
Programmer’s Reference Manual lists supervisor- and user-mode instructions.
Trace exception Trace mode, which allows instruction-by-instruction tracing, is enabled by setting SR[T].
If SR[T] is set, instruction completion (for all but the STOP instruction) signals a trace exception.The STOP
instruction has the following effects:
1 The instruction before the STOP executes and then generates a trace exception. In the exception stack
frame, the PC points to the STOP opcode.
2 When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate
operand from the instruction.
3 The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after STOP, and the SR reflects the value loaded in the previous step.
If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets
SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points
to the instruction after STOP, and the SR reflects the value loaded in step 2. Note that because ColdFire
processors do not support hardware stacking of multiple exceptions, it is the responsibility of the operating
system to check for trace mode after processing other exception types. For example, when a TRAP
instruction executes in trace mode, the processor initiates the TRAP exception and passes control to the
corresponding handler. If the system requires a trace exception, the TRAP exception handler must check for
this condition (SR[15] in the exception stack frame set) and pass control to the trace handler before returning
from the original exception.
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Exception Processing Overview
Table 3-23. Processor Exceptions (Continued)
Type
Description
Unimplemented A line-a opcode results when bits 15–12 of the opword are 1010. This exception is generated by the
line-a opcode attempted execution of an undefined line-a opcode.
Unimplemented A line-f opcode results when bits 15–12 of the opword are 1111. This exception is generated under the
line-f opcode following conditions:
• When attempting to execute an undefined line-f opcode.
• When attempting to execute an FPU instruction when the FPU has been disabled in the CACR.
Debug interrupt The debug interrupt exception is caused by a hardware breakpoint register trigger. Rather than generating
an IACK cycle, the processor internally calculates the vector number (12 or 13, depending on the type of
breakpoint trigger). Additionally, SR[M,I] are unaffected by the interrupt.
Separate exception vectors are provided for PC breakpoints and for address/data breakpoints. In the case of
a two-level trigger, the last breakpoint determines the vector. The two unique entries occur when a PC
breakpoint generates the 0x034 vector. In case of a two-level trigger, the last breakpoint event determines
the vector. See Chapter 8, “Debug Support,” for more information.
Format error
When an RTE instruction executes, the processor first examines the 4-bit format field to validate the frame
type. For a ColdFire processor, attempted execution of an RTE where the format is not equal to {4, 5, 6, 7}
generates a format error. The exception stack frame for the format error is created without disturbing the
original exception frame and the stacked PC points to RTE. The selection of the format value provides limited
debug support for porting code from M68000 applications. On M68000 Family processors, the SR was at the
top of the stack. Bit 30 of the longword addressed by the system stack pointer is typically zero. Attempting an
RTE using this old format generates a format error on a ColdFire processor. If the format field defines a valid
type, the processor does the following:
1 Reloads the SR operand.
2 Fetches the second longword operand.
3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the first
longword fetch.
4 Transfers control to the instruction address defined by the second longword operand in the stack frame.
When the processor executes a FRESTORE instruction, if the restored FPU state frame contains a
non-supported value, execution is aborted and a format error exception is generated.
Trap
Executing a TRAP instruction always forces an exception and is useful for implementing system calls. The
trap instruction may be used to change from user to supervisor mode.
Interrupt
exception
Please refer to Section Chapter 13, “Interrupt Controller.”
Reset exception Asserting the reset input signal (RSTI) causes a reset exception, which has the highest exception priority and
provides for system initialization and recovery from catastrophic failure. When assertion of RSTI is
recognized, current processing is aborted and cannot be recovered. The reset exception places the
processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T]. It clears SR[M] and
sets SR[I] to the highest level (0b111, priority level 7). Next, VBR is cleared. Configuration registers
controlling operation of all processor-local memories are invalidated, disabling the memories.
Note: Implementation-specific supervisor registers are also affected at reset.
After RSTI is negated, the processor waits 16 cycles before beginning the reset exception process. During
this time, certain events are sampled, including the assertion of the debug breakpoint signal. If the processor
is not halted, it initiates the reset exception by performing two longword read bus cycles. The longword at
address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC. After the initial
instruction is fetched from memory, program execution begins at the address in the PC. If an access error or
address error occurs before the first instruction executes, the processor enters a fault-on-fault halted state.
Unsupported
instruction
exception
If the CF4e attempts to execute a valid instruction but the required optional hardware module is not present
in the OEP, a non-supported instruction exception is generated (vector 0x61). Control is then passed to an
exception handler that can then process the opcode as required by the system.
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3.9
Precise Faults
To support a demand-paged virtual memory environment, all memory references require precise,
recoverable faults. The ColdFire instruction restart mechanism ensures that a faulted instruction restarts
from the beginning of execution; that is, no internal state information is saved when an exception occurs
and none is restored when the handler ends. Given the PC address defined in the exception stack frame,
the processor reestablishes program execution by transferring control to the given location as part of the
RTE (return from exception) instruction.
The instruction restart recovery model requires program-visible register changes made during execution
to be undone if that instruction subsequently faults.
The Version 4 (and later) OEP structure naturally supports this concept for most instructions;
program-visible registers are updated only in the final OEP stage when fault collection is complete. If any
type of exception occurs, pending register updates are discarded.
For V4 cores and later, most single-cycle instructions already support precise faults and instruction restart.
Some complex instructions do not. Consider the following memory-to-memory move:
mov.l
(Ay)+,(Ax)+
# copy 4 bytes from source to destination
On a Version 4 processor, this instruction takes one cycle to read the source operand (Ay) and one to write
the data into Ax. Both the source and destination address pointers are updated as part of execution.
Table 3-24 lists the operations performed in execute stage (EX).
Table 3-24. OEP EX Cycle Operations
EX Cycle
Operations
1
Read source operand from memory @ (Ay), update Ay, new Ay = old Ay + 4
2
Write operand into destination memory @ (Ax), update Ax, new Ax = old Ax + 4, update CCR
A fault detected with the destination memory write is reported during the second cycle. At this point,
operations performed in the first cycle are complete, so if the destination write takes any type of access
error, Ay is updated. After the access error handler executes and the faulting instruction restarts, the
processor’s operation is incorrect because the source address register has an incorrect (post-incremented)
value.
To recover the original state of the programming model for all instructions, the CF4e CPU adds the needed
hardware to support full register recovery. This hardware allows program-visible registers to be restored
to their original state for multi-cycle instructions so that the instruction restart mechanism is supported.
Memory-to-memory moves and move multiple loads are representative of the complex instructions
needing the special recovery support.
The other major pipeline change affects the IFP. The IFP and OEP are decoupled by a FIFO instruction
buffer. In the V4 IFP, each buffer entry includes 48 bits of instruction data fetched from memory and 64
bits of early decode and branch prediction information. This datapath is expanded slightly to include IFP
fault status information. Thus, every IFP access can be tagged in case an instruction fetch terminates with
an error acknowledge.
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Precise Faults
NOTE
For access errors signaled on instruction prefetches, an access error
exception is generated only if instruction execution is attempted. If an
instruction fetch access error exception is generated and the FS field
indicates the fault occurred on an extension word, it may be necessary for
the exception PC to be rounded-up to the next page address to determine the
faulting instruction fetch address.
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Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
This chapter describes the functionality, microarchitecture, and performance of the enhanced
multiply-accumulate (EMAC) unit in the ColdFire family of processors.
4.1
Introduction
The MAC design provides a set of DSP operations which can be used to improve the performance of
embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture.
The MAC provides functionality in three related areas:
• Signed and unsigned integer multiplies
• Multiply-accumulate operations supporting signed and unsigned integer operands, as well as
signed, fixed-point, fractional operands
• Miscellaneous register operations
The ColdFire family supports two MAC implementations with different performance levels and
capabilities. The original MAC uses a three-stage execution pipeline optimized for 16-bit operands and
featuring a 16 × 16 multiply array with a single 32-bit accumulator. The EMAC features a four-stage
pipeline optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit
accumulators.
The first ColdFire MAC supported signed and unsigned integer operands and was optimized for 16 × 16
operations, such as those found in a variety of applications, including servo control and image
compression. As ColdFire-based systems proliferated, the desire for more precision on input operands
increased. The result was an improved ColdFire MAC with user-programmable control to optionally
enable use of fractional input operands.
EMAC improvements target three primary areas:
• Improved performance of 32 × 32 multiply operations.
• Addition of three more accumulators to minimize EMAC pipeline stalls caused by exchanges
between the accumulator and the pipeline’s general-purpose registers.
• A 48-bit accumulation data path to allow the use of a 40-bit product plus the addition of 8 extension
bits to increase the dynamic number range when implementing signal processing algorithms.
The three areas of functionality are addressed in detail in following sections. The logic required to support
this functionality is contained in a MAC module, as shown in Figure 4-1.
Operand Y
Operand X
X
Shift 0,1,-1
+/-
Accumulator(s)
Figure 4-1. Multiply-Accumulate Functionality Diagram
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4.1.1
MAC Overview
The MAC is an extension of the basic multiplier found in most microprocessors. It is typically
implemented in hardware within an architecture and supports rapid execution of signal processing
algorithms in fewer cycles than comparable non-MAC architectures. For example, small digital filters can
tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as
orthogonal transforms may have more demanding speed requirements beyond the scope of any processor
architecture, and may require full DSP implementation.
To strike a balance between speed, size, and functionality, the ColdFire MAC is optimized for a small set
of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is
optimized for single-cycle pipelined operations with a possible accumulation after product generation.
This functionality is common in many signal processing applications. The ColdFire core architecture also
has been modified to allow an operand to be fetched in parallel with a multiply, increasing overall
performance for certain DSP operations.
Consider a typical filtering operation where the filter is defined,11 as in Figure 4-2.
N–1
y(i) =
N–1
∑ a ( k )y ( i – k ) + ∑ b ( k )x ( i – k )
k=1
k=0
Figure 4-2. Infinite Impulse Response (IIR) Filter
Here, the output y(i) is determined by past output values and past input values. This is the general form of
an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting
coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies
and product summing. To show this point, reduce the above equation to a simple, four-tap FIR filter, shown
in Figure 4-3, in which the accumulated sum is a sum of past data values and coefficients.
3
y(i) =
∑ b ( k )x ( i – k ) = b ( 0 )x ( i ) + b ( 1 )x ( i – 1 ) + b ( 2 )x ( i – 2 ) + b ( 3 )x ( i – 3 )
k=0
Figure 4-3. Four-Tap FIR Filter
4.1.2
General Operation
The MAC speeds execution of ColdFire integer multiply instructions (MULS and MULU) and provides
additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC,
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Introduction
execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early
termination that the OEP normally uses if no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed
by the addition or subtraction of the product to or from the value in an accumulator. Optionally, the product
may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation
arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions.
Multiply-accumulate operations support 16- or 32-bit input operands of the following formats:
• Signed integers
• Unsigned integers
• Signed, fixed-point, fractional numbers
The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and
longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the
destination accumulator. For fractional operands, the entire 64-bit product is calculated and either
truncated or rounded to the most-significant 40-bit result using the round-to-nearest (even) method before
it is combined with the destination accumulator.
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for
signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined
with the 48-bit destination accumulator.
Figure 4-4 and Figure 4-5 show relative alignment of input operands, the full 64-bit product, the resulting
40-bit product used for accumulation, and 48-bit accumulator formats.
X
Product
Extended Product
OperandY
32
OperandX
32
40
23
8
“0”
40
+
Accumulator
8
Extension Byte Upper [7:0]
8
40
Accumulator [31:0]
Extension Byte Lower [7:0]
Figure 4-4. Fractional Alignment
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4-3
X
Product
Extended Product
OperandY
32
OperandX
32
8
32
8
8
32
8
8
32
24
+
Accumulator
Extension Byte Upper [7:0]
Accumulator [31:0]
Extension Byte Lower [7:0]
Figure 4-5. Signed and Unsigned Integer Alignment
Thus, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that each 48-bit
accumulator is the concatenation of 16-bit accumulator extension register (ACCextn) contents and 32-bit
ACCn contents, the specific definitions are as follows:
if MACSR[6:5] == 00/* signed integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
if MACSR[6:5] == -1/* signed fractional mode */
Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]}
if MACSR[6:5] == 10/* unsigned integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
The four accumulators are represented as an array, ACCn, where n selects the register.
Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC instructions
have an effective issue rate of 1 cycle, regardless of input operand size or type.
All arithmetic operations use register-based input operands, and summed values are stored internally in an
accumulator. Thus, an additional move instruction is needed to store data in a general-purpose register.
One new feature found in EMAC instructions is the ability to choose the upper or lower word of a register
as a 16-bit input operand. This is useful in filtering operations if one data register is loaded with the input
data and another is loaded with the coefficient. Two 16-bit multiply accumulates can be performed without
fetching additional operands between instructions by alternating the word choice during the calculations.
The EMAC has four accumulator registers versus the MAC’s one accumulator. The additional registers
improve the performance of some algorithms by minimizing pipeline stalls needed to store an accumulator
value back to general-purpose registers. Many algorithms require multiple calculations on a given data set.
By applying different accumulators to these calculations, it is often possible to store one accumulator
without any stalls while performing operations involving a different destination accumulator.
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Memory Map/Register Definition
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP
engines. New and existing ColdFire instructions can accommodate these requirements. A MOVEM
instruction can move large blocks of data efficiently by generating line-sized burst transfers. The ability to
simultaneously load an operand from memory into a register and execute a MAC instruction makes some
DSP operations such as filtering and convolution more manageable.
The programming model includes a 16-bit mask register (MASK), which can optionally be used to
generate an operand address during MAC + MOVE instructions. The application of this register with
auto-increment addressing mode supports efficient implementation of circular data queues for memory
operands.
The additional MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.
4.2
Memory Map/Register Definition
The EMAC provides the following program-visible registers:
• Four 32-bit accumulators (ACCn = ACC0, ACC1, ACC2, and ACC3)
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values for load
and store operations (ACCext01 and ACCext23)
• One 16-bit mask register (MASK)
• One 32-bit MAC status register (MACSR) including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0–PAV3)
These registers are shown in Figure 4-6.
31
0
MACSR
ACC0
ACC1
ACC2
ACC3
ACCext01
ACCext23
MASK
MAC status register
MAC accumulator 0
MAC accumulator 1
MAC accumulator 2
MAC accumulator 3
Extensions for ACC0 and ACC1
Extensions for ACC2 and ACC3
MAC mask register
Figure 4-6. EMAC Register Set
4.2.1
MAC Status Register (MACSR)
MACSR functionality is organized as follows:
• MACSR[11–8] contains one product/accumulation overflow flag per accumulator.
• MACSR[7–4] defines the operating configuration of the MAC unit.
• MACSR[3–0] contains indicator flags from the last MAC instruction execution.
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R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
OMC
S/U
F/I
R/T
N
Z
V
EV
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
PAVx
W
Reset
0
0
0
0
Reg
Addr
Figure 4-7. MAC Status Register (MACSR)
Table 4-1 describes MACSR fields.
Table 4-1. MACSR Field Descriptions
Bits
Name
Description
31–12
—
11–8
PAVx
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past
MAC or MSAC instructions generated an overflow during product calculation or the 48-bit
accumulation. When a MAC or MSAC instruction is executed, the PAVx flag associated with the
destination accumulator is used to form the general overflow flag, MACSR[V]. Once set, each flag
remains set until V is cleared by a MOV.L , MACSR instruction or the accumulator is loaded directly.
7
OMC
Operational mode field: Overflow/saturation mode. Used to enable or disable saturation mode on
overflow. If set, the accumulator is set to the appropriate constant on any operation which overflows
the accumulator. Once saturated, the accumulator remains unaffected by any other MAC or MSAC
instructions until either the overflow bit is cleared or the accumulator is directly loaded.
6
S/U
Operational mode field: Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the
accumulator value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive
(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on both the instruction
and the value of the product that overflowed.
1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest
value (0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.
In fractional mode:
S/U controls rounding while storing an accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose
register as a 32-bit value.
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when it
is moved to a general-purpose register. See Section 4.2.1.1.1, “Rounding.” The resulting 16-bit
value is stored in the lower word of the destination register. The upper word is zero-filled. The
accumulator value is not affected by this rounding procedure.
Reserved, should be cleared.
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Memory Map/Register Definition
Table 4-1. MACSR Field Descriptions (Continued)
Bits
Name
Description
5
F/I
Operational mode field: Fractional/integer mode Determines whether input operands are treated as
fractions or integers.
0 Integers can be represented in either signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from
-1 to 1- 2-15 for 16-bit fractions and -1 to 1 - 2-31 for 32-bit fractions. See Section 4.3.2, “Data
Representation."
4
R/T
Operational mode field: Round/truncate mode. Controls the rounding procedure for MOV.L
ACCx,Rx, or MSAC.L instructions when operating in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator. Additionally,
when a store accumulator instruction is executed (MOV.L ACCx,Rx), the 8 lsbs of the 48-bit
accumulator logic are simply truncated.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the
nearest 40-bit value. If the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to
the nearest even (lsb = 0) value.See Section 4.2.1.1.1, “Rounding.” Additionally, when a store
accumulator instruction is executed (MOV.L ACCx,Rx), the lsbs of the 48-bit accumulator logic are
used to round the resulting 16- or 32-bit value. If MACSR[S/U] = 0 and MACSR[R/T] = 1, the
low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] = 1, the low-order
24 bits are used to round the resulting 16-bit fraction.
3
N
Negative flag. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC,
and load operations; it is not affected by MULS and MULU instructions.
2
Z
Zero flag. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC,
and load operations; it is not affected by MULS and MULU instructions.
1
V
Overflow flag. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the
result cannot be represented in the limited width of the EMAC. V is set only if a product overflow
occurs or the accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC
operation and uses the appropriate PAVx flag in the next-state V evaluation.
0
EV
Extension overflow flag. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in
integer mode or the 40 lsbs in fractional mode of the destination accumulator. However, the result is
still accurately represented in the combined 48-bit accumulator structure. Although an overflow has
occurred, the correct result, sign, and magnitude are contained in the 48-bit accumulator.
Subsequent MAC or MSAC operations may return the accumulator to a valid 32/40-bit result.
Table 4-2 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
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Table 4-2. Summary of S/U, F/I, and R/T Control Bits
4.2.1.1
S/U
F/I
R/T
Operational Modes
0
0
x
Signed, integer
0
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
0
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores
1
0
x
Unsigned, integer
1
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
1
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Fractional Operation Mode
This section describes behavior when the fractional mode is used (MACSR[F/I] is set).
4.2.1.1.1
Rounding
When the processor is in fractional mode, there are two operations during which rounding can occur.
• Execution of a store accumulator instruction (MOV.L ACCx,Rx). The lsbs of the 48-bit
accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared,
the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] is set, the
low-order 24 bits are used to round the resulting 16-bit fraction.
• Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero,
multiplying two 32-bit numbers creates a 64-bit product that is truncated to the upper 40 bits;
otherwise, it is rounded using round-to-nearest (even) method.
To understand the round-to-nearest-even method, consider the following example involving the rounding
of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest
16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L.
• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.
• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).
• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on
the lsb of R0.U, so the result is always even (lsb = 0).
— If the lsb of R0.U = 1 and R0.L = 0x8000, the number is rounded up.
— If the lsb of R0.U = 0 and R0.L =0x8000, the number is rounded down.
This method minimizes rounding bias and creates as statistically correct an answer as possible.
The rounding algorithm is summarized in the following pseudocode:
if R0.L < 0x8000
then Result = R0.U
else if R0.L > 0x8000
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Memory Map/Register Definition
then Result = R0.U + 1
else if lsb of R0.U = 0
/* R0.L = 0x8000 */
then Result = R0.U
else Result = R0.U + 1
The round-to-nearest-even technique is also known as convergent rounding.
4.2.1.1.2
Saving and Restoring the EMAC Programming Model
The presence of rounding logic in the output datapath of the EMAC requires that special care be taken
during the EMAC’s save/restore process. In particular, any result rounding modes must be disabled during
the save/restore process so the exact bit-wise contents of the EMAC registers are accessed. Consider the
following memory structure containing the EMAC programming model:
struct
macState {
int
int
int
int
int
int
int
int
acc0;
acc1;
acc2;
acc3;
accext01;
accext02;
mask;
macsr;
} macState;
The following assembly language routine shows the proper sequence for a correct EMAC state save. This
code assumes all Dn and An registers are available for use and the memory location of the state save is
defined by A7.
EMAC_state_save:
move.l macsr,d7
clr.l
d0
move.l d0,macsr
move.l acc0,d0
move.l acc1,d1
move.l acc2,d2
move.l acc3,d3
move.l accext01,d4
move.l accext23,d5
move.l mask,d6
movem.l #0x00ff,(a7)
;
;
;
;
save the macsr
zero the register to ...
disable rounding in the macsr
save the accumulators
; save the accumulator extensions
; save the address mask
; move the state to memory
The following code performs the EMAC state restore:
EMAC_state_restore:
movem.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
(a7),#0x00ff
#0,macsr
d0,acc0
d1,acc1
d2,acc2
d3,acc3
d4,accext01
d5,accext23
; restore the state from memory
; disable rounding in the macsr
; restore the accumulators
; restore the accumulator extensions
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move.l
move.l
d6,mask
d7,macsr
; restore the address mask
; restore the macsr
By executing this type of sequence, the exact state of the EMAC programming model can be correctly
saved and restored.
4.2.1.1.3
MULS/MULU
MULS and MULU are unaffected by fractional mode operation; operands are still assumed to be integers.
4.2.1.1.4
Scale Factor in MAC or MSAC Instructions
The scale factor is ignored while the MAC is in fractional mode.
4.2.2
Mask Register (MASK)
The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved
with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source
operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.
This register performs a simple AND with the operand address for MAC instructions. That is, the
processor calculates the normal operand address and, if enabled, that address is then ANDed with
{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand
address can be constrained to a certain memory region. This is used primarily to implement circular queues
in conjunction with the (An)+ addressing mode.
This feature minimizes the addressing support required for filtering, convolution, or any routine that
implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can
optionally be included in all memory effective address calculations. The syntax is as follows:
MAC.sz
Ry,RxSF,<ea>y&,Rw
The & operator enables the use of MASK and causes bit 5 of the extension word to be set. The exact
algorithm for the use of MASK is as follows:
if extension word, bit [5] = 1, the MASK bit, then
if <ea> = (An)
oa = An & {0xFFFF, MASK}
if <ea> = (An)+
oa = An
An = (An + 4) & {0xFFFF, MASK}
if <ea> =-(An)
oa = (An - 4) & {0xFFFF, MASK}
An = (An - 4) & {0xFFFF, MASK}
if <ea> = (d16,An)
oa = (An + se_d16) & {0xFFFF0x, MASK}
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For
auto-addressing modes of post-increment and pre-decrement, the calculation of the updated An value is
also shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue
implementations.
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EMAC Instruction Set Summary
4.3
EMAC Instruction Set Summary
Table 4-3 summarizes EMAC unit instructions.
Table 4-3. EMAC Instruction Summary
Command
Mnemonic
Description
Multiply Signed
MULS <ea>y,Dx
Multiplies two signed operands yielding a signed result
Multiply Unsigned
MULU <ea>y,Dx
Multiplies two unsigned operands yielding an unsigned result
Multiply Accumulate
MAC Ry,RxSF,ACCx
MSAC Ry,RxSF,ACCx
Multiplies two operands and adds/subtracts the product to/from an
accumulator
Multiply Accumulate
with Load
MAC Ry,Rx,<ea>y,Rw,ACCx
Multiplies two operands and combines the product to an
MSAC Ry,Rx,<ea>y,Rw,ACCx accumulator while loading a register with the memory operand
Load Accumulator
MOV.L {Ry,#imm},ACCx
Loads an accumulator with a 32-bit operand
Store Accumulator
MOV.L ACCx,Rx
Writes the contents of an accumulator to a CPU register
Copy Accumulator
MOV.L ACCy,ACCx
Copies a 48-bit accumulator
Load MACSR
MOV.L {Ry,#imm},MACSR
Writes a value to MACSR
Store MACSR
MOV.L MACSR,Rx
Write the contents of MACSR to a CPU register
Store MACSR to CCR
MOV.L MACSR,CCR
Write the contents of MACSR to the CCR
Load MAC Mask Reg
MOV.L {Ry,#imm},MASK
Writes a value to the MASK register
Store MAC Mask Reg
MOV.L MASK,Rx
Writes the contents of the MASK to a CPU register
Load AccExtensions01
MOV.L {Ry,#imm},ACCext01
Loads the accumulator 0,1 extension bytes with a 32-bit operand
Load AccExtensions23
MOV.L {Ry,#imm},ACCext23
Loads the accumulator 2,3 extension bytes with a 32-bit operand
Store AccExtensions01 MOV.L ACCext01,Rx
Writes the contents of accumulator 0,1 extension bytes into a CPU
register
Store AccExtensions23 MOV.L ACCext23,Rx
Writes the contents of accumulator 2,3 extension bytes into a CPU
register
4.3.1
EMAC Instruction Execution Timing
The instruction execution times for the EMAC can be found in Section 3.7, “Instruction Execution
Timing.”
The ColdFire family supports two multiply-accumulate implementations that provide different levels of
performance and capability for differing silicon costs. The EMAC features a four-stage execution pipeline,
optimized for 32-bit operands with a fully-pipelined 32 × 32 multiply array and four 48-bit accumulators.
The EMAC execution pipeline overlaps the AGEX stage of the OEP; that is, the first stage of the EMAC
pipeline is the last stage of the basic OEP. EMAC units are designed for sustained, fully-pipelined
operation on accumulator load, copy, and multiply-accumulate instructions. However, instructions that
store contents of the multiply-accumulate programming model can generate OEP stalls that expose the
EMAC execution pipeline depth, as in the following:
mac.w
Ry, Rx, Acc0
move.l
Acc0, Rz
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The mov.l instruction that stores the accumulator to an integer register (Rz) stalls until the program-visible
copy of the accumulator is available. Figure 4-8 shows EMAC timing.
Three-cycle
regBusy stall
mac
DSOC
mov
mov
AGEX
mac
mov
EMAC EX1
mac
mov
mac
EMAC EX2
mac
EMAC EX3
mac
EMAC EX4
Accumulator 0
new
old
Figure 4-8. EMAC-Specific OEP Sequence Stall
In Figure 4-8, the OEP stalls the store-accumulator instruction for 3 cycles: the depth of the EMAC
pipeline minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle,
the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is
performed, the just-updated accumulator 0 value is available.
As with change or use stalls between accumulators and general-purpose registers, introducing intervening
instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC
instruction stalls. In fact, a major benefit of the EMAC is the addition of three accumulators to minimize
stalls caused by exchanges between the accumulator(s) and the general-purpose registers.
4.3.2
Data Representation
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand
type:
• Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2(N-1)
< operand < 2(N-1) - 1. The binary point is right of the lsb.
• Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N - 1. The
binary point is right of the lsb.
• Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining
bits signify the first N-1 bits after the binary point. Given an N-bit number, aN-1aN-2aN-3... a2a1a0,
its value is given by the equation in Figure 4-9.
N–2
value = – ( 1 ⋅ a N – 1 ) +
∑
2
(i + 1 – N)
⋅ ai
i=0
Figure 4-9. Two’s Complement, Signed Fractional Equation
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EMAC Instruction Set Summary
This format can represent numbers in the range -1 < operand < 1 - 2(N-1).
For words and longwords, the largest negative number that can be represented is -1, whose internal
representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2-15);
the most positive longword is 0x7FFF_FFFF or (1 - 2-31).
4.3.3
EMAC Opcodes
EMAC opcodes are described in the ColdFire Programmer’s Reference Manual. Note the following:
• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that
involves the product and the accumulator.
• The overflow (V) flag is handled differently. It is set if the complete product cannot be represented
as a 40-bit value (this applies to 32 × 32 integer operations only) or if the combination of the
product with an accumulator cannot be represented in the given number of bits. The EMAC design
includes an additional product/accumulation overflow bit for each accumulator that are treated as
sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction. See
Section 4.2.1, “MAC Status Register (MACSR).”
• For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator) and
MSAC (multiply and subtract from accumulator) instructions does not include a reference to the
single accumulator. For the EMAC, it is expected that assemblers support this syntax and that no
explicit reference to an accumulator is interpreted as a reference to ACC0. These assemblers would
also support syntaxes where the destination accumulator is explicitly defined.
• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1
indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is
added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the
EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because
a product can overflow, the following guidelines are implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless the
product is zero. For signed, longword operations, the sign bit is shifted into the product unless
an overflow occurs or the product is zero, in which case a zero is shifted in.
— For all left shifts, a zero is inserted into the lsb position.
The following pseudocode explains basic MAC or MSAC instruction functionality. This example is
presented as a case statement covering the three basic operating modes with signed integers, unsigned
integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {},
indicates a concatenation operation.
switch (MACSR[6:5])
/* MACSR[S/U, F/I] */
{
case 0:
/* signed integers */
if (MACSR.OMC == 0 || MACSR.PAVx == 0)
then {
MACSR.PAVx = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}
else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}
if (U/Lx == 1)
then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}
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}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xfff
f_ff_1))
then {
/* product overflow */
MACSR.PAVx = 1
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then if (product[63] == 1)
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
if (product[63] == 1)
then result[47:0] = 0xffff_8000_0000
else result[47:0] = 0x0000_7fff_ffff
}
/* sign-extend to 48 bits before performing any scaling */
product[47:40] = {8{product[39]}}
/* sign-extend */
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
product[40:0] = {product[39:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
product[39:0] = {product[39], product[39:1]}
break;
}
if (MACSR.PAVx == 0)
then {if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[47:0]
else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVx = 1
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EMAC Instruction Set Summary
MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[47] == 1)
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1))
then MACSR.EV = 0
else MACSR.EV = 1
break;
case 1,3:
/* signed fractionals */
if (MACSR.OMC == 0 || MACSR.PAVx == 0)
then {
MACSR.PAVx = 0
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {Ry[31:16], 0x0000}
else operandY[31:0] = {Ry[15:0], 0x0000}
if (U/Lx == 1)
then operandX[31:0] = {Rx[31:16], 0x0000}
else operandX[31:0] = {Rx[15:0], 0x0000}
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
/* perform the multiply */
product[63:0] = (operandY[31:0] * operandX[31:0]) << 1
/* check for product rounding */
if (MACSR.R/T == 1)
then { /* perform convergent rounding */
if (product[23:0] > 0x80_0000)
then product[63:24] = product[63:24] + 1
else if ((product[23:0] == 0x80_0000) && (product[24] == 1))
then product[63:24] = product[63:24] + 1
}
/* sign-extend to 48 bits and combine with accumulator */
/* check for the -1 * -1 overflow case */
if ((operandY[31:0] == 0x8000_0000) && (operandX[31:0] == 0x8000_0000))
then product[71:64] = 0x00
/* zero-fill */
else product[71:64] = {8{product[63]}}
/* sign-extend */
if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[71:24]
else result[47:0] = ACCx[47:0] + product[71:24]
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/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVx = 1
MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[47] == 1)
then result[47:0] = 0x007f_ffff_ff00
else result[47:0] = 0xff80_0000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1))
then MACSR.EV = 0
else MACSR.EV = 1
break;
case 2:
/* unsigned integers */
if (MACSR.OMC == 0 || MACSR.PAVx == 0)
then {
MACSR.PAVx = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {0x0000,
else operandY[31:0] = {0x0000,
if (U/Lx == 1)
then operandX[31:0] = {0x0000,
else operandX[31:0] = {0x0000,
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
Ry[31:16]}
Ry[15:0]}
Rx[31:16]}
Rx[15:0]}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if (product[63:40] != 0x0000_00)
then {
/* product overflow */
MACSR.PAVx = 1
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then result[47:0] = 0x0000_0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
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EMAC Instruction Set Summary
result[47:0] = 0xffff_ffff_ffff
}
/* zero-fill to 48 bits before performing any scaling */
product[47:40] = 0
/* zero-fill upper byte */
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
product[40:0] = {product[39:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
product[39:0] = {0, product[39:1]}
break;
}
/* combine with accumulator */
if (MACSR.PAVx == 0)
then {if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[47:0]
else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVx = 1
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then result[47:0] = 0x0000_0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
result[47:0] = 0xffff_ffff_ffff
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if (ACCx[47:32] == 0x0000)
then MACSR.EV = 0
else MACSR.EV = 1
break;
}
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Chapter 5
Memory Management Unit (MMU)
This chapter describes the ColdFire virtual memory management unit (MMU), which provides
virtual-to-physical address translation and memory access control. The MMU consists of memory-mapped
control, status, and fault registers that provide access to translation-lookaside buffers (TLBs). Software can
control address translation and access attributes of a virtual address by configuring MMU control registers
and loading TLBs. With software support, the MMU provides demand-paged, virtual addressing.
5.1
Features
The MMU has the following features:
• MMU memory-mapped control, status, and fault registers
— Support a flexible, software-defined virtual environment
— Provide control and maintenance of TLBs
— Provide fault status and recovery information functions
• Separate, 32-entry, fully associative instruction and data TLBs (Harvard TLBs)
— Resides in the controller
— Operates in parallel with the memories
— Suffers no performance penalty on TLB hits
— Supports 1-, 4-, and 8-Kbyte and 1-Mbyte page sizes concurrently
— Contains register-based TLB entries
• Core extensions:
— User stack pointer
— All access error exceptions are precise and recoverable
• Harvard TLB provides 97% of baseline performance on large embedded applications using
equivalent V4 without MMU support as a baseline.
5.2
Virtual Memory Management Architecture
The ColdFire memory management architecture provides a demand-paged, virtual-address environment
with hardware address translation acceleration. It supports supervisor/user, read, write, and execute
permission checking on a per-memory request basis.
The architecture defines the MMU TLB, associated control logic, TLB hit/miss logic, address translation
based on the TLB contents, and access faults due to TLB misses and access violations. It intentionally
leaves some virtual environment details undefined to maximize the software-defined flexibility. These
include the exact structure of the memory-resident pointer descriptor/page descriptor tables, the base
registers for these tables, the exact information stored in the tables, the methodology (if any) for
maintenance of access, and written information on a per-page basis.
5.2.1
MMU Architecture Features
To add optional virtual addressing support, demand-page support, permission checking, and hardware
address translation acceleration to the ColdFire architecture, the MMU architecture features the following:
• Addresses from the core to the MMU are treated as physical or virtual addresses.
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5-1
•
•
•
•
5.2.2
The address access control logic, address attribute logic, memories, and controller function as in
previous ColdFire versions with the addition of the MMU. The MMU, its TLB, and associated
control reside in the logic.
The MMU appears as a memory-mapped device in the space. Information for access error fault
processing is stored in the MMU.
A precise fault (transfer error acknowledge) signals the core on translation (TLB miss) and access
faults. The core supports an instruction restart model for this fault class. Note that this structure
uses the existing ColdFire access error fault vector and needs no new ColdFire exception stack
frames.
The following additions are made to the memory access control to better support the fault
processing and memory maintenance necessary for this virtual addressing environment. These
additions improve memory performance and functionality for physical and virtual address
environments:
— New supervisor-protect bits to the access control registers (ACRs) and the cache control
register (CACR)
— Improved addressing of the ACRs
MMU Architecture Location
Figure 5-1 shows the placement of the MMU/TLB hardware. It follows a traditional model in which it is
closely coupled to the processor local-memory controllers.
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Virtual Memory Management Architecture
Instruction Fetch
Pipeline
J
IAG
Branch
Cache
KC1
IC1
KC2
IC2
Branch
Accel.
Instruction
Memory
Physical
KC1
IED
IB
Memory
Management
Unit
(MMU)
Operand Execution Pipeline
DS
Physical
KC1
DS
J
OAG
Data
Memory
KC1
OC1
KC2
OC2
EX
M Bus
K2M
EMAC
Misalignment
Module
FPU
DA
BDM
DSCLK DSI
DSDO
DDATA
PSTDDATA PSTCLK
Figure 5-1. CF4e Processor Core Block with MMU
5.2.3
MMU Architecture Implementation
This section describes ColdFire design additions and changes for the MMU architecture. It includes
precise faults, MMU access, virtual mode, virtual memory references, instruction and data cache
addresses, supervisor/user stack pointers, access error stack frame additions, expanded control register
space, ACR address improvements, supervisor protection, and debugging in a virtual environment.
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5.2.3.1
Precise Faults
The MMU architecture performs virtual-to-physical address translation and permission checking in the
core. To support demand-paging, the core design provides a precise, recoverable fault for all references.
5.2.3.2
MMU Access
The MMU TLB control registers are memory-mapped. The TLB entries are read and written indirectly
through the MMU control registers. The memory space for these resources is defined by a new supervisor
program model register, the MMU base address register (MMUBAR). This register defines a
supervisor-mode, data-only space. It has the highest priority for the data address mode determination.
5.2.3.3
Virtual Mode
Every instruction and data reference is either a virtual or physical address mode access. All addresses for
special mode (interrupt acknowledges, emulator mode operations, etc.) accesses are physical. All
addresses are physical if the MMU is not enabled. If the MMU is present and enabled, the address mode
for normal accesses is determined by the MMUBAR, RAMBARs, and ACRs in the priority order listed.
Addresses that hit in the MMUBAR, RAMBARs, and ACRs are treated as physical references. These
addresses are not translated and their address attributes are sourced from the highest priority mapping
register they hit. If an address hits none of these mapping registers, it is a virtual address and is sent to the
MMU. If the MMU is enabled, the default CACR information is not used.
5.2.3.4
Virtual Memory References
The ColdFire MMU architecture references the MMU for all virtual mode accesses to the . MMU, SRAM
and ACR memory spaces are treated as physical address spaces and all permissions that apply to these
spaces are contained in the respective mapping register. The virtual mode access either hits or misses in
the TLB of the MMU. A TLB miss generates an access fault in the processor, allowing software to either
load the appropriate translation into the TLB and restart the faulting instruction or abort the process. Each
TLB hit checks permissions based on the access control information in the referenced TLB entry.
5.2.3.5
Instruction and Data Cache Addresses
For a given page size, virtual address bits that reference within a page are called the in-page address. All
bits above this are the virtual page number. Likewise, the physical address has a physical page number and
in-page address bits. Virtual and physical in-page address bits are the same; the MMU translates the virtual
page number to the physical page number.
Instruction and data caches are accessed with the untranslated address. The translated address is used for
cache allocation. That is, caches are virtual-address accessed and physical-address tagged. If instruction
and data cache addresses are not larger than the in-page address for the smallest active MMU page, the
cache is considered physically accessed; if they are larger, the cache can have aliasing problems between
virtual and cache addresses. Software handles these problems by forcing the virtual address to be equal to
the physical address for those bits addressing the cache, but above the in-page address of the smallest
active page size. The number of these bits depends on cache and page sizes.
Caches are addressed with the virtual address, because the cache uses synchronous memory elements, and
an access starts at the rising-clock edge of the first pipeline stage. The MMU provides a physical address
midway through this cycle.
If the cache set address has fewer bits than the in-page address, the cache is considered physically
addressed because these bits are the same in the virtual and physical addresses. If the cache set address has
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Virtual Memory Management Architecture
more bits than the in-page address, one or more of the low-order virtual page number bits are used to
address the cache. The MMU translates these bits; the resulting low-order physical page number bits are
used to determine cache hits.
Address aliasing problems occur when two virtual addresses access one physical page. This is generally
allowed and, if the page is cacheable, one coherent copy of the page image is mapped in the cache at any
time.
If multiple virtual addresses pointing to the same physical address differ only in the low-order virtual page
number bits, conflicting copies can be allocated. For an 8-Kbyte, 4-way, set-associative cache with a
16-byte line size, the cache set address uses address bits 10–4. If virtual addresses 0x0_1000 and 0x0_1400
are mapped to physical address 0x0_1000, using virtual address 0x0_1000 loads cache set 0x00; using
virtual address 0x0_1400 loads cache set 0x40. This puts two copies of the same physical address in the
cache making this memory space not coherent. To avoid this problem, software must force low-order
virtual page number bits to be equal to low-order physical address bits for all bits used to address the cache
set.
5.2.3.6
Supervisor/User Stack Pointers
To isolate supervisor and user modes, CF4e implements two A7 register stack pointers, one for supervisor
mode (SSP) and one for user mode (USP). Two former M68000 family privileged instructions to load and
store the user stack pointer are restored in the instruction set architecture.
5.2.3.7
Access Error Stack Frame
accesses that fault (that is, terminate with a transfer error acknowledge) generate an access error
exception. MMU TLB misses and access violations use the same fault. To quickly determine if a fault was
due to a TLB miss or another type of access error, new fault status field (FS) encodings in the exception
stack frame signal TLB misses on the following:
• Instruction fetch
• Instruction extension fetch
• Data read
• Data write
See Section 5.4.3, “Access Error Stack Frame Additions,” for more information.
5.2.3.8
Expanded Control Register Space
The MMU base address register (MMUBAR) is added for ColdFire virtual mode. Like other control
registers, it can be accessed from the debug module or written using the privileged MOVEC instruction.
See Section 5.5.3.1, “MMU Base Address Register (MMUBAR).”
5.2.3.9
Changes to ACRs and CACR
New ACR and CACR bits, Table 5-1, improve address granularity and supervisor mode protection. These
improvements are not necessary to implement the ColdFire MMU, but they improve memory
functionality for physical and virtual address environments.
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Table 5-1. New ACR and CACR Bits
Bits
Name
Description
ACRn[10]
AMM
Address mask mode. Determines access to the associated address space.
0 The ACR hit function is the same as previous versions, allowing control of a 16-Mbyte
or greater memory region.
1 The upper 8 bits of the address and ACR are compared without a mask function; bits
23–20 of the address and ACR are compared masked by ACR[19–16], allowing control
of a 1- to 16-Mbyte region.
Reset value is 0.
ACRn[3]
SP
Supervisor protect. Determines access to the associated address space.
0 Supervisor and user access allowed.
1 Only supervisor access allowed. Attempted user access causes an access error
exception.
Reset value is 0.
CACR[23]
DDSP
Default data supervisor protect. Determines access to the associated data space.
0 Supervisor and user access allowed.
1 Only supervisor access allowed. Attempted user access causes an access error
exception.
Reset value is 0.
CACR[7]
DISP
Default instruction supervisor protect. Determines access to the associated instruction
space.
0 Supervisor and user access allowed.
1 Only supervisor access allowed. Attempted user access causes access error exception
Reset value is 0.
5.2.3.10
ACR Address Improvements
ACRs provide a 16-Mbyte address window. For a given request address, if the ACR is valid and the request
mode matches the mode specified in the supervisor mode field, ACRn[S], hit determination is specified as
follows:
ACRx_Hit = 0;
if ((address[31:24] & ~ACRn[23:16]) == (ACRn[31:24] & ~ACRn[23:16]))
ACRx_Hit = 1;
With this hit function, ACRs can assign address attributes for user or supervisor requests to memory spaces
of at least 16 Mbytes (through the address mask). With the MMU definition, the ACR hit function is
improved by the address mask mode bit (ACRn[AMM]), which supports finer address granularity. See
Table 5-1.
The revised hit determination becomes the following:
ACRx_Hit = 0;
if (ACRn[10] == 1)
if ((address[31–24] == ACRn[31–24])) &&
((address[23–20] & ~ACRn[19–16]) == (ACRn[23–20] & ~ACRn[19–16])))
ACRx_Hit = 1;
else if (address[31–24] & ~ACRn[23–16]) == (ACRn[31–24] & ~ACRn[23–16]))
ACRx_Hit = 1;
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Debugging in a Virtual Environment
5.2.3.11
Supervisor Protection
Each instruction or data reference is either a supervisor or user access. The CPU’s status register supervisor
bit (SR[S]) determines the operating mode. New ACR and CACR bits protect supervisor space. See
Table 5-1.
5.3
Debugging in a Virtual Environment
To support debugging in a virtual environment, numerous enhancements are implemented in the ColdFire
debug architecture. These enhancements are collectively called Debug revision D and primarily relate to
the addition of an 8-bit address space identifier (ASID) to yield a 40-bit virtual address. This expansion
affects two major debug functions:
• The ASID is optionally included in the hardware breakpoint registers specification. For example,
the four PC breakpoint registers are expanded by 8 bits each, so that a specific ASID value can be
part of the breakpoint instruction address. Likewise, data address/data breakpoint registers are
expanded to include an ASID value. The new control registers define whether and how the ASID
is included in the breakpoint comparison trigger logic.
• The debug module implements the concept of ownership trace in which an ASID value can be
optionally displayed as part of real-time trace. When enabled, real-time trace displays instruction
addresses on any change-of-flow instruction that is not absolute or PC-relative. For Debug revision
D architecture, the address display is expanded to optionally include ASID contents, thus providing
the complete instruction virtual address on these instructions. Additionally, when a Sync_PC serial
BDM command is loaded from the external development system, the processor displays the
complete virtual instruction address, including the 8-bit ASID value.
The MMU control registers are accessible through serial BDM commands. See Chapter 8, “Debug
Support.”
5.4
Virtual Memory Architecture Processor Support
To support the MMU, enhancements have been made to the exception model, the stack pointers, and the
access error stack frame.
5.4.1
Precise Faults
To support demand-paging, all memory references require precise, recoverable faults. The ColdFire
instruction restart mechanism ensures that a faulted instruction restarts from the beginning of execution;
that is, no internal state information is saved when an exception occurs and none is restored when the
handler ends. Given the PC address defined in the exception stack frame, the processor reestablishes
program execution by transferring control to the given location as part of the RTE (return from exception)
instruction.
For a detailed description, see Section 3.9, “Precise Faults.”
5.4.2
Supervisor/User Stack Pointers
To provide the required isolation between these operating modes as dictated by a virtual memory
management scheme, a user stack pointer (A7–USP) is added. The appropriate stack pointer register (SSP,
USP) is accessed as a function of the processor’s operating mode.
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In addition, the following two privileged M68000 family instructions to load/store the USP are added to
the ColdFire instruction set architecture:
mov.l
mov.l
Ay,USP
USP,Ax
# move to
USP: opcode = 0x4E6{0-7}
# move from USP: opcode = 0x4E6{8–F}
The address register number is encoded in the three low-order bits of the opcode.
These instructions are described in detail in Section 5.7, “MMU Instructions.”
5.4.3
Access Error Stack Frame Additions
ColdFire exceptions generate a standard 2-longword stack frame, signaling the contents of the SR and PC
at the time of the exception, the exception type, and a 4-bit fault status field (FS). The first longword
contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second contains the 32-bit
program counter address of the faulted instruction.
31
A7 →
28
FORMAT
27
26
25
FS[3–2]
18
VEC[7–0]
+ 0x04
17
16
15
FS[1–0]
0
STATUS REGISTER
PROGRAM COUNTER [31–0]
Figure 5-2. Exception Stack Frame
The FS field is used for access and address errors. To optimize TLB miss exception handling, new FS
encodings (Table 5-2) allow quick error classification.
Table 5-2. Fault Status Encodings
FS[3:0]
0000
0001, 001x
Definition
Not an access or address error
Reserved
0100
Error (for example, protection fault) on instruction fetch
0101
TLB miss on opword of instruction fetch (New in CF4e)
0110
TLB miss on extension word of instruction fetch (New in CF4e)
0111
IFP access error while executing in emulator mode (New in CF4e)
1000
Error on data write
1001
Attempted write of protected space
1010
TLB miss on data write (New in CF4e)
1011
Reserved
1100
Error on data read
1101
Attempted read, read-modify-write of protected space (New in CF4e)
1110
TLB miss on data read, or read-modify-write (New in CF4e)
1111
OEP access error while executing in emulator mode (New in CF4e)
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MMU Definition
5.5
MMU Definition
The ColdFire MMU provides a virtual address, demand-paged memory architecture. The MMU supports
hardware address translation acceleration using software-managed TLBs. It enforces permission checking
on a per-memory request basis, and has control, status, and fault registers for MMU operation.
5.5.1
Effective Address Attribute Determination
The ColdFire core generates an effective memory address for all instruction fetches and data read and write
memory accesses. The previous ColdFire memory access control model was based strictly on physical
addresses. Every memory request address is a physical address that is analyzed by this memory access
control logic and assigned address attributes, which include the following:
• Cache mode
• SRAM enable information
• Write protect information
• Write mode information
These attributes control processing of the memory request. The address itself is not affected by memory
access control logic.
Instruction and data references base effective address attributes and access mode on the instruction type
and the effective address. Accesses are of the following two types:
• Special mode accesses, including interrupt acknowledges, reads/writes to program-visible control
registers (such as CACR, ROMBARs, RAMBARs, and ACRs), cache control commands
(CPUSHL and INTOUCH), and emulator mode operations. These accesses have the following
attributes:
— Non-cacheable
— Precise
— No write protection
Unless the CPU space/IACK mask bit is set, interrupt acknowledge cycles and emulator mode
operations are allowed to hit in RAMBARs and ROMBARs. All other operations are normal mode
accesses.
• Normal mode accesses. For these accesses, an effective cache mode, precision and write-protection
are calculated for each request.
For data, a normal mode access address is compared with the following priority, from highest to lowest:
RAMBAR0, RAMBAR1, ROMBAR0, ROMBAR1, ACR0, and ACR1. If no match is found, default
attributes in the CACR are used. The priority for instruction accesses is RAMBAR0, RAMBAR1,
ROMBAR0, ROMBAR1, ACR2, and ACR3. Again, if no match is found, default CACR attributes are
used.
Only the test-and-set (TAS) instruction can generate a normal mode access with implied cache mode and
precision. TAS is a special, byte-sized, read-modify-write instruction used in synchronization routines. A
TAS data access that does not hit in the RAMBARs is non-cacheable and precise. TAS uses the normal
effective write protection.
The ColdFire MMU is an optional enhancement to the memory access control. If the MMU is present and
enabled, it adds two factors for calculating effective address attributes:
• MMUBAR defines a memory-mapped, privileged data-only space with the highest priority in
effective address attribute calculation for the data (that is, the MMUBAR has priority over
RAMBAR0).
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
5-9
•
If virtual mode is enabled, any normal mode access that does not hit in the MMUBAR,
RAMBARs, ROMBARs, or ACRs is considered a normal mode virtual address request and
generates its access attributes from the MMU. For this case, the default CACR address attributes
are not used.
The MMU also uses TLB contents to perform virtual-to-physical address translation.
5.5.2
MMU Functionality
The MMU provides virtual-to-physical address translation and memory access control. The MMU consists
of memory-mapped, control, status, and fault registers, and a TLB that can be accessed through MMU
registers. Supervisor software can access these resources through MMUBAR. Software can control
address translation and access attributes of a virtual address by configuring MMU control registers and
loading the MMU’s TLB, which functions as a cache, associating virtual addresses to corresponding
physical addresses and providing access attributes. Each TLB entry maps a virtual page. Several page sizes
are supported. Features such as clear-all and probe-for-hit help maintain TLBs.
Fault-free, virtual address accesses that hit in the TLB incur no pipeline delay. Accesses that miss the TLB
or hit the TLB but violate an access attribute generate an access error exception. On an access error,
software can reference address and information registers in the MMU to retrieve data. Depending on the
fault source, software can obtain and load a new TLB entry, modify the attributes of an existing entry, or
abort the faulting process.
5.5.3
MMU Organization
Access to the MMU memory-mapped region is controlled by MMUBAR, a 32-bit supervisor control
register at 0x008 that is accessed using MOVEC or the serial BDM debug port. The ColdFire
Programmers Reference Manual describes the MOVEC instruction.
5.5.3.1
MMU Base Address Register (MMUBAR)
Figure 5-3 shows MMUBAR. The default reset state is an invalid MMUBAR, so that the MMU is disabled
and the memory-mapped space is not visible.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
BA
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
CPU + 0x008
Figure 5-3. MMU Base Address Register (MMUBAR)
Table 5-3 describes MMU base address register fields.
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MMU Definition
Table 5-3. MMUBAR Field Descriptions
Bits
Name
Description
31–16
BA
Base address. Defines the base address for the 64-Kbyte address space mapped to the
MMU.
15–1
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
0
V
Valid. Indicates when MMUMBAR contents are valid. BA is not used unless V is set.
0 MMUBAR contents are not valid.
1 MMUBAR contents are valid.
5.5.3.2
MMU Memory Map
MMUBAR holds the base address for the 64-Kbyte MMU memory map, shown in Table 5-4. The MMU
memory map area is not visible unless the MMUBAR is valid and must be referenced aligned. A large
portion of the map is reserved for future use.
Table 5-4. MMU Memory Map
Offset from MMUBAR
+ 0x0000
MMU control register (MMUCR)
+ 0x0004
MMU operation register (MMUOR)
+ 0x0008
MMU status register (MMUSR)
+ 0x000C
Reserved
+ 0x0010
MMU fault, test, or TLB address register (MMUAR)
+ 0x0014
MMU read/write TLB tag register (MMUTR)
+ 0x0018
MMU read/write TLB data register (MMUDR)
+ 0x001C–0xFFFC
1
Name
Reserved1
May be used for implementation-specific information/control registers
The address space ID (ASID) is located in a CPU space control register. The 8-bit ASID value located in
the low order byte of a 32-bit supervisor control register, mapped into CPU space at address 0x003 and
accessed using a MOVEC instruction. The ColdFire Family Programmer’s Reference Manual describes
MOVEC.
This 8-bit field is the current user ASID. The ASID is an extension to the virtual address. Address space
0x00 may be reserved for supervisor mode. See address space mode functionality in Section 5.5.3.3,
“MMU Control Register (MMUCR).” The other 255 address spaces are used to tag user processes. The
TLB entry ASID values are compared to this value for user mode unless the TLB entry is marked shared
(MMUTR[SG] is set). The TLB entry ASID value may be compared to 0x00 for supervisor accesses.
5.5.3.3
MMU Control Register (MMUCR)
MMUCR, Figure 5-4, has the address space mode and virtual mode enable bits. The user must force
pipeline synchronization after writing to this register. Therefore, all writes to this register must be
immediately followed by a NOP instruction.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
5-11
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ASM
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Reg
Addr
MMUBAR + 0x000
Figure 5-4. MMU Control Register (MMUCR)
Table 5-5 describes MMUCR fields.
Table 5-5. MMUCR Field Descriptions
Bits
Name
31–2
—
1
ASM
0
EN
5.5.3.4
Description
Reserved, should be cleared. Writes are ignored and reads return zeros.
Address space mode. Controls how the address space ID is used for TLB hits.
0 TLB entry ASID values are compared to the address space ID register value for user or
supervisor mode unless the TLB entry is marked shared (MMUTR[SG] = 1). The
address space ID register value is the effective address space for all requests,
supervisor and user.
1 Address space 0x00 is reserved for supervisor mode and the effective address space
is forced to 0x00 for all supervisor accesses. The other 255 address spaces are used to
tag user processes. The TLB entry ASID values are compared to the address space ID
register for user mode unless the TLB entry is marked shared (SG = 1). The TLB entry
ASID value is always compared to 0x00 for supervisor accesses. This allows two levels
of sharing. All users but not the supervisor share an entry if SG = 1and ASID ¦ 0. All
users and the supervisor share an entry if SG = 1 and ASID = 0
Virtual mode enabled. Indicates when virtual mode is enabled.
0 Virtual mode is disabled.
1 Virtual mode is enabled.
MMU Operation Register (MMUOR)
Figure 5-5 shows the MMUOR.
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MMU Definition
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
AA
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R/W
ACC
UAA
0
0
0
0
0
0
0
0
0
0
STLB CA CNL CAS ITLB ADR
W
Reset
Reg
Addr
0
0
0
0
0
0
MMUBAR + 0x004
Figure 5-5. MMU Operation Register (MMUOR)
Table 5-6 describes MMUOR fields.
Table 5-6. MMUOR Field Descriptions
Bits
Name
Description
31–16
AA
TLB allocation address. This read-only field is maintained by MMU hardware. Its range and
format depend on the TLB implementation (specific TLB size in entries, associativity, and
organization). The access TLB function can use AA to read or write the addressed TLB
entry. The MMU loads AA on the following three events:
• On DTLB access errors, it loads the address of the TLB entry that caused the error.
• If UAA is set, it loads the address of the TLB entry chosen by the MMU for replacement.
• If STLB is set, it uses the data in MMUAR to search the TLB and if the TLB hits, loads
the address of the TLB entry that hits, or if the TLB misses, loads the TLB entry chosen
by the MMU for replacement.
The MMU never picks a locked entry for replacement, and TLB hits of locked entries do not
update hardware replacement algorithm information. This is so access error handlers
mapped with locked TLB entries do not influence the replacement algorithm. Further, TLB
search operations do not update the hardware replacement algorithm information while
TLB writes (loads) do update the hardware replacement algorithm information. The
algorithm used to choose the allocation address depends on the TLB implementation
(such as LRU, round-robin, pseudo-random).
15–9
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
8
STLB
7
CA
6
CNL
Search TLB. STLB always reads as zero.
0 No operation
1 The MMU searches the TLB using data in MMUAR. This operation updates the probe
TLB hit bit in the status register plus loads the AA field as described above.
Clear all TLB entries. CA always reads as zero.
0 No operation
1 Clear all TLB entries and all hardware TLB replacement algorithm information.
Clear all non-locked TLB entries. Setting CNL clears all TLB entries that do not have their
locked bit set. CNL always reads as zero.
0 No operation
1 Clear all non-locked TLB entries.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
5-13
Table 5-6. MMUOR Field Descriptions (Continued)
Bits
Name
5
CAS
Clear all non-locked TLB entries that match ASID. CAS is always reads as a zero.
0 No operation
1 Clear all non-locked TLB entries that match ASID register.
4
ITLB
ITLB operation. Used by TLB search and access operations that use the TLB allocation
address.
0 The MMU uses the DTLB to search or update the allocation address.
1 The MMU uses the ITLB for searches and updates of the allocation address.
3
ADR
TLB address select. Indicates which address to use when accessing the TLB.
0 Use the TLB allocation address for the TLB address.
1 Use MMUAR for the TLB address.
2
R/W
TLB access read/write select. Indicates whether to do a read or a write when accessing
the TLB.
0 Write
1 Read
1
ACC
MMU TLB access. This bit always reads as a zero. STLB is used for search operations.
0 No operation. ACC should be a zero to search the TLB.
1 The MMU reads or writes the TLB depending on R/W. For TLB reads, TLB tag and data
results are loaded into MMUTR and MMUDR. For TLB writes, the contents of these
registers are written to the TLB. The TLB is accessed using the TLB allocation address
if ADR is zero or using MMUAR if ADR is set.
0
UAA
Update allocation address. UAA always reads as a zero.
0 No operation
1 MMU updates the allocation address field with the MMU’s choice for the allocation
address in the ITLB or DTLB depending on the ITLB instruction operation bit.
5.5.3.5
Description
MMU Status Register (MMUSR)
MMUSR, Figure 5-6, is updated on all data access faults and search TLB operations.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
SPF
RF
WF
0
HIT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Reg
Addr
MMUBAR + 0x008
Figure 5-6. MMU Status Register (MMUSR)
Table 5-7 describes MMUSR fields.
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MMU Definition
Table 5-7. MMUSR Field Descriptions
Bits
Name
31–6
—
5
SPF
Supervisor protect fault. Indicates if the last data fault was a user mode access that hit in
a TLB entry that had its supervisor protect bit set.
0 Last data access fault did not have a supervisor protect fault.
1 Last data access fault had a supervisor protect fault.
4
RF
Read access fault. Indicates if the last data fault was an data read access that hit in a TLB
entry that did not have its read bit set.
0 Last data access fault did not have a read protect fault.
1 Last data access fault had a read protect fault.
3
WF
Write access fault. Indicates if the last data fault was an data write access that hit in a TLB
entry that did not have its write bit set.
0 Last data access fault did not have a write protect fault.
1 Last data access fault had a write protect fault.
2
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
1
HIT
0
—
5.5.3.6
Description
Reserved, should be cleared. Writes are ignored and reads return zeros.
Search TLB hit. Indicates if the last data fault or the last search TLB operation hit in the
TLB.
0 Last data access fault or search TLB operation did not hit in the TLB.
1 Last data access fault or search TLB operation hit in the TLB.
Reserved, should be cleared. Writes are ignored and reads return zeros.
MMU Fault, Test, or TLB Address Register (MMUAR)
The MMUAR format, Figure 5-7, depends on how the register is used.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
FA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
FA
W
Reset
0
0
0
0
0
Reg
Addr
0
0
0
MMUBAR + 0x010
Figure 5-7. MMU Fault, Test, or TLB Address Register (MMUAR)
Table 5-8 describes MMUAR fields.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
5-15
Table 5-8. MMUAR Field Descriptions
Bits
Name
Description
31–0
FA
Form address. Written by the MMU with the virtual address on DTLB misses and access
faults. For this case, all 32 bits are address bits. This register may be written with a virtual
address and address attribute information for searching the TLB (MMUCR[STLB]). For this
case, FA[31–1] are the virtual page number and FA[0] is the supervisor bit. The current
ASID is used for the TLB search. MMUAR can also be written with a TLB address for use
with the access TLB function (using MMUCR[ACC]).
5.5.3.7
MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR)
Each TLB entry consists of a 32-bit TLB tag entry and a 32-bit TLB data entry. TLB entries are referenced
through MMUTR and MMUDR. For read TLB accesses, the contents of the TLB tag and data entries
referenced by the allocation address or MMUAR are loaded in MMUTR and MMUDR. TLB write
accesses place MMUTR and MMUDR contents into the TLB tag and data entries defined by the allocation
address or MMUAR.
MMUTR, Figure 5-8, contains the virtual address tag, the address space ID (ASID), a shared page
indicator, and the valid bit.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
VA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SG
V
0
0
R
VA
ID
W
Reset
0
0
0
0
0
Reg
Addr
0
0
0
0
0
0
0
0
0
MMUBAR + 0x014
Figure 5-8. MMU Read/Write TLB Tag Register (MMUTR)
Table 5-9 describes MMUTR fields.
Table 5-9. MMUTR Field Descriptions
Bits
Name
Description
31–10
VA
Virtual address. Defines the virtual address mapped by this entry. The number of bits used
in the TLB hit determination depends on the page size field in the corresponding TLB data
entry.
9–2
ID
Address space ID (ASID). This extension to the virtual address marks this entry as part of
1 of 256 possible address spaces. Address space 0x00 can be reserved for supervisor
mode. The other 255 address spaces are used to tag user processes. TLB entry ASID
values are compared to the ASID register value for user mode unless the TLB entry is
marked shared (SG = 1). The TLB entry ASID value may be compared to 0x00 for
supervisor accesses or to the ASID. The description of MMUCR[ASM] in Table 5-5 gives
details on supervisor mode and ASID compares.
MCF548x Reference Manual, Rev. 3
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MMU Definition
Table 5-9. MMUTR Field Descriptions (Continued)
Bits
Name
Description
1
SG
Shared global. Indicates when the entry is shared among user address spaces. If an entry
is shared, its ASID is not part of the TLB hit determination for user accesses.
0 This entry is not shared globally.
1 This entry is shared globally.
Note that the ASID can be used to determine supervisor mode hits to allow two sharing
levels. If SG and MMUCR[ASM] are set and the ASID is not zero, all users (but not the
supervisor) share an entry. If SG and MMUCR[ASM] are set and the ASID is zero, all users
and the supervisor share an entry. The description of ASM in Table 5-5 details supervisor
mode and ASID compares.
0
V
Valid. Indicates when the entry is valid. Only valid entries generate a TLB hit.
0 Entry is not valid.
1 Entry is valid.
MMUDR, Figure 5-9, contains the physical address, page size, cache mode field, supervisor-protect bit,
read, write, execute permission bits, and lock-entry bit.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
PA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SP
R
W
X
LK
0
0
0
0
0
0
0
R
PA
SZ
CM
W
Reset
0
0
0
0
0
0
Reg
Addr
0
0
0
0
MMUBAR + 0x014
Figure 5-9. MMU Read/Write TLB Data Register (MMUDR)
Table 5-10 describes MMUDR fields.
Table 5-10. MMUDR Field Descriptions
Bits
Name
Descriptions
31–10
PA
Physical address. Defines the physical address which is mapped by this entry. The number
of bits used to build the effective physical address if this TLB entry hits depends on the
page size field.
9–8
SZ
Page size. Page size for this entry:
00
01
10
11
1 Mbyte: VA[31–20] used for TLB hit
4 Kbytes VA[31–12] used for TLB hit
8 Kbytes VA[31–13] used for TLB hit
1 Kbyte VA[31–10] used for TLB hit
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
5-17
Table 5-10. MMUDR Field Descriptions (Continued)
5.5.4
Bits
Name
Descriptions
7–6
CM
Cache mode. If a Harvard TLB implementation is used, CM0 is a don’t care for the ITLB.
CM is ignored on writes and always reads as zero for the ITLB.
Instruction cache modes:
1x Page is non-cacheable.
0x Page is cacheable.
Data cache modes
00 Page is cacheable writethrough.
01 Page is cacheable copyback.
10 Page is non-cacheable precise.
11 Page is non-cacheable imprecise.
5
SP
Supervisor protect. Controls user mode access to the page mapped by this entry.
0 Entry is not supervisor protected.
1 Entry is supervisor protected. An attempted user mode access that matches this entry
generates an access error exception.
4
R
Read access enable. Indicates if data read accesses to this entry are allowed. If a Harvard
TLB implementation is used, this bit is a don’t care for the ITLB. This bit is ignored on writes
and always reads as zero for the ITLB.
0 Do not allow data read accesses. Attempted data read accesses that match this entry
generate an access error exception.
1 Allow data read accesses.
3
W
Write access enable. Indicates if data write accesses are allowed to this entry. If separate
ITLB and DTLBs) are used, W is a don’t care for the ITLB. W is ignored on writes and reads
as zero for the ITLB.
0 Do not allow data write accesses. Attempted data write accesses that match this entry
generate an access error exception.
1 Allow data write accesses.
2
X
Execute access enable. Indicates if instruction fetches to this entry are allowed. If separate
ITLB and DTLBs are is used, X is a don’t care for the DTLB. X is ignored on writes and
reads as zero for the DTLB.
0 Do not allow instruction fetches. Attempted instruction fetches that match this entry
cause an access error exception.
1 Allow instruction fetch accesses.
1
LK
Lock entry bit. Indicates if this entry is included in the replacement algorithm. TLB hits of
locked entries do not update replacement algorithm information.
0 Include this entry when determining the best entry for a TLB allocation.
1 Do not allow this entry to be selected by the replacement algorithm.
0
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
MMU TLB
Each TLB entry consists of two 32-bit fields. The first is the TLB tag entry, and the second is the TLB data
entry. TLB size and organization are implementation dependent. TLB entries can be read and written
through MMU registers. TLB contents are unaffected by reset.
MCF548x Reference Manual, Rev. 3
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MMU Definition
5.5.5
MMU Operation
The processor sends instruction fetch requests and data read/write requests to the MMU in the instruction
and operand address generation cycles (IAG and OAG). The controller and memories occupy the next two
pipeline stages, instruction fetch cycles 1 and 2 (IC1 and IC2) and operand fetch cycles 1 and 2 (OC1 and
OC2). For late writes, optional data pipeline stages are added to the controller as well as any writable
memories.
Table 5-11 shows the association between memory pipeline stages and the processor’s pipeline structures,
shown in Figure 5-1.
.
Table 5-11. Version 4 Memory Pipelines
Memory Pipeline Stage
Instruction Fetch Pipeline Operand Execution Pipeline
J stage
IAG
OAG
KC1 stage
IC1
OC1
KC2 stage
IC2
OC2
Operand execute stage
n/a
EX
Late-write stage
n/a
DA
Version 4 use the same 2-cycle read pipeline developed for Version 3. Each has 32-bit address and 32-bit
read data paths. Version 4 uses synchronous memory elements for all memory control units. To support
this, certain control information and all address bits are sent on the at the end of the cycle before the initial
bus access cycle (The data has an additional 32-bit write data path). For processor store operations,
Version 4 ColdFire uses a late-write strategy, which can require 2 additional data cycles. This strategy
yields the pipeline behavior described in Table 5-12.
Table 5-12. Pipeline Cycles
Cycle
J
Description
Control and partial address broadcast (to start synchronous memories)
KC1
Complete address and control broadcast plus MMU information. It is during this cycle that all memory
element read operations are performed; that is, memory arrays are accessed.
KC2
Select appropriate memory as source, return data to processor, handle cache misses or hold pipeline
as needed.
EX
Optional write stage, pipeline address and control for store operations.
DA
Data available for stores from processor; memory element update occurs in the next cycle.
The contains two independent memory unit access controllers and two independent controllers. Each
instruction and data is analyzed to see which, if any, controller is referenced. This information, along with
cache mode, store precision, and fault information, is sourced during KC1.
The optional MMU is referenced concurrently with the memory unit access controllers. It has two
independent control sections to simultaneously process an instruction and data request. Figure 5-1 shows
how the MMU and memory unit access controllers fit in the pipeline. As the diagram shows, core address
and attributes are used to access the mapping registers and the MMU. By the middle of the KC1 cycle, the
memory address is available along with its corresponding access control.
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Figure 5-10 shows more details of the MMU structure. The TLB is accessed at the beginning of the KC1
pipeline stage so the resulting physical address can be sourced to the cache controllers to factor into the
cache hit/miss determination. This is required because caches are virtually indexed but physically mapped.
JADDR, J Control
To memory controllers
J
TLB data
entries
TLB tag
entries
Memory unit access control
(MMUBAR, RAMBARs, ROMBARs,
ACRs, CACR priority hit logic)
Comp
To control for TLB miss
logic
TLB hit
entry
data
KC1
Translated address
MMU’s access control
TLB Hit
Untranslated address
mapping register’s
access control
To control for TLB miss
logic
Mapping register hit
or special mode access
To memory controllers plus
bus interface
KADDR_KC1
KC1 cycle access control
Figure 5-10. Address and Attributes Generation
5.6
MMU Implementation
The MMU implements a 64-entry full-associative Harvard TLB architecture with 32-entry ITLB and
DTLB. This section provides more details of this specific TLB implementation. This section details the
operation and looks at the size, frequency, miss rate, and miss recovery time of this specific TLB
implementation.
5.6.1
TLB Address Fields
Because the TLB has a total of 64 entries (32 each for the ITLB and DTLB), a 6-bit address field is
necessary. TLB addresses 0–31 reference the ITLB, and TLB addresses 32–63 reference the DTLB.
In the MMUOR, bits 0 through 5 of the TLB allocation address (AA[5–0]) have this address format for
CF4e. The remaining TLB allocation address bits (AA[15–6]) are ignored on updates and always read as
zero.
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MMU Implementation
When MMUAR is used for a TLB address, bits FA[5–0] also have this address format for CF4e. The
remaining form address bits (FA[31–6]) are ignored when this register is being used for a TLB address.
5.6.2
TLB Replacement Algorithm
The instruction and data TLBs provide low-latency access to recently used instruction and operand
translation information. CF4e ITLBs and DTLBs are 32-entry fully associative caches. The 32 ITLB
entries are searched on each instruction reference; the 32 DTLB entries are searched on each operand
reference.
CF4e TLBs are software controlled. The TLB clear-all function clears valid bits on every TLB entry and
resets the replacement logic. A new valid entry is loaded in the TLBs may be designated as locked and
unavailable for allocation. TLB hits to locked entries do not update replacement algorithm information.
When a new TLB entry needs to be allocated, the user can specify the exact TLB entry to be updated
(through MMUOR[ADR] and MMUAR) or let TLB hardware pick the entry to update based on the
replacement algorithm. A pseudo-least-recently used (PLRU) algorithm picks the entry to be replaced on
a TLB miss. The algorithm works as follows:
• If any element is empty (non-valid), use the lowest empty element as the allocate entry (that is,
entry 0 before 1, 2, 3, and so on).
• If all entries are valid, use the entry indicated by the PLRU as the allocate entry.
The PLRU algorithm uses 31 most-recently used state bits per TLB to track the TLB hit history. Table 5-13
lists these state bits.
Table 5-13. PLRU State Bits
State Bits
Meaning
rdRecent31To16
A one indicates 31To16 is more recent than 15To00
rdRecent31To24
A one indicates 31To24 is more recent than 23To16
rdRecent15To08
A one indicates 15To08 is more recent than 07To00
rdRecent31To28
A one indicates 31To28 is more recent than 27To24
rdRecent23To20
A one indicates 23To20 is more recent than 19To16
rdRecent15To12
A one indicates 15To12 is more recent than 11To08
rdRecent07To04
A one indicates 07To04 is more recent than 03To00
rdRecent31To30
A one indicates 31To30 is more recent than 29To28
rdRecent27To26
A one indicates 27To26 is more recent than 25To24
rdRecent23To22
A one indicates 23To22 is more recent than 21To20
rdRecent19To18
A one indicates 19To18 is more recent than 17To16
rdRecent15To14
A one indicates 15To14 is more recent than 13To12
rdRecent11To10
A one indicates 11To10 is more recent than 09To08
rdRecent07To06
A one indicates 07To06 is more recent than 05To04
rdRecent03To02
A one indicates 03To02 is more recent than 01To00
rdRecent31
A one indicates 31 is more recent than 30
rdRecent29
A one indicates 29 is more recent than 28
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Table 5-13. PLRU State Bits (Continued)
State Bits
Meaning
rdRecent27
A one indicates 27 is more recent than 26
rdRecent25
A one indicates 25 is more recent than 24
rdRecent23
A one indicates 23 is more recent than 22
rdRecent21
A one indicates 21 is more recent than 20
rdRecent19
A one indicates 19 is more recent than 18
rdRecent17
A one indicates 17 is more recent than 16
rdRecent15
A one indicates 15 is more recent than 14
rdRecent13
A one indicates 13 is more recent than 12
rdRecent11
A one indicates 11 is more recent than 10
rdRecent09
A one indicates 09 is more recent than 08
rdRecent07
A one indicates 07 is more recent than 06
rdRecent05
A one indicates 05 is more recent than 04
rdRecent03
A one indicates 03 is more recent than 02
rdRecent01
A one indicates 01 is more recent than 00
Binary state bits are updated on all TLB write (load) operations, as well as normal ITLB and DTLB hits
of non-locked entries. Also, if all entries in a binary state are locked, than that state is always set. That is,
if entries 15, 14, 13, and 12 were locked, LRU state bit rdRecent15To14 is forced to one.
For a completely valid TLB, binary state information determines the LRU entry. The CF4e replacement
algorithm is deterministic and, for the case of a full TLB (with no locked entries and always touching new
pages), the replacement entry repeats every 32 TLB loads.
5.6.3
TLB Locked Entries
Figure 5-11 is a ColdFire MMU Harvard TLB block diagram.
For TLB miss faults, the instruction restart model completely reexecutes an instruction on returning from
the exception handler. An instruction can touch two instruction pages (a 32- or 48-bit instruction can
straddle two pages) or four data pages (a memory-to-memory word or longword move where misaligned
source and destination operands straddle two pages). Therefore, one instruction may take two ITLB misses
and allocate two ITLB pages before completion. Likewise, one instruction may require four DTLB misses
and allocate four DTLB pages. Because of this, a pool of unlocked TLB entries must be available if virtual
memory is used.
The above examples show the fewest entries needed to guarantee an instruction can complete execution.
For good MMU performance, more unlocked TLB entries should be available.
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MMU Instructions
Current address space ID (ASID)
J
Instruction or data address and attributes
TLB Tag
Entry 31
TLB Tag
Entry 0
TLB Tag
Entry 31
TLB Tag
Entry 0
KC1
Compare
Compare
Instruction or data hit select
To control for instruction or DTLB miss
logic
IC1 or OC1 translated address
IC1 or OC1 access control
Figure 5-11. Version 4 ColdFire MMU Harvard TLB
5.7
MMU Instructions
The MOVE to USP and MOVE from USP instructions have been added for accessing the USP. Refer to
the ColdFire Programmer’s Reference Manual for more information.
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Chapter 6
Floating-Point Unit (FPU)
6.1
Introduction
This chapter describes instructions implemented in the floating-point unit (FPU) designed for use with the
ColdFire family of microprocessors. The FPU conforms to the American National Standards Institute
(ANSI)/Institute of Electrical and Electronics Engineers (IEEE) Standard for Binary Floating-Point
Arithmetic (ANSI/IEEE Standard 754).
The hardware unit is optimized for real-time execution with exceptions disabled and default results
provided for specific operations, operands, and number types. The FPU does not support all IEEE-754
number types and operations in hardware. Exceptions can be enabled to support these cases in software.
6.1.1
Overview
The FPU operates on 64-bit, double-precision, floating-point data and supports single-precision and signed
integer input operands. The FPU programming model is like that in the MC68060 microprocessor. The
FPU is intended to accelerate the performance of certain classes of embedded applications, especially
those requiring high-speed floating-point arithmetic computations. See Section 6.7.3, “Key Differences
between ColdFire and M68000 FPU Programming Models.”
The FPU appears as another execute engine at the bottom stages of the operand execution pipeline (OEP),
using operands from a dual-ported register file.
Setting bit 4 in the cache control register (CACR[DF]) disables the FPU. If CACR[DF] is cleared, all FPU
instructions are issued and executed, otherwise the processor responds with an unimplemented line-F
instruction exception (vector 11).
Operating systems often assume user applications are integer-only (to minimize the time required by save
context) by setting CACR[DF] at process initiation. If the application includes floating-point instructions,
the attempted execution of the first FP instruction generates the unimplemented line-F exception, which
signals the kernel that the FPU registers must be included in the context for the application. The application
then continues execution with CACR[DF] cleared to enable FPU execution.
6.1.1.1
Notational Conventions
Table 6-1 defines notational conventions used in this chapter.
Table 6-1. Notational Conventions
Symbol
Description
Single- and Double-Precision Operand Operations
+
Arithmetic addition or postincrement indicator
−
Arithmetic subtraction or predecrement indicator
×
Arithmetic multiplication
÷
Arithmetic division or conjunction symbol
∼
Invert, operand is logically complemented. An overbar, , is also used for this operation.
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6-1
Table 6-1. Notational Conventions (Continued)
Symbol
Description
&
Logical AND
|
Logical OR
→
<op>
<operand>tested
sign-extended
Source operand is moved to destination operand
Any double-operand operation
Operand is compared to zero and the condition codes are set appropriately
All bits of the upper portion are made equal to the high-order bit of the lower portion
Other Operations
If <condition>
then <operations>
else <operations>
Test the condition. If true, the operations after then are performed. If the condition is false and the
optional else clause is present, the operations after else are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.
Register Specifications
An
Address register n (example: A3 is address register 3)
Ay, Ax
Source and destination address registers, respectively
Dn
Data register n (example: D3 is data register 3)
Dy,Dx
Source and destination data registers, respectively
FPCR
Floating-point control register
FPIAR
Floating-point instruction address register
FPn
FPSR
FPy,FPx
Floating-point data register n (example: FP3 is FPU data register 3)
Floating-point status register
Source and destination floating-point data registers, respectively
PC
Program counter
Rn
Address or data register
Rx
Destination register
Ry
Source register
Xi
Index register
Table 6-2 describes addressing modes and syntax for floating-point instructions.
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Operand Data Formats and Types
Table 6-2. Floating-Point Addressing Modes
Addressing Modes
Syntax
Register direct
Address register direct
Address register direct
6.2
Dy
Ay
Register indirect
Address register indirect
Address register indirect with postincrement
Address register indirect with predecrement
Address register indirect with displacement
(Ay)
–(Ay)
(d16,Ay)
Program counter indirect with displacement
(d16,PC)
Operand Data Formats and Types
The FPU supports signed byte, word, and longword integer formats, which are identical to those supported
by the integer unit. The FPU also supports single- and double-precision binary floating-point formats that
fully comply with the IEEE-754 standard.
6.2.1
Signed-Integer Data Formats
The FPU supports 8-bit byte (B), 16-bit word (W), and 32-bit longword (L) integer data formats.
6.2.2
Floating-Point Data Formats
Figure 6-1 shows the two binary floating-point data formats.
31
30
S
63
S
62
8-Bit Exponent
Sign of Mantissa
51
11-Bit Exponent
0
22
52-Bit Fraction
23-Bit Fraction
Single
0
Double
Sign of Mantissa
Figure 6-1. Floating-Point Data Formats
Note that, throughout this chapter, a mantissa is defined as the concatenation of an integer bit, the binary
point, and a fraction. A fraction is the term designating the bits to the right of the binary point in the
mantissa.
Mantissa
(integer bit).(fraction)
Figure 6-2. Mantissa
The integer bit is implied to be set for normalized numbers and infinities, clear for zeros and denormalized
numbers. For not-a-numbers (NANs), the integer bit is ignored. The exponent in both floating-point
formats is an unsigned binary integer with an implied bias added to it. Subtracting the bias from exponent
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6-3
yields a signed, two’s complement power of two. This represents the magnitude of a normalized
floating-point number when multiplied by the mantissa.
By definition, a normalized mantissa always takes values starting from 1.0 and going up to, but not
including, 2.0; that is, [1.0...2.0).
6.2.3
Floating-Point Data Types
Each floating-point data format supports five unique data types: normalized numbers, zeros, infinities,
NANs, and denormalized numbers. The normalized data type, Figure 6-3, never uses the maximum or
minimum exponent value for a given format.
6.2.3.1
Normalized Numbers
Normalized numbers include all positive or negative numbers with exponents between the maximum and
minimum values. For single- and double-precision normalized numbers, the implied integer bit is one and
the exponent can be zero.
Min < Exponent < Max
Fraction = Any bit pattern
Sign of Mantissa, 0 or 1
Figure 6-3. Normalized Number Format
6.2.3.2
Zeros
Zeros can be positive or negative and represent real values, + 0.0 and – 0.0. See Figure 6-4.
Exponent = 0
Fraction = 0
Sign of Mantissa, 0 or 1
Figure 6-4. Zero Format
6.2.3.3
Infinities
Infinities can be positive or negative and represent real values that exceed the overflow threshold. A
result’s exponent greater than or equal to the maximum exponent value indicates an overflow for a given
data format and operation. This overflow description ignores the effects of rounding and the
user-selectable rounding models. For single- and double-precision infinities, the fraction is a zero. See
Figure 6-5.
Exponent = Maximum
Fraction = 0
Sign of Mantissa, 0 or 1
Figure 6-5. Infinity Format
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Operand Data Formats and Types
6.2.3.4
Not-A-Number
When created by the FPU, NANs represent the results of operations having no mathematical interpretation,
such as infinity divided by infinity. Operations using a NAN operand as an input return a NAN result.
User-created NANs can protect against uninitialized variables and arrays or can represent user-defined
data types. See Figure 6-6.
Exponent = Maximum
Fraction = Any nonzero bit pattern
Sign of Mantissa, 0 or 1
Figure 6-6. Not-a-Number Format
If an input operand to an operation is a NAN, the result is an FPU-created default NAN. When the FPU
creates a NAN, the NAN always contains the same bit pattern in the fraction: all fraction bits are ones and
the sign bit is zero. When the user creates a NAN, any nonzero bit pattern can be stored in the fraction and
the sign bit.
6.2.3.5
Denormalized Numbers
Denormalized numbers represent real values near the underflow threshold. Denormalized numbers can be
positive or negative. For denormalized numbers in single- and double-precision, the implied integer bit is
a zero. See Figure 6-7.
Exponent = 0
Fraction = Any nonzero bit pattern
Sign of Mantissa, 0 or 1
Figure 6-7. Denormalized Number Format
Traditionally, the detection of underflow causes floating-point number systems to perform a flush-to-zero.
The IEEE-754 standard implements gradual underflow: the result mantissa is shifted right (denormalized)
while the result exponent is incremented until reaching the minimum value. If all the mantissa bits of the
result are shifted off to the right during this denormalization, the result becomes zero.
Denormalized numbers are not supported directly in the hardware of this implementation but can be
handled in software if needed (software for the input denorm exception could be written to handle
denormalized input operands, and software for the underflow exception could create denormalized
numbers). If the input denorm exception is disabled, all denormalized numbers are treated as zeros.
Table 6-3 summarizes the data type specifications for byte, word, longword, single- and double-precision
data formats.
Table 6-3. Real Format Summary
Parameter
Data Format
Single-Precision
3130
s
23 22
e
Double-Precision
0
f
6362
s
52 51
e
0
f
Field Size in Bits
Sign (s)
1
1
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Table 6-3. Real Format Summary (Continued)
Parameter
Single-Precision
Double-Precision
Biased exponent (e)
8
11
Fraction (f)
23
52
Total
32
64
Interpretation of Sign
Positive fraction
s=0
s=0
Negative fraction
s=1
s=1
Normalized Numbers
Bias of biased exponent
Range of biased exponent
Range of fraction
+127 (0x7F)
+1023 (0x3FF)
0 < e < 255 (0xFF)
0 < e < 2047 (0x7FF)
Zero or Nonzero
Zero or Nonzero
1.f
1.f
(–1)s × 2e–127 × 1.f
(–1)s × 2e–1023 × 1.f
Mantissa
Relation to representation of real numbers
Denormalized Numbers
Biased exponent format minimum
Bias of biased exponent
Range of fraction
0 (0x00)
0 (0x000)
+126 (0x7E)
+1022 (0x3FE)
Nonzero
Nonzero
0.f
0.f
(–1)s × 2–126 × 0.f
(–1)s × 2–1022 × 0.f
Mantissa
Relation to representation of real numbers
Signed Zeros
Biased exponent format minimum
0 (0x00)
0 (0x00)
Mantissa
0.f = 0.0
0.f = 0.0
Signed Infinities
Biased exponent format maximum
Mantissa
255 (0xFF)
2047 (0x7FF)
0.f = 0.0
0.f = 0.0
NANs
Sign
Don’t Care
0 or 1
Biased exponent format maximum
255 (0xFF)
2047 (0x7FF)
Nonzero
Nonzero
xxxxx…xxxx
11111…1111
xxxxx…xxxx
11111…1111
Fraction
Representation of Fraction
Nonzero Bit Pattern Created by User
Fraction When Created by FPU
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Register Definition
Table 6-3. Real Format Summary (Continued)
Parameter
Single-Precision
Double-Precision
Approximate Ranges
Maximum Positive Normalized
3.4 × 1038
1.8 x 10308
Minimum Positive Normalized
1.2 × 10–38
2.2 x 10–308
Minimum Positive Denormalized
1.4 × 10–45
4.9 x 10–324
6.3
Register Definition
The programmer’s model for the FPU consists of the following:
• Eight 64-bit floating-point data registers (FP0–FP7)
• One 32-bit floating-point control register (FPCR)
• One 32-bit floating-point status register (FPSR)
• One 32-bit floating-point instruction address register (FPIAR)
Figure 6-8 shows the FPU programming model.
63
0
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FPCR
FPSR
FPIAR
Floating-point data registers
Floating-point control register
Floating-point status register
Floating-point instruction address register
Figure 6-8. Floating-Point Programmer’s Model
6.3.1
Floating-Point Data Registers (FP0–FP7)
Floating-point data registers are analogous to the integer data registers for the 68K/ColdFire family. They
always contain numbers in double-precision format, even though the operand may be a single-precision
value used in a single-precision calculation. All external operands, regardless of the source data format,
are converted to double-precision format before being used in any calculation or being stored in a
floating-point data register. A reset or a null-restore operation sets FP0–FP7 to positive, nonsignaling
NANs.
6.3.2
Floating-Point Control Register (FPCR)
The FPCR, Figure 6-9, contains an exception enable byte (EE) and a mode control byte (MC). Each EE
bit corresponds to a floating-point exception class. The user can separately enable traps for each class of
floating-point exceptions. The MC bits control FPU operating modes.
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The user can read or write to FPCR using FMOVE or FRESTORE. A processor reset or a restore operation
of the null state clears the FPCR. When this register is cleared, the FPU never generates exceptions.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
Exception Enable Byte (EE)
R BSUN INAN
OPERR OVFL UNFL
Mode Control Byte (MC)
DZ
INEX
IDE
0
PREC
0
0
0
0
0
RND
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
Reg
Addr
0
0
CPU + 0x824
Figure 6-9. Floating-Point Control Register (FPCR)
Table 6-4 describes FPCR fields.
Table 6-4. FPCR Field Descriptions
Bits
Field
Description
31–16
—
15
BSUN
Branch set on unordered
14
INAN
Input not-a-number
13
OPERR
12
OVFL
Overflow
11
UNFL
Underflow
10
DZ
9
INEX
8
IDE
7
—
6
PREC
5–4
RND
3–0
—
Reserved, should be cleared.
Operand error
Divide by zero
Inexact operation
Input denormalized
Reserved, should be cleared.
Rounding precision
0 Double (D)
1 Single (S)
Rounding mode
00 To nearest (RN)
01 To zero (RZ)
10 To minus infinity (RM)
11 To plus infinity (RP)
Reserved, should be cleared.
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Register Definition
6.3.3
Floating-Point Status Register (FPSR)
The FPSR, Figure 6-10, contains a floating-point condition code byte (FPCC), a floating-point exception
status byte (EXC), and a floating-point accrued exception byte (AEXC). The user can read or write all
FPSR bits. Execution of most floating-point instructions modifies FPSR. FPSR is loaded using FMOVE
or FRESTORE. A processor reset or a restore operation of the null state clears the FPSR.
The floating-point condition code byte contains 4 condition code bits that are set after completion of all
arithmetic instructions involving the floating-point data registers. The floating-point store operation,
FMOVEM, and move system control register instructions do not affect the FPCC.
The exception status byte contains a bit for each floating-point exception that might have occurred during
the most recent arithmetic instruction or move operation. This byte is cleared at the start of all operations
that generate floating-point exceptions (except FBcc only affects BSUN and that only for nonaware tests).
Operations that do not generate floating-point exceptions do not clear this byte. An exception handler can
use this byte to determine which floating-point exception or exceptions caused a trap. The equations below
the table show the comparative relationship between the EXC byte and AEXC byte.
The accrued exception byte contains 5 required bits for IEEE-754 exception-disabled operations. These
exceptions are logical combinations of EXC bits. AEXC records all floating-point exceptions since AEXC
was last cleared, either by writing to FPSR or as a result of reset or a restore operation of the null state.
Many users disable traps for some or all floating-point exception classes. AEXC eliminates the need to
poll EXC after each floating-point instruction. At the end of arithmetic operations, EXC bits are logically
combined to form an AEXC value that is logically ORed into the existing AEXC byte (FBcc only updates
IOP). This operation creates sticky floating-point exception bits in AEXC that the user can poll only at the
end of a series of floating-point operations. A sticky bit is one that remains set until the user clears it.
Setting or clearing AEXC bits neither causes nor prevents an exception. The equations below the table
show relationships between EXC and AEXC. Comparing the current value of an AEXC bit with a
combination of EXC bits derives a new value in the corresponding AEXC bit. These boolean equations
apply to setting AEXC bits at the end of each operation affecting AEXC.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Floating-Point Condition Code Byte (FPCC)
R
0
0
0
0
N
Z
I
NAN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
Exception Status Byte (EXC)
Floating-Point Accrued Exception Byte (AEXC)
R BSUN INAN OPERR OVFL UNFL DZ INEX IDE
IOP
OVFL UNFL
DZ
INEX
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
Reg
Addr
0
0
0
0
0
0
0
CPU + 0x822
Figure 6-10. Floating-Point Status Register (FPSR)
Table 6-5 describes FPSR fields.
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Table 6-5. FPSR Field Descriptions
Bits
Field
Description
31–28
—
Reserved, should be cleared.
27
N
Negative
26
Z
Zero
25
I
Infinity
24
NAN
23–16
—
15
BSUN
Branch/set on unordered
14
INAN
Input not-a-number
13
OPERR
12
OVFL
Overflow
11
UNFL
Underflow
10
DZ
Divide by zero
9
INEX
Inexact result
8
IDE
Input is denormalized
7
IOP
Invalid operation
6
OVFL
Overflow
5
UNFL
Underflow
4
DZ
Divide by zero
3
INEX
Inexact result
2–0
—
Not-a-number
Reserved, should be cleared.
Operand error
Reserved, should be cleared.
For AEXC[OVFL], AEXC[DZ], and AEXC[INEX], the next value is determined by ORing the current
AEXC value with the EXC equivalent, as shown in the following:
• Next AEXC[OVFL] = Current AEXC[OVFL] | EXC[OVFL]
• Next AEXC[DZ] = Current AEXC[DZ] | EXC[DZ]
• Next AEXC[INEX] = Current AEXC[INEX] | EXC[INEX]
For AEXC[IOP] and AEXC[UNFL], the next value is calculated by ORing the current AEXC value with
EXC bit combinations, as follows:
• Next AEXC[IOP] = Current AEXC[IOP] | EXC[BSUN | INAN | OPERR]
• Next AEXC[UNFL] = Current AEXC[UNFL] | EXC[UNFL & INEX]
6.3.4
Floating-Point Instruction Address Register (FPIAR)
The ColdFire OEP can execute integer and floating-point instructions simultaneously. As a result, the PC
value stacked by the processor in response to a floating-point exception trap may not point to the
instruction that caused the exception.
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Floating-Point Computational Accuracy
For FPU instructions that can generate exception traps, the 32-bit FPIAR is loaded with the instruction PC
address before the FPU begins execution. In case of an FPU exception, the trap handler can use the FPIAR
contents to determine the instruction that generated the exception. FMOVE to/from FPCR, FPSR, or
FPIAR and FMOVEM instructions cannot generate floating-point exceptions; therefore, they do not
modify FPIAR. A reset or a null-restore operation clears FPIAR.
6.4
Floating-Point Computational Accuracy
The FPU performs all floating-point internal operations in double-precision. It supports mixed-mode
arithmetic by converting single-precision operands to double-precision values before performing the
specified operation. The FPU converts all memory data formats to the double-precision data format and
stores the value in a floating-point register or uses it as the source operand for an arithmetic operation.
When moving a double-precision floating-point value from a floating-point data register, the FPU can
convert the data depending on the destination, as follows:
• Valid data formats for memory destination: B, W, L, S, or D
• Valid data formats for integer data register destinations: B, W, L, or S
Normally if the input operand is a denormalized number, the number must be normalized before an FPU
instruction can be executed. A denormalized input operand is converted to zero if the input denorm
exception (IDE) is disabled. If IDE is enabled, the floating-point engine traps to allow software action to
be taken by the handler.
6.4.1
Intermediate Result
All FPU calculations use an intermediate result. When the FPU performs any operation, the calculation is
carried out using double-precision inputs, and the intermediate result is calculated as if to produce infinite
precision. After the calculation is complete, any necessary rounding of the intermediate result for the
selected precision is performed and the result is stored in the destination.
Figure 6-11 shows the intermediate result format. The intermediate result’s exponent for some dyadic
operations (for example, multiply and divide) can easily overflow or underflow the 11-bit exponent of the
designated floating-point register. To simplify overflow and underflow detection, intermediate results in
the FPU maintain a 12-bit two’s complement, integer exponent. Detection of an intermediate result
overflow or underflow always converts the 12-bit exponent into a 11-bit biased exponent before being
stored in a floating-point data register. The FPU internally maintains a 56-bit mantissa for rounding
purposes. The mantissa is always rounded to 53 bits (or fewer, depending on the selected rounding
precision) before it is stored in a floating-point data register.
56-Bit Intermediate Mantissa
12-Bit Exponent
52-Bit Fraction
Integer
lsb
Guard
Round
Sticky
Figure 6-11. Intermediate Result Format
If the destination is a floating-point data register, the result is in double-precision format but may be
rounded to single-precision, if required by the rounding precision, before being stored. If the
single-precision mode is selected, the exponent value is in the correct range even if it is stored in
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double-precision format. If the destination is a memory location or an integer data register, rounding
precision is ignored. In this case, a number in the double-precision format is taken from the source
floating-point data register, rounded to the destination format precision, and then written to memory or the
integer data register.
Depending on the selected rounding mode or destination data format, the location of the lsb of the mantissa
and the locations of the guard, round, and sticky bits in the 56-bit intermediate result mantissa vary. Guard
and round bits are calculated exactly. The sticky bit creates the illusion of an infinitely wide intermediate
result. As the arrow in Figure 6-11 shows, the sticky bit is the logical OR of all bits to the right of the round
bit in the infinitely precise result. During calculation, nonzero bits generated to the right of the round bit
set the sticky bit. Because of the sticky bit, the rounded intermediate result for all required IEEE arithmetic
operations in RN mode can err by no more than one half unit in the last place.
6.4.2
Rounding the Result
The FPU supports the four rounding modes specified by the IEEE-754 standard: round-to-nearest (RN),
round-toward-zero (RZ), round-toward-plus-infinity (RP), and round-toward-minus-infinity (RM). The
RM and RP modes are often referred to as directed-rounding-modes and are useful in interval arithmetic.
Rounding is accomplished through the intermediate result. Single-precision results are rounded to a 24-bit
mantissa boundary; double-precision results are rounded to a 53-bit mantissa boundary.
The current floating-point instruction can specify rounding precision, overriding the rounding precision
specified in FPCR for the duration of the current instruction. For example, the rounding precision for
FADD is determined by FPCR, while the rounding precision for FSADD is single-precision, independent
of FPCR.
Range control helps emulate devices that support only single-precision arithmetic by rounding the
intermediate result’s mantissa to the specified precision and checking that the intermediate exponent is in
the representable range of the selected rounding precision. If the intermediate result’s exponent exceeds
the range, the appropriate underflow or overflow value is stored as the result in the double-precision format
exponent. For example, if the data format and rounding mode is single-precision RM and the result of an
arithmetic operation overflows the single-precision format, the maximum normalized single-precision
value is stored as a double-precision number in the destination floating-point data register; that is, the
unbiased 11-bit exponent is 0x0FF and the 52-bit fraction is 0xF_FFFF_E000_0000. If an infinity is the
appropriate result for an underflow or overflow, the infinity value for the destination data format is stored
as the result; that is, the exponent has the maximum value and the mantissa is zero.
Figure 6-12 shows the algorithm for rounding an intermediate result to the selected rounding precision and
destination data format. If the destination is a floating-point register, the rounding boundary is determined
by either the selected rounding precision specified by FPCR[PREC] or by the instruction itself. For
example, FSADD and FDADD specify single- and double-precision rounding regardless of FPCR[PREC].
If the destination is memory or an integer data register, the destination data format determines the rounding
boundary. If the rounded result of an operation is inexact, INEX is set in FPSR[EXC].
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Floating-Point Computational Accuracy
Entry
Guard, Round
and Sticky Bits = 0
INEX
1
Select Rounding Mode
Check Intermediate Result
RN
Pos
G and lsb = 1,
R and S = 0
or
G = 1,
R or S = 1
RM
Neg
RP
Pos
G, R,
or S = 1
N
Y
RZ
Neg
G, R,
or S = 1
Y
N
Exact Result
G,R, and S
are chopped
Add 1 to lsb
Add 1 to
lsb
Overflow = 1
Shift mantissa
right 1 bit,
Add 1 to exponent
Guard
Round
Sticky
0
0
0
Exit
Exit
Figure 6-12. Rounding Algorithm Flowchart
The 3 additional bits beyond the double-precision format, the difference between the intermediate result’s
56-bit mantissa and the storing result’s 53-bit mantissa, allow the FPU to perform all calculations as
though it were performing calculations using a compute engine with infinite bit precision. The result is
always correct for the specified destination’s data format before rounding (unless an overflow or
underflow error occurs). The specified rounding produces a number as close as possible to the infinitely
precise intermediate value and still representable in the selected precision. The tie case in Table 6-6 shows
how the 56-bit mantissa allows the FPU to meet the error bound of the IEEE specification.
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Table 6-6. Tie-Case Example
Result
Integer
52-Bit Fraction
Guard
Round
Sticky
Intermediate
x
xxx…x00
1
0
0
Rounded-to-Nearest
x
xxx…x00
0
0
0
The lsb of the rounded result does not increment even though the guard bit is set in the intermediate result.
The IEEE-754 standard specifies this way of handling ties. If the destination data format is
double-precision and there is a difference between the infinitely precise intermediate result and the
round-to-nearest result, the relative difference is 2–53 (the value of the guard bit). This error is equal to half
of the lsb’s value and is the worst case error that can be introduced with RN mode. Thus, the term one-half
unit in the last place correctly identifies the error bound for this operation. This error specification is the
relative error present in the result; the absolute error bound is equal to 2exponent x 2–53. Table 6-7 shows
the error bound for other rounding modes.
Table 6-7. Round Mode Error Bounds
Result
Integer
52-Bit Fraction
Guard
Round
Sticky
Intermediate
x
xxx…x00
1
1
1
Rounded-to-Zero
x
xxx…x00
0
0
0
The difference between the infinitely precise result and the rounded result is 2–53 + 2–54 + 2–55, which is
slightly less than 2–52 (the value of the lsb). Thus, the error bound for this operation is not more than one
unit in the last place. The FPU meets these error bounds for all arithmetic operations, providing accurate,
repeatable results.
6.5
Floating-Point Post-Processing
Most operations end with post-processing, for which the FPU provides two steps. First, FPSR[FPCC] bits
are set or cleared at the end of each arithmetic or move operation to a single floating-point data register.
FPCC bits are consistently set based on the result of the operation. Second, the FPU supports 32
conditional tests that allow floating-point conditional instructions to test floating-point conditions in the
same way that integer conditional instructions test the integer condition code. The combination of
consistently set FPCC bits and the simple programming of conditional instructions gives the processor a
highly flexible, efficient way to change program flow based on floating-point results. When the summary
for each instruction is read, it should be assumed that an instruction performs post processing, unless the
summary specifically states otherwise. The following paragraphs describe post processing in detail.
6.5.1
Underflow, Round, and Overflow
During calculation of an arithmetic result, the FPU has more precision and range than the 64-bit
double-precision format. However, the final result is a double-precision value. In some cases, an
intermediate result becomes either smaller or larger than can be represented in double-precision. Also, the
operation can generate a larger exponent or more bits of precision than can be represented in the chosen
rounding precision. For these reasons, every arithmetic instruction ends by checking for underflow,
rounding the result and checking for overflow.
At the completion of an arithmetic operation, the intermediate result is checked to see if it is too small to
be represented as a normalized number in the selected precision. If so, the underflow (UNFL) bit is set in
FPSR[EXC]. If no underflow occurs, the intermediate result is rounded according to the user-selected
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Floating-Point Post-Processing
rounding precision and mode. After rounding, the inexact bit (INEX) is set as described in Figure 6-12.
Lastly, the magnitude of the result is checked to see if it exceeds the current rounding precision. If so, the
overflow (OVFL) bit is set, and a correctly signed infinity or correctly signed largest normalized number
is returned, depending on the rounding mode.
NOTE
INEX can also be set by OVFL, UNFL, and when denormalized numbers
are encountered.
6.5.2
Conditional Testing
Unlike operation-dependent integer condition codes, an instruction either always sets FPCC bits in the
same way or does not change them at all. Therefore, instruction descriptions do not include FPCC settings.
This section describes how FPCC bits are set.
FPCC bits differ slightly from integer condition codes. An FPU operation’s final result sets or clears FPCC
bits accordingly, independent of the operation itself. Integer condition code bits N and Z have this
characteristic, but V and C are set differently for different instructions. Table 6-8 lists FPCC settings for
each data type. Loading FPCC with another combination and executing a conditional instruction can
produce an unexpected branch condition.
Table 6-8. FPCC Encodings
Data Type
N
Z
I
NAN
+ Normalized or Denormalized
0
0
0
0
– Normalized or Denormalized
1
0
0
0
+0
0
1
0
0
–0
1
1
0
0
+ Infinity
0
0
1
0
– Infinity
1
0
1
0
+ NAN
0
0
0
1
– NAN
1
0
0
1
The inclusion of the NAN data type in the IEEE floating-point number system requires each conditional
test to include FPCC[NAN] in its boolean equation. Because it cannot be determined whether a NAN is
bigger or smaller than an in-range number (since it is unordered), the compare instruction sets
FPCC[NAN] when an unordered compare is attempted. All arithmetic instructions that result in a NAN
also set the NAN bit. Conditional instructions interpret NAN being set as the unordered condition.
The IEEE-754 standard defines the following four conditions:
• Equal to (EQ)
• Greater than (GT)
• Less than (LT)
• Unordered (UN)
The standard requires only the generation of the condition codes as a result of a floating-point compare
operation. The FPU can test for these conditions and 28 others at the end of any operation affecting
condition codes. For floating-point conditional branch instructions, the processor logically combines the
4 bits of the FPCC condition codes to form 32 conditional tests, 16 of which cause an exception if an
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unordered condition is present when the conditional test is attempted (IEEE nonaware tests). The other 16
do not cause an exception (IEEE-aware tests). The set of IEEE nonaware tests is best used in one of the
following cases:
• When porting a program from a system that does not support the IEEE standard to a conforming
system
• When generating high-level language code that does not support IEEE floating-point concepts (that
is, the unordered condition).
An unordered condition occurs when one or both of the operands in a floating-point compare operation is
a NAN. The inclusion of the unordered condition in floating-point branches destroys the familiar
trichotomy relationship (greater than, equal, less than) that exists for integers. For example, the opposite
of floating-point branch greater than (FBGT) is not floating-point branch less than or equal (FBLE).
Rather, the opposite condition is floating-point branch not greater than (FBNGT). If the result of the
previous instruction was unordered, FBNGT is true, whereas both FBGT and FBLE would be false because
unordered fails both of these tests (and sets BSUN). Compiler code generators should be particularly
careful of the lack of trichotomy in the floating-point branches, because it is common for compilers to
invert the sense of conditions.
When using the IEEE nonaware tests, the user receives a BSUN exception if a branch is attempted and
FPCC[NAN] is set, unless the branch is an FBEQ or an FBNE. If the BSUN exception is enabled in FPCR,
the exception takes a BSUN trap. Therefore, the IEEE nonaware program is interrupted if an unexpected
condition occurs. Users knowledgeable of the IEEE-754 standard should use IEEE-aware tests in
programs that contain ordered and unordered conditions. Because the ordered or unordered attribute is
explicitly included in the conditional test, EXC[BSUN] is not set when the unordered condition occurs.
Table 6-9 summarizes conditional mnemonics, definitions, equations, predicates, and whether
EXC[BSUN] is set for the 32 floating-point conditional tests. The equation column lists FPCC bit
combinations for each test in the form of an equation. Condition codes with an overbar indicate cleared
bits; all other bits are set.
Table 6-9. Floating-Point Conditional Tests
Mnemonic
Definition
Equation
Predicate 1
EXC[BSUN] Set
IEEE Nonaware Tests
EQ
Equal
Z
000001
No
NE
Not equal
Z
001110
No
GT
Greater than
NAN | Z | N
010010
Yes
Not greater than
NAN | Z | N
011101
Yes
Greater than or equal
Z | (NAN | N)
010011
Yes
Not greater than or equal
NAN | (N & Z)
011100
Yes
Less than
N & (NAN | Z)
010100
Yes
NLT
Not less than
NAN | (Z | N)
011011
Yes
LE
Less than or equal
Z | (N & NAN)
010101
Yes
Not less than or equal
NAN | (N | Z)
011010
Yes
Greater or less than
NAN | Z
010110
Yes
NGL
Not greater or less than
NAN | Z
011001
Yes
GLE
Greater, less or equal
NAN
010111
Yes
NGT
GE
NGE
LT
NLE
GL
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Table 6-9. Floating-Point Conditional Tests (Continued)
Mnemonic
NGLE
Definition
Equation
Not greater, less or equal
Predicate 1
EXC[BSUN] Set
011000
Yes
NAN
IEEE-Aware Tests
EQ
Equal
Z
000001
No
NE
Not equal
Z
001110
No
OGT
Ordered greater than
NAN | Z | N
000010
No
ULE
Unordered or less or equal
NAN | Z | N
001101
No
OGE
Ordered greater than or equal
Z | (NAN | N)
000011
No
ULT
Unordered or less than
NAN | (N & Z)
001100
No
OLT
Ordered less than
N & (NAN | Z)
000100
No
UGE
Unordered or greater or equal
NAN | (Z | N)
001011
No
OLE
Ordered less than or equal
Z | (N & NAN)
000101
No
UGT
Unordered or greater than
NAN | (N | Z)
001010
No
OGL
Ordered greater or less than
NAN | Z
000110
No
UEQ
Unordered or equal
NAN | Z
001001
No
OR
Ordered
NAN
000111
No
UN
Unordered
NAN
001000
No
Miscellaneous Tests
1
6.6
F
False
False
000000
No
T
True
True
001111
No
SF
Signaling false
False
010000
Yes
ST
Signaling true
True
011111
Yes
SEQ
Signaling equal
Z
010001
Yes
SNE
Signaling not equal
Z
011110
Yes
This column refers to the value in the instruction’s conditional predicate field that specifies this test.
Floating-Point Exceptions
This section describes floating-point exceptions and how they are handled. Table 6-10 lists the vector
numbers related to floating-point exceptions. If the exception is taken pre-instruction, the PC contains the
address of the next floating-point instruction (nextFP). If the exception is taken post-instruction, the PC
contains the address of the faulting instruction (fault).
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Table 6-10. Floating-Point Exception Vectors
Vector Number
Vector Offset
Program Counter
Assignment
48
0x0C0
Fault
Floating-point branch/set on unordered condition
49
0x0C4
NextFP or Fault
Floating-point inexact result
50
0x0C8
NextFP
Floating-point divide-by-zero
51
0x0CC
NextFP or Fault
Floating-point underflow
52
0x0D0
NextFP or Fault
Floating-point operand error
53
0x0D4
NextFP or Fault
Floating-point overflow
54
0x0D8
NextFP or Fault
Floating-point input NAN
55
0x0DC
NextFP or Fault
Floating-point input denormalized number
In addition to these vectors, attempting to execute a FRESTORE instruction with a unsupported frame
value generates a format error exception (vector 14). See the FRESTORE instruction in the ColdFire
Programmer’s Reference Manual.
Attempting to execute an FPU instruction with an undefined or unsupported value in the 6-bit effective
address, the 3-bit source/destination specifier, or the 7-bit opmode generates a line-F emulator exception,
vector 11. See Table 6-23.
6.6.1
Floating-Point Arithmetic Exceptions
This section describes floating-point arithmetic exceptions; Table 6-11 lists these exceptions in order of
priority:
Table 6-11. Exception Priorities
Priority
Exception
1
Branch/set on unordered (BSUN)
2
Input Not-a-Number (INAN)
3
Input denormalized number (IDE)
4
Operand error (OPERR)
5
Overflow (OVFL)
6
Underflow (UNFL)
7
Divide-by-zero (DZ)
8
Inexact (INEX)
Most floating-point exceptions are taken when the next floating-point arithmetic instruction is encountered
(this is called a pre-instruction exception). Exceptions set during a floating-point store to memory or to an
integer register are taken immediately (post-instruction exception).
Note that FMOVE is considered an arithmetic instruction because the result is rounded. Only FMOVE
with any destination other than a floating-point register (sometimes called FMOVE OUT) can generate
post-instruction exceptions. Post-instruction exceptions never write the destination. After a
post-instruction exception, processing continues with the next instruction.
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Floating-Point Exceptions
A floating-point arithmetic exception becomes pending when the result of a floating-point instruction sets
an FPSR[EXC] bit and the corresponding FPCR[ENABLE] bit is set. A user write to the FPSR or FPCR
that causes the setting of an exception bit in FPSR[EXC] along with its corresponding exception enabled
in FPCR, leaves the FPU in an exception-pending state. The corresponding exception is taken at the start
of the next arithmetic instruction as a pre-instruction exception.
Executing a single instruction can generate multiple exceptions. When multiple exceptions occur with
exceptions enabled for more than one exception class, the highest priority exception is reported and taken.
It is up to the exception handler to check for multiple exceptions. The following multiple exceptions are
possible:
• Operand error (OPERR) and inexact result (INEX)
• Overflow (OVFL) and inexact result (INEX)
• Underflow (UNFL) and inexact result (INEX)
• Divide-by-zero (DZ) and inexact result (INEX)
• Input denormalized number (IDE) and inexact result (INEX)
• Input not-a-number (INAN) and input denormalized number (IDE)
In general, all exceptions behave similarly. If the exception is disabled when the exception condition
exists, no exception is taken, a default result is written to the destination (except for BSUN exception,
which has no destination), and execution proceeds normally.
If an enabled exception occurs, the same default result above is written for pre-instruction exceptions but
no result is written for post-instruction exceptions.
An exception handler is expected to execute FSAVE as its first floating-point instruction. This also clears
FPCR, which keeps exceptions from occurring during the handler. Because the destination is overwritten
for floating-point register destinations, the original floating-point destination register value is available for
the handler on the FSAVE state frame. The address of the instruction that caused the exception is available
in the FPIAR. When the handler is done, it should clear the appropriate FPSR exception bit on the FSAVE
state frame, then execute FRESTORE. If the exception status bit is not cleared on the state frame, the same
exception occurs again.
Alternatively, instead of executing FSAVE, an exception handler could simply clear appropriate FPSR
exception bits, optionally alter FPCR, and then return from the exception. Note that exceptions are never
taken on FMOVE to or from the status and control registers and FMOVEM to or from the floating-point
data registers.
At the completion of the exception handler, the RTE instruction must be executed to return to normal
instruction flow.
6.6.1.1
Branch/Set on Unordered (BSUN)
A BSUN results from performing an IEEE nonaware conditional test associated with the FBcc instruction
when an unordered condition is present. Any pending floating-point exception is first handled by a
pre-instruction exception, after which the conditional instruction restarts. The conditional predicate is
evaluated and checked for a BSUN exception before executing the conditional instruction. A BSUN
exception occurs if the conditional predicate is an IEEE non-aware branch and FPCC[NAN] is set. When
this condition is detected, FPSR[BSUN] is set.
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Table 6-12. BSUN Exception Enabled/Disabled Results
Condition
BSUN
Description
Exception
disabled
0
The floating-point condition is evaluated as if it were the equivalent IEEE-aware conditional
predicate. No exceptions are taken.
Exception
Enabled
1
The processor takes a floating-point pre-instruction exception.
The BSUN exception is unique in that the exception is taken before the conditional
predicate is evaluated. If the user BSUN exception handler fails to update the PC to the
instruction after the excepting instruction when returning, the exception executes again.
Any of the following actions prevent taking the exception again:
• Clearing FPSR[NAN]
• Disabling FPCR[BSUN]
• Incrementing the stored PC in the stack bypasses the conditional instruction. This
applies to situations where fall-through is desired. Note that to accurately calculate the
PC increment requires knowledge of the size of the bypassed conditional instruction.
6.6.1.2
Input Not-A-Number (INAN)
The INAN exception is a mechanism for handling a user-defined, non-IEEE data type. If either input
operand is a NAN, FPSR[INAN] is set. By enabling this exception, the user can override the default action
taken for NAN operands. Because FMOVEM, FMOVE FPCR, and FSAVE instructions do not modify
status bits, they cannot generate exceptions. Therefore, these instructions are useful for manipulating
INANs. See Table 6-13.
Table 6-13. INAN Exception Enabled/Disabled Results
Condition
INAN
Description
Exception
disabled
0
If the destination data format is single- or double-precision, a NAN is generated with a
mantissa of all ones and a sign of zero transferred to the destination. If the destination data
format is B, W, or L, a constant of all ones is written to the destination.
Exception
enabled
1
The result written to the destination is the same as the exception disabled case unless the
exception occurs on a FMOVE OUT, in which case the destination is unaffected.
6.6.1.3
Input Denormalized Number (IDE)
The input denorm bit, FPCR[IDE], provides software support for denormalized operands. When the IDE
exception is disabled, the operand is treated as zero, FPSR[INEX] is set, and the operation proceeds. When
the IDE exception is enabled and an operand is denormalized, an IDE exception is taken, but FPSR[INEX]
is not set to allow the handler to set it appropriately. See Table 6-14.
Note that the FPU never generates denormalized numbers. If necessary, software can create them in the
underflow exception handler.
Table 6-14. IDE Exception Enabled/Disabled Results
Condition
IDE
Description
Exception
disabled
0
Any denormalized operand is treated as zero, FPSR[INEX] is set, and the operation
proceeds.
Exception
enabled
1
The result written to the destination is the same as the exception disabled case unless the
exception occurs on a FMOVE OUT, in which case the destination is unaffected.
FPSR[INEX] is not set to allow the handler to set it appropriately.
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6.6.1.4
Operand Error (OPERR)
The operand error exception encompasses problems arising in a variety of operations, including errors too
infrequent or trivial to merit a specific exception condition. Basically, an operand error occurs when an
operation has no mathematical interpretation for the given operands. Table 6-15 lists possible operand
errors. When one occurs, FPSR[OPERR] is set.
Table 6-15. Possible Operand Errors
Instruction
Condition Causing Operand Error
FADD
[(+∞) + (-∞)] or [(-∞) + (+∞)]
FDIV
(0 ÷ 0) or (∞ ÷ ∞)
FMOVE OUT (to B, W, or L)
Integer overflow, source is NAN or ±∞
FMUL
One operand is 0 and the other is ±∞
FSQRT
Source is < 0 or -∞
FSUB
[(+∞) - (+∞)] or [(-∞) - (-∞)]
Table 6-16 describes results when the exception is enabled and disabled.
Table 6-16. OPERR Exception Enabled/Disabled Results
Condition OPERR
Description
Exception
disabled
0
When the destination is a floating-point data register, the result is a double-precision NAN, with
its mantissa set to all ones and the sign set to zero (positive).
For a FMOVE OUT instruction with the format S or D, an OPERR exception is impossible. With
the format B, W, or L, an OPERR exception is possible only on a conversion to integer overflow,
or if the source is either an infinity or a NAN. On integer overflow and infinity source cases, the
largest positive or negative integer that can fit in the specified destination size (B, W, or L) is
stored. In the NAN source case, a constant of all ones is written to the destination.
Exception
enabled
1
The result written to the destination is the same as for the exception disabled case unless the
exception occurred on a FMOVE OUT, in which case the destination is unaffected. If desired,
the user OPERR handler can overwrite the default result.
6.6.1.5
Overflow (OVFL)
An overflow exception is detected for arithmetic operations in which the destination is a floating-point
data register or memory when the intermediate result’s exponent is greater than or equal to the maximum
exponent value of the selected rounding precision. Overflow occurs only when the destination is S- or
D-precision format; overflows for other formats are handled as operand errors. At the end of any operation
that could potentially overflow, the intermediate result is checked for underflow, rounded, and then
checked for overflow before it is stored to the destination. If overflow occurs, FPSR[OVFL,INEX] are set.
Even if the intermediate result is small enough to be represented as a double-precision number, an
overflow can occur if the magnitude of the intermediate result exceeds the range of the selected rounding
precision format. See Table 6-17.
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Table 6-17. OVFL Exception Enabled/Disabled Results
Condition
OVFL
Description
Exception
disabled
0
The values stored in the destination based on the rounding mode defined in FPCR[MODE].
RN Infinity, with the sign of the intermediate result.
RZ Largest magnitude number, with the sign of the intermediate result.
RM For positive overflow, largest positive normalized number
For negative overflow, -∞.
RP For positive overflow, +∞
For negative overflow, largest negative normalized number.
Exception
enabled
1
The result written to the destination is the same as for the exception disabled case unless
the exception occurred on a FMOVE OUT, in which case the destination is unaffected. If
desired, the user OVFL handler can overwrite the default result.
6.6.1.6
Underflow (UNFL)
An underflow exception occurs when the intermediate result of an arithmetic instruction is too small to be
represented as a normalized number in a floating-point register or memory using the selected rounding
precision; that is, when the intermediate result exponent is less than or equal to the minimum exponent
value of the selected rounding precision. Underflow can only occur when the destination format is single
or double precision. When the destination is byte, word, or longword, the conversion underflows to zero
without causing an underflow or an operand error. At the end of any operation that could underflow, the
intermediate result is checked for underflow, rounded, and checked for overflow before it is stored in the
destination. FPSR[UNFL] is set if underflow occurs. If the underflow exception is disabled, FPSR[INEX]
is also set.
Even if the intermediate result is large enough to be represented as a double-precision number, an
underflow can occur if the magnitude of the intermediate result is too small to be represented in the
selected rounding precision. Table 6-18 shows results when the exception is enabled or disabled.
Table 6-18. UNFL Exception Enabled/Disabled Results
Condition
UNFL
Description
Exception
disabled
0
The stored result is defined below. The UNFL exception also sets FPSR[INEX] if the UNFL
exception is disabled.
RN Zero, with the sign of the intermediate result.
RZ Zero, with the sign of the intermediate result.
RM For positive underflow, + 0
For negative underflow, smallest negative normalized number.
RP For positive underflow, smallest positive normalized number
For negative underflow, - 0
Exception
enabled
1
The result written to the destination is the same as for the exception disabled case unless
the exception occurs on a FMOVE OUT, in which case the destination is unaffected. If
desired, the user UNFL handler can overwrite the default result. The UNFL exception does
not set FPSR[INEX] if the UNFL exception is enabled so the exception handler can set
FPSR[INEX] based on results it generates.
6.6.1.7
Divide-by-Zero (DZ)
Attempting to use a zero divisor for a divide instruction causes a divide-by-zero exception. When a
divide-by-zero is detected, FPSR[DZ] is set. Table 6-19 shows results when the exception is enabled or
disabled.
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Floating-Point Exceptions
Table 6-19. DZ Exception Enabled/Disabled Results
Condition
DZ
Exception
disabled
0
The destination floating-point data register is written with infinity with the sign set to the
exclusive OR of the signs of the input operands.
Exception
enabled
1
The destination floating-point data register is written as in the exception is disabled case.
6.6.1.8
Description
Inexact Result (INEX)
An INEX exception condition exists when the infinitely precise mantissa of a floating-point intermediate
result has more significant bits than can be represented exactly in the selected rounding precision or in the
destination format. If this condition occurs, FPSR[INEX] is set and the infinitely-precise result is rounded
according to Table 6-20.
Table 6-20. Inexact Rounding Mode Values
Mode
Result
RN
The representable value nearest the infinitely-precise intermediate value is the result. If the two nearest
representable values are equally near, the one whose lsb is 0 (even) is the result. This is sometimes called
round-to-nearest-even.
RZ
The result is the value closest to and no greater in magnitude than the infinitely-precise intermediate
result. This is sometimes called chop-mode, because the effect is to clear bits to the right of the rounding
point.
RM
The result is the value closest to and no greater than the infinitely-precise intermediate result (possibly -×).
RP
The result is the value closest to and no less than the infinitely-precise intermediate result (possibly +×).
FPSR[INEX] is also set for any of the following conditions:
• If an input operand is a denormalized number and the IDE exception is disabled
• An overflowed result
• An underflowed result with the underflow exception disabled
Table 6-18 shows results when the exception is enabled or disabled.
Table 6-21. INEX Exception Enabled/Disabled Results
Condition
INEX
Description
Exception
disabled
0
The result is rounded and then written to the destination.
Exception
enabled
1
The result written to the destination is the same as for the exception disabled case unless
the exception occurred on a FMOVE OUT, in which case the destination is unaffected. If
desired, the user INEX handler can overwrite the default result.
6.6.2
Floating-Point State Frames
Floating-point arithmetic exception handlers should have FSAVE as the first floating-point instruction;
otherwise, encountering another floating-point arithmetic instruction will cause the exception to be
reported again. After FSAVE executes, the handler should use FMOVEM to access floating-point data
registers, because it cannot generate further exceptions or change the FPSR.
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6-23
Note that if no intervention is needed, instead of FSAVE, the handler can simply clear the appropriate
FPCR and FPSR bits and then return from the exception.
Because the FPCR and FPSR are written in the FSAVE frame, a context switch needs only execute FSAVE
and FMOVEM for data registers. The new process needs to load data registers by using a
FMOVEM/FRESTORE sequence before it can continue.
FSAVE operations always write a 4-longword floating-point state frame that holds a 64-bit exception
operand. Figure 6-13 shows FSAVE frame contents.
31
24 23
19 18
16
15
0
Format word
Frame Format
Control Register (FPCR)
0000_0
Vector
Exception operand upper 32 bits
Exception operand lower 32 bits
Status register (FPSR)
Figure 6-13. Floating-Point State Frame Contents
Table 6-22 describes format word fields.
Table 6-22. Format Word Field Descriptions
Bits
Name
31–24
Frame
format
23–19
—
18–16
Vector
Description
Defines the format of the frame.
0x00 Null Frame (NULL)
0x05 Idle Frame (IDLE)
0xE5 Exception Frame (EXCP)
Zeros
Exception vector
000 BSUN
001 INEX
010 DZ
011 UNFL
100 OPERR
101 OVFL
110 INAN
111 IDE
When FSAVE executes, the floating-point frame reflects the FPU state at the time of the FSAVE.
Internally, the FPU can be in the NULL, IDLE, or EXCP states. Upon reset, the FPU is in NULL state, in
which all floating-point registers contain NANs and the FPCR, FPSR, and FPIAR contain zeros. The FPU
remains in NULL state until execution of an implemented floating-point instruction (except FSAVE). At
this point, the FPU transitions from NULL to an IDLE state. A FRESTORE of NULL returns the FPU to
NULL state.
EXCP state is entered as a result of a floating-point exception or an unsupported data type exception. The
vector field identifies exception types associated with the EXCP state. This field and the exception vector
taken are determined directly from the exception control (FPCR) and status (FPSR) bits. An FSAVE
instruction always clears FPCR after saving its state. Thus, after an FSAVE, a handler does not generate
further floating-point exceptions unless the handler re-enables the exceptions. FRESTORE returns FPCR
and FPSR to their previous state before entering the handler, as stored in the state frame. A handler could
alter the state frame to restore the FPU (using FRESTORE) into a different state than that saved by using
FSAVE.
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Instructions
Normally, an exception handler executes FSAVE, processes the exception, clears the exception bit in the
FSAVE state frame status word, and executes FRESTORE. If appropriate exception bits set in the status
word are not cleared, the same exception is taken again. If multiple exception bits are set in the status word,
each should be processed, cleared, and restored by their respective handlers. In this way, all exceptions are
processed in priority order.
If it is not necessary to handle multiple exceptions, the exception model can be simplified (after any
processing) by the handler manually loading FPCR and FPSR and then discarding the state frame before
executing an RTE. Given that state frames are four longwords, it may be quicker to discard the state frame
by incrementing the address pointer (often the system stack pointer, A7) by 16.
The exception operand, contained in longwords two and three of the FSAVE frame, is always the value of
the destination operand before the operation which caused the exception commenced. Thus, for dyadic
register-to-register operations, the exception operand contains the value of the destination register before
it was overwritten by the operation which caused the exception. This operand can be retrieved by an
exception handler that needs both original operands in order to process the exception.
6.7
Instructions
This section includes an instruction set summary, execution times, and differences between ColdFire and
M68000 FPU programming models. For detailed instruction descriptions, see the ColdFire Programmer’s
Reference Manual.
6.7.1
Floating-Point Instruction Overview
ColdFire instructions are 16-, 32-, or 48-bits long. The general definition of a floating-point operation and
effective addressing mode require 32 bits; some addressing modes require another 16-bit extension word.
Table 6-23 shows the minimum size instruction formats. The first word is the opword; the second is
extension word 1.
Table 6-23. Floating-Point Instruction Formats
Mnemonic
Instruction Code
FABS
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
opmode
FADD
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
opmode
FBcc
1 1 1 1 0 0 1 0 1 s
z
cond predicate
16b displacement or MS Word of 32b
LS Word of 32b Displacement
FCMP
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg 0 1 1 1 0 0 0
FDIV
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
FINT
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg 0 0 0 0 0 0 1
FINTRZ
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg 0 0 0 0 0 1 1
opmode
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Table 6-23. Floating-Point Instruction Formats (Continued)
Mnemonic
FMOVE
Instruction Code
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0
1
1 dest fmt
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
1
0
d
r
FMOVEM
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
1
1
d 1 0
r
FMUL
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
opmode
FNEG
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
opmode
FNOP
1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0
FRESTOR
E
1 1 1 1 0 0 1 1 0 1
ea
mode
ea reg
FSAVE
1 1 1 1 0 0 1 1 0 0
ea
mode
ea reg
FSQRT
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
opmode
FSUB
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg
opmode
FTST
1 1 1 1 0 0 1 0 0 0
ea
mode
ea reg
0 r/m 0 src spec dest reg 0 1 1 1 0 1 0
0
reg sel
0 0 0
src reg
0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0
0 0 0
opmode
register list
0 0 0 0 0 0 0 0
Table 6-24 defines the terminology used in Table 6-23.
Table 6-24. Instruction Format Terminology
Term
Definition
Instructions
Instructions appear in memory as sequential, 16-bit values, and are read in the above table
left to right. An instruction can have from 1 to 3 16-bit words. A shaded block indicates this
word is never used and is not present.
EA MODE
EA REG
Defines the effective address for an operand located external to the FPU. For most FPU
instructions, this field defines the location of an external source operand; for FP store
operations, it specifies the destination location.
R/M
If R/M = 0, an FPU data register is one source operand, otherwise the source operand is
specified by the EA {MODE, REG} fields.
SRC SPEC
Defines the format (byte, word, longword, single-, or double-precision) of an external
operand.
DEST REG
Specifies the destination FPU data register.
COND
PREDICATE
Defines the condition to be evaluated (EQ, NE, and so on) during the execution of the FPU
conditional branch instruction.
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Instructions
Table 6-24. Instruction Format Terminology (Continued)
Term
Definition
OPMODE
Defines the exact operation to be performed by the FPU.
SZ
Defines the length of the PC-relative displacement for the FPU conditional branch
instruction. If SZ = 0, the displacement is 16 bits, otherwise a 32-bit displacement is used.
dr
Specifies direction of the MOVE transfer. As a 0, it moves from memory to the FP; as 1, it
moves from the FP to memory.
REGISTER
LIST
Defines FPU data registers to be moved during the execution of the FMOVEM instruction.
REG SEL
6.7.2
Indicates the FPU control register to be moved during execution of an FMOVE control
register instruction.
Floating-Point Instruction Execution Timing
Table 6-25 shows the ColdFire execution times for the floating-point instructions in terms of processor
core clock cycles. Each timing entry is presented as C(r/w).
• C = The number of processor clock cycles including all applicable operand reads and writes plus
all internal core cycles required to complete instruction execution
• r = The number of operand reads
• w = The number of operand writes
NOTE
Timing assumptions are the same as those for the ColdFire ISA. See the
ColdFire Microprocessor Family Programmer’s Reference Manual.
Table 6-25. Floating-Point Instruction Execution Times1, 2, 3
Effective Address <ea>
Opcode
Format
FPn
Dn
(An)
(An)+
-(An)
(d16,An)
(d16,PC)
FABS
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
FADD
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
FBcc
<label>
—
—
—
—
—
—
2(0/0) if correct,
9(0/0) if incorrect
FCMP
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
FDIV
<ea>y,FPx
23(0/0)
23(0/0)
23(1/0)
23(1/0)
23(1/0)
23(1/0)
23(1/0)
FINT
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
FINTRZ
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
FMOVE
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
FPy,<ea>x
—
2(0/1)
2(0/1)
2(0/1)
2(0/1)
2(0/1)
—
<ea>y,FP*R
—
6(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
FP*R,<ea>x
—
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
—
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Table 6-25. Floating-Point Instruction Execution Times1, 2, 3 (Continued)
Effective Address <ea>
Opcode
Format
FPn
Dn
(An)
(An)+
-(An)
(d16,An)
(d16,PC)
<ea>y,#list
—
—
2n(2n/0)
—
—
2n(2n/0)
2n(2n/0)
#list,<ea>x
—
—
1+2n(0/2n)
—
—
1+2n(0/2n)
—
FMUL
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
FNEG
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
—
—
—
—
—
—
2(0/0)
FMOVEM 4
FNOP
FRESTORE
<ea>y
—
—
6(4/0)
—
—
6(4/0)
6(4/0)
FSAVE
<ea>x
—
—
7(0/4)
—
—
7(0/4)
—
FSQRT
<ea>y,FPx
56(0/0)
56(0/0)
56(1/0)
56(1/0)
56(1/0)
56(1/0)
56(1/0)
FSUB
<ea>y,FPx
4(0/0)
4(0/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
4(1/0)
FTST
<ea>y,FPx
1(0/0)
1(0/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1
Add 1(1/0) for an external read operand of double-precision format for all instructions except FMOVEM, and 1(0/1)
for FMOVE FPy,<ea>x when the destination is double-precision.
2 If the external operand is an integer format (byte, word, longword), there is a 4 cycle conversion time which must be
added to the basic execution time.
3 If any exceptions are enabled, the execution time for FMOVE FPy,<ea>x increases by one cycle. If the BSUN
exception is enabled, the execution time for FBcc increases by one cycle.
4 For FMOVEM, n refers to the number of registers being moved.
The ColdFire architecture supports concurrent execution of integer and floating-point instructions. The
latencies in this table define the execution time needed by the FPU. After a multi-cycle FPU instruction is
issued, subsequent integer instructions can execute concurrently with the FPU execution. For this
sequence, the floating-point instruction occupies only one OEP cycle.
6.7.3
Key Differences between ColdFire and M68000 FPU Programming
Models
This section is intended for compiler developers and developers porting assembly language routines from
the M68000 family to ColdFire. It highlights major differences between the ColdFire FPU instruction set
architecture (ISA) and the equivalent M68000 family ISA, using the MC68060 as the reference. The
internal FPU datapath width is the most obvious difference. ColdFire uses 64-bit double-precision and the
M68000 family uses 80-bit extended precision. Other differences pertain to supported addressing modes,
both across all FPU instructions as well as specific opcodes. Table 6-26 lists key differences. Because all
ColdFire implementations support instruction sizes of 48 bits or less, M68000 operations requiring larger
instruction lengths cannot be supported.
.
Table 6-26. Key Programming Model Differences
Feature
Internal datapath width
Support for fpGEN d8(An,Xi),FPx
M68000
ColdFire
80 bits
64 bits
Yes
No
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Instructions
Table 6-26. Key Programming Model Differences (Continued)
Feature
M68000
ColdFire
Support for fpGEN xxx.{w,l},FPx
Yes
No
Support for fpGEN d8(PC,Xi),FPx
Yes
No
Support for fpGEN #xxx,FPx
Yes
No
Support for fmovem (Ay)+,#list
Yes
No
Support for fmovem #list,-(Ax)
Yes
No
Support for fmovem FP Control Registers
Yes
No
Some differences affect function activation and return. M68000 subroutines typically began with
FMOVEM #list,-(a7) to save registers on the system stack, with each register occupying three longwords.
In ColdFire, each register occupies two longwords and the stack pointer must be adjusted before the
FMOVEM instruction. A similar sequence generally occurs at the end of the function, preparing to return
control to the calling routine.
The examples in Table 6-27, Table 6-28, and Table 6-29 show a M68000 operation and the equivalent
ColdFire sequence.
Table 6-27. M68000/ColdFire Operation Sequence 11
M68000
ColdFire Equivalent
fmovem.x #list,-(a7)
lea -8*n(a7),a7;allocate stack space
fmovem.d #list,(a7) ;save FPU registers
fmovem.x (a7)+,#list
fmovem.d (a7),#list ;restore FPU registers
lea 8*n(a7),a7 ;deallocate stack space
1
n is the number of FP registers to be saved/restored.
If the subroutine includes LINK and UNLK instructions, the stack space needed for FPU register storage
can be factored into these operations and LEA instructions are not required.
The M68000 FPU supports loads and stores of multiple control registers (FPCR, FPSR, and FPIAR) with
one instruction. For ColdFire, only one can be moved at a time.
For instructions that require an unsupported addressing mode, the operand address can be formed with a
LEA instruction immediately before the FPU operation. See Table 6-28.
Table 6-28. M68000/ColdFire Operation Sequence 2
M68000
ColdFire Equivalent
fadd.s label,fp2
lea label,a0;form pointer to data
fadd.s (a0),fp2
fmul.d (d8,a1,d7),fp5
lea (d8,a1,d7),a0;form pointer to data
fmul.d (a0),fp5
fcmp.l (d8,pc,d2),fp3
lea (d8,pc,d2),a0;form pointer to data
fcmp.l (a0),fp3
The M68000 FPU allows floating-point instructions to directly specify immediate values; the ColdFire
FPU does not support these types of immediate constants. It is recommended that floating-point immediate
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values be moved into a table of constants that can be referenced using PC-relative addressing or as an offset
from another address pointer. See Table 6-29.
Table 6-29. M68000/ColdFire Operation Sequence 3
M68000
ColdFire Equivalent
fadd.l #imm1,fp3
fadd.l (imm1_label,pc),fp3
fsub.s #imm2,fp4
fsub.s (imm2_label,pc),fp3
fdiv.d #imm3,fp5
fdiv.d (imm3_label,pc),fp3
align 4
imm1_label:
long imm1 ;integer longword
imm2_label:
long imm2 ;single-precision
imm3_label:
long imm3_upper,
imm3_lower ;double-precision
Finally, ColdFire and the M68000 differ in how exceptions are made pending. In the ColdFire exception
model, asserting both an FPSR exception indicator bit and the corresponding FPCR enable bit makes an
exception pending. Thus, a pending exception state can be created by loading FPSR and/or FPCR. On the
M68000, this type of pending exception is not possible.
Analysis of compiled floating-point applications indicates these differences account for most of the
changes between M68000-compatible text and the equivalent ColdFire program.
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Chapter 7
Local Memory
This chapter describes the MCF548x implementation of the ColdFire Version 4e local memory
specification. It consists of two major sections.
• Section 7.2, “SRAM Overview,” describes the MCF548x core’s local static RAM (SRAM)
implementation. It covers general operations, configuration, and initialization. It also provides
information and examples showing how to minimize power consumption when using the SRAM.
• Section 7.7, “Cache Overview,” describes the MCF548x cache implementation, including
organization, configuration, and coherency. It describes cache operations and how the cache
interfaces with other memory structures.
7.1
Interactions between Local Memory Modules
Depending on configuration information, instruction fetches and data read accesses may be sent
simultaneously to the SRAM and cache controllers. This approach is required because all three controllers
are memory-mapped devices, and the hit/miss determination is made concurrently with the read data
access. Power dissipation can be minimized by configuring the RAMBARs to mask unused address spaces
whenever possible.
If the access address is mapped into the region defined by the SRAM (and this region is not masked), the
SRAM provides the data back to the processor, and the cache data is discarded. Accesses from the SRAM
module are never cached. The complete definition of the processor’s local bus priority scheme for read
references is as follows:
if (SRAM “hits”)
SRAM supplies data to the processor
else if (data cache “hits”)
data cache supplies data to the processor
else system memory reference to access data
For data write references, the memory mapping into the local memories is resolved before the appropriate
destination memory is accessed. Accordingly, only the targeted local memory is accessed for data write
transfers.
NOTE
The two SRAMs discussed in this chapter is on the processor local bus.
There is a third 32-Kbyte SRAM on the MCF548x device. See Chapter 16,
“32-Kbyte System SRAM,” for more information.
7.2
SRAM Overview
The two 4-Kbyte, on-chip SRAM modules provide the core with pipelined, single-cycle access to memory.
Memory can be independently mapped to any 0-modulo-4K location in the 4-Gbyte address space and
configured to respond to either instruction or data accesses.
The following summarizes features of the MCF548x SRAM implementation:
• Two 4-Kbyte SRAMs, organized as 1024 x 32 bits
• Single-cycle throughput. When the pipeline is full, one access can occur per clock cycle.
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7-1
•
•
•
•
7.3
Physical location on the processor’s high-speed local bus with a user-programmed connection to
the internal instruction or data bus
Memory location programmable on any 0-modulo-4K address boundary
Byte, word, and longword address capabilities
The RAM base address registers (RAMBAR0 and RAMBAR1) define the logical base address,
attributes, and access types for the two SRAM modules.
SRAM Operation
Each SRAM module provides a general-purpose memory block that the ColdFire processor can access
with single-cycle throughput. The location of the memory block can be specified to any 0-module-4K
address boundary in the 4-Gbyte address space by RAMBARn[BA], described in Section 7.4.1, “SRAM
Base Address Registers (RAMBAR0/RAMBAR1).” The memory is ideal for storing critical code or data
structures or for use as the system stack. Because the SRAM module connects physically to the processor’s
high-speed local bus, it can service processor-initiated accesses or memory-referencing debug module
commands.
The Version 4e ColdFire processor core implements a Harvard memory architecture. Each SRAM module
may be logically connected to either the processor’s internal instruction or data bus. This logical
connection is controlled by a configuration bit in the RAM base address registers (RAMBAR0 and
RAMBAR1).
If an instruction fetch is mapped into the region defined by the SRAM, the SRAM sources the data to the
processor and any cache data is discarded. Likewise, if a data access is mapped into the region defined by
the SRAM, the SRAM services the access and the cache is not affected. Accesses from SRAM modules
are never cached, and debug-initiated references are treated as data accesses.
Note also that the SRAMs cannot be accessed by the on-chip DMAs. The on-chip system configuration
allows concurrent core and DMA execution, where the CPU can reference code or data from the internal
SRAMs or caches while performing a DMA transfer.
Accesses are attempted in the following order:
1. SRAM
2. Cache (if space is defined as cacheable)
3. System SRAM, MBAR space, or external access
7.4
SRAM Register Definition
The SRAM programming model consists of RAMBAR0 and RAMBAR1.
7.4.1
SRAM Base Address Registers (RAMBAR0/RAMBAR1)
The SRAM modules are configured through the RAMBARs, shown in Figure 7-1. Each RAMBAR holds
the base address of the SRAM. The MOVEC instruction provides write-only access to this register from
the processor. Each RAMBAR can be read or written from the debug module in a similar manner. All
undefined RAMBAR bits are reserved. These bits are ignored during writes to the RAMBAR and return
zeros when read from the debug module. The valid bits, RAMBARn[V], are cleared at reset, disabling the
SRAM modules. All other bits are unaffected.
NOTE
RAMBARn is read/write by the debug module.
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SRAM Register Definition
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
BA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
WP
D/I
0
C/I
SC
SD
UC
UD
V
0
0
0
0
0
0
0
0
0
0
0
0
R
BA
W
Reset
0
0
0
Reg
Addr
0
CPU space + 0xC04 (RAMBAR0), 0xC05 (RAMBAR1)
Figure 7-1. SRAM Base Address Registers (RAMBARn)
RAMBARn fields are described in detail in Table 7-1.
Table 7-1. RAMBARn Field Description
Bits
Name
Description
31–12
BA
Base address. Defines the SRAM module’s word-aligned base address. Each SRAM
module occupies a 4-Kbyte space defined by the contents of BA. SRAM may reside on any
4-Kbyte boundary in the 4 Gbyte address space.
11–9
—
Reserved. Should be cleared.
8
WP
Write protect. Controls read/write properties of the SRAM.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module. Any attempted write reference
generates an access error exception to the ColdFire processor core.
7
D/I
Data/instruction bus. Indicates whether SRAM is connected to the internal data or
instruction bus.
0 Data bus
1 Instruction bus
6
—
Reserved, should be cleared.
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Table 7-1. RAMBARn Field Description (Continued)
Bits
Name
Description
5
C/I
4
SC
3
SD
2
UC
1
UD
Address space masks (ASn). These fields allow certain types of accesses to be masked,
or inhibited from accessing the SRAM module. These bits are useful for power
management as described in Section 7.6, “Power Management.” In particular, C/I is
typically set.
The address space mask bits are follows:
C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each ASn bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address
space is made, it is inhibited from accessing the SRAM module and is processed like
any other non-SRAM reference.
0
V
Valid. Enables/disables the SRAM module. V is cleared at reset.
0 RAMBAR contents are not valid.
1 RAMBAR contents are valid.
The mapping of a given access into the SRAM uses the following algorithm to determine if the access hits
in the memory:
if (RAMBAR[0] = 1)
if (((access = instructionFetch) & (RAMBAR[7] = 1)) |
((access = dataReference)
& (RAMBAR[7] = 0)))
if (requested address[31:10] = RAMBAR[31:10])
if (requested address[31:n] = RAMBAR[31:n]
if (ASn of the requested type = 0)
Access is mapped to the SRAM module
if (access = read)
Read the SRAM and return the data
if (access = write)
if (RAMBAR[8] = 0)
Write the data into the SRAM
else Signal a write-protect access error
ASn refers to the five address space mask bits: C/I, SC, SD, UC, and UD.
7.5
SRAM Initialization
After a hardware reset, the contents of each SRAM module are undefined. The valid bits, RAMBARn[V],
are cleared, disabling the SRAM modules. If the SRAM requires initialization with instructions or data,
the following steps should be performed:
1. Load RAMBARn with bit 7 = 0, mapping the SRAM module to the desired location. Clearing
RAMBARn[7] logically connects the SRAM module to the processor’s data bus.
2. Read the source data and write it to the SRAM. Various instructions support this function,
including memory-to-memory move instructions and the move multiple instruction (MOVEM).
MOVEM is optimized to generate line-sized burst fetches on line-aligned addresses, so it
generally provides maximum performance.
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SRAM Initialization
3. After the data is loaded into the SRAM, it may be appropriate to revise the RAMBAR attribute
bits, including the write-protect and address-space mask fields. If the SRAM contains
instructions, RAMBAR[D/I] must be set to logically connect the memory to the processor’s
internal instruction bus.
Remember that the SRAM cannot be accessed by the on-chip DMAs. The on-chip system configuration
allows concurrent core and DMA execution, where the core can execute code out of internal SRAM or
cache during DMA access.
The ColdFire processor or an external emulator using the debug module can perform these initialization
functions.
7.5.1
SRAM Initialization Code
The code segment below initializes the SRAM using RAMBAR0. The code sets the base address of the
SRAM at 0x2000_0000 before it initializes the SRAM to zeros.
RAMBASE
RAMVALID
move.l
movec.l
EQU
0x20000000
EQU
0x00000035
#RAMBASE+RAMVALID,D0
D0, RAMBAR0
;set this variable to 0x20000000
;load RAMBASE + valid bit into D0
;load RAMBAR0 and enable SRAM
The following loop initializes the entire SRAM to zero:
lea.l
move.l
RAMBASE,A0
#1024,D0
;load pointer to SRAM
;load loop counter into D0
(A0)+
#1,D0
SRAM_INIT_LOOP
;clear 4 bytes of SRAM
;decrement loop counter
;exit if done; else continue looping
SRAM_INIT_LOOP:
clr.l
subq.l
bne.b
The following function copies the number of bytesToMove from the source (*src) to the processor’s local
SRAM at an offset relative to the SRAM base address defined by destinationOffset. The bytesToMove
must be a multiple of 16. For best performance, source and destination SRAM addresses should be
line-aligned (0-modulo-16).
; copyToCpuRam (*src, destinationOffset, bytesToMove)
RAMBASE
RAMFLAGS
EQU
EQU
lea.l
movem.l
;
;
;
;
;
;
0x20000000
0x00000035
;SRAM base address
;RAMBAR valid + mask bits
-12(a7),a7;allocate temporary space
#0x1c,(a7);store D2/D3/D4 registers
stack arguments and locations
+0
saved d2
+4
saved d3
+8
saved d4
+12
returnPc
+16
pointer to source operand
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7-5
; +20
; +24
loop:
7.6
destinationOffset
bytesToMove
move.l
movec.l
RAMBASE+RAMFLAGS,a0 ;define RAMBAR0 contents
a0,rambar0;load it
move.l
16(a7),a0;load argument defining *src
lea.l
add.l
RAMBASE,a1;memory pointer to SRAM base
20(a7),a1;include destinationOffset
move.l
asr.l
24(a7),d4;load byte count
#4,d4
;divide by 16 to convert to loop count
.align
movem.l
movem.l
lea.l
lea.l
subq.l
bne.b
4
;force loop on 0-mod-4 address
(a0),#0xf;read 16 bytes from source
#0xf,(a1);store into SRAM destination
16(a0),a0;increment source pointer
16(a1),a1;increment destination pointer
#1,d4
;decrement loop counter
loop
;if done, then exit, else continue
movem.l
lea.l
rts
(a7),#0x1c;restore d2/d3/d4 registers
12(a7),a7;deallocate temporary space
Power Management
Because processor memory references may be simultaneously sent to an SRAM module and cache, power
can be minimized by configuring RAMBAR address space masks as precisely as possible. For example,
if an SRAM is mapped to the internal instruction bus and contains instruction data, setting the ASn mask
bits associated with operand references can decrease power dissipation. Similarly, if the SRAM contains
data, setting ASn bits associated with instruction fetches minimizes power.
Table 7-2 shows typical RAMBAR configurations.
.
Table 7-2. Examples of Typical RAMBAR Settings
Data Contained in SRAM
7.7
RAMBAR[5–0]
Code only
0x2B
Data only
0x35
Both code and data
0x21
Cache Overview
This section describes the MCF548x cache implementation, including organization, configuration, and
coherency. It describes cache operations and how the cache interacts with other memory structures.
The MCF548x implements a special branch instruction cache for accelerating branches, enabled by a bit
in the cache access control register (CACR[BEC]). The branch cache is described in Section 3.2.1.1.1,
“Branch Acceleration.”
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Cache Organization
The MCF548x processor’s Harvard memory structure includes a 32-Kbyte data cache and a 32-Kbyte
instruction cache. Both are nonblocking and 4-way set-associative with a 16-byte line. The cache improves
system performance by providing single-cycle access to the instruction and data pipelines. This decouples
processor performance from system memory performance, increasing bus availability for on-chip DMA
or external devices. Figure 7-2 shows the organization and integration of the data cache.
Cache
Control
External
Bus
Control
Control Logic
Control
Data Array
ColdFire
Processor
Core
System
Integration
Unit
(SIU)
Directory Array
Data
Data
Address
Address/
Data
Data Path
Address
Address Path
Figure 7-2. Data Cache Organization
Both caches implement line-fill buffers to optimize line-sized burst accesses. The data cache supports
operation of copyback, write-through, or cache-inhibited modes. A four-entry, 32-bit buffer supports cache
line-push operations, and can be configured to defer write buffering in write-through or cache-inhibited
modes. The cache lock feature can be used to guarantee deterministic response for critical code or data
areas.
A nonblocking cache services read hits or write hits from the processor while a fill (caused by a cache
allocation) is in progress. As Figure 7-2 shows, accesses use a single bus connected to the cache.
All addresses from the processor to the cache are physical addresses. A cache hit occurs when an address
matches a cache entry. For a read, the cache supplies data to the processor. For a write, which is permitted
only to the data cache, the processor updates the cache. If an access does not match a cache entry (misses
the cache) or if a write access must be written through to memory, the cache performs a bus cycle on the
internal bus and correspondingly on the external bus by way of the system integration unit (SIU).
The cache module does not implement bus snooping; cache coherency with other possible bus masters
must be maintained in software.
7.8
Cache Organization
A four-way set associative cache is organized as four ways (levels). There are 512 sets in the 32-Kbyte
data cache with each line containing 16 bytes (4 longwords). The 32-Kbyte instruction cache has 512 sets.
Entire cache lines are loaded from memory by burst-mode accesses that cache 4 longwords of data or
instructions. All 4 longwords must be loaded for the cache line to be valid.
Figure 7-3 shows data cache organization as well as terminology used.
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7-7
Way 0
Way 1
Way 2
Way 3
•
•
•
•
•
•
Line
•
•
•
•
•
•
Set 0
Set 1
Set 510
Set 511
Cache Line Format
TAG
V
M
Longword 0
Longword 1
Longword 2
Longword 3
Where:
TAG—21-bit address tag
V—Valid bit for line
M—Modified bit for line (data cache only)
Figure 7-3. Data Cache Organization and Line Format
A set is a group of four lines (one from each level, or way), corresponding to the same index into the cache
array.
7.8.1
Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified
As shown in Table 7-3, a data cache line can be invalid, valid-unmodified (often called exclusive), or
valid-modified. An instruction cache line can be valid or invalid.
Table 7-3. Valid and Modified Bit Settings
V
M
Description
0
x
Invalid. Invalid lines are ignored during lookups.
1
0
Valid, unmodified. Cache line has valid data that matches system memory.
1
1
Valid, modified. Cache line contains most recent data, data at system memory location is
stale.
A valid line can be explicitly invalidated by executing a CPUSHL instruction.
7.8.2
The Cache at Start-Up
As Figure 7-4 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines
even though the cache may not contain the appropriate data for start up. Because reset and power-up do
not invalidate cache lines automatically, the cache should be cleared explicitly by setting
CACR[DCINVA,ICINVA] before the cache is enabled (B).
After the entire cache is flushed, cacheable entries are loaded first in way 0. If way 0 is occupied, the
cacheable entry is loaded into the same set in way 1, as shown in Figure 7-4 (D). This process is described
in detail in Section 7.9, “Cache Operation.”
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Cache Organization
Invalid (V = 0)
Valid, not modified (V = 1, M = 0)
Valid, modified (V = 1, M = 1)
A: Cache population at
start-up
Way 0Way 1Way 2Way 3
B: Cache after invalidation, C: Cache after loads in
before it is enabled
Way 0
Way 0Way 1Way 2Way 3
Way 0Way 1Way 2Way 3
At reset, cache contents
are indeterminate; V and
M may be set. The cache
should be cleared
explicitly by setting
CACR[DCINVA] before
the cache is enabled.
Setting CACR[DCINVA]
invalidates the entire
cache.
D: First load in Way 1
Way 0Way 1Way 2Way 3
Set 0
Set 511
Initial cacheable
accesses to memory-fill
positions in way 0.
A line is loaded in way 1
only if that set is full in
way 0.
Figure 7-4. Data Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern
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7.9
Cache Operation
Figure 7-5 shows the general flow of a caching operation using the 32-Kbyte data cache as an example.
The discussion in this chapter assumes a data cache. Instruction cache operations are similar except that
there is no support for writing to the cache; therefore, such notions of modified cache lines and write
allocation do not apply.
Address
31
13 12
Tag Data/Tag Reference
4 3 0
Way 3
Way 2
Way 1
Way 0
Index
Set 0
Set
Select
A[12:4]
Set 1
•
•
•
Set 511
TAG
STATUS LW0 LW1 LW2 LW3
•
•
•
TAG
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
STATUS LW0 LW1 LW2 LW3
Data
Address
A[31:13]
MUX
3
2
1
Comparator
0
Line Select
Hit 3
Hit 2
Hit 1
Hit 0
Logical OR
Hit
Figure 7-5. Data Caching Operation
The following steps determine if a data cache line is allocated for a given address:
1. The cache set index, A[12:4], selects one cache set.
2. A[31:13] and the cache set index are used as a tag reference or are used to update the cache line
tag field. Note that A[31:13] can specify 19 possible address lines that can be mapped to one of
the four ways.
3. The four tags from the selected cache set are compared with the tag reference. A cache hit occurs
if a tag matches the tag reference and the V bit is set, indicating that the cache line contains valid
data. If a cacheable write access hits in a valid cache line, the write can occur to the cache line
without having to load it from memory.
If the memory space is copyback, the updated cache line is marked modified (M = 1), because the
new data has made the data in memory out of date. If the memory location is write-through, the
write is passed on to system memory and the M bit is never used. Note that the tag does not have
TT or TM bits.
To allocate a cache entry, the cache set index selects one of the cache’s 512 sets. The cache control logic
looks for an invalid cache line to use for the new entry. If none is available, the cache controller uses a
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Cache Operation
pseudo-round-robin replacement algorithm to choose the line to be deallocated and replaced. First the
cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit
replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to
the next way.
Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking. If
CACR[DHLCK,IHLCK] = 1, the replacement pointer is restricted to way 2 or 3.
As part of deallocation, a valid, unmodified cache line is invalidated. It is consistent with system memory,
so memory does not need to be updated. To deallocate a modified cache line, data is placed in a push buffer
(for an external cache line push) before being invalidated. After invalidation, the new entry can replace it.
The old cache line may be written after the new line is read.
When a cache line is selected to host a new cache entry, the following three things happen:
1. The new address tag bits A[31:13] are written to the tag.
2. The cache line is updated with the new memory data.
3. The cache line status changes to a valid state (V = 1).
Read cycles that miss in the cache allocate normally as previously described.
Write cycles that miss in the cache do not allocate on a cacheable write-through region, but do allocate for
addresses in a cacheable copyback region.
A copyback byte, word, longword, or line write miss causes the following:
1. The cache initiates a line fill or flush.
2. Space is allocated for a new line.
3. V and M are both set to indicate valid and modified.
4. Data is written in the allocated space. No write to memory occurs.
Note the following:
• Read hits cannot change the status bits and no deallocation or replacement occurs; the data or
instructions are read from the cache.
• If the cache hits on a write access, data is written to the appropriate portion of the accessed cache
line. Write hits in cacheable, write-through regions generate an external write cycle and the cache
line is marked valid, but is never marked modified. Write hits in cacheable copyback regions do
not perform an external write cycle; the cache line is marked valid and modified (V = 1 and M = 1).
• Misaligned accesses are broken into at least two cache accesses.
• Validity is provided only on a line basis. Unless a whole line is loaded on a cache miss, the cache
controller does not validate data in the cache line.
Write accesses designated as cache-inhibited by the CACR or ACR bypass the cache and perform a
corresponding external write.
Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to
this normal operation occurs when all of the following conditions are true during a cache-inhibited read:
• The cache-inhibited fill buffer bit, CACR[DNFB], is set.
• The access is an instruction read.
• The access is normal (that is, transfer type (TT) equals 0).
In this case, an entire line is fetched and stored in the fill buffer. It remains valid there, and the cache can
service additional read accesses from this buffer until either another fill or a cache-invalidate-all operation
occurs.
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Valid cache entries that match during cache-inhibited address accesses are neither pushed nor invalidated.
Such a scenario suggests that the associated cache mode for this address space was changed. To avoid this,
it is generally recommended to use the CPUSHL instruction to push or invalidate the cache entry or set
CACR[DCINVA] to invalidate the data cache before switching cache modes.
7.9.1
Caching Modes
For every memory reference generated by the processor or debug module, a set of effective attributes is
determined based on the address and the ACRs. Caching modes determine how the cache handles an
access. A data access can be cacheable in either write-through or copyback mode; it can be cache-inhibited
in precise or imprecise modes. For normal accesses, the ACRn[CM] bit corresponding to the address of
the access specifies the caching modes. If an address does not match an ACR, the default caching mode is
defined by CACR[DDCM,IDCM]. The specific algorithm is as follows:
if (address == ACR0-address including mask)
effective attributes = ACR0 attributes
else if (address == ACR1-address including mask)
effective attributes = ACR1 attributes
else effective attributes = CACR default attributes
Addresses matching an ACR can also be write-protected using ACR[W]. Addresses that do not match
either ACR can be write-protected using CACR[DW].
Reset disables the cache and clears all CACR bits. As shown in Figure 7-4, reset does not automatically
invalidate cache entries; they must be invalidated through software.
The ACRs allow the defaults selected in the CACR to be overridden. In addition, some instructions (for
example, CPUSHL) and processor core operations perform accesses that have an implicit caching mode
associated with them. The following sections discuss the different caching accesses and their associated
cache modes.
7.9.1.1
Cacheable Accesses
If ACRn[CM] or the default field of the CACR indicates write-through or copyback, the access is
cacheable. A read access to a write-through or copyback region is read from the cache if matching data is
found. Otherwise, the data is read from memory and the cache is updated. When a line is being read from
memory for either a write-through or copyback read miss, the longword within the line that contains the
core-requested data is loaded first and the requested data is given immediately to the processor, without
waiting for the three remaining longwords to reach the cache.
The following sections describe write-through and copyback modes in detail. Note that some of this
information applies to data caches only.
7.9.1.1.1
Write-Through Mode (Data Cache Only)
Write accesses to regions specified as write-through are always passed on to the external bus, although the
cycle can be buffered, depending on the state of CACR[DESB]. Writes in write-through mode are handled
with a no-write-allocate policy—that is, writes that miss in the cache are written to the external bus but do
not cause the corresponding line in memory to be loaded into the cache. Write accesses that hit always
write through to memory and update matching cache lines. The cache supplies data to data-read accesses
that hit in the cache; read misses cause a new cache line to be loaded into the cache.
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Cache Operation
7.9.1.1.2
Copyback Mode (Data Cache Only)
Copyback regions are typically used for local data structures or stacks to minimize external bus use and
reduce write-access latency. Write accesses to regions specified as copyback that hit in the cache update
the cache line and set the corresponding M bit without an external bus access.
The cache should be flushed using the CPUSHL instruction before invalidating the cache in copyback
mode using the CINV bit. Modified cache data is written to memory only if the line is replaced because of
a miss or a CPUSHL instruction pushes the line. If a byte, word, longword, or line write access misses in
the cache, the required cache line is read from memory, thereby updating the cache. When a miss selects
a modified cache line for replacement, the modified cache data moves to the push buffer. The replacement
line is read into the cache and the push buffer contents are then written to memory.
7.9.1.2
Cache-Inhibited Accesses
Memory regions can be designated as cache-inhibited, which is useful for memory containing targets such
as I/O devices and shared data structures in multiprocessing systems. It is also important to not cache the
MCF548x memory-mapped registers. If the corresponding ACRn[CM] or CACR[DDCM] indicates
cache-inhibited, precise or imprecise, the access is cache-inhibited. The caching operation is identical for
both cache-inhibited modes, which differ only regarding recovery from an external bus error.
In determining whether a memory location is cacheable or cache-inhibited, the CPU checks
memory-control registers in the following order:
1. RAMBARs
2. ACR0 and ACR2
3. ACR1 and ACR3
4. If an access does not hit in the RAMBARs or the ACRs, the default is provided for all accesses in
CACR.
Cache-inhibited write accesses bypass the cache, and a corresponding external write is performed.
Cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the
following conditions are true:
• The cache-inhibited fill-buffer bit, CACR[DNFB], is set.
• The access is an instruction read.
• The access is normal (that is, TT = 0).
In this case, a fetched line is stored in the fill buffer and remains valid there; the cache can service
additional read accesses from this buffer until another fill occurs or a cache-invalidate-all operation occurs.
If ACRn[CM] indicates cache-inhibited mode, precise or imprecise, the controller bypasses the cache and
performs an external transfer. If a line in the cache matches the address and the mode is cache-inhibited,
the cache does not automatically push the line if it is modified, nor does it invalidate the line if it is valid.
Before switching cache mode, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] to
invalidate the entire cache.
If ACRn[CM] indicates precise mode, the sequence of read and write accesses to the region is guaranteed
to match the instruction sequence. In imprecise mode, the processor core allows read accesses that hit in
the cache to occur before completion of a pending write from a previous instruction. Writes are not
deferred past data-read accesses that miss the cache (that is, that must be read from the bus).
Precise operation forces data-read accesses for an instruction to occur only once by preventing the
instruction from being interrupted after data is fetched. Otherwise, if the processor is not in precise mode,
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7-13
an exception aborts the instruction and the data may be accessed again when the instruction is restarted.
These guarantees apply only when ACRn[CM] indicates precise mode and aligned accesses.
CPU space-register accesses using the MOVEC instruction are treated as cache-inhibited and precise.
7.9.2
Cache Protocol
The following sections describe the cache protocol for processor accesses and assumes that the data is
cacheable (that is, write-through or copyback). Note that the discussion of write operations applies to the
data cache only.
7.9.2.1
Read Miss
A processor read that misses in the cache requests the cache controller to generate a bus transaction. This
bus transaction reads the needed line from memory and supplies the required data to the processor core.
The line is placed in the cache in the valid state.
7.9.2.2
Write Miss (Data Cache Only)
The cache controller handles processor writes that miss in the data cache differently for write-through and
copyback regions. Write misses to copyback regions cause the cache line to be read from system memory,
as shown in Figure 7-6.
1. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line.
Cache Line
0x0C 0x08
MCF548x
0x04
0x00
V=0
M=0
X
2. The cache line (characters A–P) is updated from system memory, and the line is marked valid.
0x0C 0x08 0x04 0x00
V=1
ABCD EFGH IJKL MNOP M = 0
System
Memory
3. After the cache line is filled, the write that initiated the write miss (the character X) completes to 0x0B.
MCF548x
0x0C 0x08 0x04 0x00
V=1
ABCD EXGH IJKL MNOP M
=1
Figure 7-6. Write-Miss in Copyback Mode
The new cache line is then updated with write data and the M bit is set for the line, leaving it in modified
state. Write misses to write-through regions write directly to memory without loading the corresponding
cache line into the cache.
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Cache Operation
7.9.2.3
Read Hit
On a read hit, the cache provides the data to the processor core and the cache line state remains unchanged.
If the cache mode changes for a specific region of address space, lines in the cache corresponding to that
region that contain modified data are not pushed out to memory when a read hit occurs within that line.
First execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching the cache mode.
7.9.2.4
Write Hit (Data Cache Only)
The cache controller handles processor writes that hit in the data cache differently for write-through and
copyback regions. For write hits to a write-through region, portions of cache lines corresponding to the
size of the access are updated with the data. The data is also written to external memory. The cache line
state is unchanged. For copyback accesses, the cache controller updates the cache line and sets the M bit
for the line. An external write is not performed and the cache line state changes to (or remains in) the
modified state.
7.9.3
Cache Coherency (Data Cache Only)
The MCF548x provides limited cache coherency support in multiple-master environments. Both
write-through and copyback memory update techniques are supported to maintain coherency between the
cache and memory.
The cache does not support snooping (that is, cache coherency is not supported while external or DMA
masters are using the bus). Therefore, on-chip DMAs of the MCF548x cannot access local memory and
do not maintain coherency with the data cache.
7.9.4
Memory Accesses for Cache Maintenance
The cache controller performs all maintenance activities that supply data from the cache to the core,
including requests to the SIU for reading new cache lines and writing modified lines to memory. The
following sections describe memory accesses resulting from cache fill and push operations. Chapter 17,
“FlexBus,” describes required bus cycles in detail.
7.9.4.1
Cache Filling
When a new cache line is required, a line read is requested from the SIU, which generates a burst-read
transfer by indicating a line access with the size signals, SIZ[1:0].
The responding device supplies 4 consecutive longwords of data. Burst operations can be inhibited or
enabled through the burst read/write enable bits (BSTR/BSTW) in the chip-select control registers
(CSCR0–CSCR7).
SIU line accesses implicitly request burst-mode operations from memory. For more information regarding
external bus burst-mode accesses, see Chapter 17, “FlexBus.”
The first cycle of a cache-line read loads the longword entry corresponding to the requested address.
Subsequent transfers load the remaining longword entries.
A burst operation is aborted by an a write-protection fault, which is the only possible access error.
Exception processing proceeds immediately. Note that unlike Version 2 and Version 3 access errors, the
program counter stored on the exception stack frame points to the faulting instruction. See Section 3.8.2,
“Processor Exceptions.”
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7.9.4.2
Cache Pushes
Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To
reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed
in the push buffer while the new line is fetched from memory. After the bus transfer for the new line
completes, the modified cache line is written back to memory and the push buffer is invalidated.
7.9.4.2.1
Push and Store Buffers
The 16-byte push buffer reduces latency for requested new data on a cache miss by holding a displaced
modified data cache line while the new data is read from memory.
If a cache miss displaces a modified line, a miss read reference is immediately generated. While waiting
for the response, the current contents of the cache location load into the push buffer. When the burst-read
bus transaction completes, the cache controller can generate the appropriate line-write bus transaction to
write the push buffer contents into memory.
In imprecise mode, the FIFO store buffer can defer pending writes to maximize performance. The store
buffer can support as many as four entries (16 bytes maximum) for this purpose.
Data writes destined for the store buffer cannot stall the core. The store buffer effectively provides a
measure of decoupling between the pipeline’s ability to generate writes (one per cycle maximum) and the
external bus’s ability to retire those writes. In imprecise mode, writes stall only if the store buffer is full
and a write operation is on the internal bus. The internal write cycle is held, stalling the data execution
pipeline.
If the store buffer is not used (that is, store buffer disabled or cache-inhibited precise mode), external bus
cycles are generated directly for each pipeline write operation. The instruction is held in the pipeline until
external bus transfer termination is received. Therefore, each write is stalled for 5 cycles, making the
minimum write time equal to 6 cycles when the store buffer is not used. See Section 3.2.1.2, “Operand
Execution Pipeline (OEP).”
The data store buffer enable bit, CACR[DESB], controls the enabling of the data store buffer. This bit can
be set and cleared by the MOVEC instruction. DESB is zero at reset and all writes are performed in order
(precise mode). ACRn[CM] or CACR[DDCM] generates the mode used when DESB is set. Cacheable
write-through and cache-inhibited imprecise modes use the store buffer.
The store buffer can queue data as much as 4 bytes wide per entry. Each entry matches the corresponding
bus cycle it generates; therefore, a misaligned longword write to a write-through region creates two entries
if the address is to an odd-word boundary. It creates three entries if it is to an odd-byte boundary—one per
bus cycle.
7.9.4.2.2
Push and Store Buffer Bus Operation
As soon as the push or store buffer has valid data, the internal bus controller uses the next available external
bus cycle to generate the appropriate write cycles. In the event that another cache fill is required (for
example, cache miss to process) during the continued instruction execution by the processor pipeline, the
pipeline stalls until the push and store buffers are empty, then generate the required external bus
transaction.
Supervisor instructions, the NOP instruction, and exception processing synchronize the processor core and
guarantee the push and store buffers are empty before proceeding. Note that the NOP instruction should
be used only to synchronize the pipeline. The preferred no-operation function is the TPF instruction. See
the ColdFire Programmer’s Reference Manual for more information on the TPF instruction.
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Cache Operation
7.9.5
Cache Locking
Ways 0 and 1 of the data cache can be locked by setting CACR[DHLCK]; likewise, ways 0 and 1 of the
instruction cache can be locked by setting CACR[IHLCK]. If a cache is locked, cache lines in ways 0 and
1 are not subject to being deallocated by normal cache operations.
As Figure 7-7 (B and C) shows, the algorithm for updating the cache and for identifying cache lines to be
deallocated is otherwise unchanged. If ways 2 and 3 are entirely invalid, cacheable accesses are first
allocated in way 2. Way 3 is not used until the location in way 2 is occupied.
Ways 0 and 1 are still updated on write hits (D in Figure 7-7) and may be pushed or cleared only explicitly
by using specific cache push/invalidate instructions. However, new cache lines cannot be allocated in ways
0 and 1.
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Invalid (V = 0)
Valid, not modified (V = 1, M = 0)
Valid, modified (V = 1, M = 1)
A: Ways 0 and 1 are
filled. Ways 2 and 3
are invalid.
B: CACR[DHLCK] is set,
locking ways 0 and 1.
C: When a set in Way 2 is D: Write hits to ways 0
occupied, the set in way 3
and 1 update cache
is used for a cacheable
lines.
access.
Way 0Way 1Way 2Way 3
Way 0Way 1Way 2Way 3
Way 0Way 1Way 2Way 3
Way 0Way 1Way 2Way 3
After CACR[DHLCK] is
set, subsequent cache
accesses go to ways 2
and 3.
While the cache is locked
and after a position in
ways is full, the set in
Way 3 is updated.
While the cache is
locked, ways 0 and 1 can
be updated by write hits.
In this example, memory
is configured as
copyback, so updated
cache lines are marked
modified.
Set 0
Set 511
After reset, the cache is
invalidated, ways 0 and 1
are then written with data
that should not be
deallocated. Ways 0 and 1
can be filled systematically
by using the INTOUCH
instruction.
Figure 7-7. Data Cache Locking
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Cache Register Definition
7.10
Cache Register Definition
This section describes the MCF548x implementation of the Version 4e cache registers.
7.10.1
Cache Control Register (CACR)
The CACR in Figure 7-8 contains bits for configuring the cache. It can be written by the MOVEC register
instruction and can be read or written from the debug facility. A hardware reset clears CACR, which
disables the cache; however, reset does not affect the tags, state information, or data in the cache.
NOTE
CACR is read/write by the debug module.
31
30
29
28
27
26
R DEC DW DESB DDPI DHLCK
25
DDCM
24
23
DCINVA DDSP
22
21
20
0
0
0
19
18
BEC BCINVA
17
16
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ICINVA
IDSP
0
0
0
0
0
0
0
0
0
0
0
0
0
R IEC
0
DNFB IDPI
IHLCK IDCM
EUSP DF
W
Reset
0
0
Reg
Addr
0
0
0
0
0
0x002
Figure 7-8. Cache Control Register (CACR)
Table 7-4 describes CACR fields. Note that some implementations may include fields not defined here;
consult the part-specific documentation.
Table 7-4. CACR Field Descriptions
Bits
Name
Description
31
DEC
Enable data cache.
0 Cache disabled. The data cache is not operational, but data and tags are preserved.
1 Cache enabled.
30
DW
Data default write-protect. For normal operations that do not hit in the RAMBARs or ACRs, this field
defines write-protection. See Section 7.9.1, “Caching Modes.”
0 Not write protected.
1 Write protected. Write operations cause an access error exception.
29
DESB
Enable data store buffer. Affects the precision of transfers.
0 Imprecise-mode, write-through or cache-inhibited writes bypass the store buffer and generate
bus cycles directly. Section 7.9.4.2.1, “Push and Store Buffers,” describes the associated
performance penalty.
1 The four-entry FIFO store buffer is enabled; to maximize performance, this buffer defers pending
imprecise-mode, write-through or cache-inhibited writes.
Precise-mode, cache-inhibited accesses always bypass the store buffer. Precise and imprecise
modes are described in Section 7.9.1.2, “Cache-Inhibited Accesses.”
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Table 7-4. CACR Field Descriptions (Continued)
Bits
Name
Description
28
DDPI
Disable CPUSHL invalidation.
0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified, then
invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified, then
left valid.
27
DHLCK
Half-data cache lock mode
0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache
allocates the way pointed at by the counter and then increments this counter.
1 Half-cache operation. The cache allocates to the lower invalid way of levels 2 and 3; if both are
valid, the cache allocates to Way 2 if the high-order bit of the round-robin counter is zero;
otherwise, it allocates Way 3 and increments the round-robin counter. This locks the contents of
ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or cleared by
specific cache push/invalidate instructions.
26–25
DDCM
Default data cache mode. For normal operations that do not hit in the RAMBARs, ROMBARs, or
ACRs, this field defines the effective cache mode.
00 Cacheable write-through imprecise
01 Cacheable copyback
10 Cache-inhibited precise
11 Cache-inhibited imprecise
Precise and imprecise accesses are described in Section 7.9.1.2, “Cache-Inhibited Accesses.”
24
DCINVA
Data cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. Once invalidation
is complete, this bit automatically returns to 0; it is not necessary to clear it explicitly. Note the caches
are not cleared on power-up or normal reset, as shown in Figure 7-4.
0 No invalidation is performed.
1 Initiate invalidation of the entire data cache. The cache controller sequentially clears V and M bits
in all sets. Subsequent data accesses stall until the invalidation is finished, at which point, this bit
is automatically cleared. In copyback mode, the cache should be flushed using a CPUSHL
instruction before setting this bit.
23
DDSP
Data default supervisor-protect. For normal operations that do not hit in the RAMBAR, ROMBAR,
or ACRs, this field defines supervisor-protection
0 Not supervisor protected
1 Supervisor protected. User operations cause a fault
22–20
—
19
BEC
18
BCINVA
17–16
—
15
IEC
14
—
Reserved, should be cleared.
Enable branch cache.
0 Branch cache disabled. This may be useful if code is unlikely to be reused.
1 Branch cache enabled.
Branch cache invalidate. Invalidation occurs when this bit is written as a 1. Note that branch caches
are not cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate an invalidation of the entire branch cache.
Reserved, should be cleared.
Enable instruction cache
0 Instruction cache disabled. All instructions and tags in the cache are preserved.
1 Instruction cache enabled.
Reserved, should be cleared.
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Cache Register Definition
Table 7-4. CACR Field Descriptions (Continued)
Bits
Name
Description
13
DNFB
Default cache-inhibited fill buffer
0 Fill buffer does not store cache-inhibited instruction accesses (16 or 32 bits).
1 Fill buffer can store cache-inhibited accesses. The buffer is used only for normal (TT = 0)
instruction reads of a cache-inhibited region. Instructions are loaded into the buffer by a burst
access (line fill). They stay in the buffer until they are displaced; subsequent accesses may not
appear on the external bus.
Setting DNFB can cause a coherency problem for self-modifying code. If a cache-inhibited access
uses the buffer while DNFB = 1, instructions remain valid in the buffer until a cache-invalidate-all
instruction, another cache-inhibited burst, or a miss that initiates a fill. A write to the line in the fill
goes to the external bus without updating or invalidating the buffer. Subsequent reads of that written
data are serviced by the fill buffer and receive stale information.
Note: Freescale discourages the use of self-modifying code.
12
IDPI
11
IHLCK
Instruction cache half-lock.
0 Normal operation. The cache allocates to the lowest invalid way; if all ways are valid, the cache
allocates to the way pointed at by the round-robin counter and then increments this counter.
1 Half cache operation. The cache allocates to the lowest invalid way of ways 2 and 3; if both of
these ways are valid, the cache allocates to way 2 if the high-order bit of the round-robin counter
is zero; otherwise, it allocates way 3 and then increments the round-robin counter. This locks the
contents of ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or
cleared by specific cache push/invalidate instructions.
10
IDCM
Instruction default cache mode. For normal operations that do not hit in the RAMBARs or ACRs, this
field defines the effective cache mode.
0 Cacheable
1 Cache-inhibited
9
—
8
ICINVA
Instruction cache invalidate. Invalidation occurs when this bit is written as a 1. Note the caches are
not cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate invalidation of instruction cache. The cache controller sequentially clears all V bits.
Subsequent local memory bus accesses stall until invalidation completes, at which point ICINVA
is cleared automatically without software intervention. For copyback mode, use CPUSHL before
setting ICINVA.
7
IDSP
Default instruction supervisor protection bit. For normal operations that do not hit in the RAMBAR,
ROMBAR, or ACRs, this field defines supervisor-protection.
0 Not supervisor protected
1 Supervisor protected. User operations cause a fault
6
—
5
EUSP
4
DF
Disable FPU. Determines whether the FPU is enabled. See Section 6.1.1, “Overview.”
0 FPU enabled.
1 FPU disabled
3–0
—
Reserved, should be cleared.
Instruction CPUSHL invalidate disable.
0 Normal operation. A CPUSHL instruction causes the selected line to be invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be left valid.
Reserved, should be cleared.
Reserved, should be cleared.
Enable USP. Enables the use of the user stack pointer.
0 USP disabled. Core uses a single stack pointer.
1 USP enabled. Core uses separate supervisor and user stack pointers.
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7.10.2
Access Control Registers (ACR0–ACR3)
The ACRs, Figure 7-9, assign control attributes, such as cache mode and write protection, to specified
memory regions. ACR0 and ACR1 control data attributes; ACR2 and ACR3 control instruction attributes.
Registers are accessed with the MOVEC instruction with the Rc encodings in Figure 7-9.
For overlapping data regions, ACR0 takes priority; ACR2 takes priority for overlapping instruction
regions. Data transfers to and from these registers are longword transfers.
NOTE
The MBAR region should be mapped as cache-inhibited through an ACR or
the CACR.
NOTE
ACR0–ACR3 is read/write by the debug module.
31
30
29
28
R
27
26
25
24
23
22
21
BA
20
19
18
17
16
0
0
0
0
3
2
1
0
0
SP
W1
0
0
0
0
0
0
0
ADMSK
W
Reset
0
0
0
0
Reg
Addr
0
0
0
0
0
0
0
0
ACR0: 0x004; ACR1: 0x005; ACR2: 0x006; ACR3: 0x007
15
R
14
E
13
S
12
11
10
9
8
7
0
0
AMM
0
0
0
0
0
0
0
0
0
6
5
CM
4
W
Reset
0
0
Reg
Addr
0
0
0
ACR0: 0x004; ACR1: 0x005; ACR2: 0x006; ACR3: 0x007
1
Reserved in ACR2 and ACR3.
Figure 7-9. Access Control Register Format (ACRn)
Table 7-5 describes ACRn fields.
I
Table 7-5. ACRn Field Descriptions
Bits
Name
Description
31–24
BA
Base address. Compared with address bits A[31:24]. Eligible addresses that match are assigned
the access control attributes of this register.
23–16
ADMSK
Address mask. Setting a mask bit causes the corresponding address base bit to be ignored. The
low-order mask bits can be set to define contiguous regions larger than 16 Mbytes. The mask can
define multiple noncontiguous regions of memory.
15
E
Enable. Enables or disables the other ACRn bits.
0 Access control attributes disabled
1 Access control attributes enabled
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Cache Management
Table 7-5. ACRn Field Descriptions (Continued)
Bits
Name
Description
14–13
S
Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address
range or if the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
12–11
—
Reserved, should be cleared.
10
AMM
9–7
—
Reserved; should be cleared.
6–5
CM
Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are
described in Section 7.9.1.2, “Cache-Inhibited Accesses.”
00 Cacheable, write-through
01 Cacheable, copyback
10 Cache-inhibited, precise
11 Cache-inhibited, imprecise
4
—
Reserved, should be cleared.
3
SP
Supervisor protect.
0 Indicates supervisor and user mode access allowed, reset value is 0
1 Indicates only supervisor access is allowed to this address space and attempted user mode
accesses generate an access error exception
2
W
ACR0/ACR1 only. Write protect. Selects the write privilege of the memory region. ACR2[W] and
ACR3[W] are reserved.
0 Read and write accesses permitted
1 Write accesses not permitted
1–0
—
Reserved, should be cleared.
7.11
Address mask mode.
0 The ACR hit function allows control of a 16 Mbytes or greater memory region.
1 The upper 8 bits of the address and ACR are compared without a mask function. Address bits
[23:20] of the address and ACR are compared using ACR[19:16] as a mask, allowing control of
a 1–16 Mbyte memory region.
Cache Management
The cache can be enabled and configured by using a MOVEC instruction to access CACR. A hardware
reset clears CACR, disabling the cache and removing all configuration information; however, reset does
not affect the tags, state information, and data in the cache.
Set CACR[DCINVA,ICINVA] to invalidate the caches before enabling them.
The privileged CPUSHL instruction supports cache management by selectively pushing and invalidating
cache lines. The address register used with CPUSHL directly addresses the cache’s directory array. The
CPUSHL instruction flushes a cache line.
The value of CACR[DDPI,IDPI] determines whether CPUSHL invalidates a cache line after it is pushed.
To push the entire cache, implement a software loop to index through all sets and through each of the four
lines within each set (a total of 512 lines for the data cache and 1024 lines for the instruction cache). The
state of CACR[DEC,IEC] does not affect the operation of CPUSHL or CACR[DCINVA,ICINVA].
Disabling a cache by setting CACR[IEC] or CACR[DEC] makes the cache nonoperational without
affecting tags, state information, or contents.
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7-23
The contents of An used with CPUSHL specify cache row and line indexes. This differs from the 68K
family where a physical address is specified. Figure 7-11 shows the An format for the data cache. The
contents of An used with CPUSHL specify cache row and line indexes.
Figure 7-10 shows the An format for the data cache.
31
13
12
0
4
3
0
Set Index
Way Index
Figure 7-10. An Format (Data Cache)
Figure 7-11 shows the An format for the instruction cache.
31
13
12
0
4
3
0
Set Index
Way Index
Figure 7-11. An Format (Instruction Cache)
The following code example flushes the entire data cache:
_cache_disable:
nop
move.w
jsr
clr.l
movec
movec
move.l
movec
rts
#0x2700,SR
_cache_flush
d0
d0,ACR0
d0,ACR1
#0x01000000,d0
d0,CACR
;mask off IRQs
;flush the cache completely
;ACR0 off
;ACR1 off
;Invalidate and disable cache
_cache_flush:
nop
moveq.l
moveq.l
move.l
#0,d0
#0,d1
d0,a0
;synchronize—flush store buffer
;initialize way counter
;initialize set counter
;initialize cpushl pointer
cpushl
add.l
addq.l
cmpi.l
bne
dc,(a0)
#0x0010,a0
#1,d1
#511,d1
setloop
;push cache line a0
;increment set index by 1
;increment set counter
;are sets for this way done?
moveq.l
addq.l
move.l
cmpi.l
bne
rts
#0,d1
#1,d0
d0,a0
#4,d0
setloop
;set counter to zero again
;increment to next way
;set = 0, way = d0
;flushed all the ways?
setloop:
The following CACR loads assume the instruction cache has been invalidated, the default instruction
cache mode is cacheable, and the default data cache mode is copyback.
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Cache Management
dataCacheLoadAndLock:
move.l
movec
#0xa3080800,d0; enable and invalidate data cache ...
d0,cacr ; ... in the CACR
The following code preloads half of the data cache (16 Kbytes). It assumes a contiguous block of data is
to be mapped into the data cache, starting at a 0-modulo-16K address.
move.l
lea
dataCacheLoop:
tst.b
lea
subq.l
bne.b
#1024,d0 ;256 16-byte lines in 16K space
data_,a0 ; load pointer defining data area
(a0)
;touch location + load into data cache
16(a0),a0;increment address to next line
#1,d0
;decrement loop counter
dataCacheLoop;if done, then exit, else continue
; A 16K region has been loaded into ways 0 and 1 of the 32K data cache. lock it!
move.l
movec
rts
#0xaa088000,d0;set the data cache lock bit ...
d0,cacr ; ... in the CACR
align
16
The following CACR loads assume the data cache has been invalidated, the default instruction cache mode
is cacheable and the default operand cache mode is copyback.
Note that this function must be mapped into a cache inhibited or SRAM space, or these text lines will be
prefetched into the instruction cache, possibly displacing some of the 8-Kbyte space being explicitly
fetched.
instructionCacheLoadAndLock:
move.l
movec
#0xa2088100,d0;enable and invalidate the instruction
d0,cacr ;cache in the CACR
The following code segments preload half of the instruction cache (8 Kbytes). It assumes a contiguous
block of data is to be mapped, starting at a 0-modulo-8K address
move.l
#512,d0 ;512 16-byte lines in 8K space
lea
code_,a0 ;load pointer defining code area
instCacheLoop:
intouch (a0)
;touch location + load into instruction cache
; Note in the assembler we use, there is no INTOUCH opcode. The following
; is used to produce the required binary representation
cpushl
#nc,(a0) ;touch location + load into
;instruction cache
lea
16(a0),a0;increment address to next line
subq.l
#1,d0
;decrement loop counter
bne.b
instCacheLoop;if done, then exit, else continue
; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. ; lock it!
move.l
movec
rts
#0xa2088800,d0;set the instruction cache lock bit
d0,cacr ;in the CACR
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7.12
Cache Operation Summary
This section gives operational details for the cache and presents instruction and data cache-line state
diagrams.
7.12.1
Instruction Cache State Transitions
Because the instruction cache does not support writes, it supports fewer operations than the data cache. As
Figure 7-12 shows, an instruction cache line can be in one of two states, valid or invalid. Modified state is
not supported. Transitions are labeled with a capital letter indicating the previous state and a number
indicating the specific case listed in Table 7-6. These numbers correspond to the equivalent operations on
data caches, described in Section 7.12.2, “Data Cache State Transitions.”
II5—ICINVA
II6—CPUSHL & IDPI
II7—CPUSHL & IDPI
IV1—CPU read miss
IV2—CPU read hit
IV7—CPUSHL & IDPI
II1—CPU read miss
Invalid
V=0
Valid
V=1
IV5—ICINVA
IV6—CPUSHL & IDPI
Figure 7-12. Instruction Cache Line State Diagram
Table 7-6 describes the instruction cache state transitions shown in Figure 7-12.
Table 7-6. Instruction Cache Line State Transitions
Current State
Access
Invalid (V = 0)
Valid (V = 1)
Read miss
II1
Read line from memory and update cache; IV1 Read new line from memory and update cache;
supply data to processor;
supply data to processor; stay in valid state.
go to valid state.
Read hit
II2
Not possible
IV2 Supply data to processor;
stay in valid state.
Write miss
II3
Not possible
IV3 Not possible
Write hit
II4
Not possible
IV4 Not possible
Cache
invalidate
II5
No action;
stay in invalid state.
IV5 No action;
go to invalid state.
Cache
push
II6, No action;
II7 stay in invalid state.
IV6 No action;
go to invalid state.
IV7 No action;
stay in valid state.
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Cache Operation Summary
7.12.2
Data Cache State Transitions
Using the V and M bits, the data cache supports a line-based protocol allowing individual cache lines to
be invalid, valid, or modified. To maintain memory coherency, the data cache supports both write-through
and copyback modes, specified by the corresponding ACR[CM], or CACR[DDCM] if no ACR matches.
Read or write misses to copyback regions cause the cache controller to read a cache line from memory into
the cache. If available, tag and data from memory update an invalid line in the selected set. The line state
then changes from invalid to valid by setting the V bit. If all lines in the row are already valid or modified,
the pseudo-round-robin replacement algorithm selects one of the four lines and replaces the tag and data.
Before replacement, modified lines are temporarily buffered and later copied back to memory after the
new line has been read from memory.
Figure 7-13 shows the three possible data cache line states and possible processor-initiated transitions for
memory configured as copyback. Transitions are labeled with a capital letter indicating the previous state
and a number indicating the specific case; see Table 7-7.
CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL & DDPI
CI5—DCINVA
CI6—CPUSHL & DDPI
CI7—CPUSHL & DDPI
CI1—CPU read miss
Invalid
V=0
Valid
V=1
M=0
CV5—DCINVA
CV6—CPUSHL & DDPI
CI3—CPU
write miss
CD1—CPU
read miss
CD7—CPUSHL
CD5—DCINVA
& DDPI
CV3—CPU write miss
CD6—CPUSHL & DDPI
CV4—CPU write hit
Modified
V=1
M=1
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
Figure 7-13. Data Cache Line State Diagram—Copyback Mode
Figure 7-14 shows the two possible states for a cache line in write-through mode.
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DDPI
WI3—CPU write miss
WI5—DCINVA
WI6—CPUSHL & DDPI
WI1—CPU read miss
Invalid
V=0
Valid
V=1
WV5—DCINVA
WV6—CPUSHL & DDPI
Figure 7-14. Data Cache Line State Diagram—Write-Through Mode
Table 7-7 describes data cache line transitions and the accesses that cause them.
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Table 7-7. Data Cache Line State Transitions
Current State
Access
Invalid (V = 0)
Valid (V = 1, M = 0)
Modified (V = 1, M = 1)
Read
miss
(C,W)I1 Read line from
memory and update
cache;
supply data to
processor;
go to valid state.
(C,W)V1 Read new line from
memory and update
cache;
supply data to processor;
stay in valid state.
CD1 Push modified line to buffer;
read new line from memory and
update cache;
supply data to processor;
write push buffer contents to
memory;
go to valid state.
Read hit
(C,W)I2 Not possible.
(C,W)V2 Supply data to processor;
stay in valid state.
CD2 Supply data to processor;
stay in modified state.
Write
miss
(copyback)
CI3
Read line from
memory and update
cache;
write data to cache;
go to modified state.
CV3
Read new line from
memory and update
cache;
write data to cache;
go to modified state.
CD3 Push modified line to buffer;
read new line from memory and
update cache;
write push buffer contents to
memory;
stay in modified state.
Write
miss
(writethrough)
WI3
Write data to memory; WV3
stay in invalid state.
Write data to memory;
stay in valid state.
WD3 Write data to memory;
stay in modified state.
Cache mode changed for the
region corresponding to this
line. To avoid this state, execute
a CPUSHL instruction or set
CACR[DCINVA,ICINVA] before
switching modes.
Write hit
(copyback)
CI4
Not possible.
CV4
Write data to cache;
go to modified state.
CD4 Write data to cache;
stay in modified state.
Write hit
(writethrough)
WI4
Not possible.
WV4
Write data to memory and
to cache;
stay in valid state.
WD4 Write data to memory and to
cache;
go to valid state.
Cache mode changed for the
region corresponding to this
line. To avoid this state, execute
a CPUSHL instruction or set
CACR[DCINVA,ICINVA] before
switching modes.
Cache
(C,W)I5 No action;
invalidate
stay in invalid state.
(C,W)V5 No action;
go to invalid state.
CD5 No action (modified data lost);
go to invalid state.
Cache
push
(C,W)V6 No action;
go to invalid state.
CD6 Push modified line to memory;
go to invalid state.
(C,W)V7 No action;
stay in valid state.
CD7 Push modified line to memory;
go to valid state.
(C,W)I6 No action;
(C,W)I7 stay in invalid state.
The following tables present the same information as Table 7-7, organized by the current state of the cache
line. In Table 7-8 the current state is invalid.
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Cache Operation Summary
Table 7-8. Data Cache Line State Transitions (Current State Invalid)
Access
Response
Read miss
(C,W)I1 Read line from memory and update cache;
supply data to processor;
go to valid state.
Read hit
(C,W)I2 Not possible
Write miss (copyback)
CI3
Read line from memory and update cache;
write data to cache;
go to modified state.
Write miss (write-through)
WI3
Write data to memory;
stay in invalid state.
Write hit (copyback)
CI4
Not possible
Write hit (write-through)
WI4
Not possible
Cache invalidate
(C,W)I5 No action;
stay in invalid state.
Cache push
(C,W)I6 No action;
stay in invalid state.
Cache push
(C,W)I7 No action;
stay in invalid state.
In Table 7-9 the current state is valid.
Table 7-9. Data Cache Line State Transitions (Current State Valid)
Access
Response
Read miss
(C,W)V1 Read new line from memory and update cache;
supply data to processor; stay in valid state.
Read hit
(C,W)V2 Supply data to processor;
stay in valid state.
Write miss (copyback)
CV3
Read new line from memory and update cache;
write data to cache;
go to modified state.
Write miss (write-through)
WV3
Write data to memory;
stay in valid state.
Write hit (copyback)
CV4
Write data to cache;
go to modified state.
Write hit (write-through)
WV4
Write data to memory and to cache;
stay in valid state.
Cache invalidate
(C,W)V5 No action;
go to invalid state.
Cache push
(C,W)V6 No action;
go to invalid state.
Cache push
(C,W)V7 No action;
stay in valid state.
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In Table 7-10 the current state is modified.
Table 7-10. Data Cache Line State Transitions (Current State Modified)
Access
Response
Read miss
CD1 Push modified line to buffer;
read new line from memory and update cache;
supply data to processor;
write push buffer contents to memory;
go to valid state.
Read hit
CD2 Supply data to processor;
stay in modified state.
Write miss
(copyback)
CD3 Push modified line to buffer;
read new line from memory and update cache;
write push buffer contents to memory;
stay in modified state.
Write miss
(write-through)
WD3 Write data to memory;
stay in modified state.
Cache mode changed for the region corresponding to this line. To avoid this state, execute
a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
Write hit
(copyback)
CD4 Write data to cache;
stay in modified state.
Write hit
(write-through)
WD4 Write data to memory and to cache;
go to valid state.
Cache mode changed for the region corresponding to this line. To avoid this state, execute
a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
Cache invalidate
CD5 No action (modified data lost);
go to invalid state.
Cache push
CD6 Push modified line to memory;
go to invalid state.
Cache push
CD7 Push modified line to memory;
go to valid state.
7.13
Cache Initialization Code
The following example sets up the cache for FLASH or ROM space only.
move.l
#0xA30C8100,D0
movec
D0, CACR
move.l #0xFF00C000,D0
movec
//enable cache, invalidate it,
//default mode is cache-inhibited imprecise
//cache FLASH space, enable,
//ignore FC2, cacheable, writethrough
D0,ACR0
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Chapter 8
Debug Support
8.1
Introduction
This chapter describes the Revision D enhanced hardware debug support in the ColdFire Version 4. This
revision of the ColdFire debug architecture encompasses earlier revisions. An expanded set of debug
functionality is defined as Revision B (or Rev. B). The further enhanced debug architecture implemented
in the Version 4 ColdFire is known as Revision C (or Rev. C). The addition of the memory management
unit (MMU) in the Version 4e ColdFire requires corresponding enhancements to the ColdFire debug
functionality, resulting in Revision D.
8.1.1
Overview
The debug module interface is shown in Figure 8-1.
High-speed
local bus
ColdFire CPU Core
Debug Module
Trace Port
Control
PSTDDATA[7:0]
BKPT
PSTCLK
Communication Port
DSCLK, DSI, DSO
Figure 8-1. Processor/Debug Module Interface
Debug support is divided into three areas:
• Real-time trace support: The ability to determine the dynamic execution path through an
application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel
output bus that reports processor execution status and data to an external BDM emulator system.
See Section 8.3, “Real-Time Trace Support.”
• Background debug mode (BDM): Provides low-level debugging in the ColdFire processor
complex. In BDM, the processor complex is halted and a variety of commands can be sent to the
processor to access memory and registers. The external BDM emulator uses a three-pin, serial,
full-duplex channel. See Section 8.5, “Background Debug Mode (BDM),” and Section 8.4,
“Memory Map/Register Definition.”
• Real-time debug support: BDM requires the processor to be halted, which many real-time
embedded applications cannot do. Debug interrupts let real-time systems execute a unique service
routine that can quickly save key register and variable contents and return the system to normal
operation without halting. External development systems can access saved data, because the
hardware supports concurrent operation of the processor and BDM-initiated commands. In
addition, the option is provided to allow interrupts to occur. See Section 8.6, “Real-Time Debug
Support.”
The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based
on feedback from customers and third-party developers, enhancements have been added to succeeding
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generations of ColdFire cores. For Revision A, CSR[HRL] is 0. See Section 8.4.2, “Configuration/Status
Register (CSR).”
The Version 3 core implements Revision B of the debug architecture, offering more flexibility for
configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent
BDM processing while hardware breakpoint registers are active. For Revision B, CSR[HRL] is 1.
Revision C of the debug architecture more than doubles the on-chip breakpoint registers and provides an
ability to interrupt debug service routines. For Revision C, CSR[HRL] is 2.
Differences between Revision B and C are summarized as follows:
• Debug Revision B has separate PST[3:0] and DDATA[3:0] signals.
• Debug Revision C adds breakpoint registers and supports normal interrupt request service during
debug. It combines debug signals into PSTDDATA[7:0].
The addition of the memory management unit (MMU) to the baseline architecture requires corresponding
enhancements to the ColdFire debug functionality, resulting in Revision D. For Revision D, the revision
level bit, CSR[HRL], is 3.
With software support, the MMU can provide a demand-paged, virtual address environment. To support
debugging in this virtual environment, the debug enhancements are primarily related to the expansion of
the virtual address to include the 8-bit address space identifier (ASID). Conceptually, the virtual address
is expanded to a 40-bit value: the 8-bit ASID plus the 32-bit address.
The expansion of the virtual address affects two major debug functions:
• The ASID is optionally included in the specification of the hardware breakpoint registers. As an
example, the four PC breakpoint registers are each expanded by 8 bits, so that a specific ASID
value may be programmed as part of the breakpoint instruction address. Likewise, each operand
address/data breakpoint register is expanded to include an ASID value. Finally, new control
registers define if and how the ASID is to be included in the breakpoint comparison trigger logic.
• The debug module implements the concept of ownership trace in which the ASID value may be
optionally displayed as part of the real-time trace functionality. When enabled, real-time trace
displays instruction addresses on every change-of-flow instruction that is not absolute or
PC-relative. For Rev. D, this instruction address display optionally includes the contents of the
ASID, thus providing the complete instruction virtual address on these instructions.
Additionally when a Sync_PC serial BDM command is loaded from the external development
system, the processor optionally displays the complete virtual instruction address, including the
8-bit ASID value.
In addition to these ASID-related changes, the new MMU control registers are accessible by using serial
BDM commands. The same BDM access capabilities are also provided for the EMAC and FPU
programming models.
Finally, a new serial BDM command is implemented (FORCE_TA) to assist debugging when a software
error generates an incorrect memory address that hangs the external bus. The new BDM command
attempts to break this condition by forcing a bus termination.
8.2
Signal Descriptions
Table 8-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a
rising edge of the processor core’s clock signal. The standard 26-pin debug connector is shown in
Section 8.9, “Freescale-Recommended BDM Pinout.”
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Signal Descriptions
Table 8-1. Debug Module Signals
Signal
Description
DSCLK
Development Serial Clock-Internally synchronized input. (The logic level on DSCLK is validated
if it has the same value on two consecutive rising bus clock edges.) Clocks the serial
communication port to the debug module during packet transfers. Maximum frequency is
PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and
DSO changes state.
DSI
Development Serial Input -Internally synchronized input that provides data input for the serial
communication port to the debug module, once the DSCLK has been seen as high (logic 1).
DSO
Development Serial Output -Provides serial output communication for debug module responses.
DSO is registered internally. The output is delayed from the validation of DSCLK high.
BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of BKPT puts the processor
into a halted state after the current instruction completes. Halt status is reflected on processor
status/debug data signals (PSTDDATA[7:0]) as the value 0xF. If CSR[BKD] is set (disabling
normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the
processor.
PSTCLK
Processor Status Clock - Half-speed version of the processor clock. Its rising edge appears in the
center of the two-processor-cycle window of valid PSTDDATA output. See Figure 8-2. PSTCLK
indicates when the development system should sample PSTDDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK and PSTDDATA outputs from
toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing
CSR[PCD], although the external development systems must resynchronize with the PSTDDATA
output.
PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during
system reset exception processing. Table 8-4 describes PST values.
PSTDDATA[7:0]
Processor Status/Debug Data - These outputs, which change on the negative edge of PSTCLK,
indicate both processor status and captured address and data values and are discussed more
thoroughly in Section 8.2.1, “Processor Status/Debug Data (PSTDDATA[7:0]).”
Figure 8-2 shows PSTCLK timing with respect to PSTDDATA.
PSTCLK
STDDATA
Figure 8-2. PSTCLK Timing
8.2.1
Processor Status/Debug Data (PSTDDATA[7:0])
Processor status data outputs are used to indicate both processor status and captured address and data
values. They operate at half the processor’s frequency. Given that real-time trace information appears as a
sequence of 4-bit data values, there are no alignment restrictions; that is, the processor status (PST) values
and operands may appear on either nibble of PSTDDATA[7:0]. The upper nibble (PSTDDATA[7:4]) is the
more significant and yields values first.
CSR controls capturing of data values to be presented on PSTDDATA. Executing the WDDATA
instruction captures data that is displayed on PSTDDATA too. These signals are updated each processor
cycle and display two values at a time for two processor clock cycles. Table 8-2 shows the PSTDDATA
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output for the processor’s sequential execution of single-cycle instructions (A, B, C, D...). Cycle counts
are shown relative to processor frequency. These outputs indicate the current processor pipeline status and
are not related to the current bus transfer.
Table 8-2. PSTDDATA: Sequential Execution of Single-Cycle Instructions
Cycles
PSTDDATA[7:0]
T+0, T+1
{PST for A, PST for B}
T+2, T+3
{PST for C, PST for D}
T+4, T+5
{PST for E, PST for F}
The signal timing for the example in Table 8-2 is shown in Figure 8-3.
T+0
T+1
T+2
T+3
T+4
T+5
T+6
Processor Clock
PSTCLK
{A, B}
PSTDDATA
{C, D}
{E, F}
Figure 8-3. PSTDDATA: Single-Cycle Instruction Timing
Table 8-3 shows the case where a PSTDDATA module captures a memory operand on a simple load
instruction: mov.l <mem>,Rx.
Table 8-3. PSTDDATA: Data Operand Captured
Cycle
T
PSTDDATA[7:0]
{PST for mov.l, PST marker for captured operand) = {0x1, 0xB}
T+1
{0x1, 0xB}
T+2
{Operand[3:0], Operand[7:4]}
T+3
{Operand[3:0], Operand[7:4]}
T+4
{Operand[11:8], Operand[15:12]}
T+5
{Operand[11:8], Operand[15:12]}
T+6
{Operand[19:16], Operand[23:20]}
T+7
{Operand[19:16], Operand[23:20]}
T+8
{Operand[27:24], Operand[31:28]}
T+9
{Operand[27:24], Operand[31:28]}
T+10
(PST for next instruction)
T+11
(PST for next instruction,...)
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Real-Time Trace Support
NOTE
A PST marker and its data display are sent contiguously. Except for this
transmission, the IDLE status (0x0) can appear anytime. Again, given that
real-time trace information appears as a sequence of 4-bit values, there are
no alignment restrictions. That is, PST values and operands may appear on
either nibble of PSTDDATA.
8.3
Real-Time Trace Support
Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire
solution is to include a parallel output port providing encoded processor status and data to an external
development system. This 8-bit port is partitioned into two consecutive 4-bit nibbles. Each nibble can
either transmit information concerning the processor’s execution status (PST) or debug data (DDATA).
The processor status may not be related to the current bus transfer, due to the decoupling FIFOs.
External development systems can use PSTDDATA outputs with an external image of the program to
completely track the dynamic execution path. This tracking is complicated by any change in flow,
especially when branch target address calculation is based on the contents of a program-visible register
(variant addressing). PSTDDATA outputs can be configured to display the target address of such
instructions in sequential nibble increments across multiple processor clock cycles, as described in
Section 8.3.1, “Begin Execution of Taken Branch (PST = 0x5).” Four 32-bit storage elements form a FIFO
buffer connecting the processor’s high-speed local bus to the external development system through
PSTDDATA[7:0]. The buffer captures branch target addresses and certain data values for eventual display
on the PSTDDATA port, two nibbles at a time starting with the least significant bit (lsb).
Execution speed is affected only when three storage elements contain valid data to be dumped to the
PSTDDATA port. This occurs only when two values are captured simultaneously in a read-modify-write
operation. The core stalls until two FIFO entries are available.
Table 8-4 shows the encoding of these signals.
Table 8-4. Processor Status Encoding
PST[3:0]
Definition
Hex
Binary
0x0
0000
Continue execution. Many instructions execute in one processor cycle. If an instruction requires
more clock cycles, subsequent clock cycles are indicated by driving PSTDDATA outputs with this
encoding.
0x1
0001
Begin execution of one instruction. For most instructions, this encoding signals the first clock cycle
of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA
instructions, generate different encodings.
0x2
0010
Begin execution of two instructions. For superscalar instruction dispatches, this encoding signals the
first clock cycle of the simultaneous instructions’ execution.
0x3
0011
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor
to enter user mode. If the display of the ASID is enabled (CSR[3] = 1), the following occurs:
• The 8-bit ASID follows the instruction address; that is, the PSTDDATA sequence is {0x3, 0x5,
marker, instruction address, 0x8, ASID}, where 0x8 is the ASID data marker.
• Whenever the current ASID is loaded by the privileged MOVEC instruction, the ASID is displayed
on PSTDDATA. The resulting PSTDDATA sequence for the MOVEC instruction is then {0x1, 0x8,
ASID}, where the 0x8 is the data marker for the ASID.
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Table 8-4. Processor Status Encoding (Continued)
PST[3:0]
Definition
Hex
Binary
0x4
0100
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for
debug or performance analysis. WDDATA lets the core write any operand (byte, word, or longword)
directly to the PSTDDATA port, independent of debug module configuration. When WDDATA is
executed, a value of 0x4 is signaled, followed by the appropriate marker, and then the data transfer
on the PSTDDATA port. Transfer length depends on the WDDATA operand size.
0x5
0101
Begin execution of taken branch or SYNC_PC command. For some opcodes, a branch target
address may be displayed on PSTDDATA depending on the CSR settings. CSR also controls the
number of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble
that begins the data output. See Section 8.3.1, “Begin Execution of Taken Branch (PST = 0x5).” Also
indicates that the SYNC_PC command has been issued.
0x6
0110
Begin execution of instruction plus a taken branch. The processor completes execution of a taken
conditional branch instruction and simultaneously starts executing the target instruction. This is
achieved through branch folding.
0x7
0111
Begin execution of return from exception (RTE) instruction.
0x8–0xB
1000–1011 Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The
value is driven onto the PSTDDATA port one cycle before the data is displayed.
0x8 Begin 1-byte transfer on PSTDDATA.
0x9 Begin 2-byte transfer on PSTDDATA.
0xA Begin 3-byte transfer on PSTDDATA.
0xB Begin 4-byte transfer on PSTDDATA.
0xC
1100
Normal exception processing. Exceptions that enter emulation mode (debug interrupt or optionally
trace) generate a different encoding, as described below. Because the 0xC encoding defines a
multiple-cycle mode, PSTDDATA outputs are driven with 0xC until exception processing completes.
0xD
1101
Emulator mode exception processing. Displayed during emulation mode (debug interrupt or
optionally trace). Because this encoding defines a multiple-cycle mode, PSTDDATA outputs are
driven with 0xD until exception processing completes.
0xE
1110
A breakpoint state change causes this encoding to assert for one cycle only followed by the trigger
status value. If the processor stops waiting for an interrupt, the encoding is asserted for multiple
cycles. See Section 8.3.2, “Processor Stopped or Breakpoint State Change (PST = 0xE).”
0xF
1111
Processor is halted. Because this encoding defines a multiple-cycle mode, the PSTDDATA outputs
display 0xF until the processor is restarted or reset. (see Section 8.5.1, “CPU Halt”)
8.3.1
Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed
on PSTDDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
which is indicated by the PST marker value immediately preceding the PSTDDATA nibble that begins the
data output.
Multiple byte DDATA values are displayed in least-to-most-significant order. The processor captures only
those target addresses associated with taken branches which use a variant addressing mode, that is, RTE
and RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing
modes, and all exception vectors.
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Real-Time Trace Support
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
change-of-flow operations, the V4 microarchitecture uses the debug pins to output the following sequence
of information on two successive processor clock cycles:
1. Use PSTDDATA (0x5) to identify that a taken branch is executed.
2. Optionally signal the target address to be displayed sequentially on the PSTDDATA pins.
Encodings 0x9–0xB identify the number of bytes displayed.
3. The new target address is optionally available on subsequent cycles using the PSTDDATA port.
The number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes,
where the encoding is 0x9, 0xA, and 0xB, respectively).
Another example of a variant branch instruction would be a JMP (A0) instruction. Figure 8-4 shows when
the PSTDDATA outputs that indicate when a JMP (A0) executed, assuming the CSR was programmed to
display the lower 2 bytes of an address.
Processor Clock
PSTCLK
PSTDDATA
0x59
A0[3–0,7–4]
A0[11–8,15–12]
Figure 8-4. Example JMP Instruction Output on PSTDDATA
PSTDDATA is driven two nibbles at a time with a 0x59; 0x5 indicates a taken branch and the marker value
0x9 indicates a 2-byte address. Thus, the subsequent 4 nibbles display the lower 2 bytes of address register
A0 in least-to-most-significant nibble order. The PSTDDATA output after the JMP instruction continues
with the next instruction.
8.3.2
Processor Stopped or Breakpoint State Change (PST = 0xE)
The 0xE encoding is generated either as a one- or multiple-cycle issue as follows:
• When the core is stopped by a STOP instruction, this encoding appears in multiple-cycle format.
The ColdFire processor remains stopped until an interrupt occurs; thus, PSTDDATA outputs
display 0xE until stopped mode is exited.
• When a breakpoint status change is to be output on PSTDDATA, 0xE is displayed for one cycle,
followed immediately with the 4-bit value of the current trigger status, where the trigger status is
left justified rather than in the CSR[BSTAT] description. Section 8.4.2, “Configuration/Status
Register (CSR),” shows that status is right justified. That is, the displayed trigger status on
PSTDDATA after a single 0xE is as follows:
— 0x0 = no breakpoints enabled
— 0x2 = waiting for level-1 breakpoint
— 0x4 = level-1 breakpoint triggered
— 0xA = waiting for level-2 breakpoint
— 0xC = level-2 breakpoint triggered
Thus, 0xE can indicate multiple events, based on the next value, as Table 8-5 shows.
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Freescale Semiconductor
8-7
Table 8-5. 0xE Status Posting
PSTDDATA Stream Includes
8.3.3
Result
{0xE, 0x2}
Breakpoint state changed to waiting for level-1 trigger
{0xE, 0x4}
Breakpoint state changed to level-1 breakpoint triggered
{0xE, 0xA}
Breakpoint state changed to waiting for level-2 trigger
{0xE, 0xC}
Breakpoint state changed to level-2 breakpoint triggered
{0xE, 0xE}
Stopped mode.
Processor Halted (PST = 0xF)
PST is 0xF when the processor is halted (see Section 8.5.1, “CPU Halt”). Because this encoding defines a
multiple-cycle mode, the PSTDDATA outputs display 0xF until the processor is restarted or reset.
Therefore, PSTDDATA[7:0] continuously are 0xFF.
NOTE
HALT can be distinguished from a data output 0xFF by counting 0xFF
occurrences on PSTDDATA. Because data always follows a marker (0x8,
0x9, 0xA, or 0xB), the longest occurrence in PSTDDATA of 0xFF in a data
output is four.
Two scenarios exist for data 0xFFFF_FFFF:
• The B marker occurs on the most-significant nibble of PSTDDATA with the data of 0xFF
following:
PSTDDATA[7:0]
0xBF
0xFF
0xFF
0xFF
0xFX (X indicates that the next PST value is guaranteed to not be 0xF.)
• The B marker occurs on the least-significant nibble of PSTDDATA with the data of 0xFF
following:
PSTDDATA[7:0]
0xYB
0xFF
0xFF
0xFF
0xFF
0xXY (X indicates the PST value is guaranteed not to be 0xF, and Y signifies a PSTDDATA
value that doesn’t affect the 0xFF count.)
NOTE
As the result of the above, a count of at least nine or more sequential single
0xF values or five or more sequential 0xFF values indicates the HALT
condition.
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Memory Map/Register Definition
8.4
Memory Map/Register Definition
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains 19 registers to support the required functionality. These registers
are also accessible from the processor’s supervisor programming model by executing the WDEBUG
instruction (write only). Thus, the breakpoint hardware in the debug module can be read or written by the
external development system using the debug serial interface or written by the operating system running
on the processor core. Software is responsible for guaranteeing that accesses to these resources are
serialized and logically consistent. Hardware provides a locking mechanism in the CSR to allow the
external development system to disable any attempted writes by the processor to the breakpoint registers
(setting CSR[IPW]). BDM commands must not be issued if the WDEBUG instruction is used to access
debug module registers or the resulting behavior is undefined.
These registers, shown in Figure 8-5, are treated as 32-bit quantities, regardless of the number of
implemented bits.
31
31
31
31
15
7
15
15
0
AATR
Address attribute trigger register
ABLR
ABHR
Address low breakpoint register
Address high breakpoint register
AATR1
Address 1 attribute trigger register
0
7
15
0
0
ABLR1 Address low breakpoint 1 register
ABHR1 Address high breakpoint 1 register
31
31
31
31
15
15
15
15
7
0
BAAR
BDM address attributes register
CSR
Configuration/status register
DBR
DBMR
Data breakpoint register
Data breakpoint mask register
0
0
0
Data breakpoint 1 register
DBR1
DBMR1 Data breakpoint mask 1 register
31
31
31
15
15
15
0
PBR
PBR1
PBR2
PBR3
PBMR
PC breakpoint register
PC breakpoint 1 register
PC breakpoint 2 register
PC breakpoint 3 register
PC breakpoint mask register
TDR
Trigger definition register
XTDR
Extended trigger definition register
0
0
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
All debug control registers are writable from the external development system or the CPU via the WDEBUG
instruction.
CSR is write-only from the programming model. It can be read from and written to through the BDM port.
CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and
Figure 8-5. Debug Programming Model
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Freescale Semiconductor
8-9
The registers in Table 8-7 are accessed through the BDM port by BDM commands, WDMREG and RDMREG,
described in Section 8.5.3.3, “Command Set Descriptions.” These commands contain a 5-bit field, DRc,
that specifies the register, as shown in Table 8-6.
Table 8-6. BDM/Breakpoint Registers
DRc[4–0]
0x00
0x01–0x05
Register Name
Configuration/status register1
Reserved
Initial State
Section/
Page
CSR
0x0020_0000
8.4.2/8-11
—
—
—
0x04
PC breakpoint ASID control
PBAC
—
8.4.3/8-14
0x05
BDM address attribute register
BAAR
0x0000_0005
8.4.4/8-15
0x06
Address attribute trigger register
AATR
0x0000_0005
8.4.5/8-16
0x07
Trigger definition register
TDR
0x0000_0000
8.4.6/8-17
0x08
Program counter breakpoint register
PBR
—
8.4.7/8-20
0x09
Program counter breakpoint mask register
PBMR
—
8.4.7/8-20
—
—
—
0x0A–0x0B Reserved
0x0C
Address breakpoint high register
ABHR
—
8.4.8/8-21
0x0D
Address breakpoint low register
ABLR
—
8.4.8/8-21
0x0E
Data breakpoint register
DBR
—
8.4.9/8-22
0x0F
Data breakpoint mask register
DBMR
—
8.4.9/8-22
—
—
—
PBASID
—
8.4.10/8-24
—
—
—
0x10–0x153 Reserved
1
Abbreviation
0x14
PC breakpoint ASID register
0x15
Reserved
0x16
Address attribute trigger register 1
AATR1
0x0000_0005
8.4.5/8-16
0x17
Extended trigger definition register
XTDR
0x0000_0000
8.4.11/8-25
0x18
Program counter breakpoint 1 register
PBR1
0x0000_0000
8.4.7/8-20
0x19
Reserved
—
—
—
0x1A
Program counter breakpoint register 2
PBR2
0x0000_0000
8.4.7/8-20
0x1B
Program counter breakpoint register 3
PBR3
0x0000_0000
8.4.7/8-20
0x1C
Address high breakpoint register 1
ABHR1
—
8.4.8/8-21
0x1D
Address low breakpoint register 1
ABLR1
—
8.4.8/8-21
0x1E
Data breakpoint register 1
DBR1
—
8.4.9/8-22
0x1F
Data breakpoint mask register 1
DBMR1
—
8.4.9/8-22
CSR is write-only from the programming model. It can be read or written through the BDM port using the
RDMREG and WDMREG commands.
These registers are also accessible from the processor’s supervisor programming model through the
execution of the WDEBUG instruction. Thus, the external development system and the operating system
running on the processor core can access the breakpoint hardware. It is the responsibility of the software
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Memory Map/Register Definition
to guarantee that all accesses to these resources are serialized and logically consistent. The hardware
provides a locking mechanism in the CSR to allow the external development system to disable any
attempted writes by the processor to the breakpoint registers (setting IPW = 1). BDM commands must not
be issued if the ColdFire processor is accessing debug module registers with the WDEBUG instruction or
the resulting behavior is undefined.
The ColdFire debug architecture supports a number of hardware breakpoint registers, that can be
configured into single- or double-level triggers based on the PC or operand address ranges with an optional
inclusion of specific data values. With the addition of the MMU capabilities, the breakpoint specifications
must be expanded to optionally include the address space identifier (ASID) in these user-programmable
virtual address triggers.
The core includes four PC breakpoint triggers and two sets of operand address breakpoint triggers, each
with two independent address registers (to allow specification of a range) and a data breakpoint with
masking capabilities. Core breakpoint triggers are accessible through the serial BDM interface or written
through the supervisor programming model using the WDEBUG instruction.
Two ASID-related registers (PBAC and PBASID) are added for the PC breakpoint qualification, and two
existing registers (AATR and AATR1) are expanded for the address breakpoint qualification.
8.4.1
Revision A Shared Debug Resources
In the Revision A implementation of the debug module, certain hardware structures are shared between
BDM and breakpoint functionality, as shown in Table 8-7.
Table 8-7. Rev. A Shared BDM/Breakpoint Hardware
Register
BDM Function
Breakpoint Function
AATR
Bus attributes for all memory commands
Attributes for address breakpoint
ABHR
Address for all memory commands
Address for address breakpoint
DBR
Data for all BDM write commands
Data for data breakpoint
Thus, loading a register to perform a specific function that shares hardware resources is destructive to the
shared function. For example, a BDM command to access memory overwrites an address breakpoint in
ABHR. A BDM write command overwrites the data breakpoint in DBR.
Revision B added hardware registers to eliminate these shared functions. The BAAR is used to specify bus
attributes for BDM memory commands and has the same format as the LSB of the AATR. Note that the
registers containing the BDM memory address and the BDM data are not program visible.
8.4.2
Configuration/Status Register (CSR)
The configuration/status register (CSR) defines the debug configuration for the processor and memory
subsystem and contains status information from the breakpoint logic. CSR is write-only from the
programming model. CSR is accessible in supervisor mode as debug control register 0x00 using the
WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands. It can
be read from and written to through the BDM port.
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Freescale Semiconductor
8-11
31
R
30
29
28
BSTAT
27
26
25
24
FOF TRG HALT
23
22
BKPT
21
20
HRL
19
0
18
17
16
BKD0 PCD0 IPW0
W
Reset
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
NPL
0
0
0
0
0
0
0
0
0
0
R MAP TRC EMU
DDC
UHE
BTB
SSM OTE
W
Reset
0
0
0
0
0
0
0
Reg
Addr
0
0
0
CPU + 0x00
Figure 8-6. Configuration/Status Register (CSR)
Table 8-8 describes CSR fields.
Table 8-8. CSR Field Descriptions
Bits
Name
Description
31–28
BSTAT
Breakpoint status. Provides read-only status information concerning hardware breakpoints. Also
output on PSTDDATA when it is not displaying PST or other processor data. BSTAT is cleared by a
TDR or XTDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1
breakpoint is triggered and the level-2 breakpoint is disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
27
FOF
Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM.
26
TRG
Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and
forced entry into BDM. Reset, and the debug GO command clear TRG.
25
HALT
Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset,
and the debug GO command clear HALT.
24
BKPT
Breakpoint assert. If BKPT is set, BKPT is asserted, forcing the processor into BDM. Reset, and
the debug GO command clear BKPT.
23–20
HRL
Hardware revision level. Indicates the level of debug module functionality. An emulator could use
this information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A)
0001 Revision B
0010 Revision C
0011 Revision D
19
—
Reserved, should be cleared.
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Memory Map/Register Definition
Table 8-8. CSR Field Descriptions (Continued)
Bits
Name
Description
18
BKD
Breakpoint disable. Used to disable the normal BKPT input functionality and to allow the assertion
of BKPT to generate a debug interrupt.
0 Normal operation
1 BKPT is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the processor.
The processor makes this interrupt request pending until the next sample point, when the
exception is initiated. In the ColdFire architecture, the interrupt sample point occurs once per
instruction. There is no support for nesting debug interrupts.
17
PCD
PSTCLK disable. Setting PCD disables generation of PSTCLK and PSTDDATA outputs and forces
them to remain quiescent.
16
IPW
Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s
programming model registers. IPW can be modified only by commands from the external
development system.
15
MAP
Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT = 10,
TM = 101 or 110. The internal SRAM and caches are disabled.
14
TRC
Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a
trace exception occurs. If TRC=0, the processor enters supervisor mode.
13
EMU
Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 8.6.1.1, “Emulator Mode.”
12–11
DDC
Debug data control. Controls operand data capture for PSTDDATA, which displays the number of
bytes defined by the operand reference size before the actual data; byte displays 8 bits, word
displays 16 bits, and long displays 32 bits (one nibble at a time across multiple clock cycles). See
Table 8-4.
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
10
UHE
User halt enable. Selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
9–8
BTB
Branch target bytes. Defines the number of bytes of branch target address PSTDDATA displays.
00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
See Section 8.3.1, “Begin Execution of Taken Branch (PST = 0x5).”
7
—
Reserved, should be cleared.
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Freescale Semiconductor
8-13
Table 8-8. CSR Field Descriptions (Continued)
Bits
Name
Description
6
NPL
Non-pipelined mode. Determines whether the core operates in pipelined or mode.
0 Pipelined mode
1 Non-pipelined mode. The processor effectively executes one instruction at a time with no overlap.
This adds at least 5 cycles to the execution time of each instruction. Superscalar instruction
dispatch is disabled when operating in this mode. Given an average execution latency of 1.6,
throughput in non-pipeline mode would be 6.6, approximately 25% or less of pipelined
performance.
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering
instruction executes. In normal pipeline operation, the occurrence of an address or data breakpoint
trigger is imprecise. In non-pipeline mode, triggers are always reported before the next instruction
begins execution and trigger reporting can be considered precise.
An address or data breakpoint should always occur before the next instruction begins execution.
Therefore, the occurrence of the address/data breakpoints should be guaranteed.
5
—
4
SSM
Single-step mode. Setting SSM puts the processor in single-step mode.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any
BDM command can be executed. On receipt of the GO command, the processor executes the
next instruction and halts again. This process continues until SSM is cleared.
3
OTE
Ownership-trace enable.
1 The display of the ASID on the PSTDDATA outputs by entering in user mode, by loading the
ASID by a MOVEC, or by executing a BDM SYNC_PC command.
3–0
—
8.4.3
Reserved, should be cleared.
Reserved, should be cleared.
PC Breakpoint ASID Control Register (PBAC)
The PBAC configures the breakpoint qualification for each PC breakpoint register (PBR, PBR1, PBR2,
and PBR3). Four bits are dedicated for each breakpoint register and specify how the ASID is used in PC
breakpoint qualification.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
PBR3AC
PBR2AC
PBR1AC
PBRAC
W
Reset
Reg
Addr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU + 0x0A
Figure 8-7. PC Breakpoint ASID Control Register (PBAC)
PBR3AC, PBR2AC, PBR1AC, and PBRAC apply to PBR3, PBR2, PBR1, and PBR, respectively, and are
functionally identical. They enable or disable ASID, supervisor mode, and user mode breakpoint
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Memory Map/Register Definition
qualification. Reset clears these fields, disabling qualifications and defaulting to the Revision C debug
module functionality.
Table 8-9. PBAC Field Descriptions
Bits
Name
31-16
—
15–12
PBR3AC
11–8
PBR2AC
7–4
PBR1AC
3–0
PBRAC
8.4.4
Description
Reserved, should be cleared.
PBRn ASID control. Corresponds to the ASID control associated with PBRn. Determines
whether the ASID is included in the PC breakpoint comparison and whether the operating
mode (supervisor or user) is included in the comparison logic.
x00x No ASID qualification; no mode qualification
x010 No ASID qualification; user mode qualification enabled
x011 No ASID qualification; supervisor mode qualification enabled
x10x ASID qualification enabled; no mode qualification
x110 ASID qualification enabled; user mode qualification enabled
x111 ASID qualification enabled; supervisor mode qualification enabled
BDM Address Attribute Register (BAAR)
The BAAR defines the address space for memory-referencing BDM commands. To maintain
compatibility with Revision A, BAAR is loaded with any data written to the LSB of AATR. See
Figure 8-8. The reset value of 0x5 sets supervisor data as the default address space.
BAAR is write only. BAAR[R,SZ] are loaded directly from the BDM command. BAAR[TT,TM] can be
programmed as debug control register 0x05 from the external development system. For compatibility with
Rev. A, BAAR is loaded each time AATR is written.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
W
Reset
R
SZ
TT
TM
W
Reset
Reg
Addr
0
0
0
0
1
0
1
CPU + 0x05
Figure 8-8. BDM Address Attribute Register (BAAR)
Table 8-10 describes BAAR fields.
Table 8-10. BAAR Field Descriptions
Bits
Name
Description
31-8
—
Reserved
7
R
Read/write
0 Write
1 Read
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Freescale Semiconductor
8-15
Table 8-10. BAAR Field Descriptions
Bits
Name
6–5
SZ
Size
00 Longword
01 Byte
10 Word
11 Reserved
4–3
TT
Transfer type. See the TT definition in Table 8-11.
2–0
TM
Transfer modifier. See the TM definition in Table 8-11.
8.4.5
Description
Address Attribute Trigger Registers (AATR, AATR1)
The AATR and AATR1, Figure 8-9, define address attributes and a mask to be matched in the trigger. The
register value is compared with address attribute signals from the processor’s local high-speed bus, as
defined by the setting of the trigger definition register (TDR) for AATR and the extended trigger definition
register (XTDR) for AATR1.
This register is expanded to include an optional ASID specification and a control bit that enables the use
of the ASID field.
31
R
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
ASIDCTRL1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ATTRASID
W
Reset
R RM
SZM
TTM
TMM
R
SZ
TT
TM
W
Reset
0
0
Reg
Addr
0
0
0
0
0
0
0
0
0
0
0
1
0
1
CPU + 0x06 (AATR), 0x16( AATR1)
1
Write only. AATR and AATR1 are accessible in supervisor mode as debug control register 0x06 and 0x16
respectively using the WDEBUG instruction and through the BDM port using the WDMREG command.
Figure 8-9. Address Attribute Trigger Registers (AATR, AATR1)
Table 8-11 describes AATR and AATR1 fields.
Table 8-11. AATR and AATR1 Field Descriptions
Bits
Name
31–25
—
24
Description
Reserved, should be cleared.
ASIDCTRL ABLR/ABHR/ATTR address breakpoint ASID enable. Corresponds to the ASID control enable for
the address breakpoint defined in ABLR, ABHR, and ATTR.
0 Disable ASID qualifier (reset default)
1 Enable ASID qualifier
MCF548x Reference Manual, Rev. 3
8-16
Freescale Semiconductor
Memory Map/Register Definition
Table 8-11. AATR and AATR1 Field Descriptions (Continued)
Bits
23–16
Name
Description
ATTRASID ABLR/ABHR/ATTR ASID. Corresponds to the ASID to be included in the address breakpoint
specified by ABLR, ABHR, and ATTR.
15
RM
Read/write mask. Setting RM masks R in address comparisons.
14–13
SZM
Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
12–11
TTM
Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
10–8
TMM
Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address
comparisons.
7
R
Read/write. R is compared with the R/W signal of the processor’s local bus.
6–5
SZ
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
4–3
TT
Transfer type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding
indicates an external or DMA access (for backward compatibility). These bits affect the TM bits.
2–0
TM
Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental
information for each transfer type.
TT = 00 (normal mode):
000 Data and instruction cache line push
001 User data access
010 User code access
011 Instruction cache invalidate
100 Data cache push/Instruction cache invalidate
101 Supervisor data access
110 Supervisor code access
111 INTOUCH instruction access
TT = 10 (emulator mode):
0xx–100 Reserved
101 Emulator mode data access
110 Emulator mode code access
111 Reserved
TT = 11 (acknowledge/CPU space transfers):
000 CPU space access
001–111 Interrupt acknowledge levels 1–7
These bits also define the TM encoding for BDM memory commands (for backward compatibility).
8.4.6
Trigger Definition Register (TDR)
The TDR, shown in Table 8-10, configures the operation of the hardware breakpoint logic that corresponds
with the ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the
debug module. In conjunction with the XTDR and its associated debug registers, TDR controls the actions
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-17
taken under the defined conditions. Breakpoint logic may be configured as one- or two-level triggers.
TDR[31–16] or XTDR[31–16] define second-level triggers, and bits 15–0 define first-level triggers.
TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the WDMREG command.
NOTE
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before
defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
When cleared, the data enable bits (EDxx) for both the second level and first level triggers disable data
breakpoints. When set, these bits enable the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus.
The address breakpoint for each trigger is enabled by setting the address enable bits (EAx); clearing all
three bits disables the corresponding breakpoint.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DI
2
EAI
2
EAR
2
EAL
2
EPC
2
PCI
2
Second Level Triggers
R
TRC
EBL
2
W
Reset
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DI
1
EAI
1
EAR
1
EAL
1
EPC
1
PCI
1
0
0
0
0
0
0
First Level Triggers
R
0
0
EBL
1
0
0
0
W
Reset
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
1
1
1
1
1
1
1
0
0
Reg
Addr
0
0
0
0
0
CPU + 0x07
Figure 8-10. Trigger Definition Register (TDR)
Table 8-12 describes TDR fields.
Table 8-12. TDR Field Descriptions
Bits
Name
Description
31–30
TRC
Trigger response control. Determines how the processor responds to a completed trigger
condition. The trigger response is always displayed on PSTDDATA.
00 Display on PSTDDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
29
EBL2
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL]
enables a breakpoint trigger. If both TDL[EBL] and XTDL[EBL] are cleared, all breakpoints are
disabled.
MCF548x Reference Manual, Rev. 3
8-18
Freescale Semiconductor
Memory Map/Register Definition
Table 8-12. TDR Field Descriptions (Continued)
Bits
Name
Description
28
EDLW2
Data enable bit: Data longword. Entire processor’s local data bus.
27
EDWL2
Data enable bit: Lower data word.
26
EDWU2
Data enable bit: Upper data word.
25
EDLL2
Data enable bit: Lower lower data byte. Low-order byte of the low-order word.
24
EDLM2
Data enable bit: Lower middle data byte. High-order byte of the low-order word.
23
EDUM2
Data enable bit: Upper middle data byte. Low-order byte of the high-order word.
22
EDUU2
Data enable bit: Upper upper data byte. High-order byte of the high-order word.
21
DI2
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR contents.
20
EAI2
Address enable bit: Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR and ABHR. Trigger if address > ABHR or if address < ABLR.
19
EAR2
Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive
range defined by ABLR and ABHR. Trigger if address Š ABHR or if address ð ABLR.
18
EAL2
Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the
ABLR. Trigger address = ABLR
17
EPC2
Enable PC breakpoint. If set, this bit enables the PC breakpoint for the second level trigger.
16
PCI2
Breakpoint invert. If set, this bit allows execution outside a given region as defined by
PBR/PBR1/PBR2/PBR3 and PBMR to enable a trigger. If cleared, the PC breakpoint is defined
within the region defined by PBR/PBR1/PBR2/PBR3 and PBMR.
15–14
—
13
EBL1
12
EDLW1
Data enable bit: Data longword. Entire processor’s local data bus.
11
EDWL1
Data enable bit: Lower data word.
10
EDWU1
Data enable bit: Upper data word.
9
EDLL1
Data enable bit: Lower lower data byte. Low-order byte of the low-order word.
8
EDLM1
Data enable bit: Lower middle data byte. High-order byte of the low-order word.
7
EDUM1
Data enable bit: Upper middle data byte. Low-order byte of the high-order word.
6
EDUU1
Data enable bit: Upper upper data byte. High-order byte of the high-order word.
5
DI1
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR contents.
4
EAI1
Address enable bit: Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR and ABHR. Trigger if address > ABHR or if address < ABLR.
3
EAR1
Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive
range defined by ABLR and ABHR. Trigger if address Š ABHR or if address ð ABLR.
Reserved, should be cleared.
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL]
enables a breakpoint trigger. If both TDL[EBL] and XTDL[EBL] are cleared, all breakpoints are
disabled.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-19
Table 8-12. TDR Field Descriptions (Continued)
Bits
Name
Description
2
EAL1
Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the
ABLR. Trigger address = ABLR
1
EPC1
Enable PC breakpoint. If set, this bit enables the PC breakpoint for the first level trigger.
0
PCI1
Breakpoint invert. If set, this bit allows execution outside a given region as defined by
PBR/PBR1/PBR2/PBR3 and PBMR to enable a trigger. If cleared, the PC breakpoint is defined
within the region defined by PBR/PBR1/PBR2/PBR3 and PBMR.
8.4.7
Program Counter Breakpoint and Mask Registers (PBRn, PBMR)
Each PC breakpoint register (PBR, PBR1, PBR2, PBR3) defines an instruction address for use as part of
the trigger. These registers’ contents are compared with the processor’s program counter register when the
appropriate valid bit is set, and TDR or XTDR are configured appropriately. PBR bits are masked by
setting corresponding PBMR bits. Results are compared with the processor’s program counter register, as
defined in TDR or XTDR. PBR1–PBR3 are not masked. Figure 8-11 shows the PC breakpoint register.
PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and through the
BDM port using the RDMREG and WDMREG commands using values shown in Section 8.5.3.3, “Command
Set Descriptions.”
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
CNTRAD
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CNTRAD
0
V1
W
Reset
0
Reg
Addr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU + 0x08 (PBR); 0x18 (PBR1); 0x1A (PBR2); 0x1B (PBR3)
1
PBR0 does not have a valid bit. PBR0 is read as 0 and should be cleared.
Figure 8-11. Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3)
Table 8-13 describes PBR, PBR1, PBR2, and PBR3 fields.
MCF548x Reference Manual, Rev. 3
8-20
Freescale Semiconductor
Memory Map/Register Definition
Table 8-13. PBR, PBR1, PBR2, PBR3 Field Descriptions
Bits
Name
Description
31–1
CNTRAD
PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint
trigger.
0
V
Valid.
0 Breakpoint registers are not compared with the processor’s program counter register
1 Breakpoint registers are compared with the processor’s program counter register when
the appropriate valid bit is set and TDR or XTDR are configured appropriately.
Note: This bit is not implemented on PBR0; it is implemented on PBR[1:3].
Figure 8-12 shows PBMR. PBMR is accessible in supervisor mode as debug control register 0x09 using
the WDEBUG instruction and via the BDM port using the WDMREG command.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
CNTRMSK
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
CNTRMSK
W
Reset
0
0
0
0
0
Reg
Addr
0
0
0
0
CPU + 0x09
Figure 8-12. Program Counter Breakpoint Mask Register (PBMR)
Table 8-14 describes PBMR fields.
Table 8-14. PBMR Field Descriptions
Bits
Name
31–0
8.4.8
Description
CNTRMSK PC breakpoint mask.
0 This PBMR bit causes the corresponding PBR bit to be compared to the appropriate
program counter register bit.
1 This PBMR bit causes the corresponding PBR bit to be ignored.
Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1)
The ABLR, ABLR1, ABHR, and ABHR1, shown in Figure 8-13, define regions in the processor’s data
address space that can be used as part of the trigger. These register values are compared with the address
for each transfer on the processor’s high-speed local bus. The trigger definition register (TDR) identifies
the trigger as one of three cases:
• Identically the value in ABLR
• Inside the range bound by ABLR and ABHR inclusive
• Outside that same range
XTDR determines the same for ABLR1 and ABHR1.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-21
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
AD
W1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
R
AD
W1
Reset
0
0
0
Reg
Addr
0
0
0
0
0
CPU + 0x0D (ABLR); 0x1D (ABLR1); 0x0C (ABHR); 0x1C (ABHR1)
1
ABHR and ABHR1 are accessible in supervisor mode as debug control registers 0x0C and 0x1C, using the
WDEBUG instruction and via the BDM port using the RDMREG and WDMREG commands.
Figure 8-13. Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)
Table 8-15 describes ABLR and ABLR1 fields.
Table 8-15. ABLR and ABLR1 Field Description
Bits
Name
Description
31–0
AD
Low address. Holds the 32-bit address marking the lower bound of the address breakpoint
range. Breakpoints for specific addresses are programmed into ABLR or ABLR1.
Table 8-16 describes ABHR and ABHR1 fields.
Table 8-16. ABHR and ABHR1 Field Description
8.4.9
Bits
Name
Description
31–0
AD
High address. Holds the 32-bit address marking the upper bound of the address breakpoint
range.
Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1)
The data breakpoint registers (DBR/DBR1, Figure 8-14), specify data patterns used as part of the trigger
into debug mode. DBRn bits are masked by setting corresponding DBMR bits, as defined in TDR.
DBR and DBR1 are accessible in supervisor mode as debug control register 0x0E and 0x1E, using the
WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands.
MCF548x Reference Manual, Rev. 3
8-22
Freescale Semiconductor
Memory Map/Register Definition
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
DATA (DBR/DBR1)
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
DATA (DBR/DBR1)
W
Reset
0
0
0
0
0
0
Reg
Addr
0
0
0
CPU + 0x0E (DBR), 0x1E (DBR1)
Figure 8-14. Data Breakpoint Registers (DBR/DBR1)
Table 8-17 describes DBRn fields.
Table 8-17. DBRn Field Descriptions
Bits
Name
31–0
DATA
Description
Data breakpoint value. Contains the value to be compared with the data value from the
processor’s local bus as a breakpoint trigger.
DBMR and DBMR1 are accessible in supervisor mode as debug control register 0x0F and 0x1F, using the
WDEBUG instruction and via the BDM port using the WDMREG command.
31
30
29
28
27
26
R
25
24
23
22
21
20
19
18
17
16
MSK (DBMR/DBMR1)
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
MSK (DBMR/DBMR1)
W
Reset
0
0
0
0
0
Reg
Addr
0
0
0
0
0
CPU + 0x0F (DBMR), 0x1F (DBMR1)
Figure 8-15. Data Breakpoint Mask Registers (DBMR/DBMR1)
Table 8-18 describes DBMRn fields.
Table 8-18. DBMRn Field Descriptions
Bits
Name
Description
31–0
MSK
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBRn
bit allows the corresponding DBRn bit to be compared to the appropriate bit of the
processor’s local data bus. Setting a DBMRn bit causes that bit to be ignored.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-23
DBRs support both aligned and misaligned references. Table 8-19 shows relationships between processor
address, access size, and location within the 32-bit data bus.
Table 8-19. Access Size and Operand Data Location
8.4.10
A[1:0]
Access Size
Operand Location
00
Byte
D[31:24]
01
Byte
D[23:16]
10
Byte
D[15:8]
11
Byte
D[7:0]
0x
Word
D[31:16]
1x
Word
D[15:0]
xx
Longword
D[31:0]
PC Breakpoint ASID Register (PBASID)
Each PC breakpoint register (PBR, PBR1, PBR2, or PBR3) specifies an instruction address that can be
used to trigger a breakpoint. To support debugging in a virtual environment, an ASID can optionally be
associated with the instruction address in the PC breakpoint registers. The optional specification of an
ASID value is made using PBASID and its exact inclusion within the breakpoint specification defined by
the PBAC.
31
30
29
R
28
27
26
25
24
23
22
21
PBR3ASID
20
19
18
17
16
PBR2ASID
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
PBR1ASID
PBRASID
W
Reset
0
0
0
Reg
Addr
0
0
0
0
0
0
0
0
0
0
CPU + 0x14
Figure 8-16. PC Breakpoint ASID Register (PBASID)
PBASID contains one 8-bit ASID values for each PC breakpoint register, as described in Table 8-20,
which allows each PC breakpoint register to be associated with a unique virtual address and process.
Table 8-20. PBASID Field Descriptions
Bits
Name
Description
31–24
PBA3SID
PBR3ASID. Corresponds to the ASID associated with PBR3.
23–16
PBA2SID
PBR2ASID Corresponds to the ASID associated with PBR2.
MCF548x Reference Manual, Rev. 3
8-24
Freescale Semiconductor
Memory Map/Register Definition
Table 8-20. PBASID Field Descriptions (Continued)
Bits
Name
15–8
PBA1SID
PBR1ASID. Corresponds to the ASID associated with PBR1.
7–0
PBASID
PBRASID. Corresponds to the ASID associated with PBR.
8.4.11
Description
Extended Trigger Definition Register (XTDR)
The XTDR configures the operation of the hardware breakpoint logic that corresponds with the
ABHR1/ABLR1/AATR1 and DBR1/DBMR1 registers within the debug module and, in conjunction with
the TDR and its associated debug registers, controls the actions taken under the defined conditions. The
breakpoint logic may be configured as a one- or two-level trigger, where TDR[31–16] or XTDR[31–16]
define the second-level trigger and bits 15–0 define the first-level trigger. The XTDR is accessible in
supervisor mode as debug control register 0x17 using the WDEBUG instruction and via the BDM port
using the WDMREG command.
NOTE
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before
defining triggers.
A write to the XTDR clears the trigger status bits, CSR[BSTAT].
When cleared, the data enable bits (EDxx) for both the second level and first level triggers disable data
breakpoints. When set, these bits enable the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus.
The address breakpoint for each trigger is enabled by setting the address enable bits (EAx); clearing all
three bits disables the corresponding breakpoint.
Section 8.4.11.1, “Resulting Set of Possible Trigger Combinations,” describes how to handle multiple
breakpoint conditions.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DI
2
EAI
2
EAR
2
EAL
2
0
0
Second Level Triggers
R
0
0
W
Reset
EBL
2
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
2
2
2
2
2
2
2
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DI
1
EAI
1
EAR
1
EAL
1
0
0
0
0
0
0
0
First Level Triggers
R
0
W
Reset
0
—
0
EBL
1
0
Reg
Addr
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
1
1
1
1
1
1
1
0
0
0
0
0
0
0
—
0
CPU + 0x17
Figure 8-17. Extended Trigger Definition Register (XTDR)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-25
Table 8-21 describes XTDR fields.
Table 8-21. XTDR Field Descriptions
Bits
Name
Description
31–30
—
29
EBL2
28
EDLW2
Data enable bit: Data longword. Entire processor’s local data bus.
27
EDWL2
Data enable bit: Lower data word.
26
EDWU2
Data enable bit: Upper data word.
25
EDLL2
Data enable bit: Lower lower data byte. Low-order byte of the low-order word.
24
EDLM2
Data enable bit: Lower middle data byte. High-order byte of the low-order word.
23
EDUM2
Data enable bit: Upper middle data byte. Low-order byte of the high-order word.
22
EDUU2
Data enable bit: Upper upper data byte. High-order byte of the high-order word.
21
DI2
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR1 contents.
20
EAI2
Address enable bit: Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR1 and ABHR1. Trigger if address > ABHR or if address < ABLR.
19
EAR2
Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive
range defined by ABLR1 and ABHR1. Trigger if address Š ABHR or if address ð ABLR.
18
EAL2
Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the
ABLR1. Trigger address = ABLR
17–14
—
13
EBL1
12
EDLW1
Data enable bit: Data longword. Entire processor’s local data bus.
11
EDWL1
Data enable bit: Lower data word.
10
EDWU1
Data enable bit: Upper data word.
9
EDLL1
Data enable bit: Lower lower data byte. Low-order byte of the low-order word.
8
EDLM1
Data enable bit: Lower middle data byte. High-order byte of the low-order word.
7
EDUM1
Data enable bit: Upper middle data byte. Low-order byte of the high-order word.
6
EDUU1
Data enable bit: Upper upper data byte. High-order byte of the high-order word.
5
DI1
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR contents.
4
EAI1
Address enable bit: Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR1 and ABHR1. Trigger if address > ABHR or if address < ABLR.
Reserved, should be cleared.
Enable breakpoint level. If set, EBL2 is the global enable for the breakpoint trigger; that is, if
TDR[EBL2] or XTDR[EBL2] is set, a breakpoint trigger is enabled. Clearing both disables all
breakpoints.
Reserved, should be cleared.
Enable breakpoint level. If set, EBL1 is the global enable for the breakpoint trigger; that is, if
TDR[EBL1] or XTDR[EBL1] is set, a breakpoint trigger is enabled. Clearing both disables all
breakpoints.
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Memory Map/Register Definition
Table 8-21. XTDR Field Descriptions (Continued)
Bits
Name
3
EAR1
Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive
range defined by ABLR1 and ABHR1. Trigger if address Š ABHR or if address ð ABLR.
2
EAL1
Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the
ABLR1. Trigger address = ABLR
1–0
—
8.4.11.1
Description
Reserved, should be cleared.
Resulting Set of Possible Trigger Combinations
The resulting set of possible breakpoint trigger combinations consist of the following options where ||
denotes logical OR, && denotes logical AND, and {} denotes an optional additional trigger term:
One-level triggers of the form:
if
if
if
(PC_breakpoint)
(PC_breakpoint|| Address_breakpoint{&& Data_breakpoint})
(PC_breakpoint|| Address_breakpoint{&& Data_breakpoint}
||
Address1_breakpoint{&& Data1_breakpoint})
if
if
(Address_breakpoint
{&& Data_breakpoint})
((Address_breakpoint
{&& Data_breakpoint})
||
(Address1_breakpoint{&& Data1_breakpoint}))
if
(Address1_breakpoint
{&& Data1_breakpoint})
Two-level triggers of the form:
if
(PC_breakpoint)
then if
(Address_breakpoint{&& Data_breakpoint})
if
if
(PC_breakpoint)
then if
||
(Address_breakpoint{&& Data_breakpoint}
Address1_breakpoint{&& Data1_breakpoint})
(PC_breakpoint)
then if
(Address1_breakpoint{&& Data1_breakpoint})
if
(Address_breakpoint
{&& Data_breakpoint})
then if
(Address1_breakpoint{&& Data1_breakpoint})
if
(Address1_breakpoint
{&& Data1_breakpoint})
then if
(Address_breakpoint{&& Data_breakpoint})
if
(Address_breakpoint
{&& Data_breakpoint})
then if
(PC_breakpoint)
if
(Address1_breakpoint
{&& Data1_breakpoint})
then if
(PC_breakpoint)
if
(Address_breakpoint
{&& Data_breakpoint})
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8-27
then if
||
if
(PC_breakpoint
Address1_breakpoint{&& Data1_breakpoint})
(Address1_breakpoint
{&& Data1_breakpoint})
then if
(PC_breakpoint
||
Address_breakpoint{&& Data_breakpoint})
In this example, PC_breakpoint is the logical summation of the PBR/PBMR, PBR1, PBR2, and PBR3
breakpoint registers; Address_breakpoint is a function of ABHR, ABLR, and AATR; Data_breakpoint is
a function of DBR and DBMR; Address1_breakpoint is a function of ABHR1, ABLR1, and AATR1; and
Data1_breakpoint is a function of DBR1 and DBMR1. In all cases, the data breakpoints can be included
with an address breakpoint to further qualify a trigger event as an option.
8.5
Background Debug Mode (BDM)
The ColdFire Family implements a low-level system debugger in the microprocessor hardware.
Communication with the development system is handled through a dedicated, high-speed serial command
interface. The ColdFire architecture implements the BDM controller in a dedicated hardware module.
Although some BDM operations, such as CPU register accesses, require the CPU to be halted, all other
BDM commands, such as memory accesses, can be executed while the processor is running.
BDM is useful for the following reasons:
• In-circuit emulation is not needed, so physical and electrical characteristics of the system are not
affected.
• BDM is always available for debugging the system and provides a communication link for
upgrading firmware in existing systems.
• Provides high-speed cache downloading (500 Kbytes/sec), especially useful for flash
programming
• Provides absolute control of the processor, and thus the system. This feature allows quick hardware
debugging with the same tool set used for firmware development.
8.5.1
CPU Halt
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation
requires the CPU to be halted. The sources that can cause the CPU to halt are listed below, in order of
priority:
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint can be configured to generate a pending halt condition similar to the
assertion of BKPT. This type of halt is always first made pending in the processor. Next, the
processor samples for pending halt and interrupt conditions once per instruction. When a pending
condition is asserted, the processor halts execution at the next sample point. See Section 8.6.1,
“Theory of Operation.”
3. The execution of a HALT instruction immediately suspends execution. Attempting to execute
HALT in user mode while CSR[UHE] = 0 generates a privilege violation exception. If
CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes, the processor can be
restarted by serial shifting a GO command into the debug module. Execution continues at the
instruction after HALT.
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Background Debug Mode (BDM)
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, asserting BKPT creates a
pending halt, which is postponed until the processor core samples for halts/interrupts. The
processor samples for these conditions once during the execution of each instruction; if a pending
halt is detected then, the processor suspends execution and enters the halted state.
The assertion of BKPT should be considered in the following two special cases:
• After the system reset signal is negated, the processor waits for 16 processor clock cycles before
beginning reset exception processing. If the BKPT input is asserted within eight cycles after RSTI
is negated, the processor enters the halt state, signaling halt status (0xF) on the PSTDDATA
outputs. While the processor is in this state, all resources accessible through the debug module can
be referenced. This is the only chance to force the processor into emulation mode through
CSR[EMU].
After system initialization, the processor’s response to the GO command depends on the set of
BDM commands performed while it is halted for a breakpoint. Specifically, if the PC register was
loaded, the GO command causes the processor to exit halted state and pass control to the instruction
address in the PC, bypassing normal reset exception processing. If the PC was not loaded, the GO
command causes the processor to exit halted state and continue reset exception processing.
• The ColdFire architecture also handles a special case of BKPT being asserted while the processor
is stopped by execution of the STOP instruction. For this case, the processor exits the stopped mode
and enters the halted state. At this point, all BDM commands may be exercised. When restarted,
the processor continues by executing the next sequential instruction, that is, the instruction
following the STOP opcode.
CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt conditions.
Debug module Revisions A and B clear CSR[27–24] upon a read of the CSR, but Revision C and D (in
V4) do not. The debug GO command clears CSR[26–24].
HALT can be recognized by counting 0xFF occurrences on PSTDDATA. The count is necessary to
determine between a possible data output value of 0xFF and the HALT condition. Because data always
follows a marker (0x8, 0x9, 0xA, or 0xB), PSTDDATA can display no more than four data 0xFFs. Two
such scenarios exist:
• A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF following:
PSTDDATA[7:0]
0xBF
0xFF
0xFF
0xFF
0xFX (X indicates that the next PST value is guaranteed to not be 0xF)
• A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF following:
PSTDDATA[7:0]
0xYB
0xFF
0xFF
0xFF
0xFF
0xXY (X indicates that the PST value is guaranteed to not be 0xF, and Y indicates a PSTDDATA
value that doesn’t affect the 0xFF count).
Thus, a count of either nine or more sequential single 0xF values or five or more sequential 0xFF values
signifies the HALT condition.
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8.5.2
BDM Serial Interface
When the CPU is halted and PSTDDATA reflects the halt status, the development system can send
unrestricted commands to the debug module. The debug module implements a synchronous protocol using
two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the
rising edge of the processor clock. See Table 8-1. The development system serves as the serial
communication channel master and must generate DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel uses
full-duplex mode, where data is sent and received simultaneously by both master and slave devices. The
transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown
in Figure 8-18, all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is
high; that is, DSI is sampled and DSO is driven.
C0
C1
C2
C3
C4
PSTCLK
DSCLK
DSI
BDM State
Machine
DSO
Current
Current State
Past
Next
Next State
Current
Figure 8-18. Maximum BDM Serial Interface Timing
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled, along
with DSI, on the rising edge of PSTCLK. DSO is delayed from the DSCLK-enabled PSTCLK rising edge
(registered after a BDM state machine state change). All events in the debug module’s serial state machine
are based on the PSTCLK rising edge. DSCLK must also be sampled low (on a positive edge of PSTCLK)
between each bit exchange. The msb is sent first. Because DSO changes state based on an internally
recognized rising edge of DSCLK, DSO cannot be used to indicate the start of a serial transfer. The
development system must count clock cycles in a given transfer. C0–C4 are described as follows:
• C0: Set the state of the DSI bit.
• C1: First synchronization cycle for DSI (DSCLK is high).
• C2: Second synchronization cycle for DSI (DSCLK is high).
• C3: BDM state machine changes state depending upon DSI and whether the entire input data
transfer has been transmitted.
• C4: DSO changes to next value.
NOTE
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
8.5.2.1
Receive Packet Format
The basic receive packet, Figure 8-19, consists of 16 data bits and 1 status bit
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Background Debug Mode (BDM)
.
16
15
0
S
Data Field [15:0]
Figure 8-19. Receive BDM Packet
Table 8-22 describes receive BDM packet fields.
Table 8-22. Receive BDM Packet Field Description
Bits
Name
Description
16
S
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can
be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
S
0
0
1
1
1
15–0
Data
8.5.2.2
DataMessage
xxxx Valid data transfer
0xFFFFStatus OK
0x0000Not ready with response; come again
0x0001Error: Terminated bus cycle; data invalid
0xFFFFIllegal command
Data. Contains the message to be sent from the debug module to the development system. The
response message is always a single word, with the data field encoded as shown above.
Transmit Packet Format
The basic transmit packet, Figure 8-20, consists of 16 data bits and 1 control bit.
16
15
0
C
D[15:0]
Figure 8-20. Transmit BDM Packet
Table 8-23 describes transmit BDM packet fields.
Table 8-23. Transmit BDM Packet Field Description
8.5.3
Bits
Name
16
C
15–0
Data
Description
Control. This bit is reserved. Command and data transfers initiated by the development
system should clear C.
Contains the data to be sent from the development system to the debug module.
BDM Command Set
Table 8-24 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of
each command. Issuing a BDM command when the processor is accessing debug module registers using
the WDEBUG instruction causes undefined behavior.
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Table 8-24. BDM Command Summary
Description
CPU
State1
Command
(Hex)
Command
Mnemonic
Read A/D
register
rareg/
rdreg
Read the selected address or data register and
return the results through the serial interface.
Halted
8.5.3.3.1 0x218 {A/D,
Reg[2:0]}
Write A/D
register
wareg/
wdreg
Write the data operand to the specified address or
data register.
Halted
8.5.3.3.2 0x208 {A/D,
Reg[2:0]}
Read
memory
location
read
Read the data at the memory location specified by
the longword address.
Steal
8.5.3.3.3 0x1900—byte
0x1940—word
0x1980—lword
Write
memory
location
write
Write the operand data to the memory location
specified by the longword address.
Steal
8.5.3.3.4 0x1800—byte
0x1840—word
0x1880—lword
Dump
memory
block
dump
Used with READ to dump large blocks of memory. An
initial READ is executed to set up the starting address
of the block and to retrieve the first result. A DUMP
command retrieves subsequent operands.
Steal
8.5.3.3.5 0x1D00—byte
0x1D40—word
0x1D80—lword
Fill memory
block
fill
Used with WRITE to fill large blocks of memory. An
initial WRITE is executed to set up the starting
address of the block and to supply the first operand.
A FILL command writes subsequent operands.
Steal
8.5.3.3.6 0x1C00—byte
0x1C40—word
0x1C80—lword
Resume
execution
go
The pipeline is flushed and refilled before resuming
instruction execution at the current PC.
Halted
8.5.3.3.7 0x0C00
No operation
nop
Perform no operation; may be used as a null
command.
Parallel
8.5.3.3.8 0x0000
Output the
current PC
sync_pc
Capture the current PC and display it on the
PSTDDATA output pins.
Parallel
8.5.3.3.9 0x0001
Read control
register
rcreg
Read the system control register.
Halted
8.5.3.3.11 0x2980
Write control
register
wcreg
Write the operand data to the system control
register.
Halted
8.5.3.3.15 0x2880
Read debug
module
register
rdmreg
Read the debug module register.
Parallel
8.5.3.3.16 0x2D {0x42
DRc[4:0]}
Write debug
module
register
wdmreg
Write the operand data to the debug module
register.
Parallel
8.5.3.3.17 0x2C {0x42
DRc[4:0]}
Section
1
General command effect and/or requirements on CPU operation:
- Halted. The CPU must be halted to perform this command.
- Steal. Command generates bus cycles that can be interleaved with bus accesses.
- Parallel. Command is executed in parallel with CPU activity.
2 0x4 is a three-bit field.
Unassigned command opcodes are reserved by Freescale. All unused command formats within any
revision level perform a NOP and return the illegal command response.
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Background Debug Mode (BDM)
8.5.3.1
ColdFire BDM Command Format
All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one
or more extension words, as shown in Figure 8-21.
15
10
Operation
9
8
0
R/W
7
6
5
4
3
Op Size
0
0
A/D
2
0
Register
Extension Word(s)
Figure 8-21. BDM Command Format
Table 8-25 describes BDM fields.
Table 8-25. BDM Field Descriptions
Bit
Name
15–10
Operation
9
—
8
R/W
7–6
Operand
Size
5–4
—
3
A/D
2–0
Register
8.5.3.1.1
Description
Specifies the command. These values are listed in Table 8-24.
Reserved
Direction of operand transfer.
0 Data is written to the CPU or to memory from the development system.
1 The transfer is from the CPU to the development system.
Operand data size for sized operations. Addresses are expressed as 32-bit absolute
values. Note that a command performing a byte-sized memory read leaves the upper 8 bits
of the response data undefined. Referenced data is returned in the lower 8 bits of the
response.
Operand SizeBit Values
00 Byte8 bits
01 Word16 bits
10 Longword32 bits
11 Reserved—
Reserved
Address/data. Determines whether the register field specifies a data or address register.
0 Indicates a data register.
1 Indicates an address register.
Contains the register number in commands that operate on processor registers.
Extension Words as Required
Some commands require extension words for addresses or immediate data. Addresses require two
extension words because only absolute long addressing is permitted. Longword accesses are forcibly
longword-aligned and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long.
Byte and word data each requires one extension word and longword data requires two extension words.
Operands and addresses are transferred most-significant word first. In the following descriptions of the
BDM command set, the optional set of extension words is defined as address, data, or operand data.
8.5.3.2
Command Sequence Diagrams
The command sequence diagram in Figure 8-22 shows serial bus traffic for commands. Each bubble
represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system
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sends to the debug module; the bottom half indicates the debug module’s response to the previous
development system commands. Command and result transactions overlap to minimize latency.
Commands transmitted to the debug module
Command code transmitted during this cycle
High-order 16 bits of memory address
Low-order 16 bits of memory address
Non-serial-related
activity
READ (LONG)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
READ
MEMORY
LOCATION
Sequence taken if operation
has not completed
XXX
’NOT READY’
Next
Command
Code
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR
NEXT CMD
’NOT READY’
Data used from this transfer
Sequence taken if illegal command
is received by debug module
Results from previous command
Responses from the debug module
Sequence taken if bus error
occurs on memory access
High- and low-order 16 bits of result
Figure 8-22. Command Sequence Diagram
The sequence is as follows:
• In cycle 1, the development system command is issued (READ in this example). The debug module
responds with either the low-order results of the previous command or a command complete status
of the previous command, if no results are required.
• In cycle 2, the development system supplies the high-order 16 address bits. The debug module
returns a not-ready response unless the received command is decoded as unimplemented, which is
indicated by the illegal command encoding. If this occurs, the development system should
retransmit the command.
NOTE
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
•
•
•
In cycle 3, the development system supplies the low-order 16 address bits. The debug module
always returns a not-ready response.
At the completion of cycle 3, the debug module initiates a memory read operation. Any serial
transfers that begin during a memory access return a not-ready response.
Results are returned in the two serial transfer cycles after the memory access completes. For any
command performing a byte-sized memory read operation, the upper 8 bits of the response data are
undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is
sent to the debug module during the final transfer. If a memory or register access is terminated with
a bus error, the error status (S = 1, DATA = 0x0001) is returned instead of result data.
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Background Debug Mode (BDM)
8.5.3.3
Command Set Descriptions
The following sections describe the commands summarized in Table 8-24.
NOTE
The BDM status bit (S) is 0 for normally completed commands. S = 1 for
illegal commands, not-ready responses, and transfers with bus-errors.
Section 8.5.2, “BDM Serial Interface,” describes the receive packet format.
Freescale reserves unassigned command opcodes for future expansion. Unused command formats in any
revision level perform a NOP and return an illegal command response.
8.5.3.3.1
Read A/D Register (RAREG/RDREG)
Read the selected address or data register and return the 32-bit result. A bus error response is returned if
the CPU core is not halted.
Command/Result Formats:
15
Command
12
11
0x2
8
7
0x1
4
0x8
Result
3
A/D
2
0
Register
D[31:16]
D[15:0]
Figure 8-23. RAREG/RDREG Command Format
Command Sequence:
RAREG/RDREG
???
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR
NEXT CMD
’NOT READY’
Figure 8-24. RAREG/RDREG Command Sequence
Operand Data:
Result Data:
8.5.3.3.2
None
The contents of the selected register are returned as a longword value,
most-significant word first.
Write A/D Register (WAREG/WDREG)
The operand longword data is written to the specified address or data register. A write alters all 32 register
bits. A bus error response is returned if the CPU core is not halted.
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Command Format:
15
12
11
0x2
8
7
0x0
4
0x8
3
2
A/D
0
Register
D[31:16]
D[15:0]
Figure 8-25. WAREG/WDREG Command Format
Command Sequence
WAREG/WDREG
???
MS DATA
’NOT READY’
LS DATA
’NOT READY’
XXX
BERR
NEXT CMD
’NOT READY’
NEXT CMD
’CMD COMPLETE’
Figure 8-26. WAREG/WDREG Command Sequence
Operand Data
Result Data
8.5.3.3.3
Longword data is written into the specified address or data register. The data is
supplied most-significant word first.
Command complete status is indicated by returning 0xFFFF (with S cleared)
when the register write is complete.
Read Memory Location (READ)
Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces
low-order address bits to zeros for word and longword accesses to ensure that word addresses are
word-aligned and longword addresses are longword-aligned.
Command/Result Formats:
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Background Debug Mode (BDM)
15
12
Byte
11
8
0x1
7
0x9
4
3
0x0
Command
0
0x0
A[31:16]
A[15:0]
Result
Word
Command
X
X
X
X
X
X
0x1
X
X
0x9
D[7:0]
0x4
0x0
0x8
0x0
A[31:16]
A[15:0]
Result
Longword Command
D[15:0]
0x1
0x9
A[31:16]
A[15:0]
Result
D[31:16]
D[15:0]
Figure 8-27. READ Command/Result Formats
Command Sequence:
READ (B/W)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
READ
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
RESULT
XXX
BERR
READ (LONG)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
READ
MEMORY
LOCATION
NEXT CMD
’NOT READY’
XXX
’NOT READY’
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR
NEXT CMD
’NOT READY’
Figure 8-28. READ Command Sequence
Operand Data
The only operand is the longword address of the requested location.
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Result Data
8.5.3.3.4
Word results return 16 bits of data; longword results return 32. Bytes are returned
in the LSB of a word result, the upper byte is undefined. 0x0001 (S = 1) is returned
if a bus error occurs.
Write Memory Location (WRITE)
Write data to the memory location specified by the longword address. The address space is defined by
BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to
ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Command Formats:
15
12
Byte
11
8
0x1
7
0x8
4
0x0
3
1
0x0
A[31:16]
A[15:0]
X
Word
X
X
0x1
X
X
X
X
X
0x8
D[7:0]
0x4
0x0
0x8
0x0
A[31:16]
A[15:0]
D[15:0]
Longword
0x1
0x8
A[31:16]
A[15:0]
D[31:16]
D[15:0]
Figure 8-29. WRITE Command Format
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Background Debug Mode (BDM)
Command Sequence:
WRITE (B/W)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
DATA
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
NEXT CMD
’NOT READY’
WRITE (LONG)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
MS DATA
’NOT READY’
LS DATA
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
NEXT CMD
’NOT READY’
Figure 8-30. WRITE Command Sequence
Operand Data
Result Data
8.5.3.3.5
This two-operand instruction requires a longword absolute address that specifies
a location to which the data operand is to be written. Byte data is sent as a 16-bit
word, justified in the LSB; 16- and 32-bit operands are sent as 16 and 32 bits,
respectively.
Command complete status is indicated by returning 0xFFFF (with S cleared)
when the register write is complete. A value of 0x0001 (with S set) is returned if
a bus error occurs.
Dump Memory Block (DUMP)
DUMP is used with the READ command to access large blocks of memory. An initial READ is executed to
set up the starting address of the block and to retrieve the first result. If an initial READ is not executed
before the first DUMP, an illegal command response is returned. The DUMP command retrieves subsequent
operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary
register. Subsequent DUMP commands use this address, perform the memory read, increment it by the
current operand size, and store the updated address in the temporary register.
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NOTE
DUMP does not check for a valid address; it is a valid command only when
preceded by NOP, READ, or another DUMP command. Otherwise, an illegal
command response is returned. NOP can be used for intercommand padding
without corrupting the address pointer.
The size field is examined each time a
dynamically altered.
DUMP
command is processed, allowing the operand size to be
Command/Result Formats:
15
Byte
Command
Result
Word
12
11
8
0x1
X
Command
X
7
0xD
X
X
X
0x1
X
4
3
0x0
X
Result
0x0
X
0xD
0
D[7:0]
0x4
0x0
0x8
0x0
D[15:0]
Longword Command
0x1
0xD
Result
D[31:16]
D[15:0]
Figure 8-31. DUMP Command/Result Formats
Command Sequence:
READ
MEMORY
LOCATION
DUMP (B/W)
???
XXX
’NOT READY’
NEXT CMD
RESULT
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
READ
MEMORY
LOCATION
DUMP (LONG)
???
XXX
’ILLEGAL’
XXX
BERR
NEXT CMD
’NOT READY’
XXX
’NOT READY’
NEXT CMD
’NOT READY’
NEXT CMD
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR
NEXT CMD
’NOT READY’
Figure 8-32. DUMP Command Sequence
Operand Data:
None
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Background Debug Mode (BDM)
Result Data:
8.5.3.3.6
Requested data is returned as either a word or longword. Byte data is returned in
the least-significant byte of a word result. Word results return 16 bits of significant
data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if
a bus error occurs.
Fill Memory Block (FILL)
A FILL command is used with the WRITE command to access large blocks of memory. An initial WRITE is
executed to set up the starting address of the block and to supply the first operand. The FILL command
writes subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved
in a temporary register after the memory write. Subsequent FILL commands use this address, perform the
write, increment it by the current operand size, and store the updated address in the temporary register.
If an initial
returned.
WRITE
is not executed preceding the first
FILL
command, the illegal command response is
NOTE
The FILL command does not check for a valid address: FILL is a valid
command only when preceded by another FILL, a NOP, or a WRITE command.
Otherwise, an illegal command response is returned. The NOP command can
be used for intercommand padding without corrupting the address pointer.
The size field is examined each time a FILL command is processed, allowing the operand size to be altered
dynamically.
Command Formats:
15
12
Byte
11
8
0x1
X
Word
X
0xC
X
0x1
7
X
X
X
4
3
0x0
X
X
0xC
0
0x0
D[7:0]
0x4
0x0
0x8
0x0
D[15:0]
Longword
0x1
0xC
D[31:16]
D[15:0]
Figure 8-33. FILL Command Format
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Command Sequence:
FILL (LONG)
???
MS DATA
’NOT READY’
LS DATA
’NOT READY’
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
FILL (B/W)
???
DATA
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
NEXT CMD
’NOT READY’
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
NEXT CMD
’NOT READY’
XXX
BERR
Figure 8-34. FILL Command Sequence
Operand Data:
Result Data:
8.5.3.3.7
A single operand is data to be written to the memory location. Byte data is sent as
a 16-bit word, justified in the least-significant byte; 16- and 32-bit operands are
sent as 16 and 32 bits, respectively.
Command complete status (0xFFFF) is returned when the register write is
complete. A value of 0x0001 (with S set) is returned if a bus error occurs.
Resume Execution (GO)
The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the
current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered
by a BDM command while the processor is halted, the updated value is used when prefetching resumes.
If a GO command is issued and the CPU is not halted, the command is ignored.
15
12
0x0
11
8
0xC
7
4
0x0
3
0
0x0
Figure 8-35. GO Command Format
Command Sequence:
GO
???
NEXT CMD
’CMD COMPLETE’
Figure 8-36. GO Command Sequence
Operand Data:
None
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Background Debug Mode (BDM)
Result Data:
8.5.3.3.8
NOP
The command-complete response (0xFFFF) is returned during the next shift
operation.
No Operation (NOP)
performs no operation and may be used as a null command where required.
Command Formats:
15
12
0x0
11
8
0x0
7
4
0x0
3
0
0x0
Figure 8-37. NOP Command Format
Command Sequence:
NOP
???
NEXT CMD
’CMD COMPLETE’
Figure 8-38. NOP Command Sequence
Operand Data:
Result Data:
8.5.3.3.9
None
The command-complete response, 0xFFFF (with S cleared), is returned during the
next shift operation.
Synchronize PC to the PSTDDATA Lines (SYNC_PC)
The SYNC_PC command captures the current PC and displays it on the PSTDDATA outputs. After the
debug module receives the command, it sends a signal to the ColdFire processor that the current PC must
be displayed. The processor then forces an instruction fetch at the next PC with the address being captured
in the DDATA logic under control of CSR[BTB]. The specific sequence of PSTDDATA values is as
follows:
1. Debug signals a SYNC_PC command is pending.
2. CPU completes the current instruction.
3. CPU forces an instruction fetch to the next PC, generates a PST = 0x5 value indicating a taken
branch and signals the capture of DDATA.
4. The instruction address corresponding to the PC is captured.
5. The PST marker (0x9–0xB) is generated and displayed as defined by CSR[BTB] followed by the
captured PC address.
If the option to display ASID is enabled (CSR[3] = 1), the 8-bit ASID follows the address. That is, the
PSTDDATA sequence is {0x5, Marker, Instruction Address, 0x8, ASID}, where the 0x8 is the marker for
the ASID.
The SYNC_PC command can be used to dynamically access the PC for performance monitoring. The
execution of this command is considerably less obtrusive to the real-time operation of an application than
a HALT-CPU/READ-PC/RESUME command sequence.
Command Formats:
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15
12
11
0x0
8
7
4
0x0
3
0x0
0
0x1
Figure 8-39. SYNC_PC Command Format
Command Sequence:
SYNC_PC
NEXT CMD
???
“CMD COMPLETE”
Figure 8-40. SYNC_PC Command Sequence
Operand Data:
Result Data:
8.5.3.3.10
None
Command complete status (0xFFFF) is returned when the register write is
complete.
Force Transfer Acknowledge (FORCE_TA)
DEBUG_D logic implements the new FORCE_TA serial BDM command to resolve a hung bus condition.
In some system designs, references to certain unmapped memory addresses may cause the external bus to
hang with no transfer acknowledge generated by any bus responders. The FORCE_TA forces generation of
a transfer acknowledge signal, which can be logically summed into the normal acknowledge logic located
in the system integration module (SIM) outside of the ColdFire core.
There are two scenarios of interest, one caused by a processor access and the other caused by a BDM
access. The following sequences identify the operations needed to break the hung bus condition:
• Bus hang caused by processor or external or internal alternate master:
— Assert the breakpoint input to force a processor core halt.
— If the bus hang was caused by a processor access, send in FORCE_TA commands until the
processor is halted, as signaled by PST = 0xF. Due to pipeline and store buffer depths, many
memory accesses may be queued up behind the access causing the bus hang. Repeated
FORCE_TA commands eventually allow processing of all these pending accesses. As soon as the
processor is halted, the system reaches a quiescent, controllable state.
— If the hang was caused by another master, such as a DMA channel, the processor can halt
immediately. In this case as well, multiple assertions of the FORCE_TA command may be
required to terminate the alternate master’s errant access.
• Bus hang caused by BDM access:
— It is assumed the processor is already halted at the time of the errant BDM access. To resolve
the hung bus, it is necessary to process four or more FORCE_TA commands, because the BDM
command may have initiated a cache line access that fetches 4 longwords, each needing a
unique transfer acknowledge.
Formats:
15
12
0x0
11
8
0x0
7
4
0x0
3
0
0x2
Figure 8-41. FORCE_TA Command
Command Sequence:
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Background Debug Mode (BDM)
FORCE_TA
NEXT CMD
???
“CMD COMPLETE”
Figure 8-42. FORCE_TA Command Sequence
Operand Data:
Result Data:
8.5.3.3.11
None
The command complete response, 0xFFFF (with the status bit cleared), is returned
during the next shift operation. This response indicates the FORCE_TA command
was processed correctly and does not necessarily reflect the status of any internal
bus.
Read Control Register (RCREG)
Read the selected control register and return the 32-bit result. Accesses to the processor/memory control
registers are always 32 bits wide, regardless of register width. The second and third words of the command
form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified
control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.
Command/Result Formats:
15
Command
12
11
8
7
4
3
0
0x2
0x9
0x8
0x0
0x0
0x0
0x0
0x0
0x0
Rc
Result
D[31:16]
D[15:0]
Figure 8-43. RCREG Command/Result Formats
Command Sequence:
RCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
READ
CONTROL
REGISTER
XXX
’NOT READY’
NEXT CMD
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR
NEXT CMD
’NOT READY’
Figure 8-44. RCREG Command Sequence
Operand Data:
Result Data:
The only operand is the 32-bit Rc control register select field.
Control register contents are returned as a longword, most-significant word first.
The implemented portion of registers smaller than 32 bits is guaranteed correct;
other bits are undefined.
Rc encoding: See Table 8-26.
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Table 8-26. ColdFire CPU Control Register Map
Name
CPU Space (Rc)
Register Name
Memory Management Control Registers
CACR
0x002
Cache control register
ASID
0x003
Address space identifier
ACR0–ACR3
MMUBAR
0x004–0x007
Access control registers 0–3
0x008
MMU base address register
Processor General-Purpose Registers
D0–D7
0x(0,1)80–0x(0,1)87 Data registers 0–7 (0 = load, 1 = store)
A0–A7
0x(0,1)88–0x(0,1)8F Address registers 0–7 (0 = load, 1 = store) A7 is user stack pointer
Processor Miscellaneous Registers
OTHER_A7
0x800
Other stack pointer
VBR
0x801
Vector base register
MACSR
0x804
MAC status register
MASK
0x805
MAC address mask register
ACC0–ACC3
0x806–0x80B
MAC accumulators 0–3
ACCext01
0x807
MAC accumulator 0, 1 extension bytes
ACCext23
0x808
MAC accumulator 2, 3 extension bytes
SR
0x80E
Status register
PC
0x80F
Program counter
Processor Floating-Point Registers
FPU0
0x810
32 msbs of floating-point data register 0
FPL0
0x811
32 lsbs of floating-point data register 0
FPU1
0x812
32 msbs of floating-point data register 1
FPL1
0x813
32 lsbs of floating-point data register 1
FPU2
0x814
32 msbs of floating-point data register 2
FPL2
0x815
32 lsbs of floating-point data register 2
FPU3
0x816
32 msbs of floating-point data register 3
FPL3
0x817
32 lsbs of floating-point data register 3
FPU4
0x818
32 msbs of floating-point data register 4
FPL4
0x819
32 lsbs of floating-point data register 4
FPU5
0x81A
32 msbs of floating-point data register 5
FPL5
0x81B
32 lsbs of floating-point data register 5
FPU6
0x81C
32 msbs of floating-point data register 6
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Background Debug Mode (BDM)
Table 8-26. ColdFire CPU Control Register Map (Continued)
Name
CPU Space (Rc)
Register Name
FPL6
0x81D
32 lsbs of floating-point data register 6
FPU7
0x81E
32 msbs of floating-point data register 7
FPL7
0x81F
32 lsbs of floating-point data register 7
FPIAR
0x821
Floating-point instruction address register
FPSR
0x822
Floating-point status register
FPCR
0x824
Floating-point control register
Local Memory and Module Control Registers
RAMBAR0
0xC04
RAM base address register 0
RAMBAR1
0xC05
RAM base address register 1
MBAR
0xC0F
Primary module base address register (not a core register)
8.5.3.3.12
BDM Accesses of the Stack Pointer Registers (A7: SSP and USP)
The Version 4 ColdFire core supports two unique stack pointer (A7) registers: the supervisor stack pointer
(SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible
32-bit registers does not uniquely identify one as the SSP and the other as the USP. Rather, the hardware
uses one 32-bit register as the currently-active A7; the other is named simply the OTHER_A7. Thus, the
contents of the two hardware registers is a function of the operating mode of the processor:
if SR[S] = 1
then
else
A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
The BDM programming model supports reads and writes to A7 and OTHER_A7 directly. It is the
responsibility of the external development system to determine the mapping of A7 and OTHER_A7 to the
two program-visible definitions (supervisor and user stack pointers), based on the SR[S].
8.5.3.3.13
BDM Accesses of the EMAC Registers
The presence of rounding logic in the output datapath of the EMAC requires special care for
BDM-initiated reads and writes of its programming model. In particular, any result rounding modes must
be disabled during the read/write process so the exact bit-wise EMAC register contents are accessed.
For example, a BDM read of an accumulator (ACCx) requires the following sequence:
BdmReadACCx (
rcreg
wcreg
rcreg
wcreg
)
macsr;
#0,macsr;
ACCx;
#saved_data,macsr;
//
//
//
//
read current macsr contents & save
disable all rounding modes
read the desired accumulator
restore the original macsr
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Likewise, to write an accumulator register, the following BDM sequence is needed:
BdmWriteACCx (
rcreg
wcreg
wcreg
wcreg
)
macsr;
#0,macsr;
#data,ACCx;
#saved_data,macsr;
//
//
//
//
read current macsr contents & save
disable all rounding modes
write the desired accumulator
restore the original macsr
Additionally, writes to the accumulator extension registers must be performed after the corresponding
accumulators are updated because a write to any accumulator alters the corresponding extension register
contents.
For more information on saving and restoring the complete EMAC programming model, see the
appropriate section of the EMAC chapter.
8.5.3.3.14
BDM Accesses of Floating-Point Data Registers (FPn)
The ColdFire debug architecture allows BDM accesses of the entire programming model (including all
FPU-related registers) of the processor core using RCREG and WCREG. However, certain hardware
restrictions require the accesses related to the 64-bit FPn data registers be performed in a certain manner
to guarantee correct operation.
The serial BDM command structure supports 8-, 16- and 32-bit accesses, but there is no direct mechanism
for accessing 64-bit data values. Rather than changing this well-established protocol and command set,
BDM accesses of 64-bit data values are treated as two independent 32-bit references. In particular, 64-bit
FPn data registers are treated as two separate values from the BDM perspective. Each FPn is partitioned
into upper and lower longwords, FPUn and FPLn.
Either longword can be read first. The processor treats the BDM read command as a pseudo-FMOVEM.
Accordingly, all rounding modes and exception enables are ignored and the 32-bit contents of FPUn or
FPLn are sent to the debug module for transmission over the serial communication channel. The FPU
programming model is unchanged.
To write to an FPU data register, FPUn must be written first and followed by a write to FPLn. The
processor operates as follows: the BDM write to FPUn is performed, which loads the upper 32 bits of an
internal double-precision operand register; the BDM write to FPLn loads the supplied operand into the
lower 32 bits of the same internal register, and the entire 64-bit value is loaded into the selected FPn.
Failure to execute this sequence of commands produces an undefined value in the FPUn.
Note that any BDM write of an FPU register changes the internal state from NULL to IDLE.
8.5.3.3.15
Write Control Register (WCREG)
The operand (longword) data is written to the specified control register. The write alters all 32 register bits.
See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7
stack pointers and the EMAC and FPU programming models.
Command/Result Formats:
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Background Debug Mode (BDM)
15
12
Command
11
8
7
4
3
0
0x2
0x8
0x8
0x0
0x0
0x0
0x0
0x0
0x0
Rc
Result
D[31:16]
D[15:0]
Figure 8-45. WCREG Command/Result Formats
Command Sequence:
WCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
MS DATA
’NOT READY’
LS DATA
’NOT READY’
WRITE
CONTROL
REGISTER
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
NEXT CMD
’NOT READY’
Figure 8-46. WCREG Command Sequence
Operand Data:
Result Data:
8.5.3.3.16
This instruction requires two longword operands. The first selects the register to
which the operand data is to be written; the second contains the data.
Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern of
0x0001.
Read Debug Module Register (RDMREG)
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR clears the trigger status bits
(CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered
and no level-2 breakpoint has been enabled.
Command/Result Formats:
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15
Command
12
11
0x2
8
7
5
0xD
4
0
100
Result
DRc
D[31:16]
D[15:0]
Figure 8-47. RDMREG BDM Command/Result Formats
Table 8-27 shows the definition of DRc encoding.
Table 8-27. Definition of DRc Encoding—Read
DRc[4:0]
Debug Register Definition
Mnemonic
Initial State
Page
0x00
Configuration/Status
CSR
0x0
p. 8-11
0x01–0x1F
Reserved
—
—
—
Command Sequence:
RDMREG
???
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
Figure 8-48. RDMREG Command Sequence
Operand Data:
Result Data:
8.5.3.3.17
None
The contents of the selected debug register are returned as a longword value. The
data is returned most-significant word first.
Write Debug Module Register (WDMREG)
The operand (longword) data is written to the specified debug module register. All 32 bits of the register
are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU
accesses are performed using the WDEBUG instruction.
Command Format:
Figure 8-49. WDMREG BDM Command Format
15
12
0x2
11
8
7
0xC
5
100
4
0
DRc
D[31:16]
D[15:0]
Table 8-6 shows the definition of the DRc write encoding.
Command Sequence:
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Real-Time Debug Support
WDMREG
???
MS DATA
’NOT READY’
LS DATA
’NOT READY’
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
NEXT CMD
’CMD COMPLETE’
Figure 8-50. WDMREG Command Sequence
Operand Data:
Longword data is written into the specified debug register. The data is supplied
most-significant word first.
Command complete status (0xFFFF) is returned when register write is complete.
Result Data:
8.6
Real-Time Debug Support
The ColdFire Family provides support debugging real-time applications. For these types of embedded
systems, the processor must continue to operate during debug. The foundation of this area of debug support
is that while the processor cannot be halted to allow debugging, the system can generally tolerate the small
intrusions of the BDM inserting instructions into the pipeline with minimal effect on real-time operation.
The debug module provides three types of breakpoints: PC with mask, operand address range, and data
with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger
response also programmable. The debug module programming model can be written from either the
external development system using the debug serial interface or from the processor’s supervisor
programming model using the WDEBUG instruction. Only CSR is readable using the external
development system.
8.6.1
Theory of Operation
Breakpoint hardware can be configured through TDR[TCR] to respond to triggers by displaying
PSTDDATA, initiating a processor halt, or generating a debug interrupt. As shown in Table 8-28, when a
breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the PSTDDATA output port of the
DDATA information when it is not displaying captured processor status, operands, or branch addresses.
See Section 8.3.2, “Processor Stopped or Breakpoint State Change (PST = 0xE).”
Table 8-28. PSTDDATA Nibble/CSR[BSTAT] Breakpoint Response
PSTDDATA Nibble/CSR[BSTAT] 1
1
Breakpoint Status
0000/0000
No breakpoints enabled
0010/0001
Waiting for level-1 breakpoint
0100/0010
Level-1 breakpoint triggered
1010/0101
Waiting for level-2 breakpoint
1100/0110
Level-2 breakpoint triggered
Encodings not shown are reserved for future use.
The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR read when either
a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled.
Status is also cleared by writing to either TDR or XTDR to disable trigger options.
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BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates,
a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner: exception recognition and processing are initiated before
the excepting instruction is executed. All other breakpoint events are recognized on the processor’s local
bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these
interrupts are said to be imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] = 01, a
breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher
than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the
processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC
breakpoint to occur before the targeted instruction executes and is precise. This is possible because the PC
breakpoint is enabled when interrupt sampling occurs. For address and data breakpoints, reporting is
considered imprecise because several instructions may execute after the triggering address or data is
detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception
processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for
multiple cycles. The core enters emulator mode when exception processing begins. After the standard
8-byte exception stack is created, the processor fetches a unique exception vector from the vector table.
Table 8-29 describes the two unique entries that distinguish PC breakpoints from other trigger events.
Table 8-29. Exception Vector Assignments
Vector Number
Vector Offset (Hex)
Stacked Program Counter
Assignment
12
0x030
Next
Non-PC-breakpoint debug interrupt
13
0x034
Next
PC-breakpoint debug interrupt
(Refer to the ColdFire Programmer’s Reference Manual.)
In the case of a two-level trigger, the last breakpoint event determines the exception vector; however, if
the second-level trigger is PC || Address {&& Data} (as shown in the last condition in the code example
in Section 8.4.11.1, “Resulting Set of Possible Trigger Combinations”), the vector taken is determined by
the first condition that occurs after the first-level trigger: vector 13 if PC occurs first or vector 12 if Address
{&& Data} occurs first. If both occur simultaneously, the non-PC-breakpoint debug interrupt is taken
(vector number 12).
Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. The
debug interrupt handler can use supervisor instructions to save the necessary context such as the state of
all program-visible registers into a reserved memory area.
During a debug interrupt service routine, all normal interrupt requests are evaluated and sampled once per
instruction. If any exception occurs, the processor responds as follows:
1. It saves a copy of the current value of the emulator mode state bit and then exits emulator mode by
clearing the actual state.
2. Bit 1 of the fault status field (FS1) in the next exception stack frame is set to indicate the
processor was in emulator mode when the interrupt occurred. This corresponds to bit 17 of the
longword at the top of the system stack. See Section 3.8.1, “Exception Stack Frame Definition.”
3. It passes control to the appropriate exception handler.
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Real-Time Debug Support
4. It executes an RTE instruction when the exception handler finishes. During the processing of the
RTE, FS1 is reloaded from the system stack. If this bit is set, the processor sets the emulator mode
state and resumes execution of the original debug interrupt service routine. This is signaled
externally by the generation of the PST value that originally identified the debug interrupt
exception, that is, PST = 0xD.
Fault status encodings are listed in Table 5-2. Implementation of this debug interrupt handling fully
supports the servicing of a number of normal interrupt requests during a debug interrupt service routine.
The emulator mode state bit is essentially changed to be a program-visible value, stored into memory
during exception stack frame creation, and loaded from memory by the RTE instruction.
When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator
mode. After the debug interrupt handler completes execution, the external development system can use
BDM commands to read the reserved memory locations.
In Revision A, if a hardware breakpoint such as a PC trigger is left unmodified by the debug interrupt
service routine, another debug interrupt is generated after the completion of the RTE instruction. In
Revisions B and C, the generation of another debug interrupt during the first instruction after the RTE exits
emulator mode is inhibited. This behavior is consistent with the existing logic involving trace mode where
the first instruction executes before another trace exception is generated. Thus, all hardware breakpoints
are disabled until the first instruction after the RTE completes execution, regardless of the programmed
trigger response.
8.6.1.1
Emulator Mode
Emulator mode is used to facilitate nonintrusive emulator functionality. This mode can be entered in three
different ways:
• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is
negated and the processor begins reset exception processing. It can be set while the processor is
halted before reset exception processing begins. See Section 8.5.1, “CPU Halt.”
• A debug interrupt always puts the processor in emulation mode when debug interrupt exception
processing begins.
• Setting CSR[TRC] forces the processor into emulation mode when trace exception processing
begins.
While operating in emulation mode, the processor exhibits the following properties:
• Unmasked interrupt requests are serviced. The resulting interrupt exception stack frame has FS[1]
set to indicate the interrupt occurred while in emulator mode.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory
accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5 or 0x6.
This includes stack frame writes and the vector fetch for the exception that forced entry into this
mode.
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding
for emulator mode entry (0xD) and exit (0x7).
8.6.2
Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM commands. BDM
commands may be executed while the processor is running, except the following:
• Read/write address and data registers
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•
Read/write control registers
For BDM commands that access memory, the debug module requests the processor’s local bus. The
processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
NOTE
Breakpoint registers must be carefully configured in a development system
if the processor is executing. The debug module contains no hardware
interlocks, so TDR and XTDR should be disabled while breakpoint registers
are loaded, after which TDR and XTDR can be written to define the exact
trigger. This prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU
is writing the debug’s registers (DSCLK must be inactive).
8.7
Debug C Definition of PSTDDATA Outputs
This section specifies the ColdFire processor and debug module’s generation of the PSTDDATA output on
an instruction basis. In general, the PSTDDATA output for an instruction is defined as follows:
PSTDDATA = 0x1, {[0x89B], operand}
where the {...} definition is optional operand information defined by the setting of the CSR.
The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST
value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the PSTDDATA output
{1, 2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions, CSR[BTB] provides the
capability to display the target instruction address on the PSTDDATA output {2, 3, or 4 bytes} using a PST
value of {0x9, 0xA, or 0xB}.
8.7.1
User Instruction Set
Table 8-30 shows the PSTDDATA specification for user-mode instructions. Rn represents any {Dn, An}
register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the destination
operand. For a given instruction, the optional operand data is displayed only for those effective addresses
referencing memory.
Table 8-30. PSTDDATA Specification for User-Mode Instructions
Instruction
Operand Syntax
PSTDDATA
add.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
add.l
Dy,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
adda.l
<ea>y,Ax
PSTDDATA = 0x1,{0xB, source operand}
addi.l
#<data>,Dx
PSTDDATA = 0x1
addq.l
#<data>,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
addx.l
Dy,Dx
PSTDDATA = 0x1
and.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
and.l
Dy,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
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Debug C Definition of PSTDDATA Outputs
Table 8-30. PSTDDATA Specification for User-Mode Instructions (Continued)
Instruction
Operand Syntax
PSTDDATA
andi.l
#<data>,Dx
PSTDDATA = 0x1
asl.l
{Dy,#<data>},Dx
PSTDDATA = 0x1
asr.l
{Dy,#<data>},Dx
PSTDDATA = 0x1
bcc.{b,w,l}
if taken, then PSTDDATA = 0x5, else PSTDDATA = 0x1
bchg.{b,l}
#<data>,<ea>x
PSTDDATA = 0x1,{0x8, source},{0x8, destination}
bchg.{b,l}
Dy,<ea>x
PSTDDATA = 0x1,{0x8, source},{0x8, destination}
bclr.{b,l}
#<data>,<ea>x
PSTDDATA = 0x1,{0x8, source},{0x8, destination}
bclr.{b,l}
Dy,<ea>x
PSTDDATA = 0x1,{0x8, source},{0x8, destination}
bra.{b,w,l}
PSTDDATA = 0x5
bset.{b,l}
#<data>,<ea>x
PSTDDATA = 0x1,{0x8, source},{0x8, destination}
bset.{b,l}
Dy,<ea>x
PSTDDATA = 0x1,{0x8, source},{0x8, destination}
bsr.{b,w,l}
PSTDDATA = 0x5,{0xB, destination operand}
btst.{b,l}
#<data>,<ea>x
PSTDDATA = 0x1,{0x8, source operand}
btst.{b,l}
Dy,<ea>x
PSTDDATA = 0x1,{0x8, source operand}
clr.b
<ea>x
PSTDDATA = 0x1,{0x8, destination operand}
clr.l
<ea>x
PSTDDATA = 0x1,{0xB, destination operand}
clr.w
<ea>x
PSTDDATA = 0x1,{0x9, destination operand}
cmp.b
<ea>y,Dx
PSTDDATA = 0x1, {0x8, source operand}
cmp.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
cmp.w
<ea>y,Dx
PSTDDATA = 0x1, {0x9, source operand}
cmpa.l
<ea>y,Ax
PSTDDATA = 0x1,{0xB, source operand}
cmpa.w
<ea>y,Ax
PSTDDATA = 0x1, {0x9, source operand}
cmpi.b
#<data>,Dx
PSTDDATA = 0x1
cmpi.l
#<data>,Dx
PSTDDATA = 0x1
cmpi.w
#<data>,Dx
PSTDDATA = 0x1
divs.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
divs.w
<ea>y,Dx
PSTDDATA = 0x1,{0x9, source operand}
divu.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
divu.w
<ea>y,Dx
PSTDDATA = 0x1,{0x9, source operand}
eor.l
Dy,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
eori.l
#<data>,Dx
PSTDDATA = 0x1
ext.l
Dx
PSTDDATA = 0x1
ext.w
Dx
PSTDDATA = 0x1
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Table 8-30. PSTDDATA Specification for User-Mode Instructions (Continued)
Instruction
extb.l
Operand Syntax
Dx
PSTDDATA
PSTDDATA = 0x1
PSTDDATA = 0x11
illegal
jmp
<ea>y
PSTDDATA = 0x5, {[0x9AB], target address} 2
jsr
<ea>y
PSTDDATA = 0x5, {[0x9AB], target address},{0xB , destination operand}2
lea.l
<ea>y,Ax
PSTDDATA = 0x1
link.w
Ay,#<displacement> PSTDDATA = 0x1,{0xB, destination operand}
lsl.l
{Dy,#<data>},Dx
PSTDDATA = 0x1
lsr.l
{Dy,#<data>},Dx
PSTDDATA = 0x1
mov3q.l
#<data>,<ea>x
PSTDDATA = 0x1, {0xB, destination operand}
move.b
<ea>y,<ea>x
PSTDDATA = 0x1,{0x8, source},{0x8, destination}
move.l
<ea>y,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
move.w
<ea>y,<ea>x
PSTDDATA = 0x1,{0x9, source},{0x9, destination}
move.w
CCR,Dx
PSTDDATA = 0x1
move.w
{Dy,#<data>},CCR
PSTDDATA = 0x1
movea.l
<ea>y,Ax
PSTDDATA = 0x1,{0xB, source}
movea.w
<ea>y,Ax
PSTDDATA = 0x1,{0x9, source}
movem.l
#list,<ea>x
PSTDDATA = 0x1,{0xB, destination},... 3
movem.l
<ea>y,#list
PSTDDATA = 0x1,{0xB, source},... 3
moveq.l
#<data>,Dx
PSTDDATA = 0x1
muls.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
muls.w
<ea>y,Dx
PSTDDATA = 0x1,{0x9, source operand}
mulu.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
mulu.w
<ea>y,Dx
PSTDDATA = 0x1,{0x9, source operand}
mvs.b
<ea>y,Dx
PSTDDATA = 0x1, {0x8, source operand}
mvs.w
<ea>y,Dx
PSTDDATA = 0x1, {0x9, source operand}
mvz.b
<ea>y,Dx
PSTDDATA = 0x1, {0x8, source operand}
mvz.w
<ea>y,Dx
PSTDDATA = 0x1, {0x9, source operand}
neg.l
Dx
PSTDDATA = 0x1
negx.l
Dx
PSTDDATA = 0x1
nop
PSTDDATA = 0x1
not.l
Dx
PSTDDATA = 0x1
or.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
or.l
Dy,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
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Debug C Definition of PSTDDATA Outputs
Table 8-30. PSTDDATA Specification for User-Mode Instructions (Continued)
Instruction
Operand Syntax
PSTDDATA
ori.l
#<data>,Dx
PSTDDATA = 0x1
pea.l
<ea>y
PSTDDATA = 0x1,{0xB, destination operand}
pulse
PSTDDATA = 0x4
rems.l
<ea>y,Dw:Dx
PSTDDATA = 0x1,{0xB, source operand}
remu.l
<ea>y,Dw:Dx
PSTDDATA = 0x1,{0xB, source operand}
rts
PSTDDATA = 0x1, PSTDDATA = 0x5, {[0x9AB], target address}
sats.l
Dx
PSTDDATA = 0x1
scc.b
Dx
PSTDDATA = 0x1
sub.l
<ea>y,Dx
PSTDDATA = 0x1,{0xB, source operand}
sub.l
Dy,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
suba.l
<ea>y,Ax
PSTDDATA = 0x1,{0xB, source operand}
subi.l
#<data>,Dx
PSTDDATA = 0x1
subq.l
#<data>,<ea>x
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
subx.l
Dy,Dx
PSTDDATA = 0x1
swap.w
Dx
PSTDDATA = 0x1
tas.b
<ea>x
PSTDDATA = 0x1, {0x8, source}, {0x8, destination}
tpf
PST = 0x1
tpf.l
#<data>
PST = 0x1
tpf.w
#<data>
PST = 0x1
trap
#<data>
PSTDDATA = 0x11
tst.b
<ea>x
PSTDDATA = 0x1,{0x8, source operand}
tst.l
<ea>y
PSTDDATA = 0x1,{0xB, source operand}
tst.w
<ea>y
PSTDDATA = 0x1,{0x9, source operand}
unlk
Ax
PSTDDATA = 0x1,{0xB, destination operand}
wddata.b
<ea>y
PSTDDATA = 0x4, {0x8, source operand
wddata.l
<ea>y
PSTDDATA = 0x4, {0xB, source operand
wddata.w
<ea>y
PSTDDATA = 0x4, {0x9, source operand
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1
During normal exception processing, the PSTDDATA output is driven to a 0xC indicating the exception
processing state. The exception stack write operands, as well as the vector read and target address of the
exception handler may also be displayed.
Exception ProcessingPSTDDATA = 0xC,{0xB,destination},// stack frame
{0xB,destination},// stack frame
{0xB,source},// vector read
PSTDDATA = 0x5,{[0x9AB],target}// handlerPC
The PSTDDATA specification for the reset exception is shown below:
Exception ProcessingPSTDDATA = 0xC,
PSTDDATA = 0x5,{[0x9AB],target}// handlerPC
The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated
as instruction fetches.
For all types of exception processing, the PSTDDATA = 0xC value is driven at all times, unless the PSTDDATA
output is needed for one of the optional marker values or for the taken branch indicator (0x5).
2
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective
address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An),
(d8,An,Xi), (d8,PC,Xi).
3 For Move Multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the
operand address reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For
these line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value.
The automatic line-sized burst transfers are provided to maximize performance during these sequential
memory access operations.
Table 8-31 shows the PSTDDATA specification for multiply-accumulate instructions.
Table 8-31. PSTDDATA Values for User-Mode Multiply-Accumulate Instructions
Instruction
Operand Syntax
PSTDDATA
mac.l
Ry,Rx
PSTDDATA = 0x1
mac.l
Ry,Rx,<ea>y,Rw,ACCx
PSTDDATA = 0x1,{0xB, source operand}
mac.l
Ry,Rx,ACCx
PSTDDATA = 0x1
mac.l
Ry,Rx,ea,Rw
PSTDDATA = 0x1,{0xB, source operand}
mac.w
Ry,Rx
PSTDDATA = 0x1
mac.w
Ry,Rx,<ea>y,Rw,ACCx
PSTDDATA = 0x1,{0xB, source operand}
mac.w
Ry,Rx,ACCx
PSTDDATA = 0x1
mac.w
Ry,Rx,ea,Rw
PSTDDATA = 0x1,{0xB, source operand}
move.l
{Ry,#<data>},ACCext01
PSTDDATA = 0x1
move.l
{Ry,#<data>},ACCext23
PSTDDATA = 0x1
move.l
{Ry,#<data>},ACCx
PSTDDATA = 0x1
move.l
{Ry,#<data>},MACSR
PSTDDATA = 0x1
move.l
{Ry,#<data>},MASK
PSTDDATA = 0x1
move.l
ACCext01,Rx
PSTDDATA = 0x1
move.l
ACCext23,Rx
PSTDDATA = 0x1
move.l
ACCy,ACCx
PSTDDATA = 0x1
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Debug C Definition of PSTDDATA Outputs
Table 8-31. PSTDDATA Values for User-Mode Multiply-Accumulate Instructions (Continued)
Instruction
Operand Syntax
PSTDDATA
move.l
ACCy,Rx
PSTDDATA = 0x1
move.l
MACSR,CCR
PSTDDATA = 0x1
move.l
MACSR,Rx
PSTDDATA = 0x1
move.l
MASK,Rx
PSTDDATA = 0x1
msac.l
Ry,Rx
PSTDDATA = 0x1
msac.l
Ry,Rx,<ea>y,Rw,ACCx
PSTDDATA = 0x1,{0xB, source operand}
msac.l
Ry,Rx,ACCx
PSTDDATA = 0x1
msac.l
Ry,Rx,<ea>y,Rw
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
msac.w
Ry,Rx
PSTDDATA = 0x1
msac.w
Ry,Rx,<ea>y,Rw,ACCx
PSTDDATA = 0x1,{0xB, source operand}
msac.w
Ry,Rx,ACCx
PSTDDATA = 0x1
msac.w
Ry,Rx,<ea>y,Rw
PSTDDATA = 0x1,{0xB, source},{0xB, destination}
Table 8-32 shows the PSTDDATA specification for floating-point instructions; note that <ea>y includes
FPy, Dy, Ay, and <mem>y addressing modes. The optional operand capture and display applies only to the
<mem>y addressing modes. Note also that the PSTDDATA values are the same for a given instruction,
regardless of explicit rounding precision.
Table 8-32. PSTDDATA Values for User-Mode Floating-Point Instructions
Instruction 1
Operand Syntax
PSTDDATA
fabs.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fadd.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fbcc.{w,l}
<label>
if taken, then PSTDDATA = 5, else PSTDDATA = 0x1
fcmp.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fdiv.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fint.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fintrz.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fmove.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fmove.sz
FPy,<ea>x
PSTDDATA = 0x1, [89B], destination}
fmove.l
<ea>y,FP*R
PSTDDATA = 0x1, B, source}
fmove.l
FP*R,<ea>x
PSTDDATA = 0x1, B, destination}
fmovem
<ea>y,#list
PSTDDATA = 0x1
fmovem
#list,<ea>x
PSTDDATA = 0x1
fmul.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
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Table 8-32. PSTDDATA Values for User-Mode Floating-Point Instructions (Continued)
Instruction 1
fneg.sz
Operand Syntax
PSTDDATA
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fnop
PSTDDATA = 0x1
fsqrt.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
fsub.sz
<ea>y,FPx
PSTDDATA = 0x1, [89B], source}
ftst.sz
<ea>y
PSTDDATA = 0x1, [89B], source}
1
The FP*R notation refers to the floating-point control registers: FPCR, FPSR, and FPIAR.
Depending on the size of any external memory operand specified by the f<op>.fmt field, the data marker
is defined as shown in Table 8-33.
Table 8-33. Data Markers and FPU Operand Format Specifiers
8.7.2
Format Specifier
Data Marker
.b
8
.w
9
.l
B
.s
B
.d
Never captured
Supervisor Instruction Set
The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown
below. The PSTDDATA specification for these opcodes is shown in Table 8-34.
Table 8-34. PSTDDATA Specification for Supervisor-Mode Instructions
Instruction
Operand Syntax
PSTDDATA
cpushl
dc,(Ax)
ic,(Ax)
bc,(Ax)
PSTDDATA = 0x1
frestore
<ea>y
PSTDDATA = 0x1
fsave
<ea>x
PSTDDATA = 0x1
halt
PSTDDATA = 0x1,
PSTDDATA = 0xF
intouch
(Ay)
PSTDDATA = 0x1
move.l
Ay,USP
PSTDDATA = 0x1
move.l
USP,Ax
PSTDDATA = 0x1
move.w
SR,Dx
PSTDDATA = 0x1
move.w
{Dy,#<data>},SR
PSTDDATA = 0x1, {0x3}
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ColdFire Debug History
Table 8-34. PSTDDATA Specification for Supervisor-Mode Instructions (Continued)
Instruction
movec.l
Operand Syntax
Ry,Rc
rte
PSTDDATA
PSTDDATA = 0x1, {8, ASID}
PSTDDATA = 0x7, {0xB, source operand}, {3},{0xB, source operand}, {DD},
PSTDDATA = 0x5, {[0x9AB], target address}
stop
#<data>
PSTDDATA = 0x1,
PSTDDATA = 0xE
wdebug.l
<ea>y
PSTDDATA = 0x1, {0xB, source, 0xB, source}
The move-to-SR and RTE instructions include an optional PSTDDATA = 0x3 value, indicating an entry
into user mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode,
a multiple-cycle status of 0xD is signaled.
Similar to the exception processing mode, the stopped state (PSTDDATA = 0xE) and the halted state
(PSTDDATA = 0xF) display this status throughout the entire time the ColdFire processor is in the given
mode.
8.8
ColdFire Debug History
This section describes the origins of the ColdFire debug systems.
8.8.1
ColdFire Debug Classic: The Original Definition
The original design, Revision A, provided debug support in three separate areas:
• Real-time trace
• Background debug mode (BDM)
• Real-time debug
The real-time debug features may be accessed from the external BDM emulator or from the supervisor
programming model of the processor. The hardware breakpoint registers include: a PC breakpoint + mask,
two address registers for defining a specific address or a range of addresses, and a data breakpoint + mask.
The original design supported breakpoints of the form:
if PC_breakpoint is triggered
then respond using user-defined configuration
if Address_breakpoint {&& Data_breakpoint} is triggered
then respond using user-defined configuration
Two-level triggers of the form:
if PC_breakpoint is triggered
then if Address_breakpoint {&& Data_breakpoint} is triggered
then respond using user-defined configuration
if Address_breakpoint {&& Data_breakpoint} is triggered
then if PC_breakpoint is triggered
then respond using user-defined configuration
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The data_breakpoint can be included as an optional part of an address breakpoint.
The ColdFire debug architecture was created to provide this set of functionality without requiring the
traditional connection to the external system bus. Rather, the functionality is provided using only a
connection to a Freescale-defined 26-pin debug connector. By providing the required debug signals in
customer-specific designs, standard third-party emulators can be used for debug of these designs.
NOTE
The baseline debug functionality is described in any of the ColdFire
MCF52xx User’s Manuals, which are available as PDF files at:
http://www.freescale.com/ColdFire/. As an example, see the debug section
of the MCF5272 User’s Manual located under MCF5272 Product
Information.
8.8.2
ColdFire Debug Revision B
During development of the Version 3 ColdFire design, there were a number of enhancements to the
original debug functionality requested by customers and third-party developers. These requests resulted in
an expanded set of debug functionality named Revision B.
The Rev. B enhancements are as follows:
• Addition of a BDM SYNC_PC command to display the processor’s current PC
• Creation of more flexible hardware breakpoint triggers, i.e., support for “OR” combinations
• Removal of the restrictions involving concurrent hardware breakpoint use and BDM command
activity
• Redefinition of the processor status values for the RTS instruction
• An external mechanism to generate a debug interrupt
• A mechanism to inhibit debug interrupts after the RTE exit
• A mechanism to identify the revision level of the debug module
Rev. B enhancements provide backward compatibility with the original design.
8.8.3
ColdFire Debug Revision C
Continuing discussions with customers and the developer community led to Revision C design
enhancements primarily related to improvements in the real-time debug capabilities of the ColdFire
architecture. The remainder of this section details these enhancements.
8.8.3.1
Debug Interrupts and Interrupt Requests (Emulator Mode)
In Rev. A and Rev. B ColdFire debug implementations, the response to a user-defined breakpoint trigger
can be configured to be one of three possibilities:
• The breakpoint trigger can merely be displayed on the DDATA bus, with no internal reaction to the
trigger. The trigger state information is displayed on DDATA in all situations.
• The breakpoint trigger can force the processor to halt and allow BDM activities.
• The breakpoint trigger can generate a special debug interrupt to allow real-time systems to quickly
process the interrupt and return to normal system executing as rapidly as possible.
The occurrence of the debug interrupt exception is treated as a special type of interrupt. It is considered to
be higher in priority than all normal interrupt requests and has special processor status values to provide
an external indication that this interrupt has occurred.
MCF548x Reference Manual, Rev. 3
8-62
Freescale Semiconductor
Freescale-Recommended BDM Pinout
Additionally, the execution of the debug interrupt service routine is forced to be interrupt-inhibited by the
processor hardware. While in this service routine, there is an optional capability to map all instruction and
operand references into a separate address space, so that an emulator could define the routine dynamically.
The current processor implementations actually include a program-invisible state bit that defines this
emulator mode of operation. Also note, the interrupt mask level is not modified during the processing of
a debug interrupt.
Customers with real-time embedded systems have specifically asked for the ability to service normal
interrupt requests while processing the debug interrupt service routine. In many systems of this type,
motion-based servo interrupts must be considered as the highest priority interrupt request.
To provide this functionality and be able to service any number of normal interrupt requests (including the
possibility of nested interrupts), the processor state signaling emulator mode must be included as part of
the exception stack frame.
As part of the Rev. C functionality, the operation of the debug interrupt is modified in the following
manner:
1. The occurrence of the breakpoint trigger, configured to generate a debug interrupt, is treated
exactly as before. The debug interrupt is treated as a higher priority exception relative to the normal
interrupt requests encoded on the interrupt priority input signals.
2. At the appropriate sample point, the ColdFire processor initiates debug interrupt exception
processing. This event is signaled externally by the generation of a unique PST value (PST =
0xD) asserted for multiple cycles. The processor sets the emulator mode state bit as part of this
exception processing.
3. While the processor in the debug interrupt service routine, all normal interrupt requests are
evaluated and sampled once per instruction. While in this routine, if any type of exception occurs,
the processor responds in the following manner:
a) In response to the new exception, the processor saves a copy of the current value of the
emulator mode state bit and then exits emulator mode by clearing the actual state.
b) The new exception stack frame sets bit 1 of the fault status field, using the saved emulator
mode bit, indicating execution while in emulator mode has been interrupted. This corresponds
to bit 17 of the longword at the top of the system stack.
c) Control is passed to the appropriate exception handler.
d) When the exception handler is complete, a Return From Exception (RTE) instruction is
executed. During the processing of the RTE, FS[1] is reloaded from the system stack. If this
bit is asserted, the processor sets the emulator mode state and resumes execution of the
original debug interrupt service routine. This is signaled externally by the generation of the
PST value that originally identified the occurrence of a debug interrupt exception, that is,
PST = 0xD.
Implementation of this revised debug interrupt handling fully supports the servicing of any number of
normal interrupt requests while in a debug interrupt service routine. The emulator mode state bit is
essentially changed to be a program-visible value, stored into memory during exception stack frame
creation and loaded from memory by the RTE instruction.
8.9
Freescale-Recommended BDM Pinout
The ColdFire BDM connector, Figure 8-51, is a 26-pin Berg connector arranged 2 x 13.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-63
Developer reserved 1
1
2
BKPT
GND
3
4
DSCLK
GND
5
6
Developer reserved1
RESET
7
8
DSI
VDD_IO 2
9
10
DSO
GND
11
12
PSTDDATA7
PSTDDATA6
13
14
PSTDDATA5
PSTDDATA4
15
16
PSTDDATA3
PSTDDATA2
17
18
PSTDDATA1
PSTDDATA0
19
20
GND
Freescale reserved
21
22
Freescale reserved
GND
23
24
PSTCLK
VDD_CPU
25
26
TA
1
Pins
2
reserved for BDM developer use.
Supplied by target.
Figure 8-51. Recommended BDM Connector
MCF548x Reference Manual, Rev. 3
8-64
Freescale Semiconductor
Part II
System Integration Unit
Part II describes the system integration unit, which provides overall control of the bus and serves as the
interface between the ColdFire core processor complex and internal peripheral devices. It includes a
general description of the SIU and individual chapters that describe components of the SIU, such as the
interrupt controller, general purpose timers, slice timers, and GPIOs.
Contents
Part II contains the following chapters:
• Chapter 9, “System Integration Unit (SIU),” describes the SIU programming model, bus
arbitration, and system-protection functions for the MCF548x.
• Chapter 10, “Internal Clocks and Bus Architecture,” describes the clocking and internal buses of
the MCF548x and discusses the main functional blocks controlling the XL bus and the XL bus
arbiter
• Chapter 11, “General Purpose Timers (GPT),” describes the functionality of the four general
purpose timers, GPT0–GPT3.
• Chapter 12, “Slice Timers (SLT),” describes the two slice timers, shorter term periodic interrupts,
used in the MCF548x.
• Chapter 13, “Interrupt Controller,” describes operation of the interrupt controller portion of the
SIU. It includes descriptions of the registers in the interrupt controller memory map and the
interrupt priority scheme.
• Chapter 14, “Edge Port Module (EPORT),” describes EPORT module functionality.
• Chapter 15, “GPIO,” describes the operation and programming model of the parallel port pin
assignment, direction-control, and data registers.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
i
MCF548x Reference Manual, Rev. 3
ii
Freescale Semiconductor
Chapter 9
System Integration Unit (SIU)
9.1
Introduction
The system integration unit (SIU) of the MCF548x family integrates several timer functions required by
most embedded systems. The SIU contains the following components:
• Slice timers
• Watchdog timer
• General purpose timers
• General purpose I/O ports
• Interrupt controller
Two internal 32-bit slice timers are provided to create short cycle periodic interrupts, typically utilized for
RTOS scheduling and alarm functionality. A watchdog timer is included that will reset the processor if not
regularly serviced, catching software hang-ups. Up to four 32-bit general purpose timers are included,
which are capable of input capture, output compare, and PWM functionality. Most peripheral I/O pins on
the MCF548x family are muxed with GPIO, adding flexibility and usability to pins on the chip.
The programmable interrupt controller multiplexes the external interrupts, general purpose timers, slice
timers, and peripheral sources to the CF4e core. Refer to Chapter 13, “Interrupt Controller,” for
information about the MCF548x interrupt controller.
The SIU timers are discussed in the following chapters:
• General purpose timers and watchdog timer (GPT0) are described in Chapter 11, “General Purpose
Timers (GPT).”
— The watchdog timer is further detailed in Section 10.3.2.3, “Watchdog Functions.”
• Slice timers are detailed in Chapter 12, “Slice Timers (SLT).”
• GPIO functionality is discussed in Chapter 15, “GPIO.”
9.2
Features
The system integration unit has the following features:
• Interrupt controller
• Two 32-bit slice timers for periodic alarm and interrupt generation
• Software watchdog timer with programmable secondary bus monitor
• Up to four 32-bit general-purpose timers with capture, compare, and PWM capability
• General-purpose I/O ports multiplexed with peripheral pins
• System protection and reset status and control
9.3
Memory Map/Register Definition
Table 9-1 shows the programming model for the SIU.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
9-1
Table 9-1. SIU Register Map
Address
(MBAR +)
Name
CPU+0xC0F
Module Base Address Register
0x04
Byte0
SDRAM Drive Strength Register
Byte3
Access
R/W
1
SDRAMDS
R/W
SBCR
R/W
Reserved
System Breakpoint Control Register
0x1–0x1C
Reserved
0x20
SDRAM Chip Select 0
Configuration Register1
CS0CFG01
R/W
0x24
SDRAM Chip Select 1
Configuration Register1
CS1CFG11
R/W
0x28
SDRAM Chip Select 2
Configuration Register1
CS2CFG21
R/W
0x2C
SDRAM Chip Select 3
Configuration Register1
CS3CFG31
R/W
0x30–0x34
0x38
RESERVED
Sequential Access Control Register
0x3C–0x40
0x44
0x50
SECSACR
R/W
RSR
R/W
JTAGID
R
RESERVED
Reset Status Register
0x48–0x4C
1
Byte2
MBAR
1
0x08–0x0C
0x10
Byte1
RESERVED
JTAG Device Identification Number
The SDRAM Drive Strength and Chip Select Configuration registers are discussed in Chapter 18, “SDRAM Controller
(SDRAMC).” They are shown in this memory map for reference purposes.
9.3.1
Module Base Address Register (MBAR)
The supervisor-level MBAR, Figure 9-1, specifies the base address and allowable access types for all
internal peripherals. It is written with a MOVEC instruction using the CPU address 0xC0F (refer to the
ColdFire Family Programmer’s Reference Manual). MBAR can be read or written through the debug
modules as a read/write register, as described in Chapter 8, “Debug Support.” Only the debug module can
read MBAR.
The MBAR is initialized to 0x8000_0000 at reset; however, it can be relocated to a new base address. To
access internal peripherals, write MBAR with the appropriate base address (BA) after system reset.
All internal peripheral registers occupy a single relocatable memory block along 256-KByte boundaries.
MBAR[BA] is compared to the upper 14 bits of the full 32-bit internal address to determine if an internal
peripheral is being accessed. Any accesses in this range, whether to a valid peripheral address or not, will
be made internally rather than using the external bus.
NOTE
The MBAR region must be mapped to non-cacheable space.
MCF548x Reference Manual, Rev. 3
9-2
Freescale Semiconductor
Memory Map/Register Definition
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
BA
17
16
0
0
W
Reset
R
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
CPU + 0xC0F
Figure 9-1. Module Base Address Register (MBAR)
9.3.1.1
System Breakpoint Control Register (SBCR)
The System Breakpoint Control Register allows for discrete control over functionality of the BKPT signal.
The assertion of the BKPT signal can be programmed to halt the core, DMA, and DSPI or any
combination. In addition, a halt condition in the DMA can be programmed to halt the CPU, or a halt in the
CPU can halt the DMA.
31
R PIN2
CPU
W
Reset
R
30
29
28
27
PIN2 CPU2 DMA2 PIN2
DMA DMA CPU DSPI
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0x0010
Figure 9-2. System Breakpoint Control Register (SBCR)
Table 9-2. SBCR Field Descriptions
Bit
Name
Description
31
PIN2CPU
Pin control of the ColdFire V4e breakpoint. This bit controls whether the BKPT pin can halt the
ColdFire V4e.
0 The assertion of BKPT will not halt the ColdFire V4e core.
1 The assertion of BKPT will halt the ColdFire V4e core.
30
PIN2DMA
Pin control of the multichannel DMA breakpoint. This bit controls whether the BKPT pin can halt
the DMA.
0 The assertion of BKPT will not halt the DMA.
1 The assertion of BKPT will halt the DMA.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
9-3
Table 9-2. SBCR Field Descriptions (Continued)
Bit
Name
Description
29
CPU2DMA ColdFire V4e control of the multichannel DMA breakpoint. This bit controls whether a ColdFire
V4e halt condition causes the assertion of the DMA breakpoint.
0 A ColdFire V4e halt condition will not halt the DMA.
1 A ColdFire V4e halt condition will halt the DMA.
28
DMA2CPU DMA control of the ColdFire V4e breakpoint. This bit controls whether a DMA halt condition
causes the assertion of the ColdFire V4e breakpoint.
0 A DMA halt condition will not halt the ColdFire V4e.
1 A DMA halt condition will halt the ColdFire V4e.
27
PIN2DSPI
26-0
—
9.3.1.2
Pin control of the DSPI breakpoint. This bit controls whether the BKPT pin can halt the DSPI.
0 The assertion of BKPT will not halt the DSPI.
1 The assertion of BKPT will halt the DSPI.
Reserved, should be cleared.
SEC Sequential Access Control Register (SECSACR)
This register is used to control bus accesses to the SEC module. If a sequential accesses to the SEC are
enabled, then data will be buffered to create a single 64-bit access to the SEC instead of splitting up the
transfer into two longwords. This can help to improve overall SEC performance.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEQEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Reg
Addr
MBAR + 0x38
Figure 9-3. SEC Sequential Access Control Register (SECSACR)
Table 9-3. SECSACR Field Descriptions
Bits
Name
31–1
—
0
SEQEN
Description
Reserved
SEC Sequential access enable.
0 SEC Sequential Access is disabled.
1 SEC Sequential Access is enabled.
Note: Setting this bit is recommended when the SEC is in use.
MCF548x Reference Manual, Rev. 3
9-4
Freescale Semiconductor
Memory Map/Register Definition
9.3.1.3
Reset Status Register (RSR)
RSR allows the software, particularly the reset exception service routine, to know what type of reset has
been asserted. When a reset signal is asserted, the associated status bit is set, and it maintains its value until
the software explicitly clears the bit.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
RST
JTG
0
RST
WD
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
R
W
Reset
R
W
Reset
Reg
Addr
MBAR + 0x44
Figure 9-4. Reset Status Register (RSR)
Table 9-4. RSR Field Descriptions
Bits
Name
31–4
—
3
RSTJTG
2
—
1
RSTWD
General purpose watchdog timer reset asserted. Cleared by writing 1 to this bit position or
by external reset.
0
RST
External reset (PLL Lock qualification) asserted. Cleared by writing a 1 to this bit position.
9.3.1.4
Description
Reserved, should be cleared.
JTAG reset asserted. Cleared by writing 1 to this bit position or by external reset.
Reserved, should be cleared.
JTAG Device Identification Number (JTAGID)
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
JTAGID
W
Reset
See Table 9-5
15
14
R
13
12
11
10
9
8
7
JTAGID
W
Reset
See Table 9-5
Reg
Addr
MBAR + 0x50
Figure 9-5. JTAG Device ID Register (JTAGID)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
9-5
Table 9-5. JTAGID Field Descriptions
Bits
Name
Description
31–0
JTAGID
The JTAG Identification Number Register is a read only register which contains the JTAG
ID number for the MCF548x. Its value is hard coded and cannot be modified.
Values for the MCF548x are the following:
MCF5485 0x0800c01d
MCF5484 0x0800d01d
MCF5483 0x0800e01d
MCF5482 0x0800f01d
MCF5481 0x0801001d
MCF5480 0x0801101d
MCF548x Reference Manual, Rev. 3
9-6
Freescale Semiconductor
Chapter 10
Internal Clocks and Bus Architecture
10.1
Introduction
This chapter describes the clocking and internal buses of the MCF548x and discusses the main functional
blocks controlling the XL bus and the XL bus arbiter.
10.1.1
Block Diagram
Figure 10-1 shows a top-level block diagram of the MCF548x products.
ColdFire V4e Core
FPU, MMU
EMAC
32K D-cache
32K I-cache
PLL
DDR SDRAM
Interface
FlexBus
Interface
XL Bus
Arbiter
Memory
Controller
FlexBus
Controller
Cryptography
Accelerator***
XL Bus
Read/Write
Write
DMA
DMA
Bus
Read
32K System
SRAM
GP
Timers x 4
PCI 2.2
Controller
Multichannel DMA
Master Bus Interface and FIFOs
FlexCAN
x2
PCI Interface
& FIFOs
CommBus
DSPI
I2C
PSC x 4
FEC0
FEC1**
Perpheral Communications I/O Interface & Ports
USB 2.0
DEVICE*
Communications
I/O Subsystem
Slice
Timers x 2
PCI I/O Interface and Ports
Watchdog
Timer
R/W
Master/Slave
Interface
Crypto
Interrupt
Controller
Slave
Perpheral I/O Interface & Ports
System
Integration Unit
XL Bus
USB 2.0
PHY*
*Available in MCF5485, MCF5484, MCF5483, and MCF5482 devices.
**Available in MCF5485, MCF5484, MCF5481, and MCF5480 devices.
***Available in MCF5485, MCF5483, and MCF5481 devices.
Figure 10-1. MCF548x Internal Bus Architecture
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-1
10.1.2
Clocking Overview
The MCF548x requires a clock generated externally to be input to the CLKIN signal. The MCF548x uses
this clock as the reference clock for the internal PLL. The internal PLL then generates the clocks needed
by the CPU core and integrated peripherals.
The external PCI and FlexBus signals are always clocked at the same frequency as the CLKIN signal. A
programmable clock multiplier (determined by the AD[12:8] signals at reset) is used to determine the XL
bus frequency. All integrated peripherals and the 32KB system SRAM are clocked at the same frequency
as the XLB. The ColdFire V4e core complex (core, MMU, FPU, SRAMs, etc.) is always clocked at twice
the XLB frequency.
Table 10-1 shows the supported PLL encodings and the corresponding clock frequency ranges.
Table 10-1. MCF548x Divide Ratio Encodings
1
2
AD[12:8]1
Clock
Ratio
CLKIN–PCI and
FlexBus Frequency
Range (MHz)
Internal XLB, SDRAM bus,
and PSTCLK Frequency
Range (MHz)
Core Frequency
Range (MHz)
00011
1:2
41.6–50.0
83.33–100
166.66–200
00101
1:2
25.0–41.5
50.0–83.02
100.0–166.66
01111
1:4
25.0
100
200
All other values of AD[12:8] are reserved.
Note that DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy down to
75 MHz. Check with the memory component specifications to verify.
Figure 10-2 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
Internal Clock
CLKIN
Core Clock
2x
2x
25.0
50.0
50.0
100.0
100.0
200.0
2x
4x
25.0
100.0
200.0
25 40 50 60 70
30 40 50 60 70 80 90 100
60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
CLKIN (MHz)
Internal Clock (MHz)
Core Clock (MHz)
Figure 10-2. CLKIN, Internal Bus, and Core Clock Ratios
10.1.3
Internal Bus Overview
There are three main internal buses in the MCF548x—the extended local bus (XL bus), the internal
peripheral bus (slave bus), and the communication subsystem bus (CommBus). See Figure 10-1.
• XL bus — Interface between the ColdFire core, memory controller, communication subsystem,
FlexBus controller, and PCI controller.
• Internal peripheral bus (slave bus) — The control/data interface from the core to the
communication subsystem or peripheral programming registers and FIFOs. The base address of
this memory-mapped bus will be stored in the internal peripheral bus base address register
(MBAR).
MCF548x Reference Manual, Rev. 3
10-2
Freescale Semiconductor
Introduction
•
CommBus — The data transfer interface between the multichannel DMA and each peripheral
function.
10.1.4
XL Bus Features
Features of the XL bus and its integration modules include the following:
• 32-bit physical address
• 64-bit data bus width
• Split-transaction bus; address and data tenures occur independently.
• One-level address pipeline; supports up to two complete address tenures before the first data tenure
completes.
• Strict, in-order, address and data tenures are enforced.
• Address and data bus “parking” may be used to remove arbitration phase from the address and data
tenures—most recent master, programmed master, or no parking methods supported.
• Access can occur in single (1-8 bytes) beat, or four-beat (32 bytes) burst transfers.
• Eight-level arbitration priority that is hardware selectable for each master with a least recently used
(LRU) protocol for masters of equal priority. Priority may change dynamically based on specific
system requirements.
• Fully static, multiplexed bus architecture.
10.1.5
Internal Bus Transaction Summaries
The XL bus can be mastered by the ColdFire core, multichannel DMA controller, and the PCI controller
(external PCI master). Any of these masters can access all resources available to the XL bus.
Bus masters can access any on-chip or off-chip resources via the XL bus. The sequence is as follows:
• Bus masters gains mastership of the XL bus from the XL bus arbiter.
• The bus master’s address is asserted during the address tenure. XL bus slave devices (SDRAM,
PCI, etc.) decode the address. If the address falls within a slave’s space, it returns an address
acknowledge.
• The bus master initiates the data tenure and transfers the data to the appropriate slave device.
10.1.6
XL Bus Interface Operations
This section describes how the XLB interface operates.
10.1.6.1
Basic Transfer Protocol
An XLB interface memory transaction is illustrated in Figure 10-3. It shows that the transaction consists
of distinct address and data tenures, each having three phases: arbitration, transfer, and termination. The
separation of these operations allows address pipelines and split transactions to be implemented.
Split-bus transaction capability allows one master to have mastership of the address bus, while another
master has mastership of the data bus. Pipelines allows the address tenure of a bus transaction to begin
before the data tenure of the previous transaction finishes.
The data transfer phase can either be one beat or four, depending on whether or not the transaction is a
burst.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-3
Address Tenure
Arbitration
Transfer
Termination
Data Tenure
Arbitration
Transfer
Termination
Figure 10-3. Address and Data Tenures
The following outlines the basic functions of each of the phases:
• Address tenure:
— Arbitration: During arbitration, address bus arbitration signals are used to gain mastership of
the address bus.
— Transfer: After mastership is obtained, the address bus master transfers the address and transfer
attributes on the address bus. Address signals and transfer attribute signals control the address
transfer.
— Termination: After the address transfer, the system signals that the address tenure is complete
or that it must be repeated.
• Data tenure:
— Arbitration: To begin a data tenure, the master arbitrates for data bus mastership.
— Transfer: After mastership is obtained, the data bus master samples the data bus for read
operations or drives the data bus for write operations.
— Termination: Data termination signals are required after each data beat in a data transfer. In a
single-beat transaction, data termination signals also indicate the end of the tenure; in burst
accesses, data termination signals apply to individual beats and indicate the end of the tenure
only after the final data beat.
10.1.6.2
Address Pipelines
The XLB protocol provides independent address and data bus capability to support pipeline and split-bus
transaction system organizations.
The XLB arbiter allows for one level of pipeline. This feature can be enabled and disabled in the Arbiter
Configuration Register (XARB_CFG). While this feature does not improve latency, it can significantly
improve bus/memory throughput, so it should be considered for systems that expect to stress bus
throughput capacity.
The XLB arbiter effects pipelines by regulating address bus grant, data bus grants, and address
acknowledge signals. For example, a one-level pipeline is enabled by asserting the address acknowledge
signal to the current address bus master, as well as granting the address bus to the next requesting master
before the current data bus tenure completes.
MCF548x Reference Manual, Rev. 3
10-4
Freescale Semiconductor
PLL
10.2
PLL
10.2.1
PLL Memory Map/Register Descriptions
Table 10-2. System PLL Memory Map
10.2.2
MBAR
Offset
Name
0x300
System PLL Control Register
Byte0
Byte1
Byte2
Byte3
SPCR
Access
R/W
System PLL Control Register (SPCR)
The system PLL control register (SPCR) defines the clock enables used to control clocks to a set of
peripherals. Unused peripherals can have their clock stopped, reducing power consumption. In addition,
the SPCR contains a read-only bit for the system PLL lock status. At reset, the clock enables are set,
enabling all system PLL gated output clocks.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PLLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
COR
EN
CRY
ENB
0
PSC
EN
0
FB
EN
PCI
EN
MEM
EN
0
1
1
1
1
1
1
1
1
W
Reset
R
W
Reset
CRY CAN1
ENA
EN
1
1
Reg
Addr
USB FEC1 FEC0 DMA CAN0
EN
EN
EN
EN
EN
1
1
1
1
1
MBAR + 0x300
Figure 10-4. System PLL Control Register (SPCR)
Table 10-3. SPCR Field Descriptions
Bits
Name
Description
31
PLLK
30-15
—
14
COREN
Core & Communications Sub-System Clock Enable - Controls clocks for the CF4 Core, System
SRAM, CommBus Arbiter, I2C, Comm Timers, and External DMA modules
13
CRYENB
Crypto Clock Enable B - Controls the fast clock to the SEC
12
CRYENA
Crypto Clock Enable A - Controls the slow clock to the SEC
11
CAN1EN
CAN1 Clock Enable
10
—
System PLL Lock Status - Read-only lock status of the system PLL.
1 PLL has obtained frequency lock
0 PLL has not locked
Reserved, should be cleared.
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-5
Table 10-3. SPCR Field Descriptions (Continued)
Bits
Name
9
PSCEN
8
—
7
USBEN
USB Clock Enable
6
FEC1EN
FEC1 Clock Enable
5
FEC0EN
FEC0 Clock Enable
4
DMAEN
Multi-channel DMA Clock Enable
3
CAN0EN
CAN0 Clock Enable
2
FBEN
FlexBus Clock Enable
1
PCIEN
PCI Bus Clock Enable
0
MEMEN
10.3
Description
PSC Clock Enable - Controls clock for all PSC modules.
Reserved, should be cleared.
Memory Clock Enable - Controls clocks of the SDRAM controller module
XL Bus Arbiter
The XL bus arbiter handles bus arbitration between XL bus masters.
10.3.1
Features
The arbiter features are as follows:
• Eight priority levels
• Priority levels may be changed dynamically by XL bus masters
• XL bus arbitration support for eight masters
• Least recently used (LRU) priority scheme for masters of equal priority
• Multiple masters at each priority level supported
• One level of address pipelines is enforced by the arbiter
• Bus grant parking modes:
— No parking
— Park on last master
— Park on programmed master
• Watchdog timers for various XL bus time-out conditions
10.3.2
10.3.2.1
Arbiter Functional Description
Prioritization
The prioritization function will indicate that a master is requesting the bus and indicate which master has
priority.
Priority is determined first by using the hardcoded master priority or the master n priority bits in the arbiter
master priority register (XARB_PRIEN), depending on the arbiter master priority enable bit for each
master. Secondly, masters at the same level of priority will be further sorted by a least recently used
MCF548x Reference Manual, Rev. 3
10-6
Freescale Semiconductor
XL Bus Arbiter
algorithm (LRU). Once a requesting master is identified as having priority and is granted the bus, that
master will be continue to be granted the bus if:
1. It is requesting the bus. The request must occur immediately after the required 1 clock de-assertion
after a qualified bus grant.
and
2. It is the highest priority device.
and
3. There is no address retry.
Multiple masters at level 0 will only be able to perform one tenure before the bus is passed to the next
master at level 0 using the LRU algorithm.
The priority level of each master may be changed while the arbiter is running. This allows dynamic
changes in priority such as an aging scheme. The arbiter recognizes changes after one clock.
It is possible to control priority by enabling the master priority enable bits for a master (XARB_PRIEN).
This causes the priority to be determined from the master n priority bits in the arbiter master priority
register (XARB_PRI). Once again a system dependent dynamic scheme may be employed.
10.3.2.2
10.3.2.2.1
Bus Grant Mechanism
Bus Grant
The bus grant mechanism generates the address bus grant signals to the masters using the signals from the
prioritization function. It will also generate required indicators of state to the prioritization and watchdog
functions.
The bus grant mechanism will enforce the one level address pipeline. The critical condition is that before
a third address tenure is granted, the first tenure (address and, if needed, data) must be completed. The
arbiter will assert a bus grant to a master when there are masters requesting, or if parking is enabled and
the one level pipeline condition is met.
10.3.2.2.2
Parking Modes
The bus grant mechanism will support the no parking, park on programmed master, and park on last master
bus parking modes.
• When in no parking mode, the arbiter will not assert a bus grant when there are no masters asserting
a bus request.
• In park on programmed master mode, the arbiter will assert a bus grant to the master indicated in
the select parked master field (ACFG[SP]) when no masters are asserting a bus request and the one
level pipeline will not be violated.
• In park on last master mode, the arbiter will assert a bus grant to the last master granted the bus
when no masters are asserting a bus request and the one level pipeline will not be violated.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-7
10.3.2.3
Watchdog Functions
10.3.2.3.1
Timer Functions
There are three watchdog timers: address tenure time out, data tenure time out, and bus activity time out.
Each has a programmable timer count and can be disabled. A timer time-out will set a status bit and trigger
an interrupt if that interrupt is enabled.
• The address tenure watchdog is a 32-bit timer. If an acknowledge is not detected by the
programmed number of clocks after bus grant is accepted, the address watchdog timer will expire
and the arbiter will issue an acknowledge. The related data tenure will be terminated with a transfer
error acknowledge. The arbiter will set the Address Tenure Time-out Status bit in the arbiter status
register and issue an interrupt if that interrupt is enabled.
The upper 28 bits of address tenure time-out are programmed via the address tenure time-out
register. The lower 4 bits are always 0xF.
• The data tenure watchdog is a 32-bit timer. If a data tenure is not terminated, the data watchdog
timer will expire and the arbiter will issue a transfer error acknowledge. The arbiter will set the
Data Tenure Time-out Status bit in the arbiter status register and issue an interrupt if that interrupt
is enabled.
Address Time-out (32 bits) = {address tenure time-out register (28bits), 0xF}
Data Time-out (32 bits) = {data tenure time-out register (28 bits), 0xF}
• The bus activity watchdog is a 32-bit timer. If no bus activity is detected by the programmed
number of clocks, the bus activity watchdog timer will expire and the arbiter will set the Bus
Activity Time-out Status bit in the arbiter status register and issue an interrupt if that interrupt is
enabled.
NOTE
Enabling the data time-out will also enable the address time-out. It is
recommended that the data watchdog timer should always be programmed
to a value that is larger than the address watchdog timer. This prevents the
XL bus arbiter from generating a transfer error acknowledge due to
expiration of the data watchdog timer while the address tenure has not
completed.
10.3.3
XLB Arbiter Register Descriptions
The XLB Arbiter registers and their locations are defined in Table 10-4.
Table 10-4. XL Bus Arbiter Memory Map
MBAR
Offset
Name
0x240
Arbiter Configuration Register
XARB_CFG
R/W
0x244
Arbiter Version Register
XARB_VER
R
0x248
Arbiter Status Register
XARB_SR
R/W
0x24C
Arbiter Interrupt Mask Register
XARB_IMR
R/W
0x250
Arbiter Address Capture
XARB_ADRCAP
R/W
0x254
Arbiter Signal Capture
XARB_SIGCAP
R/W
Byte0
Byte1
Byte2
Byte3
Access
MCF548x Reference Manual, Rev. 3
10-8
Freescale Semiconductor
XL Bus Arbiter
Table 10-4. XL Bus Arbiter Memory Map (Continued)
MBAR
Offset
Name
0x258
Arbiter Address Timeout
XARB_ADRTO
R/W
0x25C
Arbiter Data Timeout
XARB_DATTO
R/W
0x260
Arbiter Bus Timeout
XARB_BUSTO
R/W
0x264
Arbiter Master Priority Enable
XARB_PRIEN
R/W
0x268
Arbiter Master Priority
XARB_PRI
R/W
10.3.3.1
Byte0
Byte1
Byte2
Byte3
Access
Arbiter Configuration Register (XARB_CFG)
The arbiter configuration register is used to enable watchdog functions and arbiter protocol functions.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BA
DT
AT
0
0
0
0
0
0
0
0
1
1
0
R PLDIS
W
Reset
R
SP
0
PM
W
Reset
0
0
Reg
Addr
0
0
0
0
MBAR + 0x0240
Figure 10-5. Arbiter Configuration Register (XARB_CFG)
Table 10-5. XARB_CFG Bit Descriptions
Bit
Name
Description
31
PLDIS
30–11
—
Reserved, should be cleared.
10–8
SP
Select Parked Master. These bits set the master that is used in Park on Programmed Master mode.
000 Master 0
001 Master 1
...
111 Master 7).
7
—
Reserved, should be cleared.
6–5
PM[1:0]
Pipeline Disable. This bit is used to control the pipeline functionality
0 Enable pipeline
1 Disable pipeline
Parking Mode. Parking modes are detailed in Section 10.3.2.2.2, “Parking Modes.”
00 No parking (default)
01 Reserved
10 Park on most recently used master
11 Park on programmed master as specified by the Select Parked Master bits 21:23 above.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-9
Table 10-5. XARB_CFG Bit Descriptions (Continued)
Bit
Name
4
—
Reserved, should be cleared.
3
BA
Bus Activity Time-out Enable. If enabled, the arbiter will set the Bus Activity Time-out Status bit
(XARB_SR[BA]) when the Bus Activity Time-out is reached. Bus Activity Time-out is derived from
the arbiter bus activity time out count register.
0 Disable bus activity time-out
1 Enable bus activity time-out
2
DT
Data Tenure Time-out Enable. If enabled, the arbiter will transfer error acknowledge when the Data
Tenure Time-out is reached. Data Tenure Time-out is derived from the arbiter data tenure time out
count register. Also, the arbiter will set the Data Tenure Time-out Status bit (Arbiter Status Register
Bit 30). Setting this bit will also enable the Address Tenure Time-out. This is required to ensure that
a data time-out will not occur before an address acknowledge.
0 Disable data tenure time-out
1 Enable data tenure time-out
1
AT
Address Tenure Time-out Enable. If enabled, the arbiter will AACK and TEA (if required) when the
Address Tenure Time-out is reached. Address Tenure Time-out is derived from the Arbiter Address
Tenure Time Out Count register. Also, the arbiter will set the Address Tenure Time-out Status bit
(Arbiter Status Register Bit 31). Address Tenure Time-out is also enabled by the DT bit above.
0 Disable address tenure time-out
1 Enable address tenure time-out
0
—
Reserved, should be cleared.
10.3.3.2
31
Description
Arbiter Version Register (XARB_VER)
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
VER
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
R
VER
W
Reset
0
0
Reg
Addr
0
0
0
0
0
0
MBAR + 0x0244
Figure 10-6. Arbiter Version Register (XARB_VER)
Table 10-6. VER Field Descriptions
Bit
Name
31–0
VER
Description
Hardware Version ID. The current version number is 0x0001.
MCF548x Reference Manual, Rev. 3
10-10
Freescale Semiconductor
XL Bus Arbiter
10.3.3.3
Arbiter Status Register (XARB_SR)
The arbiter status register indicates the state of watchdog functions. When a monitored condition occurs,
the respective bit is set to 1. The bit will stay set until the bit is cleared by writing a 1 into that bit. Even if
the causal condition is removed, the bit will remain set until cleared.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SEA
MM
TTA
TTR
ECW
TTM
BA
DT
AT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Reg
Addr
MBAR + 0x0248
Figure 10-7. Arbiter Status Register (XARB_SR)
Table 10-7. XARB_SR Field Descriptions
Bits
Name
31–9
—
8
SEA
Slave Error Acknowledge. This bit is set when an error is detected by any slave devices during the
transfer.
7
MM
Multiple Masters at priority 0. If more than 1 master is recognized at priority 0, this bit is set. Once this
occurs this bit will remain set until cleared. This bit is intended to help in tuning dynamic priority
algorithm development.
6
TTA
TT Address Only. The arbiter automatically AACKs for address only TT codes. This bit is set when this
occurs.
5
TTR
TT Reserved. The arbiter automatically AACKs for reserved TT codes. This bit is set when this occurs.
4
ECW
External Control Word Read/Write. External Control Word Read/Write operations are not supported
on the XL bus. If either occur, the arbiter AACKs and TEAs and sets this bit.
3
TTM
TBST/TSIZ mismatch. Set when an illegal/reserved TBST and TSIZ[0:2] combination occurs. These
combinations are TBST asserted and TSIZ[0:2] = 000, 001, 011, or 1xx (x is 0 or 1).
2
BA
Bus Activity Tenure Time-out. Set when the bus activity time-out counter expires.
1
DT
Data Tenure Time-out. Set when the data tenure time-out counter expires.
0
AT
Address Tenure Time-out. Set when the address tenure time-out counter expires.
10.3.3.4
Description
Reserved, should be cleared.
Arbiter Interrupt Mask Register (XARB_IMR)
The arbiter interrupt mask register is used to enable a status bit to cause an interrupt. If the interrupt mask
and corresponding status bits are set in the arbiter status register and arbiter interrupt mask register, the
arbiter will assert the interrupt signal. Normally, an interrupt service routine would read the status register
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-11
to determine the state of the arbiter. It is possible that multiple conditions exist that would cause an
interrupt. Disabling an interrupt by writing a 0 to a bit in this register will not clear the status bit in the
arbiter status register.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
BAE
DTE
ATE
0
0
0
0
0
0
0
0
0
0
W
Reset
R
SEAE MME TTAE TTRE ECWE TTME
W
Reset
Reg
Addr
0
0
0
0
0
0
MBAR + 0x024C
Figure 10-8. Arbiter Interrupt Mask Register (XARB_IMR)
Table 10-8. XARB_IMR Field Descriptions
Bits
Name
Description
31–9
—
8
SEAE
Slave Error Acknowledge interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
7
MME
Multiple Masters at priority 0 interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
6
TTAE
TT Address Only interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
5
TTRE
TT Reserved interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
4
ECWE
External Control Word Read/Write interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
3
TTME
TBST/TSIZ mismatch interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
2
BAE
Bus Activity Tenure Time-out interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
10-12
Freescale Semiconductor
XL Bus Arbiter
Table 10-8. XARB_IMR Field Descriptions (Continued)
Bits
Name
1
DTE
Data Tenure Time-out interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
0
ATE
Address Tenure Time-out interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
10.3.3.5
Description
Arbiter Address Capture Register (XARB_ADRCAP)
The arbiter address capture register will capture the address for a tenure that has an address time-out, data
time-out, or there is a transfer error acknowledge from another source. This value is held until unlocked
by writing any value to the arbiter address capture register or arbiter bus signal capture register. This value
is also unlocked by writing a 1 to either XARB_SR[DT] or XARB_SR[AT]. Unlocking the register does
not clear its contents.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
ADRCAP
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
ADRCAP
W
Reset
0
0
0
Reg
Addr
0
0
0
0
0
0
MBAR + 0x0250
Figure 10-9. Arbiter Address Capture Register (XARB_ADRCAP)
Table 10-9. XARB_ADRCAP Field Descriptions
Bits
Name
Description
31–0
ADRCAP
Address that is captured when a bus error occurs. This happens on an address time-out,
data time-out, or any transfer error acknowledge.
10.3.3.6
Arbiter Bus Signal Capture Register (XARB_SIGCAP)
Important bus signals are captured when a bus error occurs. This happens on an address time-out, data
time-out, or any transfer error acknowledge.
The arbiter bus signal capture register will capture TT, TBST, and TSIZ for a tenure that has an address
time-out or data time-out, or there is a transfer error acknowledge from another source. These values are
held until unlocked by writing any value to the arbiter address capture register (XARB_ADRCAP) or
arbiter bus signal capture register (XARB_SIGCAP). These values are also unlocked by writing a 1 to
either XARB_SR[DT] or XARB_SR[AT]. Unlocking the register does not clear its contents.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-13
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
—
TBST
0
0
0
0
0
0
0
0
0
0
W
Reset
R
TSIZ[0:2]
TT[0:4]
W
Reset
0
Reg
Addr
0
0
0
0
0
MBAR + 0x0254
Figure 10-10. Arbiter Bus Signal Capture Register (XARB_SIGCAP)
Table 10-10. XARB_SIGCAP Field Descriptions
Bits
Name
31–10
—
9–7
TSIZ[0:2]
6
—
5
TBST
4–0
TT
10.3.3.7
R
Description
Reserved, should be cleared.
TSIZ[0:2]
Reserved, should be cleared
TBST
TT[0:4]
Arbiter Address Tenure Time Out Register (XARB_ADRTO)
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
21
20
19
18
17
16
1
1
1
1
1
1
6
5
4
3
2
1
0
1
1
1
1
1
1
1
ADRTO
W
Reset
R
ADRTO
W
Reset
Reg
Addr
1
1
1
1
1
1
1
1
1
MBAR + 0x0258
Figure 10-11. Arbiter Address Tenure Time Out Register (XARB_ADRTO)
MCF548x Reference Manual, Rev. 3
10-14
Freescale Semiconductor
XL Bus Arbiter
Table 10-11. XARB_ADRTO Field Descriptions
Bits
Name
31–28
—
27–0
ADRTO
10.3.3.8
R
Description
Reserved, should be cleared.
Upper 28-bits of the Address time-out counter value. This field is prepended to 0xF to
generate the full 32-bit time-out counter value.
Arbiter Data Tenure Time Out Register (XARB_DATTO)
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
21
20
19
18
17
16
1
1
1
1
1
1
6
5
4
3
2
1
0
1
1
1
1
1
1
1
DATTO
W
Reset
R
DATTO
W
Reset
1
1
1
Reg
Addr
1
1
1
1
1
1
MBAR + 0x025C
Figure 10-12. Arbiter Data Tenure Time Out Register (XARB_DATTO)
Table 10-12. XARB_DATTO Field Descriptions
Bits
Name
31–28
—
27–0
DATTO
Description
Reserved, should be cleared.
Upper 28-bits fo the Data time-out counter value. This field is prepended to 0xF to generate
the full 32-bit time-out counter value.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-15
10.3.3.9
Arbiter Bus Activity Time Out Register (XARB_BUSTO)
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
BUSTO
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
BUSTO
W
Reset
1
1
1
1
1
1
1
1
Reg
Addr
1
MBAR + 0x0260
Figure 10-13. Arbiter Bus Activity Time Out Register (XARB_BUSTO)
Table 10-13. XARB_BUSTO Field Descriptions
Bits
Name
31–0
BUSTO
Description
Bus activity time-out counter value in XLB clocks.
10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN)
The arbiter master priority enable register determines whether the arbiter uses the hardwired or software
programmable priority for a master. The default is enabled for all masters. Both methods may be used at
the same time for different masters. This register may be written at any time. The change will become
effective 1 clock after the register is written.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
—
—
—
—
M3
M2
—
M0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
W
Reset
R
W
Reset
Reg
Addr
MBAR + 0x0264
Figure 10-14. Arbiter Master Priority Enable Register (XARB_PRIEN)
MCF548x Reference Manual, Rev. 3
10-16
Freescale Semiconductor
XL Bus Arbiter
Table 10-14. XARB_PRIEN Field Descriptions
Bits
Name
Description
31–4
—
Reserved, should be cleared.
3
M3
Master 3 Priority Register Enable
2
M2
Master 2 Priority Register Enable
1
—
Reserved, should be cleared.
0
M0
Master 0 Priority Register Enable
When enabled, the software programmable value in the arbiter master priority register (XARB_PRI) is
used as the priority for the master. When disabled, the master’s priority is determined as follows:
Table 10-15. Hardcoded Master Priority
Master
Priority
Description
M7–M4
—
Unused
M3
7
PCI Target Interface
M2
7
Multichannel DMA
M1
—
Unused
M0
7
ColdFire core
10.3.3.11 Arbiter Master Priority Register (XARB_PRI)
The master n priority bits of the arbiter master priority register are used to set the priority of each master
if the corresponding arbiter master priority enable register bit is enabled. This XARB_PRI register, in
conjunction with the arbiter master priority enable (XARB_PRIEN) register, allows master priorities to be
set, ignoring the hardcoded priority. This register may be written at anytime. The change will become
effective 1 clock after the register is written. Valid values are from 0 to 7, with 0 being the highest priority.
31
R
30
0
29
28
Reserved
27
26
0
25
24
Reserved
23
22
0
21
20
Reserved
19
18
0
17
16
Reserved
W
Reset
R
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
M3 Priority
0
M2 Priority
0
Reserved
0
M0 Priority
W
Reset
0
1
Reg
Addr
1
1
0
1
1
1
0
1
1
1
0
1
1
1
MBAR + 0x0268
Figure 10-15. Arbiter Master Priority Register (XARB_PRI)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-17
Table 10-16. XARB_PRI Field Descriptions
Bits
Name
31–15
—
14–12
M3P
11
—
10–8
M2P
7–3
—
2–0
M0P
Description
Reserved, should be cleared.
Master 3 Priority
Reserved, should be cleared.
Master 2 Priority
Reserved, should be cleared.
Master 0 Priority
MCF548x Reference Manual, Rev. 3
10-18
Freescale Semiconductor
Chapter 11
General Purpose Timers (GPT)
11.1
Introduction
This chapter describes the operation of the MCF548x general purpose timers.
11.1.1
Overview
The MCF548x has four general-purpose timers (GPT[0:3]) that are configurable for the following
functions:
• Input capture
• Output capture
• Pulse width modulation (PWM) output
• Simple GPIO
• Internal CPU timer
• Watchdog timer (on GPT0 only)
Timer modules run off the internal peripheral bus clock. Each timer is associated to a single I/O signal.
Each timer has a 16-bit prescaler and 16-bit counter, thus achieving a 32-bit range (but only 16-bit
resolution).
11.1.2
Modes of Operation
The following gives a brief description of the available GPT modes:
1. Input Capture—When enabled in this mode, the counters run until the specified capture event
occurs (rise, fall, or pulse) on TIN[3:0]. At the capture event, the counter value is latched in the
status register. When this occurs, a CPU interrupt is generated.
2. Output Capture—When enabled in this mode, the counters run until they reach the programmed
terminal count value. At this point, the specified output event is generated (toggle, pulse high, or
pulse low) on TOUT[3:0]. When this occurs, a CPU interrupt is generated.
3. PWM (pulse width modulation)—In this mode the user can program period and width values to
create an adjustable, repeating output waveform on TOUT[3:0]. A CPU interrupt can be
generated at the beginning of each PWM period, at which time a new width value can be loaded.
The new width value, which represents “ON time,” is automatically applied at the beginning of
the next period. This mode is suitable for PWM audio encoding.
4. Simple GPIO—In this mode TOUT[3:0] and TIN[3:0] operate as a GPIO. Either TOUT[3:0] or
TIN[3:0] are specified, according to the programmable GPIO field. GPIO mode is mutually
exclusive of modes 1 through 3 (listed above). In GPIO mode, modes 5 through 6 (listed below)
remain available.
5. CPU Timer—The I/O signal is not used in this mode. Once enabled, the counters run until they
reach a programmed terminal count. When this occurs, an interrupt can be generated to the CPU.
This timer mode can be used simultaneously with the simple GPIO mode.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
11-1
6. Watchdog Timer—This is a special CPU timer mode, available only on GPT0. The user must
enable the watchdog timer mode, which is not active upon reset. The terminal count value is
programmable. If the counter is allowed to expire, a full reset occurs. To prevent the watchdog
timer from expiring, software must periodically write 0xA5 to the GMS0[OCPW] field. This
causes the counter to reset.
11.2
External Signals
The GPT signals are the following:
• TIN[3:0]—External timer input
• TOUT[3:0]—External timer output
11.3
Memory Map/Register Definition
Each GPT uses four 32-bit registers. These registers are located at MBAR + the GPT offset 0x800.
Table 11-1 summarizes the GPT control registers.
Table 11-1. General Purpose Timer Memory Map
Address
(MBAR +)
Name
0x800
GPT Enable and Mode Select Register 0
GMS0
R/W
0x804
GPT Counter Input Register 0
GCIR0
R/W
0x808
GPT PWM Configuration Register 0
GPWM0
R/W
0x80C
GPT Status Register 0
GSR0
R
0x810
GPT Enable and Mode Select Register 1
GMS1
R/W
0x814
GPT Counter Input Register 1
GCIR1
R/W
0x818
GPT PWM Configuration Register 1
GPWM1
R/W
0x81C
GPT Status Register 1
GSR1
R
0x820
GPT Enable and Mode Select Register 2
GMS2
R/W
0x824
GPT Counter Input Register 2
GCIR2
R/W
0x828
GPT PWM Configuration Register 2
GPWM2
R/W
0x82C
GPT Status Register 2
GSR2
R
0x830
GPT Enable and Mode Select Register 3
GMS3
R/W
0x834
GPT Counter Input Register 3
GCIR3
R/W
0x838
GPT PWM Configuration Register 3
GPWM3
R/W
0x83C
GPT Status Register 3
GSR3
R
Byte 0
Byte 1
Byte 2
Byte 3
Access
MCF548x Reference Manual, Rev. 3
11-2
Freescale Semiconductor
Memory Map/Register Definition
11.3.1
GPT Enable and Mode Select Register (GMSn)
31
30
29
R
28
27
26
25
24
OCPW
23
22
0
0
21
20
19
18
0
0
OCT
17
16
ICT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CE
0
SC
OD
IEN
0
0
0
0
0
0
0
0
0
0
0
R WDE
N
W
Reset
0
Reg
Addr
GPIO
0
0
0
0
TMS
0
0
0
MBAR + 0x800 (GMS0), 0x810 (GMS1), 0x820 (GMS2), 0x830 (GSM3)
Figure 11-1. GPT Enable and Mode Select Register (GMSn)
Table 11-2. GMSn Field Descriptions
Bits
Name
Description
31–24
OCPW
Output capture pulse width. Applies to OC pulse types only. This field specifies the number of clocks
(non-prescaled) to create a short output pulse at each output event. This pulse is generated at the
end of the output capture period and overlays the next OC period (rather than adding to the period).
This field is alternately used as the watchdog reset field if watchdog timer mode is enabled.
23–22
—
21–20
OCT
19–18
—
17–16
ICT
Reserved, should be cleared.
Output capture type. Describes action to occur at each output capture event, as follows:
00 Special case, output is immediately forced low without respect to each output capture event.
01 Output pulses highs, initial value is low (OCPW field applies).
10 Output pulses low, initial value is high (OCPW field applies).
11 Output toggles.
GPIO modalities can be used to achieve an initial output state prior to enabling OC mode. It is
important to move directly from GPIO output mode to OC mode and not to pass through the
TMS=000 state.
To prevent the internal timer mode from engaging during the GPIO state, CE bit should be cleared
during the configuration steps.
GPIO initialization is needed when presetting the I/O to 1 in conjunction with a simple toggle OCT
setting.
Reserved, should be cleared.
Input capture type. Describes the input transition type required to trigger an input capture event, as
follows:
00 Any input transition causes an IC event.
01 IC event occurs at input rising edge.
10 IC event occurs at input falling edge.
11 IC event occurs at any input pulse (i.e., at the second input edge).
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
11-3
Table 11-2. GMSn Field Descriptions (Continued)
Bits
Name
Description
15
WDEN
Watchdog enable. Enables watchdog operation. A timer expiration causes an internal MCF548x
reset. Watchdog operation requires the TMS field be set for internal timer mode and the CE bit to be
set.
In this mode the OCPW byte field operates as a watchdog reset field. Writing A5 to the OCPW field
resets the watchdog timer, preventing it from expiring. As long as the timer is properly configured, the
watchdog operation continues.
This bit (and functionality) is implemented only for GPT0.
0 Watchdog not enabled
1 Watchdog enabled
14–13
—
Reserved, should be cleared.
12
CE
Counter enable. Enables or resets the internal counter during internal timer modes only. CE must be
set to enable these modes. If cleared, counter is held in reset.
0 Timer counter held in reset
1 Timer counter enabled
This bit is secondary to the timer mode select bits (TMS). If TMS is1XX, internal timer modes are
enabled. CE can then enable or reset the internal counter without changing the TMS field.
GPIO operation is also available in this mode.
11
—
Reserved, should be cleared.
10
SC
Stop/continuous mode.
0 Stops the operation
1 Continues the operation
The SC bit applies to multiple modes, as follows:
IC mode (input capture mode)
Stop operation—At each IC event, counter is reset.
Continuous operation—counter is not reset at each IC event.
Effect is to create status count values that are cumulative between capture events. If the special pulse
mode capture type is specified, the SC bit is not used, operation fixed as if it were stop.
OC mode (output capture mode)
Stop operation—Counter resets and stops at the first output capture event. Software needs to pass
through TMS=000 state to restart timer.
Continuous operation—counter resets and continues at each OC event. The effect to is create
back-to-back periodic OC events.
PWM mode (pulse width modulation mode)
The SC bit is not used; operation is always continuous.
CPU Timer mode
Stop operation—On counter expiration, timer waits until status bit is cleared by passing through
TMS=000 state before beginning a new cycle.
Continuous operation—On counter expiration, timer resets and immediately begin a new cycle. The
effect is to generate fixed periodic timeouts.
WatchDog Timer and GPIO modes
The SC bit is not used.
9
OD
Open drain.
0 Normal I/O
1 Open Drain emulation—affects all modes that drive the I/O pin (GPIO, OC, and PWM). Any output
“1” is converted to a tri-state at the I/O pin.
MCF548x Reference Manual, Rev. 3
11-4
Freescale Semiconductor
Memory Map/Register Definition
Table 11-2. GMSn Field Descriptions (Continued)
Bits
Name
Description
8
IEN
Interrupt enable. Enables interrupt generation to the CPU for all modes (IC, OC, PWM, and Internal
Timer). IEN is not required for watchdog expiration to create a reset.
0 Interrupt disabled
1 Interrupt enabled
7–6
—
5–4
GPIO
3
—
2–0
TMS
11.3.2
Reserved, should be cleared.
GPIO mode type. Simple GPIO functionality that can be used simultaneously with the internal timer
mode. It is not compatible with IC, OC, or PWM modes, because these modes dictate the usage of
the I/O signals.
0X Timer enabled as simple GPIO input on TINn
10 Timer enabled as simple GPIO output, TOUTn=0
11 Timer enabled as simple GPIO output, TOUTn=1 (tri-state if OD=1)
While in GPIO modes, internal timer mode is also available. To prevent undesired timer expiration,
keep the CE bit cleared.
Reserved, should be cleared.
Timer mode select (and module enable).
000 Timer module not enabled. All timer operation is completely disabled. Control and status
registers are still accessible. This mode should be entered when the timer is to be re-configured,.
001 Timer enabled for input capture.
010 Timer enabled for output capture.
011 Timer enabled for PWM.
1XX Timer enabled for simple GPIO. Internal timer modes available. CE bit controls timer counter.
GPT Counter Input Register (GCIRn)
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
PRE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
CNT
W
Reset
0
0
Reg
Addr
0
0
0
0
0
0
MBAR + 0x804 (GCIR0), 0x814 (GCIR1), 0x824 (GCIR2), 0x834 (GCIR3)
Figure 11-2. GPT Counter Input Register (GCIRn)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
11-5
Table 11-3. GCIRn Field Descriptions
Bits
Name
Description
31–16
PRE
Prescaler. Prescale amount applied to internal counter (in clocks).
Note that in addition to other enable bits and field settings, the PRE field must be written as
non-zero to enable counter operation for all modes except the simple GPIO mode. A prescale of
0x0001 means one clock per count increment.
15–0
CNT
Count value. Sets number of prescaled counts applied to reference events, as follows:
IC—Field has no effect, internal counter starts at 0.
OC—Number of prescaled counts counted before creating output event.
PWM—Number of prescaled counts defining the PWM output period.
Internal Timer—Number of prescaled counts counted before timer (or watchdog) expires.
Reading this register only returns the programmed value, intermediate values of the internal
counter are not available to software.
11.3.3
GPT PWM Configuration Register (GPWMn)
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
WIDTH
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PWM
OP
0
0
0
0
0
0
0
LOAD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0x808 (GPWM0), 0x818 (GPWM1), 0x828 (GPWM2), 0x838 (GPWM3)
Figure 11-3. GPT PWM Configuration Register (GPWMn)
Table 11-4. GPWMn Field Descriptions
Bits
Name
31–16
WIDTH
15–9
—
8
PWMOP
Description
PWM width. Used in PWM mode only. Defines ON time for output in prescaled counts. Similar to
count value, which defines the period. ON time overlays the period time.
If WIDTH = 0, output is always OFF.
If WIDTH exceeds count value, output is always ON.
ON and OFF polarity is set by the PWMOP bit.
Reserved. Should be cleared.
PWM output polarity. Defines PWM output polarity for OFF time. Opposite state is ON time. PWM
cycles begin with ON time.
0 PWM output is low during OFF time
1 PWM output is high during OFF time
MCF548x Reference Manual, Rev. 3
11-6
Freescale Semiconductor
Memory Map/Register Definition
Table 11-4. GPWMn Field Descriptions (Continued)
Bits
Name
7–1
—
0
LOAD
11.3.4
Description
Reserved. Should be cleared.
Bit forces immediate period update. Bit auto clears itself. A new period begins immediately with the
current count and width settings.
If LOAD = 0, new count or width settings are not updated until end of current period.
Prescale setting is not part of this process. Changing prescale value while PWM is active causes
unpredictable results for the period in which it was changed. The same is true for PWMOP bit.
GPT Status Register (GSRn)
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
CAPTURE
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
PIN
0
0
0
0
0
0
0
0
0
0
0
0
0
OVF
TEXP PWMP COMP CAPT
W
Reset
0
0
0
Reg
Addr
0
0
0
0
0
MBAR + 0x80C (GSR0), 0x81C (GSR1), 0x82C (GSR2), 0x83C (GSR3)
Figure 11-4. GPT Status Register (GSRn)
Table 11-5. GSRn Field Descriptions
Bits
31–16
Name
Description
CAPTURE Read of internal counter, latch at reference event. This is pertinent only in IC mode, in which case
it represents the count value at the time the input event occurred. Capture status does not shadow
the internal counter while an event is pending, it is updated only at the time the input event occurs.
If ICT is set to 11, which is Pulse Capture Mode, the Capture value records the width of the pulse.
Also, the SC bit is irrelevant in Pulse Capture Mode, operation is as if SC were 0.
15
—
14–12
OVF
11–9
—
8
PIN
7–4
—
3
TEXP
Reserved. Should be cleared.
Overflow counter. Represents how many times internal counter has rolled over. This is pertinent
only during IC mode and would represent an extremely long period of time between input events.
However, if SC = 1 (indicating cumulative reporting of input events), this field could come into play.
This field is cleared by any “sticky bit” status write in the TEXP, PWMP, COMP, or CAPT bit fields.
Reserved
GPIO input value. This bit reflects the registered state of the TINn pin (all modes). The clock
registers the state of the input. Valid, even if timer is not enabled.
Reserved. Should be cleared.
Timer expired in internal timer mode. Cleared by writing 1 to this bit position. Also cleared if TMS
is 000 (i.e., timer not enabled).
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
11-7
Table 11-5. GSRn Field Descriptions (Continued)
Bits
Name
2
PWMP
PWM end of period occurred. Cleared by writing 1 to this bit position. Also cleared if TMS is 000
(i.e., timer not enabled).
1
COMP
OC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if TMS is 000
(i.e., timer not enabled).
0
CAPT
IC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if TMS is 000
(i.e., timer not enabled).
11.4
11.4.1
Description
Functional Description
Timer Configuration Method
Use the following method to configure each timer:
1. Determine the mode select field (GMSn[TMS]) value for the desired operation.
2. Program any other registers associated with this mode.
3. Program interrupt enable as desired.
4. Enable the timer by writing the mode select value into the TMS field.
11.4.2
Programming Notes
Programmers should observe the following notes:
1. Intermediate values of the timer internal counters are not readable by software.
2. In PWM mode, an interrupt occurs at the beginning of a pulse. An interrupt service routine
prepares the new pulse width of the next pulse while the current pulse is running.
3. The stop/continuous mode bit (GMSn[SC] ) operates differently for different modes. In general,
this bit controls whether the timer halts at the end of a current mode, or resets and continues with
a repetition of the mode. See Table 11-2 for precise operation.
4. The GMSn[TMS] field operates somewhat as a global enable. If it is zero, then all timer modes
are disabled and internal counters are reset. See Table 11-2 for more detail.
5. There is a counter enable bit (GMSn[CE]) that operates somewhat independently of the TMS
field. This bit controls the counter for CPU timer or watchdog timer modes only. See Table 11-2
to understand the operation of these bits across the various modes.
MCF548x Reference Manual, Rev. 3
11-8
Freescale Semiconductor
Chapter 12
Slice Timers (SLT)
12.1
Introduction
This chapter explains the operation of the MCF548x slice timers.
12.1.1
Overview
Two slice timers are included to provide shorter term periodic interrupts—SLT0 and SLT1. Each timer
consists of a 32-bit counter with no prescale. The counters count down from a prescribed value and
expire/interrupt when they reach zero. They can be configured to automatically preset to the prescribed
value and resume counting or wait until the status/interrupt is serviced before beginning a new cycle.
The current count value can be read without disturbing the count operation. Each SLT has a status bit to
indicate the timer has expired. If enabled, a CPU interrupt is generated at count expiration. Each timer has
a separate interrupt. Clearing the status and/or interrupt is accomplished by writing 1 to the status bit, or
disabling the timer entirely with the timer enable (SCR[TEN]) bit.
Software should write a terminal count value of greater than 255.
12.2
Memory Map/Register Definition
There are two slice timers. Each one uses four 32-bit registers. These registers are located at an offset from
MBAR of 0x900.
Table 12-1 summarizes the SLT control registers.
Table 12-1. Slice Timer Memory Map
Address
(MBAR +)
Name
0x900
SLT Terminal Count Register 0
STCNT0
R/W
0x904
SLT Control Register 0
SCR0
R/W
0x908
SLT Count Value Register 0
SCNT0
R
0x90C
SLT Status Register 0
SSR0
R
0x910
SLT Terminal Count Register 1
STCNT1
R/W
0x914
SLT Control Register 1
SCR1
R/W
0x918
SLT Count Value Register 1
SCNT1
R
0x91C
SLT Status Register 1
SSR1
R
Byte 0
Byte 1
Byte 2
Byte 3
Access
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
12-1
12.2.1
SLT Terminal Count Register (STCNTn)
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
TC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
TC
W
Reset
0
0
0
0
0
Reg
Addr
0
0
0
MBAR + 0x900 (STCNT0), + 0x910 (STCNT1)
Figure 12-1. SLT Terminal Count Register (STCNTn)
Table 12-2. STCNTn Field Descriptions
Bits
Name
Description
31–0
TC
Terminal count. GPIO output bit set. The user programs this register to set the terminal count value
to be used by the SLT. This register can be updated even if the timer is running; the new value takes
effect immediately. The new value also clears any existing interrupt.
Note: Software should not write a value less than 255 to the timer.
12.2.2
R
SLT Control Register (SCRn)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
RUN
IEN
TEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Reg
Addr
MBAR + 0x904 (SCR0), + 0x914 (SCR1)
Figure 12-2. SLT Control Register (SCRn)
MCF548x Reference Manual, Rev. 3
12-2
Freescale Semiconductor
Memory Map/Register Definition
Table 12-3. SCRn Field Descriptions
Bits
Name
31–27
—
26
RUN
Run or wait mode
0 Timer counter expires, but then waits until the timer is cleared (either by writing 1 to the status
bit or by disabling and re-enabling the timer), before resuming operation.
1 Timer is enabled, and runs continuously. When the timer counter expires the terminal count
value immediately is reloaded and resumes counting down.
25
IEN
Interrupt enable. A CPU interrupt is generated only if this bit is set.
0 Interrupt is not generated
1 Interrupt is generated
This bit does not affect operation of the timer counter or status bit registers.
24
TEN
Timer enable
0 Timer is reset, then remains idle
1 Normal timer operation
23–0
—
12.2.3
Description
Reserved, should be cleared.
Reserved, should be cleared.
SLT Timer Count Register (SCNTn)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CNT
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
CNT
R
W
Reset
0
0
0
Reg
Addr
0
0
0
0
0
MBAR + 0x908 (SCNT0), + 0x918 (SCNT1)
Figure 12-3. SLT Count Register (SCNTn)
Table 12-4. SCNTn Field Descriptions
Bits
Name
Description
31–0
CNT
Timer count. GPIO output bit set. Provides the current state of the timer counter. This
register does not change while a read is in progress, but the actual timer counter continues
unaffected.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
12-3
12.2.4
R
SLT Status Register (SSRn)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
BE
ST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Reg
Addr
MBAR + 0x90C (SSR0), + 0x91C (SSR1)
Figure 12-4. SLT Status Register (SSRn)
Table 12-5. SSRn Field Descriptions
Bits
Name
Description
31–26
—
Reserved, should be cleared
25
BE
Bus Error Status. Provides information on attempted write to read-only register. The bit is
cleared by writing 1 to its bit position.
24
ST
SLT timeout. This status bit is set whenever the timer has expired. The bit is cleared by
writing 1 to its bit position. If interrupts are enabled, clearing this status bit also clears the
interrupt.
23–0
—
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
12-4
Freescale Semiconductor
Chapter 13
Interrupt Controller
13.1
Introduction
This section details the functionality for the MCF548x interrupt controller. The general features of the
interrupt controller include:
• 63 interrupt sources, organized as:
— 56 fully-programmable interrupt sources
— 7 fixed-level interrupt sources
• Each of the 63 sources has a unique interrupt control register (ICRn) to define the
software-assigned levels and priorities within the level
• Unique vector number for each interrupt source
• Ability to mask any individual interrupt source, plus global mask-all capability
• Support for both hardware and software interrupt acknowledge cycles
• “Wake-up” signal from stop mode
The 56 fully-programmable and seven fixed-level interrupt sources for each of the two interrupt controllers
on the MCF548x handle the complete set of interrupt sources from all of the modules on the device. This
section describes how the interrupt sources are mapped to the interrupt controller logic, and how interrupts
are serviced.
13.1.1
68K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the MCF548x interrupt controller, a brief review of the interrupt
architecture of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit
encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt
requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The
processor samples for active interrupt requests once per instruction by comparing the encoded priority
level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If
the priority level is greater than the SR[I] field at the sample point, the processor suspends normal
instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as
non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and
may be masked depending on the value of the SR[I] field. For correct operation, the ColdFire requires that,
once asserted, the interrupt source remain asserted until explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then
fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt
acknowledge (IACK) cycle, with the ColdFire implementation using a special encoding of the transfer
type and transfer modifier attributes to distinguish this data fetch from a “normal” memory access. The
fetched data provides an index into the exception vector table that contains 256 addresses, each pointing
to the beginning of a specific exception service routine. In particular, vectors 64–255 of the exception
vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for
the processor to handle reset, error conditions (access, address), arithmetic faults, system calls, etc.
Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in
memory. For ColdFire, all exception stack frames are 2 longwords in length and contain 32 bits of vector
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-1
and status register data, along with the 32-bit program counter value of the instruction that was interrupted
(see Section 3.8.1, “Exception Stack Frame Definition,” for more information on the stack frame format).
After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the
exception vector table using the vector number as the offset, and then jumps to that address to begin
execution of the service routine.
After the status register is stored in the exception stack frame, the SR[I] mask field is set to the level of the
interrupt being acknowledged, effectively masking that level and all lower values while in the service
routine. For many peripheral devices, the processing of the IACK cycle directly negates the interrupt
request, while other devices require that request to be explicitly negated during the processing of the
service routine.
For the MCF548x, the processing of the interrupt acknowledge cycle is fundamentally different than
previous 68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by the interrupt
controller, so the requesting peripheral device is not accessed during the IACK. As a result, the interrupt
request must be explicitly cleared in the peripheral during the interrupt service routine. For more
information, see Section 13.1.1.1.3, “Interrupt Vector Determination.”
Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the service routine
is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR,
interrupts can be safely disabled, if required.
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual at
http://www.freescale.com/coldfire
13.1.1.1
Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt
sources are organized as 7 levels, with each level supporting up to nine prioritized requests. Consider the
priority structure within a single interrupt level (from highest to lowest priority) as shown in Table 13-1.
Table 13-1. Interrupt Priority Within a Level
ICR[2:0]
Priority
Interrupt
Sources
111
7 (Highest)
8-63
110
6
8-63
101
5
8-63
100
4
8-63
—
Fixed Midpoint Priority
1-7
011
3
8-63
010
2
8-63
001
1
8-63
000
0 (Lowest)
8-63
The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source
1–7 (the external interrupts) are fixed at the corresponding level’s midpoint priority. Thus, a maximum of
MCF548x Reference Manual, Rev. 3
13-2
Freescale Semiconductor
Introduction
8 fully-programmable interrupt sources are mapped into a single interrupt level. The “fixed” interrupt
source is hardwired to the given level and represents the mid-point of the priority within the level. For the
fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in
the 8-bit interrupt control register (ICRn).
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector determination during IACK
13.1.1.1.1
Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register to
determine if there are active requests. This is the recognition phase.
13.1.1.1.2
Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit
decoded priority level (IRQ[7:1]) is driven out of the interrupt controller.
13.1.1.1.3
Interrupt Vector Determination
Once the core has sampled for pending interrupts and begun interrupt exception processing, it generates
an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by
the processor and routed to the interrupt controller. Next, the interrupt controller extracts the level being
acknowledged from address bits[4:2], determines the highest priority interrupt request active for that level,
and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is
formed using the following algorithm:
vector_number = 64 + interrupt source number
Recall vector numbers 0—63 are reserved for the ColdFire processor and its internal exceptions. Thus, the
mapping of bit positions to vector numbers that apply are the following:
if interrupt source 1 is active and acknowledged,
then vector_number =
65
if interrupt source 2 is active and acknowledged,
then vector_number =
66
if interrupt source 8 is active and acknowledged,
then vector_number =
72
if interrupt source 9 is active and acknowledged,
then vector_number =
73
...
...
if interrupt source 63 is active and acknowledged,
then vector_number = 127
The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector
number.
If there is no active interrupt source for the given level, a special “spurious interrupt” vector
(vector_number = 24) is returned, and it is the responsibility of the service routine to handle this error
situation.
Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since
the interrupt controller completely services the acknowledge. This means the interrupt source must be
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-3
explicitly cleared in the interrupt service routine. This design provides unique vector capability for all
interrupt requests, regardless of the “complexity” of the peripheral device.
Vector number 64 is unused.
13.2
Memory Map/Register Descriptions
The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In
the following discussion, there are a number of program-visible registers greater than 32 bits in size. For
these control fields, the physical register is partitioned into two 32-bit values: a register “High” (the upper
longword) and a register “Low” (the lower longword). The nomenclature <reg_name>H and
<reg_name>L is used to reference these values.
The registers and their locations are defined in Table 13-2.
Table 13-2. Interrupt Controller Memory Map
Address
Offset
Name
Byte0
Byte1
Byte2
Byte3
Access
0x700
Interrupt Pending Register High
[63:32]
IPRH
R
0x704
Interrupt Pending Register Low
[31:0]
IPRL
R
0x708
Interrupt Mask Register High
[63:32]
IMRH
R/W
0x70c
Interrupt Mask Register Low
[31:0]
IMRL
R/W
0x710
Interrupt Force Register High
[63:32]
INTFRCH
R/W
0x714
Interrupt Force Register Low
[31:0]
INTFRCL
R
0x718
Interrupt Request Level Register
and Interrupt Acknowledge Level
and Priority Register
0x71C–
0x73C
—
IRLR[7:1]
IACKLPR
Reserved
Reserved
R
—
MCF548x Reference Manual, Rev. 3
13-4
Freescale Semiconductor
Memory Map/Register Descriptions
Table 13-2. Interrupt Controller Memory Map (Continued)
Address
Offset
Name
Byte0
Byte1
Byte2
Byte3
Access
0x740
Interrupt Control Registers
Reserved
ICR01
ICR02
ICR03
R
0x744
ICR04
ICR05
ICR06
ICR07
R
0x748
ICR08
ICR09
ICR10
ICR11
R/W
0x74c
ICR12
ICR13
ICR14
ICR15
R/W
0x750
ICR16
ICR17
ICR18
ICR19
R/W
0x754
ICR20
ICR21
ICR22
ICR23
R/W
0x758
ICR24
ICR25
ICR26
ICR27
R/W
0x75C
ICR28
ICR29
ICR30
ICR31
R/W
0x760
ICR32
ICR33
ICR34
ICR35
R/W
0x764
ICR36
ICR37
ICR38
ICR39
R/W
0x768
ICR40
ICR41
ICR42
ICR43
R/W
0x76C
ICR44
ICR45
ICR46
ICR47
R/W
0x770
ICR48
ICR49
ICR50
ICR51
R/W
0x774
ICR52
ICR53
ICR54
ICR55
R/W
0x778
ICR56
ICR57
ICR58
ICR59
R/W
0x77C
ICR60
ICR61
ICR62
ICR63
R/W
0x780-0x7D
C
—
0x7E0
Software IACK Register
SWIACK
Reserved
R
0x7E4
Level N IACK Registers
L1IACK
Reserved
R
0x7E8
L2IACK
Reserved
R
0x7EC
L3IACK
Reserved
R
0x7F0
L4IACK
Reserved
R
0x7F4
L5IACK
Reserved
R
0x7F8
L6IACK
Reserved
R
0x7FC
L7IACK
Reserved
R
13.2.1
13.2.1.1
Reserved
—
Register Descriptions
Interrupt Pending Registers (IPRH, IPRL)
The IPRH and IPRL registers, Figure 13-1 and Figure 13-2, are each 32 bits in size and provide a bit map
for each interrupt request to indicate if there is an active request for the given source (1 = active request,
0 = no request). The state of the interrupt mask register does not affect the IPR. The IPR is cleared by reset.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-5
The IPR is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented
and reads as a zero.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INT[63:48]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
INT[47:32]
W
Reset
0
0
0
0
0
0
0
Reg
Addr
0
0
MBAR + 0x700
Figure 13-1. Interrupt Pending Register High (IPRH)
Table 13-3. IPRH Field Descriptions
Bits
Name
31–0
INT[63:32]
31
30
Description
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRH bit
determines whether an interrupt condition can generate an interrupt. At every system clock, the
IPRH samples the signal generated by the interrupting source. The corresponding IPRH bit
reflects the state of the interrupt signal even if the corresponding IMRH bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INT[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INT[15:1]
0
W
Reset
Reg
Addr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MBAR + 0x704
Figure 13-2. Interrupt Pending Register Low (IPRL)
MCF548x Reference Manual, Rev. 3
13-6
Freescale Semiconductor
Memory Map/Register Descriptions
Table 13-4. IPRL Field Descriptions
Bits
Name
Description
31–1
INT[31:1]
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRL bit
determines whether an interrupt condition can generate an interrupt. At every system clock, the
IPRL samples the signal generated by the interrupting source. The corresponding IPRL bit reflects
the state of the interrupt signal even if the corresponding IMRL bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
0
—
13.2.1.2
Reserved, should be cleared.
Interrupt Mask Register (IMRH, IMRL)
The IMRH and IMRL registers are each 32 bits in size and provide a bit map for each interrupt to allow
the request to be disabled (1 = disable the request, 0 = enable the request). The IMR is set to all ones by
reset, disabling all interrupt requests. The IMR can be read and written. A write that sets bit 0 of the IMR
forces the other 63 bits to be set, disabling all interrupt sources and providing a global mask-all capability.
NOTE
If an interrupt source is masked in the interrupt controller mask register
(IMR) or a module’s interrupt mask register while the interrupt mask in the
status register (SR[I]) is set to a value lower than the interrupt’s level, a
spurious interrupt may occur. This situation occurs because by the time the
status register acknowledges the interrupt, it has been masked and the CPU
cannot determine the interrupt source. To avoid this situation for interrupt
sources with levels 1–6, first write a higher level interrupt mask to the status
register before setting the mask in the IMR or the module’s interrupt mask
register. After the mask is set, return the interrupt mask in the status register
to its previous value. Since level 7 interrupts cannot be disabled in the status
register prior to masking, use of the IMR or module interrupt mask registers
to disable level 7 interrupts is not recommended.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INT_MASK[63:48]
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
INT_MASK[47:32]
W
Reset
1
1
Reg
Addr
1
1
1
1
1
1
1
MBAR + 0x708
Figure 13-3. Interrupt Mask Register High (IMRH)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-7
Table 13-5. IMRH Field Descriptions
Bits
31–0
31
Name
Description
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRH bit
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRH bit reflects the state of the interrupt signal even if the corresponding IMRH bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INT_MASK[31:16]
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INT_MASK[15:1]
MASK
ALL
W
Reset
1
1
1
Reg
Addr
1
1
1
1
1
1
1
1
1
1
1
1
1
MBAR + 0x70C
Figure 13-4. Interrupt Mask Register Low (IMRL)
Table 13-6. IMRL Field Descriptions
Bits
31–1
0
13.2.1.3
Name
Description
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRL bit
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRL bit reflects the state of the interrupt signal even if the corresponding IMRL bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
MASKALL
Mask all interrupts. Setting this bit will force the other 63 bits of the IMRH and IMRL to ones,
disabling all interrupt sources, and providing a global mask-all capability.
Interrupt Force Registers (INTFRCH, INTFRCL)
The INTFRCH and INTFRCL registers are each 32 bits in size and provide a mechanism to allow software
generation of interrupts for each possible source for functional or debug purposes. The system design may
reserve one or more sources to allow software to self-schedule interrupts by forcing one or more of these
bits in the appropriate INTFRC register (1 = force request, 0 = negate request). The assertion of an interrupt
request via the INTFRC register is not affected by the interrupt mask register. The INTFRC register is
cleared by reset.
MCF548x Reference Manual, Rev. 3
13-8
Freescale Semiconductor
Memory Map/Register Descriptions
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INTFRC[63:48]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
INTFRC[47:32]
W
Reset
0
0
0
0
0
0
0
Reg
Addr
0
0
MBAR + 0x710
Figure 13-5. Interrupt Force Register High (INTFRCH)
Table 13-7. INTFRCH Field Descriptions
Bits
Name
Description
31–0
INTFRC
Interrupt force. Allows software generation of interrupts for each possible source for functional or
debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INTFRC[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INTFRC[16:1]
—
W
Reset
0
0
0
0
0
0
0
Reg
Addr
0
0
0
0
0
0
0
0
0
MBAR + 0x714
Figure 13-6. Interrupt Force Register Low (INTFRCL)
.
Table 13-8. INTFRCL Field Descriptions
Bits
Name
Description
31–1
INTFRC
Interrupt force. Allows software generation of interrupts for each possible source for functional or
debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
0
—
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-9
13.2.1.4
Interrupt Request Level Register (IRLR)
This 7-bit register is updated each machine cycle and represents the current interrupt requests for each
interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc.
7
6
5
R
4
3
2
1
0
IRQ
0
W
Reset
0
0
0
Reg
Addr
0
0
0
0
0
MBAR + 0x718
Figure 13-7. Interrupt Request Level Register (IRLR)
Table 13-9. IRQn Field Descriptions
Bits
Name
7–1
IRQ
0
—
13.2.1.5
Description
Interrupt requests. Represents the prioritized active interrupts for each level.
0 There are no active interrupts at this level
1 There is an active interrupt at this level
Reserved
Interrupt Acknowledge Level and Priority Register (IACKLPR)
Each time an IACK is performed, the interrupt controller responds with the vector number of the highest
priority source within the level being acknowledged. In addition to providing the vector number directly
for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level
and priority being acknowledged. This register provides the association between the acknowledged
“physical” interrupt request number and the programmed interrupt level/priority. The contents of this
read-only register are described in Figure 13-8 and Table 13-10.
7
R
6
5
—
4
3
2
LEVEL
1
0
0
0
PRI
W
Reset
0
0
0
Reg
Addr
0
0
0
MBAR + 0x719
Figure 13-8. IACK Level and Priority Register (IACKLPR)
Table 13-10. IACKLPR Field Descriptions
Bits
Name
7
—
Description
Reserved
MCF548x Reference Manual, Rev. 3
13-10
Freescale Semiconductor
Memory Map/Register Descriptions
Table 13-10. IACKLPR Field Descriptions (Continued)
Bits
Name
6–4
LEVEL
3–0
PRI
13.2.1.6
Description
Interrupt level. Represents the interrupt level currently being acknowledged.
Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently
being acknowledged.
0 Priority 0
1 Priority 1
2 Priority 2
3 Priority 3
4 Priority 4
5 Priority 5
6 Priority 6
7 Priority 7
8 Mid-Point Priority associated with the fixed level interrupts only
Interrupt Control Registers 1–63 (ICRn)
Each ICRn specifies the interrupt level (1–7) and the priority within the level (0–7). All ICRn registers can
be read, but only ICR8 to ICR63 can be written. It is software’s responsibility to program the ICRn
registers with unique and non-overlapping level and priority definitions. Failure to program the ICRn
registers in this matter can result in undefined behavior. If a specific interrupt request is completely unused,
the ICRn value can remain in its reset (and disabled) state.
R
7
6
0
0
0
0
5
4
3
2
IL
1
0
IP
W
Reset
Reg
Addr
0
0
0
0
0
0
See Table 13-2 for register offsets
Figure 13-9. Interrupt Control Registers 1–63 (ICRn)
Table 13-11. ICRn Field Descriptions
Bits
Name
Description
7–6
—
Reserved, should be cleared.
5–3
IL
Interrupt level. Indicates the interrupt level assigned to each interrupt input.
2–0
IP
Interrupt priority. Indicates the interrupt priority for internal modules within the
interrupt-level assignment. 000b represents the lowest priority and 111b represents the
highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the level,
and the IP field will always read as 000b.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-11
13.2.1.6.1
Interrupt Sources
Table 13-12 lists the interrupt sources for each interrupt request line
Table 13-12. Interrupt Source Assignments
Sourc
e
Module
Flag
1
EPORT
EPF1
Edge port flag 1
Write ‘1’ to EPFR[EPF1]
2
EPF2
Edge port flag 2
Write ‘1’ to EPFR[EPF2]
3
EPF3
Edge port flag 3
Write ‘1’ to EPFR[EPF3]
4
EPF4
Edge port flag 4
Write ‘1’ to EPFR[EPF4]
5
EPF5
Edge port flag 5
Write ‘1’ to EPFR[EPF5]
6
EPF6
Edge port flag 6
Write ‘1’ to EPFR[EPF6]
7
EPF7
Edge port flag 7
Write ‘1’ to EPFR[EPF7]
Source Description
8–14
15
Flag Clearing Mechanism
Not used
USB 2.0
EP0ISR
Endpoint 0 interrupt
Write ‘1’ to appropriate bit in EP0ISR
16
EP1ISR
Endpoint 1 interrupt
Write ‘1’ to appropriate bit in EP1ISR
17
EP2ISR
Endpoint 2 interrupt
Write ‘1’ to appropriate bit in EP2ISR
18
EP3ISR
Endpoint 3 interrupt
Write ‘1’ to appropriate bit in EP3ISR
19
EP4ISR
Endpoint 4 interrupt
Write ‘1’ to appropriate bit in EP4ISR
20
EP5ISR
Endpoint 5 interrupt
Write ‘1’ to appropriate bit in EP5ISR
21
EP6ISR
Endpoint 6 interrupt
Write ‘1’ to appropriate bit in EP6ISR
22
USBISR
USB 2.0 general interrupt
Write ‘1’ to appropriate bit in USBISR
23
USBAISR USB 2.0 core interrupt
24
OR of all USB interrupts
Clear appropriate USB interrupt(s)
RFOF |
TFUF
DSPI overflow or underflow
Write ‘1’ to DSR[RFDF] and/or DSR[TFUF]
26
RFOF
Receive FIFO overflow interrupt
Write ‘1’ to DSR[RFOF]
27
RFDF
Receive FIFO drain interrupt
Write ‘1’ to DSR[RFDF] or DMA acknowledge
28
TFUF
Transmit FIFO underflow interrupt Write ‘1’ to DSR[TFUF]
29
TCF
Transfer complete interrupt
Write ‘1’ to DSR[TCF]
30
TFFF
Transfer FIFO fill interrupt
Write ‘1’ to DSR[TFFF] or DMA acknowledge
31
EOQF
End of queue interrupt
Write ‘1’ to DSR[EOQF]
25
—
Write ‘0’ to appropriate bit in USBAISR
DSPI
32
PSC3
—
PSC3 interrupt
Cleared when service complete
33
PSC2
—
PSC2 interrupt
Cleared when service complete
34
PSC1
—
PSC1 interrupt
Cleared when service complete
35
PSC0
—
PSC0 interrupt
Cleared when service complete
MCF548x Reference Manual, Rev. 3
13-12
Freescale Semiconductor
Memory Map/Register Descriptions
Table 13-12. Interrupt Source Assignments (Continued)
Sourc
e
Module
Flag
36
CommTim
TC
Combined interrupts from comm
timers
Write ‘1’ to CTCRn[I]
37
SEC
—
SEC interrupt
Service interrupt and write ‘1’ to SICR
Source Description
Flag Clearing Mechanism
38
FEC1
—
FEC1 interrupt
Write appropriate interrupt condition bit = 1
39
FEC0
—
FEC0 interrupt
Write appropriate interrupt condition bit = 1
40
I2C
—
I2C interrupt
Write IIF = 0
—
PCI arbiter interrupt
Write ‘1’ to PASR[EXTMBK] or PASR[ITLMBK]
41
PCIARB
42
CBPCI
—
Comm bus PCI interrupt
Clear FIFO alarm condition
43
XLBPCI
—
XLB PCI interrupt
Write ‘1’ to appropriate PCIISR bit(s)
44–46
47
Not used
—
XLBARB to CPU interrupt
Write ‘1’ to appropriate ARB_SR bit(s)
—
Multichannel DMA interrupt
Write ‘1’ to DIPR[TASKn]
ERROR
FlexCAN error interrupt
Read error bits in ESR or write ERR_INT = 0
50
BUSOFF
FlexCAN bus off interrupt
Write BOFF_INT = 0
51
MBOR
Message buffer ORed interrupt
Write BUFnI = 1 after reading BUFnI = 1
48
49
XLBARB
DMA
CAN0
52
53
Not used
SLT1
Slice timer 1 interrupt
Write ST = 1
SLT0
Slice timer 0 interrupt
Write ST = 1
ERROR
FlexCAN error interrupt
Read error bits in ESR or write ERR_INT = 0
56
BUSOFF
FlexCAN bus off interrupt
Write BOFF_INT = 0
57
MBOR
Message buffer ORed interrupt
Write BUFnI = 1 after reading BUFnI = 1
54
55
Slice
Timer
CAN1
58
59
Not used
GPTs
GPT3
GPT3 interrupt
Write ‘1’ to appropriate GSR bit
60
GPT2
GPT2 interrupt
Write ‘1’ to appropriate GSR bit
61
GPT1
GPT1 interrupt
Write ‘1’ to appropriate GSR bit
62
GPT0
GPT0 interrupt
Write ‘1’ to appropriate GSR bit
63
13.2.1.7
Not used
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt
controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK arrives
in the interrupt controller, the controller examines all the currently-active level-n interrupt requests,
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-13
determines the highest priority within the level, and then responds with the unique vector number
corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized
IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level
and priority number for the level into the IACKLPR, where it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK is a useful
concept that allows an interrupt service routine to determine if there are other pending interrupts, so that
the overhead associated with interrupt exception processing (including machine state save/restore
functions) can be minimized. In general, the software IACK is performed near the end of an interrupt
service routine, and if there are additional active interrupt sources, the current interrupt service routine
(ISR) passes control to the appropriate service routine, but without taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number associated with
the highest level, highest priority unmasked interrupt source for that interrupt controller. The IACKLPR
is also loaded as the software IACK is performed. If there are no active sources, the interrupt controller
returns an all-zero vector as the operand. For this situation, the IACKLPR is also cleared.
In addition to the software IACK registers within each interrupt controller, there are global software IACK
registers. A read from the global SWIACK will return the vector number for the highest level and priority
unmasked interrupt source from all interrupt controllers. A read from one of the LnIACK registers will
return the vector for the highest priority unmasked interrupt within a level for all interrupt controllers.
7
6
5
4
R
3
2
1
0
0
0
0
0
VECTOR
W
Reset
0
0
Reg
Addr
0
0
See Table 13-2 for register offsets
Figure 13-10. Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
Table 13-13. SWIACK and L1IACK–L7IACK Field Descriptions
Bits
Name
Description
7–0
VECTOR
Vector number. A read from the SWIACK register returns the vector number associated
with the highest level, highest priority unmasked interrupt source. A read from one of the
LnACK registers returns the highest priority unmasked interrupt source within the level.
MCF548x Reference Manual, Rev. 3
13-14
Freescale Semiconductor
Chapter 14
Edge Port Module (EPORT)
14.1
Introduction
The edge port module (EPORT) has seven external interrupt pins, IRQ[7:1]. Each pin can be configured
individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or
both), or a general-purpose input/output (I/O) pin. See Figure 14-1.
Stop
Mode
EPPAR[2n, 2n + 1]
Edge Detect
Logic
EPFRn
D0
Internal Bus
Q
D0
D1
Q
D1
To Interrupt
Controller
EPPDRn
Synchronizer
Rising Edge
of System Clock
EPIERn
EPDRn
IRQn PIN
EPDDRn
Figure 14-1. EPORT Block Diagram
14.2
Interrupt/General-Purpose I/O Pin Descriptions
All interrupt pins default to general-purpose input pins at reset. The pin value is synchronized to the rising
edge of the internal clock when read from the EPORT pin data register (EPPDR). The values used in the
edge/level detect logic are also synchronized to the rising edge of the internal clock. These pins use
Schmitt-triggered input buffers which have built-in hysteresis that decrease the probability of generating
false edge-triggered interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding
bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
14-1
NOTE
The GPIO functionality of the external interrupt pins is controlled by the
EPORT module. However, some external interrupt signals are muxed with
other functions. In this case, the pin’s IRQ functionality must be enabled in
the GPIO module’s pin assignment register in order to use the pin’s GPIO
function via the EPORT registers. For more information, refer to
Chapter 15, “GPIO.”
14.3
Memory Map/Register Definition
This subsection describes the memory map and register structure.
14.3.1
Memory Map
Refer to Table 14-1 for a description of the EPORT memory map. The EPORT has an MBAR offset for
base address of 0xF00.
Table 14-1. Edge Port Module Memory Map
MBAR
Offset
Name
0xF00
EPORT pin assignment register
0xF04
EPORT data direction register
EPORT interrupt enable register
EPDDR
0xF08
EPORT data register
EPORT pin data register
EPDR
0xF0C
EPORT flag register
EPFR
Byte0
Byte1
Byte2
Byte3
Access1
—2
S
EPIER
—2
S/U
EPPDR
—2
EPPAR
—2
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
2 Writing to reserved address locations has no effect, and reading returns 0s.
14.3.2
Register Descriptions
The EPORT programming model consists of these registers:
• The EPORT pin assignment register (EPPAR) controls the function of each pin individually.
• The EPORT data direction register (EPDDR) controls the direction of each pin individually.
• The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin individually.
• The EPORT data register (EPDR) holds the data to be driven to the pins.
• The EPORT pin data register (EPPDR) reflects the current state of the pins.
• The EPORT flag register (EPFR) individually latches EPORT edge events.
MCF548x Reference Manual, Rev. 3
14-2
Freescale Semiconductor
Memory Map/Register Definition
14.3.2.1
15
R
EPORT Pin Assignment Register (EPPAR)
14
13
EPPA7
12
11
EPPA6
10
9
EPPA5
8
EPPA4
7
6
5
EPPA3
4
3
EPPA2
2
EPPA1
1
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Reg
Addr
0
0
0
0
0
0
MBAR + 0xF00
Figure 14-2. EPORT Pin Assignment Register (EPPAR)
Table 14-2. EPPAR Field Descriptions
Bits
Name
Description
15–2
EPPAn
EPORT pin assignment select fields. The read/write EPPAn fields configure EPORT pins for level
detection and rising and/or falling edge detection.
Pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a valid
interrupt request. Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive
interrupt request is acknowledged, the interrupt source must keep the signal asserted until
acknowledged by software. Level sensitivity must be selected to bring the device out of stop mode
with an IRQn interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt
generation. A pin configured for edge detection can trigger an interrupt regardless of its
configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt controller
module. EPPAR functionality is independent of the selected pin direction.
Reset clears the EPPAn fields.
00 Pin IRQn level-sensitive
01 Pin IRQn rising edge triggered
10 Pin IRQn falling edge triggered
11 Pin IRQn both falling edge and rising edge triggered
1–0
—
14.3.2.2
Reserved, should be cleared.
EPORT Data Direction Register (EPDDR)
R
7
6
5
4
3
2
1
0
EPDD7
EPDD6
EPDD5
EPDD4
EPDD3
EPDD2
EPDD1
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xF04
Figure 14-3. EPORT Data Direction Register (EPDDR)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
14-3
Table 14-3. EPDDR Field Descriptions
Bits
Name
Description
7–1
EPDDn
Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in
EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge
detection configuration. Reset clears EPDD7–EPDD1.
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must
be clear. Software can generate interrupt requests by programming the EPORT data register when
the EPDDR selects output.
0 Corresponding EPORT pin configured as input
1 Corresponding EPORT pin configured as output
0
—
14.3.2.3
Reserved, should be cleared.
Edge Port Interrupt Enable Register (EPIER)
R
7
6
5
4
3
2
1
0
EPIE7
EPIE6
EPIE5
EPIE4
EPIE3
EPIE2
EPIE1
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xF05
Figure 14-4. EPORT Port Interrupt Enable Register (EPIER)
Table 14-4. EPIER Field Descriptions
Bits
Name
7–1
EPIEn
0
—
14.3.2.4
Description
Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT
generates an interrupt request when:
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.
• The corresponding pin level is low and the pin is configured for level-sensitive operation.
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin. Reset
clears EPIE7–EPIE1.
0 Interrupt requests from corresponding EPORT pin disabled
1 Interrupt requests from corresponding EPORT pin enabled
Reserved, should be cleared.
Edge Port Data Register (EPDR)
R
7
6
5
4
3
2
1
0
EPD7
EPD6
EPD5
EPD4
EPD3
EPD2
EPD1
0
1
1
1
1
1
1
1
1
W
Reset
Reg
Addr
MBAR + 0xF08
Figure 14-5. EPORT Port Data Register (EPDR)
MCF548x Reference Manual, Rev. 3
14-4
Freescale Semiconductor
Memory Map/Register Definition
Table 14-5. EPDR Field Descriptions
Bits
Name
Description
7–1
EPDx
Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the port is
configured as an output, the bit stored for that pin is driven onto the pin. Reading EDPR returns
the data stored in the register. Reset sets EPD7-EPD1.
0
—
14.3.2.5
Reserved, should be cleared.
Edge Port Pin Data Register (EPPDR)
R
7
6
5
4
3
2
1
0
EPPD7
EPPD6
EPPD5
EPPD4
EPPD3
EPPD2
EPPD1
0
W
Reset
Current pin state
Reg
Addr
0
MBAR + 0xF09
Figure 14-6. EPORT Port Pin Data Register (EPPDR)
Table 14-6. EPPDR Field Descriptions
Bits
Name
Description
7–1
EPPDx
Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins
IRQ7–IRQ1. Writing to EPPDR has no effect, and the write cycle terminates normally. Reset does
not affect EPPDR.
0
—
14.3.2.6
Reserved, should be cleared.
Edge Port Flag Register (EPFR)
R
7
6
5
4
3
2
1
0
EPF7
EPF6
EPF5
EPF4
EPF3
EPF2
EPF1
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xF0C
Figure 14-7. EPORT Port Flag Register (EPFR)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
14-5
Table 14-7. EPFR Field Descriptions
Bits
Name
7–1
EPFn
0
—
Description
Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding
read/write bit in EPFR indicates that the selected edge has been detected. Reset clears
EPF7–EPF1.
Bits in this register are set when the selected edge is detected on the corresponding pin. A bit
remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as
level-sensitive (EPPARn = 00), pin transitions do not affect this register.
0 Selected edge for IRQx pin has not been detected.
1 Selected edge for IRQx pin has been detected.
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
14-6
Freescale Semiconductor
Chapter 15
GPIO
15.1
Introduction
Many of the MCF548x pins whose primary function is to serve as the external interface to off-chip
resources may also be used for general-purpose digital I/O (GPIO) access and for one or two secondary
functions. When used for GPIO purposes, the port x pins (PXXX) indicate which port is being accessed. In
some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
The MCF548x GPIO signals are grouped into 8-bit ports; however, some ports do not use all eight bits.
Each GPIO port has registers that configure, monitor, and control the port signals.
Figure 15-1 is a block diagram of the MCF548x GPIO module.
NOTE
The actual signals and functions available vary for different members of the
MCF548x family. See Chapter 2, “Signal Descriptions,” for more details.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-1
PORT
FBCTL
PORT
FBCS
PORT
DMA
PORT
FEC0H
PORT
FEC0L
PORT
FEC1H
PORT
FEC1L
PORT
FECI2C
BWE[3:0] / PFBCTL[7:4]
OE / PFBCTL3
R/W / PFBCTL2
TA / PFBCTL1
ALE / PFBCTL0
PORT
PCIBG
PCIBG[4:0] / PPCIBG[4:0]
PORT
PCIBR
PCIBR[4:0] / PPCIBR[4:0]
FBCS[5:1] / PFBCS[5:1]
DACK[1:0] / PDMA[3:2]
DREQ[1:0] / PDMA[1:0]
PORT
PSC3PSC2
FEC0TXCLK / PFEC0H7
FEC0TXEN / PFEC0H6
FEC0TXD0 / PFEC0H5
FEC0COL / PFEC0H4
FEC0RXCLK / PFEC0H3
FEC0RXDV / PFEC0H2
FEC0RXD0 / PFEC0H1
FEC0CRS / PFEC0H0
PORT
PSC1PSC0
FEC0TXD3 / PFEC0L7
FEC0TXD2 / PFEC0L6
FEC0TXD1 / PFEC0L5
FEC0TXER / PFEC0L4
FEC0RXD3 / PFEC0L3
FEC0RXD2 / PFEC0L2
FEC0RXD1 / PFEC0L1
FEC0RXER / PFEC0L0
FEC1TXCLK / PFEC1H7
FEC1TXEN / PFEC1H6
FEC1TXD0 / PFEC1H5
FEC1COL / PFEC1H4
FEC1RXCLK / PFEC1H3
FEC1RXDV / PFEC1H2
FEC1RXD0 / PFEC1H1
FEC1CRS / PFEC1H0
PORT
DSPI
PORT
IRQ1
FEC1TXD3 / PFEC1L7
FEC1TXD2 / PFEC1L6
FEC1TXD1 / PFEC1L5
FEC1TXER / PFEC1L4
FEC1RXD3 / PFEC1L3
FEC1RXD2 / PFEC1L2
FEC1RXD1 / PFEC1L1
FEC1RXER / PFEC1L0
PORT
TIM2
PSC3CTS / PPSC3PSC27
PSC3RTS / PPSC3PSC26
PSC3RXD / PPSC3PSC25
PSC3TXD / PPSC3PSC24
PSC2CTS / PPSC3PSC23
PSC2RTS / PPSC3PSC22
PSC2RXD / PPSC3PSC21
PSC2TXD / PPSC3PSC20
PSC1CTS / PPSC1PSC07
PSC1RTS / PPSC1PSC06
PSC1RXD / PPSC1PSC05
PSC1TXD / PPSC1PSC04
PSC0CTS / PPSC1PSC03
PSC0RTS / PPSC1PSC02
PSC0RXD / PPSC1PSC01
PSC0TXD / PPSC1PSC00
DSPIPCS5 / PCSS / PDSPI6
DSPIPCS3 / PDSPI5
DSPIPCS2 / PDSPI4
DSPIPCS0 / SS / PDSPI3
DSPISCK / PDSPI2
DSPISIN / PDSPI1
DSPISOUT / PDSPI1
IRQ[7:1] / PIRQ[5:1]
TOUT[3:0] / PTIM[7:4]
TIN[3:0] / PTIM[3:0]
FEC0EMDIO / PFECI2C3
FEC0EMDC / PFECI2C2
SCL / PFECI2C1
SDA / PFECI2C0
1 The
2 The
port IRQ GPIO functionality is provided through the EPORT module.
port TIM GPIO funtionality is provided through the GPT module.
Figure 15-1. MCF548x GPIO Module Block Diagram
15.1.1
Overview
The MCF548x GPIO module controls the configuration and use for the following external GPIO ports
(register types in parentheses):
• ColdFire bus (FlexBus) accesses (FBCTL, FBCS)
MCF548x Reference Manual, Rev. 3
15-2
Freescale Semiconductor
External Pin Description
•
•
•
•
•
•
External DMA request and acknowledge (DMA)
PCI bus access (PCIGNT, PCIREQ)
Ethernet data and control (FEC0H, FEC0L, FEC1H, FEC1L, FECI2C)
I2C serial control (FECI2C)
DMA serial peripheral interface (DSPI)
Programmable serial control (PSC1PSC0 and PSC3PSC2)
15.1.2
Features
The MCF548x GPIO module includes these distinctive features:
• Control of primary function use of the supported GPIO ports indicated in Section 15.1.1,
“Overview”
• General purpose I/O support for all ports:
— Registers for storing output pin data
— Registers for controlling pin data direction
— Registers for reading current pin state
— Registers for setting and clearing output pin data registers
15.2
External Pin Description
The MCF548x GPIO module controls the functionality of several external pins. These pins are listed in
Table 15-1.
Table 15-1. MCF548x GPIO Module External Pins
Primary
Function
(Pin Name)1
GPIO
Alternate
Function 1
Alternate
Function 2
Description
Flexbus Control
BWE[3:2]
PFBCTL[7:6]
BE / BWE[3:2]
TSIZ[1:0]
Byte write strobes for external data transfer / Port
FBCTL[7:4] / Byte enables for external data transfer /
FlexBus transfer size
BWE[1:0]
PFBCTL[5:4]
BE / BWE[1:0]
FBADDR[1:0]
Byte write strobes for external data transfer / Port
FBCTL[7:4] / Byte enables for external data transfer /
FlexBus address[1:0]
OE
PFBCTL3
—
—
Output enable for external reads / Port FBCTL3
R/W
PFBCTL2
TBST
—
Read/write indication for external data transfer / Port
FBCTL2 / FlexBus transfer burst
TA
PFBCTL1
—
—
Transfer acknowledge for external data transfer / Port
FBCTL1
ALE
PFBCTL0
TBST
—
Address latch enable indication for external data transfer
/ Port FBCTL0 / FlexBus transfer burst
Flexbus Chip Selects
FBCS[5:1]
PFBCS[5:1]
—
—
Flexbus chip selects 5 – 1 / Port FBCS[5:4]
DMA Controller
DACK1
PDMA3
TOUT1
—
DMA acknowledge 1 / Port DMA3 / GP timer output 1
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-3
Table 15-1. MCF548x GPIO Module External Pins (Continued)
Primary
Function
(Pin Name)1
GPIO
Alternate
Function 1
Alternate
Function 2
DACK0
PDMA2
TOUT0
—
DREQ1
PDMA1
TIN1
IRQ1
DREQ0
PDMA0
TIN0
—
Description
DMA acknowledge 0 / Port DMA2 / GP timer output 0
DMA request 1 / Port DMA1 / GP timer input 1 / Interrupt 1
DMA request 0 / Port DMA0 / GP timer input 0
Fast Ethernet Controller 0
FEC0TXCLK
PFEC0H7
—
—
Ethernet Controller 0 transmit clock / Port FEC0H7
FEC0TXEN
PFEC0H6
—
—
Ethernet Controller 0 transmit enable / PFEC0H6
FEC0TXD0
PFEC0H5
—
—
Ethernet Controller 0 transmit data 0 / Port FEC0H5
FEC0COL
PFEC0H4
—
—
Ethernet Controller 0 collision / Port FEC0H4
FEC0RXCLK
PFEC0H3
—
—
Ethernet Controller 0 receive clock / Port FEC0H3
FEC0RXDV
PFEC0H2
—
—
Ethernet Controller 0 receive data valid / Port FEC0H2
FEC0RXD0
PFEC0H1
—
—
Ethernet Controller 0 receive data 0 / Port FEC0H1
FEC0CRS
PFEC0H0
—
—
Ethernet Controller 0 carrier receive sense / Port FEC0H0
FEC0TXD[3:1]
PFEC0L[7:5]
—
—
Ethernet Controller 0 transmit data / Port FEC0L[7:5]
FEC0TXER
PFEC0L4
—
—
Ethernet Controller 0 transmit error / Port FEC0L4
FEC0RXD[3:1]
PFEC0L[3:1]
—
—
Ethernet Controller 0 receive data [3:1] / Port FEC0L[3:1]
FEC0RXER
PFEC0L0
—
—
Ethernet Controller 0 receive error / Port FEC0L0
FEC0MDIO
PFECI2C3
—
—
Ethernet Controller 0 management data control / Port
FECI2C3
FEC0MDC
PFECI2C2
—
—
Ethernet Controller 0 management data clock / Port
FECI2C2
Fast Ethernet Controller 1
FEC1TXCLK
PFEC1H7
—
—
Ethernet Controller 1 transmit clock / Port FEC1H7
FEC1TXEN
PFEC1H6
—
—
Ethernet Controller 1 transmit enable / Port FEC1H6
FEC1TXD0
PFEC1H5
—
—
Ethernet Controller 1 transmit data 0 / Port FEC1H5
FEC1COL
PFEC1H4
—
—
Ethernet Controller 1 collision / Port FEC1H4
FEC1RXCLK
PFEC1H3
—
—
Ethernet Controller 1 receive clock / Port FEC1H3
FEC1RXDV
PFEC1H2
—
—
Ethernet Controller 1 receive data valid / Port FEC1H2
FEC1RXD0
PFEC1H1
—
—
Ethernet Controller 1 receive data 0 / Port FEC1H1
FEC1CRS
PFEC1H0
—
—
Ethernet Controller 1 carrier receive sense / Port FEC1H0
FEC1TXD[3:1]
PFEC1L[7:5]
—
—
Ethernet Controller 1 transmit data / Port FEC1L[7:5]
FEC1TXER
PFEC1L4
—
—
Ethernet Controller 1 transmit error / Port FEC1L4
FEC1RXD[3:1]
PFEC1L[3:1]
—
—
Ethernet Controller 1 receive data [3:1] / Port FEC1L[3:1]
FEC1RXER
PFEC1L0
—
—
Ethernet Controller 1 receive error / Port FEC1L0
FEC1MDIO
—
SDA
CANRX0
Ethernet Controller 1 management data control / I2C
serial data / FlexCAN 0 receive data
MCF548x Reference Manual, Rev. 3
15-4
Freescale Semiconductor
External Pin Description
Table 15-1. MCF548x GPIO Module External Pins (Continued)
Primary
Function
(Pin Name)1
GPIO
Alternate
Function 1
Alternate
Function 2
Description
FEC1MDC
—
SCL
CANTX0
Ethernet Controller 1 management data clock / I2C serial
clock / FlexCAN 0 transmit data
I2C Serial Control
SDA
PFECI2C1
—
—
I2C serial data / Port FECI2C1
SCL
PFECI2C0
—
—
I2C serial clock / Port FECI2C0
External Interrupts
IRQ6
2
PIRQ6
CANRX1
—
Interrupt 6 / Port IRQ6 / FlexCAN 1 receive data
IRQ5
PIRQ52
CANRX1
—
Interrupt 5 / Port IRQ5 / FlexCAN 1 receive data
DMA Serial Peripheral Interface
DSPICS5/PCSS
PDSPI6
—
—
DSPI synchronous peripheral chip select 3 / Port DSPI6
DSPICS3
PDSPI5
TOUT3
CANTX1
DSPI synchronous peripheral chip select 3 / Port DSPI5 /
GP timer out 3 / FlexCAN 1 transmit data
DSPICS2
PDSPI4
TOUT2
CANTX1
DSPI synchronous peripheral chip select 3 / Port DSPI4 /
GP timer out 2 / FlexCAN 1 transmit data
DSPICS0/SS
PDSPI3
PSC3RTS
PSC3FSYNC
DSPI synchronous peripheral chip select 3 / Port DSPI3 /
PSC3 request-to-send / PSC3 frame sync
DSPISCK
PDSPI2
PSC3CTS
PSC3BCLK
DSPISIN
PDSPI1
PSC3RXD
—
DSPI serial data input / Port DSPI1 / PSC3 receive data
DSPISOUT
PDSPI0
PSC3TXD
—
DSPI serial data output / Port DSPI 0 / PSC3 transmit data
DSPI serial clock / Port DSPI2 / PSC3 clear-to-send /
PSC3 modem clock
Programmable Serial Control Module 3
PSC3CTS
PPSC3PSC27
PSC3BCLK
—
PSC3 clear-to-send indication / Port PSC3PSC27 / PSC3
modem clock
PSC3RTS
PPSC3PSC26
PSC3FSYNC
—
PSC3 request-to-send indication / Port PSC3PSC26 /
PSC3 frame sync
PSC3RXD
PPSC3PSC25
—
—
PSC3 receive data / Port PSC3PSC25
PSC3TXD
PPSC3PSC24
—
—
PSC3 transmit data / Port PSC3PSC24
Programmable Serial Control Module 2
PSC2CTS
PPSC3PSC23
PSC2BCLK
CANRX0
PSC2 clear-to-send indication / Port PSC3PSC23 / PSC2
modem clock
PSC2RTS
PPSC3PSC22
PSC2FSYNC
CANTX0
PSC2 request-to-send indication / Port PSC3PSC22 /
PSC2 frame sync
PSC2RXD
PPSC3PSC21
—
—
PSC2 receive data / Port PSC3PSC21
PSC2TXD
PPSC3PSC20
—
—
PSC2 transmit data / Port PSC3PSC20
Programmable Serial Control Module 1
PSC1CTS
PPSC1PSC07
PSC1BCLK
—
PSC1 clear-to-send indication / Port PSC1PSC07 / PSC1
modem clock
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-5
Table 15-1. MCF548x GPIO Module External Pins (Continued)
Primary
Function
(Pin Name)1
GPIO
Alternate
Function 1
Alternate
Function 2
PSC1RTS
PPSC1PSC06
PSC1FSYNC
—
PSC1 request-to-send indication / Port PSC1PSC06 /
PSC1 frame sync
PSC1RXD
PPSC1PSC05
—
—
PSC1 receive data / Port PSC1PSC05
PSC1TXD
PPSC1PSC04
—
—
PSC1 transmit data / Port PSC1PSC04
Description
Programmable Serial Control Module 0
PSC0CTS
PPSC1PSC03
PSC0BCLK
—
PSC0 clear-to-send indication / Port PSC1PSC03 / PSC0
modem clock
PSC0RTS
PPSC1PSC02
PSC0FSYNC
—
PSC0 request-to-send indication / Port PSC1PSC02 /
PSC0 frame sync
PSC0RXD
PPSC1PSC01
—
—
PSC0 receive data / Port PSC1PSC01
PSC0TXD
PPSC1PSC00
—
—
PSC0 transmit data / Port PSC1PSC00
Peripheral Component Interface
PCIBG4
PPCIGNT4
TBST
—
PCI bus grant 4 / Port PCIGNT4 / Flexbus transfer burst
PCIBG3
PPCIGNT3
TOUT3
—
PCI bus grant 3 / Port PCIGNT3 / GP timer out 3
PCIBG2
PPCIGNT2
TOUT2
—
PCI bus grant 2 / Port PCIGNT2 / GP timer out 2
PCIBG1
PPCIGNT1
TOUT1
—
PCI bus grant 1 / Port PCIGNT1 / GP timer out 1
PCIBG0
PPCIGNT0
TOUT0
—
PCI bus grant 0 / Port PCIGNT0 / GP timer out 0
PCIBR4
PPCIREQ4
IRQ4
—
PCI bus request 4 / Port PCIREQ4 / Interrupt 4
PCIBR3
PPCIREQ3
TIN2
—
PCI bus request 3 / Port PCIREQ3 / GP timer in 3
PCIBR2
PPCIREQ2
TIN2
—
PCI bus request 2 / Port PCIREQ2 / GP timer in 2
PCIBR1
PPCIREQ1
TIN1
—
PCI bus request 1 / Port PCIREQ1 / GP timer in 1
PCIBR0
PPCIREQ0
TIN0
—
PCI bus request 0 / Port PCIREQ0 / GP timer in 0
General Purpose Timer
2
TIN3
PTIM3
IRQ3
CANRX1
TOUT3
PTIM72
CANTX1
—
2
TIN2
PTIM2
IRQ2
CANRX1
TOUT2
PTIM62
CANTX1
—
GP timer in 3 / Port TIM7 / Interrupt 3 / FlexCAN 1 receive
data
GP timer out 3 / Port TIM6 / FlexCAN 1 transmit data
GP timer in 2 / Port TIM5 / Interrupt 1 / FlexCAN 2 receive
data
GP timer out 2 / Port TIM4 / FlexCAN 1 transmit data
1
The primary functionality of a pin is not necessarily the default function of the pin after reset. Most pins that have muxed GPIO
functionality will default to GPIO inputs. See the reset value of the associated pin assignment register. See Section 15.3.2.5, “Port
x Pin Assignment Registers (PAR_x)”) for more information on default pin functionality.
2 GPIO is supported, but the GPIO functionality is controlled by the timer or EPORT module instead of the GPIO module. Signals
are listed because there are pin assignment registers in the GPIO module for controlling the signal functions.
Refer to the signals chapter of the MCF548x chip specification for more detailed descriptions of these
signals. The function of most of the pins (primary function, GPIO, etc.) is determined by the GPIO module
pin assignment registers.
MCF548x Reference Manual, Rev. 3
15-6
Freescale Semiconductor
Memory Map/Register Definition
It should be noted from Table 15-1 that there are several cases where a function is mapped to more than
one pin. While it is possible to enable the function on more than one pin simultaneously, this type of
programming should be avoided for input functions to prevent unexpected behavior. All multiple-pin
functions are listed in Table 15-2.
Table 15-2. MCF548x Multiple-Pin Functions
Function
Direction
Associated Pins
GP timer in 3 (TIN3)
I
TIN3, PCIBR3
GP timer in 2 (TIN2)
I
TIN2, PCIBR2
GP timer in 1 (TIN1)
I
TIN1, PCIBR1, DREQ1
GP timer in 0 (TIN0)
I
TIN0, PCIBR0, DMA_REQ0
GP timer out 3 (TOUT3)
O
TOUT3, PCIBG3, DSPI_PSC3
GP timer out 2 (T2OUT)
O
TOUT2, PCIBG2, DSPI_PSC2
GP timer out 1 (T1OUT)
O
TOUT1, PCIBG1, DACK1
GP timer out 0 (T0OUT)
O
TOUT0, PCIBG0, DACK0
FlexCAN 0 transmit data (CANTX0)
O
PSC2RTS, FEC1MDC
FlexCAN 0 receive data (CANRX0)
I
PSC2CTS, FEC1MDIO
FlexCAN 1 transmit data (CANTX1)
O
T3OUT, T2OUT, DSPI_PCS3, DSPI_PCS2
FlexCAN 1 receive data (CANRX1)
I
T3IN, T2IN, IRQ6, IRQ5
2C
I
serial data (SDA)
I/O
SDA, FEC1MDC
I2C
serial clock (SCL)
I/O
SDA, FEC1MDIO
PSC3 request-to-send (PSC3RTS)
O
PSC3RTS, DSPIPCS0/SS
PSC3 clear-to-send (PSC3CTS)
I
PSC3CTS, DSPISCK
PSC3 modem clock (PSC3BCLK)
I
PSC3CTS, DSPISCK
PSC3 frame sync (PSC3FSYNC)
I
PSC3CTS, DSPIPCS0/SS
PSC3 uart receive data (PSC3RXD)
I
PSC3RXD, DSPISIN
PSC3 uart transmit data (PSC3TXD)
O
PSC3TXD, DSPISOUT
15.3
15.3.1
Memory Map/Register Definition
Register Overview
Table 15-3 summarizes all the registers in the MCF548x GPIO module address space.
Table 15-3. MCF548x GPIO Module Memory Map
MBAR
Offset
31–24
23–16
15–8
7–0
Access1
Port Output Data Registers
0xA00
PODR_FBCTL
PODR_FBCS
PODR_DMA
Reserved3
S/U
0xA04
PODR_FEC0H
PODR_FEC0L
PODR_FEC1H
PODR_FEC1L
S/U
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-7
Table 15-3. MCF548x GPIO Module Memory Map (Continued)
MBAR
Offset
31–24
23–16
15–8
7–0
Access1
0xA08
PODR_FECI2C
PODR_PCIBG
PODR_PCIBR
Reserved3
S/U
0xA0C
PODR_PSC3PSC2
PODR_PSC1PSC0
PODR_DSPI
Reserved3
S/U
Port Data Direction Registers
0xA10
PDDR_FBCTL
PDDR_FBCS
PDDR_DMA
Reserved2
S/U
0xA14
PDDR_FEC0H
PDDR_FEC0L
PDDR_FEC1H
PDDR_FEC1L
S/U
0xA18
PDDR_FECI2C
PDDR_PCIBG
PDDR_PCIBR
Reserved3
S/U
3
Reserved
S/U
0xA1C
PDDR_PSC3PSC2
PDDR_PSC1PSC0
PDDR_DSPI
Port Pin Data/Set Data Registers
0xA20
PPDSDR_FBCTL
PPDSDR_FBCS
PPDSDR_DMA
Reserved3
S/U
0xA24
PPDSDR_FEC0H
PPDSDR_FEC0L
PPDSDR_FEC1H
PPDSDR_FEC1L
S/U
S/U
0xA28
PPDSDR_FECI2C
PPDSDR_PCIBG
PPDSDR_PCIBR
Reserved3
0xA2C
PPDSDR_PSC3PSC2
PPDSDR_PSC1PSC0
PPDSDR_DSPI
Reserved3
S/U
Port Clear Output Data Registers
0xA30
PCLRR_FBCTL
PCLRR_FBCS
PCLRR_DMA
Reserved3
S/U
0xA34
PCLRR_FEC0H
PCLRR_FEC0L
PCLRR_FEC1H
PCLRR_FEC1L
S/U
0xA38
PCLRR_FECI2C
PCLRR_PCIBG
PCLRR_PCIBR
Reserved3
S/U
PCLRR_DSPI
Reserved3
S/U
PAR_DMA
S/U
0xA3C
PCLRR_PSC3PSC2
PCLRR_PSC1PSC0
Pin Assignment Registers
0xA40
PAR_FBCTL
0xA44
PAR_FECI2CIRQ
Reserved3
S/U
0xA48
PAR_PCIBG
PAR_PCIBR
S/U
0xA4C
0xA50
PAR_PSC3
PAR_FBCS
PAR_PSC2
PAR_DSPI
2
PAR_PSC0
S/U
PAR_TIMER
3
S/U
Reserved
Reserved3
0xA54–
0xA7F
1
PAR_PSC1
S/U = supervisor or user mode access.
Reads to reserved locations return 0s. Writes have no effect.
15.3.2
15.3.2.1
Register Descriptions
Port x Output Data Registers (PODR_x)
The PODR registers store the data to be driven on the corresponding port x pins when the pins are
configured for general purpose output.
MCF548x Reference Manual, Rev. 3
15-8
Freescale Semiconductor
Memory Map/Register Definition
Most PODR_x registers have full 8-bit implementations, as shown in Figure 15-2. The remaining PODR_x
registers use fewer than eight bits. These registers are shown in Figure 15-3, Figure 15-4, Figure 15-5, and
Figure 15-6.
The PODR_x registers are read/write. At reset, all implemented bits in the PODR_x registers are set.
Unimplemented bits always remain cleared.
Reading a PODR_x register returns the current values in the register, not the port x pin values.
To set bits in a PODR_x register, write 1s to the PODR_x bits, or write 1s to the corresponding bits in the
PORTP_x/SET_x register. To clear bits in a PODR_x register, write 0s to the PODR_x bits, or write 0s to
the corresponding bits in the PCLRR_x register.
15.3.2.1.1
8-Bit PODR_x Registers
The 8-bit PODR_x registers include the following:
• PODR_FBCTL
• PODR_FEC0H
• PODR_FEC0L
• PODR_FEC1H
• PODR_FEC1L
• PODR_PSC3PSC2
• PODR_PSC1PSC0
Figure 15-2 displays the 8-bit PODR_x registers.
R
7
6
5
4
3
2
1
0
PODRx7
PODRx6
PODRx5
PODRx4
PODRx3
PODRx2
PODRx1
PODRx0
1
1
1
1
1
1
1
1
W
Reset
Reg MBAR + 0xA00 (PODR_FBCTL), 0xA04 (PODR_FEC0H), 0xA05 (PODR_FEC0L), 0xA06 (PODR_FEC1H),
Addr
0xA07 (PODR_FEC1L), 0xA0C (PODR_PSC3PSC2), 0xA0D (PODR_PSC1PSC0)
Figure 15-2. 8-Bit Port Output Data Registers (PODR_x)
Table 15-4. 8-Bit PODR_x Field Descriptions
Bits
Name
7–0
PODRxn
15.3.2.1.2
Description
PODRx Output Data Bits
0 Drive 0 when PORT x pin is general purpose output
1 Drive 1 when PORT x pin is general purpose output
7-Bit PODR_x Register
The 7-bit PODR_DSPI register is the output data register for the PDSPIn port. Figure 15-3 displays the
7-bit PODR_x register.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-9
7
R
0
6
5
4
3
2
1
0
PODRDSPI6 PODRDSPI5 PODRDSPI4 PODRDSPI3 PODRDSPI2 PODRDSPI1 PODRDSPI0
W
Reset
0
1
1
Reg
Addr
1
1
1
1
1
MBAR + 0xA0E (PODR_DSPI)
Figure 15-3. 7-Bit PODR_DSPI Register (PODR_x)
Table 15-5. 7-Bit PODR_DSPI Field Descriptions
Bits
Name
7
—
6–0
PODRDSPIn
15.3.2.1.3
Description
Reserved, should be cleared
PODR DSPI output data bits
0 Drive 0 when PDSPIn pin is general purpose output
1 Drive 1 when PDSPIn pin is general purpose output
5-Bit PODR_x Registers
The 5-bit PODR_x registers are the output data registers for PPCIBGn (PODR_PCIBG) and PPCIBRn
(PODR_PCIBR). Figure 15-4 displays the 5-bit PODR_x registers.
R
7
6
5
4
3
2
1
0
0
0
0
PODRx4
PODRx3
PODRx2
PODRx1
PODRx0
0
0
0
1
1
1
1
1
W
Reset
Reg
Addr
MBAR + 0xA09 (PODR_PCIBG), 0xA0A (PODR_PCIBR)
Figure 15-4. 5-Bit PODR_PCIBG and PODR_PCIBR Registers
Table 15-6. 5-Bit PODR_PCIBG and PODR_PCIBR Field Descriptions
Bits
Name
7–5
—
4–0
PODRxn
15.3.2.1.4
Description
Reserved, should be cleared
PODR_PCIBG and PODR_PCIBR output data bits
0 Drive 0 when PPCIBGn or PPCIBRn pin is general purpose output
1 Drive 1 when PPCIBGn or PPCIBRn pin is general purpose output
4-Bit PODR_x Registers
The 4-bit PODR_x registers are the output data registers for PDMAn (PODR_DMA) and PFECI2Cn
(PODR_FECI2C). Figure 15-3 displays the 4-bit PODR_x registers.
MCF548x Reference Manual, Rev. 3
15-10
Freescale Semiconductor
Memory Map/Register Definition
R
7
6
5
4
3
2
1
0
0
0
0
0
PODRx3
PODRx2
PODRx1
PODRx0
0
0
0
0
1
1
1
1
W
Reset
Reg
Addr
MBAR + 0xA02 (PORT_DMA), 0xA08 (PORT_FECI2C)
Figure 15-5. 4-Bit PODR_DMA and PODR_FECI2C Registers
Table 15-7. 4-Bit PODR_DMA and PODR_FECI2C Field Descriptions
Bits
Name
7–4
—
3–0
PODRxn
15.3.2.1.5
Description
Reserved, should be cleared
PORT_DMA and PORT_FECI2C output data bits
0 Drive 0 when PDMAn or PFECI2Cn pin is general purpose output
1 Drive 1 when PDMAn or PFECI2Cn pin is general purpose output
FBCS Register (PODR_FBCS)
The 5-bit PODR_FBCS register is the output data register for PFBCSn (PODR_FBCS). Figure 15-6
displays the 5-bit PODR_FBCS register.
R
7
6
5
4
3
2
1
0
0
0
PODRFB5
PODRFB4
PODRFB3
PODRFB2
PODRFB1
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xA01 (PODR_FBCS)
Figure 15-6. 5-Bit PODR_FBCS Register
Table 15-8. 5-Bit PODR_FBCS Field Descriptions
Bits
Name
7–6
—
5–1
0
15.3.2.2
Description
Reserved, should be cleared
PODRFBn PORT_FBCS output data
0 Drive 0 when PFBCSn pin is general purpose output
1 Drive 1 when PFBCSn pin is general purpose output
—
Reserved, should be cleared
Port x Data Direction Registers (PDDR_x)
The PDDR registers control the direction of the port x pin drivers when the pins are configured for general
purpose I/O.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-11
Most PDDR_x registers have a full 8-bit implementation, as shown in Figure 15-7. The remaining
PDDR_x registers use fewer than eight bits. Their bit definitions are shown in Figure 15-8, Figure 15-9,
Figure 15-10, and Figure 15-11.
The PDDR_x registers are read/write. At reset, all bits in the PDDR_x registers are cleared. Setting any bit
in a PDDR_x register configures the corresponding port x pin as an output. Clearing any bit in a PDDR_x
register configures the corresponding pin as an input.
15.3.2.2.1
8-Bit PDDR_x Registers
The 8-bit PDDR_x registers include the following:
• PDDR_FBCTL
• PDDR_FEC0H
• PDDR_FEC0L
• PDDR_FEC1H
• PDDR_FEC1L
• PDDR_PSC3PSC2
• PDDR_PSC1PSC0
Figure 15-7 displays the 8-bit PDDR_x registers.
R
7
6
5
4
3
2
1
0
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
0
0
0
0
0
0
0
0
W
Reset
Reg MBAR + 0xA10 (PDDR_FBCTL), 0xA14 (PDDR_FEC0H), 0xA15 (PDDR_FEC0L), 0xA16 (PDDR_FEC1H), 0xA17
Addr
(PDDR_FEC1L), 0xA1C (PDDR_PSC3PSC2), 0xA1D (PDDR_PSC1PSC0)
Figure 15-7. 8-Bit Port Data Direction Registers
Table 15-9. 8-Bit PDDR_x Field Descriptions
Bits
Name
7–0
DDxn
15.3.2.2.2
Description
PDDR_x Data Direction Bits
0 PORT x pin is configured as input
1 PORT x pin is configured as output
7-Bit PDDR_x Register
The 7-bit PDDR_DSPI register sets the data direction for the PDSPIn port. Figure 15-8 displays the 7-bit
PDDR_DSPI register.
MCF548x Reference Manual, Rev. 3
15-12
Freescale Semiconductor
Memory Map/Register Definition
R
7
6
5
4
3
2
1
0
0
DDDSP
6
DDDSP5
DDDSP4
DDDSPI3
DDDSPI2
DDDSP1
DDDSP0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xA1E (PDDR_DSPI)
Figure 15-8. 7-Bit PDDR_DSPI Data Direction Register
Table 15-10. 7-Bit PDDR_DSPI Field Descriptions
Bits
Name
7
—
6–0
DDDSPn
15.3.2.2.3
Description
Reserved, should be cleared
PODR_DSPI data direction
0 PDSPIn pin configured as input
1 PDSPIn pin configured as output
5-Bit PDDR_x Registers
The 5-bit PDDR_x registers are the data direction registers for PPCIBGn (PDDR_PCIBG) and PPCIBRn
(PDDR_PCIBR). Figure 15-9 displays the 5-bit PDDR_x registers.
R
7
6
5
4
3
2
1
0
0
0
0
DDx4
DDx3
DDx2
DDx1
DDx0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xA11 (PDDR_FBCS), 0xA19 (PDDR_PCIBG), 0xA1A (PDDR_PCIBR)
Figure 15-9. 5-Bit PDDR_PCIBG and PDDR_PCIBR Registers
Table 15-11. 5-Bit PDDR_PCIBG and PDDR_PCIBR Field Descriptions
Bits
Name
7–5
—
4–0
DDxn
15.3.2.2.4
Description
Reserved, should be cleared
PDDR_PCIBG and PDDR_PCIBR Data Direction
0 PPCIBGn or PPCIBRn pin is configured as input
1 PPCIBGn or PPCIBRn pin is configured as output
4-Bit PDDR_x Registers
The 4-bit PDDR_x registers are for data direction of PDMAn (PDDR_DMA) and
(PDDR_FECI2C). Figure 15-10 displays the 4-bit PDDR_x registers.
PFECI2Cn
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-13
R
7
6
5
4
3
2
1
0
0
0
0
0
DDx3
DDx2
DDx1
DDx0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xA12 (PDDR_DMA), 0xA18 (PDDR_FECI2C)
Figure 15-10. 4-Bit PDDR_DMA and PDDR_FECI2C Registers
Table 15-12. 4-Bit PDDR_DMA and PDDR_FECI2C Field Descriptions
Bits
Name
7–4
—
3–0
DDxn
15.3.2.2.5
Description
Reserved, should be cleared
PDDR_DMA and PDDR_FECI2C Data Direction
0 PDMAn or PFECI2Cn pin is configured as input
1 PDMAn or PFECI2Cn pin is configured as output
FBCS Register (PDDR_FBCS)
The 5-bit PDDR_FBCS register is for data direction of PFBCSn. Figure 15-11 displays the 5-bit
PDDR_FBCS register.
R
7
6
5
4
3
2
1
0
0
0
DDFB5
DDFB4
DDFB3
DDFB2
DDFB1
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0xA11 (PDDR_FBCS)
Figure 15-11. 5-Bit PDDR_FBCS Register
Table 15-13. 5-Bit PDDR_FBCS Field Descriptions
Bits
Name
7–6
—
5–1
DDFBn
0
—
15.3.2.3
Description
Reserved, should be cleared
PDDR_FBCS data direction
0 PFBCSn pin is configured as input
1 PFBCSn pin is configured as output
Reserved, should be cleared
Port x Pin Data/Set Data Registers (PPDSDR_x)
The PPDSDR registers reflect the current pin states and control the setting of output pins when the pin is
configured for general purpose I/O.
MCF548x Reference Manual, Rev. 3
15-14
Freescale Semiconductor
Memory Map/Register Definition
Most PPDSDR_x registers have a full 8-bit implementation, as shown in Figure 15-12. The remaining
PPDSDR_x registers use fewer than eight bits. Their bit definitions are shown in Figure 15-13,
Figure 15-14, Figure 15-15, and Figure 15-16.
The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the current
pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Writing 1s to a
PPDSDR_x register sets the corresponding bits in the PODR_x register. Writing 0s has no effect.
15.3.2.3.1
8-Bit PPDSDR_x Registers
The 8-bit PPDSDR_x registers include the following:
• PPDSDR_FBCTL
• PPDSDR_FEC0H
• PPDSDR_FEC0L
• PPDSDR_FEC1H
• PPDSDR_FEC1L
• PPDSDR_PSC3PSC2
• PPDSDR_PSC1PSC0
• PPDSDR_PSC3PSC2
Figure 15-12 displays the 8-bit PPDSDR_x registers.
7
6
5
4
3
2
1
0
R
PPDx7
PPDx6
PPDx5
PPDx4
PPDx3
PPDx2
PPDx1
PPDx0
W
PSDx7
PSDx6
PSDx5
PSDx4
PSDx3
PSDx2
PSDx1
PSDx0
P1
P1
P1
P1
P1
P1
P1
P1
Reset
Reg
Addr
MBAR + 0xA20 (PPDSDR_FBCTL), 0xA24 (PPDSDR_FEC0H), 0xA25 (PPDSDR_FEC0L), 0xA26
(PPDSDR_FEC1H), 0xA27 (PPDSDR_FEC1L), 0xA2C (PPDSDR_PSC3PSC2), 0xA2D (PPDSDR_PSC1PSC0)
1
P = the current pin state. The exception is that PPDSDR_FBCTL is always reset to 0.
Figure 15-12. 8-Bit Port Pin Data / Set Data Registers
Table 15-14. 8-Bit PPDSDR_x Field Descriptions
Bits
Name
7–0
PPDxn
Port pin data. This is read-only.
0 Port x pin state is low
1 Port x pin state is high
PSDxn
Port set data.
0 No effect
1 Corresponding PODR_x bit is set
15.3.2.3.2
Description
7-Bit PPDSDR_x Register
The 7-bit PPDSDR_x register is for pin data and set data for PDSPIn. Figure 15-13 displays the 7-bit
PPDSDR_DSPI register.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-15
R
7
6
5
4
3
2
1
0
0
PPDx6
PPDx5
PPDx4
PPDx3
PPDx2
PPDx1
PPDx0
PSDx6
PSDx5
PSDx4
PSDx3
PSDx2
PSDx1
PSDx0
W
Reset
1
0
1
P
1
P
Reg
Addr
1
P
P
1
1
P
P
P1
MBAR + 0xA2E (PPDSDR_DSPI)
1
P = the current pin state.
Figure 15-13. 7-Bit Port Pin Data / Set Data Registers
Table 15-15. 7-Bit PPDSDR_DSPI Field Descriptions
Bits
Name
7
—
6–0
PPDxn
PPDSDR_DSPI pin data. This is Read-only.
0 PDSPIn pin state is low
1 PDSPIn pin state is high
PSDxn
PPDSDR_DSPI set data.
0 No effect
1 Corresponding PODR_DSPI bit is set
15.3.2.3.3
Description
Reserved, should be cleared.
5-Bit PPDSDR_x Registers
The 5-bit PPDSDR_x registers are the pin data and set data registers for PPCIBGn (PPDSDR_PCIBG) and
PPCIBRn (PPDSDR_PCIBR). Figure 15-14 displays the 5-bit PPDSDR_x registers.
R
7
6
5
4
3
2
1
0
0
0
0
PPDx4
PPDx3
PPDx2
PPDx1
PPDx0
PSDx4
PSDx3
PSDx2
PSDx1
PSDx0
P1
P1
P1
P1
P1
W
Reset
0
0
Reg
Addr
0
MBAR + 0xA29 (PPDSDR_PCIBG) and 0xA2A (PPDSDR_PCIBR)
1
P = the current pin state.
Figure 15-14. 5-Bit PPDSDR_PCIBG and PPDSDR_PCIBR Registers
Table 15-16. 5-Bit PPDSDR_PCIBG and PPDSDR_PCIBR Field Descriptions
Bits
Name
7–5
—
Description
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
15-16
Freescale Semiconductor
Memory Map/Register Definition
Table 15-16. 5-Bit PPDSDR_PCIBG and PPDSDR_PCIBR Field Descriptions (Continued)
Bits
Name
4–0
PPDxn
PPDSDR_PCIBG and PPDSDR_PCIBR pin data. This is Read-only.
0 PPCIBGn or PPCIBRn pin state is low
1 PPCIBGn or PPCIBRn pin state is high
PSDxn
PPDSDR_PCIBG and PPDSDR_PCIBR set data.
0 No effect
1 Corresponding PODR_PCIBGn or PODR_PCIBRn bit is set
15.3.2.3.4
Description
4-Bit PPDSDR_x Registers
The 4-bit PPDSDR_x registers are the pin data and set data registers for PDMAn (PPDSDR_DMA) and
PFECI2Cn (PPDSDR_FECI2C). Figure 15-15 displays the 4-bit PPDSDR_DMA and PPDSDR_FECI2C
registers.
R
7
6
5
4
3
2
1
0
0
0
0
0
PPDx3
PPDx2
PPDx1
PPDx0
PSDx3
PSDx2
PSDx1
PSDx0
P1
P1
P1
P1
W
Reset
0
0
Reg
Addr
0
0
MBAR + 0xA22 (PPDSDR_DMA) and 0xA28 (PPDSDR_FECI2C)
1
P = the current pin state.
Figure 15-15. 4-Bit PPDSDR_DMA and PPDSDR_FECI2C Registers
Table 15-17. 4-Bit PPDSDR_DMA and PPDSDR_FECI2C Field Descriptions
Bits
Name
7–4
—
4–0
PPDxn
PPDSDR_DMA and PPDSDR_FECI2C pin data. This is Read-only.
0 PDMAn or PFECI2Cn pin state is low
1 PDMAn or PFECI2Cn pin state is high
PSDXn
PPDSDR_DMA and PPDSDR_FECI2C set data.
0 No effect
1 Corresponding PODR_DMA or PODR_FECI2C bit is set
15.3.2.3.5
Description
Reserved, should be cleared.
FBCS Register (PPDSDR_FBCS)
The 5-bit PPDSDR_FBCS register is for pin data and set data for PFBCSn. Figure 15-16 displays the 5-bit
PPDSDR_FBCS register.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-17
R
7
6
5
4
3
2
1
0
0
0
PPDx5
PPDx4
PPDx3
PPDx2
PPDx1
0
PSDx5
PSDx4
PSDx3
PSDx2
PSDx1
W
Reset
0
1
0
P
Reg
Addr
1
P
1
P
1
P
P1
0
MBAR + 0xA21 (PDDSDR_FBCS)
1
P = the current pin state.
Figure 15-16. 5-Bit PDDSDR_FBCS Register
Table 15-18. 5-Bit PDDSDR_FBCS Field Descriptions
Bits
Name
7–6
—
5–1
PPDxn
PDDSDR_FBCS pin data. This is Read-only.
0 PFBCSn pin state is low
1 PFBCSn pin state is high
PSDxn
PDDSDR_FBCS set data.
0 No effect
1 Corresponding PODR_FBCS bit is set
0
15.3.2.4
—
Description
Reserved, should be cleared.
Reserved, should be cleared.
Port x Clear Output Data Registers (PCLRR_x)
Writing 0s to a PCLRR_x register clears the corresponding bits in the PODR_x register. Writing 1s has no
effect. Reading the PCLRR_x register returns 0s.
Most PCLRR_x registers have a full 8-bit implementation, as shown in Figure 15-17. The remaining
PCLRR_x registers use fewer than eight bits. Their bit definitions are shown in Figure 15-18,
Figure 15-19, Figure 15-20, and Figure 15-21.
The PCLRR_x registers are read/write. The 8-bit PCLRR_x registers include the following:
• PCLRR_FBCTL
• PCLRR_FEC0H
• PCLRR_FEC0L
• PCLRR_FEC1H
• PCLRR_FEC1L
• PCLRR_PSC3PSC2
• PCLRR_PSC1PSC0
Figure 15-17 displays the 8-bit PCLRR_x registers.
MCF548x Reference Manual, Rev. 3
15-18
Freescale Semiconductor
Memory Map/Register Definition
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
CLRx7
CLRx6
CLRx5
CLRx4
CLRx3
CLRx2
CLRx1
CLRx0
0
0
0
0
0
0
0
0
Reset
Reg MBAR + 0xA30 (PCLRR_FBCTL), 0xA34 (PCLRR_FEC0H), 0xA35 (PCLRR_FEC0L), 0xA36 (PCLRR_FEC1H),
Addr
0xA37 (PCLRR_FEC1L), 0xA3C (PCLRR_PSC3PSC2), 0xA3D (PCLRR_PSC1PSC0)
Figure 15-17. 8-Bit Port Clear Output Data Registers
Table 15-19. 8-Bit PCLRR_x Field Descriptions
Bits
Name
7–0
CLRxn
15.3.2.4.1
Description
Clear output data registers
0 Corresponding PODR_x bit is cleared
1 No effect
7-Bit PCLRR_x Register
The 7-bit PCLRR_DSPI register is the clear output data register for PDSPIn. Figure 15-18 displays the
7-bit PCLRR_DSPI register.
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
CLRDSP6
CLRDSP5
CLRDSP4
CLRDSP3
CLRDSP2
CLRDSP1
CLRDSP0
0
0
0
0
0
0
0
W
Reset
0
Reg
Addr
MBAR + 0xA3E (PCLRR_DSPI)
Figure 15-18. 7-Bit Port Clear Output Data DSPI Register
Table 15-20. 7-Bit PCLRR_DSPI Field Descriptions
Bits
Name
7
—
6–0
CLRDSPn
15.3.2.4.2
Description
Reserved, should be cleared
PCLRR_DSPI Clear output data register
0 Corresponding PODR_DSPI bit is cleared
1 No effect
5-Bit PCLRR_x Registers
The 5-bit PCLRR_x registers are the pin data and set data registers for PPCIBGn (PCLRR_PCIBG) and
PPCIBRn (PCLRR_PCIBR). Figure 15-19 displays the 5-bit PCLRR_x registers.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-19
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PCLRRx4
PCLRRx3
PCLRRx2
PCLRRx1
PCLRRx0
0
0
0
0
0
W
Reset
0
0
Reg
Addr
0
MBAR + 0xA39 (PCLRR_PCIBG) and 0xA3A (PCLRR_PCIBR)
Figure 15-19. 5-Bit PCIBG and PCIBR Clear Output Data Register
Table 15-21. 5-Bit PCLRR_PCIBG and PCLRR_PCIBR Field Descriptions
Bits
Name
7–5
—
4–0
PCLRRxn
15.3.2.4.3
Description
Reserved, should be cleared
PCLRR_PCIBG and PCLRR_PCIBR clear output data registers
0 Corresponding PODR_PCIGNT or PODR_PCIBR bit is cleared
1 No effect
4-Bit PCLRR_x Registers
The 4-bit PCLRR_x registers are the clear output data registers for PDMAn (PCLRR_DMA) and
PFECI2Cn (PCLRR_FECI2C). Figure 15-20 displays the 4-bit PCLRR_x registers.
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PCLRRx3
PCLRRx2
PCLRRx1
PCLRRx0
0
0
0
0
W
Reset
0
0
Reg
Addr
0
0
MBAR + 0xA32 (PCLRR_DMA) and 0xA38 (PCLRR_FECI2C)
Figure 15-20. 4-Bit DMA and FECI2C Clear Output Data Registers
Table 15-22. 4-Bit PCLRR_DMA and PCLRR_FECI2C Field Descriptions
Bits
Name
7–4
—
3–0
PCLRRxn
15.3.2.4.4
Description
Reserved, should be cleared
PCLRR_DMA and PCLRR_FECI2C clear output data registers
0 Corresponding PODR_DMA or PODR_FECI2C bit is cleared
1 No effect
5-Bit PCLRR_FBCS Registers
The 5-bit PCLRR_FBCS register is the clear output data register for PFBCSn. Figure 15-21 displays the
5-bit PCLRR_FBCS register.
MCF548x Reference Manual, Rev. 3
15-20
Freescale Semiconductor
Memory Map/Register Definition
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
CLRFB5
CLRFB4
CLRFB3
CLRFB2
CLRFB1
0
0
0
0
0
W
Reset
0
0
Reg
Addr
0
MBAR + 0xA31 (PCLRR_FBCS)
Figure 15-21. 5-Bit FlexBus Clear Output Data Register
Table 15-23. 5-Bit PCLRR_FBCS Field Descriptions
Bits
Name
7–6
—
5–1
CLRFBn
0
—
15.3.2.5
Description
Reserved, should be cleared
PCLRR_FBCS clear output data register
0 Corresponding PODR_FBCS bit is cleared
1 No effect
Reserved, should be cleared
Port x Pin Assignment Registers (PAR_x)
The PAR_x registers select the signal function that will be driven on the physical pin.
15.3.2.5.1
FlexBus Control Pin Assignment Register (PAR_FBCTL)
The FlexBus control pin assignment (PAR_FBCTL) register controls the function of the FlexBus control
signal pins. The PAR_FBCTL register is read/write.
R
15
14
13
12
11
10
9
8
7
6
0
PAR_
BWE3
0
PAR_
BWE2
0
PAR_
BWE1
0
PAR_
BWE0
0
PAR_
OE
0
1
0
1
0
1
0
1
0
1
W
Reset
Reg
Addr
5
4
PAR_RWB
1
1
3
2
0
PAR_
TA
0
1
1
0
PAR_ALE
1
1
MBAR + 0xA40 (PAR_FBCTL)
Figure 15-22. FlexBus Control Pin Assignment Register (PAR_FBCTL)
Table 15-24. PAR_FBCTL Field Descriptions
Bits
Name
15
—
14
13
Description
Reserved, should be cleared.
PAR_BWE3 The PAR_BWE bit configures the BE3/BWE3 pin for its primary function or general purpose I/O.
0 BE3/BWE3 pin configured for general purpose I/O (PFBCTL7)
1 BE3/BWE3 pin configured for FlexBus BE3/BWE3 or TSIZ1 function.
The function chosen depends on the reset configuration.
—
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-21
Table 15-24. PAR_FBCTL Field Descriptions (Continued)
Bits
Name
12
Description
PAR_BWE2 The PAR_BWE bit configures the BE2/BWE2 pin for its primary function or general purpose I/O.
0 BE2/BWE2 pin configured for general purpose I/O (PFBCTL6)
1 BE2/BWE2 pin configured for FlexBus BE2/BWE2 or TSIZ0 function.
The function chosen depends on the reset configuration.
11
—
Reserved, should be cleared. Writes have no effect and terminate without transfer error exception
PAR_BWE1 The PAR_BWE bit configures the BE1/BWE1 pin for its primary function or general purpose I/O.
0 BE1/BWE1 pin configured for general purpose I/O (PFBCTL5)
1 BE1/BWE1 pin configured for FlexBus BE1/BWE1 or FBADDR1 function.
The function chosen depends on the reset configuration.
10
9
—
Reserved, should be cleared.
PAR_BWE0 The PAR_BWE bit configures the BE0/BWE0 pin for its primary function or general purpose I/O.
0 BE0/BWE0 pin configured for general purpose I/O (PFBCTL4)
1 BE0/BWE0 pin configured for FlexBus BE0/BWE0 or FBADDR0 function.
The function chosen depends on the reset configuration.
8
7
—
6
PAR_OE
5–4
Reserved, should be cleared.
The PAR_OE bit configures the OE pin for its primary function or general purpose I/O.
0 OE pin configured for general purpose I/O (PFBCTL3)
1 OE pin configured for Flexbus OE function.
PAR_RWB The PAR_RWB bit configures the R/W pin for its primary function or general purpose I/O
0x R/W pin configured for general purpose I/O (PFBCTL2)
10R/W pin configured for Flexbus TBST function
11R/W pin configured for Flexbus R/W function
3
—
2
PAR_TA
1–0
PAR_ALE
15.3.2.6
Reserved, should be cleared.
The PAR_TA bit configures the TA pin for its primary function or general purpose I/O
0 TA pin configured for general purpose I/O (PFBCTL1)
1 TA pin configured for Flexbus TA function
The PAR_ALE bit configures the ALE pin for one of its primary functions or general purpose I/O.
0X ALE pin configured for general purpose I/O (PFBCTL0)
10 ALE pin configured for Flexbus TBST function
11 ALE pin configured for Flexbus ALE function
FlexBus Chip Select Pin Assignment Register (PAR_FBCS)
The PAR_FBCS register controls the function of the FlexBus chip select signal pins. The PAR_FBCS
register is read/write.
R
7
6
5
4
3
2
1
0
0
0
PAR_CS5
PAR_CS4
PAR_CS3
PAR_CS2
PAR_CS1
0
0
0
1
1
1
1
1
0
W
Reset
Reg
Addr
MBAR + 0xA42 (PAR_FBCS)
Figure 15-23. Flexbus Chip Select Pin Assignment Register (PAR_FBCS)
MCF548x Reference Manual, Rev. 3
15-22
Freescale Semiconductor
Memory Map/Register Definition
Table 15-25. PAR_FBCS Field Descriptions
Bits
Name
7–6
—
5–1
PAR_CSn
0
—
15.3.2.7
Description
Reserved, should be cleared.
The PAR_CSn bit configures the FBCSn pin for its primary function or general purpose I/O.
0 FBCSn pin configured for general purpose I/O (PFBCS[5:1])
1 FBCSn pin configured for FlexBus FBCSn function
Reserved, should be cleared.
DMA Pin Assignment Register (PAR_DMA)
The PAR_DMA register controls the function of the four MCF548x DMA pins.
The PAR_DMA register is read/write
7
R
6
PAR_DACK1
5
4
PAR_DACK0
3
2
PAR_DREQ1
1
0
PAR_DREQ0
W
Reset
0
Reg
Addr
0
0
0
0
0
0
0
MBAR + 0xA43 (PAR_DMA)
Figure 15-24. DMA Pin Assignment Register (PAR_DMA)
Table 15-26. PAR_DMA Field Descriptions
Bits
Name
Description
7–6
PAR_DACK1
The PAR_DACK1 field configures the DACK1 pin for its primary functions or general purpose I/O.
0X DACK1 pin configured for general purpose I/O (PDMA3)
10 DACK1 pin configured for GP Timer TOUT1 function
11 DACK1 pin configured for DACK1 function
5–4
PAR_DACK0
The PAR_DACK0 field configures the DACK0 pin for its primary functions or general purpose I/O.
0X DACK0 pin configured for general purpose I/O (PDMA2)
10 DACK0 pin configured for GP Timer TOUT0 function
11 DACK0 pin configured for DACK0 function
3–2
PAR_DREQ1 The PAR_DREQ1 field configures the DREQ1 pin for its primary functions or general purpose I/O.
00 = DREQ1 pin configured for general purpose I/O (PDMA1)
01 = DREQ1 pin configured for IRQ1 function
10 = DREQ1 pin configured for GP Timer TIN1 function
11 = DREQ1 pin configured for DREQ1 function
1–0
PAR_DREQ0 The PAR_DREQ0 field configures the DREQ0 pin for its primary functions or general purpose I/O.
0X = DREQ0 pin configured for general purpose I/O (PDMA0)
10 = DREQ0 pin configured for GP Timer TIN0 function
11 = DREQ0 pin configured for DREQ0 function
15.3.2.8
FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ)
The PAR_FECI2CIRQ register controls the functions of the FEC0, FEC1, I2C, and IRQ pins. The
PAR_FECI2CIRQ register is read/write
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-23
15
14
13
12
11
10
9
8
7
6
R PAR_ PAR_ PAR_
PAR_ PAR_ PAR_ PAR_E1MDIO PAR_E1MDC
E07 E0MII E0MDIO E0MDC E17 E1MII
W
Reset
0
0
0
Reg
Addr
0
0
0
1
1
1
1
5
4
0
0
0
0
3
2
1
PAR_ PAR_ PAR_ PAR_
SDA
SCL IRQ6 IRQ5
0
0
1
MBAR + 0xA44 (PAR_FECI2CIRQ)
Figure 15-25. FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ)
Table 15-27. PAR_FEC/I2C/IRQ Field Descriptions
Bits
Name
Description
15
PAR_E07
FEC0 7-wire mode pin assignment. Configures all the FEC0 7-wire mode pins (port FEC0H pins,
except for E0CRS) for their primary functions or general purpose I/O.
0 All FEC1 7-wire mode pins configured for GPIO (PFEC0H[7:1])
1 All FEC1 7-wire mode pins configured for their primary functions
14
PAR_E0MII
FEC1 MII mode-only pin assignment. Configures all the FEC0 MII mode-only pins (port FEC0L
pins, plus FEC0_CRS) for their primary functions or general purpose I/O.
0 All FEC0 MII mode-only pins configured for GPIO (PFEC0H0 and PFEC0L[7:0]
1 All FEC0 MII mode-only pins configured for their primary functions
13
PAR_E0MDIO
FEC0 MDIO pin assignment. Configures the E0MDIO pin for its primary function or general
purpose I/O.
0 E0MDIO pin configured for GPIO (PFECI2C3)
1 E0MDIO pin configured for E0MDIO function
12
PAR_E0MDC
FEC0 MDC pin assignment. Configures the E0MDC pin for its primary function or general
purpose I/O.
0 E0MDC pin configured for GPIO (PFECI2C2)
1 E0MDC pin configured for E0MDC function
11
PAR_E17
FEC1 7-wire mode pin assignment. Configures all the FEC1 7-wire mode pins (port FEC1H pins,
except for E1CRS) for their primary functions or general purpose I/O.
0 All FEC1 7-wire mode pins configured for GPIO (PFEC1H[7:1])
1 All FEC1 7-wire mode pins configured for their primary functions
10
PAR_E1MII
FEC1 MII mode-only pin assignment. Configures all the FEC1 MII mode-only pins (port FEC1L
pins, plus E1CRS) for their primary functions or general purpose I/O.
0 All FEC1 MII mode-only pins configured for GPIO (PFEC1H0 and PFEC1L[7:0])
1 All FEC1 MII mode-only pins configured for their primary functions
9–8
PAR_
E1MDIO
FEC1 MDIO pin assignment. Configures the E1MDIO pin for one of its primary functions. There
is no GPIO capability on this pin.
0X E1MDIO pin configured for FlexCAN CANRX0
10 E1MDIO pin configured for I2C SDA function
11 E1MDIO pin configured for FEC1 E1MDIO function
7–6
PAR_
E1MDC
FEC1 MDC pin assignment. Configures the E1MDC pin for one of its primary functions. There is
no GPIO capability on this pin.
0X E1MDC pin configured for FlexCAN CANTX0
10 E1MDC pin configured for I2C SCL function
11 E1MDC pin configured for FEC1 E1MDC function
5–4
—
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
15-24
0
Freescale Semiconductor
1
Memory Map/Register Definition
Table 15-27. PAR_FEC/I2C/IRQ Field Descriptions (Continued)
Bits
Name
3
PAR_SDA
SDA Pin Assignment. Configures the SDA pin for its primary function or general purpose I/O.
0 SDA pin configured for general purpose input (PFECI2C1)
1 SDA pin configured for SDA function
2
PAR_SCL
SCL Pin Assignment. Configures the SCL pin for its primary function or general purpose I/O.
0 SCL pin configured for GPIO (PFECI2C0)
1 SCL pin configured for SCL function
1
PAR_
IRQ6
IRQ6 Pin Assignment. Configures the IRQ6 pin for one of its primary functions.
0 IRQ6 pin configured for FlexCAN CANRX1
1 IRQ6 pin configured for IRQ6 function
Note that GPIO is obtained on the IRQ6 pin by (1) writing a 1 to PAR_IRQ6 and (2) disabling the
IRQ6 function in the EPORT module.
0
PAR_
IRQ5
IRQ5 Pin Assignment. Configures the IRQ5 pin for one of its primary functions.
0 IRQ5 pin configured for FlexCAN CANRX1
1 IRQ5 pin configured for IRQ5 function
Note that GPIO is obtained on the IRQ5 pin by (1) writing a 1 to PAR_IRQ5 and (2) disabling the
IRQ5 function in the EPORT module.
15.3.2.9
Description
PCI Grant Pin Assignment Register (PAR_PCIBG)
The PAR_PCIBG register controls the functions of the PCI grant pins. The PAR_PCIBG register is
read/write.
R
15
14
13
12
11
10
9
0
0
0
0
0
0
PAR_
PCIBG4
PAR_
PCIBG3
PAR_
PCIBG2
PAR_
PCIBG1
PAR_
PCIBG0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
8
0
7
6
0
5
4
0
3
2
0
1
0
0
MBAR + 0xA48 (PAR_PCIBG)
Figure 15-26. PCI Grant Pin Assignment Register (PAR_PCIBG)
Table 15-28. PAR_PCIBG Field Descriptions
Bits
Name
Description
15–10
—
9–8
PAR_
PCIBG4
PCIBG4 pin assignment. Configures the PCIBG4 pin for one of its primary functions or GPIO.
0X PCIBG4 pin configured for general purpose I/O (PPCIGNT4)
10 PCIBG4 pin configured for FlexBus TBST function
11 PCIBG4 pin configured for PCIBG4 function
7–6
PAR_
PCIBG3
PCIBG3 pin assignment. Configures the PCIBG3 pin for one of its primary functions or GPIO.
0X PCIBG3 pin configured for general purpose I/O (PPCIGNT3)
10 PCIBG3 pin configured for GP timer TOUT3 function
11 PCIBG3 pin configured for PCIBG3 function
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-25
Table 15-28. PAR_PCIBG Field Descriptions (Continued)
Bits
Name
Description
5–4
PAR_
PCIBG2
PCIBG2 pin assignment. Configures the PCIBG2 pin for one of its primary functions or GPIO.
0X PCIBG2 pin configured for general purpose I/O (PPCIGNT2)
10 PCIBG2 pin configured for GP timer TOUT2 function
11 PCIBG2 pin configured for PCIBG2 function
3–2
PAR_
PCIBG1
PCIBG1 pin assignment. Configures the PCIBG1 pin for one of its primary functions or GPIO.
0X PCIBG1 pin configured for general purpose I/O (PPCIGNT1)
10 PCIBG1 pin configured for GP timer TOUT1 function
11 PCIBG1 pin configured for PCIBG1 function
1–0
PAR_
PCIBG0
PCIBG0 pin assignment. Configures the PCIBG0 pin for one of its primary functions or GPIO.
0X PCIBG0 pin configured for general purpose I/O (PPCIGNT0)
10 PCIBG0 pin configured for GP timer TOUT0 function
11 PCIBG0 pin configured for PCIBG0 function
15.3.2.10 PCI Request Pin Assignment Register (PAR_PCIBR)
The PAR_PCIBR controls the functions of the PCI request pins. The PAR_PCIBR is read/write.
R
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
PAR_PCIBR4 PAR_PCIBR3 PAR_PCIBR2 PAR_PCIBR1 PAR_PCIBR0
W
Reset
Reg
Addr
0
0
0
0
0
0
0
0
0
0
MBAR + 0xA4A (PAR_PCIBR)
Figure 15-27. PCI Request Pin Assignment Register (PAR_PCIBR)
Table 15-29. PAR_PCIBR Field Descriptions
Bits
Name
15–10
—
Description
Reserved, should be cleared. Writes have no effect and terminate without transfer error
exception
9–8
PAR_PCIBR4 PCIBR4 Pin Assignment. Configures the PCIBR4 pin for one of its primary functions or GPIO.
0X PCIBR4 pin configured for general purpose I/O (PPCIREQ4)
10 PCIBR4 pin configured for IRQ4 function
11 PCIBR4 pin configured for PCIBR4 function
7–6
PAR_PCIBR3 PCIBR3 Pin Assignment. Configures the PCIBR3 pin for one of its primary functions or GPIO.
0X PCIBR3 pin configured for general purpose I/O (PPCIREQ3)
10 PCIBR3 pin configured for GP timer TIN3 function
11 PCIBR3 pin configured for PCIBR3 function
5–4
PAR_PCIBR2 PCIBR2 Pin Assignment. Configures the PCIBR2 pin for one of its primary functions or GPIO.
0X PCIBR2 pin configured for general purpose I/O (PPCIREQ2)
10 PCIBR2 pin configured for GP timer TIN2 function
11 PCIBR2 pin configured for PCIBR2 function
MCF548x Reference Manual, Rev. 3
15-26
Freescale Semiconductor
Memory Map/Register Definition
Table 15-29. PAR_PCIBR Field Descriptions (Continued)
Bits
Description
Name
3–2
PAR_PCIBR1 PCIBR1 Pin Assignment. Configures the PCIBR1 pin for one of its primary functions or GPIO.
0X PCIBR1 pin configured for general purpose I/O (PPCIREQ1)
10 PCIBR1 pin configured for GP timer TIN1 function
11 PCIBR1 pin configured for PCIBR1 function
1–0
PAR_PCIBR0 PCIBR0 Pin Assignment. Configures the PCIBR0 pin for one of its primary functions or GPIO.
0X PCIBR0 pin configured for general purpose I/O (PPCIREQ0)
10 PCIBR0 pin configured for GP timer TIN0 function
11 PCIBR0 pin configured for PCIBR0 function
15.3.2.11 PSC3 Pin Assignment Register (PAR_PSC3)
The PAR_PSC3 register controls the functions of the PSC3 pins. The PAR_PSC3 register is read/write.
7
6
R
5
PAR_CTS3
4
PAR_RTS3
3
2
1
0
PAR_RXD3
PAR_TXD3
0
0
0
0
0
0
W
Reset
0
Reg
Addr
0
0
0
MBAR + 0xA4C (PAR_PSC3)
Figure 15-28. PSC3 Pin Assignment Register (PAR_PCS3)
Table 15-30. PAR_PSC3 Descriptions
Bits
Name
Description
7–6
PAR_CTS3 PSC3CTS pin assignment. Configures the PSC3CTS pin for one of its primary functions or general
purpose I/O.
0X PSC3CTS pin configured for general purpose I/O (PPSC3PSC27)
10 PSC3CTS pin configured for PSC3BCLK function
11 PSC3CTS pin configured for PSC3CTS function
5–4
PAR_RTS3 PSC3RTS pin assignment. Configures the PSC3RTS pin for one of its primary functions or general
purpose I/O.
0X PSC3RTS pin configured for general purpose I/O (PPSC3PSC26)
10 PSC3RTS pin configured for PSC3FSYNC function
11 PSC3RTS pin configured for PSC3RTS function
3
PAR_RXD3 PSC3RXD pin assignment. Configures the PSC3RXD pin for its primary function or general purpose
I/O.
0 PSC3RXD pin configured for general purpose I/O (PPSC3PSC25)
1 PSC3RXD pin configured for PSC3RXD function
2
PAR_TXD3 PSC3TXD pin assignment. Configures the PSC3TXD pin for its primary function or general purpose
I/O.
0 PSC3TXD pin configured for general purpose I/O (PPSC3PSC24)
1 PSC3TXD pin configured for PSC3TXD function
1–0
—
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-27
15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2)
The PAR_PSC2 register controls the functions of the PSC2 pins. The PAR_PSC2 register is read/write.
7
R
6
5
PAR_CTS2
4
PAR_RTS2
3
2
1
0
PAR_RXD2
PAR_TXD2
0
0
0
0
0
0
W
Reset
0
0
Reg
Addr
0
0
MBAR + 0xA4D (PAR_PSC2)
Figure 15-29. PSC2 Pin Assignment Register (PAR_PSC2)
Table 15-31. PAR_PSC2 Descriptions
Bits
Name
Description
7–6
PAR_CTS2 PSC2CTS pin assignment. Configures the PSC2CTS pin for one of its primary functions or general
purpose I/O.
00 PSC2CTS pin configured for general purpose I/O (PPSC3PSC23)
01 PSC2CTS pin configured for FlexCAN CANRX0
10 PSC2CTS pin configured for PSC2BCLK function
11 PSC2CTS pin configured for PSC2CTS function
5–4
PAR_RTS2 PSC2RTS pin assignment. Configures the PSC2RTS pin for one of its primary functions or general
purpose I/O.
00 PSC2RTS pin configured for general purpose I/O (PPSC3PSC22)
01 PSC2RTS pin configured for FlexCAN CANTX0
10 PSC2RTS pin configured for PSC2FSYNC function
11 PSC2RTS pin configured for PSC2RTS function
3
PAR_RXD2 PSC2RXD pin assignment. Configures the PSC2RXD pin for its primary function or general
purpose I/O.
0 PSC2RXD pin configured for general purpose I/O (PPSC3PSC21)
1 PSC2RXD pin configured for PSC2RXD function
2
PAR_TXD2 PSC2TXD pin assignment. Configures the PSC2TXD pin for its primary function or general
purpose I/O.
0 PSC2TXD pin configured for general purpose I/O (PPSC3PSC20)
1 PSC2TXD pin configured for PSC2TXD function
1–0
—
Reserved, should be cleared.
15.3.2.13 PSC1 Pin Assignment Register (PAR_PSC1)
The PAR_PSC1 register controls the functions of the PSC1 pins. The PAR_PSC1 register is read/write.
MCF548x Reference Manual, Rev. 3
15-28
Freescale Semiconductor
Memory Map/Register Definition
7
R
6
5
PAR_CTS1
4
PAR_RTS1
3
2
PAR_RXD1 PAR_TXD1
1
0
0
0
0
0
W
Reset
0
0
0
Reg
Addr
0
0
0
MBAR + 0xA4E (PAR_PSC1)
Figure 15-30. PSC1 Pin Assignment Register (PAR_PSC1)
Table 15-32. PAR_PCS1 Descriptions
Bits
Name
Description
7–6
PAR_CTS1 PSC1CTS pin assignment. Configures the PSC1CTS pin for one of its primary functions or general
purpose I/O.
0X PSC1CTS pin configured for general purpose I/O (PPSC1PSC07)
10 PSC1CTS pin configured for PSC1BCLK function
11 PSC1CTS pin configured for PSC1CTS function
5–4
PAR_RTS1 PSC1RTS pin assignment. Configures the PSC1RTS pin for one of its primary functions or general
purpose I/O.
0X PSC1RTS pin configured for general purpose I/O (PPSC1PSC06)
10 PSC1RTS pin configured for PSC1FSYNC function
11 PSC1RTS pin configured for PSC1RTS function
3
PAR_RXD1 PSC1RXD Pin Assignment. Configures the PSC1RXD pin for its primary function or general purpose
I/O.
0 PSC1RXD pin configured for general purpose I/O (PPSC1PSC05)
1 PSC1RXD pin configured for PSC1RXD function
2
PAR_TXD1 PSC1TXD Pin Assignment. Configures the PSC1TXD pin for its primary function or general purpose
I/O.
0 PSC1TXD pin configured for general purpose I/O (PPSC1PSC04)
1 PSC1TXD pin configured for PSC1TXD function
1–0
—
Reserved, should be cleared.
15.3.2.14 PSC0 Pin Assignment Register (PAR_PSC0)
The PAR_PSC0 register controls the functions of the PSC0 pins. The PAR_PSC0 register is read/write.
7
R
6
5
PAR_CTS0
4
PAR_RTS0
3
2
1
0
PAR_RXD0
PAR_TXD0
0
0
0
0
0
0
W
Reset
0
Reg
Addr
0
0
0
MBAR + 0xA4F (PAR_PSC0)
Figure 15-31. PSC0 Pin Assignment Register (PAR_PSC0)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-29
Table 15-33. PAR_PCS0 Descriptions
Bits
Name
Description
7–6
PAR_CTS0 PSC0CTS pin assignment. Configures the PSC0CTS pin for one of its primary functions or general
purpose I/O.
0X PSC0CTS pin configured for general purpose I/O (PPSC1PSC03)
10 PSC0CTS pin configured for PSC0BCLK function
11 PSC0CTS pin configured for PSC0CTS function
5–4
PAR_RTS0 PSC0RTS pin assignment. Configures the PSC0RTS pin for one of its primary functions or general
purpose I/O.
0X PSC0RTS pin configured for general purpose I/O (PPSC1PSC02)
10 PSC0RTS pin configured for PSC0FSYNC function
11 PSC0RTS pin configured for PSC0RTS function
3
PAR_RXD0 PSC0RXD Pin Assignment. Configures the PSC0RXD pin for its primary function or general
purpose I/O.
0 PSC0RXD pin configured for general purpose I/O (PPSC1PSC01)
1 PSC0RXD pin configured for PSC0RXD function
2
PAR_TXD0 PSC0TXD Pin Assignment. Configures the PSC0TXD pin for its primary function or general
purpose I/O.
0 PSC0TXD pin configured for general purpose I/O (PPSC1PSC00)
1 PSC0TXD pin configured for PSC0TXD function
1–0
—
Reserved, should be cleared.
15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI)
The PAR_DSPI register controls the functions of MCF548x DSPI pins. The PAR_DSPI register is
read/write.
R
15
14
13
12
0
0
0
PAR_
CS5
0
0
0
0
W
Reset
Reg
Addr
11
10
9
8
7
6
PAR_CS3
PAR_CS2
PAR_CS0
0
0
0
0
0
5
4
PAR_SCK
0
0
0
3
2
PAR_SIN
0
0
1
0
PAR_SOUT
0
0
MBAR + 0xA50 (PAR_DSPI)
Figure 15-32. DSPI Pin Assignment Register (PAR_DSPI)
Table 15-34. PAR_DSPI Descriptions
Bits
Name
15–13
—
12
PAR_CS5
Description
Reserved, should be cleared.
DSPICS5/PCSS pin assignment. Configures the DSPICS5/PCSS pin for its primary function or
general purpose I/O.
0 DSPICS5/PCSS pin configured for general purpose I/O (PDSPI6)
1 DSPICS5/PCSS pin configured for DSPICS5/PCSS function
MCF548x Reference Manual, Rev. 3
15-30
Freescale Semiconductor
Memory Map/Register Definition
Table 15-34. PAR_DSPI Descriptions (Continued)
Bits
Name
Description
11–10
PAR_CS3
DSPICS3 pin assignment. Configures the DSPICS3 pin for its primary function or general purpose I/O.
00 DSPICS3 pin configured for general purpose I/O (PDSPI5)
01 DSPICS3 pin configured for FlexCAN CANTX1
10 DSPICS3 pin configured for GP timer TOUT3 function
11 DSPICS3 pin configured for DSPICS3 function
9–8
PAR_CS2
DSPICS2 pin assignment. Configures the DSPICS2 pin for its primary function or general purpose I/O.
00 DSPICS2 pin configured for general purpose I/O (PDSPI4)
01 DSPICS2 pin configured for FlexCAN CANTX1
10 DSPICS2 pin configured for GP timer TOUT2 function
11 DSPICS2 pin configured for DSPICS2 function
7–6
PAR_CS0
DSPICS0/SS pin assignment. Configures the DSPICS0/SS pin for its primary function or general
purpose I/O.
00 DSPICS0/SS pin configured for general purpose I/O (PDSPI3)
01 DSPICS0/SS pin configured for PSC3FSYNC data
10 DSPICS0/SS pin configured for PSC3RTS function
11 DSPICS0/SS pin configured for DSPICS0/SS function
5–4
PAR_SCK
DSPISCK pin assignment. Configures the DSPISCK pin for its primary function or general purpose
I/O.
00 DSPISCK pin configured for general purpose I/O (PDSPI2)
01 DSPISCK pin configured for PSC3BCLK data
10 DSPISCK pin configured for PSC3CTS function
11 DSPISCK pin configured for DSPISCK function
3–2
PAR_SIN
DSPISIN pin assignment. Configures the DSPISIN pin for its primary function or general purpose I/O.
0X DSPISIN pin configured for general purpose I/O (PDSPI1)
10 DSPISIN pin configured for PSC3RXD function
11 DSPISIN pin configured for DSPISIN function
1–0
PAR_SOUT DSPISOUT pin assignment. Configures the DSPISOUT pin for its primary function or general purpose
I/O.
0X DSPISOUT pin configured for general purpose I/O (PDSPI0)
10 DSPISOUT pin configured for PSC3TXD function
11 DSPISOUT pin configured for DSPISOUT function
15.3.2.16 General Purpose Timer Pin Assignment Register (PAR_TIMER)
The PAR_TIMER register controls the functions of MCF548x general purpose timer pins. The
PAR_TIMER register is read/write.
R
7
6
0
0
0
0
5
4
PAR_TIN3
3
2
PAR_TOUT3
1
PAR_TIN2
0
PAR_TOUT2
W
Reset
Reg
Addr
1
1
1
1
1
1
MBAR + 0xA52 (PAR_TIMER)
Figure 15-33. General Purpose Timer Pin Assignment Register (PAR_TIMER)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-31
Table 15-35. PAR_TIMER Descriptions
Bits
Name
7–6
—
5–4
PAR_TIN3
3
2–1
0
Description
Reserved, should be cleared.
TIN3 pin assignment. Configures the TIN3 pin for its primary function
0X TIN3 pin configured for FlexCAN CANRX1
10 TIN3 pin configured for IRQ3 function
11 TIN3 pin configured for GP timer TIN3 function or general purpose input
Note: General purpose input is obtained on the TIN3 pin by (1) writing 3 to the PAR_TIN3 field
and (2) disabling the timer function in the general purpose timer module. General purpose output
is not possible on the TIN3 pin.
PAR_TOUT TOUT3 pin assignment. Configures the TOUT3 pin for its primary function
3
0 TOUT3 pin configured for FlexCAN CANTX1
1 TOUT3 pin configured for GP timer TOUT3 function or general purpose output
Note: General purpose output is obtained on the TOUT3 pin by (1) writing 1 to the PAR_TOUT3
field and (2) disabling the timer function in the general purpose timer module. General purpose
input is not possible on the TOUT3 pin.
PAR_TIN2
TIN2 pin assignment. Configures the TIN2 pin for its primary function
0X TIN2 pin configured for FlexCAN CANRX1
10 TIN2 pin configured for IRQ2 function
11 TIN2 pin configured for GP timer TIN2 function or general purpose input
Note: General purpose input is obtained on the TIN2 pin by (1) writing 3 to the PAR_TIN2 field
and (2) disabling the timer function in the general purpose timer module. General purpose output
is not possible on the TIN2 pin.
PAR_TOUT TOUT2 pin assignment. Configures the TOUT2 pin for its primary function
2
0 TOUT2 pin configured for FlexCAN CANTX1
1 TOUT2 pin configured for GP timer TOUT2 function or general purpose output
Note: General purpose output is obtained on the TOUT2 pin by (1) writing 1 to the PAR_TOUT2
field and (2) disabling the timer function in the general purpose timer module. General purpose
input is not possible on the TOUT2 pin.
NOTE
Explicit pin function assignment capability for the TIN1, TOUT1, TIN0,
and TOUT0 pins is not needed in the GPIO module since these pins only
have the primary timer functions and general purpose I/O. Switching
between the primary timer functions and GPIO is handled by the general
purpose timer module.
15.4
15.4.1
Functional Description
Overview
Initial pin function is determined during reset configuration. See Chapter 2, “Signal Descriptions,” for
more details. Most pins are configured as general purpose I/O by default. The notable exceptions to this
are FlexBus control pins. These pins are configured for their primary functions after reset. The pin
assignment registers allow the user to select among various primary functions and general purpose I/O
after reset.
Every general purpose I/O pin is individually configurable as an input or an output via a data direction
register (PDDR_x). Every GPIO port has an output data register (PODR_x) and a pin data register
MCF548x Reference Manual, Rev. 3
15-32
Freescale Semiconductor
Functional Description
(PPDSDR_x) to monitor and control the state of its pins. Data written to a PODR_x register is stored and
then driven to the corresponding port x pins configured as outputs.
Reading a PODR_x register returns the current state of the register regardless of the state of the
corresponding pins. Reading a PPDSDR_x register returns the current state of the corresponding pins
when configured as general purpose I/O, regardless of whether the pins are inputs or outputs.
Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing
individual bits in the PODR_x register.
The MCF548x GPIO module does not generate interrupt requests.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-33
MCF548x Reference Manual, Rev. 3
15-34
Freescale Semiconductor
Part III
On-Chip Integration
Part III describes on-chip integration for the MCF548x device. It includes descriptions of the system
SRAM, SDRAM controller, PCI, FlexBus interface, FlexCAN, SEC cryptography accelerator, and JTAG.
Contents
Part III contains the following chapters:
• Chapter 16, “32-Kbyte System SRAM,” describes the MCF548x on-chip system SRAM
implementation. It covers general operations, configuration, and initialization.
• Chapter 17, “FlexBus,” describes data transfer operations, error conditions, and reset operations.
It describes transfers initiated by the MCF548x and by an external master, and includes detailed
timing diagrams showing the interaction of signals in supported bus operations.
• Chapter 18, “SDRAM Controller (SDRAMC),” describes configuration and operation of the
synchronous DRAM controller component of the SIU. It includes a description of signals involved
in DRAM operations, including chip select signals and their address, mask, and control registers.
• Chapter 19, “PCI Bus Controller,” details the operation of the PCI bus controller for the MCF548x.
• Chapter 20, “PCI Bus Arbiter Module,” describes the MCF548x PCI bus arbiter module, including
timing for request and grant handshaking, the arbitration process, and the register in the PCI bus
arbiter programing model.
• Chapter 21, “FlexCAN,” describes the MCF548x implementation of the controller area network
(CAN) protocol. This chapter describes FlexCAN module operation and provides a programming
model.
• Chapter 22, “Integrated Security Engine (SEC),” provides an overview of the MCF548x security
encryption controller.
• Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the
MCF548x JTAG test implementation. It describes the use of JTAG instructions and provides
information on how to disable JTAG functionality.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
i
MCF548x Reference Manual, Rev. 3
ii
Freescale Semiconductor
Chapter 16
32-Kbyte System SRAM
16.1
Introduction
This chapter explains the operation of the MCF548x 32-Kbyte system SRAM.
16.1.1
Block Diagram
The system SRAM is organized as four 8-Kbyte banks, each organized as 2048 × 32-bits. The four banks
occupy a contiguous block of memory but can be optionally interleaved on long-word boundaries. When
configured for interleaved access, each bank contains the data for long word address modulo {bank #} (e.g.
bank 2 contains data for all long word address modulo 2 locations). Figure 16-1 shows the SRAM
organization in both linear and interleaved modes.
Byte Address
Byte Address
Long Word 0
Long Word 1
Long Word 2
.
.
.
0x1_0000
0x1_0004
0x1_0008
.
.
.
0x1_1FFC
0x1_2000
0x1_2004
0x1_2008
.
.
.
0x1_3FFC
0x1_4000
0x1_4004
0x1_4008
.
.
.
0x1_5FFC
0x1_6000
0x1_6004
0x1_6008
.
.
.
0x1_7FFC
Long Word 2047
Long Word 2048
Long Word 2049
Long Word 2050
.
.
.
Long Word 4095
Long Word 4096
Long Word 4097
Long Word 4098
.
.
.
Long Word 6143
Long Word 6144
Long Word 6145
Long Word 6146
.
.
.
Long Word 8191
Linear Organization
Long Word 0
Long Word 4
Long Word 8
.
.
.
0x1_0000
Bank 0
Bank 1
Bank 2
Bank 3
0x1_0010
0x1_0020
.
.
.
0x1_7FF0
0x1_0004
Long Word 8188
Long Word 1
Long Word 5
Long Word 9
.
.
.
0x1_0014
0x1_0024
.
.
.
0x1_7FF4
0x1_0008
Long Word 8189
Long Word 2
Long Word 6
Long Word 10
.
.
.
0x1_0018
0x1_0028
.
.
.
0x1_7FF8
0x1_000C
Long Word 8190
Long Word 3
Long Word 7
Long Word 11
.
.
.
0x1_001C
0x1_002C
.
.
.
0x1_7FFC
Bank 0
Bank 1
Bank 2
Bank 3
Long Word 8191
Interleaved Organization
Figure 16-1. SRAM Organization
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
16-1
The system SRAM contents always reside at MBAR + 0x0001 0000; therefore, it can be relocated by
changing the MBAR contents.
16.1.2
Features
The 32-Kbyte system SRAM is intended primarily as a fast scratch memory and data buffer for DMA and
SEC processing, and as memory accessed through the shared bus by all system masters. The module
features are the following:
• Four 8-Kbyte banks, each organized as 2048 × 32-bits
• Dedicated 32-bit data bus per bank
• Optionally interleaved along long-word boundaries under software control
• Single cycle access when accessed by the DMA
• Byte, word, and longword addressing capabilities
• Independent arbitration mechanism per bank
16.1.3
Overview
This module provides a general-purpose memory block that can be accessed by the masters in the system
(ColdFire core, SEC, DMA, and PCI) via the shared internal system bus. The SRAM is also accessed
directly (without going through the system bus) by the SEC and DMA. This allows a mechanism for the
sharing of parameter data among the various masters as well as a dedicated fast scratch memory and data
buffer for DMA and SEC processing tasks.
In order to maximize concurrent utilization, the system SRAM is organized as four banks. Each master is
allocated a maximum transfer count and must give up access to the bank when its transfer count has been
depleted. In this fashion, each master is given the opportunity to access each bank to prevent starvation of
any given master. The transfer counts are configurable under software control for each master and each
bank, so it can be optimized to maximize the SRAM utilization for specific tasks. Optionally, a master can
be set to “own” a bank, whereby all other masters can access the bank only when the “own” master is not
making accesses to the bank.
16.2
Memory Map/Register Definition
Table 16-1 shows the memory map of the system SRAM module. For more information about a particular
register, refer to the description of the register in the following sections.
Table 16-1. System SRAM Memory Map
Address
(MBAR + )
Name
Byte 0
Byte 1
Byte 2
Byte 3
Access
0x1_0000–
0x1_7FFC
SRAM Contents
R/W
0x1_FFC0
System SRAM Configuration Register
SSCR
R/W
0x1_FFC4
Transfer Count Configuration Register
TCCR
R/W
0x1_FFC8
Transfer Count Configuration Register - DMA
Read Channel
TCCRDR
R/W
MCF548x Reference Manual, Rev. 3
16-2
Freescale Semiconductor
Memory Map/Register Definition
Table 16-1. System SRAM Memory Map (Continued)
Address
(MBAR + )
Name
Byte 0
Byte 1
Byte 2
Byte 3
Access
0x1_0000–
0x1_7FFC
SRAM Contents
0x1_FFCC
Transfer Count Configuration Register - DMA
Write Channel
TCCRDW
R/W
0x1_FFD0
Transfer Count Configuration Register - SEC
TCCRSEC
R/W
16.2.1
R/W
System SRAM Configuration Register (SSCR)
This register is used to define the base address of the system SRAM and whether to interleave the banks.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INLV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Reg
Addr
MBAR + 0x1_FFC0
Figure 16-2. System SRAM Configuration Register (SSCR)
Each field is described in Table 16-2.
Table 16-2. SSCR Register Field Descriptions
Bits
Name
31–17
—
16
INLV
15–0
—
Description
Reserved, should be cleared.
Interleave enable. Controls whether the banks are interleaved along longword boundaries or linear.
0 The four SRAM banks are not interleaved (linear).
1 The four SRAM banks are interleaved. SRAM bank # contains data for long word address modulo
{bank #}
Reserved. Should be cleared.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
16-3
16.2.2
Transfer Count Configuration Register (TCCR)
This register is used to configure the allocated maximum transfer count for each bank for the following
masters: the ColdFire core, DMA, SEC, or PCI. This occurs as they access memory through the shared
system bus. The DMA and the SEC can access the system SRAM either via the system bus or via their
dedicated ports. Refer to sections 16.2.3 through 16.2.5.
31
30
29
28
0
0
0
0
0
0
0
0
1
1
1
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
R
27
26
25
24
23
22
21
20
0
0
0
0
1
0
0
0
0
1
1
1
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BANK3_TC
19
18
17
16
BANK2_TC
W
Reset
R
BANK1_TC
BANK0_TC
W
Reset
1
1
Reg
Addr
1
1
1
1
1
1
MBAR + 0x1_FFC4
Figure 16-3. Transfer Count Configuration Register (TCCR)
Each field is described in the Table 16-3.
Table 16-3. TCCR Register Field Descriptions
Bits
Name
31–28
—
27–24
23–20
19–16
15–12
11–8
7–4
3–0
Description
Reserved, should be cleared.
BANK3_TC Bank three transfer count. This field indicates the maximum transfer count for bank 3. The master
can make at most 4 * {field value} 32-bit transfers to/from bank 3 before it must wait for other
masters to complete their transfers. If this field is programmed to “0” the master can “own” bank 3
for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK2_TC Bank two transfer count. This field indicates the maximum transfer count for bank 2. The master
can make at most 4 * {field value} 32-bit transfers to/from bank 2 before it must wait for other
masters to complete their transfers. If this field is programmed to “0” the master can “own” bank 2
for arbitrarily long transfers.
—
Reserved. Should be cleared.
BANK1_TC Bank one transfer count. This field indicates the maximum transfer count for bank 1. The master
can make at most 4 * {field value} 32-bit transfers to/from bank 1 before it must wait for other
masters to complete their transfers. If this field is programmed to “0” the master can “own” bank 1
for arbitrarily long transfers.
—
Reserved. Should be cleared.
BANK0_TC Bank zero transfer count. This field indicates the maximum transfer count for bank 0. The master
can make at most 4 * {field value} 32-bit transfers to/from bank 0 before it must wait for other
masters to complete their transfers. If this field is programmed to “0” the master can “own” bank 0
for arbitrarily long transfers.
MCF548x Reference Manual, Rev. 3
16-4
Freescale Semiconductor
Memory Map/Register Definition
16.2.3
Transfer Count Configuration Register—DMA Read Channel
(TCCRDR)
This register is used to configure the allocated maximum transfer count for each bank for the DMA read
channel as it accesses SRAM directly, without going through the system bus.
R
31
30
29
28
27
26
25
0
0
0
0
0
0
0
0
1
1
1
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
24
23
22
21
20
0
0
0
0
1
0
0
0
0
1
1
1
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BANK3_TC
19
18
17
16
BANK2_TC
W
Reset
R
BANK1_TC
BANK0_TC
W
Reset
1
1
Reg
Addr
1
1
1
1
1
1
MBAR + 0x1_FFC8
Figure 16-4. Transfer Count Configuration Register—DMA Read Channel (TCCRDR)
Each field is described in the table below.
Table 16-4. TCCRDR Register Field Descriptions
Bits
Name
31–28
—
27–24
23–20
19–16
15–12
11–8
7–4
3–0
Description
Reserved, should be cleared.
BANK3_TC Bank three transfer count. This field indicates the maximum transfer count for bank 3. The DMA
read channel can make at most 4 * {field value} 32-bit transfers from bank 3 before it must wait for
other masters to complete their transfers. If this field is programmed to “0” the DMA read channel
can “own” bank 3 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK2_TC Bank two transfer count. This field indicates the maximum transfer count for bank 2. The DMA read
channel can make at most 4 * {field value} 32-bit transfers from bank 2 before it must wait for other
masters to complete their transfers. If this field is programmed to “0” the DMA read channel can
“own” bank 2 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK1_TC Bank one transfer count. This field indicates the maximum transfer count for bank 1. The DMA read
channel can make at most 4 * {field value} 32-bit transfers from bank 1 before it must wait for other
masters to complete their transfers. If this field is programmed to “0” the DMA read channel can
“own” bank 1 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK0_TC Bank zero transfer count. This field indicates the maximum transfer count for bank 0. The DMA read
channel can make at most 4 * {field value} 32-bit transfers from bank 0 before it must wait for other
masters to complete their transfers. If this field is programmed to “0” the DMA read channel can
“own” bank 0 for arbitrarily long transfers.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
16-5
16.2.4
Transfer Count Configuration Register—DMA Write Channel
(TCCRDW)
This register is used to configure the allocated maximum transfer count for each bank of the DMA write
channel as it accesses SRAM directly, without going through the system bus.
R
31
30
29
28
27
26
25
0
0
0
0
0
0
0
0
1
1
1
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
24
23
22
21
20
0
0
0
0
1
0
0
0
0
1
1
1
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BANK3_TC
19
18
17
16
BANK2_TC
W
Reset
R
BANK1_TC
BANK0_TC
W
Reset
1
1
Reg
Addr
1
1
1
1
1
1
MBAR + 0x1_FFCC
Figure 16-5. Transfer Count Configuration Register—DMA Write Channel (TCCRDW)
Each field is described in the table below.
Table 16-5. TCCRDW Register Field Descriptions
Bits
Name
31–28
—
27–24
23–20
19–16
15–12
11–8
7–4
3–0
Description
Reserved, should be cleared.
BANK3_TC Bank three transfer count. This field indicates the maximum transfer count for bank 3. The
DMA write channel can make at most 4 * {field value} 32-bit transfers to bank 3 before it
must wait for other masters to complete their transfers. If this field is programmed to “0” the
DMA write channel can “own” bank 3 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK2_TC Bank two transfer count. This field indicates the maximum transfer count for bank 2. The
DMA write channel can make at most 4 * {field value} 32-bit transfers to bank 2 before it
must wait for other masters to complete their transfers. If this field is programmed to “0” the
DMA write channel can “own” bank 2 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK1_TC Bank one transfer count. This field indicates the maximum transfer count for bank 1. The
DMA write channel can make at most 4 * {field value} 32-bit transfers to bank 1 before it
must wait for other masters to complete their transfers. If this field is programmed to “0” the
DMA write channel can “own” bank 1 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK0_TC Bank zero transfer count. This field indicates the maximum transfer count for bank 0. The
DMA write channel can make at most 4 * {field value} 32-bit transfers to bank 0 before it
must wait for other masters to complete their transfers. If this field is programmed to “0” the
DMA write channel can “own” bank 0 for arbitrarily long transfers.
MCF548x Reference Manual, Rev. 3
16-6
Freescale Semiconductor
Memory Map/Register Definition
16.2.5
Transfer Count Configuration Register—SEC (TCCRSEC)
This register is used to configure the allocated maximum transfer count for each bank for the SEC as it
accesses SRAM directly, without going through the system bus.
R
31
30
29
28
27
26
25
0
0
0
0
0
0
0
0
1
1
1
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
24
23
22
21
20
0
0
0
0
1
0
0
0
0
1
1
1
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BANK3_TC
19
18
17
16
BANK2_TC
W
Reset
R
BANK1_TC
BANK0_TC
W
Reset
1
1
Reg
Addr
1
1
1
1
1
1
MBAR + 0x1_FFD0
Figure 16-6. Transfer Count Configuration Register—SEC (TCCRSEC))
Each field is described in the table below.
Table 16-6. TCCRSEC Register Field Descriptions
Bits
Name
31–28
—
27–24
23–20
19–16
15–12
11–8
7–4
3–0
Description
Reserved, should be cleared.
BANK3_TC Bank three transfer count. This field indicates the maximum transfer count for bank 3. The
SEC can make at most 4 * {field value} 32-bit transfers to/from bank 3 before it must wait
for other masters to complete their transfers. If this field is programmed to “0” the SEC can
“own” bank 3 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK2_TC Bank two transfer count. This field indicates the maximum transfer count for bank 2. The
SEC can make at most 4 * {field value} 32-bit transfers to/from bank 2 before it must wait
for other masters to complete their transfers. If this field is programmed to “0” the SEC can
“own” bank 2 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK1_TC Bank one transfer count. This field indicates the maximum transfer count for bank 1. The
SEC can make at most 4 * {field value} 32-bit transfers to/from bank 1 before it must wait
for other masters to complete their transfers. If this field is programmed to “0” the SEC can
“own” bank 1 for arbitrarily long transfers.
—
Reserved, should be cleared.
BANK0_TC Bank zero transfer count. This field indicates the maximum transfer count for bank 0. The
SEC can make at most 4 * {field value} 32-bit transfers to/from bank 0 before it must wait
for other masters to complete their transfers. If this field is programmed to “0” the SEC can
“own” bank 0 for arbitrarily long transfers.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
16-7
16.3
Functional Description
The system SRAM decodes the addresses for all four banks to determine which master is trying to access
which bank. The system SRAM module provides a bus arbitration mechanism for granting access of each
bank to each master. All masters simply request a data transfer and the SRAM grants a specified cycle
count to the appropriate master. The arbitration is overlapped with the address phase of SRAM transfers
and therefore imposes no performance penalty or overhead.
The current master pointer for each bank is determined as shown in Figure 16-7. The current master
pointer transitions to another master when the current master’s maximum transfer count is exceeded, or
the current master is idle and another master requests access to the bank. Otherwise, the current master
pointer remains unchanged.
RE
S
(Ba ET
nk 0
)
ET
RES 1)
k
(Ban
Master
DMA-R
SEC
DMA-W
SET
RE
)
nk 3
(Ba
RES
E
(Ban T
k 2)
Figure 16-7. SRAM Arbitration
MCF548x Reference Manual, Rev. 3
16-8
Freescale Semiconductor
Chapter 17
FlexBus
17.1
Introduction
This chapter describes data transfer operations, error conditions, and reset operations. It describes transfers
initiated by the MCF548x and includes detailed timing diagrams showing the interaction of signals in
supported bus operations.
NOTE
Unless otherwise noted, in this chapter the term ‘clock’ refers to the CLKIN
used for the bus.
17.1.1
Overview
A multi-function external bus interface called the FlexBus interface controller is provided on the
MCF548x with basic functionality of interfacing to slave-only devices up to a maximum bus frequency of
66 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot
ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
The FlexBus interface has six general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be
dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32
bits) wide. Control signal timing is compatible with common ROM / flash memories.
17.1.2
Features
The following list summarizes the key FlexBus features:
• Six independent, user-programmable chip-select signals (FBCS[5:0]) that can interface with
SRAM, PROM, EPROM, EEPROM, Flash, and other peripherals
• 8-, 16-, and 32-bit port sizes with configuration for multiplexed or non-multiplexed address and
data buses
• Byte, word, and longword, and line sized transfers
• Programmable burst and burst-inhibited transfers selectable for each chip select and transfer
direction
• Programmable address setup time with respect to the assertion of chip select
• Programmable address hold time with respect to the negation of chip select and transfer direction
17.1.3
Modes of Operation
The FlexBus interface is a configurable multiplexed bus that is set to one of four modes:
• Multiplexed 32-bit address and 32-bit data
• Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16-bit data)
• Multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit data)
• Non-multiplexed 32-bit address with 32-bit data
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-1
17.2
Byte Lanes
Figure 17-1 shows the byte lanes that external memory should be connected to and the sequential transfers
if a longword is transferred for three port sizes. For example, an 8-bit memory should be connected to
AD[31:24] (BE/BWE0). A longword transfer takes four transfers on AD[31:24], starting with the MSB
and going to the LSB.
Byte Select
Processor
External
Data Bus
BE/BWE0
BE/BWE1
BE/BWE2
BE/BWE3
AD[31:24]
AD[23:16]
AD[15:8]
AD[7:0]
32-Bit Port
Memory
Byte 0
Byte 1
16-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
8-Bit Port
Memory
Byte 2
Byte 3
Driven with
address values
Byte 0
Byte 1
Byte 2
Driven with
address values
Byte 3
Figure 17-1. Connections for External Memory Port Sizes
17.3
Address Latch
Because the FlexBus uses a multiplexed address and data bus, external logic might be needed in some
cases to capture the address phase as shown in Figure 17-2.
MCF548x Reference Manual, Rev. 3
17-2
Freescale Semiconductor
External Signals
External Device / Peripheral
DATA[31:Y]
AD[31:0]
FlexBus
Address
ADDR[X:0]
Latch
Logic
ALE
Interface
ALE
Controller
R/W
R/W
TSIZ[1:0]
SIZ[1:0]
TBST
BURST
BE/BWE[3:0]
BE/BWE[3:0]
OE
OE
TA
TA
FBCSx
CS
Figure 17-2. Multiplexed FlexBus Implementation
17.4
External Signals
This section describes the external signals that are involved in data transfer operations. Table 17-1
summarizes the MCF548x FlexBus signals.
Table 17-1. FlexBus Signal Summary
Signal Name
Direction
Description
Reset State
FBCS[5:0]
O
General purpose chip-selects
Hi-Z
AD[31:0]
I/O
Address / Data bus
Hi-Z
ALE
O
Address Latch Enable
Hi-Z
BE/BWE[3:0]
O
Byte Selects
Hi-Z
OE
O
Output Enable
Hi-Z
R/W
O
Read/Write. 1 = Read, 0 = Write
Hi-Z
TBST
O
Burst Transfer indicator
Hi-Z
TSIZ[1:0]
O
Transfer Size
Hi-Z
TA
I
Transfer Acknowledge
—
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-3
17.4.1
Chip-Select (FBCS[5:0])
The chip-select signal indicates which device is being selected. A particular chip-select asserts when the
transfer address is within the device’s address space as defined in the base and mask address registers, see
Section 17.5.2, “Chip-Select Registers.”
17.4.2
Address/Data Bus (AD[31:0])
The AD[31:0] bus carries address and data. The full 32-bit address is always driven on the first clock of a
bus cycle (address phase). The number of byte lanes used to carry the data during the data phase is
determined by the port size associated with the matching chip select.
In non-multiplexed mode, it is divided into sub-buses: address (output) and data (input/output). In
multiplexed mode, it carries the address during the address phase and the data during the data phase. Note
that in multiplexed mode and during the data phase, the address continues driving on the lower byte lanes
if these lanes are not used to carry the data.
17.4.3
Address Latch Enable (ALE)
The assertion of ALE indicates that the MCF548x has begun a bus transaction and that the address and
attributes are valid. ALE is asserted for one bus clock cycle. In multiplexed bus mode, ALE is used
externally as an address latch enable to capture the address phase of the bus transfer, as shown in
Figure 17-2.
17.4.4
Read/Write (R/W)
MCF548x drives the R/W signal to indicate the direction of the current bus operation. It is driven high
during read bus cycles and driven low during write bus cycles.
17.4.5
Transfer Burst (TBST)
Transfer Burst indicates that a burst transfer is in progress as driven by the MCF548x. A burst transfer can
be 2 to 16 beats depending on TSIZ[1:0] and the port size.
NOTE
When burst (TBST = 0) and transfer size is 16 bytes (TSIZ = 2’b11) and the
address is misaligned within the 16-byte boundary, the external device must
be able to wrap around the address.
17.4.6
Transfer Size (TSIZ[1:0])
For memory accesses, these signals, along with TBST, indicate the data transfer size of the current bus
operation. The FlexBus interface supports byte, word, and longword operand transfers and allows accesses
to 8-, 16-, and 32-bit data ports.
For misaligned transfers, TSIZ[1:0] indicate the size of each transfer. For example, if a longword access
through a 32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first
(TSIZ[1:0] = 01), a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is
transferred at offset 0x4 (TSIZ[1:0] = 01).
MCF548x Reference Manual, Rev. 3
17-4
Freescale Semiconductor
External Signals
For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows:
• If bursting is used, TSIZ[1:0] is driven to the size of transfer.
• If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port
size.
Table 17-2. Data Transfer Size
TSIZ[1:0]
Transfer Size
00
4 bytes (longword)
01
1 byte
10
2 bytes (word)
11
16 bytes (line)
For burst-inhibited transfers, TSIZ[1:0] changes with each ALE assertion to reflect the next transfer size.
For transfers to port sizes smaller than the transfer size, TSIZ[1:0] indicates the size of the entire transfer
on the first access and the size of the current port transfer on subsequent transfers. For example, for a
longword write to an 8-bit port, TSIZ[1:0] = 2’b00 for the first transaction and 2’b01 for the next three
transactions. If bursting is used and in the case of longword write to an 8-bit port, TSIZ[1:0] is driven to
2’b00 for the entire transfer.
17.4.7
Byte Selects (BE/BWE[3:0])
The byte strobe (BE/BWE[3:0]) outputs indicate that data is to be latched or driven onto a byte of the data
when driven low as shown in Table 17-1. BE/BWEn signals are asserted only to the memory bytes used
during a read or write access.
17.4.8
Output Enable (OE)
The output enable signal (OE) is sent to the interfacing memory and/or peripheral to enable a read transfer.
OE is asserted only when a chip select matches the current address decode.
17.4.9
Transfer Acknowledge (TA)
This signal indicates that the external data transfer is complete. During a read cycle, when the processor
recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the
processor recognizes TA, the bus cycle is terminated.
If auto-acknowledge is disabled, the external device drives TA to terminate the bus transfer; if
auto-acknowledge is enabled, the TA is generated internally after a specified wait states or the external
device may assert external TA before the wait-state countdown, terminating the cycle early. The MCF548x
negates FBCSn a cycle after the last TA asserts. During read cycles, the peripheral must continue to drive
data until TA is recognized. For write cycles, the processor continues to drive data one clock after FBCSn
is negated.
The number of wait states is determined either by internally programmed auto acknowledgement or by the
external TA input. If the external TA is used, the peripheral has total control on the number of wait states.
NOTE
External devices should only assert TA while the FBCSn signal to the
external device is asserted.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-5
17.5
Chip-Select Operation
Each chip-select has a dedicated set of the following registers for configuration and control:
• Chip-select address registers (CSARn) control the base address space of the chip-select. See
Section 17.5.2.1, “Chip-Select Address Registers (CSAR0–CSAR5).”
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 17.5.2.2, “Chip-Select Mask Registers (CSMR0–CSMR5).”
• Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, address setup and hold times, and automatic acknowledge generation features. See
Section 17.5.2.3, “Chip-Select Control Registers (CSCR0–CSCR5).”
FBCS0 is a global chip-select after reset and provides re-locatable boot ROM capability.
17.5.1
General Chip-Select Operation
When a bus cycle is initiated, the MCF548x first compares its address with the base address and mask
configurations programmed for chip-selects 0–5 (configured in CSCR0–CSCR5). If the driven address
matches a programmed chip-select, the appropriate chip-select is asserted fulfilling the requirements as
programmed in the respective configuration register.
17.5.1.1
8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 17.5.2.3,
“Chip-Select Control Registers (CSCR0–CSCR5).” Note that the MCF548x always drives 32-bit address
on the AD bus in the first cycle regardless of the external device’s address size. The external device must
connect its address lines to the appropriate AD bits starting from AD0 and upward. It must also connect
its data lines to the AD bus starting from the AD31 and downward. No bit ordering is required when
connecting address and data lines to the AD bus. For example, a 16-bit address/16-bit data device would
connect its addr[15:0] to AD[15:0] and data[15:0] to AD[31:16]. See Figure 17-6 for graphical connection.
17.5.1.2
Global Chip-Select Operation
FBCS0, the global (boot) chip-select, allows address decoding for boot ROM before system initialization.
Its operation differs from other external chip-select outputs after system reset.
After system reset, FBCS0 is asserted for every external access. No other chip-select can be used until the
valid bit, CSMR0[V], is set, at which point FBCS0 functions as configured. After this, FBCS[5:1] can be
used as well. At reset, the port size, and automatic acknowledge functions of the global chip-select are
determined by the logic levels on the AD[2:0] signals. Table 17-3, Table 17-4, and Table 17-5 list the
various reset encodings for the configuration signals.
Table 17-3. AD4/FB_CONFIG Selection of Non-Multiplexed
32-bit Address/32-bit Data Mode
AD4
1
FlexBus Operating Mode
0
AD[31:0] used for data.
PCIAD[31:0] used for address1
1
PCIAD[31:0] used for PCI bus.
AD[31:0] used for both address and data.
If the non-multiplexed 32-bit address/32-bit data mode is selected the PCI bus
cannot be used.
MCF548x Reference Manual, Rev. 3
17-6
Freescale Semiconductor
Chip-Select Operation
Table 17-4. AD[2]/AA Automatic Acknowledge of Boot FBCS0
AD[2]/AA
Boot FBCS0 AA Configuration at Reset
0
Disabled
1
Enabled with 63 wait states
Table 17-5. AD[1:0]/PS[1:0], Port Size of Boot FBCS0
17.5.2
AD[1:0]/PS[1:0]
Boot FBCS0 Port Size at Reset
00
32-bit port
01
8-bit port
1x
16-bit port
Chip-Select Registers
The following tables describe in detail the registers and bit meanings for configuring chip-select operation.
The chip-select controller register map is accessed relative to the memory base address register (MBAR).
Table 17-6 shows the chip-select register memory map. Reading unused or reserved locations terminates
normally and returns zeros.
Table 17-6. Chip-Select Registers
Register
Offset
[31:24]
[23:16]
[15:8]
[7:0]
ResetValue
Access 1
0x0500
Chip-select address register—bank 0 (CSAR0)
0x0000_0000
R/W
0x0504
Chip-select mask register—bank 0 (CSMR0)
0x0000_0000
R/W
0x0508
Chip-select control register—bank 0 (CSCR0)
BSTW = 0
BSTR = 0
PS = AD[1:0]
AA = AD[2]
WS = 111111
WRAH = 11
RDAH = 11
ASET = 11
SWSEN = 0
SWS = 000000
R/W
0x050C
Chip-select address register—bank 1 (CSAR1)
0x0000_0000
R/W
0x0510
Chip-select mask register—bank 1 (CSMR1)
0x0000_0000
R/W
0x054
Chip-select control register—bank 1 (CSCR1)
0x0000_0000
R/W
0x0518
Chip-select address register—bank 2 (CSAR2)
0x0000_0000
R/W
0x051C
Chip-select mask register—bank 2 (CSMR2)
0x0000_0000
R/W
0x0520
Chip-select control register—bank 2 (CSCR2)
0x0000_0000
R/W
0x0524
Chip-select address register—bank 3 (CSAR3)
0x0000_0000
R/W
0x0528
Chip-select mask register—bank 3 (CSMR3)
0x0000_0000
R/W
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-7
Table 17-6. Chip-Select Registers (Continued)
Register
Offset
[31:24]
[23:16]
[15:8]
[7:0]
ResetValue
Access 1
0x052C
Chip-select control register—bank 3 (CSCR3)
0x0000_0000
R/W
0x0530
Chip-select address register—bank 4 (CSAR4)
0x0000_0000
R/W
0x0534
Chip-select mask register—bank 4 (CSMR4)
0x0000_0000
R/W
0x0538
Chip-select control register—bank 4 (CSCR4)
0x0000_0000
R/W
0x053C
Chip-select address register—bank 5 (CSAR5)
0x0000_0000
R/W
0x0540
Chip-select mask register—bank 5 (CSMR5)
0x0000_0000
R/W
0x0544
Chip-select control register—bank 5 (CSCR5)
0x0000_0000
R/W
1 The access column indicates whether the corresponding register allows both read/write functionality (R/W), read-only
functionality (R), or write-only functionality (W). A read access to a write-only register returns zeros. A write access to a
read-only register has no effect.
2 Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved
address spaces and reserved register bits have no effect.
17.5.2.1
Chip-Select Address Registers (CSAR0–CSAR5)
CSARn, Figure 17-3, specify the chip-select base addresses.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
BA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
Reg
Addr
MBAR + 0x500 (CSAR0); 0x50C (CSAR1); 0x518 (CSAR2);
0x524 (CSAR3); 0x530 (CSAR4); 0x53C (CSAR5)
Figure 17-3. Chip-Select Address Registers (CSARn)
Table 17-7. CSARn Field Descriptions
Bits
Name
Description
31–16
BA
Base address. Defines the base address for memory dedicated to chip-select FBCSn. BA is
compared to bits 31–16 on the internal address bus to determine if chip-select memory is being
accessed.
15–0
—
Reserved, should be cleared
MCF548x Reference Manual, Rev. 3
17-8
Freescale Semiconductor
Chip-Select Operation
17.5.2.2
Chip-Select Mask Registers (CSMR0–CSMR5)
CSMRn, Figure 17-4, are used to specify the address mask and allowable access types for the respective
chip-selects.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
BAM
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
WP
0
0
0
0
0
0
0
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0x504 (CSMR0); 0x510 (CSMR1); 0x51C (CSMR2);
0x528 (CSMR3); 0x534 (CSMR4); 0xr540 (CSMR5)
Figure 17-4. Chip-Select Mask Registers (CSMRn)
Table 17-8 describes CSMR fields.
Table 17-8. CSMRn Field Descriptions
Bits
Name
Description
31–16
BAM
15–9
—
8
WP
7–1
—
Reserved, should be cleared
0
V
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid.
Programmed chip-selects do not assert until V bit is set (except for FBCS0, which acts as the global
chip-select). Reset clears each CSMRn[V]. At reset, no chip-select other than FBCS0 can be used
until the CSMR0[V] is set. At which point FBCS[5:0] functions as configured.
0 chip-select invalid
1 chip-select valid
Base address mask. Defines the chip-select block size by masking address bits. Setting a BAM bit
causes the corresponding CSAR bit to be a “don’t care” in the decode.
0 Corresponding address bit is used in chip-select decode.
1 Corresponding address bit is a don’t care in chip-select decode.
The block size for FBCSn is 2n; n = (number of bits set in respective CSMR[BAM]) + 16.
For example, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008, FBCS0 would address two
discontinuous 64-Kbyte memory blocks: one from 0x0000–0xFFFF and one from
0x8_0000–0x8_FFFF.
Likewise, for FBCS0 to access 32 Mbytes of address space starting at location 0x0, FBCS1 must
begin at the next byte after FBCS0 for a 16-Mbyte address space. Then CSAR0 = 0x0000,
CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and CSMR1[BAM] = 0x00FF.
Reserved, should be cleared
Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting
to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate chip-select not
being selected. No exception occurs.
0 Both read and write accesses are allowed
1 Only read accesses are allowed
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-9
17.5.2.3
Chip-Select Control Registers (CSCR0–CSCR5)
Each CSCRn, Figure 17-5, controls the auto acknowledge, address setup and hold times, port size, burst
capability, and activation of each chip-select. Note that to support the global chip-select, FBCS0, the
CSCR0 reset values differ from the other CSCRs. FBCS0 allows address decoding for boot ROM before
system initialization.
31
30
29
R
28
27
26
SWS
25
24
23
22
0
0
SWS
EN
—
W
21
20
19
ASET
18
RDAH
17
16
WRAH
Reset: CSCR0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Reset: CSCRs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
AA
PS
BEM BSTR BSTW
0
0
0
AD[1:0]
AD3
0
0
0
0
0
0
0
0
0
0
0
R
WS
W
Reset: CSCR0
1
1
1
1
1
1
0
AD2
Reset: CSCRs
0
0
0
0
0
0
0
0
Reg
Addr
0
0
MBAR + 0x508 (CSCR0); 0x514 (CSCR1); 0x520 (CSCR2);
0x52C (CSCR3); 0x538 (CSCR4); 0x544 (CSCR5)
Figure 17-5. Chip-Select Control Registers (CSCRn)
Table 17-9 describes CSCRn fields.
Table 17-9. CSCRn Field Descriptions
Bits
Name
Description
31–26
SWS
Secondary wait states. The number of wait states inserted before an internal transfer acknowledge
is generated for burst transfer except for the first termination, which is controlled by the wait state
count. The secondary wait state is only used if the secondary wait state enable is set, otherwise the
wait state value is used for all burst transfers.
25–24
—
23
SWSEN
22
—
21–20
ASET
Reserved, should be cleared
Secondary wait state enable. If set (SWSEN = 1), then the secondary wait state value is used to
insert wait states before an internal transfer acknowledge is generated for burst transfer secondary
terminations. If cleared (SWSEN = 0), then the wait state value is used to insert wait states before
an internal transfer acknowledge is generated for all transfers.
Reserved, should be cleared
Address setup. This field controls the asserting of chip-select with respect to assertion of a valid
address and attributes. Note that the address and attributes are considered valid at the same time
ALE asserts.
00 Assert chip-select on rising clock edge after address is asserted. (Default FBCSn)
01 Assert chip-select on second rising clock edge after address is asserted.
10 Assert chip-select on third rising clock edge after address is asserted.
11 Assert chip-select on fourth rising clock edge after address is asserted.(Reset FBCS0)
MCF548x Reference Manual, Rev. 3
17-10
Freescale Semiconductor
Chip-Select Operation
Table 17-9. CSCRn Field Descriptions (Continued)
Bits
Name
Description
19–18
RDAH
Read Address Hold or (Deselect). This field controls the address and attribute hold time after the
termination during a read cycle that hits in the chip-select address space. The hold time only applies
at the end of a transfer. Therefore, a burst transfer only has a hold time added after the last bus
cycle.
RDAH = 00; Hold address and attributes one cycle after FBCSn negates on reads. (Default FBCSn)
01 Hold address and attributes two cycles after FBCSn negates on reads.
10 Hold address and attributes three cycles after FBCSn negates on reads.
11 Hold address and attributes four cycles after FBCSn negates on reads. (Reset FBCS0)
17–16
WRAH
Write Address Hold or (Deselect). This field controls the address, data and attribute hold time after
the termination of a write cycle that hits in the chip-select address space.The hold time only applies
at the end of a transfer. Therefore, a burst transfer only has a hold time added after the last bus
cycle.
WRAH = 00; Hold address and attributes one cycle after FBCSn negates on writes. (Default
FBCSn)
01 Hold address and attributes two cycles after FBCSn negates on writes.
10 Hold address and attributes three cycles after FBCSn negates on writes.
11 Hold address and attributes four cycles after FBCSn negates on writes. (Reset FBCS0)
15–10
WS
Wait states. The number of wait states inserted after FBCSn asserts and before an internal transfer
acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states). If
AA = 0, TA must be asserted by the external system regardless of the number of wait states
generated. In that case, the external transfer acknowledge ends the cycle. An external TA
supersedes the generation of an internal TA.
9
—
Reserved, should be cleared.
8
AA
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for
accesses specified by the chip-select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding FBCSn and
the external system asserts an external TA before the wait-state countdown asserts the internal TA,
the cycle is terminated. Burst cycles increment the address bus between each internal termination.
7–6
PS
Port size. Specifies the width of the data port associated with each chip-select. It determines where
data is driven during write cycles and where data is sampled during read cycles.
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
5
BEM
Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that
must be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide
the appropriate mode of byte enable support in support of these SRAMs.
0 Neither BE or BWE is asserted for reads. BWE is generated for data write only.
1 BE is asserted for reads; BWE is asserted for writes.
4
BSTR
Burst read enable. Specifies whether burst reads are used for memory associated with each
FBCSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For
example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8and 16-bit ports and word reads from 8-bit ports.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-11
Table 17-9. CSCRn Field Descriptions (Continued)
Bits
Name
Description
3
BSTW
Burst write enable. Specifies whether burst writes are used for memory associated with each
FBCSn.
0 Break data larger than the specified port size into individual port-sized, non-burst writes. For
example, a longword write to an 8-bit port takes four byte writes.
1 Enables burst write of data larger than the specified port size, including longword writes to 8 and
16-bit ports and word writes to 8-bit ports.
2–0
—
17.6
17.6.1
Reserved, should be cleared.
Functional Description
Data Transfer Operation
Data transfers between the MCF548x and other devices involve the following signals:
• Address/data bus (AD[31:0])
• Control signals (ALE and TA)
• FBCSn
• OE
• BE/BWE[3:0]
• Attribute signals (R/W, TBST, TSIZ[1:0])
The address and write data (AD[31:0]), R/W, ALE, FBCSn, and all attribute signals change on the rising
edge of the clock. Read data is registered in the MCF548x on the rising edge of the clock.
The MCF548x FlexBus supports byte, word, and longword operand transfers and allows accesses to 8-,
16-, and 32-bit data ports.Transfer parameters such as address setup and hold, port size, the number of wait
states for the external device being accessed, automatic internal transfer termination enable or disable, and
burst enable or disable are programmed in the chip-select control registers (CSCRs), Section 17.5.2.3,
“Chip-Select Control Registers (CSCR0–CSCR5).”
17.6.2
Data Byte Alignment and Physical Connections
The MCF548x aligns data transfers in FlexBus byte lanes, the number of lanes depending on the width of
the data port. Figure 17-6 shows the byte lanes that external memory should be connected to and the
sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit memory should
be connected to the single lane AD[31:24]. A longword transfer through this 8-bit port takes four transfers
on AD[31:24], starting with the MSB and going to the LSB. A longword transfer through a 32-bit port
requires one transfer on each of the four byte lanes of the FlexBus.
MCF548x Reference Manual, Rev. 3
17-12
Freescale Semiconductor
Functional Description
Byte Select
BE/BWE0
BE/BWE1
BE/BWE2
BE/BWE3
Processor
External
Data Bus
AD[31:24]
AD[23:16]
AD[15:8]
AD[7:0]
32-Bit Port
Memory
Byte 0
Byte 1
16-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
8-Bit Port
Memory
Byte 2
Byte 3
Driven with
address values
Byte 0
Byte 1
Driven with
address values
Byte 2
Byte 3
Figure 17-6. Connections for External Memory Port Sizes
17.6.3
Address/Data Bus Multiplexing
The MCF548x FlexBus uses a 32-bit wide multiplexed address and data bus (AD[31:0]). The full 32-bit
address will always be driven on the first clock of a bus cycle. During the data phase, which AD[31:0] lines
are used for data is determined by the programmed port size for the corresponding chip select. The
MCF548x continues to drive the address on any AD[31:0] lines that are not used for data.
Table 17-10 lists the supported combinations of address and data bus widths.
Table 17-10. FlexBus Operating Modes
Port Size
Address Signals During
Address Phase
Data Signals During
Data Phase
Address Signals During
Data Phase
32-bit1
AD[31:0]
AD[31:0]
--
16-bit
AD[31:0]
AD[31:16]
AD[15:0]
8-bit
AD[31:0]
AD[31:24]
AD[23:0]
1
17.6.4
The 32-bit Address/32-bit Data non-multiplexed mode uses the PCI address/data bus to
provide a second 32-bit bus for the address. PCI cannot be used if this mode is selected.
Bus Cycle Execution
As shown in Figure 17-9 and Figure 17-11, basic bus operations occur in four clocks, as follows:
1. At the first clock edge, the address, attributes, and ALE are driven.
2. FBCSn is asserted at the second rising clock edge to indicate which device has been selected and
by that time the address and attributes are valid and stable. ALE is negated at this edge.
For a write transfer, data is driven on the bus at this clock edge and continues to be driven until one
clock cycle after FBCSn negates. For a read transfer, data is also returned at this cycle.
External slave asserts TA at this clock edge.
3. Read data and TA are sampled on the third clock edge. TA can be negated after this edge and read
data can then be tristated.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-13
4. FBCSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would
be an idle clock between cycles to provide hold time for address, attributes, and write data.
17.6.4.1
Data Transfer Cycle States
The data transfer operation in the MCF548x is controlled by an on-chip state machine. The state transition
diagram for basic read and write cycles is shown in Figure 17-7.
Next Cycle
S0
Wait States
S3
S1
S2
Figure 17-7. Data Transfer State Transition Diagram
Table 17-11 describes the states as they appear in subsequent timing diagrams.
Table 17-11. Bus Cycle States
State
Cycle
Description
S0
All
The read or write cycle is initiated. On the rising clock edge, the MCF548x places a valid address
on AD[31:0], asserts ALE, and drives R/W high for a read and low for a write, if these signals are
not already in the appropriate state.
S1
All
ALE is negated on the rising edge of CLK, and FBCSn is asserted. Data is driven on AD[31:Y] for
writes, and AD[31:Y] is three-stated for reads. Address continues to be driven on AD[X:0] pins that
are unused for data.
If TA is recognized asserted, then the cycle moves on to S2. If TA is not asserted either internally
or externally, then the S1 state continues to repeat.
S2
Read
Data is made available by the external device before the rising edge of CLK with TA asserted. The
the MCF548x will latch data on this rising clock edge.
All
For internal termination, both the FBCSn and internal TA will be negated. For external termination,
the external device should negate TA, and FBCSn select is negated after the rising edge of CLK at
the end of S2.
Read
S3
All
The external device can stop driving data after the rising edge of CLK at the beginning of S2.
However, data can be driven until the end of S3 or any additional address hold cycles.
Address, data, and R/W go invalid off the rising edge of CLK at the end of S3, terminating the read
or write cycle.
MCF548x Reference Manual, Rev. 3
17-14
Freescale Semiconductor
Functional Description
17.6.5
17.6.5.1
FlexBus Timing Examples
Basic Read Bus Cycle
During a read cycle, the MCF548x receives data from memory or from a peripheral device. Figure 17-8 is
a read cycle flowchart.
NOTE
Throughout this chapter AD[X:0] is used to indicate an address bus that can
be 32-, 24-, or 16-bits in width. AD[31:Y] is a data bus that can be 32-, 16-,
or 8-bits wide.
MCF548X
System
1. Set R/W to read.
2. Place address on AD[31:0].
3. Assert ALE.
1. Decode address.
1. Negate ALE.
2. Assert FBCSn.
1. CS unit asserts internal TA (auto
acknowledge/internal termination).
2. Sample TA low and latch data.
1. Select the appropriate slave device.
2. Drive data on AD[31:Y].
3. Assert TA (external termination).
1. Start next cycle.
1. Negate TA (external termination).
Figure 17-8. Read Cycle Flowchart
The read cycle timing diagram is shown in Figure 17-9.
NOTE
In the following timing diagrams, the dotted lines indicate TA, OE, and
FBCSn timing when internal termination is used (CSCR[AA] = 1). The
external and internal TA assert at the same time; however, TA is not driven
externally for internally terminated bus cycles.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-15
S0
S1
S2
S3
CLK
ADDR[X:0]
AD[X:0]
A[31:Y]
AD[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-9. Basic Read Bus Cycle
17.6.5.2
Basic Write Bus Cycle
During a write cycle, the MCF548x sends data to memory or to a peripheral device. The write cycle
flowchart is shown in Figure 17-10.
NOTE
Throughout this chapter AD[X:0] is used to indicate an address bus that can
be 32-, 24-, or 16-bits in width. AD[31:Y] is a data bus that can be 32-, 16-,
or 8-bits wide.
MCF548X
System
1. Set R/W to write.
2. Place address on AD[31:0].
3. Assert ALE.
1. Decode address.
1. Negate ALE.
2. Assert FBCSn.
1. CS unit asserts internal TA (auto
acknowledge/internal termination).
2. Sample TA low.
1. Select the appropriate slave device.
2. Drive data on AD[31:Y].
3. Assert TA (external termination).
1. Start next cycle.
1. Negate TA (external termination).
Figure 17-10. Write Cycle Flowchart
MCF548x Reference Manual, Rev. 3
17-16
Freescale Semiconductor
Functional Description
The write cycle timing diagram is shown in Figure 17-11.
S0
S1
S2
S3
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-11. Basic Write Bus Cycle
17.6.5.3
Bus Cycle Multiplexing
This section shows timing diagrams for various port size scenarios. Figure 17-12 illustrates the basic word
read transfer to a 16-bit device with no wait states. The address is driven on the full AD[31:0] bus in the
first clock. The MCF548x tristates AD[31:16] on the second clock and continues to drive address on
AD[15:0] throughout the bus cycle. The external device returns the read data on AD[31:16] and may
tristate the data line or continue to drive the data one clock after TA is sampled asserted.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-17
S0
S1
S2
S3
CLK
AD[31:24]
A[31:24]
D[15:8]
AD[23:16]
A[23:16]
D[7:0]
AD[15:8]
ADDR[15:8]
AD[7:0]
ADDR[7:0]
R/W
ALE
10
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-12. Single Word Read Transfer with Muxed 32-A / 16-D
or Non-Muxed 16-A / 16-D
Figure 17-13 shows the similar configuration for a write transfer. The data is driven from the second clock
on AD[31:16].
S0
S1
S2
S3
CLK
AD[31:24]
A[31:24]
DATA[15:8]
AD[23:16]
A[23:16]
DATA[7:0]
AD[15:8]
ADDR[15:8]
AD[7:0]
ADDR[7:0]
R/W
ALE
TSIZ[1:0]
10
FBCSn, BE/BWEn
OE
TA
Figure 17-13. Single Word Write Transfer with Muxed 32-A / 16-D
or Non-Muxed 16-A / 16-D
MCF548x Reference Manual, Rev. 3
17-18
Freescale Semiconductor
Functional Description
Figure 17-14 illustrates the basic byte read transfer to an 8-bit device with no wait states. The address is
driven on the full AD[31:0] bus in the first clock. The MCF548x tristates AD[31:24] on the second clock
and continues to drive address on AD[23:0] throughout the bus cycle. The external device returns the read
data on AD[31:24], and may tristate the data line or continue to drive the data one clock after TA is sampled
asserted.
S0
S1
S2
S3
CLK
AD[31:24]
A[31:24]
D[7:0]
AD[23:16]
ADDR[23:16]
AD[15:8]
ADDR[15:8]
AD[7:0]
ADDR[7:0]
R/W
ALE
TSIZ[1:0]
01
FBCSn, BE/BWEn
OE
TA
Figure 17-14. Single Byte Read Transfer with Muxed 32-A / 8-D
or Non-Muxed 24-A / 8-D
Figure 17-15 shows the similar configuration for a write transfer. The data is driven from the second clock
on AD[31:24].
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-19
S0
S1
S2
S3
CLK
AD[31:24]
A[31:24]
DATA[7:0]
AD[23:16]
ADDR[23:16]
AD[15:8]
ADDR[15:8]
AD[7:0]
ADDR[7:0]
R/W
ALE
01
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-15. Single Byte Write Transfer with Muxed 32-A / 8-D
or Non-Muxed 24-A / 8-D
Figure 17-16 depicts a longword read through a 32-bit device. Notice that when the device port size is 32
bits, the only mode the bus supports is multiplexing address and data lines.
S0
S1
S2
S3
CLK
AD[31:24]
A[31:24]
D[31:24]
AD[23:16]
A[23:16]
D[23:16]
AD[15:8]
A[15:8]
D[15:8]
AD[7:0]
A[7:0]
D[7:0]
R/W
ALE
TSIZ[1:0]
00
FBCSn, BE/BWEn
OE
TA
Figure 17-16. Longword Read Transfer with Muxed 32-A / 32-D
MCF548x Reference Manual, Rev. 3
17-20
Freescale Semiconductor
Functional Description
Figure 17-17 illustrates the longword write to a 32-bit device.
S0
S1
S2
S3
CLK
AD[31:24]
A[31:24]
DATA[31:24]
AD[23:16]
A[23:16]
DATA[23:16]
AD[15:8]
A[15:8]
DATA[15:8]
AD[7:0]
A[7:0]
DATA[7:0]
R/W
ALE
TSIZ[1:0]
00
FBCSn, BE/BWEn
OE
TA
Figure 17-17. Longword Write Transfer with Muxed 32-A / 32-D
17.6.5.4
Timing Variations
The MCF548x has several features that can be used to change the timing characteristics of a basic read or
write bus cycle to provide additional address setup, address hold, and time for a device to provide or latch
data.
17.6.5.4.1
Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states
can be used to give the peripheral or memory more time to return read data or sample write data.
Figure 17-18 and Figure 17-19 show the basic read and write bus cycles (also shown in Figure 17-9 and
Figure 17-11). This is the default case with no wait states.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-21
S0
S1
S2
S3
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-18. Basic Read Bus Cycle (No Wait States)
S0
S1
S2
S3
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-19. Basic Write Bus Cycle (No Wait States)
If wait states are used, then the S1 state will repeat continuously until either the internal TA is asserted by
the chip select auto-acknowledge unit or the external TA is recognized as asserted. Figure 17-20 and
Figure 17-21 show a read and write cycle with one wait state.
MCF548x Reference Manual, Rev. 3
17-22
Freescale Semiconductor
Functional Description
S0
S1
WS
S2
S3
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-20. Read Bus Cycle (One Wait State)
S0
S1
WS
S2
S3
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-21. Write Bus Cycle (One Wait State)
17.6.5.4.2
Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output enable can be
programmed on a chip select basis. Each chip select can be programmed to assert one to four clocks after
address latch enable (ALE) is asserted. Figure 17-22 and Figure 17-23 show read and write bus cycles with
two clocks of address setup.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-23
S0
AS
S1
S2
S3
CLK
ADDR[X:0]
AD[X:0]
A[31:Y]
AD[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-22. Read Bus Cycle with Two Clock Address Setup (No Wait States)
S0
AS
S1
S2
S3
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-23. Write Bus Cycle with Two Clock Address Setup (No Wait States)
In addition to address setup, there is also a programmable address hold option for each chip select. Address
and attributes can be held one to four clocks after chip select, byte selects, and output enable negate.
Figure 17-24 and Figure 17-25 show read and write bus cycles with two clocks of address hold.
MCF548x Reference Manual, Rev. 3
17-24
Freescale Semiconductor
Functional Description
S0
S1
S2
S3
AH
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-24. Read Cycle with Two Clock Address Hold (No Wait States)
S0
S1
S2
S3
AH
CLK
ADDR[X:0]
AD[X:0]
AD[31:Y]
A[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-25. Write Cycle with Two Clock Address Hold (No Wait States)
Figure 17-26 shows a bus cycle that uses address setup, wait states, and address hold.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-25
S0
AS
S1
WS
S2
S3
AH
CLK
ADDR[X:0]
AD[X:0]
A[31:Y]
AD[31:Y]
DATA
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
Figure 17-26. Write Cycle with Two Clock Address Setup and
Two Clock Hold (One Wait State)
17.6.6
Burst Cycles
The MCF548x can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it
is transferring to. The initiation of a burst cycle is encoded on the size pins. For burst transfers to smaller
port sizes, TSIZ[1:0] indicate the size of the entire transfer. For example, with bursting enabled, a word
transfer to an 8-bit port would take a 2-byte burst cycle, for which TSIZ[1:0] = 10 throughout. A longword
transfer to an 8-bit port would take a 4-byte burst cycle, for which TSIZ[1:0] = 00 throughout.
With bursting disabled, any transfer is larger than port size is broken into multiple individual transfers.
With bursting enabled, an access is larger than port size would result a burst cycle of multiple beats.
Table 17-12 shows the result of such transfer translations.
Table 17-12. Transfer Size and Port Size Translation
Port Size PS[1:0]
Transfer Size
TSIZ[1:0]
Burst-inhibited: number of transfers
Burst enabled: number of beats
01 (8-bit)
10 (word)
2
00 (longword)
4
11 (line)
16
00 (longword)
2
11 (line)
8
11 (line)
4
1- (16-bit)
00 (32-bit)
The MCF548x bus can support 3-1-1-1 burst cycles and optimize DMA transfers. A user can add wait
states by delaying termination of the cycle. If internal termination is used, different wait state counters can
be used for the first access and the following beats.
MCF548x Reference Manual, Rev. 3
17-26
Freescale Semiconductor
Functional Description
NOTE
Line-sized transfers requested by the core or cache are broken up into four
individual longword transfers, but the DMA can request line-sized transfers
when the read line or combine write flags are set. See Section 24.4.9, “Line
Buffers,” for more information.
CSCRs are used to enable bursting for reads, writes, or both. Memory spaces can be declared
burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW].
Figure 17-27 shows a longword read through an 8-bit device programmed for burst enable. The transfer
results in a 4-beat burst and the data is driven on AD[31:24]. Notice that the transfer size is driven at
longword (2’b00) throughout the bus cycle.
S0
S1
S2
S2
S2
S2
S3
CLK
ADDR[23:0]
AD[23:0]
AD[31:24]
A[31:24]
DATA
DATA
DATA
DATA
R/W
ALE
TSIZ[1:0]
00
FBCSn, BE/BWEn
TBST
OE
TA
Figure 17-27. Longword Read Burst from 8-Bit Port 3-1-1-1 (No Wait States)
Figure 17-28 shows a longword write through an 8-bit device programmed for burst enable. The transfer
results in a 4-beat burst and the data is driven on AD[31:24]. Notice that the transfer size is driven at
longword (2’b00) throughout the bus cycle.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-27
S0
S1
S2
S2
S2
S2
S3
CLK
ADDR[23:0]
AD[23:0]
AD[31:24]
A[31:24]
DATA
DATA
DATA
DATA
R/W
ALE
00
TSIZ[1:0]
FBCSn, BE/BWEn
TBST
OE
TA
Figure 17-28. Longword Write Burst to 8-Bit Port 3-1-1-1 (No Wait States)
Figure 17-29 shows a longword read through an 8-bit device with burst inhibited. The transfer results in
four individual transfers. Notice that the transfer size is driven at longword (2’b00) during the first transfer
and at byte (2’b01) during the next three transfers.
S0
S2
S1
S0
S1
S2
S0
S1
S2
S0
S2
S1
S3
CLK
ADDR[23:0]
AD[23:0]
AD[31:24]
A[31:24]
DATA
A[31:24]
DATA
A[31:24]
DATA
A[31:24]
DATA
DATA
R/W
ALE
TSIZ[1:0]
00
01
FBCSn, BE/BWEn
TBST
OE
TA
Figure 17-29. Longword Read Burst-Inhibited from 8-Bit Port (No Wait States)
MCF548x Reference Manual, Rev. 3
17-28
Freescale Semiconductor
Functional Description
Figure 17-30 shows a longword write through an 8-bit device with burst inhibited. The transfer results in
four individual transfers. Notice that the transfer size is driven at longword (2’b00) during the first transfer
and at byte (2’b01) during the next three transfers.
S1
S0
S2
S0
S1
S0
S2
S1
S2
S0
S2
S1
S3
CLK
ADDR[23:0]
AD[23:0]
AD[31:24]
A[31:24]
DATA
A[31:24]
DATA
A[31:24]
DATA
A[31:24]
DATA
R/W
ALE
01
00
TSIZ[1:0]
FBCSn, BE/BWEn
TBST
OE
TA
Figure 17-30. Longword Write Burst-Inhibited to 8-Bit Port (No Wait States)
Figure 17-31 illustrates another read burst transfer, but in this case a wait state is added between individual
beats.
S0
S1
WS
S2
WS/SWS
S2
WS/SWS
S2
WS/SWS
S2
S3
CLK
ADDR[23:0]
AD[23:0]
AD[31:24]
A[31:24]
DATA
DATA
DATA
DATA
R/W
ALE
TSIZ[1:0]
00
FBCSn, BE/BWEn
TBST
OE
TA
Figure 17-31. Longword Read Burst from 8-Bit Port 4-2-2-2 (One Wait State)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-29
Figure 17-31 illustrates a write burst transfer with one wait state.
S0
S1
WS
S2
WS/SWS
S2
WS/SWS
S2
WS/SWS
S2
S3
CLK
ADDR[23:0]
AD[23:0]
A[31:24]
AD[31:24]
DATA
DATA
DATA
DATA
R/W
ALE
00
TSIZ[1:0]
FBCSn, BE/BWEn
TBST
OE
TA
Figure 17-32. Longword Write Burst to 8-Bit Port 4-2-2-2 (One Wait State)
If address setup and hold are used, only the first and last beat of the burst cycle will be affected as shown
in Figure 17-33.
S0
AS
S1
S2
S2
S2
S2
S3
AH
CLK
ADDR[23:0]
AD[23:0]
AD[31:24]
A[31:24]
DATA
DATA
DATA
DATA
R/W
ALE
TSIZ[1:0]
11
FBCSn, BE/BWEn
OE
TBST
TA
Figure 17-33. Longword Read Burst from 8-Bit Port 4-1-1-1 (Address Setup and Hold)
Figure 17-34 shows a write cycle with one clock of address setup and address hold.
MCF548x Reference Manual, Rev. 3
17-30
Freescale Semiconductor
Functional Description
S0
AS
S1
S2
S2
S2
S2
S3
AH
CLK
AD[23:0]
AD[31:24]
ADDR[23:0]
A[31:24]
DATA
DATA
DATA
DATA
R/W
ALE
11
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TBST
TA
Figure 17-34. Longword Write Burst to 8-Bit Port 4-1-1-1 (Address Setup and Hold)
17.6.7
Misaligned Operands
Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned. A
byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a
longword is misaligned at an address not a multiple of four. Although the MCF548x enforces no alignment
restrictions for data operands (including program counter (PC) relative data addressing), additional bus
cycles are required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch
a misaligned instruction word causes an address error exception.
The MCF548x converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.
Figure 17-35 shows the transfer of a longword operand from a byte address to a 32-bit port. First a byte is
transferred at an offset of 0x1. The slave device supplies the byte and acknowledges the data transfer.
When the MCF548x starts the second cycle, a word is transferred with a byte offset of 0x2. The next two
bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the
port supplies the final byte, and the operation is complete.
31
24 23
16 15
8 7
0
A[2:0]
Transfer 1
––
Byte 0
––
––
001
Transfer 2
––
––
Byte 1
Byte 2
010
Transfer 3
Byte 3
––
––
––
100
Figure 17-35. Example of a Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the
cache. The example in Figure 17-36 differs from the one in Figure 17-35 because the operand is
word-sized and the transfer takes only two bus cycles.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
17-31
31
24 23
16 15
8 7
0
A[2:0]
Transfer 1
––
––
––
Byte 0
001
Transfer 2
Byte 0
––
––
—
100
Figure 17-36. Example of a Misaligned Word Transfer (32-Bit Port)
17.6.8
Bus Errors
The MCF548x has no bus monitor. If the auto-acknowledge feature is not enabled for the address that
generates the error, the bus cycle can be terminated by asserting TA or by using the software watchdog
timer. If it is required that the MCF548x handle a bus error differently, an interrupt handler can be invoked
by asserting an interrupt to the core along with TA when the bus error occurs.
MCF548x Reference Manual, Rev. 3
17-32
Freescale Semiconductor
Chapter 18
SDRAM Controller (SDRAMC)
18.1
Introduction
This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It
begins with a general overview and includes a description of signals involved in SDRAM operations. The
remainder of the chapter describes the programming model and signal timing, as well as the command set
required for synchronous DRAM operations. It also includes examples that the designer can follow to
better understand how to configure the SDRAM controller for synchronous operations.
18.2
18.2.1
Overview
Features
The MCF548x SDRAM controller contains the following features:
• Supports a glueless interface to SDR and DDR SDRAMs
• 32-bit fixed memory port width
• 64-bit data bus interface to internal XLB 64-bit bus
• 32 bytes critical word first burst transfer
• Up to 13 row address lines, up to 12 column address lines, 2 bits of bank address, and a maximum
of four chip selects. The maximum row bits plus column bits can be less than or equal to 24.
• Supports up to 1 Gbyte of memory—13+11 or 12+12 bit RA+CA, 2 bit BA, four chip selects
• Minimum memory configuration of 8 Mbyte—11 bit row address (RA), 8 bit column address
(CA), 2 bit bank address (BA) and one chip select
• Supports page mode to maximize the data rate
• Supports sleep mode and self-refresh mode
• Error detect and parity check are not supported
18.2.2
Terminology
The following terminology is used in this chapter:
• SDRAM block: Any group of DRAM memories selected by one of the MCF548x SDCS[3:0]
signals. Thus, the MCF548x can support up to four independent memory blocks. The base address
of each block is programmed in the DRAM address and control registers (DACR0 and DACR1).
• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM
component might be configured as four 512K x 32 banks. Banks are selected through the
SD_BA[1:0] signals.
• SDRAM: These are RAMs that operate like asynchronous DRAMs but with a synchronous clock,
a pipelined, multiple-bank architecture, and a faster speed.
• Single data rate (SDR) SDRAM: This is SDRAM that drives/latches data and command
information on the rising edge of the clock.
• Double data rate (DDR) SDRAM: This is SDRAM that latches command information on the rising
edge of the clock, but data is driven/latched on both the rising and falling edges of the clock rather
than on just the rising edge. This doubles data throughput rate without an increase in frequency.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
18-1
18.2.3
Block Diagram
Column
addr[29:4]
Address
Input
MUX
Bank
Row
Column
Address
Pipeline
Latches
Bank
Row
Address
Output
MUX
SDADDR[12:0]
SDBA[1:0]
Select
SDCS[3:0]
RAS
addr[1:3]
SDRAM
Controller
State
Machine
CAS
SDWE
SDDQS
SDCLK[1:0]
SDCLK[1:0]
SDCKE
SDDM
tsiz[1:0], tbst
datain[63:0]
dataout[63:0]
Write Data
Buffer
SDDATA[31:0]
Read Data
Buffer
SDDATA[31:0]
Figure 18-1. SDRAM Controller Block Diagram
18.3
18.3.1
External Signal Description
SDRAM Data Bus (SDDATA[31:0])
SDDATA[31:0] is the bidirectional, non-multiplexed data bus used for SDRAM accesses. Data is sampled
by the MCF548x on the rising edge of SDCLK when in SDR mode, and on both the rising and falling edge
of SDCLK when in DDR mode.
18.3.2
SDRAM Address Bus (SDADDR[12:0])
The SDADDR[12:0] signals are the 13-bit, uni-directional address bus used for multiplexed row and
column addresses during SDRAM bus cycles. The address multiplexing supports up to 256 Mbytes of
SDRAM per chip select.
18.3.3
SDRAM Bank Addresses (SDBA[1:0])
Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank.
It is also used to select the SDRAM internal mode register during power-up initialization.
MCF548x Reference Manual, Rev. 3
18-2
Freescale Semiconductor
External Signal Description
18.3.4
SDRAM Row Address Strobe (RAS)
This output is the SDRAM synchronous row address strobe.
18.3.5
SDRAM Column Address Strobe (CAS)
This output is the SDRAM synchronous column address strobe.
18.3.6
SDRAM Chip Selects (SDCS[3:0])
These signals interface to the chip select lines of the SDRAMs within a memory block. Thus, there is one
SDCS line for each memory block (the MCF548x supports up to four SDRAM memory blocks).
18.3.7
SDRAM Write Data Byte Mask (SDDM[3:0])
These output signals are sampled by the SDRAM on both edges of SDDQS to determine which byte lanes
of the SDRAM data bus should be latched during a write cycle. In DDR mode, these bits are ignored during
read operations.
18.3.8
SDRAM Data Strobe (SDDQS[3:0])
These bidirectional signals indicate when valid data is on the SDRAM data bus. Table 18-1 shows the
correspondence between SDDATA byte lanes and the SDDQS and SDDM signals.
Table 18-1. SDDQS and SDDM to Byte Lane Mapping
18.3.9
Byte Lane
SDDQS
SDDM
SDDATA[31:24] (MSB)
SDDQS3
SDDM3
SDDATA[23:16]
SDDQS2
SDDM2
SDDATA[15:8]
SDDQS1
SDDM1
SDDATA[7:0] (LSB)
SDDQS0
SDDM0
SDRAM Clock (SDCLK[1:0])
This is the output clock for SDRAM accesses.
18.3.10 Inverted SDRAM Clock (SDCLK[1:0])
This is the inverted version of the SDRAM clock. It is used with SDCLK to provide the differential clocks
for DDR SDRAM.
18.3.11 SDRAM Write Enable (SDWE)
The SDRAM write enable (SDWE) is asserted to signify that a DRAM write cycle is underway. A read
cycle is indicated by the negation of SDWE.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
18-3
18.3.12 SDRAM Clock Enable (SDCKE)
This output is the SDRAM clock enable. SDCKE negates to put the SDRAM into low-power, self-refresh
mode.
18.3.13 SDR SDRAM Data Strobe (SDRDQS)
This is connected to SDDQS inputs. It is used in SDR mode only.
18.3.14 SDRAM Memory Supply (SDVDD)
These pins supply positive power to the SDRAM module. SDVDD should be connected to +2.5V for DDR
operation and +3.3V for SDR.
18.3.15 SDRAM Reference Voltage (VREF)
This is the input reference voltage for differential SSTL_2 inputs. It is used in both DDR and SDR modes.
For DDR VREF should be connected to 1.25V, and for SDR VREF should be connected to 1.5V.
18.4
18.4.1
Interface Recommendations
Supported Memory Configurations
The SDRAM controller supports up to 13 row addresses and up to 12 column addresses. However, the
maximum row and column addresses are not supported at the same time. The number of row and column
addresses must be less than or equal to 24. In addition to row/column address lines, there are always two
row bank address bits. Therefore, the greatest possible address space which can be accessed using a single
chip select is (226) x 32 bits, or 256 Mbytes.
Table 18-2 shows the address multiplexing used by the MCF548x for different configurations. When the
SDRAM controller receives the internal module enable, it latches the internal bus address lines addr[27:2]
and multiplexes them into row, column and row bank addresses. addr[9:2] are always used for CA[7:0],
addr[11:10] are always used for BA[1:0], and addr[23:12] are always used for RA[11:0]. addr[27:24] can
be used for additional row or column address bits, as needed.
NOTE
The SDRAMC only supports an external 32-bit data bus. It is not possible
to connect a smaller device(s) to only part of the SDRAM’s data bus. For
example, if 16-bit wide devices are used, then you must use two 16-bit
devices connected as a 32-bit port.
MCF548x Reference Manual, Rev. 3
18-4
Freescale Semiconductor
Interface Recommendations
Table 18-2. SDRAM Address Multiplexing
Device
Configur
ation
Row bit x Number
Col bit x
of
Bank bit Devices
512K x 32 bit 11 x 8 x 2
4M x 16 bit
12 x 8 x 2
Total SDCR
Block [MUX]
Size Setting
27
26
25
24
1
8 MB
00
—
—
—
—
2
16 MB
00
—
—
—
—
00
—
—
—
CA8
4
32 MB
01
—
—
—
RA12
00
—
—
CA9
CA8
8
64 MB
01
—
—
CA8
RA12
1
16 MB
00
—
—
—
—
00
—
—
—
CA8
2
32 MB
01
—
—
—
RA12
00
—
—
CA9
CA8
01
—
—
CA8
RA12
00
—
CA11
CA9
CA8
01
—
CA9
CA8
RA12
00
—
—
CA9
CA8
01
—
—
CA8
RA12
00
—
CA11
CA9
CA8
01
—
CA9
CA8
RA12
00
CA12 CA11
CA9
CA8
01
CA11
CA9
CA8
RA12
00
—
CA11
CA9
CA8
01
—
CA9
CA8
RA12
00
CA12 CA11
CA9
CA8
01
CA11
CA8
RA12
12 x 9 x 2
64 Mbits
8M x 8bit
13 x 8 x 2
12 x 10 x 2
16M x 4 bit
4M x 32 bit
13 x 9 x 2
12 x 8 x 2
12 x 9 x 2
8M x 16 bit
128
Mbits
13 x 8 x 2
12 x 10 x 2
16M x 8 bit
13 x 9 x 2
4
64 MB
8
128
MB
2
64 MB
4
128
MB
8
256
MB
2
128
MB
12 x 11 x 2
32M x 4 bit
13 x 10 x 2
12 x 10 x 2
16M x 16 bit
13 x 9 x 2
12 x 11 x 2
256
Mbits
32M x 8 bit
13 x 10 x 2
12 x 12 x 2
64M x 4 bit
13 x 11 x 2
12 x 11 x 2
32M x 16 bit
512
Mbits
13 x 10x 2
12 x 12 x 2
64M x 8bit
13 x 11 x 2
4
256
MB
Internal Address
CA9
23–12
11–10
9–2
RA11-0 BA1-0 CA7-0
RA11-0 BA1-0 CA7-0
RA11-0 BA1-0 CA7-0
RA11-0 BA1-0 CA7-0
All memory devices of a single chip select block must have the same configuration and row/col address
width; however, this is not necessary between different blocks. If mixing different memory organizations
in different blocks, the following guidelines will ensure that every block is fully contiguous.
• If all devices’ row address width is 12 bits, the column address can be ≥ 8 bits.
• If all devices’ row address width is 13 bits, the column address can be ≥ 8 bits.
• If all devices’ column address width is 8 bits, the row address can be ≥ 11 bits.
• x8 and x16 data width memory devices can be mixed (but not in the same space).
• x32 data width memory devices cannot be mixed with any other width.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
18-5
18.4.2
SDRAM SDR Connections
Figure 18-2 shows a block diagram of the connections between the MCF548x and SDR SDRAM
components. SDR design requires special timing consideration for the SDDQS[3:0] signals. For reads
from DDR SDRAMs, the memory will drive the DQS pins so that the data lines and DQS signals have
concurrent edges. The MCF548x SDRAMC is designed to latch data 1/4 clock after the SDDQS[3:0] edge.
For DDR SDRAM, this ensures that the latch time is in the middle of the data valid window.
The SDRAMC also uses the SDDQS[3:0] signals to determine when read data can be latched for SDR
SDRAM; however, SDR memories do not provide DQS outputs. Instead the SDRAMC provides an
SDRDQS output that is routed back into the controller as SDDQS[3:0]. The SDRDQS signal should be
routed such that the valid data from the SDRAM reaches the MCF548x at the same time or just before the
SDRDQS reaches the SDDQS[3:0] inputs. When routing SDRDQS the outbound trace length should be
matched to the SDCLK trace length. This will align SDRDQS to the SDCLK as if the memory had
generated the DQS pulse. The inbound trace should be routed along the data path. This should synchronize
the SDDQS so that the data is latched in the middle of the data valid window.
MCF548X
SDR SDRAM
SDADDR[12:0]
A[12:0]
SDBA[1:0]
BA[1:0]
SDDATA[31:0]
DQ[31:0]
SDCSn
CS
RAS
CAS
SDWE
RAS
CAS
WE
SDCLK[1:0]
SDCKE
CLK
CKE
SDDM[3:0]
DQM[3:0]
SDRDQS
SDDQS[3:0]
Figure 18-2. MCF548x Connections to SDR SDRAM
18.4.3
SDRAM DDR Component Connections
Figure 18-3 shows a block diagram of the connections between the MCF548x and DDR SDRAM
components.
MCF548x Reference Manual, Rev. 3
18-6
Freescale Semiconductor
Interface Recommendations
DDR SDRAM
MCF548X
SDADDR[12:0]
A[12:0]
SDBA[1:0]
BA[1:0]
SDDATA[31:0]
DQ[31:0]
SDCSn
CS
RAS
CAS
SDWE
RAS
CAS
WE
SD_CLK[1:0]
SD_CLK[1:0]
SD_CKE
CLK
CLK
CKE
SDDM[3:0]
SDDQS[3:0]
DM[3:0]
DQS[3:0]
Figure 18-3. MCF548x Connections to DDR SDRAM
18.4.4
SDRAM DDR DIMM Connections
There is a JEDEC standard for a 100-pin DDR DIMM with a 32-bit wide data bus. This DIMM standard
was designed specifically to support 32-bit processors. The MCF548x can support current DIMM
configurations up to 512 Mbytes.
Figure shows a block diagram of the connections between the MCF548x and DDR SDRAM DIMMs.
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
18-7
DDR SDRAM
MCF548X
SDADDR[12:0]
A[12:0]
SDBA[1:0]
BA[1:0]
SDDATA[31:0]
DQ[31:0]
SDCS[1:0]
S[1:0]
RAS
CAS
SDWE
RAS
CAS
WE
SDCLK[1:0]
SDCLK[1:0]
SDCKE
CLK[1:0]
CLK[1:0]
CKE
SDDM[3:0]
DM[3:0]
SDDQS[3:0]
DQS[3:0]
SCL
SCL
SDA
SDA
SDVDD
SA0
Figure 18-4. MCF548x Connections to 100-pin DDR SDRAM DIMM
18.4.5
DDR SDRAM Layout Considerations
Due to the critical timing for DDR SDRAM, there are a number of considerations that should be taken into
account during PCB layout:
• Minimize overall trace lengths.
• Each DQS, DM, and DQ group must have identical loading and similar routing to maintain timing
integrity.
• Control and clock signals are routed point-to-point.
• Trace length for clock, address, and command signals should match.
• Route DDR signals on layers adjacent to the ground plane.
• Use a VREF plane under the SDRAM.
• VREF is decoupled from both SDVDD and VSS.
• To avoid crosstalk, keep address and command signals separate from data and data strobes.
• Use different resistor packs for command/address and data/data strobes.
• Use single series, single parallel termination (25 Ω series, 50 Ω parallel values are recommended,
but standard resistor packs with similar values can be substituted).
• Series termination should be between the MCF548x and memory, but closest to the processor.
• The parallel termination at end of the signal line (close to the SDRAM).
• 0.1 uF decoupling for every termination resistor pack.
MCF548x Reference Manual, Rev. 3
18-8
Freescale Semiconductor
SDRAM Overview
18.4.5.1
Termination Example
Figure 18-5 shows the recommended termination circuitry for DDR SDRAM signals.
VREF
50 Ω
DDR SDRAM
MCF548X
25 Ω
Figure 18-5. MCF548x DDR SDRAM Termination Circuit
18.5
18.5.1
SDRAM Overview
SDRAM Commands
When an internal bus master accesses SDRAM address space, the memory controller generates the
corresponding SDRAM command. Ta