Delta Tau 4AX-603625-XUXX Speaker User Manual

^1 HARDWARE REFERENCE MANUAL
^2
UMAC-CPCI
Turbo CPU Board
^3 Turbo CPU Board
^4 4Ax-603625-xUxx
^5 January 28, 2003
Single Source Machine Control
Power // Flexibility // Ease of Use
21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com
Copyright Information
© 2003 Delta Tau Data Systems, Inc. All rights reserved.
This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained
in this manual may be updated from time-to-time due to product improvements, etc., and may not
conform in every respect to former issues.
To report errors or inconsistencies, call or email:
Delta Tau Data Systems, Inc. Technical Support
Phone: (818) 717-5656
Fax: (818) 998-7807
Email: support@deltatau.com
Website: http://www.deltatau.com
Operating Conditions
All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain
static sensitive components that can be damaged by incorrect handling. When installing or
handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials.
Only qualified personnel should be allowed to handle this equipment.
In the case of industrial applications, we expect our products to be protected from hazardous or
conductive materials and/or environments that could cause harm to the controller by damaging
components or causing electrical shorts. When our products are used in an industrial
environment, install them into an industrial electrical cabinet or industrial PC to protect them
from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials.
If Delta Tau Data Systems, Inc. products are exposed to hazardous or conductive materials and/or
environments, we cannot guarantee their operation.
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Table of Contents
INTRODUCTION .......................................................................................................................................................1
Associated Manuals...................................................................................................................................................2
BOARD CONFIGURATION .....................................................................................................................................3
Option 1: Communications Interfaces.......................................................................................................................3
Option 2: Dual-Ported RAM .....................................................................................................................................3
Option 5: CPU and Memory Configurations.............................................................................................................3
Option 8: High-Accuracy Clock Crystal ...................................................................................................................4
Option 9: Serial Port Configuration ..........................................................................................................................4
Option 10: Firmware Revision Specification ............................................................................................................4
Option 16: Battery-Backed Parameter Memory........................................................................................................4
HARDWARE SETUP .................................................................................................................................................5
Clock-Source Jumpers...............................................................................................................................................5
Watchdog Timer Jumper ...........................................................................................................................................5
Operation Mode Jumpers ..........................................................................................................................................5
Firmware Reload Jumper ..........................................................................................................................................5
Re-Initialization Jumper ............................................................................................................................................5
Serial-Port Level Select Jumpers...............................................................................................................................6
DPRAM IC Select Jumper ........................................................................................................................................6
Flash IC Firmware Bank Select Jumpers ..................................................................................................................6
Flash IC Power Supply Select Jumper ......................................................................................................................6
Power-Supply Check Select Jumper .........................................................................................................................6
Reset-Lock Jumper....................................................................................................................................................6
CONNECTIONS .........................................................................................................................................................7
Compact UBUS Connector .......................................................................................................................................7
Rear Field Wiring Connector ....................................................................................................................................7
Front-Panel RS-232 Connector .................................................................................................................................7
Stack Connectors to Bridge Board ............................................................................................................................7
Factory-Use Connectors ............................................................................................................................................8
BOARD LAYOUT.......................................................................................................................................................9
JUMPER DESCRIPTIONS......................................................................................................................................11
E0: Reset-Lock Enable (Factory Use Only) ............................................................................................................11
E1A: Servo and Phase Clock Direction Control......................................................................................................11
E1B: Servo/Phase Clock Source Control ................................................................................................................11
E2: (Reserved for Future Use).................................................................................................................................11
E3: Re-Initialization on Reset Control ....................................................................................................................12
E4: (Reserved for Future Use).................................................................................................................................12
E5: USB/Ethernet Communication Jumper.............................................................................................................12
E11: Power Supply Check Control..........................................................................................................................12
E17 – E18: Serial Port Select ..................................................................................................................................12
E18A, B, C, D: Ethernet Communication Control ..................................................................................................13
E19: Watchdog Disable Jumper ..............................................................................................................................13
E20 – E22: Power-Up/Reset Load Source ..............................................................................................................13
E23: Firmware Reload Enable.................................................................................................................................13
E25A, B, C: Flash Memory Firmware Bank Select ................................................................................................13
W1: Flash IC Power Supply Select Jumper.............................................................................................................14
CONNECTOR SUMMARY .....................................................................................................................................15
CONNECTOR PINOUTS.........................................................................................................................................17
Compact UBUS Connector (J1) Pin-Out.................................................................................................................17
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
UMAC-CPCI Turbo CPU Board J2 Connector ......................................................................................................18
J4: RS-232 Serial Port Connector...........................................................................................................................19
ACCESSORIES .........................................................................................................................................................21
ACC-Cx Compact UBUS Backplane Boards..........................................................................................................21
ACC-8CR Test Breakout Board..............................................................................................................................21
ACC-11C Sinking I/O Board ..................................................................................................................................21
ACC-24C2 PWM Axis Board.................................................................................................................................22
ACC-24C2A Analog Axis Board............................................................................................................................22
ACC-51C Analog Encoder Interpolator Board .......................................................................................................22
SCHEMATICS ..........................................................................................................................................................23
ii
Table of Contents
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
INTRODUCTION
Delta Tau’s UMAC-CPCI systems provide a compact and clean integration of motion and I/O control for
sophisticated automation equipment. The system consists of a modular set of 3U-size (100mm x 160mm)
boards in the “Compact PCI” format, implementing Turbo PMAC software and hardware functions,
communicating with each other over a common backplane (the “Compact UBUS”). All field wiring is
available on rear connectors, suitable for a user-designed distribution system to the machine. UMAC
(Universal Motion and Automation Controller) -CPCI systems provide integrated connectivity as well as
ease of assembly, diagnostics, and repair. UMAC-CPCI systems differ from “standard” UMAC systems
in that all field wiring comes to the back of the rack, behind the backplane, instead of direct top and
bottom access.
The UMAC-CPCI Turbo CPU board (Part number 3A0-603625-10x) implements a Turbo PMAC2 CPU
in the 3U CPCI form factor. Its software operation is completely identical to other Turbo PMAC2
controllers.
Note that a Compact PCI interface does not automatically come with a UMAC-CPCI system, nor is one
necessary to communicate to the system, given the other possible communications ports: RS-232, RS422, USB, and Ethernet.
This picture shows the UMAC-CPCI Turbo CPU
board. The connectors on the right side plug into the
“Compact UBUS” backplane board, with the bottom
right connector being the bus connector, and the top
right connector containing the external “field wiring”
signals, which typically pass through the backplane
board. The connector at lower left is an RS-232 port
intended for setup and diagnostics; the stack
connectors top and bottom provide the link to a CPCI
“bridge board”.
This picture shows a sample configuration of a
UMAC-CPCI system, not installed in its rack. It
consists of the following components:
1. Rack power supply (not a Delta Tau product)
2. UMAC-CPCI CPU board
3. ACC-11C Sinking I/O board
4. ACC-24C2A analog axis interface board
5. ACC-C8 8-slot Compact UBUS backplane.
Note the “pass-through” connector on the
back for field-wiring distribution. In this
picture, alternate slots in the backplane have
been left open to make each board more
visible. This does not have to be done in
actual use.
Introduction
1
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Associated Manuals
This document is the Hardware Reference Manual for the UMAC-CPCI Turbo CPU board for an UMACCPCI system. It describes the hardware features and provides setup instructions.
You will need other manuals as well to use your UMAC-CPCI system. Each accessory to the UMACCPCI Turbo CPU board has its own manual, describing its operation and any required software setup of
the Turbo CPU.
You will also need the Software Reference Manual for the Turbo PMAC family, and the User Guide for
the PMAC or Turbo PMAC families.
2
Introduction
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
BOARD CONFIGURATION
The base version of the UMAC-CPCI Turbo CPU board provides a 1-slot 3U-format Eurocard board
with:
• 80 MHz DSP56303 CPU (120 MHz PMAC equivalent)
• 128k x 24 SRAM compiled/assembled program memory (Opt. 5C0)
• 128k x 24 SRAM user data memory (Opt. 5C0)
• 1M x 8 flash memory for user backup & firmware (Opt. 5C0)
• Latest released firmware version
• RS-232/422 serial interface, available both on front-panel DB-9 connector and on backside fieldwiring connector
• Backplane Compact UBUS expansion connector for communication to servo and I/O accessory
boards
• Backside field-wiring connector
Option 1: Communications Interfaces
The UMAC-CPCI Turbo CPU board comes standard only with an RS-232/422 serial interface. The
Option 1 family provides faster interfaces for high-speed communications – Universal Serial Bus (USB),
Ethernet, or the link to the CPCI bus through a “bridge” daughter board.
• Option 1: On-board 10-Base-T TCP/IP Ethernet interface. The key added components are U67 and
U32.
• Option 1A: On-board 12 Mbit/sec USB interface. The key added component is U67.
• Option 1B: Solder-side stack connectors to CPCI-bridge daughter board. This option should only be
ordered when the bridge board is to be installed on the left side of the CPU board, so the CPU board
is in the leftmost slot of the Compact UBUS backplane, and the bridge board is in the rightmost slot
of the Compact PCI bus backplane.
Option 2: Dual-Ported RAM
With either the Option 1 Ethernet interface, or the Option 1A USB interface, communications throughput
can be increased through the use of dual-ported RAM, which provides a bank of memory that can be
directly accessed by both the UMAC-CPCI Turbo CPU and the communications microcontroller.
• Option 2: 32k x 16 bank of on-board dual-ported RAM (requires Option 1 or 1A) in component U56.
Option 5: CPU and Memory Configurations
The various versions of Option 5 provide different CPU speeds and main memory sizes on the piggyback
CPU board. Only one Option 5xx may be selected for the board.
The CPU is a DSP563xx IC as component U1. It is currently available only as an 80 MHz or 100 MHz
device (with computational power equivalent to a 120 MHz or 150 MHz non-Turbo PMAC, respectively),
but higher speed versions may become available.
The compiled/assembled-program (“P”) memory SRAM ICs are located in U14, U15, and U16. These
ICs form the active memory for the firmware, compiled PLCs, and user-written phase/servo algorithms.
These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger
512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The user-data memory (“X/Y”) SRAM ICs are located in U11, U12, and U13. These ICs form the active
memory for user motion programs, uncompiled PLC programs, and user tables and buffers. These can be
128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k x 8 ICs
(for a 512k x 24 bank), fitting in the full footprint.
Board Configuration
3
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
The flash memory IC is located in U10. This IC forms the non-volatile memory for the board’s firmware,
the user setup variables, and for user programs, tables, and buffers. It can be 1M x 8, 2M x 8, or 4M x 8
in capacity.
• Option 5C0 is the standard CPU and memory configuration. It is provided automatically if no Option
5xx is specified. It provides an 80 MHz DSP56303 CPU (120 MHz PMAC equivalent) with 8k x 24
of internal memory, an external 128k x 24 of compiled/assembled program memory, an external 128k
x 24 of user data memory; and a 1M x 8 flash memory. Setup variable I52 should be set and saved at
7 for 80 MHz operation.
• Option 5C3 provides an 80 MHz DSP56303 CPU (120 MHz PMAC equivalent) with 8k x 24 of
internal memory, an expanded external 512k x 24 of compiled/assembled program memory, an
expanded external 512k x 24 of user data memory, and a 4M x 8 flash memory. Setup variable I52
should be set and saved at 7 for 80 MHz operation.
• Option 5D0 provides a 100 MHz DSP56309 CPU (150 MHz PMAC equivalent) with 34k x 24 of
internal memory, an external 128k x24 of compiled/assembled program memory, an external 128k x
24 of user data memory; and a 1M x 8 flash memory. Setup variable I52 should be set and saved at 9
for 100 MHz operation.
• Option 5D3 provides a 100 MHz DSP56309 CPU (150 MHz PMAC equivalent) with 34k x 24 of
internal memory, an expanded external 512k x 24 of compiled/assembled program memory, an
expanded external 512k x 24 of user data memory, and a 4M x 8 flash memory. Setup variable I52
should be set and saved at 9 for 100 MHz operation.
Option 8: High-Accuracy Clock Crystal
The UMAC-CPCI Turbo CPU board has a clock crystal (component Y1) of nominal frequency 19.6608
MHz (~20 MHz). The standard crystal’s accuracy specification is +/-100 ppm.
• Option 8A provides a nominal 19.6608 MHz crystal with a +/-15 ppm accuracy specification.
Option 9: Serial Port Configuration
The UMAC-CPCI Turbo CPU board comes standard with a single RS-232/422 serial port, a second serial
port can be added.
• Option 9T adds an auxiliary RS-232 port on the CPU board. The key components added are ICs U28
and U43.
Option 10: Firmware Revision Specification
Normally the UMAC-CPCI Turbo CPU board is provided with the newest released firmware revision.
Some users may wish to “freeze” their designs on an older revision. A label on the U10 flash memory IC
shows the firmware revision loaded at the factory. The VERSION command can be used to report what
firmware revision is currently installed.
• Option 10 provides for a user-specified firmware version.
Option 16: Battery-Backed Parameter Memory
The contents of the standard memory are not retained through a power-down or reset unless they have
been saved to flash memory first. Option 16 provides supplemental battery-backed RAM for real-time
parameter storage that is ideal for holding machine state parameters in case of an unexpected powerdown.
• Option 16A provides a 32k x 24 bank of battery-backed parameter RAM in components U17, U18,
and U19 and a “can-stack” lithium battery in component BT1. While the average expected battery
life is over five years, a yearly replacement schedule is recommended. Replacement batteries can be
ordered from Delta Tau as Acc-1LS (Part # 100-0QTC85-000).
4
Board Configuration
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
HARDWARE SETUP
Clock-Source Jumpers
In order to operate properly, the Turbo CPU board must receive servo and phase clock signals from a
source external to the board. These clock signals can be brought into the board from one of three possible
ports: the stack connector, the UBUS backplane connector, or the front-side main serial-port connector.
Jumpers E1A and E1B must be configured properly for the clock source used.
(Note: If the UMAC-CPCI Turbo CPU board cannot find the clock signal from the source specified by
these jumpers, it will generate its own 2.26kHz servo clock and its own 9.04kHz phase clock so it will
stay in operation.)
To receive the clock signals over the Compact-UBUS backplane, usually from an ACC-24C2x axisinterface board, E1A must connect pins 1 and 2, and E1B must connect pins 2 and 3. This configuration
is typical for an UMAC-CPCI system. The clock signals are output on the main serial port.
To receive the clock signals through the stack connectors, usually from the MACRO IC on the CPCI
“bridge” board, E1A must connect pins 1 and 2, and the E1B jumper must be removed. The clock signals
are output on the main serial port.
To receive the clock signals through the main serial port, usually from another UMAC system or a
reference signal generator, E1A must connect pins 2 and 3, and E1B must connect pins 1 and 2. This
configuration is rarely used, but permits complete synchronization to the system that is generating the
clock signals.
Watchdog Timer Jumper
Jumper E19 should be OFF for normal operation, leaving the watchdog timer circuit active and prepared
to shut down the card in case of a severe problem. Putting jumper E19 ON disables the watchdog timer
circuit. This should only be used for test purposes, in trying to track down the source of watchdog timer
trips. Normal operation of a system with this jumper ON should never be attempted, as an important
safety feature is disabled.
Operation Mode Jumpers
Jumpers E20, E21, and E22 control the operational mode of the UMAC-CPCI Turbo CPU. For normal
operation, E20 must be OFF, E21 must be ON, and E22 must be ON. Other settings of these jumpers are
for factory use only.
Firmware Reload Jumper
Jumper E23 should be OFF for normal operation. If you want to load new firmware into the flashmemory IC on the CPU, E23 should be ON when the card is powered up. This puts the card in “bootstrap
mode”, ready to accept new firmware. If you then try to establish communications to the card with the
Executive program, either over the main serial port or the optional USB or Ethernet ports, the Executive
program will automatically recognize that the card is in bootstrap mode, and prompt you for the firmware
file to download.
Re-Initialization Jumper
Jumper E3 should be OFF for normal operation, where the last saved I-variable values are loaded from
flash memory into active memory at power-up/reset. If E3 is ON during power-up/reset, the factory
default I-variable values are instead loaded into active memory at power-up/reset. The last saved values
are not lost when this happens. This jumper is typically only used when the system’s set up has a
problem severe enough that communications does not work – otherwise, a $$$*** command can be
used for re-initialization.
Board Configuration
5
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Serial-Port Level Select Jumpers
The standard serial port can be used for either RS-232 or RS-422 serial communications. To use RS-232,
jumpers E17 and E18 should connect pins 1 and 2; to use RS-422, jumpers E17 and E18 should connect
pins 2 and 3. The front-panel DB-9 serial connector provides only the RS-232 signals, so in order to use
this connector, E17 and E18 must both connect pins 1 and 2.
DPRAM IC Select Jumper
The UMAC-CPCI Turbo CPU board can provide dual-ported RAM (DPRAM) communications using
either the on-board Option 2B DPRAM IC through the USB or Ethernet port, or using the DPRAM IC on
the CPCI bridge daughter board through that board’s CPCI port. Jumper E24 must connect pins 1 and 2
to use the on-board Option 2B DPRAM; it must connect pins 2 and 3 to use the CPCI bridge board
DPRAM.
Flash IC Firmware Bank Select Jumpers
Some makes of the U10 flash memory IC on the UMAC-CPCI Turbo CPU board can store multiple
versions of the operating firmware inside. Jumpers E25A, E25B, and E25C select which bank is loaded
into active memory on a normal power-up/reset, and which bank will be written to if the board is powered
up or reset with the E23 jumper on.
The eight possible settings of these three jumpers provide eight banks for the firmware. A standard
production version of the UMAC-CPCI Turbo CPU board is shipped with firmware loaded only in the
bank selected by having all three of these jumpers OFF.
Flash IC Power Supply Select Jumper
Jumper W1 is set at the factory for the voltage level of the flash IC installed in U10. It connects pins 1
and 2 for a 3.3V flash IC; it connects pins 2 and 3 for a 5V flash IC. Even if this is a removable, not
soldered, jumper, it should not be changed by the user.
Power-Supply Check Select Jumper
The UMAC-CPCI Turbo CPU board has a circuit to evaluate the voltage levels received through the J1
Compact UBUS backplane connector. This circuit can then notify other boards in the system (without
software intervention) of a bad supply, so the outputs of those boards are automatically shut down.
Jumper E11 should be OFF if only the 5V supply is checked for this purpose; it should be ON if the +12V
and –12V backplane supplies are to be checked for this purpose. Note that many users will provide a
separate isolated +/-12V supply into the analog axis boards, and each analog axis board has its own
power-supply check circuit.
Reset-Lock Jumper
Putting jumper E0 ON locks the UMAC-CPCI Turbo CPU board in the reset state. This setting permits
the loading of logic into the programmable ICs on the board and is for factory use only. This jumper
should be OFF for all normal operation.
6
Hardware Setup
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
CONNECTIONS
In a typical installation, the UMAC-CPCI Turbo CPU board is simply slid into a slot of a 3U-Eurocard
rack until it inserts into the mating connectors on the backplane board already installed in the rack. In
actual operation, all signals to the board come into the CPU board through the backplane. (The frontpanel RS-232 connector is intended for test and debugging purposes.)
Compact UBUS Connector
The J1 “Compact UBUS” connector at the bottom of the back edge of the board provides the means for
the UMAC-CPCI Turbo CPU board to communicate with axis and I/O boards through a common
backplane board, such as a Delta Tau ACC-Cx board, or a user-designed backplane board. It also
provides the 3.3V and 5V power supply lines to the CPU board.
Because of the design of the Compact UBUS, the CPU board can operate in any slot of the bus.
However, if the CPU board has the CPCI bridge board installed on it, the CPU board must be installed in
the end slot of the Compact UBUS backplane immediately adjacent to the Compact PCI bus backplane
board, so the bridge board can be installed in the adjacent CPCI end slot.
Rear Field Wiring Connector
The J2 field-wiring connector at the top of the back edge of the board provides the path for all of the
signals between the CPU board and the outside system. In a typical configuration, this connector is mated
with a “pass-through” connector on the Compact UBUS backplane board, and a system-specific
distribution system is installed behind the backplane.
The J2 connector contains the signals for the main serial port (either RS-232 or RS-422 levels), the
optional auxiliary RS-232 serial port, the optional USB port, and the optional Ethernet port. It also
provides the outputs of the relay for the CPU board’s watchdog timer.
Front-Panel RS-232 Connector
The J4 DB-9S connector on the front panel is a standard RS-232 connector for the main serial port into
the CPU, permitting a straight-across cable to a matching cable on a host computer. Jumpers E17 and
E18 must each connect pins 1 and 2 to permit use of this connector. These same signals are available on
the rear J2 connector; this front connector is intended for setup and diagnostic use more than use in the
actual application.
Stack Connectors to Bridge Board
Stacking socket connectors J11 and J12 on the top and bottom edges, respectively, of the component side
of the CPU board provide connection to the optional CPCI bridge board that can form a two-board
“stack” with the CPU board. (Mating prong connectors on the solder side of the bridge board must be
ordered.) In this configuration, the UMAC-CPCI Turbo CPU board can be installed in the rightmost slot
of a Compact UBUS backplane, and the bridge board can be installed in the leftmost slot of a CPCI
backplane.
If Option 2C is ordered, stacking “prong” connectors J11A and J12A are provided at the same locations
on the solder side of the board. These provide connection to mating socket connectors on the component
side of the bridge board. In this configuration, the UMAC-CPCI Turbo CPU board can be installed in the
leftmost slot of a Compact UBUS backplane, and the bridge board can be installed in the rightmost slot of
a CPCI backplane.
Connections
7
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Factory-Use Connectors
There are several connectors on the interior of the board for factory setup and diagnostic use. These are
not for customer use.
8
Connections
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
BOARD LAYOUT
This diagram of the UMAC-CPCI Turbo CPU board shows the locations of the jumpers and connectors.
Detailed information about each of the jumpers and connectors follows.
UMAC-CPCI Turbo CPU Board Layout
Board Layout
9
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
10
Board Layout
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
JUMPER DESCRIPTIONS
Note:
Pin 1 of an E-point is masked by an X and a bold square in white ink on the composite
side, and by a square solder pad on the solder side.
E0: Reset-Lock Enable (Factory Use Only)
E Point &
Physical Layout
Location
Description
Jump pins 1 and 2 to lock the UMAC-CPCI Turbo CPU board in
the “reset” state to permit installation of on-board logic. This
setting for factory use only.
Remove jumper to permit normal operation of board.
Default
No jumper
installed
E1A: Servo and Phase Clock Direction Control
E Point &
Physical Layout
Location
Description
Jump pins 1 and 2 or remove jumper for the UMAC-CPCI system
to use its internally generated servo and phase clock signals and to
output these signals on the field wiring connector on the CPU
board. E1B should connect pins 2 and 3 or be removed.
Jump pins 2 and 3 for the UMAC-CPCI system to expect to
receive its servo and phase clock signals on J2 field-wiring
connector on the Turbo CPU board. E1B should also connect pins
1 and 2.
Default
Pins 1-2
jumpered
E1B: Servo/Phase Clock Source Control
E Point &
Physical Layout
Location
Description
Jump pin 1 to 2 to get phase and servo clocks from J7 RS422
connector (from an external source such as another UMAC).
Jump pin 2 to 3 to get phase and servo clocks from J1 backplane
connector (from an ACC-24C2x, or equivalent board).
Remove jumper to get phase and servo clocks from J2 Stack
connector (from an ACC-2E or equivalent board)
Default
Pins 2 – 3
jumpered
E2: (Reserved for Future Use)
E Point &
Physical Layout
Location
Description
Default
No jumper
installed
Jumper Descriptions
11
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
E3: Re-Initialization on Reset Control
E Point &
Physical Layout
Location
Description
Default
Remove jumper for normal reset mode (default).
Jump pins 1 to 2 for re-initialization on reset.
No jumper
installed
E4: (Reserved for Future Use)
E Point &
Physical Layout
Location
Description
Default
No jumper
installed
E5: USB/Ethernet Communication Jumper
E Point &
Physical Layout
Location
Description
Default
Jump 1-2 for Ethernet or USB communications from J7 (Ethernet
connector) or J3 (USB connector).
Jump 2-3 for Ethernet or USB communications through the back
J2 connector
Factory
installed
E11: Power Supply Check Control
E Point &
Physical Layout
Location
Description
Default
Jump E11 pin 1 to 2 to include the +12V and –12V analog
supplies from the J1 backplane connector in the power-supply
check circuit, inhibiting outputs if these supplies fail.
Remove E11 jumper so only 5V digital supply is used in powersupply check circuit.
E11:
No jumper
installed
E17 – E18: Serial Port Select
E Point &
Physical Layout
E17:
E18:
12
Location
Description
Default
Jump E17 pin 1 to 2 to select RS-232 serial data input for main
serial port (J4 front-panel or J2 backside connector).
Jump E17 pin 2 to 3 to select RS-422 serial data input for main
serial port (J4 front-panel or J2 backside connector).
Jump E18 pin 1 to 2 to select RS-232 serial handshake input for
main serial port (J2 backside connector only).
Jump E18 pin 2 to 3 to select RS-422 serial handshake input f for
main serial port (J2 backside connector only).
Pins 1-2
jumpered
Pins 1-2
jumpered
Jumper Descriptions
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
E18A, B, C, D: Ethernet Communication Control
E Point & Physical
Layout
1
1
1
Location
Description
Jump 1 to 2 to Ethernet Connection to J7 front connector
Jump 2-3 for Ethernet connection through back J2 connector
E18D
E18C
E18B
Default
Pins 1-2
jumpered
E19: Watchdog Disable Jumper
E Point & Physical
Layout
Location
Description
Jump pin 1 to 2 to disable Watchdog timer (for test purposes
only.).
Remove jumper to enable Watchdog timer.
Default
No jumper
installed
E20 – E22: Power-Up/Reset Load Source
E Point &
Physical Layout
Location
Description
To load active memory from flash IC on power-up/reset,
Remove jumper E20;
Jump E21 pin 1 to 2;
Jump E22 pin 1 to 2.
Other combinations are for factory use only; the board will not
operate in any other configuration.
E20:
Default
No E20 jumper
installed
E21 and E22
jump pin 1 to 2
E23: Firmware Reload Enable
E Point &
Physical Layout
Location
Description
Jump pin 1 to 2 to reload firmware through serial or host bus port.
Remove jumper for normal operations.
Default
No jumper
installed
E25A, B, C: Flash Memory Firmware Bank Select
E Point &
Physical Layout
Location
Description
Remove all jumpers to select standard factory-installed bank of
operational firmware.
Install one or more jumper(s) to select alternate bank of operation
firmware to install (E23 ON) or use (E23 OFF).
Jumper Descriptions
Default
No jumpers
installed
13
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
W1: Flash IC Power Supply Select Jumper
E Point &
Physical Layout
14
Location
Description
Default
B-1
(Note: This jumper is set at the factory and possibly hard soldered.
Users should not change this jumper.)
Jump pin 1 to 2 to select 3.3V supply for flash memory IC in U10.
Jump pin 2 to 3 to select 5V supply for flash memory IC in U10.
Setting
dependent on
flash IC used.
Jumper Descriptions
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
CONNECTOR SUMMARY
J1:
*
Compact UBUS Backplane Connector
J2:
*
“Thru-Backplane” Field Wiring Connector
J4:
*
RS-232 Front-Panel Serial-Port Connector
J5:
JTAG/OnCE (for factory use only): 10-pin IDC connector
J6:
JISP (for factory use only): 8-pin SIP connector
J10:
JISP_B (for factory use only) 8-pin SIP connector
J11:
First component-side stack connector to CPCI bridge board
J11A:
First solder-side stack connector to CPCI bridge board
J12:
First component-side stack connector to CPCI bridge board
J12A:
First solder-side stack connector to CPCI bridge board
* Pinouts shown in next section. Connectors not flagged with an asterisk are for internal use or factory setup.
Connector Summary
15
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
16
Connector Summary
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
CONNECTOR PINOUTS
Compact UBUS Connector (J1) Pin-Out
Row
Z
A
B
C
D
E
F
25
GND
5V
3.3V
5V
GND
24
GND
BD02
5V
V(I/O)
BD01
BD00
GND
23
GND
3.3V
BD05
BD04
5V
BD03
GND
22
GND
BD09
BD08
3.3V
BD07
BD06
GND
21
GND
3.3V
BD13
BD12
BD11
BD10
GND
20
GND
BD17
GND
BD16
BD15
BD14
GND
19
GND
3.3V
BD20
BD19
GND
BD18
GND
18
GND
BD23
GND
3.3V
BD22
BD21
GND
17
GND
3.3V
{BD26}
{BD25}
GND
{BD24}
GND
16
GND
{BD30}
GND
{BD29}
{BD28}
{BD27}
GND
15
GND
3.3V
BWRBRDGND
{BD31}
GND
14
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
13
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
12
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
11
GND
CS10CS4CS3GND
CS2GND
10
GND
CS16GND
3.3V
CS14CS12GND
9
GND
IREQ2IREQ1MEMCS1GND
MEMCS0GND
8
GND
PHASE+
GND
SERVO+
WAITIREQ3GND
7
GND
PHASEWDO
SERVOGND
GND
6
GND
BA02
GND
3.3V
BA01
BA00
GND
5
GND
BA04
BA03
RESETGND
BX/Y
GND
4
GND
BA07
GND
V(I/O)
BA06
BA05
GND
3
GND
BA11
BA10
BA09
5V
BA08
GND
2
GND
{BA15}
5V
{BA14}
BA13
BA12
GND
1
GND
5V
-12V
PWRGUD
+12V
5V
GND
Notes:
1. Row 25 is physically at the top of the connector in its “normal” orientation; Row 1 is at the bottom.
Looking from the front of the rack, Column Z is on the left; Column F is on the right.
2. Supply (Vxx & xxV) and ground pins are in the same locations as the Compact PCI bus.
3. Spaces marked (KEY) are for the mechanical key; these are not pins.
4. Pins marked with {} brackets are reserved for future use; the signals inside the brackets are proposed
for future expansion to a 32-bit data bus and 16-bit address bus.
Connector Pinouts
17
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
UMAC-CPCI Turbo CPU Board J2 Connector
Row
Z
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A
B
RxD/
RDCS+
DSR
SERVO-
CTS
RD+
CSDTR
SERVO+
AuxRxD/
AuxDSR
AuxCTS
AuxDTR
USBDP (D+)
EthTxF+
C
+5V
+5V
GND
GND
GND
EthTxF-
WD_NO
D
TxD/
SDRS+/
INIT/
PHASE-
PHASE+
AuxTxD/
AuxRTS
RTS
SD+
RS-
USBDM (D-)
EthRxF+
WD_CO
M
E
WD_NC
EthRxF-
F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
GND
GND
Notes:
1. Row 25 is physically at the top of the connector in its “normal” orientation; Row 1 is at the bottom. Looking
from the front of the rack, Column Z is on the left; Column F is on the right.
2. The RxD/, CTS, TxD/, and RTS lines are standard RS-232 signals. The inputs are only used if jumpers E17
and E18 each connect their pins 1 and 2. The DSR and DTR lines are simply shorted together.
3. The RD-, RD+, SD-, SD+, CS+, CS-, RS+, and RS- lines are standard RS-422 signals. The inputs are only
used if jumpers E17 and E18 each connect their pins 2 and 3.
4. The SERVO-, SERVO+, PHASE- and PHASE+ clock lines are at RS-422 levels. These signals are outputs if
jumper E1A connects its pins 1 and 2; they are inputs if jumper E1A connects pins 2 and 3.
5. The AuxRxD/, AuxCTS, AuxTxD/, and AuxRTS lines are standard RS-232 signals. These signals are
provided only if the Option 9T auxiliary serial port is ordered. The AuxDSR and AuxDTR lines are simply
shorted together.
6. The USBDP(D+) and USBDM(D-) signals are standard USB signals. They are only provided if the Option
1A USB interface is ordered.
7. The EthTxF+, EthTxF-, EthRxF+, and EthRxF- signals are standard Ethernet signals. They are only provided
if the Option 1 Ethernet interface is ordered.
8. The WD_NO (normally open), WD_COM (common) and WD_NC (normally closed) lines are the outputs of
the watchdog-timer hard-contact relay. The normally open contact is only conducting to common if the card is
powered and operating correctly. The normally closed contact is only conducting to common if the card is not
powered or the watchdog timer has tripped.
18
Connector Pinouts
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
J4: RS-232 Serial Port Connector
(DB-9S Connector)
Pin #
Symbol
Function
Description
Notes
1
N.C.
No connect
2
TXDOutput
Send Data
Low TRUE
3
RXDInput
Receive Data
Low TRUE
4
DSR
Bidirect
Data Set Ready
Shorted to DTR
5
GND
Common
UMAC CPCI Reference
6
DTR
Bidirect
Data Terminal Ready
Shorted to DSR
7
CTS
Input
Clear to Send
High TRUE
8
RTS
Output
Request to Send
High TRUE
9
N.C.
No connect
Jumpers E17 and E18 should connect pins 1 and 2 to use this port for RS-232 communications; they should connect pins 2
and 3 to use this port for RS-422 communications.
Connector Pinouts
19
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
20
Connector Pinouts
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
ACCESSORIES
The UMAC-CPCI Turbo CPU board is always used with accessory boards. Delta Tau provides several
accessory boards in the UMAC-CPCI family that can be used with the CPU board; other parties may
produce accessory boards as well. Each accessory board has its own hardware reference manual.
ACC-Cx Compact UBUS Backplane Boards
The ACC-Cx family of Compact UBUS backplane boards
provides the means for the CPU board to communicate with
other accessory boards. The x in the name of the backplane
board refers to the number of backplane data slots provided.
This picture shows an ACC-C8 8-slot backplane board. It has
a P47-style power connector suitable for a standard 1-slot
CPCI-format power supply.
ACC-8CR Test Breakout Board
The ACC-8CR board provides a behind-the-backplane breakout scheme for the J2 field wiring connector
on any of the 3U-format UMAC-CPCI board. It is designed to plug into the rear of an ACC-Cx Compact
UBUS backplane board, and it meets the Compact PCI physical specification (100mm x 80mm) for rear
distribution boards. It has 110 screw-down terminal points, one for each signal on the J2 field wiring
connector.
ACC-11C Sinking I/O Board
The ACC-11C board provides 32 isolated 12V-24V
sinking inputs and 16 isolated sinking outputs up to 24V
and 100mA per output. With its Option 1 mezzanine
board, an additional 32 inputs and 16 outputs are
provided, for a total of 96 I/O points in a single slot.
Schematics
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
ACC-24C2 PWM Axis Board
The ACC-24C2 PWM axis board provides the interface circuitry for 4 axes of purely digital control in a
single slot, with direct PWM outputs, serial ADC inputs, quadrature encoder inputs, and input/output
flags. Because of pin limitations on the J2 field wiring connector, signals that are differential on other
ACC-24x2 boards are single-ended here. To take these signals any significant distance, differential line
drivers and receivers are required on a distribution board.
ACC-24C2A Analog Axis Board
The ACC-24C2A analog axis board provides the
interface circuitry for 4 axes of control in a single slot,
with analog interface to the servo drives. It also has
one pulse-and-direction output per axis for stepper
drives, or stepper-replacement servo drives. One 18-bit
D/A converter comes standard for each axis; Option 1
provides a second D/A converter per axis, which can be
used as part of a “sine-wave” control scheme, or for
non-servo use. Option 2 provides eight 12-bit A/D
converters.
ACC-51C Analog Encoder Interpolator Board
The ACC-51C provides the circuitry for the high-resolution interpolation of 2 or 4 analog sine/cosine
encoders, yielding 4096 states per line of the encoder. The board comes standard with two channels of
interface; Option 1 provides two additional channels.
22
Accessories
Schematics
J5
6
7
8
1
2
3
4
(jisp)
J6
C86
.1UF
31
RESET-
.1UF
VCCIO
VCCIO
VCC
VCC
GND
GND
GND
GND
RESET
BSCAN
TDI/A16
TDO/A17
TCK
TMS
A14
WR
RD
FLASHCS
DRAMCS
PRAMCS
A8
A9
A10
A11
A15
U6B
WR-
MODE
A17
A15
ISPEN-
DETRST-
RESETTMS
TCK
TDO
TDI
ISPEN-
PRDY
3.3KSIP10C
1
19
RESET
T/R
OE
A0
A1
A2
A3
A4
A5
A6
A7
U34
5
43
46
47
38
39
40
41
44
45
20
21
22
23
25
26
27
28
33
34
35
37
2
GND
.1UF
C25
.1UF
C24
.1UF
C23
.1UF
C22
VCC
GND
+5V
.1UF
C88
CPURST-
PWRG
BA14
BA15
BA12
BA13
BA10
BA11
BA06
BA07
BA08
BA09
RDBA05
A19X/YP
WR-
OSC_OUT
HACK-
T/R1
B0
B1
GND
B2
B3
VCC
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
PWRG
.1UF
GND
GND
OE1
A0
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCC
A12
A13
GND
A14
A15
OE2
+5V
T/R1
B0
B1
GND
B2
B3
VCC
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
HREQ-
IPOS
BFUL
EROR
F1ER
.1UF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
C153
CS0CS1-
CS14CS16-
CS04CS06CS10CS12-
CS00CS02-
CS2CS3-
+3P3V
.1UF
+3P3V
C26
.1UF
+3P3V
C27
+3P3V
+3P3V
+3P3V
+3P3V
+3P3V
IOCS_AIOCS_BDPRCS0VMECS0-
MEMCS1PWRGUD
CS4MEMCS0-
BA14_A
BA12_A
BA13_A
BA10_A
BA11_A
BA06_A
BA07_A
BA08_A
BA09_A
BRDBA05_A
BX/Y
BWR-
GUARD BAND
BA14
BA15
BA12
BA13
BA10
BA11
BA06
BA07
BA08
BA09
BA04
BA05
BA02
BA03
BA00
BA01
.1UF
C152
BA14_A
BA12_A
BA13_A
BA10_A
BA11_A
BA06_A
BA07_A
BA08_A
BA09_A
BRDBA05_A
BX/Y
BWR-
EXTAL
BHACK-
BA14
BA15
BA12
BA13
BA10
BA11
BA06
BA07
BA08
BA09
BA04
BA05
BA02
BA03
BA00
BA01
RP14
3.3KSIP10C
IPOS
BFUL
EROR
F1ER
ENA422
HREQTXD
RTS-
10UF
16V
(TANT)
+
GND
C39
PI74FCT16245ATA
(TSSOP48)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
.1UF
C151
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
U51
T/R1
B0
B1
GND
B2
B3
VCC
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
74LCX16245
(TSSOP48)
OE1
A0
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCC
A12
A13
GND
A14
A15
OE2
74LCX16245
(TSSOP48)
U8
OE1
A0
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCC
A12
A13
GND
A14
A15
OE2
U7
C150
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
+
Firmware (64K)
User Written Phase (1K)
User Written Servo (2K)
Plcc Standard Memory Option (64K)
Plcc Extended Memory Option (448K)
20
10
18
17
16
15
14
13
12
11
IOCS-
+3P3V
+3P3V
B0
B1
B2
B3
B4
B5
B6
B7
A14
A15
A12
A13
A10
A11
A6
A7
A8
A9
A4
A5
A2
A3
A0
A1
GUARD BAND
+3P3V
+3P3V
PI74FCT245TL
(TSSOP20)
2
3
4
5
6
7
8
9
BSTD1
BSRD1
BSCK1
BSC12
BSC11
BHREQBTXD
BRTS-
N.C.
N.C.
IOCS_A
IOCS_B
DPRCS0
DPRCS1
VMECS0
VMECS1
CS4
CPURST-
CS0
CS1
CS2
CS3
CS00
CS02
CS04
CS06
CS10
CS12
CS14
CS16
IOCS
PRDY
TURBO-DECODE5
ispLSI2032E-135LT48
(TQFP48)
24
48
6
30
12
18
36
42
7
8
19
29
32
ISPENA16
A17
WRMODE
C87
1
3
4
9
10
11
13
14
15
16
17
C21
.01UF
BA14
BWRBRDFLASHCSDRAMCSPRAMCSBA08
BA09
BA10
BA11
BA15
GND
RP4
PRAM MEMORY P:
$000000-$00FFFF
$040000-$0403FF
$040400-$040BFF
$050000-$05FFFF
$050000-$0BFFFF
GND
+5V
FLASHCSDRAMCSPRAMCS-
HSIP8NO5
MODE
GND
SCLK
+3.3V
SDO
SDI
ispEN-
J6
HEADER14_NO8
(JTAG/OnCE)
J5
TSI
1
GND
2
TSO
3
GND
4
TCK
5
GND
6
N.C.
7
RST9
TMS
10
+3.3V
11
N.C.
12
DE13
TRST14
1
+3P3V
10
2
3
4
5
6
7
8
9
IOCS_AIOCS_BDPRCS0VMECS0-
MEMCS1PWRGUD
CS4MEMCS0-
CS14CS16-
CS04CS06CS10CS12-
CS00CS02-
CS2CS3-
CS0CS1-
WAIT2-
WAIT1-
GND
2
WAIT2-
U9
GND
GND
4
TA-
X/Y:$060000-$067FFF EXTENDED MEMORY ON_BOARD
X/Y:$070000-$073FFF
X/Y:$074000-$077FFF
(32K)
X/Y:$078400-$0787FF
X/Y:$068000-$06FFFF EXTENDED MEMORY OFF_BOARD (32K)
X/Y:$078E00-$078EFF
X/Y:$078F00-$078FFF
X/Y:$078A00-$078AFF
X/Y:$078B00-$078BFF
X/Y:$078C00-$078CFF
X/Y:$078D00-$078DFF
X/Y:$078800-$0789FF
X/Y:$078200-$0782FF
X/Y:$078300-$0783FF
X/Y:$078000-$0780FF
X/Y:$078100-$0781FF
NC7SZ00
(SOT23-5)
1
WAIT1-
C40
.1UF
+3P3V
SERVO
PHASE
10
2
+5V
+5V
GND
U50
NC7SZ08M5
(SOT23-5)
1
RESETCPURST-
SERVO
PHASE
IRQBRXD
CTSWAIT1WAIT2-
RP13
3.3KSIP10C
1
RP20
13
1
4
9
74ACT14
(SO14)
U33D
74ACT14
(SO14)
U33E
74ACT14
(SO14)
74ACT14
(SO14)
U33B
.1UF
C92
B0
B1
B2
B3
B4
B5
B6
B7
8
10
4
GND
BSER
BPHA
GND
.1UF
INIT-
RESET_A
R7
100
+3P3V
D6
+
1
.01FARAD
FM0H103Z
NEC
3
C17
MMBD301LT1
D5
Vout
Vbat
E19
Vout
R3
10K
RP12C
1KSIP6I
R2
1K
+5V
E0
MMBD301LT1
1
3.6V BAT
BT1
WDTC
INIT-
JUMP `E0'
TO LOAD
`isp' PART
BSA02
BSA01
BSA00
IRQB-
19.6608Mhz
C111
RXD
CTSBSER
BPHA
BSA02
BSA01
BSA00
IRQB-
RESET_A
20
10
18
17
16
15
14
13
12
11
+3P3V
19.6608Mhz
VCC
GND
74LCX245
(TSSOP20)
T/R
OE
A0
A1
A2
A3
A4
A5
A6
A7
U27
U33F
11
3
1
19
2
3
4
5
6
7
8
9
74ACT14
(SO14)
12
2
10
R1
3.3KSIP10C
+5V
12
(SO14)
74ACT14
U33A
BRXD
BCTSSER_A
PHA_A
BHA2
BHA1
BHA0
MODD/IRQDHACKT/RRESET
13
U4F
OSC_OUT
3
C16
.1UF
GND
3
.01UF
C35
2
+ C34
1UF
35V
tant
2
Q3
2
MMBT3906LT1
3
(SOT23)
4
3
2
1
VCC
3
1
4
RP12B
MAX795SCSE
(SO8)
CEI
CEO
RST
BATT
MMBD301LT1
D4
DS1231S
(SOL16)
1
D3
4
C15
.1UF
5
6
7
8
3
3
5
4
RP10A
RP10B
5
RP10D
RP11A
5
RP11D
3 E1A
1
Q4
74ACT08
(SO14)
.1UF
C2
16
15
14
13
12
11
10
9
+5V
2
6
6
8
6
4
2
8
6
4
2
3
SOT23
74ACT14
(SO14)
U38B
5
U33C
3.3KSIP8I
7
3.3KSIP8I
RP11C
3.3KSIP8I
3
RP11B
3.3KSIP8I
1
3.3KSIP8I
7
3.3KSIP8I
RP10C
3.3KSIP8I
3
3
SOT23
2N7002
(SOT23)
N.C.
VCC
N.C.
NMI
N.C.
RST
N.C.
RST
MMBD301LT1
1
1KSIP6I
3
(SO14)
74ACT14
N.C.
IN
N.C.
MODE
N.C.
TOL
N.C.
GND
GND
ON
E1B
U4B
U3
VOUT
U2
1
2
3
4
5
6
7
8
3
SER
PHA
CARD0
ENA_P1-
2
ENA_P2-
"Vbat" s/b 30mil trace
R4
100K
RP12A
2
+5V
1KSIP6I
1
74ACT14
(SO14)
.1UF
U4A
Q1
MMBT3906LT1
(SOT23)
C1
.1UF
1
GND
C36
SER
PHA
CARD0
ENA_P1-
RESET
ENA_P2-
GND
1
3.3KSIP8I
5
U4C
2
GND
Q2
2N7002
(SOT23)
11
9
3
SOT23
2N7002
(SOT23)
Q5
SERVO+
SERVO-
PHASE-
8
10
(SO14)
74ACT14
U4E
(SO14)
74ACT14
U4D
(SO14)
74ACT14
6
7
SERVO-
10
9
8
7
6
5
4
3
2
1
8
6
SERVO+
5
4
3
1
GND
GND
(SO14)
U38A
5
IN-A
R5
1K
D2
LED
GRN
PWR
MC75174BDW
(SOL20)
GND
IN-C
OUT-C
N.C.
OUT-C
EN-A,C
OUT-A
N.C.
OUT-A
IN-A
U31
MC3486D
(SO16)
GND
IB-C
IN-C
OUT-C
EN-A,C
OUT-A
IN-A
6
IN-B
IN-B
VCC
C100
IN-D
IN-D
OUT-D
EN-B,D
.1UF
C101
+5V
WDO
NMI-
RESET
11
12
13
14
15
16
17
18
19
20
9
10
11
12
13
14
15
16
.1UF
C113
RP3D
3.3K
+5V
TRST-
BBRAMCS-
BBRCS-
RESET-
16
15
14
13
12
11
10
9
RTS-
TXD
CTS-
RXD
RX
RP2A
BBRCS-
RESET-
WDO
NMI-
RESET
+5V
2
1
+3P3V
Y2
RP1A
3.3K
ECS-36-20-5P
3.6864Mhz
D1
LED
RED
WD
R6
1K
IN-D
OUT-D
N.C.
OUT-D
EN-B,D
OUT-B
N.C.
OUT-B
IN-B
VCC
VCC
TX
RX
RTS
N.C.
CTS
X1
X2
.1UF
MAX3100CEE
(QSOP)
GND
3
.1UF
C32
DIN
DOUT
SCLK
CS
N.C.
IRQ
SHDN
GND
U43
SOCKET REQ'D
1
2
3
4
5
6
7
8
OUT-B
RX
RP2C
RP1D
3.3K
GND
74ACT08
U30
2
1
RP1E
3.3K
SIRQ-
PHASE-
PHASE+
TP7
SIRQ-
R10
1K
STD0
SRD0
SCK0
SC02
PHASE+
ENA422
SERVO-
PHASE-
SERVO+
PHASE+
1
6
+5V
1
5
C14
10UF
16V
(TANT)
5
3
1
5
+3P3V
10
2
3
4
5
6
7
8
9
1
2
+5V
2
1
1
2
1
2
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
ABOVE AGREEMENT.
1
.1UF
.1UF
C96
C95
GND
RP3E
3.3K
C94
22pf
CTS
RTS
RXD
TXD
C1-
C1+
+V
E17
E18
R14
15K
GND
C2-
CTS
RTS
RXD
TXD
8
7
13
14
5
4
6
.1UF
C97
AuxCTS
AuxRTS
AuxRxD-
AuxTxD-
422_RD422_RD+
422_SD422_SD+
422_CS+
422_CS422_RS+
422_RS-
.1UF
.1UF
C98
10
1
CTSRXEN-
9
10
V-
TXEN
CTS
RTS
RXD
TXD
C2-
C2+
74ACT08
(SO14)
U38C
RXEN
CTS
RTS
RXD
TXD
+5V
8
18
SERVOSERVO+
PHASEPHASE+
ON = ENABLE `PHASE & SERVO' FROM `P1'
OFF = DISABLE `PHASE & SERVO' FROM `P1'
N.C.
MainDTR
MainTXDMainCTS
MainRXDMainRTS
MainDSR
N.C.
GND
625-0SH3
625-0SH2
SHEET3
SHEET2
R_SERVOR_SERVO+
R_PHASER_PHASE+
CHGND
1
6
2
7
3
8
4
9
5
Date:
Size
D
Monday, January 14, 2002
603625-322A
Document Number
Sheet
1
of
3
Rev
-
UMAC-CPCI-CPU, DSP56309 CPU SECTIO
Delta Tau Data Systems, Inc.
E1B EMPTY = ENABLE `PHASE & SERVO' FROM `J12/J12A'
ON = ENABLE `PHASE & SERVO' FROM `P2'
OFF = DISABLE `PHASE & SERVO' FROM `P2'
Title
GND
2 R_SERVO4 R_SERVO+
6 R_PHASE8 R_PHASE+
E1B 2 TO 3
E1B 2 TO 3
33SIP8I
RP15
E1B 2 TO 1
E1B 2 TO 1
1
3
5
7
MainTxDMainCTS
MainRxDMainRTS
MainCTS
MainRTS
MainRxD-
MainTxD-
GND
J4
MainCTS
MainRxD8
9
MainTxD-
MainRTS
14
.1UF
.1UF
C104
.1UF
C105
15
6
5
7
C106
422_RD422_RD+
422_SD422_SD+
422_CS+
422_CS422_RS+
422_RS-
AuxCTS
AuxRTS
AuxRxD-
AuxTxD-
RT. angle through (JRS232)
J4
Front Panel
DB9F
ENA422
11
C1-
C1+
+V
U29
2
2
LTC1384CS
(SOL18)
13
12
4
2
3
E18
RXD
1
E17
RTS-
TXD
.1UF
.1UF
C103
C102
3
1
3
JUMP 1 TO 2 TO ENABLE "RS232" TRANSCEIVER
JUMP 2 TO 3 TO ENABLE "RS422" TRANSCEIVER
JUMP 1 TO 2 TO DIS PHASE,SERVO,INIT ON `J2'
JUMP 2 TO 3 TO ENA PHASE,SERVO,INIT ON `J2'
R15
15K
VC2+
C99
E1A 2 TO 1 = ENABLE `CARD0'
E1A 2 TO 3 = DISABLE `CARD0'
1KSIP10C
9
10
12
11
3
1
2
U28
MAX3232ECWE
(SOL16)
|Link
|625-0SH2.sch
|625-0SH3.sch
NOTE:
RP25
RP3A
3.3K
22pf
C93
10
16
VCC
VSS
15
SCHEMATICS
2
3
4
5
6
7
8
9
10
1
9
8
7
6
5
4
3
2
5
3
5
6
2
1
1
1
1
2
1
6
9
8
7
6
5
4
3
2
1
17
VCC
VSS
16
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
1
2
10
23
24
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
+5V
BA12
BA08
BA05
BX/Y
BA00
N.C.
IREQ3MEMCS0CS12CS2(KEY)
(KEY)
(KEY)
{BD31}
{BD27}
{BD24}
BD21
BD18
BD14
BD10
BD06
BD03
BD00
+5V
+12V
BA13
+5V
BA06
GND
BA01
GND
WAITGND
CS14GND
(KEY)
(KEY)
(KEY)
GND
{BA28}
GND
DB22
GND
BD15
BD11
BD07
+5V
BD01
+3.3V
PWRGUD
{BA14}
BA09
V(I/O
RESET+3.3V
SERVOSERVO+
MEMCS1+3.3V
CS3(KEY)
(KEY)
(KEY)
BRD{BA29}
{BA25}
+3.3V
BD19
BD16
BD12
+3.3V
BD04
V(I/O)
N.C.
-12V
+5V
BA10
GND
BA03
GND
WDO
GND
IREQ1GND
CS4(KEY)
(KEY)
(KEY)
BWRGND
{BD26}
GND
{BD20}
GND
BD13
BD08
BD05
+5V
N.C.
+5V
{BA15}
BA11
BA07
BA04
BA02
PHASEPHASE+
IREQ2CS16CS10(KEY)
(KEY)
(KEY)
+3.3V
{BD30}
+3.3V
BD23
+3.3V
BD17
+3.3V
BD09
+3.3V
BD02
+5V
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
BA13_B
BD01_B
BD15_B
BD11_B
BD07_B
BD22_B
CS14-
WAIT2-
BA01_B
BA06_B
GND
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
CONN175-CPCI
J1-6
BD13_B
BD08_B
BD05_B
BD20_B
BWR_B-
CS4-
E1
E2 BA12_B
E3 BA08_B
E4 BA05_B
E5 BX/Y_B
E6 BA00_B
E7
E8 IREQ3E9 MEMCS0E10 CS12E11 CS2E12
E13
E14
E15
E16
E17
E18 BD21_B
E19 BD18_B
E20 BD14_B
E21 BD10_B
E22 BD06_B
E23 BD03_B
E24 BD00_B
E25
CONN175-CPCI
J1-5
CONN175-CPCI
J1-4
BA03_B
WDO_B
IREQ1-
C1 PWRGUD
C2
C3 BA09_B
C4 V_I/O
C5 RESET_B
C6
C7 SERVO_BC8 SERVO_B+
C9 MEMCS1C10
C11 CS3C12
C13
C14
C15 BRD_BC16
C17
C18
C19 BD19_B
C20 BD16_B
C21 BD12_B
C22
C23 BD04_B
C24 V_I/O
C25
CONN175-CPCI
J1-3
CONN175-CPCI
J1-2
BA10_B
A1
A2
A3 BA11_B
A4 BA07_B
A5 BA04_B
A6 BA02_B
A7 PHASE_BA8 PHASE_B+
A9 IREQ2A10 CS16A11 CS10A12
A13
A14
A15
A16
A17
A18 BD23_B
A19
A20 BD17_B
A21
A22 BD09_B
A23
A24 BD02_B
A25
CONN175-CPCI
J1-1
J1
+5V
+5V
EQU_2-
+3P3V
+5V
GND
GND
GND
GND
GND
GND
GND
+5V
+12V
+3P3V
+3P3V
+3P3V
+3P3V
+5V
GND
GND
GND
GND
EQU_2MEMCS0CS12CS2-
CS14-
WAIT2-
CS3-
MEMCS1-
PWRGUD
CS4-
IOCS_A-
IOCS_AD0
D1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
U20
T/R1
B0
B1
GND
B2
B3
VCCB
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BRDBD00_A
BD01_A
+5V
C52
GND
GND
IOCS_B-
IOCS_BD0
D1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
U22
T/R1
B0
B1
GND
B2
B3
VCCB
B4
B5
GND
B6
B7
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BRDBD00_B
BD01_B
+5V
C74
GND
PHA
PHA
R9 100
1
U25
VCC
C82
+5V
GND
.1UF
C48
.1UF
C47
.1UF
C46
.1UF
C45
BA12
BA13
BA04
BX/Y
BA02
BA03
D22
D23
BA00
BA01
D20
D21
D18
D19
D16
D17
D14
D15
D12
D13
D10
D11
D6
D7
D8
D9
D4
D5
D2
D3
BA06
BA07
BA08
BA09
BA10
BA11
WDO
RESET_A
+3P3V
+3P3V
+3P3V
+3P3V
T/R
OE
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
VCC
GND
+5V
GND
PI74FCT245TL
(TSSOP20)
1
19
2
3
4
5
6
7
8
9
U52
IDT74FCT164245TPA
(TSSOP48)
IDT74FCT164245TPA
(TSSOP48)
U21
48
T/R1
47 OE1
B0
46 A0
B1
45 A1
GND
44 GND
B2
43 A2
B3
A3
42
VCCB
VCCA
41
B4
40 A4
B5
39 A5
GND
38 GND
B6
37 A6
B7
36 A7
B8
35 A8
B9
34 A9
GND
33 GND
B10
A10
32
B11
31 A11
VCCB
30 VCCA
B12
29 A12
B13
28 A13
GND
GND
27
B14
26 A14
B15
25 A15
T/R2
OE2
OE1
A0
A1
GND
A2
A3
VCCA
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCCA
A12
A13
GND
A14
A15
OE2
20
10
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C51
.1UF
C127
BA06_B
BA07_B
BA08_B
BA09_B
BA10_B
BA11_B
WDO_B
RESET_B
BA12_B
BA13_B
C49
+5V
.1UF
+5V
R18
+3P3V
3.3K
BX/Y
BA04
BA05
BA02
BA03
BA04_A
BX/Y_A
BA02_A
BA03_A
D20
D21
D18
D19
D16
D17
D14
D15
D12
D13
D10
D11
D6
D7
D8
D9
D4
D5
D2
D3
D22
D23
BA00
BA01
.1UF
BD20_A
BD21_A
+3P3V
+3P3V
+3P3V
BD22_A
BD23_A
BA00_A
BA01_A
C50
+5V
.1UF
+5V
.1UF
BD18_A
BD19_A
BRDBD16_A
BD17_A
BD14_A
BD15_A
BRD-
BD12_A
BD13_A
BD10_A
BD11_A
BD06_A
BD07_A
BD08_A
BD09_A
BD04_A
BD05_A
BD02_A
BD03_A
IDT74FCT164245TPA
(TSSOP48)
IDT74FCT164245TPA
(TSSOP48)
U23
48
T/R1
47 OE1
B0
46 A0
B1
45 A1
GND
44 GND
B2
43 A2
B3
A3
42
VCCB
VCCA
41
B4
40 A4
B5
39 A5
GND
38 GND
B6
37 A6
B7
36 A7
B8
35 A8
B9
34 A9
GND
33 GND
B10
A10
32
B11
31 A11
VCCB
30 VCCA
B12
29 A12
B13
28 A13
GND
GND
27
B14
26 A14
B15
25 A15
T/R2
OE2
OE1
A0
A1
GND
A2
A3
VCCA
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCCA
A12
A13
GND
A14
A15
OE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C75
BA02_B
BA03_B
BX/Y_B
BA04_B
BA05_B
C77
+5V
.1UF
+5V
.1UF
BD20_B
BD21_B
BD22_B
BD23_B
BA00_B
BA01_B
C76
+5V
.1UF
+5V
.1UF
BD18_B
BD19_B
BRDBD16_B
BD17_B
BD14_B
BD15_B
BRD-
BD12_B
BD13_B
BD10_B
BD11_B
BD06_B
BD07_B
BD08_B
BD09_B
BD04_B
BD05_B
BD02_B
BD03_B
ENA_P1-
SER
SERVO
PHASE
ENA_P1-
SER
SERVO
PHASE
R19 100
4
3
2
1
4
3
2
GND
A
B
VCC
ADM1485JR
(SO8)
DI
DE
RE
RO
U26
A
B
GND
ADM1485JR
(SO8)
DI
DE
RE
RO
C83
.1UF
5
6
7
8
5
6
7
.1UF
8
GND
PHASE_B-
SERVO_B+
SERVO_B-
PHASE_B+
SCL
BSA02
PWRG
HPBD0
HPBD2
HPBD4
HPBD6
HR/W
BSA00
CPCIDPRCS00CS04CS0BWR_ASERVO
RESET_A
19.6608Mhz
SCL
BSA02
PWRG
HPBD0
HPBD2
HPBD4
HPBD6
HR/W
BSA00
CPCIDPRCS00CS04CS0BWR_ASERVO
RESET_A
19.6608Mhz
HW25-09-GD-450-SM
GND
+5V
+12V
+5V
GND
HW20-09-GD-450-SM
BD00_A
BD02_A
BD04_A
BD06_A
BD08_A
BD10_A
BD12_A
BD14_A
BD16_A
BD18_A
BD20_A
BD22_A
BA00_A
BA02_A
BA04_A
BA06_A
BA08_A
BA10_A
BA12_A
BX/Y_A
SSM-125-L-DV-LC
SCL
BSA02
GND
+5V
+12V
RESET_A
19.6608Mhz
+5V
GND
HPBD0
HPBD2
HPBD4
HPBD6
HR/W
BSA00
CPCIDPRCS00CS04CS0BWR_A-
GND
GND
BD00_A
BD02_A
BD04_A
BD06_A
BD08_A
BD10_A
BD12_A
BD14_A
BD16_A
BD18_A
BD20_A
BD22_A
BA00_A
BA02_A
BA04_A
BA06_A
BA08_A
BA10_A
BA12_A
BX/Y_A
SSM-120-L-DV-LC
PWRG
IRQB-
EQU_1-
BA00_A
BA02_A
BA04_A
BA06_A
BA08_A
BA10_A
BA12_A
BX/Y_A
BD00_A
BD02_A
BD04_A
BD06_A
BD08_A
BD10_A
BD12_A
BD14_A
GND
-12V
+5V
+5V
+3P3V
+3P3V
+3P3V
+3P3V
IRQB-
EQU_1-
+3P3V
CS16CS10-
+5V
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
ABOVE AGREEMENT.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
GND
-5V
-12V
WAIT2-
JEXP
Modified
WAIT2-
Delta Tau Data Systems, Inc.
SDA
+5V
GND
GND
-5V
-12V
SDA
WDO
INIT-
+5V
GND
HPBD1
HPBD3
HPBD5
HPBD7
HDSBSA01
VMECS0CS02CS06CS1BRD_A-
BA01_A
BA03_A
BA05_A
BA07_A
BA09_A
BA11_A
BA13_A
BD01_A
BD03_A
BD05_A
BD07_A
BD09_A
BD11_A
BD13_A
BD15_A
Tuesday, January 15, 2002
603625-322A
Document Number
Sheet
2
3
Rev
-
Schematics
of
UMAC-CPCI-CPU, MEMORY & I/O SECTIO
Date:
Size
D
Title
BD01_A
BD03_A
BD05_A
BD07_A
BD09_A
BD11_A
BD13_A
BD15_A
BD17_A
BD19_A
BD21_A
BD23_A
BA01_A
BA03_A
BA05_A
BA07_A
BA09_A
BA11_A
BA13_A
WAIT2-
SDA
HPBD1
HPBD3
HPBD5
HPBD7
HDSBSA01
VMECS0CS02CS06CS1BRD_APHASE
WDO
INIT-
BD01_A
BD03_A
BD05_A
BD07_A
BD09_A
BD11_A
BD13_A
BD15_A
BD17_A
BD19_A
BD21_A
BD23_A
BA01_A
BA03_A
BA05_A
BA07_A
BA09_A
BA11_A
BA13_A
WAIT2-
HPBD1
HPBD3
HPBD5
HPBD7
HDSBSA01
VMECS0CS02CS06CS1BRD_APHASE
WDO
INIT-
HEADER 25X2(MALE)
HW2515GD450SM
SOLDER SIDE
DIRECTLY UNDER J12
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
(JEXP_B)
J12A
HEADER 20X2(MALE)
HW2015GD450SM
SOLDER SIDE
DIRECTLY UNDER J11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
(JEXP_A)
J11A
HEADER 25X2(FEM)
CLS125LDDV
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
(JEXP_B)
J12
HEADER 20X2(FEM)
CLS120LDDV
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
(JEXP_A)
J11
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
CHGND
1
2
3
4
5
6
0.1uF
C20
GND
BEAD
L5
USBDM
USBDP
HOLE
M3
HOLE
M4
HOLE
0.1uF
CE3
0.1uF
CE4
0.1uF
R28
CHGND
M2
1M
HOLE
0.1uF
CE2
Schematics
GND
M1
CE1
OPTION 1
Ethernet Option
USB-B
VCC
DD+
GND
shell
shell
J3
U62
GND
A
C GND
GND
B
D GND
SN75240PW
1
2
3
4
8
7
6
5
GND
GND
C175
0.1uF
C176
2.2UF
R30
R29
R31
Avcc
24.3
24.3
1.5K
USBRST-
1
2
3
4
5
6
7
8
1:1.41
ST7011
16
15
(1-3)(16-14)1:1 14
13
12
11
(6-8)(11-9)1:2.5 10
9
U32
HREQ-
+3P3V
U65
+3P3V
GND
U64
EthTxF+
EthTxF-
EthRxF+
4
U73
2
1
2
1
NC7SZ00
EQU_1
GND
EthRxF-
NC7SZ02M5
(SOT32-5)
4
NC7SZ02M5
(SOT32-5)
4
2
HOSTENANC7SZ00M5
1
ETHENA-
5
+3P3V
5
3
+5V
IPOS
WDO
EQU_1
GND
4
GND
2
2
2
2
2
1
E18D
E18C
E18B
E18A
2
1
GND
1
3
1
3
1
3
1
3
IPOS
U61
+5V
WDO
USBRD-
PSEN-
EthExtTxF+
EthExtTxF-
EthExtRxF+
EthExtRxF-
EQU_1-
Q6
4
3
SOT23
NC7SZ00M5
RAMENA-
5
3
2N7002
INIT-
+3P3V
U58
RJ45
10
9
8
7
6
5
4
3
2
1
J7
NC7SZ08M5
2
1
.1UF
GND
U57
GND
+3P3V
C160
NC7SZ08M5
2
1
5
3
5
3
4
4
RAMCSRAMOE-
PWRG
NMI-
TCK_USB
TMS_USB
TDO_USB
TDI_USB
BSC_USB-
XIN_7
GND
-12V
+12V
+5V
+3P3
USBD0
USBD1
USBD2
USBD3
USBD4
USBD5
USBD6
USBD7
PWRG
ENA_P1-
XIN_6
TBD_0
ENA_P2-
E_51
XIN_3
XIN_4
XIN_5
CARD0
40/60
XIN_2
-5V
+12V
-12V
XIN_1
NMI-
Q7
3
SOT23
MMBD301LT1
(SOT23)
D13
8
10
5
3
+5V
VDD
OUT1
OUT2
OUT3
OUT4
DOUT
PGND
MAX8215CSD
(SO14)
VREF
GND
+5V
-5V
+12V
-12V
DIN
U66
FBR12ND05
1
12
9
4
K1
U6
T/R
OE
A0
A1
A2
A3
A4
A5
A6
A7
C192
C193
1SMC18AT3
D12
1SMC18AT3
D11
C195
C194
1SMC5.0AT3
D10
1SMC5.0AT3
D9
B0
B1
B2
B3
B4
B5
B6
B7
VCC
GND
PI74FCT245TL
(TSSOP20)
1
19
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
2N7002
+5V
3
1
1
2
U54
1
2
3
5
3
10
+3P3V
5
3
1
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
GND
+5V
10UF
25V
(TANT)
10UF
25V
(TANT)
+
10UF
16V
(TANT)
+
10UF
16V
(TANT)
+
20
10
18
17
16
15
14
13
12
11
C191
.1UF
E4
E3
2
GND
VR1
VI
VO
(TAB IS INPUT)
(SOT223)
LT1175CST-5
TP4
+12V
HPBD0
HPBD1
HPBD2
HPBD3
HPBD4
HPBD5
HPBD6
HPBD7
HSIP8NO5
E2
E3
E4
3
TP5
-12V
(jisp_b)
J10
+5V
1 SDO
2 SDI
3 ispEN4
MODE
6 GND
7 SCLK
8
TP1
GND
GND
HPBD0
HPBD1
HPBD2
HPBD3
HPBD4
HPBD5
HPBD6
HPBD7
C28
.01UF
+5V
ENA_P1-
ENA_P2-
E2
J10
.1UF
2
E11
1 E11
REMOVE `E11' FOR
DIGITAL ONLY USE
C190
GND
CARD0
RP22
3.3KSIP10C
14
13
12
11
10
9
8
+5V
WD_NO
WD_NC
WD_COM
GND
1
9
8
7
6
5
4
3
2
+
+
C196
.1UF
TP6
-5V
TP3
+5V
TP2
+3P3
GND
-5V
-12V
+12V
GND
+5V
GND
+3P3V
GND
422_RS422_SD+
MainRTS
R_PHASE+
AuxRTS
EthExtRxF-
R_PHASEINIT422_RS+
422_SDMainTxD-
AuxTxD-
EthExtRxF+
WD_NC
WD_COM
422_CS422_RD+
MainCTS
R_SERVO+
AuxCTS
EthExtTxF-
WD_NO
422_CS+
422_RDMainRxD-
+5V
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
GND
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
SERVO+
MainDTR
422_CS422_RD+
MainCTS
USBDP
AuxDTR
AuxCTS
EthExtTxF-
WD_NO
GND
GND
+5V
+5V
GND
WD_COM
PHASEINIT422_RS+
422_SDMainTXD-
AuxTXD-
USBDM
EthExtRxF+
WD_NC
422_RS422_SD+
MainRTS
PHASE+
AuxRTS
EthExtRxF-
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
n.c.
GND
CONN154-CPCI
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
J2-6
CONN154-CPCI
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
J2-5
CONN154-CPCI
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
J2-4
CONN154-CPCI
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
J2-3
CONN154-CPCI
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
J2-2
CONN154-CPCI
SERVOMainDSR
422_CS+
422_RDMainRXD-
AuxDSR
AuxRXD-
EthExtTxF+
Delta Tau Data Dystems, Inc.
2.0/Ethernet UMAC-CPCI Communication
422_RS422_SD+
MainRTS
R_PHASE+
AuxRTS
R_PHASEINIT422_RS+
422_SDMainTxD-
AuxTxD-
422_CS422_RD+
MainCTS
R_SERVO+
AuxCTS
422_CS+
422_RDMainRxD-
AuxRxDR_SERVO-
J2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
J2-1
Tuesday, January 15, 2002
603625-322A
Document Number
Sheet
3
of
3
Rev
-
25
UMAC-CPCI-CPU, USB/2.0/Ethernet Sectio
Date:
Size
D
Title
AuxRxDR_SERVO-
EthExtTxF+
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22