MXV22 DISK CONTROLLER MANUAL

MXV22 DISK CONTROLLER MANUAL
MXV22
DISK CONTROLLER
MANUAL
PREFACE
The purpose of this manual is to provide the user adequate
information
to configure and operate the MXV22 floppy disk controller. The
information provided should clarify the controller connection to
any
Shugart compatible drive and assist in the selection of
associated
interface options. Both register definition and command
protocol are
provided for reference and as an aid in development of user
software.
Operational procedures outline the use of the controller
features as
well as explaining operation in an RT-11 or RSX11M software
environment.
SECTION 1
GENERAL
INFORMATION
1. INTRODUCTION
____________
The MXV22 is a dual density controller compatible with the DEC*
RX02
floppy disk system. The MXV22 emulates two separate RXV21
controllers,
each of which controls two 8-inch floppy disk drives. When
configured
with any Shugart compatible drive, it is a direct replacement
for two
complete RX02 subsystems. The controller provides either single
density encoding compatible with IBM 3740 equipment or double
density
encoding providing up to 1 Mbyte of storage on a single
diskette.
All electronics are contained on one dual-height board which
plugs
directly into any standard LSI-11 backplane and interfaces
through a 50
conductor ribbon cable with up to four (4) Shugart compatible
drives.
All controllers are 100% tested and ready for operation. The
primary
controller registers are configured for the standard device
address
177170 U8 D and interrupt vector 264 U8 D. The secondary
controller registers
are configured with a device address of 177174 U8 D and
interrupt level is
factory set to level four. Features include:
.22 bit addressing
.Transparent firmware bootstrap automatically loads either
single
or double density diskettes.
.Formatting capabilities permit writing sector headers, checking
the written headers, and writing the data fields in the user
selected density.
.Jumper selection of both alternate address and vector.
.Jumper selectable four-level device interrupt priority
compatible
with the LSI-11/23.
.Provides power fail protection for data integrity.
.Write current control signal for tracks greater than fortythree.
.Write precompensation for reduced error rates.
*DEC, PDP-11 LSI-11, RSX, Unibus & Q bus are registered
trademarks of
Digital Equipment Corporation.
1
1.1. COMPONENTS
__________
The controller is provided with the following components:
P/N 81010-07-2
M 81010-02-2
1.2. COMPATIBILITY
Floppy disk controller
MXV22 disk controller manual
_____________
This section discusses the aspects of hardware, software and
media
compatibility with Digital Equipment's RX02 system. The
information
will aid the user in data interchanging with foreign systems.
Hardware
________
The controller is compatible with the LSI-11, LSI-11/2 and LSI11/23
processors. All circuitry is contained on one dual-wide board
that
plugs directly into any standard LSI-11 backplane.
Alternate
address
selection and a four-level device interrupt priority scheme
provide the
user added flexibility for expanded system configurations.
Shugart
compatible drive logic is interfaced through a 50-pin ribbon
cable.
The connector pins are compatible with both the 800 and 850
series
drives.
Software
________
The MXV22 is completely compatible with RXV21 register
definition and
command protocol. All DEC-supplied software designed to operate
with
the RX02 system will operate with the controller without
modification.
Media
_____
The media used with the MXV22 are
compatible with the IBM 3740
family
of equipment. Either preformatted or blank soft sectored
diskettes may
be used with the controller. The following list summarizes the
suggested media.
IBM
DEC
Single or Double Density
RX01/RX02
2
1.2.1. Logical Track Format
____________________
The diskette surface is divided into 77 concentric tracks
numbered
0-76.
Each track consists of 26 sectors numbered 1-26.
The
track
begins and ends at the index address mark. The track is
formatted in
such a way that this "soft" index is preceded by the leading
edge of
the physical index hole in the diskette. Following the physical
index
are 40 bytes of "FF" data, 6 bytes of "0" data, and the index
address
mark indicating the beginning of the track. Following the index
address mark is the post index gap consisting of 26 bytes of
"FF" data
and 6 bytes of "0" data. The next field is the sector header
for
sector 1. Following the data field is the data gap consisting
of 28
bytes of "FF" data and 6 bytes of "0" data. This field leads to
the
next sector header. Following the 26th data record is the preindex
gap consisting of approximately 274 bytes of "FF" data.
Each track is formatted in the above manner.
1.
Refer to Figure 1-
The
sector header field of each sector contains information
describing the
sector number, track number, and diskette side. All the above
fields
are recorded in FM except as noted in the following sections.
Figure 1-1:
Logical Track Format
3
1.2.2. Sector Header Field
___________________
The header field consists of 7 bytes of information.
Preceding
the
header is a field of 6 bytes of "zero" data for synchronization.
The
header and this preamble are always recorded in FM.
1.
Byte 1. ID Address Mark - A unique mark
consisting of 1 byte of FE (hex) data with
three missing clock-transitions using a C7
(hex) clock pattern. This mark is decoded by
the controller and indicates the start of the
sector header.
2.
Byte 2. Track Address - This byte indicates
the absolute (0-114 U8 D) track address. Each
sector contains this track information to
locate its position on one of the 77 tracks.
3.
Byte 3. Side - This byte indicates the
diskette side (0 or 1).
4.
Byte 4. Sector Address - This byte indicates
the absolute (1-32 U8 D) sector address. Each
sector contains this information to identify
its position on the track.
5.
Byte 5.
6.
Byte 6, 7. CRC - This is the 16 bit cyclic
redundancy character and is calculated for
each header from the first 5 bytes of
information, using the IBM 3740 polynomial.
(Refer to Cyclic Redundancy Check, Section
1.2.7.).
1.2.3. Data Field
"Zero"
__________
The data field consists of either 131 U10 D or 259 U10 D bytes
of information
depending upon the recording method. Preceding the data field
is a
field of 6 bytes of "zero" data for synchronization.
The preamble and data address mark are always written in FM.
The user
data and CRC character are either written in FM or MFM modified
depending upon the formatted diskette density.
4
1.
Byte 1. Data Address Mark - A unique mark consisting of a
data byte (see Table 1-1) with three missing clock
transitions using a C7 (hex) clock pattern. This byte is
always written in FM and is decoded by the controller to
indicate the start of the data field, its recording method
(FM vs MFM), and if the field is a deleted data field.
-----------------------------------------------| ADDRESS
| INDICATED | DATA
| CLOCK
|
|
MARK
|
DENSITY
|
|
|
|------------------------------------------------|
|------------------------------------------------|
| INDEX
|
NA
|
FC
|
D7
|
|------------------------------------------------|
|
ID
|
NA
|
FE
|
C7
|
|------------------------------------------------|
|
|
FM
|
FB
|
C7
|
|
DATA
|----------------------------------|
|
|
Modified |
FD
|
C7
|
|------------------------------------------------|
| DELETED
|
FM
|
F8
|
C7
|
|
DATA
|----------------------------------|
|
|
Modified |
F9
|
C7
|
-----------------------------------------------Table 1-1:
Address Marks
2.
Bytes 2-129 (FM) or Bytes 2-257 (MFM Modified). User Data.
This field is recorded in either FM or MFM modified.
Depending upon the encoding scheme, either 128 or 256 bytes
of information can be stored.
3.
Bytes 130-131 or 258-259. CRC - This is the 16 bit cyclic
redundancy character and is calculated for each data field
from the first 129 or 257 bytes of information using the
IBM
3740 polynomial.
(Refer to Cyclic Redundancy Check,
Section
1.2.7.). These bytes are recorded with the same encoding
scheme as the data field.
1.2.4. Recording Scheme
________________
Two recording schemes are used by the MXV22:
double frequency
(FM) and
DEC modified Miller code (MFM).
FM is used for single density
recording and is compatible with IBM 3740 or DEC RX01 media.
DEC
modified MFM is used for recording double density and is only
compatible with the DEC RX02 system.
5
1.2.5. Double Frequency (FM)
_____________________
FM recording is characterized by a flux transition at the
beginning of
each bit cell which is commonly termed a clock pulse or
transition as
shown in Figure 1-2. A logic "one" is represented by a flux
transition
withing the bit cell; a logic "zero" is represented by the lack
of any
flux transition within a bit cell. In FM the bit cell time is
4us.
"0"
_
| |
"0"
_
| |
_
| |
"1"
_
| |
"0"
_
| |
_
| |
"1"
_
| |
"0"
_
| |
_
|
|
--
-------
-------
--
--
-------
--
--
-------
-C
|
-->|
|
bit
cell
4us
C
|
|<-|
C
D
Figure 1-2:
1.2.6. DEC Modified MFM
C
C
D
C
C
FM Recording Characteristics
________________
MFM recording consists of flux transitions for a logic "one" and
no
flux transitions for a logic "zero".
A clock transition only
occurs
between two consecutive logic "zeros" as shown in Figure 1-3
below.
The MFM bit cell time is 2us.
"1"
"1" "0"
"0" "1"
"0"
"1"
"1"
_
_
_
_
_
_
| |
| |
| |
| |
| |
| |
--------------------------D
D
C
D
D
D
| bit |
-->| cell|<-| 2us |
Figure 1-3:
MFM Recording Characteristics
6
Table 1-2 summarizes the standard MFM encoding algorithm.
-----------------------------------------------|
DATA
|
ENCODED DATA
|
|------------------------------------------------|
| DN-1
DN
|
DN-1
CN
DN
|
|------------------------------------------------|
|
0
0
|
0
1
0
|
|
1
0
|
1
0
0
|
|
0
1
|
0
0
1
|
|
1
1
|
1
0
1
|
-----------------------------------------------Table 1-2:
Standard MFM Encoding
Because single density headers are used for both FM and MFM
recording formats, and since certain MFM patterns map into
single
density address marks, a modified algorithm is used.
The
mapping
occurs when a data pattern of exactly four consecutive
"ones" is
encoded.
Whenever this pattern is encoded a special
algorithm is
applied. Table 1-3 defines the encoding algorithm for this
special case.
---------------------------------------------------------|
DATA
|
|----------------------------------------------------------|
|
DN-5
| DN-4
|
DN-3
|
DN-2
|
DN-1
|
DN
|
|----------------------------------------------------------|
|
0
|
1
|
1
|
1
|
1
|
0
|
|----------------------------------------------------------|
|
X
0
| 1
0
|
0
0
|
1
0
|
0
0
|
1
0
|
|CN-5 DN-5|CN-4 DN-4|CN-3 DN-3|CN-2 DN-2|CN-1 DN-1| CN
DN
|
|----------------------------------------------------------|
|
|
ENCODED DATA
---------------------------------------------------------Table 1-3:
Modifying Algorithm (Special Case)
When reading double density data fields the controller
checks for
a missing clock bit between two zero data cells, and if
found,
substitutes ones for the two zero data bits (generated by
the
special encoding algorithm).
1.2.7. Cyclic Redundancy Check
_______________________
Each sector header field and data field has two byte CRC
character
appended. This 16 bit character is the remainder that results
when
dividing the data bits [represented as a polynomial M(x)] by a
generator polynomial G (x). The polynomial used for IBM 3740 is
G(x) =
X D16 U+ X D12 U+ X D5 U+ 1. For the sector header the data
bits include byte 1
thru 5. For an FM data field the data bits include byte 1 thru
byte
129. For an MFM data field the data bits include byte 1 thru
byte 257.
7
1.3. SPECIFICATIONS
______________
RECORDING TECHNIQUE:
Single Density
Double Density
IBM 3740 FM
DEC Modified MFM
POWER REQUIREMENTS:
Voltage
Current
Single 5V supply
(from LSI-11 backplane)
2.5A typical
ENVIRONMENTAL
Temperature
Humidity
0 degree - 45 degrees C
10% - 95% non-condensing
8
SECTION
2
INSTALLATION
2. GENERAL
_______
The controller is shipped with standard options configured. The
standard address 177170 U8 D and vector 264 U8 D are set. The
device interrupt
priority is set to level four. The firmware bootstrap is
disabled.
Most options are factory foil-etched to the most often used
configuration. The foil jumpers must first be cut before the
alternate
jumpers are inserted. Refer to Tables 2-1, 2-2, and 2-3 for
alternate
options and Figure 2-1 for jumper location. Several of the
options are
selectable by using AMP 530153-2 pin jumpers. If these pin
jumpers are
not available use #30 wire wrap.
2.1. CONFIGURATION
_____________
2.1.1. Address Vector Selection
________________________
The controller is shipped with the DEC standard device address
and
vector assignments preset to 177170 U8 D and 264 U8 D,
respectively. Any
change in these assignments would necessitate a change in system
software. However, a dual address and vector option is
selectable
enabling a second register assignment at 177174 U8 D and
270 U8 D,
respectively.
The dual address mode is used in applications requiring more
than two
drives.
In this case the controller simulates the operation of
two
controller as required by standard DEC software.
To select this
option
remove the jumper between W16 and W17.
jumper W7
to W8 as shown in Table 2-1.
9
Jumper W15 to W16 and
-------------------------------------------------|
|
JUMPERS
|
|
OPTION
|------------------------------|
|
| 15-16 | 16-17 |
7-8
|
|--------------------------------------------------|
| Standard
|
|
|
|
| Address/Vector* |
OUT
|
IN
|
OUT
|
| 177170/264
|
|
|
|
|--------------------------------------------------|
| Dual
|
|
|
|
| Address/Vector
|
IN
|
OUT
|
IN
|
| 177170/264
|
|
|
|
| 177174/270
|
|
|
|
|--------------------------------------------------|
| *Factory Preset
|
-------------------------------------------------Table 2-1:
2.1.2. Device Interrupt Priority
Address/Vector Option Configuration
_________________________
The MXV22 supports the four-level device interrupt priority
scheme
compatible with the LSI-11/23. The controller asserts interrupt
requests and monitors higher level request lines during
interrupt
arbitration as described in Table 2-2. The level four request
is
always asserted by the controller, regardless of its priority,
to
maintain compatibility with the LSI-11 and LSI-11/2 processors.
The interrupt priority level is configured to level four at the
factory. If a different interrupt level is desired the
following
foil-etched jumpers must be cut. Refer to Table 2-2 for the
proper
jumpers to insert for the desired priority level.
W19 - W20
W22 - W23
W24 - W25
W28 - W29
W30 - W31
------------------------------------------------------------------------|PTY|ASRT |MON
|________________________JUMPERS____________________________|
_______
|LEV|
|
|18-19|19-20|21-22|22-23|24-25|25-26|27-28|28-29|3031|31-32|
|-------------------------------------------------------------------------|
| 4*| 4 |5,6 | Out | In | Out | In | In | Out | Out | In | In
| Out |
|-------------------------------------------------------------------------|
| 5 | 4,5 | 6 | Out | In | In | Out | In | Out | Out | In | Out
| In |
|-------------------------------------------------------------------------|
| 6 | 4,6 | 7 | In | Out | Out | In | Out | In | In | Out | In
| Out |
|-------------------------------------------------------------------------|
| 7 |4,6,7|None| In | Out | In | Out | Out | In | In | Out | Out
| In |
|-------------------------------------------------------------------------|
| *Factory Preset
|
------------------------------------------------------------------------Table 2-2:
Priority Level Configuration
10
Factory Test
--------\
/
\
/
---------------------------++++++++++++++++++++++++--|
||||||||||||||||||||||||
|
|
W35
|
|
W1 W2 W3
*
|
|
* * *
* * * *
|
|
W44 45 33 34
|
|
|
|
|
|
W6
|
|
*
|
Factory
|
W5
|
|
|
|
|
22 Bit |
Address |
|
|
|
|
*
W4
*
|
|
|
|
|
|
|
|
|
|
Test
W7
*
W47 48 W8
* * *
*
W9
Address
|
Selection
Step
Rate
|
|
|
|
|
|
W36
*
*
W37
39
*
*
38
|
|
|
|
|
Write
|
|
PrecomBootpensation
Strap
Interrupt
TBS7
Priority
|
|
|
|
|
|
|
W41
W15
|
*
*
* * * *
W42 43 17 16
W10
|
*
|
*
* * *
W14 13 12
W20 19 18
* * *
*
*
*
W23 22 21
|
|
|
|
|
|
|
|
|
|
|
|
|_
|
|
W11
|
W24 30 29
|
* * *
|
_
W25 31 28
|
__| |
* * *
_|
|
|
* * *
|
|
|
W26 32 27
|
-----------------------------------------Figure 2-1:
Configuration Jumper Locations
11
2.1.3. Bootstrap
_________
The controller board incorporates a transparent firmware
bootstrap.
The bootstrap is initiated whenever program execution is started
at
location 173000 U8 D, homing all drives to track 0. Next, track
1, sector
1, of unit 0 is read and diskette density is determined. If the
diskette is single density, sectors 1, 3, 5, and 7 are loaded
into
memory starting at location 0. If the diskette is double
density,
sectors 1 and 3 are loaded. Program execution is then
transferred to
location 0. Controllers are shipped with this feature disabled.
To
enable the bootstrap remove the jumper between W42 and W43 and
insert
the jumper between W41 and W42 as shown in Table 2-3.
NOTE
____
Only one bootstrap should be enabled in a system for
proper operation. If another bootstrap exists in the
system, it must be disabled before enabling the
controller bootstrap.
-------------------------------------------------|
|
JUMPERS
|
| BOOTSTRAP
|------------------------------|
|
|
41-42
|
42-43
|
|--------------------------------------------------|
| ENABLED
|
IN
|
OUT
|
|--------------------------------------------------|
| DISABLED *
|
OUT
|
IN
|
|--------------------------------------------------|
| *Factory Preset
|
-------------------------------------------------Table 2-3:
2.1.4. Write Precompensation
Bootstrap Option
_____________________
The MXV22 controller provides hardware write precompensation to
reduce
the bit shift exhibited by all drives as the recorded flux
density
increases.
The controller recognizes the patterns which produce
bit
shift and precompensates the written pattern.
This unique
feature
allows the controller to perform reliably with any Shugart
compatible
drive.
12
Controllers are shipped with this feature enabled and it is
recommended
that for more reliable operation the feature not be disabled.
However,
if so desired, the feature can be defeated by cutting the foiletched
jumper between W12 and W13 and inserting a jumper between W13
and W14
as shown in Table 2-4.
-------------------------------------------------|
|
JUMPERS
|
|
WRITE
|------------------------------|
| PRECOMPENSATION |
12-13
|
13-14
|
|--------------------------------------------------|
| ENABLED*
|
IN
|
OUT
|
|--------------------------------------------------|
| DISABLED
|
OUT
|
IN
|
|--------------------------------------------------|
| *Factory Preset
|
-------------------------------------------------Table 2-4:
2.1.5. Step Rate Control
Write Precompensation
_________________
Up to four drives can be interfaced with the MXV22 controller.
These
drives are organized into two pairs, each of which is associated
with a
particular register set. The first pair of drives (DS1/DS2) is
associated with the primary register set (177170 U8 D) and the
remaining
pair (DS3/DS4) with the secondary register set (177174 U8 D).
The
controller is shipped configured with a 6ms step rate for both
pair of
drives. Alternate step rates can be selected for each pair of
drives.
Refer to Table 2-5 for desired step rate option and associated
jumpers.
-------------------------------------------------|
STEP RATE
|
JUMPERS
|
|-------------------|------------------------------|
| DS1/DS2 | DS3/DS4 |
36-37
|
38-39
|
|--------------------------------------------------|
|
6* |
6*
|
IN
|
IN
|
|-------------------|---------------|--------------|
|
3
|
6
|
OUT
|
IN
|
|--------------------------------------------------|
|
6
|
3
|
IN
|
OUT
|
|-------------------|---------------|--------------|
|
3
|
3
|
OUT
|
OUT
|
|--------------------------------------------------|
| *Factory Preset
|
-------------------------------------------------Table 2-5:
13
Step Rate
2.1.6. 22 Bit Addressing
_________________
The controller is shipped with 22 bit addressing disabled.
Enabling
this option provides extended address control during DMA
transactions
allowing the controller to transfer information throughout 22
bit
address space. The additional four bits of address (A U18 DA U21 D) are
communicated to the controller as described in section 3.1.2.
Before
enabling this option it is necessary to modify the corresponding
software drivers in order to maintain proper register
communication as
described in section 5. To enable 22-bit addressing jumper W46
and W47
as shown in Table 2-6.
----------------------------------|
|
JUMPERS
|
|
22 BIT
|---------------|
|
ADDRESSING
|
46-47
|
|-------------------|---------------|
| ENABLED
|
IN
|
|-------------------|---------------|
| DISABLED *
|
OUT
|
|-----------------------------------|
| *Factory Preset
|
----------------------------------Table 2-6:
2.1.7. Miscellaneous Options
22 Bit Addressing
_____________________
There are several options related to factory configuration of
the
controller.
These options must be configured as shown for
proper
operation of the controller.
Refer to Table 2-7 for these
options.
During DMA operations if the bus address established extends
into the
peripheral address page the controller asserts bank select 7
(BS7) as
required by normal bus protocol.
extend
If the application requires
memory overlapping the peripheral address page this option can
be
disabled as indicated in Table 2-7.
-------------------------------------------------------------------|
OPTION
|
JUMPERS
|
|
|-----------------------------------------------
|
| 1-2
-------|
|
2-3
|
4-5
|
5-6
| 33-34 | 34-35 |
10-11 |
|---------------------------------------------------------------------|
|
-
FACTORY*
| OUT
|
IN
|
OUT
|
IN
|
OUT
|
IN
|
|
|---------------------------------------------------------------
-------|
|
IN
BS7 ENABLED
|
-
|
-
|
-
|
-
|
-
|
-
|
|
|---------------------------------------------------------------
-------|
|
OUT
BS7 DISABLED |
-
|
-
|
-
|
-
|
-
|
-
|
|
|---------------------------------------------------------------
-------|
|
* Factory Preset
|
--------------------------------------------------------------------Table 2-7:
Miscellaneous Options
14
2.2. DRIVE CONFIGURATION
___________________
The controller provides an industry standard floppy interface
compatible with most available drives. However, for proper
operation,
each drive must be configured with attention to several options.
Tables 2-8 thru 2-12 summarize these options for several of the
more
popular drives.
------------------------------------------------------------------|
|
|
DUAL
|
| OPTION |
DESCRIPTION
| DRIVE 0
DRIVE 1
DRIVE 0 |
|-------------------------------------------------------------------|
|
DS1
| Drive select 1
|
IN
OUT
IN
|
|
DS2
| Drive select 2
|
OUT
IN
OUT
|
|
DS3
| Drive select 3
|
OUT
OUT
OUT
|
|
DS4
| Drive select 4
|
OUT
OUT
OUT
|
|
A
| Radial head loading option |
IN
IN
IN
|
|
B
| Radial head loading option |
IN
IN
IN
|
|
C
| Head load option
|
IN
IN
IN
|
|
D
| In use option
|
OUT
OUT
OUT
|
|
X
| Radial head loading option |
OUT
OUT
OUT
|
|
WP
| Inhibit write when protect |
IN
IN
IN
|
|
NP
| Allow write when protect
|
OUT
OUT
OUT
|
|
DS
| Stepper power from drive
|
IN
IN
IN
|
|
| select
|
|
|
HL
| Stepper power from head
|
OUT
OUT
OUT
|
|
| load
|
|
SINGLE
OUT
|
IN
|
IN
|
IN
|
|
Z
| In use from drive select
|
OUT
OUT
|
Y
| In use from head load
|
IN
IN
|
R
| Ready output
|
IN
IN
|
I
| Index output
|
IN
IN
|
DC
| Disk change output
|
X
X
X
|
S
| Sector output
|
X
X
X
|
800
| Sector option disable
|
IN
IN
|
801
| Sector option enable
|
OUT
OUT
|
L
| -5V DC bias
|
IN
IN
|
T1
| Termination HL
|
OUT
IN
|
T2
| Termination drive select
|
IN
IN
|
T3
| Termination direction
|
OUT
IN
|
T4
| Termination step
|
OUT
IN
|
T5
| Termination write data
|
OUT
IN
|
T6
| Termination write gate
|
OUT
IN
|
|
IN
|
OUT
|
IN
|
IN
|
IN
|
IN
|
IN
|
IN
|
IN
|
---------------------------------------------------------------
----Table 2-8:
Shugart 801/851 Drive Configuration
15
-------------------------------------------------------------------|
|
|
DUAL
|
| OPTION
|
DESCRIPTION
| DRIVE 0 DRIVE 1
DRIVE 0 |
|--------------------------------------------------------------------|
|
U9
|Terminations for multiplexed | IN
OUT
IN
|
|
|inputs
|
|
|
SI
|Internal write current switch| X
X
X
|
|
SE
|External write current switch| X
X
X
|
|
TR
|True ready output
| IN
IN
IN
|
|
RTR
|Radial true ready **
| IN
IN
IN
|
|
2S
|Two-sided status output*
| IN
IN
IN
|
|
DC
|Disk change option
| OUT
OUT
OUT
|
|
S1
|Side select option using
| OUT
OUT
OUT
|
|
|direction select *
|
|
|
S2
|Side select input *
| IN
IN
IN
|
|
S3
|Side select option using
| OUT
OUT
OUT
|
|
|drive select
|
|
|1B,2B,3B,4B|Side select option using
| OUT
OUT
OUT
|
|
|drive select
|
|
|
D
|Alternate input-in-use
| OUT
OUT
OUT
|
|
MS
|Motor on from drive select
| IN
IN
IN
|
|
MO
|Alternate input-motor-on
| OUT
OUT
OUT
|
|
MMO
|Alternate input-multiplexed | OUT
OUT
OUT
|
|
|motor on **
|
|
|
MD
|Motor off delay
| IN
IN
IN
|
SINGLE
IN
|
IN
|
IN
|
OUT
|
|
R
|Ready output
|
IN
IN
|
RR
|Radial ready
|
IN
IN
|
SR
|Standard ready **
|
IN
IN
|
MT
|Modified true ready (outputs |
OUT
OUT
|
|true ready on pin 22)**
|
|
IN
|
OUT
|
OUT
|
OUT
|
IN
|
|
DS1
|Drive select 1
|
IN
OUT
|
DS2
|Drive select 2
|
OUT
IN
|
DS3
|Drive select 3
|
OUT
OUT
|
DS4
|Drive select 4
|
OUT
OUT
|
Y
|Door lock/activity light
|
IN
IN
|activated from motor on **
|
|Door lock/activity light
|
OUT
OUT
|
|
|
OUT
Z
|
|
|activated from drive select**|
|
OUT
|
IN
|
|
PD
|Stepper power down
|
OUT
OUT
|
WP
|Inhibit write when write
|
IN
IN
|protected
|
|Allow write when write
|
OUT
OUT
|protected
|
|
|
|
OUT
NP
|
|
|
|
OUT
TS
|Data separation option select|
OUT
OUT
|
---------------------------------------------------------------
----| X
Don't Care
* 860 Drive Only
** Available on PCB Pin 25249
Only |
|
|
-------------------------------------------------------------------Table 2-9:
Shugart 810/860 Drive Configuration
16
--------------------------------------------------------------------|
|
|
DUAL
|
|
OPTION
|
DESCRIPTION
| DRIVE 0 DRIVE 1
DRIVE 0 |
|---------------------------------------------------------------------|
|
DS1
|Drive select 1
| IN
OUT
IN
|
|
DS2
|Drive select 2
| OUT
IN
OUT
|
|
DS3
|Drive select 3
| OUT
OUT
OUT
|
|
DS4
|Drive select 4
| OUT
OUT
OUT
|
|
A,B
|Radial head load
| IN
IN
IN
|
|
X
|Radial head load
| OUT
OUT
OUT
|
|
Z
|In use from drive select
| OUT
OUT
OUT
|
|
HL
|Stepper power from head load | OUT
OUT
OUT
|
|
R
|Alternate output ready pad
| IN
IN
IN
|
|
I
|Alternate output index pad
| IN
IN
IN
|
|
C
|Alternate input head load
| IN
IN
IN
|
|
D
|Alternate input-in-use
| OUT
OUT
OUT
|
|
DC
|Alternate output disk change | OUT
OUT
OUT
|
|
2S
|Alternate output 2-sided disk| IN
IN
IN
|
|
DS
|Stepper power from drive
|
|
|
| select
|
|
|
Y
|In use from head load
| IN
IN
IN
|
|
DL
|Door lock latch
| OUT
OUT
OUT
|
|
RR
|Radial ready
| IN
IN
IN
|
|
RI
|Radial index
| IN
IN
IN
|
|
WP
|Inhibit write when write
| IN
IN
IN
|
SINGLE
|
|protect
|
|Allow write when write
|
|protect
|
|D1,D2,D4,DDS|Drive address select
|
B1-B4
|
|
|
OUT
NP
OUT
OUT
|
OUT
OUT
|Two-sided drive select
|
OUT
OUT
S1,S3
|Head select option
|
OUT
OUT
|
S2
|Head select option
|
IN
IN
|
T40
|Test track 40
|
OUT
OUT
|
HA
|Test actuate head load
|
OUT
OUT
|4,6,8,10,12,|Alternate I/0 pins
|
OUT
OUT
|16,18,24
|
|
|
|
OUT
|
OUT
|
OUT
|
IN
|
OUT
|
OUT
|
OUT
|
|
|
-------------------------------------------------------------------Table 2-10:
Qume 842 Drive Configuration
17
--------------------------------------------------------------------|
|
|
DUAL
|
|
OPTION
|
DESCRIPTION
| DRIVE 0 DRIVE 1
DRIVE 0 |
|---------------------------------------------------------------------|
|
DS1
|Drive select 1
| IN
OUT
IN
|
|
DS2
|Drive select 2
| OUT
IN
OUT
|
|
DS3
|Drive select 3
| OUT
OUT
OUT
|
|
DS4
|Drive select 4
| OUT
OUT
OUT
|
|
A,B
|Radial head load
| IN
IN
IN
|
|
X
|Radial head load
| OUT
OUT
OUT
|
|
Z
|In use from drive select
| OUT
OUT
OUT
|
|
HL
|Stepper power from head load | OUT
OUT
OUT
|
|
R
|Alternate output ready pad
| IN
IN
IN
|
|
I
|Alternate output index pad
| IN
IN
IN
|
|
C
|Alternate input head load
| IN
IN
IN
|
|
D
|Alternate input-in-use
| OUT
OUT
OUT
|
|
DC
|Alternate output disk change | OUT
OUT
OUT
|
|
2S
|Alternate output 2-sided disk| IN
IN
IN
|
|
Y
|In use from head load
| IN
IN
IN
|
|
DL
|Door lock latch
| OUT
OUT
OUT
|
|
RR
|Radial ready
| IN
IN
IN
|
|
RI
|Radial index
| IN
IN
IN
|
|
WP
|Inhibit write when write
| IN
IN
IN
|
|
|protect
|
|
|
NP
|Allow write when write
| OUT
OUT
OUT
|
SINGLE
|
|protect
|
|D1,D2,D4,DDS|Drive address select
|
OUT
OUT
|
B1-B4
|Two-sided drive select
|
OUT
OUT
|
S1,S3
|Head select option
|
OUT
OUT
|
S2
|Head select option
|
IN
IN
|
T40
|Test track 40
|
OUT
OUT
|
HA
|Test actuate head load
|
OUT
OUT
|4,6,8,10,12,|Alternate I/0 pins
|
OUT
OUT
|16,18,24
|
|
|
SF
|Switch filter
|
IN
IN
|
SP
|Stepper power (used with HL) |
OUT
OUT
|
OUT
|
OUT
|
OUT
|
IN
|
OUT
|
OUT
|
OUT
|
|
IN
|
OUT
|
---------------------------------------------------------------
-----Table 2-11:
Qume 242 Drive Configuration
18
----------------------------------------------------------------------|
|
|
DUAL
SINGLE |
|
OPTION
|
DESCRIPTION
| DRIVE 0 DRIVE 1
DRIVE 0 |
|-----------------------------------------------------------------------|
|
DS1
|Drive select 1
| IN
OUT
IN
|
|
DS2
|Drive select 2
| OUT
IN
OUT
|
|
DS3
|Drive select 3
| OUT
OUT
OUT
|
|
DS4
|Drive select 4
| OUT
OUT
OUT
|
|
Z
|In use from drive select
| OUT
OUT
OUT
|
|
R
|Alternate output ready pad
| IN
IN
IN
|
|
I
|Alternate output index pad
| IN
IN
IN
|
|
D
|Alternate input-in-use
| OUT
OUT
OUT
|
|
DC
|Alternate output disk change
| OUT
OUT
OUT
|
|
2S
|Alternate output 2-sided disk *| IN
IN
IN
|
|
DS
|Stepper power from drive
| OUT
OUT
OUT
|
|
|select
|
|
|
DL
|Diskette lever (optional)
| OUT
OUT
OUT
|
|
Y
|In use from head load
| IN
IN
IN
|
|
HL
|Stepper power from head load
| IN
IN
IN
|
|
C
|Head load option
| IN
IN
IN
|
|
RR
|Radial ready
| IN
IN
IN
|
|
RM
|Ready modified
| OUT
OUT
OUT
|
|
RI
|Radial index
| IN
IN
IN
|
|
WP
|Inhibit write when write
| IN
IN
IN
|
|
|protected
|
|
|
OUT
NP
|Allow write when write
|
|protected
|
|Side select option using
|
|drive select*
|
OUT
OUT
OUT
OUT
|
|
|
|
OUT
B1-B4
|
|
|
OUT
|
IN
|
OUT
|
IN
|
OUT
|
OUT
|
|
S1
|Head select option
|
OUT
OUT
|
S2
|Head select option
|
IN
IN
|
S3
|Head select option
|
OUT
OUT
|
M1
|Spindle motor option
|
IN
IN
|
M2
|Spindle motor option
|
OUT
OUT
|
MC1-MC4
|Motor control select
|
OUT
OUT
|-----------------------------------------------------------------------|
|
* TM 848-2 Only
|
|________________________________________________________________________
|
Table 2-12 Tandon TM848-1/848-2 Drive
Configuration
19
2.2.1. Drive Selection Signals
_______________________
The controller provides four radial drive select signals.
Each
drive must be configured to one of the appropriate drive
select
signals. Drive select 1 and drive select 2 (DS1/DS2) are
associated with the primary register set (177170 U8 D)
while drive
select 3 and drive select 4 (DS3/DS4) are associated with
the
secondary register set (177174 U8 D).
Upon initiation of a function the controller selects the
appropriate drive, performs the operation and after ten
revolutions of inactivity deselects the drive.
2.2.2. Head Load Signal
________________
A separate head load signal is provided to prolong media
life.
The read/write heads are only loaded on the media during
read/write operations. All other operations are
completed with
the heads in the unloaded position.
Because step positioning can take place with the heads
unloaded,
the drive must be configured to provide stepper power
independent of head loading.
2.2.3. Motor Control
_____________
The controller has been configured for ease of use with
the
newer DC motor drives.
A motor on signal is provided and
is
activated by the controller upon the initiation of any
function.
Before the drive is used for read/write operations, a
motor
delay timer insures the drive is up to speed. After ten
revolutions of inactivity, the signal is deselected,
prolonging
the life of the drive.
The motor on delay timer has been configured to operate
with
drives jumpered with motor on as a function of drive
select.
When a drive is selected the motor on signal is set.
If
the
motor on signal was previously set the drive ready status
is
immediately interrogated and if valid, the function is
initiated. If the drive is not ready a motor on delay is
issued
after which the drive ready status is again interrogated.
A
valid ready status initiates the function while a not
ready
status results in a error being reported and the
operation
aborted.
20
2.3. CABLING
_______
A 50-conductor ribbon cable connects to any Shugart compatible
drive(s).
If the optional cable is purchased with the controller, connect
the socket
connector to the 50-pin header located at the edge of the
controller
board. Observe the alignment of pin 1 of the socket connector
and header
as indicated by the arrows shown in Figure 2-2. The two 50-pin
connectors
should be connected to the corresponding drives, again observing
the
location of pin 1. If the optional cable is purchased from an
independent
source, the following list of materials (or equivalent) will
help in the
construction of the required cable.
QTY
DESCRIPTION
MFG
_________________________________________________________
1 ea
50 pin socket connector
3M
3000
2 ea
50 pin edge connector
3M
0001
A/R
50 conductor ribbon cable
3M
NUMBER
342534153365/50
Pin 1 ___
\ ___
___
___
___
------|
|----|
|
|
|
|
|
|
|
/
/
|----|
|----|
|
|
|
|
|
|
|
|
|
|
/--------|
|----|
___
|
___
|----|
|----|
___
___
\
\
\
\
\
\
\
\
Card
edge
\
\
connector
\
Ribbon cable
\
(50 conductor) \
/\
\
\
\
\
|
|
|
(50 pin)
/
\
|
/ \
|
/
/
\ |
/
\/
\ |
/ Pin 1___/
/
/
\
/
/
\
/
Socket
/
\/\_____connector
/
/
(50 pin)
/ Component Side
/
/
/
/
MXV22
/
\
/
\ B
/
\
/
\/\
/
/
/
\ A
/
\
/
\
/
\ /
\/
Figure 2-2: Drive/Controller Cabling
/
\
\
\
21
The connector pins illustrated in Figure 2-3 are compatible with
both
the Shugart 800 series and 850 series drives.
Any drive that
has both
a Shugart compatible interface and connector should function
properly
with the controller.
------_______
----| 1 | 2 |----->TG 43___
________
|----| 3
|----| 5
|----| 7
|----| 9
|----|11
|----|13
|----|15
|----|17
| 4
| 6
| 8
|10
|12
|14
|16
|18
|----->MOTOR ON
|
|
_________
|<-----TWO SIDED
|
___________
|----->SIDE SELECT
|
_________
|----->HEAD LOAD
_____
|----|19 |20 |<-----INDEX
_____
|----|21 |22 |<-----READY
|----|23 |24 |
____________
|----|25 |26 |----->DRIVE SELECT 1
______________
|----|27 |28 |----->DRIVE SELECT 2
______________
|----|29 |30 |----->DRIVE SELECT 3
______________
|----|31 |32 |----->DRIVE SELECT 4
______________
|----|33 |34 |----->DIRECTION
____
|----|35 |36 |----->STEP______
____
|----|37 |38 |----->WRITE DATA
__________
|----|39 |40 |----->WRITE GATE
________
|----|41 |42 |<-----TRACK 00_____
________
|----|43 |44 |<-----WRITE PROTECT
_________
|----|45 |46 |<-----READ DATA
|----|47 |48 |
|----|49 |50 |
|
-------
_
Figure 2-3:
2.4. CONTROLLER INSTALLATION
The controller
Connector Pin Definitions
_______________________
can be inserted and will function in any LSI-11
bus
slot provided that both interrupt and DMA continuity are
maintained.
Since these signals are daisy chained through the bus slots, no
unused
slots between LSI-11 processor and the floppy controller may
exist.
Determine the order that the priority chain follows by
consulting the
documentation supplied with the LSI-11 system. Note that when
two
interrupts of the same priority level are asserted, the closer a
device
is located to the processor, the higher its priority.
22
2.5. INITIAL OPERATION AND CHECKOUT
______________________________
Before the following procedures are done and for purposes of
checkout,
verify that the controller has been configured with two drives
as
described in Sections 2.1 - 2.4.
NOTE
____
The bootstrap must be disabled for
the following procedures.
1.
Apply power to the drive(s).
2.
Place the Run/Halt switch on the processor to the Halt position
and
turn on the processor.
An "@" character should be printed on
the
terminal signifying that console ODT has been entered.
Both
drives
(first drive 1, then drive 0) will step the heads inward 2tracks, then
step the heads outward until the home signal is detected. The
heads
will not load. If the above events do not occur, check the
cabling and
drive power supplies.
3. Place a preformatted scratch diskette in drive 0.
____________
4. If the standard address assignment is selected, open the CS
register
using ODT by typing 177170/ on the terminal. The processor will
display the contents of the CS register. If the controller is
operating properly a 004040 U8 D should be printed. Deposit a
40000 U8 D in
the CS register by typing 40000 <CR>. This command will
initialize the
controller. Both drives should calibrate for home position.
First,
drive 1 steps inward 2 tracks then outward one track at a time
until
the drive indicates track 0 has been reached. The procedure is
repeated on drive 0. After both drives are calibrated, the head
on
drive 0 is loaded.
Sector 1 of track 1 on drive 0 is read into
controller buffer.
This operation is indicated by the in-use
the
LED on
the drive indicating the head load operation. The LED will
remain on
for a short time after the read operation is complete.
If, after initializing, the drives do not calibrate or the LED
is not
activated, check the cabling and power supplies.
5.
Reopen the CS register (location 177170 U8 D) using ODT as
described above.
The contents of this location should be 004040 U8 D. Examining
the next
location 177172 U8 D by using the line feed key or typing in
177172/ should
yield either a 204 U8 D, 244 U8 D, 206 U8 D or 246 U8 D. For a
detailed description of
the register protocol and bit definition, refer to Section 3.
6.
ready
booted.
7.
If the above procedures function as described, the controller is
for use. Either diagnostics or an operating system can be
For
details on bootstrapping refer to Section 4.
If the above procedures cannot be validated, consult the factory
or
your local representative for assistance.
23
24
SECTION
3
FUNCTIONAL
DESCRIPTION
3. GENERAL
_______
This section describes device registers and command protocol for
the
MXV22.
All software control of the MXV22 is performed by means of two
sets of
two device registers:
the command and status (MXVCS) register
and a
multipurpose data buffer (MXVDB) register. These registers are
assigned the bus address 177170 U8 D and 177172 U8 D,
respectively, for the
primary register set and 177174 U8 D and 177176 U8 D,
respectively, for the
secondary register set. The registers can be read or loaded,
with a
few exceptions, using any instruction referring to their
addresses.
The MXVCS register passes control information from the CPU to
the
controller and reports status and error information from the
controller
to the CPU. The MXVDB is provided for additional control and
status
information between the CPU and the controller. The information
that
is present in the MXVDB at any given time is a function of the
controller operation in progress.
The controller contains a sector buffer capable of storing a
complete
sector.
For read/write operations the buffer is either "filled"
before
a write command or "emptied" after a read command under DMA
control.
During a write command the controller locates the desired sector
and
the buffer information is transferred to the diskette.
During a
read
operation the desired sector is located and the sector data are
transferred to the buffer.
3.1. REGISTER DEFINITIONS
____________________
3.1.1. MXVCS - Command and Status Register (177170 U8 D or 177174 U8 D)
___________________________________________ U_ D__________ U_ D_
The format of the MXVCS register is shown below. Functions are
initiated by loading the command and status (CS) register, when
not
busy (bit 5 = 1), with bit 0 = 1.
Command protocol is discussed
in
detail in Section 3.2.
25
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|ERR|INT|EXT ADD|RX |
|HD |DEN|TR |INT|DN |UNT| FUNCTION |GO
|
|
|
|
|02 |
|SEL|
|
|ENB|
|SEL|
|
|
--------------------------------------------------------------BIT DESCRIPTION
15
ERROR:
_______________
This bit is set by the controller to indicate
that an
error has occurred during an attempt to execute a
command.
This bit is cleared by the initiation of a new command
or by
setting the initialize bit.
When an error is detected
the
MXVES is read into the MXVDB.
This bit is a read-only
bit.
14
MXV22 INITIALIZE: This bit is set by the program to
initialize the controller without initializing all the
devices on the LSI-11 bus. This is a write-only bit.
CAUTION
_______
Loading the lower byte of the MXVCS will
also load the upper byte of the MXVCS.
When this bit is set, the controller will negate Done
and
move the head position mechanism of drive 1 (if two
drives
are available) to track 0.
When completed, the
controller
will repeat the operation on drive 0.
The controller will then clear the error and status
register,
set Initialize Done, and set Drive Ready if drive 0 is
ready.
Finally, the controller will read sector 1, track 1,
of drive
0.
13-12
EXTENDED ADDRESS BITS:
These bits are used to specify
an
extended bus address.
These
are write-only bits.
Bit 12 = MA16.
Bit 13 = MA17.
11
RX02:
This bit is asserted by the controller to
indicate
that this is an RX02 type system.
This is a read-only
bit.
10
RESERVED:
Must be written as a zero.
09
HEAD SELECT:
This bit selects one of the two possible
sides
of the disk for execution of the desired function.
When
cleared, side 0 is selected, when set, side 1 is
selected.
This is a read/write bit.
08
DENSITY SELECT:
This bit selects either single or
double
density operation.
When cleared, single density is
selected;
when set, double density is selected.
This is a
read/write
bit.
07
TRANSFER REQUEST:
This bit signifies that the
controller
needs data or has data available. This is a read-only
bit.
26
06
INTERRUPT ENABLE:
This bit is set by the program to
enable
an interrupt when the controller has completed an
operation
and asserted the Done bit.
The condition of this bit
is
cleared by initialize.
function.
05
Done
DONE:
This is a read/write bit.
This bit indicates the completion of a
will generate an interrupt when asserted if interrupt
enable
(MXVCS bit 6) is set.
04
UNIT SELECT:
This is a read-only bit.
This bit selects one of the two possible
disks
for execution of the desired function.
This is a
read/write
bit.
03-01
FUNCTION SELECT:
These bits code one of the eight
possible
functions described in detail within this section.
These are
write-only bits.
000
001
010
011
100
101
110
111
00
GO:
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Set Media Density/Format
Read Status
Write Deleted Data Sector
Read Error Code
Initiates a command (write-only bit).
3.1.2. MXVDB - Data Buffer (177172 U8 D or 177176 U8 D)
___________________________ U_ D__________ U_ D_
This register serves as a general purpose data path between the
controller and the LSI-11. It will represent one of seven
registers
according to the protocol of the function in process. These
registers
include the MXVDB, MXVTA, MXVSA, MXVWC, MXVBA, MXVBAE and MXVES.
This register is a read/write register if the controller is not
in the
process of executing a command (i.e., it may be manipulated
without
affecting the controller).
When the controller is executing a
command,
the register can only be accessed when MXVCS bit 7 (TR) is set.
Data Buffer Register (MXVDB)
____________________________
All information transferred to and from the floppy media passes
through
the MXVDB register and is addressable only under the protocol of
the
function in progress.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------\---------------------------\/---------------------------------/
READ/WRITE DATA
MXVDB FORMAT
27
Track Address Register (MXVTA)
______________________________
This register is loaded to indicate on which of the 115 U8 D (77
decimal)
tracks a given function is to operate.
It can be addressed only
under
the protocol of the function in progress.
Bits 8 through 15 are
not
used and are ignored.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|///|///|///|///|///|///|///|///| 0 |
|
|
|
|
|
|
|
|///|///|///|///|///|///|///|///|
|
|
|
|
|
|
|
|
--------------------------------------------------------------\---------------\/--------------/\--------------\/-------------/
NOT USED
0-114 U8 D
MXVTA FORMAT
Sector Address Register (MXVSA)
_______________________________
This register is loaded to indicate on which of the 32 U8 D (26
decimal)
sectors a given function is to operate. It can be addressed
only under
the protocol of the function in progress. Bits 8 through 15 are
not
used and are ignored.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|///|///|///|///|///|///|///|///| 0 | 0 | 0 |
|
|
|
|
|
|///|///|///|///|///|///|///|///|
|
|
|
|
|
|
|
|
--------------------------------------------------------------\--------------\/---------------/\-------------\/--------------/
NOT USED
1-32 U8 D
MXVSA FORMAT
Word Count Register (MXVWC)
___________________________
This register is loaded with the number of words (maximum of 128
decimal) to be transferred. At the end of each transfer the
word count
register is decremented. When the contents of the register are
decremented to zero transfers are terminated; Done is set (MXVES
bit
5);and, if enabled, an interrupt is requested. If the word
count is
greater than the limit for the density specified, the controller
asserts a Word Count Overflow (bit 10 of the MXVCS). This
register can
be addressed only under the protocol of the function in
progress. Bits
8 through 15 are not used and are ignored.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|///|///|///|///|///|///|///|///|
|
|
|
|
|
|
|
|
|///|///|///|///|///|///|///|///|
|
|
|
|
|
|
|
|
--------------------------------------------------------------\--------------\/---------------/\------------\/---------------/
NOT USED
0-200 U8 D
MXVWC FORMAT
28
Bus Address Register (MXVBA)
____________________________
This register is used to generate the bus address which
specifies the
location to and from which data are to be transferred. The
register is
incremented after each transfer. It will increment across 32K
boundary
lines via the extended address bits in the control and status
register
and the bus address extension register. Systems with only 16
address
bits will "wrap around" to location zero when the extended
address
bits are incremented. This register can be addressed only under
the
protocol of the function in progress. Bit 0 is not used and is
ignored.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|///|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|///|
--------------------------------------------------------------MXVBA FORMAT
Bus Address Extension Register (MXVBAE)
_______________________________________
This register contains the extended address bits (A18-A21) when
22 bit
addressing is enabled.
Bits 4 thru 15 are not used and are
ignored.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|///|///|///|///|///|///|///|///|///|///|///|///|A21|A20|A19|A18|
|///|///|///|///|///|///|///|///|///|///|///|///|
|
|
|
|
--------------------------------------------------------------MXVBAE FORMAT
Error and Status Register (MXVES)
_________________________________
This register contains the current error and status conditions
of the
drive selected by bit 4 (Unit Select) of the MXVCS.
This read-
only
register can be addressed only under the protocol of the
function in
progress. The MXVES is loaded in the MXVDB upon completion of a
function.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
--------------------------------------------------------------|///|///|///|///|NXM|WC |HD |UNT|DRV|DD |DRV|DEN|AC |ID
|SID|CRC|
|///|///|///|///|
|OVF|SEL|SEL|RDY|
|DEN|ERR|LO |
|RDY|
|
--------------------------------------------------------------\------\/-------/
NOT USED
MXVES FORMAT
29
BIT DESCRIPTION
15-12
___ ___________
Not Used.
11
NONEXISTENT MEMORY ERROR: This bit is asserted by the
controller when the memory address specified for a DMA
operation is nonexistent.
10
WORD COUNT OVERFLOW:
This bit indicates that the word
count
specified is greater then the limit for the density
selected.
Upon detecting this error the controller terminates the
fill or
empty buffer operation and asserts the Error and Done
bits.
09
HEAD SELECT:
This bit indicates the side currently
selected.
If cleared, it indicates drive 0; if set, it indicates
side 1.
08
UNIT SELECT:
This bit indicates the drive currently
selected.
If cleared, it indicates drive 0; if set, it indicates
drive 1.
07
DRIVE READY: This bit is asserted if the unit currently
selected exists, is properly supplied with power, has a
diskette installed correctly, has its door closed, and
has a
diskette up to speed.
This bit is only valid when
retrieved
via a read status function or at the completion of
initialize
when it indicates the status of drive 0.
06
DELETED DATA:
During data recovery, the identification
mark
preceding the data field was decoded as a deleted data
mark.
05
DRIVE DENSITY:
The bit indicates the density of the
diskette
in the selected drive.
When zero, it indicates single
density;
when set to one, it indicates double density.
04
information
DENSITY ERROR:
A density error was detected as the
was retrieved from the data field of the diskette (a
density
error occurs when the density selected differs from that
of the
data field).
Upon detecting this error the controller
loads
the MXVES into the MXVDB and asserts the Error and Done
bits.
03
ACLO: Set by the controller to indicate a power failure.
02
INITIALIZE DONE:
This bit is asserted to indicate
completion
of the initialize routine, which can be caused by system
power
failure, or programmable LSI-11 bus initialize.
01
SIDE READY:
This bit is asserted by the controller when
a
double-sided drive is selected, is ready, and has
double-sided
media inserted.
The assertion of this bit indicates
that side
1 of the selected drive is available for read and write
operations.
00
CRC ERROR:
A cyclic redundancy check error was detected
as
information was retrieved from a data field of the
diskette.
The information stored in the buffer should be
considered
invalid.
Upon detection of this error the controller
loads the
MXVES into the MXVDB and asserts the Error and Done
bits.
30
3.1.3. Extended Status Registers
_________________________
The controller has four internal status registers. These
registers
provide specific error information in the form of error codes as
well
as drive status information depending upon the general error
type. The
registers can be retrieved by a read error code function as
described
in Section 3.2.8.
Word 1 <7:0> - Definitive Error Code
____________________________________
Octal Code Error Code Meaning
_____________________________
040
Tried to access a track greater than 76.
050
Home was found before desired track was reached.
070
Desired sector could not be found after looking at 52
headers (2 revolutions).
120
A preamble could not be found.
150
The header track address of a good header does not
compare
with the desired track.
160
Too many tries for an IDAM (identifies header).
170
Data AM not found in allotted time.
200
CRC error on reading the sector from the disk.
240
Density Error
250
Wrong Key word for Set Media Density Command
260
Illegal Data AM
270
Invalid POK during write sequence
300
Drive not ready.
310
Drive write protected.
Word 1 <15:8> - Not Used
________________________
This register is always cleared by the controller.
Word 2 <7:0> - Current Track Address of Drive 0
_______________________________________________
This register is cleared during the initialize command in order
to
synchronize with actual track position.
The register is updated
with
each seek on drive 0 and maintains current track position.
31
Word 2 <15:8> - Current Track Address of Drive 1
________________________________________________
This register is cleared during the initialize command in order
to
synchronize with actual track position.
The register is updated
with
each seek on drive 1 and maintains current track position.
Word 3 <7:0> - Target Track of Current Disk Access
__________________________________________________
If legal, the track specified for the last read/write command is
saved
in this register.
Word 3 <15:8> - Target Sector of Current Disk Access
____________________________________________________
The sector specified for the last read/write command is saved in
this
register.
Word 4 <15:8> - Track Address of Selected Drive
_______________________________________________
This register contains the track address read from the sector
header of
the desired sector during the last read/write command.
3.2. COMMAND PROTOCOL
________________
Data storage and recovery using the MXV22 controller is
accomplished by
careful manipulation of the MXVCS and MXVDB registers according
to the
strict protocol of the individual functions. The penalty for
violation
of protocol can be permanent loss of data. Each of the
functions are
encoded and written into the command and status register bits 13 as
described in Section 3.1.1. The detailed protocol for each
function is
described below.
3.2.1. Fill Buffer (000)
_________________
This function is used to fill the controller buffer with data
from the
host processor.
The number of words to transfer is specified by
the
host.
The command density bit determines the buffer size (64 or
128
words).
The controller zero-fills the remaining buffer space.
If the
word count is too large for the density selected, the function
is
aborted, Error and Done are asserted and the Word Count Overflow
bit is
set in the MXVES.
The contents of the buffer may be written on the diskette with a
subsequent write sector command or returned to the host
processor using
an empty buffer command.
When the command is loaded, MXVCS bit 5 (Done) is negated.
MXVCS bit 8
(density) must be set to define the buffer size. MXVCS bits 12
and 13
(extended address bits A16 and A17) must also be asserted to
define the
extended memory segment used with the buffer address, yet to be
specified, to form the absolute memory address of the data to be
transferred. MXVCS bit 4 (unit select) and bit 9 (head select)
are
ignored since no drive operation is required. When MXVCS bit 7
(TR) is
first asserted, the program must move the word count into the
MXVDB
which will negate TR.
32
When the controller again asserts TR, the program must move the
buffer
address into the MXVDB. If 22 bit addressing is enabled, the
controller again asserts TR and the program must move the
extended
address bits (A18-A21) into the MXVDB. The controller then
negates TR,
initiates a DMA cycle, and transfers the first word from the
host
processor to the controller buffer. At the end of the transfer
the
word count register is decremented and the buffer address is
incremented by two. This cycle is repeated until the word count
register becomes zero. The controller zero-fills the remaining
buffer
space, sets the Done bit, and if enabled, causes an interrupt
request.
After Done is asserted the MXVES is moved into the MXVDB.
During the Data Transaction,
addressed,
the controller will time out
and
Done bits will be asserted.
the
MXVES will be moved into the
request
will be generated.
3.2.2. Empty Buffer (001)
if any non-existent memory is
and abort the function.
The Error
MXVES bit 11 (NXM) will be set and
MXVDB; if enabled, an interrupt
__________________
This function is used to transfer the contents of the controller
to the
host processor.
The number of words to transfer is specified by
the
host.
The command density bit determines the maximum legal word
count.
If the word count specified is too large for the density
selected the
function is aborted, Error and Done are asserted and the Word
Count
Overflow bit is set in the MXVES.
The contents of the buffer may be transfered to the host as many
times
as desired or may be written on the diskette with a subsequent
write
sector command.
issued,
Unless a fill buffer or read sector command is
the controller buffer is not destroyed.
When the command is loaded, MXVCS bit 5 (Done) is negated, MXVCS
bit 8
(density) must be set to allow the proper word count limit.
MXVCS bits
12 and 13 (extended address bits A16 and A17) must also be
asserted to
define the extended memory segment used with the buffer address,
yet to
be specified, to form the absolute memory destination address.
MXVCS
bit 4 (unit select) and bit 9 (head select) are ignored since no
drive
operation is required. When MXVCS bit 7 (TR) is first asserted
the
program must move the word count into the MXVDB which will
negate TR.
When the controller again asserts TR the program must move the
buffer
address into the MXVDB. If 22 bit addressing is enabled, the
controller again asserts TR and the program must move the
extended
address bits (A18-A21) into the MXVDB. The controller then
negates TR,
initiates a DMA, and transfers the first word of the buffer to
the host
processor. At the end of the transfer, the word count register
is
decremented and the buffer address register is incremented by
two.
This cycle is repeated until the word count register becomes
zero. The
controller then sets the Done bit and if enabled causes an
interrupt
request. After Done is asserted the MXVES is moved into the
MXVDB.
33
During the DMA transaction, if any non-existent memory is
addressed,
the controller will time out and abort the function. The Error
and
Done bits will be asserted. MXVES bit 11 (NXM) will be set and
the
MXVES will be moved into the MXVDB. If enabled, an interrupt
request
will be generated.
3.2.3. Write Sector (010)
__________________
This function is used to locate a desired track and sector and
write
the sector with the contents of the internal sector buffer.
When the
MXVCS is loaded with this command, the MXVES is cleared and both
the TR
and Done bits are negated. When TR is first asserted the
program must
load the desired sector address into the MXVDB which will negate
TR.
When TR is again asserted the program must load the desired
track
address into the MXVDB which will negate TR. The controller
then seeks
the desired track and attempts to locate the desired sector.
The
desired track is compared with the track field of the sector
header.
If they do not match the operation is aborted, the Error and
Done bits
are asserted, the MXVES is moved into the MXVDB, and if enabled
the
controller will assert an interrupt request.
If the densities agree but the controller is unable to locate
the
desired sector within two diskette revolutions, the controller
will
abort the operation, move the contents of MXVES into MXVDB,
assert the
Error and Done bits, and if enabled, assert an interrupt
request.
If the desired track and sector located and the densities agree,
the
controller will write the contents of the internal sector buffer
followed by a CRC character, all in the function selected
density. The
controller completes the operation by moving the MXVES to the
MXVDB,
asserts Done, and if enabled, asserts an interrupt request.
CAUTION
_______
The contents of the internal sector buffer are lost
during a power failure. However, after power is brought
back to normal, a write sector command will cause the
random contents of the buffer to be written on the
diskette with a valid CRC character.
NOTE
____
The contents of the sector buffer are not destroyed by a
write sector operation.
34
3.2.4. Read Sector (011)
_________________
This function is used to locate the desired track and sector and
transfer the contents of the data field into the controller's
internal
sector buffer.
When the MXVCS is loaded with this command, the
MXVES
is cleared and both the TR and Done bits are negated.
When TR
is first
asserted the program must load the desired sector address into
the
MXVDB which will negate TR. When TR is again asserted the
program must
load the desired track address into the MXVDB which will negate
TR.
Both the TR and Done bits remain negated while the controller
attempts
to locate the desired sector. If after two revolutions the
controller
is unable to locate the desired sector, the operation is
aborted. The
controller will move the MXVES into the MXVDB, assert the Error
and
Done bits, and if enabled, assert an interrupt request.
When the desired sector is located, the controller will then
compare
the desired track with the track field of the sector header.
If
they
do not match, the operation is aborted.
The Error and Done bits
are
asserted, the MXVES is moved into the MXVDB, and if enabled, the
controller asserts an interrupt request.
If a legal data address mark is located and the densities of the
diskette and function agree, the controller will read the data
from the
sector into the internal buffer. If the data address mark
indicated a
deleted data field, MXVES bit 6 (DD) is set. As data are stored
in the
internal buffer, a CRC is computed on the data and the CRC bytes
recorded. A non-zero result indicates a read error. When a CRC
error
is encountered, the controller sets MXVES bit 0 (CRC), moves the
MXVES
into the MXVDB, asserts the Error and Done bits, and if enabled,
asserts an interrupt request.
If the desired sector is located, the density of the diskette
and
function agree, and the data are transferred with no CRC error,
the
controller will assert Done, and if enabled, will assert an
interrupt
request.
3.2.5. Set Media Density (100)
_______________________
This function is dual purpose. The controller can set the media
density by rewriting all the data address marks (single or
double
density) and writing zero data fields in the selected density.
The
controller can also "reformat" the entire diskette by rewriting
both
the sector headers and the data fields. The data fields are
written in
the selected density preceded by the corresponding data address
mark.
Both commands are initiated by the set media function but differ
in the
keyword required by the controller to execute the command.
35
When the MXVCS is loaded with the command, the MXVES is cleared
and the
Done bit is negated.
When TR is set, the program must respond
with a
keyword. This keyword must be deposited in the MXVDB to
complete the
protocol. When the controller recognizes this character, it
begins
executing the command. If an illegal keyword is used, the
operation is
aborted. The MXVES is moved into the MXVDB, the Error and Done
bits
are set, and if enabled, the controller asserts an interrupt
request.
If the keyword used is a 111 U8 D, the controller initiates a
set media
density operation. This operation starts at track 0, sector 1.
Each
sector header is located and a write operation is initiated. A
data
field is written with zero data in the density selected. If an
error
occurs reading any header, the operation is aborted. The MXVES
is
moved into the MXVDB, the Error and Done bits are set, and if
enabled,
the controller asserts and interrupt request. If the operation
is
successfully completed, Done is set and if enabled, the
controller
asserts an interrupt request.
If the keyboard used is a 222 U8 D, the controller initiates a
format
operation.
This function starts at the physical index of track
0.
Each track is written first with an index address mark, then 26
sector
headers are written sequentially about the track. When each
track has
been written, the controller initiates a set media density
function as
described above.
The following input string will format the selected unit, in the
desired density.
777170/
_______
4040
___________
XXXX
<LF>
177172/
000000
222
<CR>
___________
CAUTION
_______
The set media density function takes about 15 seconds
and the format function takes about 45 seconds. Neither
should be interrupted. If either operation is
interrupted, an illegal diskette has been generated, and
the operation should be repeated. If an error occurs
during a set media density function or a format
function, an illegal diskette has been generated. The
operation should be repeated.
36
3.2.6. Read Status (101)
_________________
This function is used to update the drive status information and
is
initiated by loading the command into the MXVCS.
The Done bit
is
negated.
MXVES bit 7 (Drive Ready) is updated by sampling the
drive
ready status line.
Drive density is updated by loading the head
of the
selected drive and reading the first data address mark. The
controller
then moves the MXVES into the MXVDB, asserts Done, and if
enabled,
asserts an interrupt request. This operation requires about
250ms to
complete.
NOTE
If double-sided media are mounted in a double-sided
drive, MXVES bit 1 (side ready is set).
3.2.7. Write Deleted Data Sector (110)
_______________________________
This operation is identical to Write Sector (010) with one
exception.
The data address mark preceding the data is not the standard
data
address mark. A single or double density deleted data address
mark is
written according to the density of the function.
3.2.8. Read Error Code (111)
_____________________
This function is used to retrieve the extended status registers
and is
initiated by loading the MXVCS with the command.
The Done bit
is
negated.
When TR is asserted, the program must load the Bus
Address
into the MXVDB.
If 22 bit addressing is enabled, the controller
again
asserts TR and the program must move the extended address bits
(A18-A21) into the MXVDB. The controller then negates TR and
assembles
one word at a time and, under DMA control, transfers them to
memory
starting at the address specified.
If non-existent memory is encountered during the transfer, the
operation is aborted. The Error and Done bits will be asserted,
MXVES
bit 11 (NXM) will be set, and the MXVES will be moved into the
MXVDB.
If enabled, an interrupt request will be generated.
When all four words have been transferred the Done bit is set
and if
enabled, an interrupt request is generated.
37
38
SECTION
4
CONTROLLER
OPERATIONS
4. GENERAL
_______
This section provides the user pertinent information concerning
the
description and use of the controller functions.
The functions
covered
include: bootstrapping, formatting, fill/write operations,
read/empty
operations, write current control, write precompensation, and
power
fail protection.
4.1. BOOTSTRAPPING THE CONTROLLER
____________________________
If the bootstrap is enabled as described in Section 2.1.3, the
controller will respond to the standard bootstrap address
173000 U8 D. The
controller is bootstrapped by typing 773000G while in console
ODT. This
causes a bus INIT and transfers program execution to location
173000 U8 D.
An alternate method is to strap the LSI-11 processor to power up
Mode
2. In this mode, when a power up occurs, the processor
automatically
starts execution at 173000 U8 D. Power-up strapping procedures
for the
LSI-11 processor can be found in the Microcomputer Processors
Handbook.*
To boot either a single or double density diskette use the
following
procedure:
1.
Place the diskette in drive 0.
2.
If the processor is strapped for power-up Mode 2,
operate the INIT (boot) switch or cycle DC power OFF
and ON.
If the processor is not strapped for power up Mode 2
3.
___
while in console ODT, type 773000G.
*Published by Digital Equipment Corporation.
1979.
39
Maynard, Mass.,
4.1.1. Bootstrap Operation
___________________
The bootstrap is not a standard ROM program. It uses the
controller's
microprocessor to capture the bus; to read block 0 of the
diskette into
memory starting at location 0; and finally to transfer program
execution to memory location 0.
Any attempt to read location 173000 U8 D will result in a nonexistent
memory trap. The controller only responds to this address
immediately
after a bus INIT. For this reason the bootstrap is called
"transparent". When the processor attempts to fetch location
173000 U8 D
following a bus INIT, the controller responds by passing the
processor
a "CLEAR RO" instruction. The processor clears RO and then
attempts to
fetch location 173002 U8 D. The controller passes the processor
a "LOAD
IMMEDIATE" instruction with R1 as the destination. The
processor then
attempts to fetch the source operand from location 173004 U8 D.
The
controller passes the the device address 177170 U8 D if the
standard
address is selected, or 177174 U8 D if the alternate address is
selected.
The processor moves the address into R1 and then attempts to
fetch
location 173006 U8 D. The controller first asserts a Direct
Memory Access
Request (DMR) then passes the processor a "CLEAR PC"
instruction.
Before the processor executes the instruction it passes bus
mastership
to the controller. The controller moves a "BRANCH TO CURRENT
LOCATION"
instruction (777 U8 D) into memory location 0 under DMA control.
When the
controller releases bus mastership the processor executes the
"CLEAR
PC" instruction and, in so doing, transfers program execution to
location 0. The processor is thus forced to loop at location 0.
The
controller initiates a Read Status function on drive 0 to
determine
diskette density. If the diskette is single density the
controller
reads sectors 1,3,5, and 7 of track 1 of drive 0 into locations
2
through 176, 200 through 376, 400 through 576, and 600 through
776
respectively. If the diskette is double density the controller
reads
sectors 1 and 3 of track 1 of drive 0 into locations 2 through
376, and
400 through 776 respectively. Finally, the controller DMA's
location 0
with a NOP instruction (240 U8 D) allowing the processor to
execute the
system bootstrap. If there is no diskette in drive 0 nothing
will be
transferred to memory and the processor will continue to loop at
location 0 until halted.
4.2. FORMAT OPERATIONS
_________________
The controller has the capability of formatting diskettes in a
specified density. The formatting is accomplished in two
passes.
During pass 1, an index address mark is written on track 0
following
the index hole. Twenty-six sector headers, appropriately
spaced, are
written following the index address. Each of the remaining 76
tracks
is written in the same manner. When track 76 is completed, pass
2 is
initiated. The controller seeks track 0 and write a zero data
field in
sector 1 using the selected density. The remaining sectors are
written
in the same manner.
40
The format command selects diskette density, unit and side (for
dual
headed drives).
Table 4-1 lists the various command word
formats.
------------------------------------------------------|
|
Unit 0
|
Unit 1
|
|-------------------------------------------------------|
| Single Density Side 0
|
11 U8 D
|
31 U8 D
|
| Single Density Side 1
|
1011 U8 D
|
1031 U8 D
| Double Density Side 0
|
411 U8 D
|
431 U8 D
| Double Density Side 1
|
1411 U8 D
|
1431 U8 D
|
|
|
------------------------------------------------------Table 4-1:
Command Word Formats
Figure 4-1 illustrates a format subroutine.
The format command
is
loaded into MXVCS. When TR is set, the keyword 222 U8 D is
loaded into
MXVDB. When the diskette has been formatted a return is made.
FORMAT:
MOV
BIS
BIS
BIS
MOV
JSR
MOV
JSR
TST
BMI
RTS
#11, CMD
DENS, CMD
UNIT, CMD
SIDE, CMD
CMD, @#MXVCS
PC, TRWAIT
#222, @#MXVDB
PC, DNWAIT
@#MXVCS
FRMERR
PC
;FORMAT
;DENSITY
;UNIT
;SIDE
;SELECT FUNCTION
;WAIT FOR TR
;KEYWORD
;WAIT FOR DONE
;ERROR
;BR IF SO
FRMERR:
Figure 4-1:
Format Subroutine
Alternatively a diskette can be formatted using console ODT.
Open the
CS register and deposit the appropriate command.
Then deposit
the
format key word 222 U8 D in the DB register. The following is
an example
of formatting unit 0 side 0 in double density.
177170/
004040
411 <LF>
177172/
000000
222 <CR>
________
________
41
_______
4.3. FILL/WRITE OPERATIONS
_____________________
Figure 4-2 illustrates subroutines to write data on a diskette
which is
done by performing a fill buffer operation followed by a write
sector.
The Fill Buffer command, specifying single or double density is
loaded
into the MXVCS.
When TR is set, the word count is loaded into
the
MXVDB.
When TR is again set, the bus address of the data is
loaded
into the MXVDB.
If 22 bit addressing is enabled TR is again set
and
the extended address bits are moved into the MXVDB.
A return is
made
when the controller's sector buffer is filled. The Write Sector
command (specifying density, unit and side) is loaded into the
MXVCS.
When TR is set the sector address is loaded into the MXVDB.
When TR is
again set, the track address is loaded into the MXVDB. When the
contents of the controller's sector buffer are written at the
selected
sector, a return is made.
FILLBF:
MOV
BIS
MOV
JSR
MOV
JSR
MOV
JSR
MOV
JSR
TST
BMI
RTS
#1, CMD
DENS, CMD
CMD, @#MXVCS
PC, TRWAIT
COUNT, @#MXVDB
PC,TRWAIT
#BUFOUT, @#MXVDB
PC, DNWAIT
#EXTAD,@#MXVDB
PC, DNWAIT
@#MXVCS
ERFIL
PC
;FILL BUFFER
;DENSITY
;SELECT FUNCTION
;WAIT FOR TR
;WORD COUNT
MOV
BIS
BIS
BIS
MOV
JSR
#5, CMD
DENS, CMD
UNIT, CMD
SIDE, CMD
CMD, @#MXVCS
PC, TRWAIT
;WRITE, SECTOR
;DENSITY
;UNIT
;SIDE
;SELECT FUNCTION
;WAIT FOR TR
;BUS ADDRESS OF DATA
;WAIT FOR DONE
;EXTEND ADDR BITS*
;WAIT FOR DONE*
;ERROR
;BR IF SO
ERFIL:
WSECT:
MOV
JSR
MOV
JSR
TST
BMI
RTS
SECTOR, @#MXVDB
PC TRWAIT
TRACK @#MXVDB
PC, DNWAIT
@#MXVCS
WSERR
PC
;SECTOR
;TRACK
;WAIT FOR DONE
;ERROR
;BR IF SO
WSERR:
*only required if 22 bit addressing is enabled!
Figure 4-2:
Write Data Subroutines
42
4.4. READ/EMPTY OPERATIONS
_____________________
Figure 4-3 illustrates subroutines to read data from a diskette
which
is done by performing a Read Sector operation followed by an
Empty
Buffer operation.
The Read Sector command (specifying density, unit and side) is
loaded
into the MXVCS.
When TR is set the sector address is loaded
into the
MXVDB.
When TR is again set, the track address is loaded into
MXVDB.
When the contents of the selected sector are read into
the
the
controller's sector buffer, a return is made.
The Empty Buffer command, specifying density, is loaded into the
MXVCS.
When TR is set, the word count is loaded into the MXVDB.
When
TR is
again set, the bus address of storage buffer is loaded into the
MXVDB.
If 22 bit addressing is enabled TR is again asserted and the
extension
address bits are loaded into the MXVDB. A return is made after
the
contents of the controller's buffer are transferred to the
memory
storage buffer.
RSECT:
MOV
BIS
BIS
BIS
MOV
JSR
MOV
JSR
MOV
JSR
MOV
JSR
TST
BMI
RTS
#7, CMD
DENS, CMD
UNIT, CMD
SIDE, CMD
CMD, @#MDVCS
PC, TRWAIT
SECTOR, @#MDVDB
PC, TRWAIT
#EXTAD, @#MXVDB
PC, DNWAIT
TRACK, @#MXVDB
PC, DNWAIT
@#MXVCS
RSERR
PC
;READ SECTOR
;DENSITY
;UNIT
;SIDE
;SELECT FUNCTION
;WAIT FOR TR
;SECTOR
MOV
#3, CMD
;EMPTY BUFFER
;EXTENDED ADDRESS BITS*
;WAIT FOR DONE*
;TRACK
;WAIT FOR DONE
;ERROR
;BR IF SO
RSERR:
EMPBF:
BIS
MOV
JSR
MOV
JSR
MOV
JSR
TST
BMI
RTS
DENS, CMD
CMD, @#MXVCS
PC, TRWAIT
COUNT, @#MXVDB
PC, TRWAIT
#BUFFIN, @#MXVDB
PC, DNWAIT
@#MXVCS
EREMP
PC
;DENSITY
;SELECT FUNCTION
;WAIT FOR TR
;WORD COUNT
;BUS ADDRESS FOR DATA
;WAIT FOR DONE
;ERROR
;BR IF SO
EREMP:
*only required if 22 bit addressing is enabled!
Figure 4-3:
Read Data Subroutines
43
4.5. WRITE CURRENT CONTROL
_____________________
The controller provides a Write Current Control signal (TG43)
which is
asserted whenever a track address greater than 43 is accessed.
This
signal is required by some drives to reduce the effects of write
saturation on the inner tracks. Since the Shugart 800 series
drives do
not require this signal, the controller is shipped with this
feature
disabled. However, Shugart 850 series double sided drives
require this
signal (refer to the Shugart double sided diskette storage drive
manual
section 7.13). This signal is provided on pin 2 of the 50 pin
ribbon
connector and is enabled according to section 2.1.4.
4.6. WRITE PRECOMPENSATION
_____________________
Bit shift occurs on both single and double density diskettes.
This
shift is more noticeable with double density due to the smaller
bit
cell size and corresponding data and clock windows. Some
aspects of
bit shift are predictable and are dealt with the precompensation
scheme
implemented in this controller; unpredictable effects are
reduced by
using PLL techniques.
Predictable bit-shift effects result from normal read/write
operation.
Data are recorded by flux changes in the gap of the read/write
head.
These flux changes produce changes in magnetization induces
current in
the read/write head. Since this change is current is not
instantaneous, it takes a finite time to build up to a peak and
return
to zero. When the magnetic flux changes are close together the
previous current transition may not reach zero before a second
transition occurs. The summation of current pulses produces
shifted
peaks. Because the flux changes are closer together on the
inner
tracks (43 through 76) the bit shift is greater in this area.
Values
of up to +350ns are typical.
_
Other causes of bit shift are variation disk drive rotational
speed.
_
The specified +2% variation will produce bit shifts of +40ns.
_
Incomplete erasure of previously recorded data can produce bit
shifts
of up to 50ns.
Other miscellaneous components of bit shift
include
instantaneous speed variation, electrical noise, radial track
alignment
and nonsymmetry of the read/write head and associated
electronics.
These effects can produce up to +10ns of bit shift, bringing the
total
_
effect to +450ns.
_
Since the data/clock window for double density is only 1000ns, a
+450ns
_
bit shift leaves only a 50ns margin before soft errors begin to
occur.
To improve this margin the controller incorporates a scheme to
recognize the data patterns which produce excessive bit shift
and
introduces a compensating bit shift. For tracks greater than
forty-three the recorded bits are shifted 165ns early, or late,
as
determined by the two previously recorded bits and the
subsequent two
bits to be recorded. The controller also incorporates a phaselocked
data recovery scheme which dynamically adjusts the recovery
clock
frequency to the data, reducing bit shifts due to rotational
speed
errors. These two features improve data recovery margins by
175ns or
more, providing approximately 225ns of margin.
44
4.7. POWER FAIL PROTECTION
_____________________
The controller continuously monitors both the BPOK and BDCOK bus
signals. Refer to the Microcomputer Processors Handbook for
detailed
descriptions of these signals. When asserted, BPOK signals an
impending DC power failure and guarantees 4ms of operation
before BDCOK
is asserted and DC power fails. Assertion of BDCOK indicates
invalid
DC power. This signal is hardwired in the controller as an
interlock
on the Write Gate signal. When BDCOK is asserted the Write Gate
signal
is blocked and write operations are prevented.
Before initiating a write sequence, the controller interrogates
the
BPOK line.
operation is
aborted.
If an impending DC failure is indicated the
45
46
SECTION 5
SOFTWARE
CONSIDERATIONS
5. GENERAL
_______
The MXV22 controller configured for 18-bit addressing can be
used with
all software designed to communicate with DEC's RXV21
controller. This
is of particular importance when using software not supported by
the
driver changes presented in this section. This section
describes the
changes required to RT-11 and RSX-11M in order to take advantage
of the
22-bit DMA support provided by the MXV22 controller. Once the
changes
described in this section have been incorporated into the
applicable
drivers the system software can be used with the MXV22
controller
configured in either 18-bit or 22-bit modes.
CAUTION
Operation via the MXV22 controller using unmodified
driver will yield questionable results if the MXV22
controller is configured for 22-bit addressing.
5.1. OPERATION USING RT-11 V4.0
__________________________
Operations involving the MXV22 controller are logically
equivalent to
those of the RXV21 except a modified "DY" driver is required
when
configured in 22-bit mode. Several techniques can be used to
incorporate the changes described in section 5.1.1; however, the
changes can not be performed on the "DY" via the MXV22
controller
without attention to the caution noted in section 5.
The MXV22 (and RX02) controller requires a different handler
than the
single density controllers.
This new handler is configured to
utilize
the DMA transfer scheme of the controller.
In addition,
diskette
density is determined by the handler without system
intervention,
allowing the use of either single or double density diskettes
interchangeably.
This handler, designated "DY", is available in RT11-V03B and
later
revisions.
47
Although earlier versions of RT-11 can be used, only the changes
to
V4.0 are provided in this document.
Changes to earlier versions
can be
accomplished using the methodology described here and the
judicial
placement of similar code. Earlier version will also require
modification to the Bootstrap program BSTRAP
5.1.1. Modifying RX02 Driver for RT11
______________________________
Changes listed in Appendix A are those required to modify DEC's
V4.0
RX02 driver for operation with the MXV22 controller. Changes
listed in
Appendix A.1 are in a format expected by the Source Language
Patch
program (SLP). Generate a file "DYMXV.DIF" using an editor of
your
choice containing changes listed in Appendix A.1. Use the
following
steps to include the changes:
.RUN SLP
*DYMXV=DY,DYMXV
NOTE
Changes in Appendix A are to edit level 2 of the
DY.MAC driver program.
The file DYMXV.MAC will contain the new MXV22 compatible driver.
Assemble, link and install the new driver using the method
described in
your RT-11 System Generation Manual.
5.1.2. Creating a DY-Compatible System Disk from a DX-based System
___________________________________________________________
The MXV22 controller requires the DY-based RT-11 monitor rather
than
the DX-based RT-11 monitor.
how to
create a DY-based system.
The following procedures explain
Using an RX01 or equivalent system, or system which has an RX01
or
equivalent peripheral device, the monitor file and other
associated
system files should be copied onto a single density diskette.
These
files can be obtained from the binary distribution media or by
performing a SYSGEN and specifying DY as the system device
(refer to
the RT11 System Generation Manual). The following commands will
initialize the diskette and copy the necessary files to Drive 1:
RT11V04
.INIT/NOQUERY DX1:
.COPY/SYS DEV:SWAP.SYS DX1:
.COPY/SYS DEV:RT11XX.SYS DX1:
.COPY/SYS DEV:TT.SYS DX1:
.COPY DEV:DIR.SAV DX1:
.COPY DEV:PIP.SAV DX1:
.COPY DEV:DUP.SAV DX1:
48
The bootstrap must then be copied from the monitor file to block
0 of
the diskette. The following command will accomplish this on the
diskette in drive 1.
RT11V04
.COPY/BOOT DX1:RT11XX DX1:
This diskette can be used with the MXV22 controller but it is
single
density.
To build a double density diskette the user must first
format
a diskette to double density as explained in Section 4.2
Boot
the
single density system diskette in drive 0.
Use the following
commands
to initialize the formatted diskette in drive 1 and copy the
system
software from drive 0 to drive 1.
RT11V04
.INIT/NOQUERY DY1:
.COPY/SYS DY:*.* DY1:
Finally, copy the bootstrap to block 0 of the diskette in drive
1.
RT11V04
.COPY/BOOT DY1:RT11XX DY1:
The diskette in drive 1 can now be booted as a double density
system
diskette.
5.2. OPERATION WITH RT-11 V5.0
_________________________
Currently undefined.
5.3. OPERATION WITH LAYERED PRODUCTS
_______________________________
Using the driver modifications described for RT-11, layered
products
such as TSX-Plus V3.01, and SHARE 11 can be used to provide 22bit
system support with the MXV22 controller.
5.4. OPERATION WITH RSX11M
_____________________
Extended address support provided by the MXV22 controller is
incorporated by the DYDRV changes listed in Appendix B. An
additional
change is required to the device data I/O structure. The file
SYSTB.MAC created by Phase I of SYSGEN must be edited prior to
assembly
and task building process. Characteristic word one of the Unit
Control
Block (UCB) must be edited to reflect 22-bit direct addressing
support
for the DYDRV device. Refer to section 4 of the Guide to
Writing and
I/O Device for details.
49
5.4.1. Modifying RX02 Driver RSX11M
____________________________
Changes to the RX02 driver program DYDRV.MAC are provided in
Appendix
B.
The change are referenced to the distributed Version 2.13.
Changes
listed in Appendix B are in the format expected by the Source
Language
Input Program (SLP). These change can be incorporated into the
standard driver using methods described in Section 17 of the
RSX-11
Utilities Manual.
5.5. DOUBLE SIDED OPERATION RT-11/RSX-11M
____________________________________
Change for RT-11 double sided support is listed in Appendix A.2.
These
changes can be used with the 22-bit changes.
Appendix B.2 contain the changes required for RSX-11M double
sided
support.
5.6. OPERATION WITH OTHER DEC SOFTWARE
_________________________________
The MXV22 Controller used in 18-bit mode emulates the operation
of the
RXV21.
This is particularly important when using programs or
systems
that might require access to the RX02 type device.
NOTE
____
Operation of the XXDP Diagnostic program require
that the MXV22 be configured to emulate the RXV21
in 18-bit mode.
50
APPENDIX
A.1
The following changes are for incorporating 22-bit support via
the
Source Language Patch program (SLP):
-/.IIF NDF DY$DD/,,/;MXV22/
$22BIT = 1
;Remove this line to disable 22-bit addressing
.IIF NDF $22BIT, $22BIT = 0
.IF NE $22BIT
DYTYP=2000
.ENDC
-/@$MPPTR/+1,,/;MXV22/
.IF EQ $22BIT
-/BIS/,,/;MXV22/
.IFF
MOV
@SP,-(SP)
ASL
@SP
ASL
@SP
MOV
(SP)+,EXMBIT
SWAB
@SP
BIC
#^C<30000>,@SP
BIS
(SP)+,R4
-/.ENDC/,,/;MXV22/
.ENDC
-/BUFRAD:/+3,,/;MXV22/
.IF NE $22BIT
BIT
#40000,R0
;Boundary crossed?
BEQ
8$
;Branch if not
INCB
EXMBIT
BIC
#40000,R0
;Remove bit
-/.ENDC/,,/;MXV22/
.ENDC
-/DYDOFN:/+6,,/;MXV22/
.IF NE $22BIT
BIT
#DYTYP,@R4
;Protocol complete
BNE
3$
2$:
.ENDC
-/RTS/,,/;MXV22/
51
.IF NE $22BIT
3$:
MOV
MOVB
4$:
BITB
BEQ
BMI
JMP
.BYTE
EXMBIT:
R2,@R5
EXMBIT,R2
#CSTR!CSDONE,@R4
4$
2$
DYERR2
0
.BYTE
0
;Extended memory addr
bits
.ENDC
-/8$:/+2,,/;MXV22/
.IF NE $22BIT
BIT
#DYTYP,@R4
BEQ
22$
CLRB
23$
22$:
.ENDC
-/MOV/,,/;MXV22/
.IF NE $22BIT
23$:
BR
9$
JSR
PC,WAIT
CLR
@R5
.ENDC
/
;22-bit controller?
;If equal no!
;One more transfer for 22-bit
52
APPENDIX
A.2
The following changes are for incorporating double sided support
for
RT-11 via the Source Language Patch (SLP) program:
-/.IIF NDF DY$DD/,,/;2SIDED/
DY$DS=1
MAXLSN=DYDSIZ*4
DBSID2=2
-/DOXFER:/,,/;2SIDED/
MOV
DYLSN,R3
-/DYLSN/,.,/;2SIDED/
/
53
APPENDIX
B.1
The following changes are for incorporating 22-bit support for
RSX-11M
via Source Language Input Program (SLP):
-/SDEN/,,/;MXV22/
ADREXT =
2000
; 22 BIT CONTROLLER BIT
-/WD. 20/,,/;MXV22/
;
WD. 21 -- NOT USED
-/(WD. 20)/,,/;MXV22/
;
I.PRM+16 (WD. 21) - EXTENDED ADDRESS BITS (BA18-BA21)
-/SWAB/,.,/;MXV22/
MOVB
UBUF(R5),R0
; EXTENDED MEMORY BITS
ROR
R0
ROR
R0
MOVB
R0,I.PRM+16(R1) ; SAVE BA18-BA21
.REPT
3
ROR
R0
.ENDM
BIC
#30000,R0
; ISOLATE BA16 & BA17
MOV
R0,UBUF(R5)
; INITIALIZE CSR WORD
-/280$:/+1,.,/;MXV22/
CMPB
R0,#'I
; END REGISTER PROTOCOL ?
BEQ
284$
; IF EQ EXIT
BIT
#ADREXT,(R2)
; 22-BIT CONTROLLER ?
BEQ
284$
; IF EQ YES
MOV
R0,RXDB(R2)
; LOAD TRACK, BUFFER ADDRESS, OR
ASCII I
281$:
283$:
284$:
ASCII I
/
BITB
BMI
BEQ
BR
MOV
MOV
#TR!DONE,(R2)
283$
281$
160$
I.PRM+16(R3),R0
R0,RXDB(R2)
; READY FOR LAST WORD ?
; IF MI YES
; ERROR, NO TRANSFER REQUEST
; EXTENDED ADDRESS BITS
; LOAD TRACK, BUFFER ADDRESS, OR
54
APPENDIX
B.2
The following changes are for incorporating double sided support
for
RSX-11M
via Source Language Input Program (SLP):
-/RSAE/,,/;2SIDED/
SSIDED =
20000
; SECOND SIDE INDICATOR BIT
(U.CW2)
-/CRCERR/,,/;2SIDED/
SIDES =
2
; DOUBLE SIDED MEDIA
-/220$:/,.,/;2SIDED/
220$: BIT
#SSIDED,U.CW2(R5) ; IS IT SECOND SIDE OPERATION?
BEQ
225$
; IF EQ NO
BIS
#DSIDED,U.BUF(R5) ; USE SECOND SIDE
225$: MOVB
S.CON(R4),R1
; RETRIEVE CONTROLLER INDEX
-/440$:/,.,/;2SIDED/
440$: BIC
#SILO!SCHAR!SSIDED!ERR1,U.CW2(R5) ; CLEAR BITS
-/470$:/,.,/;2SIDED/
470$: BIC
#SCHAR!DEN!DSIDED,U.CW2(R5) ; CLEAR FLAGS
-/480$:/,.,/;2SIDED/
480$: BIT
#SIDES,I.PRM+6(R1) ; IS IT DOUBLE SIDED?
BEQ
485$
; IF EQ NO
ASL
U.CW3(R5)
; DOUBLE THE MAXIMUM LBN'S
BIS
#DSIDED,U.CW2(R5) ; SET THE DOUBLE SIDED BIT
485$: MOV
#IS.SUC&377,R0 ; SET SUCCESS
-/600$:/,.,/;2SIDED/
600$: BIT
#SIDES,I.PRM+6(R1) ; IS IT DOUBLE SIDED?
BEQ
605$
; IF EQ NO
BIS
#DSIDED,U.CW2(R5) ; SET DOUBLE SIDED BIT
ASL
U.CW3(R5)
; DOUBLE MAX LBN'S
605$: MOV
R0,I.PRM+10(R1) ; STORE LOGICAL SECTOR NUMBER
-/CMP R0,#77./,/BEQ
60$/,/;2SIDED/
CMP
R0,#76.
; IS IT SECOND SIDE?
BLT
30$
; IF LT NO
BITB
#IO.RPB&377,I.FCN(R3) ; PHYSICAL BLOCK FUNCTION?
BEQ
23$
; IF EQ NO, IT'S A LOGICAL BLOCK
CMP
#76.,R0
; YES
BEQ
30$
; IF EQ ALLOW ACCESS TO #76.
SUB
#77.,R0
; CHANGE SIDES - PHYBLK ACCESS
23$:
25$:
BR
SUB
BIT
BEQ
BIS
25$
;
#76.,R0
;
#DSIDED,U.CW2(R5)
60$
;
#SSIDED,U.CW2(R5)
CHANGE READ HEADS
ADJUST FOR SECOND SIDE
; TWO SIDE MEDIA?
IF EQ NO, BAD BLOCK ERROR
; SET HEAD 1 SELECT BIT
/
55
CONTENTS
________
PAGE
SECTION 1
____
GENERAL INFORMATION . . . . . . . . . . . . . . . .
COMPONENTS
. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 1
. . . 2
COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 2
Logical Track Format . . . . . . . . . . . . . . . . . . .
. . . 3
Sector Header Field
. . . . . . . . . . . . . . . . . . .
. . . 4
Data Field . . . . . . . . . . . . . . . . . . . . . . . .
. . . 4
Recording Scheme . . . . . . . . . . . . . . . . . . . . .
. . . 5
Double Frequency (FM)
. . . . . . . . . . . . . . . . . .
. . . 6
DEC Modified MFM . . . . . . . . . . . . . . . . . . . . .
. . . 6
Cyclic Redundancy Check
. . . . . . . . . . . . . . . . .
. . . 7
SPECIFICATIONS
. . . . . . . . . . . . . . . . . . . . . . . .
. . . 7
SECTION 2
INSTALLATION
. . . . . . . . . . . . . . . . . . .
. . . 9
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 9
CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 9
Address Vector Selection
. . . . . . . . . . . . . . . . . . .
. . . 9
Device Interrupt Priority
. .
10
. .
12
. .
12
. .
13
. .
14
. .
14
. .
15
Bootstrap
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
Write Precompensation
. . . . . . . . . . . . . . . . . .
Step Rate Control
. . . . . . . . . . . . . . . . . . . .
22 Bit Addressing
. . . . . . . . . . . . . . . . . . . .
Miscellaneous Options
. . . . . . . . . . . . . . . . . .
DRIVE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . .
Drive Selection Signals
. .
20
. .
20
. .
20
. .
21
. .
22
. .
23
. .
25
. .
25
. . . . . . . . . . . . . . . . .
Head Load Signal . . . . . . . . . . . . . . . . . . . . .
Motor Control
. . . . . . . . . . . . . . . . . . . . . .
CABLING . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTROLLER INSTALLATION . . . . . . . . . . . . . . . . . . . .
INITIAL OPERATION AND CHECKOUT
SECTION 3
. . . . . . . . . . . . . . . .
FUNCTIONAL DESCRIPTION
REGISTER DEFINITIONS
. . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
MXVCS - Command and Status Register (177170 U8 D)
. . . .
25
. . . .
27
MXVDB - Data Buffer (177172 U8 D)
. . . .
. . . . . . . . . . . .
Extended Status Register . . . . . . . . . . . . . . . . .
. .
31
. .
32
. .
32
. .
33
. .
34
. .
35
. .
35
. .
37
. .
37
. .
37
. .
39
. .
39
. .
39
. .
40
COMMAND PROTOCOL
. . . . . . . . . . . . . . . . . . . . . . .
Fill Buffer (000)
. . . . . . . . . . . . . . . . . . . .
Empty Buffer (001) . . . . . . . . . . . . . . . . . . . .
Write Sector (010) . . . . . . . . . . . . . . . . . . . .
Read Sector (011)
. . . . . . . . . . . . . . . . . . . .
Set Media Density (100)
Read Status (101)
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
Write Deleted Data Sector (110)
Read Error Code (111)
SECTION 4
. . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
CONTROLLER OPERATIONS . . . . . . . . . . . . . . .
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOTSTRAPPING THE CONTROLLER
Bootstrap Operation
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .
i
FORMAT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . .
. .
40
. .
42
. .
43
. .
44
. .
44
. .
45
. .
47
. .
47
. .
47
. .
48
FILL/WRITE OPERATIONS . . . . . . . . . . . . . . . . . . . . .
READ/EMPTY OPERATIONS . . . . . . . . . . . . . . . . . . . . .
WRITE CURRENT CONTROL . . . . . . . . . . . . . . . . . . . . .
WRITE PRECOMPENSATION . . . . . . . . . . . . . . . . . . . . .
POWER FAIL PROTECTION . . . . . . . . . . . . . . . . . . . . .
SECTION 5
SOFTWARE CONSIDERATIONS . . . . . . . . . . . . . .
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATION USING RT-11 V4.0
. . . . . . . . . . . . . . . . . .
Modifying RX02 Driver for RT11 . . . . . . . . . . . . . .
Creating a DY-Compatible System Disk from a DX-based System
.
48
OPERATION WITH RT-11 V5.0 . . . . . . . . . . . . . . . . . . .
. .
49
. .
49
. .
49
. .
50
. .
51
. .
54
OPERATION WITH LAYERED PRODUCTS . . . . . . . . . . . . . . . .
OPERATION WITH RSX11M . . . . . . . . . . . . . . . . . . . . .
Modifying RX02 Driver RSX11M . . . . . . . . . . . . . . .
APPENDIX A
. . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX B
. . . . . . . . . . . . . . . . . . . . . . . . . .
ii
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