Epson RX-8581JE Clock User Manual

MQ372-02
Application
Manual
Real Time Clock Module
RX-8581SA/JE/NB
Model
Product Number
RX-8581SA
Q4185815xxxxx00
RX-8581JE
Q4185817xxxxx00
RX-8581NB
Q4185819xxxxx00
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NOTICE
• The material is subject to change without notice.
• Any part of this material may not be reproduced or duplicated in any form or any means without the
written permission of Seiko Epson.
• The information, applied circuit, program, using way etc., written in this material is just for reference.
Seiko Epson does not assume any liability for the occurrence of infringing any patent or copyright of third
party. This material does not authorize the licence for any patent or intellectual property rights.
• Any product described in this material may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an
export licence from the Ministry of International Trade and industry or other approval from another
government agency.
• The products (except for some product for automotive applications) listed up on this material are designed
to be used with ordinary electronic equipment (OA equipment, AV equipment, communications equipment,
measuring instruments etc). Seiko Epson does not assume any liability for the case using the products with
the appoication required high reliability or safety extremely (such as aerospace equipment etc).
When intending to use any our product with automotive application and the other application than
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RX - 8581 SA / JE / NB
Contents
1. Overview...................................................................................................................1
2. Block Diagram ........................................................................................................1
3. Terminal description.............................................................................................2
3.1. Terminal connections ..............................................................................................................2
3.2. Pin Functions .............................................................................................................................2
4. Absolute Maximum Ratings ..............................................................................3
5. Recommended Operating Conditions ...........................................................3
6. Frequency Characteristics .................................................................................3
7. Electrical Characteristics ....................................................................................3
7.1. DC characteristics .........................................................................................................................3
7.2. AC Characteristics ....................................................................................................................4
8. Use Methods ...........................................................................................................5
8.1. Overview of Functions .............................................................................................................5
8.2. Description of Registers .........................................................................................................6
8.3. Fixed-cycle Timer Interrupt Function ................................................................................13
8.4. Time Update Interrupt Function .........................................................................................16
8.5. Alarm Interrupt Function .......................................................................................................18
8.6. Reading/Writing Data via the I2C Bus Interface ...........................................................21
8.7. Backup and Recovery ...........................................................................................................25
8.8. Connection with Typical Microcontroller ..........................................................................25
9. External Dimensions / Marking Layout ........................................................26
10. Reference Data .................................................................................................27
11. Application notes ..............................................................................................28
11.1. Notes on handling ................................................................................................................28
11.2. Notes on packaging .............................................................................................................28
RX - 8581 SA / JE / NB
I2C-Bus Interface Real-time Clock Module
RX - 8581 SA / JE / NB
•
•
•
•
•
•
•
•
•
•
•
Features built-in 32.768-kHz crystal oscillator, frequency adjusted
2
Supports I C-Bus's high speed mode (400 kHz)
Alarm interrupt function for day, date, hour, and minute settings
Fixed-cycle timer interrupt function
(Seconds, minutes)
Time update interrupt function
(FOE and FOUT pins)
32.768-kHz output with OE function
(from 2000 to 2099)
Auto correction of leap years
Wide interface voltage range: 1.8 V to 5.5 V
Wide time-keeping voltage range:1.6 V to 5.5 V
Low current consumption: 0.45 µA /3 V (Typ.)
Compact package (NB: SON−22 pin PKG)
2
The I C-Bus is a trademark of PHILIPS ELECTRONICS N.V.
1. Overview
2
This module is an I C bus interface-compliant real-time clock which includes a 32.768-kHz crystal oscillator.
In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter
function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer
function, time update interrupt function, and 32.768-kHz output function.
The devices in this module are fabricated via a C-MOS process for low current consumption, which enables
long-term battery back-up.
All of these many functions are implemented in a thin, compact SON package, which makes it suitable for
various kinds of mobile telephones and other small electronic devices.
2. Block Diagram
32.768 kHz
OSC
FOUT
FOE
/ INT
CLOCK
and
CALENDAR
DIVIDER
FOUT
TIMER
CONTROLLER
INTERRUPT
ALARM
CONTROLLER
SCL
REGISTER
CONTROL
REGISTER
I2C-BUS
INTERFACE
SDA
REGISTER
and
CIRCUIT
Page - 1
SYSTEM
CONTROLLER
MQ372-02
RX - 8581 SA / JE / NB
3. Terminal description
3.1. Terminal connections
RX - 8581 SA
RX - 8581 JE
SOP − 14 pin
#1
VSOJ − 20 pin
# 14
#7
SON − 22 pin
#1
# 14
# 10
# 11
#1
# 14
# 11
(#12)
#8
No. Pin terminal No. Pin terminal
1
2
3
4
5
6
7
RX - 8581 NB
N.C.
SCL
SDA
N.C.
GND
N.C.
/ INT
14
13
12
11
10
9
8
FOUT
N.C.
N.C.
VDD
FOE
N.C.
N.C.
No. Pin terminal No. Pin terminal
1
2
3
4
5
6
7
8
9
10
N.C.
N.C.
FOE
VDD
FOUT
SCL
SDAT
( VDD )
GND
/ INT
20
19
18
17
16
15
14
13
12
11
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
No. Pin terminal No. Pin terminal
1
2
3
4
5
6
7
8
9
10
11
/ INT
GND
( VDD )
N.C.
SDA
SCL
FOUT
VDD
FOE
N.C.
N.C.
22
21
20
19
18
17
16
15
14
(13)
(12)
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
−
−
3.2. Pin Functions
Signal
name
I/O
SCL
I
Function
2
This is the serial clock input pin for I C Bus communications.
SDA
I/O
This pin's signal is used for input and output of address, data, and ACK bits,
2
synchronized with the serial clock used for I C communications.
Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable
pull-up resistance relative to the signal line capacity.
FOUT
O
This is the C-MOS output pin with output control provided via the FOE pin.
When FOE = "H" (high level), this pin outputs a 32.768-kHz signal.
When output is stopped, the FOUT pin = "L" (low level).
FOE
I
This is an input pin used to control the output mode of the FOUT pin.
When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the
FOUT pin is stopped.
/INT
O
This pins is used to output alarm signals, timer signals, time update signals, and other
signals. This pin is an open drain pin.
VDD
−
This pin is connected to a positive power supply.
(VDD)
−
Although this pin has the same potential as VDD, it should not be connected externally.
GND
−
This pin is connected to a ground.
N.C.
−
This pin is not connected to the internal IC.
Leave N.C. pins open or connect them to GND or VDD.
(Note) Note with caution that in the RX-8581NB (SON-22 pin), the N.C. pins (pins 14 to
22) are interconnected via the internal frame.
Note: Be sure to connect a bypass capacitor rated at least 0.1 µF between VDD and GND.
Page - 2
MQ372-02
RX - 8581 SA / JE / NB
4. Absolute Maximum Ratings
GND = 0 V
Item
Symbol
Condition
Supply voltage
Input voltage (1)
Input voltage (2)
Output voltage (1)
Output voltage (2)
VDD
VIN1
VIN2
VOUT1
VOUT2
Storage temperature
TSTG
Between VDD and GND
FOE pin
SCL and SDA pins
FOUT pin
SDA and /INT pins
When stored separately,
without packaging
Rating
−0.3
GND−0.3
GND−0.3
GND−0.3
GND−0.3
to
to
to
to
to
Unit
+7.0
VDD+0.3
+8.0
VDD+0.3
+8.0
V
V
V
V
V
−55 to +125
°C
5. Recommended Operating Conditions
GND = 0 V V
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating supply voltage
Clock supply voltage
Operating temperature
VDD
VCLK
TOPR
−
−
No condensation
1.8
1.6
−40
3.0
3.0
+25
5.5
5.5
+85
V
V
°C
6. Frequency Characteristics
Item
Symbol
Frequency precision
Frequency/voltage
characteristics
Frequency/temperature
characteristics
Oscillation start time
Aging
∆ f /f
GND = 0 V
Condition
Rating
Ta = +25 °C, VDD = 3.0 V
Ta = −10 °C to +70 °C,
VDD = 3.0 V ; +25 °C reference
Ta = +25 °C, VDD = 3.0 V
Ta = +25 °C, VDD = 3.0 V, first year
Top
tSTA
fa
× 10
5 ± 23.0 (∗1)
Ta = +25 °C, VDD = 2.0 V to 5.0 V
f /V
Unit
-6
± 2 Max.
× 10 /V
+10 / −120
× 10−6
3 Max.
± 5 Max.
s
× 10−6 /year
-6
(∗1) Precision gap per month: 1 minutes (excluding offset value)
7. Electrical Characteristics
*Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C
7.1. DC characteristics
Item
Symbol
Current
consumption (1)
Current
consumption (2)
Current
consumption (3)
VIH1
VIH2
VIL
Input pin
IDD1
IDD2
IDD3
Current
consumption (4)
IDD4
Current
consumption (5)
IDD5
Current
consumption (6)
IDD6
High-level
input voltage
Low-level
input voltage
High-level
output voltage
Low-level
output voltage
Input leakage
current
Output leakage
current
Condition
fSCL = 0 Hz
/INT = VDD, FOE = GND
FOUT; output OFF
( low level )
fSCL = 0 Hz
/INT, FOE = VDD
FOUT;
32.768 kHz output ON ,
CL = 0 pF
fSCL = 0 Hz
/INT, FOE = VDD
FOUT ;
32.768 kHz output ON ,
CL = 30 pF
FOE pin
SCL and SDA pins
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
VOL4
VOL5
VOL6
FOUT pin
FOUT pin
/INT pin
SDA pin
Min.
Typ.
Max.
VDD = 5 V
0.65
1.2
VDD = 3 V
0.45
0.8
VDD = 5 V
3.0
7.5
VDD = 3 V
1.7
4.5
VDD = 5 V
8.0
20.0
VDD = 3 V
5.0
12.0
Unit
µA
µA
µA
VDD=5 V, IOH=−1 mA
VDD=3 V, IOH=−1 mA
VDD=3 V, IOH=−100 µA
VDD=5 V, IOL=1 mA
VDD=3 V, IOL=1 mA
VDD=3 V, IOL=100 µA
VDD=5 V, IOL=1 mA
VDD=3 V, IOL=1 mA
VDD ≥2 V, IOL=3 mA
0.7 × VDD
0.7 × VDD
VDD + 0.3
6.0
V
V
GND − 0.3
0.3 × VDD
V
4.5
2.2
2.9
GND
GND
GND
GND
GND
GND
5.0
3.0
3.0
GND+0.5
GND+0.8
GND+0.1
GND+0.25
GND+0.4
GND+0.4
V
V
V
V
ILK
Input pin, VIN = VDD or GND
−0.5
0.5
µA
IOZ
/INT, SDA, FOUT pins, VOUT = VDD or GND
−0.5
0.5
µA
Page - 3
MQ372-02
RX - 8581 SA / JE / NB
* Unless otherwise specified,
GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C
7.2. AC Characteristics
Item
Symbol
SCL clock frequency
Start condition setup time
Start condition hold time
Data setup time
Data hold time
Stop condition setup time
Bus idle time between
start condition and stop condition
Time when SCL = "L"
Time when SCL = "H"
Rise time for SCL and SDA
Fall time for SCL and SDA
Allowable spike time on bus
FOUT duty
Condition
Min.
Typ.
Max.
Unit
400
fSCL
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
0.6
0.6
100
0
0.6
kHz
µs
µs
ns
ns
µs
tBUF
1.3
µs
tLOW
tHIGH
tr
tf
tSP
1.3
0.6
0.3
0.3
50
µs
µs
µs
µs
ns
55
%
VDD = 2.4 V ∼ 5.5 V
50% of VDD level
tW /t
45
50
Timing chart
Protocol
START
CONDITION
(S)
tSU ; STA
BIT 7
MSB
(A7)
tLOW
BIT 6
BIT 0
LSB
(R/W)
(A6)
tHIGH
ACK
(A)
STOP
CONDITION
(P)
1 / fSCL
START
CONDITION
(S)
tSU ; STA
SCL
(S)
(P)
(S)
tBUF
tr
tf
SDA
(A)
tHD ; STA
Caution:
tSU ; DAT
tHD ; DAT
tSP
tSU ; STO
tHD ; STA
When accessing this device, all communication from transmitting the start condition to transmitting the stop
condition after access should be completed within 0.95 seconds.
2
If such communication requires 0.95 seconds or longer, the I C bus interface is reset by the internal bus
timeout function.
Page - 4
MQ372-02
RX - 8581 SA / JE / NB
8. Use Methods
8.1. Overview of Functions
1) Clock functions
This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data.
Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year
2099.
∗ For details, see "8.2. Description of Registers".
2) Fixed-cycle interrupt generation function
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set
between 244.14 µs and 4095 minutes.
When an interrupt event is generated, the /INT pin goes to low level ("L") and "1" is set to the TF bit to report that an
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the
/INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the
/INT status is automatically cleared (/INT status changes from low level to Hi-Z).
∗ For details, see "8.3. Fixed-cycle Interrupt Function". .
3) Time update interrupt function
The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the
timing of the internal clock.
When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the
/INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared
(/INT status changes from low level to Hi-Z) 7.8 ms (a fixed value) after the interrupt occurs.
∗ For details, see "8.4. Time Update Interrupt Function".
4) Alarm interrupt function
The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and
minute settings.
When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an
event has occurred.
∗ For details, see "8.5. Alarm Interrupt Function".
5) 32.768-kHz clock output
The 32.768-kHz clock (with precision equal to that of the built-in crystal oscillator) can be output via the FOUT pin.
The FOUT pin is a CMOS output pin which can be set for clock output when the FOE pin is at high level and for
low-level output when the FOE pin is at low level.
6) Interface with CPU
2
Data is read and written via the I C bus interface using two signal lines: SCL (clock) and SDA (data).
Since neither SCL nor SDA includes a protective diode on the VDD side, a data interface between hosts with differing
supply voltages can still be implemented by adding pull-up resistors to the circuit board.
2
The SCL's maximum clock frequency is 400 kHz (when VDD ≥ 1.8 V), which supports the I C bus's high-speed mode.
∗ For further description of data read/write operations, see "8.6 Reading/Writing Data via the I2C Bus Interface".
Page - 5
MQ372-02
RX - 8581 SA / JE / NB
8.2. Description of Registers
8.2.1. Register table
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
0
1
2
3
4
5
6
7
8
9
SEC
MIN
HOUR
WEEK
DAY
MONTH
YEAR
RAM
MIN Alarm
HOUR Alarm
WEEK Alarm
DAY Alarm
Timer Counter 0
Timer Counter 1
Extension Register
Flag Register
Control Register
!
!
40
40
!
!
10
10
10
4
10
10
10
•
10
10
4
10
16
•
TE
TF
TIE
8
8
8
3
8
8
8
•
8
8
3
8
8
2048
4
4
4
2
4
4
4
•
4
4
2
4
4
1024
!
!
AF
AIE
!
A
B
C
D
E
F
!
6
!
!
20
20
20
5
20
!
!
!
80
•
AE
AE
40
20
•
•
40
20
20
•
6
5
AE
20
•
128
64
32
•
•
•
TEST WADA USEL
!
!
UF
!
!
UIE
!
bit 1
bit 0
2
1
2
1
2
1
1
0
2
1
2
1
2
1
•
•
2
1
2
1
1
0
2
1
2
1
512
256
TSEL1 TSEL0
!
VLF
STOP RESET
Remark
∗3
∗3
∗3
∗3
∗3
∗3
−
∗4
−
∗4
∗4
−
∗4
∗1, ∗3, ∗5
∗1, ∗2, ∗3
∗3
Note
When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before
using the module.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data
or time data is incorrect.
∗1)
During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".
∗ At this point, all other register values are undefined, so be sure to perform a reset before using the module.
∗2)
Only a "0" can be written to the UF, TF, AF, or VLF bit.
∗3)
Any bit marked with "!" should be used with a value of "0" after initialization.
∗4)
Any bit marked with "•" is a RAM bit that can be used to read or write any data.
∗5)
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.
Page - 6
MQ372-02
RX - 8581 SA / JE / NB
8.2.2. Control register (Reg F)
Address
Function
F
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Control Register
!
!
UIE
TIE
AIE
!
STOP
RESET
(Default)
(0)
(0)
(−)
(−)
(−)
(0)
(−)
(−)
∗1) The default value is the value that is read (or is set internally) after powering up from 0 V.
∗2) "o" indicates write-protected bits. A zero is always read from these bits.
∗3) "−" indicates no default value has been defined.
• This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and
calendar operations.
1) UIE (Update Interrupt Enable) bit
When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT
status remains Hi-Z).
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.
Data
Function
UIE
0
Write/Read
1
When a time update interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status changes from low to Hi-Z).
When a time update interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
∗ When a time update interrupt event occurs, low-level output from the /INT pin occurs only when
the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT
status changes from low to Hi-Z) 7.8 ms after the interrupt occurs.
∗ For details, see "8.4. Time Update Interrupt Function".
2) TIE (Timer Interrupt Enable) bit
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT
status remains Hi-Z).
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.
Data
Function
TIE
0
Write/Read
1
When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status changes from low to Hi-Z).
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/INT status changes from Hi-Z to low).
* When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".
3) AIE (Alarm Interrupt Enable) bit
When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT
status remains Hi-Z).
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.
Data
Function
AIE
0
Write/Read
1
When an alarm interrupt event occurs, an interrupt signal is not generated
or is canceled (/INT status changes from low to Hi-Z).
When an alarm interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
∗ When an alarm interrupt event has been generated low-level output from the /INT pin occurs
only when the value of the control register's AIE bit is "1". This setting is retained until the AF bit
value is cleared to zero. (No automatic cancellation)
∗ For details, see "8.5. Alarm Interrupt Function".
[Caution]
(1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.
When an interrupt has occurred (when the /INT pin is at low level), the UF, TF, read AF flags to determine which flag has a value of "1"
(this indicates which type of interrupt event has occurred).
(2) To keep the /INT pin from changing to low level, write "0" to the UIE, TIE, and AIE bits. To check whether an event has occurred without
outputting any interrupts via the /INT pin, use software to monitor the value of the UF, TF, and AF interrupt flags.
Page - 7
MQ372-02
RX - 8581 SA / JE / NB
4) STOP bit
This bit is used to stop functions related to the RTC's internal counter operations.
Writing a "1" to this bit stops the counter operations.
Writing a "0" to this bit cancels stop status (restarts operations).
∗ For optimum performance, do not use this bit for functions other than the clock and calendar functions.
Data
Description
STOP
[Normal operation mode]
0
This bit is used to cancel stop status for (i.e., restart) the clock and calendar
function. Also, when "1" is written to the STOP bit, it cancels stop status for
the fixed-cycle timer function.
∗ When the RESET bit value is "1" operation will not be restarted. To restart operation, a "0" must
be written to both the STOP bit and the RESET bit.
[Operation stop mode]
Write/Read
1
Stops updating of year, month, date, day, hour, minute, and second values
and partially stops the fixed-cycle timer function.
(Stop 1) Stops updating of year, month, date, day, hour, minute, and
second values
• This stops all clock and calendar update operations.
Once this occurs, no more time update interrupt events or alarm
interrupt events occur.
(Stop 2) Partially stops the fixed-cycle timer function
• If the fixed-cycle timer's source clock settings include an update
setting of 64 Hz, 1 Hz, or "Minute", the fixed-cycle timer function does
not operate.
∗ However, this function does operate when the fixed-cycle timer's source
clock setting is 4096 Hz.
When this bit value is "1", internal divider stops from 2048Hz to 1 Hz .
5) RESET bit
Like the STOP function described above, this function stops functions related to counter operations. It also
resets the RTC module's internal counter value when the value is less than one second.
Writing a "1" to this bit stops the counter operation and resets the RTC module's internal counter value when the
value is less than one second.
Writing a "0" to this bit cancels stop status for (restarts) these operations. If a STOP condition or repeated
START condition is received while the 0.95-second bus timeout function is operating, stop status is automatically
canceled (the RESET bit value is changed from "1" to "0").
∗ For optimum performance, do not use this bit for functions other than the clock and calendar functions.
RESET
Data
Description
[Normal operation mode]
0
This bit is used to cancel stop status for (i.e., restart) the clock and calendar
function. Also, when "1" is written to the RESET bit, it cancels stop status for
the fixed-cycle timer function.
∗ Since operation is not restarted when the STOP bit value is "1", to restart operation, a "0" must be
written to both the STOP bit and the RESET bit.
[Operation stop mode]
Write/Read
1
Stops updating of year, month, date, day, hour, minute, and second values
and partially stops the fixed-cycle timer function.
(Stop 1) Stops updating of year, month, date, day, hour, minute, and
second values
• This stops all clock and calendar update operations.
Once this occurs, no more time update interrupt events or alarm
interrupt events occur.
(Stop 2) Partially stops the fixed-cycle timer function
• If the fixed-cycle timer's source clock settings include an update
setting of 64 Hz, 1 Hz, or "Minute", the fixed-cycle timer function does
not operate.
∗ However, this function does operate when the fixed-cycle timer's source clock setting is
4096 Hz.
(Note) When this bit value is "1", the internal divider keeps the reset state, from 2048Hz to 1 Hz .
Page - 8
MQ372-02
RX - 8581 SA / JE / NB
8.2.3. Flag register (Reg-E)
Address
Function
bit 7
E
Flag register
(Default)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
!
!
UF
TF
(0)
(0)
(−)
(−)
bit 0
AF
!
VLF
!
(−)
(0)
(1)
(0)
∗1) The default value is the value that is read (or is set internally) after powering up from 0 V.
∗2) "o" indicates write-protected bits. A zero is always read from these bits.
∗3) "−" indicates a default value is undefined.
• This register is used to detect the occurrence of various interrupt events and reliability problems in internal data.
1) UF (Update Flag) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a time update interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
∗ For details, see "8.4. Time Update Interrupt Function".
2) TF (Timer Flag) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".
3) AF (Alarm Flag) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred.
Once this flag bit's value is "1", its value is retained until a "0" is written to it.
∗ For details, see "8.5. Alarm Interrupt Function".
4) VLF (Voltage Low Flag) bit
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"
when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained
until a "0" is written to it.
This bit's value is "1" after powering up from 0 V.
VLF
Data
Description
0
The VLF bit is cleared to zero to prepare for the next status detection.
1
This bit is invalid after a "1" has been written to it.
Write
0
Read
1
Data loss is not detected.
Data loss is detected.
All registers must be initialized.
(This setting is retained until a "zero" is written to this bit.)
Page - 9
MQ372-02
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8.2.4. Extension register (Reg-D)
Address
Function
bit 7
bit 6
bit 5
bit 4
D
Extension Register
TEST
WADA
USEL
TE
(Default)
(0)
(−)
(−)
(−)
∗1)
∗2)
∗3)
bit 3
bit 2
bit 1
bit 0
!
!
TSEL1
TSEL0
(0)
(0)
(−)
(−)
The default value is the value that is read (or is set internally) after powering up from 0 V.
"o" indicates write-protected bits. A zero is always read from these bits.
"−" indicates a default value is undefined.
• This register is used to specify the target for the alarm function or time update interrupt function and to select or
set operations such as fixed-cycle timer operations.
1) TEST bit
This is the manufacturer's test bit. Its value should always be "0".
Be careful to avoid writing a "1" to this bit when writing to other bits.
∗ If a "1" is inadvertently written to this TEST bit, there is a safety function where by this bit will be automatically cleared to zero when a STOP
condition or Repeated START condition is received or when the 0.95-second bus timeout function operates.
Data
TEST
Description
∗ Default
0
Normal operation mode
1
Setting prohibited (manufacturer's test bit)
Write/Read
2) WADA (Week Alarm/Day Alarm) bit
This bit is used to specify either WEEK or DAY as the target of the alarm interrupt function.
Writing a "1" to this bit specifies DAY as the comparison object for the alarm interrupt function.
Writing a "0" to this bit specifies WEEK as the comparison object for the alarm interrupt function.
∗ For details, see "8.5. Alarm Interrupt Function".
3) USEL (Update Interrupt Select) bit
This bit is used to specify either "second update" or "minute update" as the update generation timing of the time
update interrupt function.
Writing a "1" to this bit specifies the internal clock's "minute update" (once per minute) operation as the timing
by which time update interrupts are generated.
Writing a "0" to this bit specifies the internal clock's "second update" (once per second) operation as the timing
by which time update interrupts are generated.
∗ For details, see "8.4. Time Update Interrupt Function".
4) TE (Timer Enable) bit
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.
Writing a "1" to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a
preset value).
Writing a "0" to this bit specifies stopping of the fixed-cycle timer interrupt function.
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".
5) TSEL0,1 (Timer Select 0, 1) bits
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL1
TSEL0
Source clock
TSEL0,1
(bit 1)
(bit 0)
Write/Read
/Once per 244.14 µs
0
0
4096 Hz
0
1
64 Hz
1
0
"Second" update
/Once per second
1
1
"Minute" update
/Once per minute
/ Once per 15.625 ms
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".
8.2.5. RAM register (Reg - 7)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
7
RAM
•
•
•
•
•
•
•
•
• This RAM register is read/write accessible for any data in the range from 00 h to FF h.
Page - 10
MQ372-02
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8.2.6. Clock counter (Reg - 0 ∼ 2)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
2
SEC
MIN
HOUR
!
!
40
40
!
!
20
20
20
10
10
10
8
8
8
4
4
4
2
2
2
1
1
1
∗) "o" indicates write-protected bits. A zero is always read from these bits.
• The clock counter counts seconds, minutes, and hours.
• The data format is BCD format. For example, when the "seconds" register value is "0101 1001" it indicates 59
seconds.
∗ Note with caution that writing non-existent time data may interfere with normal operation of the clock counter.
1) Second counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
SEC
!
40
20
10
8
4
2
1
• This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from
00 seconds.
• When data was written to seconds counter, the internal divider is reset from 2048Hz to 1Hz.
2) Minute counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
MIN
!
40
20
10
8
4
2
1
• This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from
00 minutes.
3) Hour counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
2
HOUR
!
!
20
10
8
4
2
1
• This hour counter counts from "00" hours to "01," "02," and up to 23 hours, after which it starts again from
00 hours.
8.2.7. Day counter (Reg - 3)
Address
3
∗)
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WEEK
!
6
5
4
3
2
1
0
"o" indicates write-protected bits. A zero is always read from these bits.
• The day (of the week) is indicated by 7 bits, bit 0 to bit 6.
The day data values are counted as: Day 01h → Day 02h → Day 04h → Day 08h → Day 10h → Day
20h → Day 40h → Day 01h → Day 02h, etc.
• The correspondence between days and count values is shown below.
WEEK
Write/Read
Write prohibit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
∗ Do not set "1" to more than one day at the same time.
Also, note with caution that any setting other than the
seven shown above should not be made as it may
interfere with normal operation.
Page - 11
1
0
0
0
0
0
0
Day
Data [h]
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
01 h
02 h
04 h
08 h
10 h
20 h
40 h
−
−
MQ372-02
RX - 8581 SA / JE / NB
8.2.8. Calendar counter (Reg 4 to 6)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
4
5
6
DAY
MONTH
YEAR
!
!
20
!
!
!
80
40
20
10
10
10
8
8
8
4
4
4
2
2
2
1
1
1
∗)
"o" indicates write-protected bits. A zero is always read from these bits.
• The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099.
• The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st.
∗ Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter.
1) Date counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
4
DAY
!
!
20
10
8
4
2
1
• The updating of dates by the date counter varies according to the month setting.
∗ A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). In
February of a leap year, the counter counts dates from "01," "02," "03," to "28," "29," "01," etc.
DAY
Write/Read
Month
Date update pattern
01, 02, 03 ∼ 30, 31, 01 ∼
01, 02, 03 ∼ 30, 01, 02 ∼
01, 02, 03 ∼ 28, 01, 02 ∼
01, 02, 03 ∼ 28, 29, 01 ∼
1, 3, 5, 7, 8, 10, or 12
4, 6, 9, or 11
February in normal year
February in leap year
2) Month counter
Address
5
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MONTH
!
!
!
10
8
4
2
1
• The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again
at 01 (January).
3) Year counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
6
Years
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
• The year counter counts from 00, 01, 02 and up to 99, then starts again at 00.
• Any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.) is handled as a leap year.
8.2.9. Alarm registers (Reg - 8 ∼ A)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
8
9
MIN Alarm
HOUR Alarm
WEEK Alarm
DAY Alarm
AE
AE
40
•
6
•
20
20
5
20
10
10
4
10
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
A
AE
• The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified date, day,
hour, and minute values.
• When the settings in the above alarm registers and the WADA bit match the current time, the /INT pin goes to low
level and "1" is set to the AF bit to report that and alarm interrupt event has occurred.
∗ For details, see "8.5. Alarm Interrupt Function".
8.2.10. Fixed-cycle timer control registers (Reg - B ∼ C)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
B
C
Timer Counter 0
Timer Counter 1
128
•
64
•
32
•
16
•
8
2048
4
1024
2
512
1
256
• These registers are used to set the preset countdown value for the fixed-cycle timer interrupt function.
The TE, TF, TIE, and TSEL0/1 bits are also used to set the fixed-cycle timer interrupt function.
• When the value in the above fixed-cycle timer control register changes from 001h to 000h, the /INT pin goes to
low level and "1" is set to the TF bit to report that a fixed-cycle timer interrupt event has occurred.
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".
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MQ372-02
RX - 8581 SA / JE / NB
8.3. Fixed-cycle Timer Interrupt Function
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set
between 244.14 µs and 4095 minutes.
When an interrupt event is generated, the /INT pin goes to low level and "1" is set to the TF bit to report that an
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from
the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low-level to Hi-Z).
∗ Example of
/INT operation
7.8ms
(Max.)
TIE = " 1 " → " 0 "
period
TIE = " 1 "
TE = " 0 " → " 1 "
8.3.1. Diagram of fixed-cycle timer interrupt function
Fixed-cycle timer starts
Fixed-cycle timer stops
"1"
(1)
TE bit
(7)
Operation of fixed-cycle timer
"0"
(9)
"1"
"1"
(5)
TIE bit
"0"
Hi - z
/INT output
(7)
(6)
tRTN
tRTN
tRTN
tRTN
(8)
(4)
(3)
TF bit
period
Event occurs
(1)
• • • 001
period
h → 000 h
∗ Even when the TF
bit is cleared to zero,
the /INT status does
not change.
period
∗ Even when the TE bit is
cleared to zero, /INT
remains low during the
tRTN time.
"L"
"1"
"0"
period
(2)
(7)
∗ When the TE bit value changes from "0" to "1" the fixed-cycle timer function starts.
The counter always starts counting down from the preset value when the TE value changes from "0" to "1".
RTC internal operation
Write operation
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
When a "1" is written to the TE bit, the fixed-cycle timer countdown starts from the preset value.
A fixed-cycle timer interrupt event starts a countdown based on the countdown period (source clock). When
the count value changes from 001h to 000h, an interrupt event occurs.
∗ After the interrupt event that occurs when the count value changes from 001h to 000h, the counter
automatically reloads the preset value and again starts to count down. (Repeated operation)
When a fixed-cycle timer interrupt event occurs, "1" is written to the TF bit.
When the TF bit = "1" its value is retained until it is cleared to zero.
If the TIE bit = "1" when a fixed-cycle timer interrupt occurs, /INT pin output goes low.
∗ If the TIE bit = "0" when a fixed-cycle timer interrupt occurs, /INT pin output remains Hi-Z.
Output from the /INT pin remains low during the tRTN period following each event, after which it is
automatically cleared to Hi-Z status.
∗ /INT is again set low when the next interrupt event occurs.
When a "0" is written to the TE bit, the fixed-cycle timer function is stopped and the /INT pin is set to Hi-Z
status.
∗ When /INT = low, the fixed-cycle timer function is stopped. The tRTN period is the maximum amount of time
before the /INT pin status changes from low to Hi-Z.
As long as /INT = low, the /INT pin status does not change when the TF bit value changes from "1" to "0".
When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the TIE bit value changes from "1" to
"0".
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MQ372-02
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8.3.2. Related registers for function of time update interrupts.
Address
Function
bit 7
bit 6
B
C
D
E
F
∗1)
∗2)
Timer Counter 0
Timer Counter 1
Extension Register
Flag Register
Control Register
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
16
•
TE
TF
TIE
8
2048
4
1024
2
512
TSEL1
1
256
TSEL0
128
•
64
•
32
•
TEST
WADA
USEL
!
!
UF
!
!
UIE
!
!
AF
!
VLF
!
AIE
!
STOP
RESET
"o" indicates write-protected bits. A zero is always read from these bits.
Bits marked with "•" are RAM bits that can contain any value and are read/write-accessible.
∗ Before entering settings for operations, we recommend writing a "0" to the TE and TIE bits to prevent hardware
interrupts from occurring inadvertently while entering settings.
∗ When the STOP bit or RESET bit value is "1" the time update interrupt function operates only partially.
(Operation continues if the source clock setting is 4096 Hz. Otherwise, operation is stopped.)
∗ When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register (Reg – B to
C) can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and
TIE bits.
1) TSEL0,1 bits (Timer Select 0, 1)
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL1 TSEL0
Auto reset time Effects of STOP
TSEL0,1
Source clock
(bit 1) (bit 0)
tRTN
and RESET bits
0
0
4096 Hz /Once per 244.14 µs
122 µs
−
0
1
64 Hz / Once per 15.625 ms
7.8125 ms ∗ Does not operate
Write/Read
when the STOP bit
1
0
"Second" update /Once per second
7.8125 ms
or RESET bit value
1
1
"Minute" update /Once per minute
7.8125 ms
is "1".
∗1) The /INT pin's auto reset time (tRTN) varies as shown above according to the source clock setting.
∗2) When the source clock has been set to "second update" or "minute update", the timing of both
countdown and interrupts is coordinated with the clock update timing.
2) Fixed-cycle Timer Control register (Reg - B ∼ C)
This register is used to set the default (preset) value for the counter. Any count value from 1 (001 h) to
4095 (FFFh) can be set. The counter counts down based on the source clock's period, and when the count value
changes from 001h to 000h, the TF bit value becomes "1".
The countdown that starts when the TE bit value changes from "0" to "1" always begins from the preset value.
Be sure to write "0" to the TE bit before writing the preset value. If a value is written while TE = "1" the first
subsequent event will not be generated correctly.
Address C
Address B
Timer Counter 1
Timer Counter 0
bit 7
bit 6
bit 5
bit 4
•
•
•
•
bit 3
2048
bit 2
1024
bit 1
512
bit 0
256
bit 7
128
bit 6
64
bit 5
32
bit 4
16
bit 3
8
bit 2
4
bit 1
2
bit 0
1
3) TE (Timer Enable) bit
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.
Data
Description
TE
0
Stops fixed-cycle timer interrupt function.
1
Starts fixed-cycle timer interrupt function.
∗ The countdown that starts when the TE bit value changes from "0" to "1" always begins from the
Write/Read
preset value.
4) TF (Timer Flag) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
Data
Description
TF
Write
0
The TF bit is cleared to zero to prepare for the next status detection
1
This bit is invalid after a "1" has been written to it.
0
Fixed-cycle timer interrupt events are not detected.
1
Fixed-cycle timer interrupt events are detected.
(Result is retained until this bit is cleared to zero.)
Read
∗ Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).
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MQ372-02
RX - 8581 SA / JE / NB
5) TIE (Timer Interrupt Enable) bit
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value
specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated
(/INT status remains Hi-Z).
Data
Description
TIE
1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status remains Hi-Z).
2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is
canceled (/INT status changes from low to Hi-Z).
∗ Even when the TIE bit value is "0" another interrupt event may change the /INT status to low (or
0
Write/Read
may hold /INT = "L").
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/INT status changes from Hi-Z to low).
∗ When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin
1
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).
8.3.3. Fixed-cycle timer interrupt interval (example)
Timer
Counter
setting
Source clock
4096 Hz
64 Hz
TSEL1,0 = 0,0
TSEL1,0 = 0,1
−
244.14 µs
488.28 µs
0
1
2
"Second"
update
"Minute"
update
TSEL1,0 = 1,0
TSEL1,0 = 1,1
−
15.625 ms
31.25 ms
•
•
•
•
•
•
•
•
•
41
205
410
2048
10.010 ms
50.049 ms
100.10 ms
500.00 ms
•
•
•
•
•
•
•
•
•
4095
0.9998 s
63.984 s
640.63 ms
3.203 s
6.406 s
32.000 s
−
1s
2s
−
1 min
2 min
•
•
•
•
•
•
41 s
205 s
410 s
2048 s
41 min
205 min
410 min
2048 min
•
•
•
•
•
•
4095 s
4095 min
• Time error in fixed-cycle timer
A time error in the fixed-cycle timer will produce a positive or negative time period error in the selected
source clock. The fixed-cycle timer's time is within the following range relative to the time setting.
(Fixed-cycle timer's time setting (∗) − source clock period) to (timer's time setting)
∗) The timer's time setting = source clock period × timer counter's division value.
∗ The time actually set to the timer is adjusted by adding the time described above to the
communication time for the serial data transfer clock used for the setting.
8.3.4. Fixed-cycle timer start timing
Counting down of the fixed-cycle timer value starts at the rising edge of the SCL signal that occurs when the TE
value is changed from "0" to "1" (after bit 0 is transferred).
Address D
SCL pin
SDA pin
TE
0
0
TSEL1 TSEL0 ACK
Internal timer
/INT pin
Operation of timer
Page - 15
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8.4. Time Update Interrupt Function
The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to
the timing of the internal clock.
When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that
an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output
from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is
automatically cleared (/INT status changes from low level to Hi-Z) 7.8 ms (fixed value) after the interrupt occurs.
∗ /INT operation
example
7.8ms
UIE = " 1 " → " 0 "
period
UIE = " 1 "
8.4.1. Time update interrupt function diagram
(7)
"1"
"1"
(4)
UIE bit
"0"
Hi - z
/INT output
(5)
"L"
tRTN
tRTN
tRTN
tRTN
(6)
(3)
(2)
UF bit
period
period
∗ /INT status does not
change when UF bit is
cleared to zero.
period
"1"
"0"
period
(1)
Events
Operation in RTC
i '
i
Write operation
(1) A time update interrupt event occurs when the internal clock's value matches either the second update time or
the minute update time. The USEL bit's specification determines whether it is the second update time or the
minute update time that must be matched.
(2) When a time update interrupt event occurs, the UF bit value becomes "1".
(3) When the UF bit value is "1" its value is retained until it is cleared to zero.
(4) When a time update interrupt occurs, /INT pin output is low if UIE = "1".
∗ If UIE = "0" when a timer update interrupt occurs, the /INT pin status remains Hi-Z.
(5) Each time an event occurs, /INT pin output is low only up to the tRTN time (which is fixed as 7.1825 ms for
time update interrupts) after which it is automatically cleared to Hi-Z.
∗ /INT pin output goes low again when the next interrupt event occurs.
(6) As long as /INT = low, the /INT pin status does not change, even if the UF bit value changes from "1" to "0".
(7) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the UIE bit value changes from "1"
to "0".
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8.4.2. Related registers for time update interrupt functions.
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D
E
F
Extension Register
Flag Register
Control Register
TEST
WADA
TE
!
!
TSEL1
TSEL0
!
!
TF
AF
!
VLF
!
!
!
USEL
UF
UIE
TIE
AIE
!
STOP
RESET
∗)
"o" indicates write-protected bits. A zero is always read from these bits.
∗ Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts
from occurring inadvertently while entering settings.
∗ When the STOP bit or RESET bit value is "1" time update interrupt events do not occur.
∗ Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update
interrupt function can be prevented from changing the /INT pin status to low.
1) USEL (Update Interrupt Select) bit
This bit is used to select "second" update or "minute" update as the timing for generation of time update interrupt
events.
Data
Description
USEL
0
Selects "second update" (once per second) as the timing for generation of
interrupt events
1
Selects "minute update" (once per minute) as the timing for generation of
interrupt events
Write/Read
2) UF (Update Flag) bit
Once it has been set to "0", this flag bit value changes from "0" to "1" when a time update interrupt event occurs.
When this flag bit = "1" its value is retained until a "0" is written to it.
Data
Description
UF
Write
0
The UF bit is cleared to zero to prepare for the next status detection
∗ Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).
1
This bit is invalid after a "1" has been written to it.
0
Time update interrupt events are not detected.
1
Time update interrupt events are detected.
(The result is retained until this bit is cleared to zero.)
Read
3) UIE (Update Interrupt Enable) bit
When a time update interrupt event occurs (UF bit value changes from "0" to "1"), this bit selects whether to
generate an interrupt signal (/INT status changes from Hi-Z to low) or to not generate it (/INT status remains
Hi-Z).
Data
Description
UIE
0
1) Does not generate an interrupt signal when a time update interrupt event
occurs (/INT remains Hi-Z)
2) Cancels interrupt signal triggered by time update interrupt event (/INT
changes from low to Hi-Z).
∗ Even when the UIE bit value is "0" another interrupt event may change the /INT status to low (or
may hold /INT = "L").
Write/Read
1
When a time update interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
∗ When a time update interrupt event occurs, low-level output from the /INT pin occurs only when
the UIE bit value is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically
cleared (/INT status changes from low to Hi-Z).
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8.5. Alarm Interrupt Function
The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and
minute settings.
When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an
event has occurred.
∗ Example of
/INT operation
AIE = " 1 "
( AF = " 0 " → " 1 " )
AF = " 1 " → " 0 " or
AIE = " 1 " → " 0 "
8.4.1. Diagram of alarm interrupt function
"1"
"1"
(4)
AIE bit
"0"
(5)
Hi - z
(7)
/INT output
"L"
(6)
"1"
(3)
(2)
AF bit
"0"
(1)
Event
occurs
RTC internal operation
Write operation
(1) The hour, minute, date or day when an alarm interrupt event is to occur is set in advance along with the
WADA bit, and when the setting matches the current time an interrupt event occurs.
(Note) Even if the current date/time is used as the setting, the alarm will not occur until the counter counts up
to the current date/time (i.e., an alarm will occur next time, not immediately).
(2) When a time update interrupt event occurs, the AF bit values becomes "1".
(3) When the AF bit = "1", its value is retained until it is cleared to zero.
(4) If AIE = "1" when an alarm interrupt occurs, the /INT pin output goes low.
∗ When an alarm interrupt event occurs, /INT pin output goes low, and this status is then held until it is
cleared via the AF bit or AIE bit.
(5) If the AIE value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low to
Hi-Z. After the alarm interrupt occurs and before the AF bit value is cleared to zero, the /INT status can be
controlled via the AIE bit.
(6) If the AF bit value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low
to Hi-Z.
(7) If the AIE bit value is "0" when an alarm interrupt occurs, the /INT pin status remains Hi-Z.
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8.5.2. Related registers
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
2
3
4
8
9
MIN
HOUR
WEEK
DAY
MIN Alarm
HOUR Alarm
WEEK Alarm
DAY Alarm
Extension Register
Flag Register
Control Register
!
40
!
!
!
6
10
10
4
10
10
10
4
10
8
8
3
8
8
8
3
8
4
4
2
4
4
4
2
4
2
2
1
2
2
2
1
2
1
1
0
1
1
1
0
1
A
D
E
F
∗1)
∗2)
!
!
AE
AE
40
•
6
•
20
20
5
20
20
20
5
20
TEST
WADA
USEL
TE
!
!
TSEL1
TSEL0
!
!
UF
TF
!
VLF
!
!
!
UIE
AF
AIE
!
STOP
RESET
AE
TIE
"o" indicates write-protected bits. A zero is always read from these bits.
Bits marked with "•" are RAM bits that can contain any value and are read/write-accessible.
∗ Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts
from occurring inadvertently while entering settings.
∗ When the STOP bit or RESET bit value is "1" alarm interrupt events do not occur.
∗ When the alarm interrupt function is not being used, the Alarm registers (Reg - 8 to A) can be used as a RAM
register. In such cases, be sure to write "0" to the AIE bit.
∗ When the AIE bit value is "1" and the Alarm registers (Reg - 8 to A) is being used as a RAM register, /INT may be
changed to low level unintentionally.
1) WADA (Week Alarm /Day Alarm) bit
The alarm interrupt function uses either "Day" or "Week" as its target. The WADA bit is used to specify either
WEEK or DAY as the target for alarm interrupt events.
Data
Description
WADA
0
Sets WEEK as target of alarm function
(DAY setting is ignored)
1
Sets DAY as target of alarm function
(WEEK setting is ignored)
Write/Read
2) Alarm registers (Reg - 8 to A)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
8
9
MIN Alarm
HOUR Alarm
WEEK Alarm
DAY Alarm
AE
AE
40
•
6
•
20
20
5
20
10
10
4
10
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
A
AE
The hour, minute, date or day when an alarm interrupt event will occur is set using this register and the
WADA bit.
In the WEEK alarm /Day alarm register (Reg - A), the setting selected via the WADA bit determines whether
WEEK alarm data or DAY alarm data will be set. If WEEK has been selected via the WADA bit, multiple
days can be set (such as Monday, Wednesday, Friday, Saturday).
When the settings made in the alarm registers and the WADA bit match the current time, the AF bit value is
changed to "1". At that time, if the AIE bit value has already been set to "1", the /INT pin goes low.
∗1) The register that "1" was set to "AE" bit, doesn't compare alarm.
(Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - A):
Only the hour and minute settings are used as alarm comparison targets. The week and date settings
are not used as alarm comparison targets.
As a result, alarm occurs if only an hour and minute accords with alarm data.
∗2) If all three AE bit values are "1" the week/date settings are ignored and an alarm interrupt event will
occur once per minute.
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3) AF (Alarm Flag) bit
When this flag bit value is already set to "0", occurrence of an alarm interrupt event changes it to "1". When this
flag bit value is "1", its value is retained until a "0" is written to it.
Data
Description
AF
0
Write
The AF bit is cleared to zero to prepare for the next status detection
∗ Clearing this bit to zero enables /INT low output to be canceled (/INT remains Hi-Z) when an alarm
interrupt event has occurred.
1
This bit is invalid after a "1" has been written to it.
0
Alarm interrupt events are not detected.
1
Alarm interrupt events are detected.
(Result is retained until this bit is cleared to zero.)
Read
4) AIE (Alarm Interrupt Enable) bit
When an alarm interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies
whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
Data
Description
AIE
0
1) When an alarm interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status remains Hi-Z).
2) When an alarm interrupt event occurs, the interrupt signal is canceled
(/INT status changes from low to Hi-Z).
∗ Even when the AIE bit value is "0" another interrupt event may change the /INT status to low
Write/Read
(or may hold /INT = "L").
1
When an alarm interrupt event occurs, an interrupt signal is generated (/INT
status changes from Hi-Z to low).
∗ When an alarm interrupt event occurs, low-level output from the /INT pin occurs only when the
AIE bit value is "1". This value is retained (not automatically cleared) until the AF bit is cleared
to zero.
8.5.2. Examples of alarm settings
1) Example of alarm settings when "Day" has been specified (and WADA bit = "0")
Reg – A
Day is specified
bit bit bit bit bit bit bit bit
7 6 5 4 3 2 1 0
WADA bit = "0"
AE S
F
T W
T
M
S
Reg - 9
Reg - 8
HOUR
Alarm
MIN
Alarm
Monday through Friday, at 7:00 AM
∗ Minute value is ignored
0
0
1
1
1
1
1
0
07 h
80 h ∼ FF h
Every Saturday and Sunday, for 30 minutes
each hour ∗ Hour value is ignored
0
1
0
0
0
0
0
1
80 h ∼ FF h
30 h
18 h
59 h
Reg - 9
Reg - 8
HOUR
Alarm
MIN
Alarm
Every day, at 6:59 AM
0
1
1
1
1
1
1
1
1
Χ
Χ
Χ
Χ
Χ
Χ
Χ
Χ: Don't care
2) Example of alarm settings when "Day" has been specified (and WADA bit = "1")
Reg - A
Day is specified
bit bit bit bit bit bit bit bit
7 6 5 4 3 2 1 0
WADA bit = "1"
AE • 20 10 08 04 02 01
First of each month, at 7:00 AM
∗ Minute value is ignored
0
0
0
0
0
0
0
1
07 h
80 h ∼ FF h
15 of each month, for 30 minutes each
hour ∗ Hour value is ignored
0
0
0
1
0
1
0
1
80 h ∼ FF h
30 h
Every day, at 6:59 PM
1
Χ
Χ
Χ
Χ
Χ
Χ
Χ
18 h
59 h
th
Χ: Don't care
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8.6. Reading/Writing Data via the I2C Bus Interface
8.6.1. Overview of I2C-BUS
2
The I C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A
combination of these two signals is used to transmit and receive communication start/stop signals, data transfer
signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed.
The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at
high level.
During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and
on the receiving side the data is output while the SCL line is at high level.
2
The I C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications
only when its slave address matches the slave address in the received data. In either case, the data is transferred
via the SCL line at a rate of one bit per clock pulse.
8.6.2. System configuration
2
All ports connected to the I C bus must be either open drain or open collector ports in order to enable AND
connections to multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both
held at high level when the bus is released (when communication is not being performed).
VDD
SDA
SCL
Master
Slave
Master
Slave
Transmitter/
Receiver
Transmitter/
Receiver
Transmitter/
Receiver
Transmitter/
Receiver
CPU, etc.
RX - 8581
2
Other I C bus device
Any device that controls the data transmission and data reception is defined as a "Master".
and any device that is controlled by a master device is defined as a “Slave”.
The device transmitting data is defined as a “Transmitter” and the device receiving data is defined as a receiver”
In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is
defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a
transmitter or receiver depending on these conditions.
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2
8.6.3. Starting and stopping I C bus communications
START
Repeated START(RESTART)
condition
condition
STOP
condition
SCL
[S]
[ Sr ]
[P]
SDA
0.95 s ( Max. )
1) START condition, repeated START condition, and STOP condition
(1) START condition
•
The SDA level changes from high to low while SCL is at high level.
(2) STOP condition
• This condition regulates how communications on the I2C-BUS are terminated.
The SDA level changes from low to high while SCL is at high level.
(3) Repeated START condition (RESTART condition)
• In some cases, the START condition occurs between a previous START condition and the next
STOP condition, in which case the second START condition is distinguished as a RESTART
condition. Since the required status is the same as for the START condition, the SDA level changes
from high to low while SCL is at high level.
2) Caution points
∗1) The master device always controls the START, RESTART, and STOP conditions for communications.
∗2) The master device does not impose any restrictions on the timing by which STOP conditions affect
transmissions, so communications can be forcibly stopped at any time while in progress. (However,
this is only when this RTC module is in receiver mode (data reception mode = SDA released).
∗3) When communicating with this RTC module, the series of operations from transmitting the START
condition to transmitting the STOP condition should occur within 0.95 seconds. (A RESTART
condition may be sent between a START condition and STOP condition, but even in such cases the
series of operations from transmitting the START condition to transmitting the STOP condition should
still occur within 0.95 seconds.)
2
If this series of operations requires 0.95 seconds or longer, the I C bus interface will be automatically
cleared and set to standby mode by this RTC module's bus timeout function. Note with caution that
both write and read operations are invalid for communications that occur during or after this auto
clearing operation. (When the read operation is invalid, all data that is read has a value of "1").
Restarting of communications begins with transfer of the START condition again
∗4) When communicating with this RTC module, wait at least 1.3 µs (see the tBUF rule) between
transferring a STOP condition (to stop communications) and transferring the next START condition (to
start the next round of communications).
STOP
START
condition
condition
SCL
[P]
[S]
SDA
61 µs (Min.)
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8.6.4. Data transfers and acknowledge responses during I2C-BUS communications
1) Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit
on the amount (bytes) of data that are transferred between the START condition and STOP condition.
(However, the transfer time must be no longer than 0.95 seconds.)
The address auto increment function operates during both write and read operations.
After address Fh, incrementation goes to address 0h.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low
level. The receiver (receiving side) receives data while the SCL line is at high level.
SCL
SDA
Data is valid
when data line is
stable
Data can be
changed
∗ Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a
START, RESTART, or STOP condition.
2) Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an
8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal
communication has not been established. (This does not include instances where the master device intentionally
does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the
transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
1
2
8
SDA from transmitter (sending
side)
9
Release SDA
SDA from receiver (receiving
side)
Low active
ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is
released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer
resumes when the Master becomes the transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent
from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter
continues to release the SDA and awaits a STOP condition from the Master.
8.6.5. Slave address
2
The I C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The
receiving device responds to this communication only when the specified slave address it has received matches its
own slave address.
Slave addresses have a fixed length of 7 bits. This RTC's slave address is [1010 001∗
∗].
An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers.
Slave address
Transfer data
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Read
A3 h
1
0
1
0
0
0
Write
A2 h
Page - 23
R/W bit
bit 1
1
bit 0
1 (= Read)
0 (= Write)
MQ372-02
RX - 8581 SA / JE / NB
2
8.6.6. I C bus protocol
In the following sequence descriptions, it is assumed that the CPU is the master and the RX-8581 is the slave.
a. Address specification write sequence
Since the RX-8581 includes an address auto increment function, once the initial address has been specified,
the RX-8581 increments (by one byte) the receive address each time data is transferred.
(1) CPU transfers start condition [S].
(2) CPU transmits the RX-8581's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RX-8581.
(4) CPU transmits write address to RX-8581.
(5) Check for ACK signal from RX-8581.
(6) CPU transfers write data to the address specified at (4) above.
(7) Check for ACK signal from RX-8581.
(8) Repeat (6) and (7) if necessary. Addresses are automatically incremented.
(9) CPU transfers stop condition [P].
(1)
(2)
S
Slave address
0
(3)
(4)
(5)
(6)
(7)
(8)
0
Address
0
Data
0
Data
(9)
0
P
R/W
ACK signal from RX-8581
b. Address specification read sequence
After using write mode to write the address to be read, set read mode to read the actual data.
(1) CPU transfers start condition [S].
(2) CPU transmits the RX-8581's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RX-8581.
(4) CPU transfers address for reading from 8581.
(5) Check for ACK signal from RX-8581.
(6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition [P]).
(7) CPU transfers RX-8581's slave address with the R/W bit set to read mode.
(8) Check for ACK signal from RX-8581 (from this point on, the CPU is the receiver and the RX-8581 is
the transmitter).
(9) Data from address specified at (4) above is output by the RX-8581.
(10) CPU transfers ACK signal to RX-8581.
(11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented.
(12) CPU transfers ACK signal for "1".
(13) CPU transfers stop condition [P].
(1)
(2)
S
Slave address
0
(3)
(4)
(5)
(6)
(7)
0
Address
0
Sr
Slave address
1
R/W
(8)
(9)
(10)
(11)
0
Data
0
Data
(12) (13)
1
P
R/W
ACK from RX-8581
ACK from CPU
c. Read sequence when address is not specified
Once read mode has been initially set, data can be read immediately. In such cases, the address for each read
operation is the previously accessed address + 1.
(1) CPU transfers start condition [S].
(2) CPU transmits the RX-8581's slave address with the R/W bit set to read mode.
(3) Check for ACK signal from RX-8581 (from this point on, the CPU is the receiver and the RX-8581 is the
transmitter).
(4) Data is output from the RX-8581 to the address following the end of the previously accessed address.
(5) CPU transfers ACK signal to RX-8581.
(6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RX-8581.
(7) CPU transfers ACK signal for "1".
(8) CPU transfers stop condition [P].
(1)
(2)
S
Slave address
1
(3)
(4)
(5)
(6)
(7)
(8)
0
Data
0
Data
1
P
R/W
ACK from RX-8581
ACK from CPU
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8.7. Backup and Recovery
VDD
VCLK
0V
t R1
tF
t R2
Back up
Item
Symbol
Min.
Power supply drop time
tF
2 µs /V
Initial power-up time
t R1
1 µs /V
Clock maintenance power-up time
t R2
1 µs /V
Typ.
Max.
10 ms /V
8.8. Connection with Typical Microcontroller
VDD
SCL
I2C-BUS
master
SDA
VDD
SCL
RX - 8581
SLAVE ADRS = 1010 001∗
SDA
GND
Pull up resistor
R=
tr
C BUS
VDD
SCL
I2C-BUS
Device
SDA
GND
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RX - 8581 SA / JE / NB
9. External Dimensions / Marking Layout
RX-8581 SA (SOP - 14 pin)
• External dimensions
• Recommended soldering
10.1 ± 0.2
#14
0° - 10°
#8
1.4
5.0
7.4 ± 0.2
R8581
E 1234A
5.4
0.6
#1
#7
0.05
Min.
0.35
1.27
1.4
0.15
1.27
3.2 ± 0.1
0.7
1.27 × 6 = 7.62
1.2
Unit : mm
∗ The crystal oscillator's metal case may be visible in the area (on top) indicated in broken lines
but this has no effect on the device's characteristics.
,
RX-8581 JE (VSOJ - 20 pin)
• External dimensions
• Recommended soldering
7.0 ± 0.3
(0.75)
#20
#11
1.5
6.0 ± 0.2
R8581
5.4
E
3.8
0.35
0.65
1234A
0.3
1.5
#1
#10
(0.75)
1.3
0.22
0 Min.
0.65
0.12
0.65 × 9 = 5.85
1.5 Max.
Unit : mm
0.1
∗ The crystal oscillator's metal case may be visible in the area (on front and top) indicated in broken lines
but this has no effect on the device's characteristics.
,
RX-8581 NB (SON - 22 pin)
• External dimensions
• Soldering pattern
6.3 Max.
0.2
0.5
#14
0.8
0.25 0.5
#1
#11
0.7
#11
#11
#1
P 0.5 × 10 = 5.0
0.7
1.3 ± 0.1
0.125
5.25
0.1
1.4
0.7
0.8
4.0
4.8
E 1234A
5.0 ± 0.2
#22
R8564
#1
#22
0.7
#14
(0.3)
0.25 0.75
#14
#22
Unit : mm
∗1) The crystal oscillator's metal case may be visible in the area (on front and top) indicated in broken lines
but this has no effect on the device's characteristics.
∗2) Do not lay out signal patterns on component surfaces indicated by the shaded areas
,
in the soldering
diagram .
Page - 26
MQ372-02
RX - 8581 SA / JE / NB
10. Reference Data
(1) Example of frequency and temperature characteristics
× 10-6
θT = +25 °C Typ.
α = -0.035 × 10-6 Typ.
1. Frequency and temperature characteristics can be
approximated using the following equations.
2
∆fT = α (θT - θX)
: Frequency deviation in any
∆fT
temperature
2
α (1 / °C ) : Coefficient of secondary temperature
-6
2
(−0.035±0.005) × 10 / °C
θT (°C)
: Ultimate temperature (+25±5 °C)
: Any temperature
θX (°C)
Frequency ∆fT
0
-50
-100
-150
-50
0
+50
+100
2. To determine overall clock accuracy, add the frequency
precision and voltage characteristics.
Temperature [°C]
(2) Example of frequency and voltage characteristics
Condition :
3 V as reference, Ta=+25 °C
Frequency ∆fv
× 10−6
+3
[Finding the frequency stability]
0
∆f/f = ∆f/fo + ∆fT + ∆fV
∆f/f : Clock accuracy (stable frequency) in any
temperature and voltage
∆f/fo : Frequency precision
∆fT : Frequency deviation in any temperature
∆fV : Frequency deviation in any voltage
3. How to find the date difference
Date difference = ∆f/f × 86400 (seconds)
-6
* For example: ∆f/f = 11.574 × 10 is an error of
approximately 1 second/day.
-3
2
3
4
5
Supply Voltage VDD[V]
(3) Current and voltage consumption characteristics
(3-1) Current consumption when non-accessed (i)
when FOUT=OFF
(3-2) Current consumption when non-accessed (ii)
when FOUT=32.768 kHz
Condition :
Condition :
10
Current consumption [µA]
Current consumption [µA]
1.0
Ta = +25 °C
fSCL = 0 Hz
FOE = GND, /INT = VDD
FOUT ; Output OFF
0.5
Ta = +25 °C
fSCL = 0 Hz
FOE, /INT = VDD
FOUT ; 32.768 kHz output ON
CL=30 pF
5
CL=0 pF
2
3
4
5
2
Supply Voltage VDD[V]
3
4
5
Supply Voltage VDD[V]
Page - 27
MQ372-02
RX - 8581 SA / JE / NB
11. Application notes
11.1. Notes on handling
This module uses a C-MOS IC to realize low power consumption.
handling.
Carefully note the following cautions when
(1) Static electricity
While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be
damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of
conductive materials. In addition, only soldering irons, measurement circuits, and other such devices which do not leak
high voltage should be used with this module, which should also be grounded when such devices are being used.
(2) Noise
If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch
up." In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1F as close as
possible to the power supply pins (between VDD and GNDs). Also, avoid placing any device that generates high level of
electronic noise near this module.
* Do not connect signal lines to the shaded area in the figure shown in Fig. 1 and, if possible, embed this area in a GND
land.
(3) Voltage levels of input pins
When the input pins are at the mid-level, this will cause increased current consumption and a reduced noise margin, and
can impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VDD or
GND.
(4) Handling of unused pins
Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit
state can lead to unstable voltage level and malfunctions due to noise. Therefore, pull-up or pull-down resistors should be
provided for all unused input pins.
11.2. Notes on packaging
(1) Soldering heat resistance.
If the temperature within the package exceeds +260 °C, the characteristics of the crystal oscillator will be degraded and it
may be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting
temperature and time before mounting this device. Also, check again if the mounting conditions are later changed.
* See Fig. 2 profile for our evaluation of Soldering heat resistance for reference.
(2) Mounting equipment
While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged
in some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the
mounting conditions are later changed, the same check should be performed again.
(3) Ultrasonic cleaning
Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during
ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level,
time, state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during
ultrasonic cleaning.
(4) Mounting orientation
This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before
mounting.
(5) Leakage between pins
Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the
device is dry and clean before supplying power to it.
Fig. 1 : Example GND Pattern
RX - 8581 SA
( SOP-14pin )
Fig. 2 : Reference profile for our evaluation of Soldering heat resistance.
Temperature [ °C ]
+260 °C Max.
−1 ∼ −5 °C / s
+1 ∼ +5 °C / s
RX - 8581 JE
( VSOJ-20pin )
+1 ∼ +5 °C / s
+170 °C
100 s
+220 °C
35 s
Pre-heating area
Stable Melting area
time [ s ]
RX - 8581 NB
( SON-22pin )
Page - 28
MQ372-02
Application Manual
Distributor
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