Fujitsu MPC3045AH Computer Drive Product manual

Add to My manuals
185 Pages

advertisement

Fujitsu MPC3045AH Computer Drive Product manual | Manualzz

MPC3045AH

MPC3065AH

DISK DRIVES

PRODUCT MANUAL

C141-E056-02EN

Edition

01

02

REVISION RECORD

Revised contents Date published

May, 1998

Dec., 1998 Pages 1-4, 4-14, 5-9, 5-16, 5-30, 5-35, 5-37, 5-52 to 5-54, 5-63, 5-64, 5-69, 5-81, 6-8, 6-9 to 6-23 revised.

Specification No.: C141-E056-**EN

C141-E056-02EN

The contents of this manual is subject to change without prior notice.

All Rights Reserved.

Copyright  1998 FUJITSU LIMITED i

This page is intentionally left blank.

PREFACE

This manual describes the MPC3045AH/MPC3065AH, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface.

This manual explains, in detail, how to incorporate the hard disk drives into user systems.

This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.

This manual consists of the following six chapters:

Chapter 1 DEVICE OVERVIEW

Chapter 2

Chapter 3

Chapter 4

Chapter 5

DEVICE CONFIGURATION

INSTALLATION CONDITIONS

THEORY OF DEVICE OPERATION

INTERFACE

Chapter 6 OPERATIONS

In this manual, disk drives may be referred to as drives or devices.

C141-E056-01EN iii

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.

The following are the alert signals and their meanings:

This indicates a hazarous situation likely to result in serious personal

injury if the user does not perform the procedure correctly.

This indicates a hazarous situation could result in personal injury if the user does not perform the porocedure correctly.

This indicates a hazarous situation could result in minor or moderate

personal injury if the user does not perform the procedure correctly.

This alert signal also indicates that damages to the product or other property, may occur if the user does not perform the procedure correctly.

This indicates information that could help the user use the product more efficiently.

In the text, the alert signal is centered, followed below by the indented message. A wider line space precedes and follows the alert message to show where the alert message begins and ends. The following is an example:

(Example)

IMPORTANT

HA (host adapter) consists of address decoder, driver, and receiver.

ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-3 interface

The main alert messages in the text are also listed in the “Important Alert Items.” iv C141-E056-01EN

LIABILITY EXCEPTION

"Disk drive defects" refers to defects that involve adjustment, repair, or replacement.

Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

C141-E056-01EN v

This page is intentionally left blank.

CONTENTS

page

CHAPTER 1

DEVICE OVERVIEW ................................................................................... 1 - 1

1.1

Features .......................................................................................................................... 1 - 1

1.1.1

Functions and performance ............................................................................................ 1 - 1

1.1.2

Adaptability .................................................................................................................... 1 - 2

1.1.3

Interface.......................................................................................................................... 1 - 2

1.2

Device Specifications ..................................................................................................... 1 - 4

1.2.1

Specifications summary.................................................................................................. 1 - 4

1.6

1.7

1.8

1.9

1.2.2

Model and product number ............................................................................................ 1 - 5

1.3

Power Requirements....................................................................................................... 1 - 5

1.4

1.5

Environmental Specifications ......................................................................................... 1 - 8

Acoustic Noise ............................................................................................................... 1 - 8

Shock and Vibration ....................................................................................................... 1 - 9

Reliability ....................................................................................................................... 1 - 9

Error Rate ....................................................................................................................... 1 - 10

Media Defects................................................................................................................. 1 - 10

CHAPTER 2

DEVICE CONFIGURATION ....................................................................... 2 - 1

2.1

Device Configuration ..................................................................................................... 2 - 1

2.2

System Configuration..................................................................................................... 2 - 3

2.2.1

ATA interface ................................................................................................................. 2 - 3

2.2.2

1 drive connection .......................................................................................................... 2 - 3

2.2.3

2 drives connection......................................................................................................... 2 - 4

CHAPTER 3

INSTALLATION CONDITIONS ................................................................. 3 - 1

3.1

Dimensions..................................................................................................................... 3 - 1

3.2

3.3

Mounting ........................................................................................................................ 3 - 3

Cable Connections.......................................................................................................... 3 - 7

3.3.1

Device connector ............................................................................................................ 3 - 7

3.3.2

Cable connector specifications ....................................................................................... 3 - 8

3.3.3

Device connection .......................................................................................................... 3 - 8

3.3.4

Power supply connector (CN1) ...................................................................................... 3 - 9

3.4

Jumper Settings .............................................................................................................. 3 - 9

C141-E056-02EN vii

3.4.1

Location of setting jumpers ............................................................................................ 3 - 9

3.4.2

Factory default setting .................................................................................................... 3 - 10

3.4.3

Jumper configuration...................................................................................................... 3 - 10

CHAPTER 4

THEORY OF DEVICE OPERATION ......................................................... 4 - 1

4.1

Outline............................................................................................................................ 4 - 1

4.2

Subassemblies ................................................................................................................ 4 - 1

4.2.1

Disk ................................................................................................................................ 4 - 1

4.2.2

Head ............................................................................................................................... 4 - 2

4.2.3

Spindle............................................................................................................................ 4 - 2

4.2.4

Actuator .......................................................................................................................... 4 - 2

4.2.5

Air filter .......................................................................................................................... 4 - 2

4.3

4.4

Circuit Configuration...................................................................................................... 4 - 3

Power-on Sequence ........................................................................................................ 4 - 5

4.5

Self-calibration ............................................................................................................... 4 - 7

4.5.1

Self-calibration contents ................................................................................................. 4 - 7

4.5.2

Execution timing of self-calibration ............................................................................... 4 - 8

4.5.3

Command processing during self-calibration ................................................................. 4 - 8

4.6

Read/write Circuit........................................................................................................... 4 - 9

4.6.1

Read/write preamplifier (PreAMP)................................................................................. 4 - 9

4.6.2

Write circuit.................................................................................................................... 4 - 9

4.6.3

Read circuit..................................................................................................................... 4 - 11

4.6.4

Time base generator circuit............................................................................................. 4 - 13

4.7

Servo Control ................................................................................................................. 4 - 14

4.7.1

Servo control circuit ....................................................................................................... 4 - 15

4.7.2

Data-surface servo format............................................................................................... 4 - 18

4.7.3

Servo frame format ......................................................................................................... 4 - 18

4.7.4

Actuator motor control ................................................................................................... 4 - 19

4.7.5

Spindle motor control ..................................................................................................... 4 - 20

CHAPTER 5

INTERFACE ................................................................................................... 5 - 1

5.1

Physical Interface ........................................................................................................... 5 - 2

5.1.1

Interface signals.............................................................................................................. 5 - 2

5.1.2

Signal assignment on the connector ............................................................................... 5 - 3

5.2

Logical Interface............................................................................................................. 5 - 6

5.2.1

I/O registers .................................................................................................................... 5 - 6 viii C141-E056-02EN

5.2.2

Command block registers ............................................................................................... 5 - 8

5.2.3

Control block registers ................................................................................................... 5 - 13

5.3

Host Commands ............................................................................................................. 5 - 13

5.3.1

Command code and parameters...................................................................................... 5 - 14

5.3.2

Command descriptions ................................................................................................... 5 - 16

5.3.3

Error posting................................................................................................................... 5 - 63

5.4

Command Protocol......................................................................................................... 5 - 64

5.4.1

Data transferring commands from device to host ........................................................... 5 - 64

5.4.2

Data transferring commands from host to device ........................................................... 5 - 66

5.4.3

Commands without data transfer .................................................................................... 5 - 68

5.4.4

Other commands............................................................................................................. 5 - 69

5.4.5

DMA data transfer commands........................................................................................ 5 - 69

5.5

Ultra DMA feature set .................................................................................................... 5 - 71

5.5.1

Overview ........................................................................................................................ 5 - 71

5.5.2

Phases of operation......................................................................................................... 5 - 72

5.5.3

Ultra DMA data in commands........................................................................................ 5 - 72

5.5.3.1 Initiating an Ultra DMA data in burst............................................................................. 5 - 72

5.5.3.2 The data in transfer ......................................................................................................... 5 - 73

5.5.3.3 Pausing an Ultra DMA data in burst............................................................................... 5 - 73

5.5.3.4 Terminating an Ultra DMA data in burst........................................................................ 5 - 74

5.5.4 Ultra DMA data out commands...................................................................................... 5 - 76

5.5.4.1 Initiating an Ultra DMA data out burst........................................................................... 5 - 76

5.5.4.2 The data out transfer ....................................................................................................... 5 - 77

5.5.4.3 Pausing an Ultra DMA data out burst............................................................................. 5 - 77

5.5.4.4 Terminating an Ultra DMA data out burst...................................................................... 5 - 78

5.5.5 Ultra DMA CRC rules .................................................................................................... 5 - 80

5.5.6 Series termination required for Ultra DMA .................................................................... 5 - 81

5.6 Timing ............................................................................................................................ 5 - 82

5.6.1 PIO data transfer ............................................................................................................. 5 - 82

5.6.2 Multiword data transfer .................................................................................................. 5 - 83

5.6.3 Ultra DMA data transfer ................................................................................................. 5 - 84

5.6.3.1 Initiating an Ultra DMA data in burst............................................................................. 5 - 84

5.6.3.2 Ultra DMA data burst timing requirements .................................................................... 5 - 85

5.6.3.3 Sustained Ultra DMA data in burst................................................................................. 5 - 87

5.6.3.4 Host pausing an Ultra DMA data in burst ...................................................................... 5 - 88

5.6.3.5 Device terminating an Ultra DMA data in burst ............................................................. 5 - 89

C141-E056-02EN ix

5.6.3.6 Host terminating an Ultra DMA data in burst................................................................. 5 - 90

5.6.3.7 Initiating an Ultra DMA data out burst........................................................................... 5 - 91

5.6.3.8 Sustained Ultra DMA data out burst............................................................................... 5 - 92

5.6.3.9 Device pausing an Ultra DMA data out burst................................................................. 5 - 93

5.6.3.10 Host terminating an Ultra DMA data out burst............................................................... 5 - 94

5.6.3.11 Device terminating an Ultra DMA data in burst ............................................................. 5 - 95

5.6.4 Power-on and reset ......................................................................................................... 5 - 96

CHAPTER 6

OPERATIONS ................................................................................................ 6 - 1

6.1 Device Response to the Reset......................................................................................... 6 - 1

6.1.1 Response to power-on .................................................................................................... 6 - 2

6.1.2 Response to hardware reset ............................................................................................ 6 - 3

6.1.3 Response to software reset.............................................................................................. 6 - 4

6.1.4 Response to diagnostic command .................................................................................. 6 - 5

6.2 Address Translation........................................................................................................ 6 - 6

6.2.1 Default parameters.......................................................................................................... 6 - 6

6.2.2 Logical address............................................................................................................... 6 - 7

6.3 Power Save ..................................................................................................................... 6 - 8

6.3.1 Power save mode............................................................................................................ 6 - 8

6.3.2 Power commands ........................................................................................................... 6 - 10

6.4 Defect Management........................................................................................................ 6 - 10

6.4.1 Spare area ....................................................................................................................... 6 - 11

6.4.2 Alternating defective sectors .......................................................................................... 6 - 11

6.5 Read-Ahead Cache ......................................................................................................... 6 - 14

6.5.1 Data buffer configuration ............................................................................................... 6 - 14

6.5.2 Caching operation........................................................................................................... 6 - 15

6.5.3 Usage of read segment.................................................................................................... 6 - 16

6.6 Write Cache .................................................................................................................... 6 - 22 x C141-E056-02EN

FIGURES

4.6

4.7

4.8

4.9

4.2

4.3

4.4

4.5

5.1

5.2

5.3

1.1

2.1

2.2

2.3

2.4

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

page

Current fluctuation (Typ.) when power is turned on....................................................... 1 - 7

Disk drive outerview ...................................................................................................... 2 - 1

Configuration of disk media heads ................................................................................. 2 - 2

1 drive system configuration .......................................................................................... 2 - 3

2 drives configuration..................................................................................................... 2 - 4

Dimensions..................................................................................................................... 3 - 2

Orientation...................................................................................................................... 3 - 3

Limitation of side-mounting........................................................................................... 3 - 4

Mounting frame structure ............................................................................................... 3 - 4

Surface temperature measurement points ....................................................................... 3 - 5

Service area .................................................................................................................... 3 - 6

Connector locations ........................................................................................................ 3 - 7

Cable connections........................................................................................................... 3 - 8

Power supply connector pins (CN1)............................................................................... 3 - 9

3.10

Jumper location .............................................................................................................. 3 - 9

3.11

Factory default setting .................................................................................................... 3 - 10

3.12

Jumper setting of master or slave device ........................................................................ 3 - 10

3.13

Jumper setting of Cable Select ....................................................................................... 3 - 11

3.14

Example (1) of Cable Select ........................................................................................... 3 - 11

3.15

Example (2) of Cable Select ........................................................................................... 3 - 11

4.1

Head structure................................................................................................................. 4 - 2

MPC30xxAH Block diagram ......................................................................................... 4 - 4

Power-on operation sequence ......................................................................................... 4 - 6

Read/write circuit block diagram.................................................................................... 4 - 10

Frequency characteristic of programmable filter ............................................................ 4 - 11

PR4 signal transfer ......................................................................................................... 4 - 12

Block diagram of servo control circuit ........................................................................... 4 - 15

Physical sector servo configuration on disk surface ....................................................... 4 - 16

Servo frame format ......................................................................................................... 4 - 18

Execution example of READ MULTIPLE command .................................................... 5 - 19

Read Sector(s) command protocol.................................................................................. 5 - 65

Protocol for command abort ........................................................................................... 5 - 66

C141-E056-02EN xi

5.4

5.5

5.6

5.7

WRITE SECTOR(S) command protocol........................................................................ 5 - 67

Protocol for the command execution without data transfer ............................................ 5 - 68

Normal DMA data transfer ............................................................................................. 5 - 70

Ultra DMA termination with pull-up or pull-down ........................................................ 5 - 81

5.8

5.9

PIO data transfer timing.................................................................................................. 5 - 82

Multiword DMA data transfer timing (mode 2) ............................................................. 5 - 83

5.10

Initiating an Ultra DMA data in burst............................................................................. 5 - 84

5.11

Sustained Ultra DMA data in burst................................................................................. 5 - 87

5.12

Host pausing an Ultra DMA data in burst ...................................................................... 5 - 88

5.13

Device terminating an Ultra DMA data in burst ............................................................. 5 - 89

5.14

Host terminating an Ultra DMA data in burst................................................................. 5 - 90

5.15

Initiating an Ultra DMA data out burst........................................................................... 5 - 91

5.16

Sustained Ultra DMA data out burst............................................................................... 5 - 92

5.17

Device pausing an Ultra DMA data out burst................................................................. 5 - 93

5.18

Host terminating an Ultra DMA data out burst............................................................... 5 - 94

5.19

Device terminating an Ultra DMA data out burst ........................................................... 5 - 95

6.4

6.5

6.6

6.7

5.20

Power-on Reset Timing .................................................................................................. 5 - 96

6.1 Response to power-on .................................................................................................... 6 - 2

6.2

6.3

Response to hardware reset ............................................................................................ 6 - 3

Response to software reset.............................................................................................. 6 - 4

Response to diagnostic command .................................................................................. 6 - 5

Address translation (example in CHS mode).................................................................. 6 - 7

Address translation (example in LBA mode) ................................................................. 6 - 8

Sector slip processing ..................................................................................................... 6 - 11

6.8

6.9

Track slip processing ...................................................................................................... 6 - 12

Automatic Alternate assignment..................................................................................... 6 - 13

6.10 Data buffer configuration ............................................................................................... 6 - 14 xii C141-E056-02EN

TABLES

1.1

1.2

1.3

1.4

1.5

1.6

3.1

3.2

4.1

4.2

4.3

5.1

5.2

5.3

5.4

5.5

5.6

5.7 page

Specifications ................................................................................................................. 1 - 4

Model names and product numbers................................................................................ 1 - 5

Current and power dissipation ........................................................................................ 1 - 6

Environmental specifications.......................................................................................... 1 - 8

Acoustic noise specification ........................................................................................... 1 - 8

Shock and vibration specification................................................................................... 1 - 9

Surface temperature measurement points and standard values ....................................... 3 - 5

Cable connector specifications ....................................................................................... 3 - 8

Self-calibration execution timechart ............................................................................... 4 - 8

Write precompensation algorithm .................................................................................. 4 - 9

Write clock frequency and transfer rate of each zone ..................................................... 4 - 14

Interface signals.............................................................................................................. 5 - 2

Signal assignment on the interface connector................................................................. 5 - 3

I/O registers .................................................................................................................... 5 - 7

Command code and parameters...................................................................................... 5 - 14

Information to be read by IDENTIFY DEVICE command ............................................ 5 - 30

Features register values and settable modes ................................................................... 5 - 34

Diagnostic code .............................................................................................................. 5 - 37

5.8 Features Register values (subcommands) and functions ................................................ 5 - 48

5.9 Format of device attribute value data.............................................................................. 5 - 50

5.10 Format of insurance failure threshold value data ............................................................ 5 - 51

5.11 Contents of security password ........................................................................................ 5 - 55

5.12 Contents of SECURITY SET PASSWORD data ........................................................... 5 - 60

5.13

Relationship between combination of Identifier and Security level, and operation of the lock function .................................................................................. 5 - 60

5.14 Command code and parameters...................................................................................... 5 - 63

5.15 Recommended series termination for Ultra DMA .......................................................... 5 - 81

5.16 Ultra DMA data burst timing requirements .................................................................... 5 - 85

6.1

Default parameters.......................................................................................................... 6 - 6

C141-E056-02EN xiii

This page is intentionally left blank.

CHAPTER 1 DEVICE OVERVIEW

1.1

Features

1.2

Device Specifications

1.3

Power Requirements

1.4

Environmental Specifications

1.5

Acoustic Noise

1.6

Shock and Vibration

1.7

Reliability

1.8

Error Rate

1.9

Media Defects

Overview and features are described in this chapter, and specifications and power requirement are described.

The MPC3045AH, MPC3065AH is a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is compact and reliable.

1.1

Features

1.1.1

Functions and performance

(1) Compact

The disk has 1, 2 or 3 disks of 95 mm (3.5 inches) diameter, and its height is 25.4 mm (1 inch).

(2) Large capacity

The disk drive can record up to 2,170 MB (formatted) on one disk using the 8/9 PRML recording method and 15 recording zone technology. The MPC3045AH and MPC3065AH have a formatted capacity of 4,551 MB and 6,510 MB respectively.

(3) High-speed Transfer rate

The disk drive has an internal data rate up to 19.18 MB/s. The disk drive supports an external data rate up to 16.7 MB/s or 33.3 MB/s (ultra DMA mode).

C141-E056-01EN 1 - 1

(4) Average positioning time

Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 9 ms (at read).

1.1.2

Adaptability

(1) Power save mode

The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor.

(2) Wide temperature range

The disk drive can be used over a wide temperature range (5°C to 55°C).

(3) Low noise and vibration

In Ready status, the noise of the disk drive is only about 3.9 bels (MPC3065AH, Typical

Sound Power per ISO7779 and ISO9296).

1.1.3

Interface

(1) Connection to interface

With the built-in ATA interface controller, the disk drive can be connected to an ATA interface of a personal computer.

(2) 256-KB data buffer

The disk drive uses a 512-KB data buffer to transfer data between the host and the disk media.

In combination with the read-ahead cache system described in item (3) and the write cache described in item (6), the buffer contributes to efficient I/O processing.

(3) Read-ahead cache system

After the execution of a disk read command, the disk drive automatically reads the subsequent data block and writes it to the data buffer (read ahead operation). This cache system enables fast data access. The next disk read command would normally cause another disk access.

But, if the read ahead data corresponds to the data requested by the next read command, the data in the buffer can be transferred instead.

(4) Master/slave

The disk drive can be connected to ATA interface as daisy chain configuration. Drive 0 is a master device, drive 1 is a slave device.

1 - 2 C141-E056-01EN

(5) Error correction and retry by ECC

If a recoverable error occurs, the disk drive itself attempts error recovery. The 24-byte ECC has improved buffer error correction for correctable data errors.

(6) Write cache

When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media.

This feature reduces the access time at writing.

C141-E056-01EN 1 - 3

1.2

Device Specifications

1.2.1

Specifications summary

Table 1.1 shows the specifications of the disk drive.

Table 1.1

Specifications

Formatted Capacity (*1)

Number of Heads

Number of Cylinders

(User + Alternate & SA)

Bytes per Sector

Recording Method

MPC3045AH

4551.96 MB

4

10,424 + 83

MPC3065AH

6510.55 MB

6

Track Density

Bit Density

Rotational Speed

Average Latency

512

8/9 PRML

11,000 TPI

162,754 BPI

7,200 rpm ± 0.5%

4.17 ms

Positioning time

• Minimum

• Average

• Maximum

Start/Stop time

• Start (0 rpm to Drive

Read)

• Stop (at Power Down)

Interface

2.0 ms typical

(Read) 9 ms typical, (Write) 10 ms typical

(Read) 18 ms typical, (Write) 19 ms typical

Typical: 8 sec., Maximum: 16 sec.

Typical: 20 sec.,Maximum: 30 sec.

ATA–3

(Maximum Cable length: 0.46 m)

Data Transfer Rate

• To/From Media

• To/From Host

12.65 to 19.18 MB/s

16.7 MB/s Max. (burst PIO mode 4, burst DMA mode

2),

33.3 MB/s Max. (burst ultra DMA mode 2)

512 KB Data buffer

Physical Dimensions

(Height

×

Width

×

Depth)

26.1 mm max. × 101.6 mm × 146.0 mm

(1.03” max. × 4.0” × 5.75”)

Weight 600 g

*1: Capacity under the LBA mode and the CHS mode.

Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows.

Model

MPC3045AH

MPC3065AH

Formatted Capacity No. of Cylinder No. of Heads No. of Sectors

4551.96

9,408 15 63

6510.55

13,456 15 63

1 - 4 C141-E056-02EN

1.2.2

Model and product number

Table 1.2 lists the model names and product numbers.

Model Name

MPC3045AH

MPC3065AH

Table 1.2

Model names and product numbers

Capacity

(user area)

4551.96

6510.55

Mounting

Screw

Order No.

No. 6-32UNC CA01742-B641

No. 6-32UNC CA01742-B661

1.3

(1)

Power Requirements

Input Voltage

+ 5 V ±5 %

+ 12 V ±8 %

(2) Ripple

+12 V +5 V

Maximum 200 mV (peak to peak) 100 mV (peak to peak)

Frequency DC to 1 MHz DC to 1 MHz

Others

C141-E056-01EN 1 - 5

(3) Current Requirements and Power Dissipation

Table 1.3 lists the current and power dissipation.

Mode of

Operation

Model

Spin up

Idle (Ready) (*3)

R/W (On Track) (*4)

Seek (Random) (*5)

Standby

Sleep

Table 1.3

Current and power dissipation

Typical RMS current (*1) [mA]

+12 V +5 V

All Models

1300

1500 peak

300

All Models

500

600 peak

380

Typical Power (*2) [watts]

All Models

18.1

300

510

4

4

430

430

150

150

5.50

5.75

8.27

0.8

0.8

*1 Current is typical rms except for spin up.

*2 Power requirements reflect nominal values for +12V and +5V power.

*3 Idle mode is in effect when the drive is not reading, writing, seeking, or executing any commands. A portion of the R/W circuitry is powered down, the spindle motor is up to speed and the Drive ready condition exists.

*4 R/W mode is defined as 50% read operations and 50% write operations on a single physical track.

*5 Seek mode is defined as continuous random seek operations with minimum controller delay.

1 - 6 C141-E056-01EN

(4) Current fluctuation (Typ.) when power is turned on

Note:

Maximum current is 1.5 A and is continuance is 1.5 seconds

Figure 1.1

Current fluctuation (Typ.) when power is turned on

(5) Power on/off sequence

The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abnormal. This prevents data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

C141-E056-01EN 1 - 7

1.4

Environmental Specifications

Table 1.4 lists the environmental specifications.

Table 1.4

Environmental specifications

Temperature

• Operating

• Non-operating

• Thermal Gradient

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

Altitude (relative to sea level)

• Operating

• Non-operating

5°C to 55°C (ambient)

5°C to 60°C (disk enclosure surface)

–40°C to 60°C

20°C/h or less

8% to 80%RH (Non-condensing)

5% to 85%RH (Non-condensing)

29°C

–60 to 3,000 m (–200 to 10,000 ft)

–60 to 12,000 m (–200 to 40,000 ft)

1.5

Acoustic Noise

Table 1.5 lists the acoustic noise specification.

Table 1.5

Acoustic noise specification

Sound Power per ISO 7779 and ISO9296

(Typical at 1m)

Model

Sound Pressure

(Typical at 1m)

Idle mode

(DRIVE READY)

Seek mode (Random)

Idle mode

(DRIVE READY)

Seek mode (Random)

MPC3045AH

MPC3065AH

3.9 bels

4.4 bels

34 dBA

40 dBA

1 - 8 C141-E056-01EN

1.6

Shock and Vibration

Table 1.6 lists the shock and vibration specification.

Table 1.6

Shock and vibration specification

Vibration (swept sine, one octave per minute)

• Operating

• Non-operating

Shock (half-sine pulse, 11 ms duration)

• Operating

• Non-operating

5 to 300 Hz, 0.5G-0-peak

(without non-recovered errors)

5 to 400 Hz, 4G-0-peak (no damage)

10G (without non-recovered errors)

75G (no damage)

1.7

(1)

Reliability

Mean time between failures (MTBF)

The mean time between failures (MTBF) is 500,000 H or more (operation: 24 hours/day, 7 days/week).

This does not include failures occurring during the first three months after installation.

MTBF is defined as follows:

MTBF=

Total operation time in all fields number of device failure in all fields

(H)

"Disk drive defects" refers to defects that involve repair, readjustment, or replacement. Disk drive defects do not include failures caused by external factors, such as damage caused by handling, inappropriate operating environments, defects in the power supply host system, or interface cable.

(2) Mean time to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance staff member.

(3) Service life

In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first. Refer to item (3) in Subsection 3.2 for the measurement point of the DE surface temperature.

C141-E056-01EN 1 - 9

(4) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment).

1.8

Error Rate

Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media.

(1) Unrecoverable read error

Read errors that cannot be recovered by maximum 126 times read retries without user's retry and ECC corrections shall occur no more than 10 times when reading data of 10

15 bits. Read retries are executed according to the disk drive's error recovery procedure, and include read retries accompanying head offset operations.

(2) Positioning error

Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in 10

7 seek operations.

1.9

Media Defects

Defective sectors are replaced with alternates when the disk is formatted prior to shipment from the factory (low level format). Thus, the host sees a defect-free device.

Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors.

Chapter 6 describes the low level format at shipping.

1 - 10 C141-E056-01EN

CHAPTER 2 DEVICE CONFIGURATION

2.1

Device Configuration

2.2

System Configuration

2.1

Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter.

Figure 2.1

Disk drive outerview

C141-E056-01EN 2 - 1

(1) Disk

The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 40,000 start/stop operations.

MPC3045AH: 2 disks

MPC3065AH: 3 disks

(2) Head

The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts.

Figure 2.2 illustrates the configuration of the disks and heads of each model. In the disk surface, servo information necessary for controlling positioning and read/write and user data are written. Numerals 0 to 5 indicate read/write heads.

MPC3045AH Model

Spindle

3

2

1

0

Actuator

MPC3065AH Model

Spindle

5

2

1

0

4

3

Actuator

Figure 2.2

Configuration of disk media heads

(3) Spindle motor

The disks are rotated by a direct drive Hall-less DC motor.

(4) Actuator

The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the tip of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head. If the power is not on or if the spindle motor is stopped, the head assembly stays in the specific CSS zone on the disk and is fixed by a mechanical lock.

2 - 2 C141-E056-01EN

(5) Air circulation system

The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the recirculation filter to maintain the cleanliness of the air in the disk enclosure.

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The high-speed microprocessor unit (MPU) achieves a high-performance AT controller.

2.2

System Configuration

2.2.1

ATA interface

Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 40-pin PC

AT interface connector and supports the PIO transfer till 16.7 MB/s (ATA-3, Mode 4), the

DMA transfer till 16.7 MB/s (ATA-3, Multiword mode 2), and the ultra DMA transfer till 33.3

MB/s (ATA-4, Ultra DMA mode 2).

2.2.2

1 drive connection

Host

HA

(Host adaptor)

Disk drive

AT bus

(Host interface)

ATA interface

Figure 2.3

1 drive system configuration

C141-E056-01EN 2 - 3

2.2.3

2 drives connection

Host

HA

(Host adaptor)

Disk drive #0

AT bus

(Host interface)

Disk drive #1

ATA interface

Note:

When the drive that is not conformed to ATA is connected to the disk drive is above configuration, the operation is not guaranteed.

Figure 2.4

2 drives configuration

IMPORTANT

HA (host adapter) consists of address decoder, driver, and receiver.

ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-3 interface.

At high speed data transfer (PIO mode 3, mode 4, DMA mode 2 or ultra DMA mode 2), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability. Thus, it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA-3 and ATA-4 standard, and the cable length between the HA and the disk drive should be as short as possible.

2 - 4 C141-E056-01EN

CHAPTER 3 INSTALLATION CONDITIONS

3.1

Dimensions

3.2

Mounting

3.3

Cable Connections

3.4

Jumper Settings

3.1

Dimensions

Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm.

C141-E056-01EN 3 - 1

3 - 2

Figure 3.1

Dimensions

C141-E056-01EN

3.2

(1)

Mounting

Orientation

Figure 3.2 illustrates the allowable orientations for the disk drive. The mounting angle can vary ±5° from the horizontal.

gravity

(a) Horizontal mounting (b) Vertical mounting –1 (c) Vertical mounting –2

Figure 3.2

Orientation

(2) Frame

The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground. These are electrically shorted.

Note:

Use No.6-32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3.4.

(3) Limitation of side-mounting

When the disk drive is mounted using the screw holes on both side of the disk drive, use two screw holes shown in Figure 3.3.

Do not use the center hole. For screw length, see Figure 3.4.

C141-E056-01EN 3 - 3

Use these screw holes

Do not use this screw holes

2

A

Frame of system cabinet

Figure 3.3

Limitation of side-mounting

Bottom surface mounting

DE

2.5

2.5

Frame of system cabinet

Side surface mounting

DE

PCA

B

2.5

4.5 or less

Details of A

Screw

5.0 or less

Details of B

Figure 3.4

Mounting frame structure

Screw

3 - 4 C141-E056-01EN

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the

DE surface temperature from exceeding 60°C.

Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling. To check the cooling efficiency, measure the surface temperatures of the DE.

Regardless of the ambient temperature, this surface temperature must meet the standards listed in Table 3.1. Figure 3.5 shows the temperature measurement point.

1

Figure 3.5

Surface temperature measurement points

Table 3.1

Surface temperature measurement points and standard values

No.

1 DE cover

Measurement point Temperature

60°C max

C141-E056-01EN 3 - 5

(5) Service area

Figure 3.6 shows how the drive must be accessed (service areas) during and after installation.

- Mounting screw hole

[Q side]

- Mounting screw hole

[R side]

- Mounting screw hole

[P side]

- Cable connection

- Mode setting switches

Figure 3.6

Service area

(6) External magnetic fields

Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

3 - 6 C141-E056-01EN

3.3

Cable Connections

3.3.1

Device connector

The disk drive has the connectors and terminals listed below for connecting external devices.

Figure 3.7 shows the locations of these connectors and terminals.

Power supply connector (CN1)

ATA interface connector (CN1)

Power supply connector (CN1)

Mode

Setting

Pins

ATA interface connector

Figure 3.7

Connector locations

C141-E056-01EN 3 - 7

3.3.2

Cable connector specifications

Table 3.2 lists the recommended specifications for the cable connectors.

ATA interface cable

(40-pin, CN1)

Power supply cable

(CN1)

Table 3.2

Cable connector specifications

Model Name

Cable socket

(closed-end type)

Cable socket

(through-end type)

Signal cable

Cable socket housing

Contact

Signal cable

FCN-707B040-AU/B

FCN-707B040-AU/O

445-248-40

1-480424-0

60617-4

AWG 18 to 24

Manufacturer

Fujitsu

Fujitsu

SPECTERS STRIP

AMP

AMP

Note :

The cable of twisted pairs and neighboring line separated individually is not allowed to use for the host interface cable. It is because that the location of signal lines in these cables is not fixed, and so the problem on the crosstalk among signal lines may occur.

3.3.3

Device connection

Figure 3.8 shows how to connect the devices.

Host system

ATA interface cable

Disk Drive #0

Power supply cable

DC power supply

3 - 8

Disk Drive #1

Figure 3.8

Cable connections

C141-E056-01EN

3.3.4

Power supply connector (CN1)

Figure 3.9 shows the pin assignment of the power supply connector (CN1).

C04

B01

B05

A01

1 2 3 4

1

2

3

4

+12VDC

+12V RETURN

+5V RETURN

+5VDC

(Viewed from cable side)

Figure 3.9

Power supply connector pins (CN1)

3.4

Jumper Settings

3.4.1

Location of setting jumpers

Figure 3.10 shows the location of the jumpers to select drive configuration and functions.

C01

B02

B06

A02

CN1

C01

Power supply connector

C04

B01/02

Mode setting

Connector pins

B05/06

A01/02

Interface

Connector

A39 A40 A39/40

Figure 3.10 Jumper location

C141-E056-01EN 3 - 9

3.4.2

Factory default setting

Figure 3.11 shows the default setting position at the factory. (Master device setting)

C01

C04

B02 06

A02 A40

B01

A01

05

Figure 3.11 Factory default setting

3.4.3

Jumper configuration

(1) Device type

Master device (device #0) or slave device (device #1) is selected.

A39

B02 06

B02 06

B01 05

(a) Master device

B01 05

(b) Slave device

Figure 3.12 Jumper setting of master or slave device

(2) Cable Select (CSEL)

In Cable Select mode, the device can be configured either master device or slave device. For use of Cable Select function, Unique interface cable is needed.

3 - 10 C141-E056-01EN

B02 06

B01 05

CSEL connected to the interface

Cable selection can be done by the special interface cable.

Figure 3.13 Jumper setting of Cable Select

Figures 3.14 and 3.15 show examples of cable selection using unique interface cables.

By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level. The device is identified as a master device. At this time, the CSEL of the slave device does not have a conductor. Thus, since the slave device is not connected to the CSEL conductor, the CSEL is set to high level.

The device is identified as a slave device.

GND

Host system

CSEL conductor

Master device

Figure 3.14 Example (1) of Cable Select

Open

Slave device

GND

Host system

CSEL conductor

Open

Slave device Master device

Figure 3.15 Example (2) of Cable Select

C141-E056-01EN 3 - 11

(3) Special setting 1 (SP1)

The number of cylinders reported by the IDENTIFY DEVICE command is selected.

(a) Default mode

2 4 6 2 4 6 2 4 6

1 3 5

Master Device

Model

MPC3045AH

MPC3065AH

1 3 5

Slave Device

No. of cylinders

9,408

13,456

No. of heads

15

15

1 3 5

Cable Select

No. of sectors

63

63

(b) Special mode

2 4 6 2 4 6 2 4 6

1 3 5

Master Device

Model

MPC3045AH

MPC3065AH

1 3 5

Slave Device

No. of cylinders

4,092

4,092

No. of heads

16

16

1 3 5

Cable Select

No. of sectors

63

63

3 - 12 C141-E056-01EN

CHAPTER 4 THEORY OF DEVICE OPERATION

4.1

Outline

4.2

Subassemblies

4.3

Circuit Configuration

4.4

Power-on sequence

4.5

Self-calibration

4.6

Read/write Circuit

4.7

Servo Control

This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

4.1

Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method.

4.2

Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle, actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.

The PCA contains the control circuits for the disk drive. The disk drive has one PCA. For details, see Sections 4.3.

4.2.1

Disk

The DE contains the disks with an outer diameter of 95 mm. The MPC3045AH has 2 disks.

MPC3065AH has 3 disks.

The head contacts the disk each time the disk rotation stops; the life of the disk is 40,000 contacts or more.

Servo data is recorded on each cylinder (total 54). Servo data written at factory is read out by the read/write head. For servo data, see Section 4.7.

C141-E056-01EN 4 - 1

4.2.2

Head

Figure 4.1 shows the read/write head structures. The MPC3045AH has 4 read/write heads, and MPC3065AH has 6. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed.

MPC3045AH Model

Spindle

3

2

1

0

Actuator

MPC3065AH Model

Spindle

5

2

1

0

4

3

Actuator

Figure 4.1

Head structure

4.2.3

Spindle

The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 7,200 rpm

±0.5%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting. After that, the rotational speed is kept with detecting a servo information.

4.2.4

Actuator

The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the head carriage along the inner or outer edge of the disk. The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read/write head.

4.2.5

Air filter

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk.

4 - 2 C141-E056-01EN

4.3

Circuit Configuration

Figure 4.2 shows the disk drive circuit configuration.

(1) Read/write circuit

The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC).

The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

The RDC is the read demodulation circuit using the partial response class 4 (PR4), and contains the Viterbi detector, programmable filter, adaptable transversal filter, times base generator, and data separator circuits. The RDC also contains the 8/9 group coded recording

(GCR) encoder and decoder and servo demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by 2 closed-loop servo using the servo information recorded on the data surface. The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil motor.

(3) Spindle motor driver circuit

The circuit measures the interval of a PHASE signal generated by counter-electromotive voltage of a motor, or servo mark at the MPU and controls the motor speed comparing target speed.

(4) Controller circuit

Major functions are listed below.

Data buffer management

ATA interface control and data transfer control

Sector format control

Defect management

ECC control

Error recovery and self-diagnosis

C141-E056-01EN 4 - 3

4 - 4

Figure 4.2

MPC30xxAH Block diagram

C141-E056-01EN

4.4

Power-on Sequence

Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below.

a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to the ATA bus.

c) After confirming that the spindle motor has reached rated speed, the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM. This unlocks the heads which are parked at the inner circumference of the disks.

d) The disk drive positions the heads onto the SA area and reads out the system information.

e) The disk drive executes self-seek-calibration. This collects data for VCM torque and mechanical external forces applied to the actuator, and updates the calibrating value.

f) The drive becomes ready. The host can issue commands.

C141-E056-01EN 4 - 5

Power on Start a)

Self-diagnosis 1

• MPU bus test

• Inner register

write/read test

• Work RAM write/read

test

The spindle motor starts.

b) Self-diagnosis 2

• Data buffer write/read

test c) Confirming spindle motor speed

Release heads from actuator lock d)

Initial on-track and read out of system information e) Execute self-calibration f) Drive ready state

(command waiting state)

End

Figure 4.3

Power-on operation sequence

4 - 6 C141-E056-01EN

4.5

Self-calibration

The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations.

4.5.1

Self-calibration contents

(1) Sensing and compensating for external forces

The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.

To execute stable fast seek operations, external forces are occasionally sensed.

The firmware of the drive measures and stores the force (value of the actuator motor drive current) that balances the torque for stopping head stably. This includes the current offset in the power amplifier circuit and DAC system.

The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control.

To compensate torque varying by the cylinder, the disk is divided into 14 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration. The measured values are stored in the

SA cylinder. In the self-calibration, the compensating value is updated using the value in the

SA cylinder.

(2) Compensating open loop gain

Torque constant value of the VCM has a dispersion for each drive, and varies depending on the cylinder that the head is positioned. To realize the high speed seek operation, the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder. The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio.

For compensating, the direction current value to the power amplifier is multiplied by the compensation value. By this compensation, loop gain becomes constant value and the stable servo control is realized.

To compensate torque constant value change depending on cylinder, whole cylinders from most inner to most outer cylinder are divided into 14 partitions at calibration in the factory, and the compensation data is measured for representative cylinder of each partition. This measured value is stored in the SA area. The compensation value at self-calibration is calculated using the value in the SA area.

C141-E056-01EN 4 - 7

4.5.2

Execution timing of self-calibration

Self-calibration is executed when:

The power is turned on.

The disk drive receives the RECALIBRATE command from the host.

The self-calibration execution timechart of the disk drive specifies self-calibration.

The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. The timechart is shown in Table 4.1. After power-on, self-calibration is performed about every 30 minutes.

5

6

3

4

.

.

7

.

9

1

2

Table 4.1

Self-calibration execution timechart

Time elapsed

At power-on

About 30 minutes

About 30 minutes

About 30 minutes

About 30 minutes

About 30 minutes

Time elapsed (accumulated)

Initial calibration

About 30 minutes

About 60 minutes

About 90 minutes

About 120 minutes

About 150 minutes

Every about 30 minutes

4.5.3

Command processing during self-calibration

If the disk drive receives a command execution request from the host while executing selfcalibration according to the timechart, the disk drive terminates self-calibration and starts executing the command precedingly. In other words, if a disk read or write service is necessary, the disk drive positions the head to the track requested by the host, reads or writes data, and restarts calibration.

This enables the host to execute the command without waiting for a long time, even when the disk drive is performing self-calibration. The command execution wait time is about maximum 100 ms.

4 - 8 C141-E056-01EN

4.6

Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit.

4.6.1

Read/write preamplifier (PreAMP)

One PreAMP is mounted on the FPC. The PreAMP consists of an 6-channel read preamplifier and a write current switch and senses a write error. Each channel is connected to each data head. The head IC switches the heads by the serial port (SDEN, SCLK, SDATA). The IC generates a write error sense signal (WUS) when a write error occurs due to head short-circuit or head disconnection.

4.6.2

Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC with synchronizing with the write clock. The NRZ write data is converted from 8-bit data to 9-bit data by the encoder circuit then sent to the

PreAMP, and the data is written onto the media.

(1) 8/9 GCR

The disk drive converts data using the 8/9 (0, 4, 4) group coded recording (GCR) algorithm.

This code format is 0 to 4 code bit "0"s are placed between "1"s.

(2) Write precompensation

Write precompensation compensates, during a write process, for write non-linearity generated at reading. Table 4.2 shows the write precompensation algorithm.

Table 4.2

Write precompensation algorithm

Bit n – 1

0

1

Bit n

1

1

Bit n + 1

1

0

Compensation

Bit n

None

Late

1 1 0 Late

Late: Bit is time shifted (delayed) from its nominal time position towards the bit n+1 time position.

C141-E056-01EN 4 - 9

4 - 10

Figure 4.4

Read/write circuit block diagram

C141-E056-01EN

4.6.3

Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 8/9 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

(2) Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in read channel by an instruction of the serial data signal from MPU (M1). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

Figure 4.5 shows the frequency characteristic sample of the programmable filter.

Figure 4.5

Frequency characteristic of programmable filter

(3) Adaptive equalizer circuit

This circuit is 3-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the partial response class 4 (PR4) waveform.

C141-E056-01EN 4 - 11

4 - 12

Figure 4.6

PR4 signal transfer

C141-E056-01EN

(4) Viterbi detection circuit

The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

(5) Data separator circuit

The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer.

(6) 8/9 GCR decoder

This circuit converts the 9-bit read data into the 8-bit NRZ data.

4.6.4

Time base generator circuit

The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 15 zones to set the data transfer rate. Table 4.3

describes the data transfer rate and recording density (BPI) of each zone.

C141-E056-01EN 4 - 13

Zone

Cylinder

Transfer rate

[MB/s]

Table 4.3

Write clock frequency and transfer rate of each zone

0

0 to

760

1

761 to

1520

2

1521 to

2280

3

2281 to

3040

4

3041 to

3800

5

3801 to

4530

6

4531 to

5165

7

5166 to

5790

19.18

19.18

19.18

19.18

19.18

19.18

18.54

17.91

Zone

Cylinder

Transfer rate

[MB/s]

8

5791 to

6775

9

6776 to

7105

10

7106 to

7815

11

7816 to

8495

12

8496 to

9045

13

9046 to

9590

14

9591 to

10423

16.86

16.51

15.73

14.96

14.33

13.70

12.65

The MPU transfers the data transfer rate setup data (SDATA/SCLK) to the RDC that includes the time base generator circuit to change the data transfer rate.

4.7

Servo Control

The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.

4 - 14 C141-E056-01EN

4.7.1

Servo control circuit

Figure 4.7 is the block diagram of the servo control circuit. The following describes the functions of the blocks:

Head

(2)

Servo burst capture

(3)

ADC

Position Sense

MPU

(1)

DSP unit

(4)

DAC

SVC

(5)

P.

Amp.

VCM current

CSR

VCM

(6)

Spindle motor control

(7)

Driver

Spindle motor

CSR: Current Sense Resistor

VCM: Voice Coil Motor

Figure 4.7

Block diagram of servo control circuit

(1) Microprocessor unit (MPU)

The MPU includes DSP unit, etc., and the MPU starts the spindle motor, moves the heads to the reference cylinders, seeks the specified cylinder, and executes calibration according to the internal operations of the MPU.

The major internal operations are listed below.

a. Spindle motor start

Starts the spindle motor and accelerates it to normal speed when power is applied.

b. Move head to reference cylinder

Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).

C141-E056-01EN 4 - 15

c. Seek to specified cylinder

Drives the VCM to position the head to the specified cylinder.

d. Calibration

Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value.

Servo frame

(54 servo frames revolution)

4 - 16

Figure 4.8

Physical sector servo configuration on disk surface

C141-E056-01EN

(2) Servo burst capture circuit

The four servo signals can be synchronously detected by the STROB signal, full-wave rectified integrated.

(3) A/D converter (ADC)

The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit.

(4) D/A converter (DAC)

The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.

(5) Power amplifier

The power amplifier feeds currents, corresponding to the DAC output signal voltage to the

VCM.

(6) Spindle motor control circuit

The spindle motor control circuit controls the sensor-less spindle motor. This circuit detects number of revolution of the motor by the interrupt generated periodically, compares with the target revolution speed, then flows the current into the motor coil according to the differentiation (aberration).

(7) Driver circuit

The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor.

(8) VCM current sense resistor (CSR)

This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back.

C141-E056-01EN 4 - 17

4.7.2

Data-surface servo format

Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to

(3) in Figure 4.8 are described below.

(1) Inner guard band

The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

(2) Data area

This area is used as the user data area SA area.

(3) Outer guard band

This area is located at outer position of the user data area, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

4.7.3

Servo frame format

As the servo information, the drive uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction.

The servo frame consists of 5 blocks; write/read recovery, servo mark, gray code, servo A to

D and PAD. Figure 4.9 shows the servo frame format.

4 - 18

Write/read recovery

Servo mark

Gray code

Servo

A

Servo

B

Servo

C

Servo

D

PAD

2.76

µ s 0.54

µ s 3.06

µ s 1.74

µ s 1.80

µ s 1.80

µ s 1.80

µ s 0.54

µ s

Figure 4.9

Servo frame format

C141-E056-01EN

(1) Write/read recovery

This area is used to absorb the write/read transient and to stabilize the AGC.

(2) Servo mark

This area generates a timing for demodulating the gray code and position-demodulating the servo A to D by detecting the servo mark.

(3) Gray code (including index bit)

This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit.

(4) Servo A, servo B, servo C, servo D

This area is used as position signals between tracks, and the IDD control at on-track so that servo A level equals to servo B level.

(5) PAD

This area is used as a gap between servo and data.

4.7.4

Actuator motor control

The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive current.

The servo control of the actuator includes the operation to move the head to the reference cylinder, the seek operation to move the head to the target cylinder to read or write data, and the track-following operation to position the head onto the target track.

(1) Operation to move the head to the reference cylinder

The MPU moves the head to the reference cylinder when the power is turned. The reference cylinder is in the data area.

When power is applied the heads are moved from the inner circumference shunt zone to the normal servo data zone in the following sequence: a) Micro current is fed to the VCM to press the head against the inner circumference.

b) A current is fed to the VCM to move the head toward the outer circumference.

c) When the servo mark is detected the head is moved slowly toward the outer circumference at a constant speed.

C141-E056-01EN 4 - 19

d) If the head is stopped at the reference cylinder from there. Track following control starts.

(2) Seek operation

Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read or instruction is issued, the MPU seeks the desired track.

The MPU feeds the VCM current via the D/A converter and power amplifier to move the head. The MPU calculates the difference (speed error) between the specified target position and the current position for each sampling timing during head moving. The MPU then feeds the VCM drive current by setting the calculated result into the D/A converter. The calculation is digitally executed by the firmware. When the head arrives at the target cylinder, the track is followed.

(3) Track following operation

Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed, the MPU does track following control. To position the head at the center of a track, the DSP drives the VCM by feeding micro current. For each sampling time, the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data. The filtering includes servo compensation. These are digitally controlled by the firmware.

4.7.5

Spindle motor control

Hall-less three-phase eight-pole motor is used for the spindle motor, and the 3-phase full/halfwave analog current control circuit is used as the spindle motor driver (called SVC hereafter).

The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence: a) After the power is turned on, the MPU sends a signal to the SVC to charge the change pump capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC to the motor start mode. Then, a current (approx. 1.3 A) flows into the spindle motor.

c) The SVC generates a phase switching signal by itself, and changes the phase of the current flowed in the motor in the order of (V-phase to U-phase), (W-phase to U-phase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after that, repeating this order).

d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection.

4 - 20 C141-E056-01EN

e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode.

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates. The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 5,400 rpm. When the rotational speed reaches 7,200 rpm, the SVC enters the stable rotation mode.

(3) Stable rotation mode

The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal from the SVC. The MPU takes a difference between the current time and a time for one revolution at 7,200 rpm that the MPU already recognized. Then, the MPU keeps the rotational speed to 7,200 rpm by charging or discharging the charge pump for the different time. For example, when the actual rotational speed is 7,400 rpm, the time for one revolution is 8.108

ms. And, the time for one revolution at 7,200 rpm is 8.333 ms. Therefore, the MPU discharges the charge pump for 0.225 ms

×

k (k: constant value). This makes the flowed current into the motor lower and the rotational speed down. When the actual rotational speed is later than 7,200 rpm, the MPU charges the pump the other way. This control

(charging/discharging) is performed every 1/6 revolution.

C141-E056-01EN 4 - 21

This page is intentionally left blank.

CHAPTER 5 INTERFACE

5.1

Physical Interface

5.2

Logical Interface

5.3

Host Commands

5.4

Command Protocol

5.5

Ultra DMA feature set

5.6

Timing

C141-E056-01EN 5 - 1

5.1

Physical Interface

5.1.1

Interface signals

Table 5.1 shows the interface signals.

Table 5.1

Interface signals

Description Host

Cable select

Chip select 0

Chip select 1

Data bus bit 0

Data bus bit 1

Data bus bit 2

Data bus bit 3

Data bus bit 4

Data bus bit 5

Data bus bit 6

Data bus bit 7

Data bus bit 8

Data bus bit 9

Data bus bit 10

Data bus bit 11

Data bus bit 12

Data bus bit 13

Data bus bit 14

Data bus bit 15

Device active or slave present

Device address bit 0

Device address bit 1

Device address bit 2

DMA acknowledge

DMA request

Interrupt request

I/O read

DMA ready during Ultra DMA data in bursts

Data strobe during Ultra DMA data out bursts

I/O ready

DMA ready during Ultra DMA data out bursts

Data strobe during Ultra DMA data in bursts

I/O write

Stop during Ultra DMA data bursts

Passed diagnostics

Reset

Dir see note

↔ see note see note

Dev

Note See signal descriptions

DD5

DD6

DD7

DD8

DD9

DD10

DD11

DD12

DD13

DD14

DD15

DASP–

DA0

DA1

DA2

DMACK–

DMARQ

Acrorym

CSEL

CS0–

CS1–

DD0

DD1

DD2

DD3

DD4

INTRQ

DIOR–

HDMARDY–

HSTROBE

IORDY

DDMARDY–

DSTROBE

DIOW–

STOP

PDIAG–

RESET–

5 - 2 C141-E056-01EN

5.1.2

Signal assignment on the connector

Table 5.2 shows the signal assignment on the interface connector.

Pin No.

25

27

29

31

17

19

21

23

33

35

37

39

9

11

13

15

5

7

1

3

Table 5.2

Signal assignment on the interface connector

Signal

RESET–

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

GND

DMARQ

DIOW–, STOP

DIOR–, HDMARDY–, HSTROBE

IORDY, DDMARDY–,

DSTROBE

DMACK–

INTRQ

DA1

DA0

CS0–

DASP–

Pin No.

26

28

30

32

18

20

22

24

34

36

38

40

10

12

14

16

6

8

2

4

GND

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

(KEY)

GND

GND

GND

CSEL

GND reserved

PDIAG–

DA2

CS1–

GND

Signal

[signal]

RESET–

DATA 0-15

DIOW–, STOP

[I/O] [Description]

I Reset signal from the host. This signal is low active and is asserted for a minimum of 25

µ s during power on.

I/O Sixteen-bit bi-directional data bus between the host and the device. These signals are used for data transfer

I DIOW– is the strobe signal asserted by the host to write device registers or the data port.

DIOW– shall be negated by the host prior to initiation of an Ultra

DMA burst. STOP shall be negated by the host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during an Ultra DMA burst signals the termination of the Ultra

DMA burst.

C141-E056-01EN 5 - 3

5 - 4

DIOR–

HDMARDY–

HSTROBE

INTRQ

CS0–

CS1–

DA 0-2

KEY

[signal]

PIDAG–

DASP–

[I/O] [Description]

I

I DIOR– is the strobe signal asserted by the host to read device registers or the data port.

HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts.

The host may negate HDMARDY- to pause an Ultra DMA data in burst.

I HSTROBE is the data out strobe signal from the host for an Ultra

DMA data out burst. Both the rising and falling edge of

HSTROBE latch the data from DATA 0-15 into the device. The host may stop generating HSTROBE edges to pause an Ultra

DMA data out burst.

O Interrupt signal to the host.

This signal is negated in the following cases:

– assertion of RESET– signal

– Reset by SRST of the Device Control register

– Write to the command register by the host

– Read of the status register by the host

– Completion of sector data transfer

(without reading the Status register)

When the device is not selected or interrupt is disabled, the

INTRQ

Signal shall be in a high impedance state.

I

I

I Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers.

Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

Binary decoded address signals asserted by the host to access task file registers.

Key pin for prevention of erroneous connector insertion –

I/O This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration. This signal indicates that the slave device has been completed self diagnostics.

This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This is a time-multiplexed signal that indicates that the device is active and a slave device is present.

This signal is pulled up to +5 V through 10 k

resistor at each device.

C141-E056-01EN

[signal]

IORDY

DDMARDY–

DSTROBE

CSEL

DMACK–

DMARQ

GND

[I/O] [Description]

O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request.

O DDMARDY– is a flow control signal for Ultra DMA data out bursts.

This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts. The device may negate DDMARDY– to pause an Ultra DMA data out burst.

O DSTROBE is the data in strobe signal from the device for an Ultra

DMA data in burst. Both the rising and falling edge of

DSTROBE latch the data from DATA 0-15 into the host. The device may stop generating DSTROBE edges to pause an Ultra

DMA data in burst.

I

I

This signal to configure the device as a master or a slave device.

When CSEL signal is grounded, the IDD is a master device.

When CSEL signal is open, the IDD is a slave device.

This signal is pulled up with 240 k

resistor.

The host system asserts this signal as a response that the host system receive data or to indicate that data is valid.

O This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system

(at reading) or from the host system (at writing).

The direction of data transfer is controlled by the IOR- and IOWsignals. In other word, the device negates the DMARQ signal after the host system asserts the DMACK– signal. When there is another data to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCW16–, CS0– and

CS1- signals are not asserted. The DMA data transfer is a 16-bit data transfer.

– Grounded

Note:

"I" indicates input signal from the host to the device.

"O" indicates output signal from the device to the host.

"I/O" indicates common output or bi-directional signal between the host and the device.

C141-E056-01EN 5 - 5

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinderhead-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the

Cylinder High, Cylinder Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of

LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the INITIALIZE

DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.)

×

(Number of head) + (Head No.))

×

(Number of sector/track)]

+ (Sector No.) – 1

5.2.1

I/O registers

Communication between the host system and the device is done through input-output (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0–, CS1–, and DA0 to DA2 from the host system. Table 5.3. shows the coding address and the function of I/O registers.

5 - 6 C141-E056-01EN

CS0– CS1– DA2

1

1

1

1

1

1

Command block registers

1 0 0 0

0

0

0

0

0

0

0

0

0

1

1

1

0

Control block registers

0

0

1

1 1

1

1

1

X

1

1

0

0

1

1

X

0

1

1

1

1

DA1

Table 5.3

I/O registers

DA0

I/O registers

Read operation Write operation

0

1

0

1

0

1

0

1

X

0

1

Data

Error Register

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

(Invalid)

Alternate Status

Data

Features

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Command

(Invalid)

Device Control

Host I/O address

X'1F0'

X'1F1'

X'1F2'

X'1F3'

X'1F4'

X'1F5'

X'1F6'

X'1F7'

X'3F6'

X'3F7'

Notes:

1.

The Data register for read or write operation can be accessed by 16 bit data bus

(DATA0 to DATA15).

2.

The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

3.

When reading the Drive Address register, bit 7 is high-impedance state.

4.

The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and

Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.

C141-E056-01EN 5 - 7

5.2.2

Command block registers

(1) Data register (X'1F0')

The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode.

(2) Error register (X'1F1')

The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the EXECUTIVE

DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7

ICRC

X: Unused

Bit 6

UNC

Bit 5

X

Bit 4

IDNF

Bit 3

X

Bit 2

ABRT

Bit 1

TK0NF

Bit 0

AMNF

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Interface CRC error (ICRC). This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers.

Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error has been encountered.

Unused

ID Not Found (IDNF). This bit indicates an error except for, uncorrectable error and SB not found, and Aborted Command.

Unused

Aborted Command (ABRT). This bit indicates that the requested command was aborted due to a device status error (e.g. Not Ready, Write Fault) or the command code was invalid.

Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution.

Address Mark Not Found. This bit indicates that an SB not found error has been encountered.

5 - 8 C141-E056-01EN

[Diagnostic code]

X'01': No Error Detected.

X'02': HDC Register Compare Error

X'03': Data Buffer Compare Error.

X'05': ROM Sum Check Error.

X'06': MPU Internal RAM Compare Error

X'80': Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X'01' to X'05').

However, when the host system selects the slave device, the diagnostic code of the slave device is posted.

(3) Features register (X'1F1')

The Features register provides specific feature to a command. For instance, it is used with SET

FEATURES command to enable or disable caching.

(4) Sector Count register (X'1F2')

The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device. When the value in this register is

X'00', the sector count is 256.

When this register indicates X'00' at the completion of the command execution, this indicates that the command is completed successfully. If the command is not completed successfully, this register indicates the number of sectors to be transferred to complete the request from the host system. That is, this register indicates the number of remaining sectors that the data has not been transferred due to the error.

The contents of this register has other definition for the following commands; INITIALIZE

DEVICE PARAMETERS, SET FEATURES, IDLE, STANDBY and SET MULTIPLE

MODE.

(5) Sector Number register (X'1F3')

The contents of this register indicates the starting sector number for the subsequent command.

The sector number should be between X'01' and [the number of sectors per track defined by

INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

C141-E056-02EN 5 - 9

(6) Cylinder Low register (X'1F4')

The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access.

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indicates LBA bits 15 to 8.

(7) Cylinder High register (X'1F5')

The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

(8) Device/Head register (X'1F6')

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines "the number of heads minus 1".

Bit 7

X

Bit 6

L

Bit 5

X

Bit 4

DEV

Bit 3

HS3

Bit 2

HS2

Bit 1

HS1

Bit 0

HS0

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Unused

L. 0 for CHS mode and 1 for LBA mode.

Unused

DEV bit. 0 for the master device and 1 for the slave device.

HS3 CHS mode head address 3 (2

3

). LBA bit 27.

HS2 CHS mode head address 3 (2

2

). LBA bit 26.

HS1 CHS mode head address 3 (2

1

). LBA bit 25.

HS0 CHS mode head address 3 (2

0

). LBA bit 24.

5 - 10 C141-E056-01EN

(9) Status register (X'1F7')

The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt). Any pending interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6

BSY DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

Busy (BSY) bit. This bit is set whenever the Command register is accessed.

Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested

(DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers. If the host system reads any command block register when BSY bit is 1, the contents of the Status register are posted. This bit is set by the device under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the Device Control register, the BSY bit is set. the BSY bit is cleared, when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

(b) Within 400 ns from the host system starts writing to the Command register.

(c) Within 5

µ s following transfer of 512 bytes data during execution of the

READ SECTOR(S), WRITE SECTOR(S), FORMAT TRACK, or WRITE

BUFFER command.

Within 5

µ s following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command.

Device Ready (DRDY) bit. This bit indicates that the device is capable to respond to a command.

The IDD checks its status when it receives a command. If an error is detected

(not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is cleared until the rotational speed of the spindle motor reaches the steady speed.

The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected.

If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is completed.

C141-E056-01EN 5 - 11

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device.

Always 0.

Always 0.

Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error.

(10) Command register (X'1F7')

The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the

Command register is written.

5 - 12 C141-E056-01EN

5.2.3

Control block registers

(1) Alternate Status register (X'3F6')

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply

Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7

BSY

Bit 6

DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

(2) Device Control register (X'3F6')

The Device Control register contains device interrupt and software reset.

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2 Bit 1

SRST nIEN

Bit 0

0

- Bit 2:

- Bit 1:

SRST is the host software reset bit. When this bit is set, the device is held reset state. When two device are daisy chained on the interface, setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this bit is 0 and the device is selected, an interruption (INTRQ signal) can be enabled through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ signal is in the high-impedance state.

5.3

Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed.

C141-E056-01EN 5 - 13

5.3.1

Command code and parameters

Table 5.4 lists the supported commands, command code and the registers that needed parameters are written.

Table 5.4

Command code and parameters (1 of 2)

Command name

READ SECTOR(S)

READ MULTIPLE

READ DMA

READ VERIFY SECTOR(S)

WRITE MULTIPLE

WRITE DMA

WRITE VERIFY

Command code (Bit) Parameters used

7 6 5 4 3 2 1 0 FR SC SN CY DH

0 0 1 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 0 N Y Y Y Y

1 1 0 0 1 0 0 R N Y Y Y Y

0 1 0 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 1 N Y Y Y Y

1 1 0 0 1 0 1 R N Y Y Y Y

0 0 1 1 1 1 0 0 N Y Y Y Y

WRITE SECTOR(S)

RECALIBRATE

0 0 1 1 0 0 0 R N Y Y Y Y

0 0 0 1 X X X X N N N N D

SEEK 0 1 1 1 X X X X N N Y Y Y

INITIALIZE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 1 N Y N N Y

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

SET MULTIPLE MODE

EXECUTE DEVICE DIAGNOSTIC

FORMAT TRACK

READ LONG

WRITE LONG

READ BUFFER

WRITE BUFFER

IDLE

IDLE IMMEDIATE

STANDBY

1

1

1

1

1

0

1

1

0

0

0

1

1

1

0

1

1

0

0

1

0

0

0

0

N

N

N

N

N

N

N

N

N

N

N

N

D

D

1 1 1 0 1 1 1 1 Y N* N N D

1 1 0 0 0 1 1 0 N Y N N D

D*

0 1 0 1 0 0 0 0 N N Y* Y Y

0 0 1 0 0 0 1 R N Y Y Y Y

0 0 1 1 0 0 1 R N Y Y Y Y

1 1 1 0 0 1 0 0 N N N N D

1

1

1

1

1 1 1 0 1 0 0 0 N N N N D

1

1

0

1

0

1

1

0

0

0

1

0

1

1

1

1

N Y N N D

0

1

0

1

0

1

0

1

1

0

1

0

0

0

0

0

1

0

1

0

0

0

1

1

1

1

0

0

N

N

N

Y

N

N

N

N

D

D

5 - 14 C141-E056-01EN

STANDBY IMMEDIATE

SLEEP

SMART

Command name

FLUSH CACHE

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

Table 5.4

Command code and parameters (2 of 2)

CHECK POWER MODE

1

1

1

1

Command code (Bit) Parameters used

7 6 5 4 3 2 1 0 FR SC SN CY DH

0

1

0

1

0

1

0

1

1

0

1

0

0

0

1

0

1

0

0

1

0

0

0

1

0

0

1

0

N

N

N

N

N

N

N

N

D

D

1

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

N N N N D

1 0 1 1 0 0 0 0 Y Y Y Y D

1 1 1 0 0 1 1 1 N N N N D

1 1 1 1 0 1 1 0 N N N N D

1 1 1 1 0 0 1 1 N N N N D

1 1 1 1 0 1 0 0 N N N N D

1 1 1 1 0 1 0 1 N N N N D

1 1 1 1 0 0 0 1 N N N N D

1 1 1 1 0 0 1 1 N N N N D

Notes:

FR : Features Register CY: Cylinder Registers

SC : Sector Count Register DH : Drive/Head Register

SN : Sector Number Register

R: Retry at error

1 = Without retry 0 = with retry

Y: Necessary to set parameters

Y*: Necessary to set parameters under the LBA mode.

N: Necessary to set parameters (The parameter is ignored if it is set.)

N*: May set parameters

D: The device parameter is valid, and the head parameter is ignored.

D*: The command is addressed to the master device, but both the master device and the slave device execute it.

X: Do not care

C141-E056-01EN 5 - 15

5.3.2

Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection.

Example: READ SECTOR(S)

Bit

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

7

0

×

6 5 4 3 2 1 0

0

L

1 0 0 0 0 0

×

DV Head No. / LBA [MSB]

Start cylinder address [MSB] / LBA

Start cylinder address [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count xx

1F7

1F6

At command completion (I/O registers contents to be read)

Bit

1F5

H

H

H

(ST)

(DH)

(CH)

1F4

H

(CL)

7

×

6 5 4 3 2

End cylinder address [LSB] / LBA

End sector No.

1

/ LBA [LSB]

0

L

Status information

×

DV End Head No. / LBA [MSB]

End cylinder address [MSB] / LBA

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

X‘00’

Error information

CM: Command register

DH: Device/Head register

CH: Cylinder High register

CL: Cylinder Low register

SN: Sector Number register

SC: Sector Count register

FR: Features register

ST: Status register

ER: Error register

L: LBA (logical block address) setting bit

DV: Device address. bit x, xx: Do not care (no necessary to set)

5 - 16 C141-E056-02EN

Note:

1.

When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the

CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB

(most significant bit) and bits of the SN register are the LSB (least significant bit).

2.

At error occurrence, the SC register indicates the remaining sector count of data transfer.

3.

In the table indicating I/O registers contents in this subsection, bit indication is omitted.

(1) READ SECTOR(S) (X'20' or X'21')

This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be specified to 256 sectors in maximum. To specify 256 sectors reading, '00' is specified. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the specified track, the device reads the target sector.

The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition.

Upon the completion of the command execution, command block registers contain the cylinder, head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the last sector read.

If an error occurs in a sector, the read operation is terminated at the sector where the error occurred.

Command block registers contain the cylinder, the head, and the sector addresses of the sector

(in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

0

×

0

L

1 0 0 0 0 R

×

DV Start head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

C141-E056-01EN 5 - 17

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

×

L

Status information

×

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X'C4')

This command operates similarly to the READ SECTOR(S) command. The device does not generate an interrupt (assertion of the INTRQ signal) on each every sector. An interrupt is generated after the transfer of a block of sectors for which the number is specified by the SET

MULTIPLE MODE command.

The implementation of the READ MULTIPLE command is identical to that of the READ

SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE

MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.

The number of sectors (block count) to be transferred without interruption is specified by the

SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command.

When the READ MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector

Count register is less than the defined block count (the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors

[block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of ("number of sectors"/"block count").

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ

MULTIPLE command with an ABORTED COMMAND error.

If an error occurs, reading sector is stopped at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred, and remaining number of sectors that had not transferred after the sector where the error occurred.

An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block.

5 - 18 C141-E056-01EN

Figure 5.1 shows an example of the execution of the READ MULTIPLE command.

Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block)

READ MULTIPLE command specifies;

Number of requested sectors = 9 (Sector Count register = 9)

Number of sectors in incomplete block = remainder of 9/4 =1

BSY

DRDY

Parameter

Write

~

INTRQ

DRQ

Sector transferred

Command Issue

Status read

1 2 3 4

Block

Status read

5 6 7 8

Block

Status read

9

Partial block

Figure 5.1

Execution example of READ MULTIPLE command

1F7

H

(CM)

1F6

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

H

At command issuance (I/O registers setting contents)

(DH)

(CH)

(CL)

(SN)

(SC)

(FR)

1

×

1

L

0 0 0 1 0 0

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00

H

(*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.

C141-E056-01EN 5 - 19

(3) READ DMA (X'C8' or X'C9')

This command operates similarly to the READ SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

The device controls the assertion or negation timing of the DMARQ signal.

The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No., and first sector No. fields. At command completion, the logical block address of the last sector and remaining number of sectors of which data was not transferred, like in the CHS mode, are set.

The host system can select the DMA transfer mode by using the SET FEATURES command.

1) Multiword DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command

2) Ultra DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

(CH)

(CL)

(SN)

(SC)

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1

×

1

L

0 0 1 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

5 - 20 C141-E056-01EN

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X'40' or X'41')

This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt. Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector number of the last sector verified.

If an error occurs, the verify operation is terminated at the sector where the error occurred. The command block registers contain the cylinder, the head, and the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred.

The Sector Count register indicates the number of sectors that have not been verified.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

0

×

1

L

0 0 0 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

C141-E056-01EN 5 - 21

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X'30' or X'31')

This command writes data of sectors from the address specified in the Device/Head, Cylinder

High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified to 256 sectors in maximum. Data transfer begins at the sector specified in the Sector Number register. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the specified track, the device writes the target sector.

The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.

If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

0

×

0

L

1 1 0 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

5 - 22 C141-E056-01EN

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(6) WRITE MULTIPLE (X'C5')

This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE

MODE command.

The implementation of the WRITE MULTIPLE command is identical to that of the WRITE

SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE

MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE command operation, the DRQ bit of the Status register is required to set only at the start of the data block, not on each sector.

The number of sectors (block count) to be transferred without interruption is specified by the

SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command.

When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector

Count register is less than the defined block count the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors

[block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of ("number of sectors"/"block count").

If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE

MULTIPLE command with an ABORTED COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred. Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block. If an error occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block.

C141-E056-01EN 5 - 23

The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

L

0 0 0 1 0 1

×

DV Start head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

×

L

Status information

×

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00

H

/ LBA [LSB]

Error information

Note:

When the command terminates due to error, only the DV bit and the error information field are valid.

(7) WRITE DMA (X'CA' or X'CB')

This command operates similarly to the WRITE SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

The device controls the assertion or negation timing of the DMARQ signal.

The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the WRITE SECTOR(S) command.

A host system can be select the following transfer mode using the SET FEATURES command.

5 - 24 C141-E056-01EN

1) Multiword DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command

2) Ultra DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

L

0 0 1 0 1 R

×

DV Start head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(8) WRITE VERIFY (X'3C')

This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

0

×

0

L

1 1 1 1 0 0

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

C141-E056-01EN 5 - 25

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

×

L

Status information

×

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(9) RECALIBRATE (X'1x', x: X'0' to X'F')

This command performs the calibration. Upon receipt of this command, the device sets BSY bit of the Status register and performs a calibration. When the device completes the calibration, the device updates the Status register, clears the BSY bit, and generates an interrupt.

This command can be issued in the LBA mode.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

0

×

0

×

0

×

1

DV x x xx x

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx x

5 - 26 C141-E056-01EN

(10) SEEK (X'7x', x : X'0' to X'F')

This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt.

The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.

In the LBA mode, this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

0

×

1

L

1

×

1

DV x x x x

Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

xx

/ LBA [LSB]

xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

H

(DH)

(CH)

(CL)

(SN)

(SC)

(ER)

×

L

Status information

×

DV Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

xx

/ LBA [LSB]

Error information

C141-E056-01EN 5 - 27

(11) INITIALIZE DEVICE PARAMETERS (X'91')

The host system can set the number of sectors per track and the maximum head number

(maximum head number is "number of heads minus 1") per cylinder with this command.

Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.

When the SC register is specified to X'00', an ABORTED COMMAND error is posted. Other than X'00' is specified, this command terminates normally.

The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting.

In LBA mode

The device ignores the L bit specification and operates with the CHS mode specification. An accessible area of this command within head moving in the LBA mode is always within a default area. It is recommended that the host system refers the addressable user sectors (total number of sectors) in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

0

×

0

×

1

DV

0 0 0

Max. head No.

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Number of sectors/track xx

1

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV Max. head No.

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error Information

(12) IDENTIFY DEVICE (X'EC')

The host system issues the IDENTIFY DEVICE command to read parameter information (512 bytes) from the device. Upon receipt of this command, the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer. The device then sets the

DRQ bit of the Status register, and generates an interrupt. After that, the host system reads the information out of the sector buffer. Table 5.5 shows the arrangements and values of the parameter words and the meaning in the buffer.

5 - 28 C141-E056-01EN

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

0

DV

1 1 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

C141-E056-01EN 5 - 29

Table 5.5

Information to be read by IDENTIFY DEVICE command (1 of 3)

48

49

50

51

52

53

54

55

56

57-58

59

60-61

2

3

4

5

6

7-9

10-19

20-21

22

23-26

27-46

47

Word

0

1

69-79

80

81

82

83

84-87

88

89-127

128

129-255

62

63

64

65

66

67

68

X‘0000’

X‘2B00’

X‘0000’

X‘0200’

X‘0000’

X‘0007’

(Variable)

(Variable)

(Variable)

(Variable)

*8

X‘0087A8C0’

X‘00C20790’

X‘0000’

X‘xx07’

X‘0003’

X‘0078’

X‘0078’

X‘0078’

X‘0078’

Value

X‘045A’

X‘24C0’

X‘3490’

X‘0000’

X‘000F’

X‘0000’

General Configuration *1

Number of cylinders

Reserved

Number of Heads

Retired

X‘0000’

X‘003F’

Retired

Number of sectors per track

X‘000000000000’ Retired

– Serial number (ASCII code) *2

X‘00000000’

X‘0004’

X‘8010’

Description

MPC3045AH: X‘24C0’

MPC3065AH: X‘3490’

Retired

Number of ECC bytes transferred at READ LONG or WRITE LONG command

Firmware revision (ASCII code) *3

Model number (ASCII code) *4

Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command

X‘00’

X‘000E’

X‘0000’

X‘B86B’

X‘4000’

X‘00’

X‘xx07’

X‘00’

X‘xx’

X‘00’

Reserved

Capabilities *5

Reserved

PIO data transfer mode *6

Retired

Enable/disable setting of words 54-58, 64-70 and 88 *7

Number of current Cylinders

Number of current Head

Number of current sectors per track

Total number of current sectors

Transfer sector count currently set by READ/WRITE MULTIPLE command

Total number of user addressable sectors (LBA mode only) MPC3045AH: X‘0087A8C0’

Retired

Multiword DMA transfer mode *9

Advance PIO transfer mode support status *10

MPC3065AH: X‘00C20790’

Minimum multiword DMA transfer cycle time per word : 120 [ns]

Manufacturer's recommended DMA transfer cycle time : 120 [ns]

Minimum PIO transfer cycle time without flow control : 120 [ns]

Minimum PIO transfer cycle time with IORDY flow control : 120 [ns]

Reserved

Major version number *11

Minor version number (not reported)

Support of command sets *12

Support of command sets (fixed)

Reserved

Ultra DMA modes *13

Reserved

Security Status

Reserved

5 - 30 C141-E056-02EN

Table 5.5

Information to be read by IDENTIFY DEVICE command (2 of 3)

*1 Word 0: General configuration

Bit 15: 0 = ATA device

Bit 14-8: Vendor specific

Bit 7: 1 = Removable media device

Bit 6: 1 = not removable controller and/or device

Bit 5-1: Vendor specific

Bit 0: Reserved

*2 Word 10-19: Serial number; ASCII code (20 characters, right-justified)

*3 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)

0

0

0

1

0

0

*4 Word 27-46: Model number;

ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20')

One of three model numbers;

MPC3045AH, MPC3065AH

*5 Word 49: Capabilities

Bit 15-14: Reserved

Bit 13: Standby timer value 1 = Standby timer values as specified in ATA standard are

supported

Bit 12: Reserved

Bit 11: IORDY support 1=Supported

Bit 10: IORDY inhibition 0=Disable inhibition

Bit 9: LBA support 1=Supported

Bit 8: DMA support 1=Supported

Bit 7-0: Vendor specific

*6 Word 51: PIO data transfer mode

Bit 15-8: PIO data transfer mode X'02'=PIO mode 2

Bit 7-0: Vendor specific

*7 Word 53: Enable/disable setting of word 54-58 ,64-70 and 88

Bit 15-3: Reserved

Bit 2: Enable/disable setting of word 88 1=Enable

Bit 1: Enable/disable setting of word 64-70 1=Enable

Bit 0: Enable/disable setting of word 54-58 1=Enable

*8 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command

Bit 15-9: Reserved

Bit 8: Multiple sector transfer 1=Enable

Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without interrupt supports 2, 4, 8 and 16 sectors.

*9 Word 63: Multiword DMA transfer mode

Bit 15-8: Currently used multiword DMA transfer mode

Bit 7-0: Supportable multiword DMA transfer mode

Bit 2=1 Mode 2

Bit 1=1 Mode 1

Bit 0=1 Mode 0

C141-E056-01EN 5 - 31

Table 5.5

Information to be read by IDENTIFY DEVICE command (3 of 3)

*10 Word 64: Advance PIO transfer mode support status

Bit 15-8: Reserved

Bit 7-0: Advance PIO transfer mode

Bit 1=1 Mode 4

Bit 0=1 Mode 3

*11 Word 80: Major version number

Bit 15-4: Reserved

Bit 3: ATA-3 Supported=1

Bit 2: ATA-2 Supported=1

Bit 1: ATA-1 Supported=1

Bit 0: Undefined

*12 Word 82: Support of command sets

Bit 15: Identify Device DMA command supported = 1

Bit 14: NOP command supported = 0

Bit 13: Read Buffer command supported = 1

Bit 12: Write Buffer command supported = 1

Bit 11: Write Buffer command supported (Old Spec.) = 1

Bit 10: Host Protected Area feature command supported = 0

Bit 9: Device Reset command supported = 0

Bit 8: SERVICE Interrupt supported = 0

Bit 7: Release Interrupt supported = 0

Bit 6: Lock Ahead supported = 1

Bit 5: Write-cache supported = 1

Bit 4: Packet command feature set supported = 0

Bit 3: Power Management feature set supported=1

Bit 2: Removable feature set supported=0

Bit 1: Security feature set supported=1

Bit 0: SMART feature set supported=1

*13 Word 88: Ultra DMA modes

Bit 15-11: Reserved

Bit 10-8: Currently used Ultra DMA transfer modes

Bit 7-3: Reserved

Bit 2-0: Supportable Ultra DMA transfer mode

Bit 2=1 Mode 2

Bit 1=1 Mode 1

Bit 0=1 Mode 0

5 - 32 C141-E056-01EN

(13) IDENTIFY DEVICE DMA (X'EE')

When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

0

DV

1 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

0

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(14) SET FEATURES (X'EF')

The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. For the transfer mode

(Feature register = 03), detail setting can be done using the Sector Count register.

Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register. Then, the device clears the BSY bit, and generates an interrupt.

If the value in the Features register is not supported or it is invalid, the device posts an

ABORTED COMMAND error.

Table 5.6 lists the available values and operational modes that may be set in the Features register.

C141-E056-01EN 5 - 33

Table 5.6

Features register values and settable modes

Features Register

X‘02’

X‘03’

Drive operation mode

Enables the write cache function.

Specifies the transfer mode. Supports PIO mode 4, single word DMA mode

2, and multiword DMA mode regardless of Sector Count register contents.

Disables read cache function.

X‘55’

X‘66’

X‘82’

X‘AA’

X‘BB’

X‘CC’

Disables the reverting to power-on default settings after software reset.

Disables the write cache function.

Enables the read cache function.

Specifies the transfer of 4-byte ECC for READ LONG and WRITE LONG commands.

Enables the reverting to power-on default settings after software reset.

At power-on or after hardware reset, the default mode is the same as that is set with a value greater than X‘AA’ (except for write cache). If X‘66’ is specified, it allows the setting value greater than X‘AA’ which may have been modified to a new value since power-on, to remain the same even after software reset.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

0

DV

1 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx or transfer mode

[See Table 5.6]

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

1

5 - 34 C141-E056-01EN

The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value.

However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting.

The IDD supports following values in the Sector Count register value. If other value than below is specified, an ABORTED COMMAND error is posted.

PIO default transfer mode

PIO flow control transfer mode X

Multiword DMA transfer mode X

Ultra DMA transfer mode X

Disable IORDY

00000 000 (X‘00’)

00001 000 (X‘08’: Mode 0)

00001 001 (X‘09’: Mode 1)

00001 010 (X‘0A’: Mode 2)

00001 011 (X‘0B’: Mode 3)

00001 100 (X‘0C’: Mode 4)

00100 000 (X‘20’: Mode 0)

00100 001 (X‘21’: Mode 1)

00100 010 (X‘22’: Mode 2)

01000 000 (X‘40’: Mode 0)

01000 001 (X‘41’: Mode 1)

01000 010 (X‘42’: Mode 2)

00000 001 (X‘01’: transfer mode not changed)

(15) SET MULTIPLE MODE (X'C6')

This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command.

The number of sectors per block is written into the Sector Count register. The IDD supports 2,

4, 8 and 16 (sectors) as the block counts.

Upon receipt of this command, the device sets the BSY bit of the Status register and checks the contents of the Sector Count register. If the contents of the Sector Count register is valid and is a supported block count, the value is stored for all subsequent READ MULTIPLE and

WRITE MULTIPLE commands. Execution of these commands is then enabled. If the value of the Sector Count register is not a supported block count, an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled.

If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued, the READ MULTIPLE and WRITE MULTIPLE commands are disabled.

When the SET MULTIPLE MODE command operation is completed, the device clears the

BSY bit and generates an interrupt.

C141-E056-02EN 5 - 35

5 - 36

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

0

×

0

DV

0 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Sector count/block xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx

Sector count/block

Error information xx

0

After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.

Regarding software reset, the mode set prior to software reset is retained after software reset.

The parameters for the multiple commands which are posted to the host system when the

IDENTIFY DEVICE command is issued are listed below. See Subsection 5.3.2 for the

IDENTIFY DEVICE command.

Word 47 = 8010:

Word 59 = 0000:

= 01xx:

Maximum number of sectors that can be transferred per interrupt by the

READ MULTIPLE and WRITE MULTIPLE commands are 16 (fixed).

The READ MULTIPLE and WRITE MULTIPLE commands are disabled.

The READ MULTIPLE and WRITE MULTIPLE commands are enabled. "xx" indicates the current setting for number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE

MULTIPLE commands.

e.g. 0110 = Block count of 16 has been set by the SET MULTIPLE

MODE command.

C141-E056-01EN

(16) EXECUTE DEVICE DIAGNOSTIC (X'90')

This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis.

If device 1 is present:

Both devices shall execute self-diagnosis.

The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal.

If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall append X‘80’ to its own diagnostic status.

The device 0 clears the BSY bit of the Status register and generates an interrupt. (The device 1 does not generate an interrupt.)

A diagnostic status of the device 0 is read by the host system. When a diagnostic failure of the device 1 is detected, the host system can read a status of the device 1 by setting the

DV bit (selecting the device 1).

When device 1 is not present:

The device 0 posts only the results of its own self-diagnosis.

The device 0 clears the BSY bit of the Status register, and generates an interrupt.

Table 5.7 lists the diagnostic code written in the Error register which is 8-bit code.

If the device 1 fails the self-diagnosis, the device 0 "ORs" X‘80’ with its own status and sets that code to the Error register.

Code

X‘01’

X‘02’

X‘03’

X‘05’

X‘06’

X‘8x’

Table 5.7

Diagnostic code

Result of diagnostic

No error detected.

HDC Register compare error

Data buffer compare error

ROM sum check error

MPU internal RAM compare error

Failure of device 1

C141-E056-02EN 5 - 37

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

0

×

0

×

1

DV

0 0 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

At command completion (I/O registers contents to be read)

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information

00

00

00

01

01

H

H

Diagnostic code

0

(17) FORMAT TRACK (X'50')

Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512byte format parameter transfer from the host system. After completion of transfer, the device clears the DRQ bits, sets the BSY bit. However the device does not perform format operation, but the drive clears the BYS bit and generates an interrupt soon. When the command execution completes, the device clears the BSY bit and generates an interrupt.

The drive supports this command for keep the compatibility with previous drive only.

(18) READ LONG (X'22' or X'23')

This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.

The READ LONG command supports only single sector operation.

5 - 38 C141-E056-01EN

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

(CH)

(CL)

(SN)

(SC)

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

0

×

0

L

1 0

×

DV

0 0 1 R

Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

Number of sectors to be transferred

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, this register indicates 01.

(19) WRITE LONG (X'32' or X'33')

This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.

This command is operated under the following conditions:

The command is issued in a sequence of the READ LONG or WRITE LONG (to the same address) command issuance. (WRITE LONG command can be continuously issued after the READ LONG command.)

If above condition is not satisfied, the command operation is not guaranteed.

C141-E056-01EN 5 - 39

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

(CH)

(CL)

(SN)

(SC)

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

0

×

0

L

1 1

×

DV

0 0 1 R

Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

Number of sectors to be transferred

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, this register indicates 01.

(20) READ BUFFER (X'E4')

The host system can read the current contents of the sector buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up the sector buffer for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

1

×

1

×

1

×

0

DV

0 1 xx

0 xx xx xx xx xx

0

5 - 40 C141-E056-01EN

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(21) WRITE BUFFER (X'E8')

The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the

BSY bit when the device is ready to receive the data. After that, 512 bytes of data is transferred from the host and the device writes the data to the sector buffer, then generates an interrupt.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

1

×

1

×

1

×

0

DV

1 0 xx

0 xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx

0

C141-E056-01EN 5 - 41

(22) IDLE (X'97' or X'E3')

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.

If the contents of the Sector Count register is other than 0, the automatic power-down function is enabled and the timer starts countdown immediately. When the timer reaches the specified time, the device enters the standby mode.

If the contents of the Sector Count register is 0, the automatic power-down function is disabled.

Enabling the automatic power-down function means that the device automatically enters the standby mode after a certain period of time. When the device enters the idle mode, the timer starts countdown. If any command is not issued while the timer is counting down, the device automatically enters the standby mode. If any command is issued while the timer is counting down, the timer is initialized and the command is executed. The timer restarts countdown after completion of the command execution.

The period of timer count is set depending on the value of the Sector Count register as shown below.

0

1 to 240 [X'01' to X'F0']

241 to 251 [X'F1' to X'FB']

252

253

Sector Count register value

[X'00']

[X'FC']

[X'FD']

254 to 255 [X'FE' to X'FF']

Point of timer

Disable of timer

(Value

×

5) seconds

(Value – 240)

×

30 minutes

21 minutes

8 hours

21 minutes 15 seconds

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

× ×

X'97' or X'E3'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Period of timer xx

5 - 42 C141-E056-01EN

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(23) IDLE IMMEDIATE (X'95' or X'E1')

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

× ×

X'95' or X'E1'

×

DV xx xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx

C141-E056-01EN 5 - 43

(24) STANDBY (X'96' or X'E2')

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.

If the contents of the Sector Count register is other than 0, the automatic power-down function is enabled and the timer starts countdown when the device returns to idle mode.

When the timer value reaches 0 (passed a specified time), the device enters the standby mode.

If the contents of the Sector Count register is 0, the automatic power-down function is disabled.

Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as the READ SECTOR(s) command is received, the device processes the command after driving the spindle motor.

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'96' or X'E2'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Period of timer xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(25) STANDBY IMMEDIATE (X'94' or X'E0')

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the automatic power-down sequence.

5 - 44 C141-E056-01EN

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'94' or X'E0'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx

(26) SLEEP (X'99' or X'E6')

This command is the only way to make the device enter the sleep mode.

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the sleep mode.

In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. All

I/O register outputs are in high-impedance state.

The only way to release the device from sleep mode is to execute a software or hardware reset.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

× ×

X'99' or X'E6'

×

DV xx xx xx xx xx xx

C141-E056-01EN 5 - 45

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(27) CHECK POWER MODE (X'98' or X'E5')

The host checks the power mode of the device with this command.

The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers.

The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt.

Power save mode

• During moving to standby mode

• Standby mode

• During returning from the standby mode

• Idle mode

• Active mode

Sector Count register

X'00'

X'80'

X'FF'

5 - 46 C141-E056-01EN

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'98' or X'E5'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx

X'00' or X'FF'

Error information xx

(28) SMART (X'B0)

This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted

Command error is posted.

It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command. If the keys are set incorrectly, the Aborted Command error is posted.

When the failure prediction feature is disabled, the Aborted Command error is posted in response to subcommands other than SMART Enable Operations (FR register = D8h).

When the failure prediction feature is enabled, the device collects or updates several items to forecast failures. In the following sections, note that the values of items collected or updated by the device to forecast failures are referred to as attribute values.

C141-E056-01EN 5 - 47

Table 5.8 Features Register values (subcommands) and functions

Features Resister

X’D0’

X’D1’

X’D2’

X’D3’

X’D8’

X’D9’

X’DA’

Function

SMART Read Attribute Values:

A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512byte attribute value information to the host.

* For information about the format of the attribute value information, see Table 5.9.

SMART Read Attribute Thresholds:

This subcommand is used to transfer 512-byte insurance failure threshold value data to the host.

* For information about the format of the insurance failure threshold value data, see Table 5.10.

SMART Enable-Disable Attribute AutoSave:

This subcommand is used to enable (SC register !!XX!! 00h) or disable (SC register = 00h) the setting of the automatic saving feature for the device attribute data. The setting is maintained every time the device is turned off and then on.

When the automatic saving feature is enabled, the attribute values are saved after

15 minutes passed since the previous saving of the attribute values. However, if the failure prediction feature is disabled, the attribute values are not automatically saved.

When the device receives this subcommand, it asserts the BSY bit, enables or disables the automatic saving feature, then clears the BSY bit.

SMART Save Attribute Values:

When the device receives this subcommand, it asserts the BSY bit, saves device attribute value data, then clears the BSY bit.

SMART Enable Operations:

This subcommand enables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, enables the failure prediction feature, then clears the BSY bit.

SMART Disable Operations:

This subcommand disables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, disables the failure prediction feature, then clears the BSY bit.

SMART Return Status:

When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values. If there is an attribute value exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers. If there are no attribute values exceeding the thresholds, 4Fh and C2h are loaded into the CL and CH registers. After the settings for the CL and CH registers have been determined, the device clears the BSY bit

The host must regularly issue the SMART Read Attribute Values subcommand (FR register =

D0h), SMART Save Attribute Values subcommand (FR register = D3h), or SMART Return

Status subcommand (FR register = DAh) to save the device attribute value data on a medium.

5 - 48 C141-E056-01EN

Alternative, the device must issue the SMART Enable-Disable Attribute AutoSave subcommand (FR register = D2h) to use a feature which regularly save the device attribute value data to a medium.

The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers.

If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it life . In this case, the host recommends that the user quickly backs up the data.

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

0

×

1

×

1

DV

0 0 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Key (C2h)

Key (4Fh) xx xx

Subcommand

1F7

H

(ST)

1F6

H

At command completion (I-O registers setting contents)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Key-failure prediction status (C2h-2Ch)

Key-failure prediction status (4Fh-F4h) xx xx

Error information

0

C141-E056-01EN 5 - 49

The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register =

D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Thresholds subcommand (FR register = D1h).

06

07 to

0C

0D

0E to

169

16A to

16F

170

171

Byte

00

01

02

03

04

05

172 to

181

182 to

1FE

1FF

Table 5.9 Format of device attribute value data

Attribute 1

Item

Data format version number

Attribute ID

Status flag

Current attribute value

Attribute value for worst case so far

Raw attribute value

Attribute 2 to attribute 30

Reserved

Reserved

(The format of each attribute value is the same as that of bytes 02 to 0D.)

Failure prediction capability flag

Reserved

Vendor specific

Check sum

5 - 50 C141-E056-01EN

Byte

00

01

02

03

04

Table 5.10 Format of insurance failure threshold value data

Attribute 1

Item

Data format version number

Attribute ID

Insurance failure threshold

Threshold 1

(Threshold of attribute 1)

Reserved to to

17B

17C to

1FE

1FF

0D

0E to

169

16A

Threshold 2 to threshold 30

(The format of each threshold value is the same as that of bytes 02 to 0D.)

Reserved

Unique to vendor

Check sum

Data format version number

The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated.

C141-E056-01EN 5 - 51

5 - 52

Attribute ID

The attribute ID is defined as follows:

Attribute ID Attribute name

7

8

9

4

5

2

3

0

1

(Indicates unused attribute data.)

Read error rate

Throughput performance

Spin up time

Number of times the spindle motor is activated

Number of alternative sectors

Seek error rate

Seek time performance

Power-on time

10

12

Number of retries made to activate the spindle motor

Number of power-on-power-off times

13 to 198 (Reserved)

199 Ultra ATA CRC Error Rate

200 Write error rate

201 to 255 (Unique to vendor)

Status flag

Bit 0: If this bit is 1, the attribute is covered by the insurance of the drive when the attribute value exceeds the threshold.

Bit 1: If this bit is 1 (0), the attribute value is updated only by online test (offline test).

Bit 2: If this bit is 1, the attribute value shows the performance.

Bit 3: If this bit is 1, the attribute value shows the error rate.

Bit 4: If this bit is 1, the attribute value shows the generation times.

Bit 5: If this bit is 1, the attribute value is collected and scewed even if the failure prediction feature is disabled.

Bits 6 to 15: Reserved bits

C141-E056-02EN

Current attribute value

The current attribute value is the normalized raw attribute data. The value varies between

01h and 64h. The closer the value gets to 01h, the higher the possibility of a failure. The device compares the attribute values with thresholds. When the attribute values are larger than the thresholds, the device is operating normally.

Attribute value for the worst case so far

This is the worst attribute value among the attribute values collected to date. This value indicates the state nearest to a failure so far.

Raw attribute value

Raw attributes data is retained.

Failure prediction capability flag

Bit 0: The attribute value data is saved to a medium before the device enters power saving mode.

Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation.

Bits 2 to 15: Reserved bits

Check sum

Two's complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning.

Insurance failure threshold

The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure.

C141-E056-02EN 5 - 53

(29) FLUSH CACHE (X ‘E7’)

This command is use by the host to request the device to flush the write cache. If the write cache is to be flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. The device should use all error recovery methods available to ensure the data is written successfully. The flushing of write cache may take several seconds to complete depending upon the amount of data to be flushed and the success of the operation.

NOTE - This command may take longer than 30 s to complete.

If the command is not supported, the device shall set the ABRT bit to one. An unrecoverable error encountered during execution of writing data results in the termination of the command and the error is reported. And the test write cache data is removed.

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'E7'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

5 - 54 C141-E056-02EN

(30) SECURITY DISABLE PASSWORD (F6h)

This command invalidates the user password already set and releases the lock function.

The host transfers the 512-byte data shown in Table 1.1 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password.

If the user password or master password transferred from the host does not match, the Aborted

Command error is returned.

Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted

Command error.

(The section about the SECURITY FREEZE LOCK command describes LOCKED MODE and FROZEN MODE.)

Table 5.11 Contents of security password

Word Contents

0 Control word

Bit 0: Identifier

0 = Compares the user passwords.

1 = Compares the master passwords.

1 to 16

Bits 1 to 15: Reserved

Password (32 bytes)

17 to 255 Reserved

C141-E056-01EN 5 - 55

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

(31) SECURITY ERASE PREPARE (F3h)

The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY

ERASE PREPARE command and then the SECURITY ERASE UNIT command. The

SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command.

Issuing this command during FROZEN MODE returns the Aborted Command error.

5 - 56 C141-E056-01EN

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 0 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

1

(32) SECURITY ERASE UNIT (F4h)

This command erases all user data. This command also invalidates the user password and releases the lock function.

The host transfers the 512-byte data shown in Table 1.1 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set. The device erases user data, invalidates the user password, and releases the lock function if the passwords are the same.

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password.

If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned.

Issuing this command while in FROZEN MODE returns the Aborted Command error.

C141-E056-01EN 5 - 57

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 1 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

(33) SECURITY FREEZE LOCK (F5h)

This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN

MODE.

SECURITY SET PASSWORD

SECURITY UNLOCK

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

FROZEN MODE is canceled when the power is turned off. If this command is reissued in

FROZEN MODE, the command is completed and FROZEN MODE remains unchanged.

Issuing this command during LOCKED MODE returns the Aborted Command error.

The following medium access commands return the Aborted Command error when the device is in LOCKED MODE:

5 - 58 C141-E056-01EN

READ DMA

READ LONG

WRITE DMA

WRITE LONG

READ MULTIPLE

WRITE MULTIPLE

READ SECTORS

WRITE SECTORS

WRITE VETIFY

SECURITY DISABLE PASSWORD

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 1 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I-O registers setting contents)

× ×

Status information

×

DV xx xx xx xx

Error information xx

1

(34) SECURITY SET PASSWORD (F1h)

This command enables a user password or master password to be set.

The host transfers the 512-byte data shown in Table 1.2 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and

Security level bit in the transferred data. (Table 1.3)

Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted

Command error.

C141-E056-01EN 5 - 59

5 - 60

Table 5.12 Contents of SECURITY SET PASSWORD data

Word Contents

0 Control word

Bit 0 Identifier

0 = Sets a user password.

1 = Sets a master password.

Bits 1 to 7 Reserved

Bit 8 Security level

0 = High

1 = Maximum

1 to 16

Bits 9 to 15 Reserved

Password (32 bytes)

17 to 255 Reserved

Table 5.13

Relationship between combination of Identifier and Security level, and operation of the lock function

Indentifier

User

Master

User

Master

Level

High

High

Description

The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password or the master password already set.

The specified password is saved as a new master password. The lock function is not enabled.

Maximum The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password only. The master password already set cannot cancel LOCKED

MODE.

Maximum The specified password is saved as a new master password. The lock function is not enabled.

C141-E056-01EN

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 0 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

1

(35) SECURITY UNLOCK (F2h)

This command cancels LOCKED MODE.

The host transfers the 512-byte data shown in Table 1.1 to the device. Operation of the device varies as follows depending on whether the host specifies the master password or user password.

When the master password is selected

When the security level in LOCKED MODE is high, the password is compared with the master password already set. If the passwords are the same, LOCKED MODE is canceled.

Otherwise, the Aborted Command error is returned. If the security level in LOCKED

MODE is set to the highest level, the Aborted Command error is always returned.

When the user password is selected

The password is compared with the user password already set. If the passwords are the same, LOCKED MODE is canceled. Otherwise, the Aborted Command error is returned.

If the password comparison fails, the device decrements the UNLOCK counter. The

UNLOCK counter initially has a value of five. When the value of the UNLOCK counter reaches zero, this command or the SECURITY ERASE UNIT command causes the Aborted

Command error until the device is turned off and then on, or until a hardware reset is executed. Issuing this command with LOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCK counter.

Issuing this command in FROZEN MODE returns the Aborted Command error.

C141-E056-01EN 5 - 61

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 0 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

5 - 62 C141-E056-01EN

5.3.3

Error posting

Table 5.14 lists the defined errors that are valid for each command.

Table 5.14 Command code and parameters

Command name Error register (X'1F1')

READ SECTOR(S)

WRITE SECTOR(S)

READ MULTIPLE

WRITE MULTIPLE

READ DMA

WRITE DMA

WRITE VERIFY

READ VERIFY SECTOR(S)

RECALIBRATE

SEEK

INITIALIZE DEVICE

PARAMETERS

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

ICRC UNC INDF ABRT TR0NF

V V V

V*

V*

V*

2

2

2

V

V

V

V

V

V

V

V

V

V

V

V

SET MULTIPLE MODE

EXECUTE DEVICE

DIAGNOSTIC

FORMAT TRACK

READ LONG

WRITE LONG

READ BUFFER

WRITE BUFFER

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

SLEEP

CHECK POWER MODE

SMART

FLUSH CACHE

SECURITY DISABLE

PASSWORD

*

1

*

1

*

V

V

V

V

V

1

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

Invalid command

V: Valid on this command

*

1

: See the command descriptions.

*

2

: Valid only when Ultra DMA command is executed.

V

V

V

V

V

V

V

V

V

V

V

V

V

V

*

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

1

V

*

1

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Status register (X'1F7')

DRDY

V

V

V

V

V

V

V

V

V

V

V

DWF

V

V

V

V

V

V

V

V

V

V

V

ERR

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

C141-E056-02EN 5 - 63

5.4

Command Protocol

The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.

Commands can be executed only when the DRDY bit of the Status register is 1. However, the following commands can be executed even if DRDY bit is 0.

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

5.4.1

Data transferring commands from device to host

The execution of the following commands involves data transfer from the device to the host.

IDENTIFY DEVICE

READ SECTOR(S)

READ LONG

READ BUFFER

SMART: SMART Read Attribute Values, SMART Read Attribute Thresholds

The execution of these commands includes the transfer one or more sectors of data from the device to the host. In the READ LONG command, 516 bytes are transferred. Following shows the protocol outline.

a) The host writes any required parameters to the Features, Sector Count, Sector Number,

Cylinder, and Device/Head registers.

b) The host writes a command code to the Command register.

c) The device sets the BSY bit of the Status register and prepares for data transfer.

d) When one sector (or block) of data is available for transfer to the host, the device sets

DRQ bit and clears BSY bit. The drive then asserts INTRQ signal.

e) After detecting the INTRQ signal assertion, the host reads the Status register. The host reads one sector of data via the Data register. In response to the Status register being read, the device negates the INTRQ signal.

f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the

BSY bit and steps d) and after are repeated.

Even if an error is encountered, the device prepares for data transfer by setting the DRQ bit.

Whether or not to transfer the data is determined for each host. In other words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the

DRQ status by resetting.

Figure 5.2 shows an example of READ SECTOR(S) command protocol, and Figure 5.3

shows an example protocol for command abort.

5 - 64 C141-E056-02EN

BSY

DRDY

Parameter write

~ a

Command b c

DRQ d

Status read e

• • • • f d e

Status read

• • • •

INTRQ

Data transfer

DRQ

Command

Expanded

Min. 30

µ s (*1)

INTRQ

Data Reg.

Selection

• • •

Data

IOR-

• • • •

• • • •

• • • •

Word 0 1 2 255

IOCS16-

*1 When the IDD receives a command that hits the cache data during read-ahead, and

transfers data from the buffer without reading from the disk medium.

Figure 5.2

Read Sector(s) command protocol

Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data transfer. It is up to the host whether data is transferred. In other words, the host should receive the data of the sector (512 bytes of uninsured dummy data) or release the DRQ by resetting.

C141-E056-01EN 5 - 65

Note:

For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the

DRQ setting by the device to 5

µ s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.

When the host new command even if the device requests the data transfer (setting in DRQ bit), the correct device operation is not guaranteed.

BSY

DRDY

Parameter write

~

DRQ

Command

Status read

INTRQ

Data transfer

* Transfers dummy data

* The host should receive 512-byte dummy data or release the DRQ set state by resetting.

Figure 5.3

Protocol for command abort

5.4.2

Data transferring commands from host to device

The execution of the following commands involves Data transfer from the host to the drive.

FORMAT TRACK

WRITE SECTOR(S)

WRITE LONG

WRITE BUFFER

WRITE VERIFY

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

SECURITY SET PASSWORD

SECURITY UNLOCK

The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline.

5 - 66 C141-E056-01EN

a) The host writes any required parameters to the Features, Sector Count, Sector Number,

Cylinder, and Device/Head registers.

b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register.

c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit.

d) The host writes one sector of data through the Data register.

e) The device clears the DRQ bit and sets the BSY bit.

f) When the drive completes transferring the data of the sector, the device clears BSY bit and asserts INTRQ signal. If transfer of another sector is requested, the drive sets the DRQ bit.

g) After detecting the INTRQ signal assertion, the host reads the Status register.

h) The device resets INTRQ (the interrupt signal).

I) If transfer of another sector is requested, steps d) and after are repeated.

Figure 5.4 shows an example of WRITE SECTOR(S) command protocol, and Figure 5.3

shows an example protocol for command abort.

BSY

Parameter write

~ a

DRDY

DRQ b

Command

INTRQ

Data transfer d

Command

Expanded

DRQ

Max. 1

µ s c e

Data Reg. Selection

Data

IOR-

IOCS16

Word 0 1 f

Status read g d h

• • •

• • • •

Status read g

• • • •

2

• • • •

• • • •

• • • •

255

Figure 5.4 WRITE SECTOR(S) command protocol

C141-E056-01EN 5 - 67

Note:

For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the

DRQ setting by the device to 5

µ s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred. If the timing to read the Status register does not meet above condition, normal data transfer operation is not assured guaranteed.

When the host issues the command even if the drive requests the data transfer (DRQ bit is set), or when the host executes resetting, the device correct operation is not guaranteed.

5.4.3

Commands without data transfer

Execution of the following commands does not involve data transfer between the host and the device.

RECALIBRATE

SEEK

READY VERIFY SECTOR(S)

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

SET FEATURES

SET MULTIPLE MODE

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

CHECK POWER MODE

FLUSH CACHE

SECURITY ERASE PREPARE

SECURITY FREEZE LOCK

SMART: except for SMART Read Attribute values and SMART Read Attribute

Thresholds

Figure 5.5 shows the protocol for the command execution without data transfer.

BSY

Parameter write

~

DRDY

INTRQ

Command

Status read

Figure 5.5

Protocol for the command execution without data transfer

5 - 68 C141-E056-01EN

5.4.4

Other commands

READ MULTIPLE

SLEEP

WRITE MULTIPLE

See the description of each command.

5.4.5

DMA data transfer commands

READ DMA

WRITE DMA

IDENTIFY DEVICE DMA

Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE

SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.

The interrupt processing for the DMA transfer differs the following point.

The interrupt processing for the DMA transfer differs the following point.

a) The host writes any parameters to the Features, Sector Count, Sector Number,

Cylinder, and Device/Head register.

b) The host initializes the DMA channel c) The host writes a command code in the Command register.

d) The device sets the BSY bit of the Status register.

e) The device asserts the DMARQ signal after completing the preparation of data transfer. The device asserts either the BSY bit during DMA data transfer.

f) When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal.

g) The host reads the Status register.

h) The host resets the DMA channel.

C141-E056-02EN 5 - 69

BSY

Parameter write a

~

DRDY

INTRQ

DRQ

Data transfer

Command c, d e

• •

• •

• • f

Expanded

[Multiword DMA transfer]

DRQ

DMARQ

DMACK-

IOR- or

IOW-

Word 0

• • • •

• • • •

• • • •

• • • •

1 n-1

Figure 5.6

Normal DMA data transfer

n

Status read g

5 - 70 C141-E056-01EN

5.5

Ultra DMA feature set

5.5.1

Overview

Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra

DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).

Several signal lines are redefined to provide new functions during an Ultra DMA burst. These lines assume these definitions when 1) an Ultra DMA Mode is selected, and 2) a host issues a

READ DMA or a WRITE DMA, command requiring data transfer, and 3) the host asserts

DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of DMACK- by the host at the termination of an Ultra DMA burst. All of the control signals are unidirectional. DMARQ and DMACK- retain their standard definitions.

With the Ultra DMA protocol, the control signal (STROBE) that latches data from DD (15:0) is generated by the same agent (either host or device) that drives the data onto the bus.

Ownership of DD (15:0) and this data strobe signal are given either to the device during an

Ultra DMA data in burst or to the host for an Ultra DMA data out burst.

During an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a

STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data. The highest fundamental frequency on the cable shall be 16.67 million transitions per second or 8.33 MHz (the same as the maximum frequency for PIO Mode 4 and DMA Mode 2).

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the

Ultra DMA Modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates. The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only the Ultra DMA Mode shall be selected at any given time. All timing requirements for a selected Ultra DMA Mode shall be satisfied. Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and

1. Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0.

An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after executing a Software reset sequence. An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non-Ultra DMA Modes after executing a

Power on or hardware reset.

Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its

CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more

Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

C141-E056-01EN 5 - 71

5.5.2

Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra

DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6.4 defines the specific timing requirements).

In the following rules DMARDY- is used in cases that could apply to either DDMARDY- or

HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or

HSTROBE. The following are general Ultra DMA rules.

a) An Ultra DMA burst is defined as the period from an assertion of DMACK- by the host to the subsequent negation of DMACK-.

b) A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst.

5.5.3

Ultra DMA data in commands

5.5.3.1 Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.1 and 5.6.4.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of

DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.

3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert

STOP.

4) The host shall negate HDMARDY-.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,

DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4) and (5) shall have occurred at least t

ACK

before the host asserts DMACK-.

The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7) The host shall release DD (15:0) within t

AZ

after asserting DMACK-.

8) The device may assert DSTROBE t

ZIORDY

after the host has asserted DMACK-. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.

9) The host shall negate STOP and assert HDMARDY- within t

ENV

after asserting DMACK-.

After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).

10) The device shall drive DD (15:0) no sooner than t

ZAD

after the host has asserted DMACK-, negated STOP, and asserted HDMARDY-.

5 - 72 C141-E056-01EN

11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10).

12) To transfer the first word of data the device shall negate DSTROBE within t

FS

after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than t

DVS

after driving the first word of data onto DD (15:0).

5.5.3.2 The data in transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.3 and 5.6.4.2):

1) The device shall drive a data word onto DD (15:0).

2) The device shall generate a DSTROBE edge to latch the new word no sooner than t

DVS after changing the state of DD (15:0). The device shall generate a DSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA Mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than 2t

CYC

for the selected Ultra DMA mode.

3) The device shall not change the state of DD (15:0) until at least t

DVH

after generating a

DSTROBE edge to latch the data.

4) The device shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra

DMA burst is paused, whichever occurs first.

5.5.3.3 Pausing an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.4 and 5.6.4.2 for specific timing requirements).

a) Device pausing an Ultra DMA data in burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.

NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t

RP

before asserting STOP.

3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.

b) Host pausing an Ultra DMA data in burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by negating HDMARDY-.

C141-E056-01EN 5 - 73

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating

HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a

DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.

5.5.3.4 Terminating an Ultra DMA data in burst

a) Device terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.5 and 5.6.4.2 for specific timing requirements):

1) The device shall initiate termination of an Ultra DMA burst by not generating

DSTROBE edges.

2) The device shall negate DMARQ no sooner than t

SS

after generating the last

DSTROBE edge. The device shall not assert DMARQ again until after the Ultra

DMA burst is terminated.

3) The device shall release DD (15:0) no later than t

AZ

after negating DMARQ.

4) The host shall assert STOP within t

LI

after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

5) The host shall negate HDMARDY- within t

LI

after the device has negated DMARQ.

The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated. Steps (4) and (5) may occur at the same time.

6) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated

DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5):

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (6), the host shall place the result of its CRC calculation on

DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted

DSTROBE and negated DMARQ and the host has asserted STOP and negated

HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

5 - 74 C141-E056-01EN

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DSTROBE within t

IORDYZ

after the host negates DMACK-.

13) The host shall not negate STOP no assert HDMARDY- until at least t

ACK

after negating DMACK-.

14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

b) Host terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.6 and 5.6.4.2 for specific timing requirements):

1) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated.

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating

HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a

DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall assert STOP no sooner than t

RP

after negating HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

6) The device shall negate DMARQ within t

LI

after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) The device shall release DD (15:0) no later than t

AZ

after negating DMARQ.

9) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated

DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5).

C141-E056-01EN 5 - 75

10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on

DD (15:0) (see 5.5.5).

11) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted

DSTROBE and negated DMARQ and the host has asserted STOP and negated

HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

12) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

13) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

14) The device shall release DSTROBE within t

IORDYZ

after the host negates DMACK-.

15) The host shall neither negate STOP nor assert HDMARDY- until at least t

ACK

after the host has negated DMACK-.

16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

5.5.4

Ultra DMA data out commands

5.5.4.1 Initiating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.7 and 5.6.4.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst.

3) Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert

STOP.

4) The host shall assert HSTROBE.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,

DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4), and (5) shall have occurred at least t

ACK

before the host asserts DMACK-.

The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7) The device may negate DDMARDY- t

ZIORDY

after the host has asserted DMACK-. Once the device has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK- at the end of an Ultra DMA burst.

8) The host shall negate STOP within t

ENV

after asserting DMACK-. The host shall not assert

STOP until after the first negation of HSTROBE.

5 - 76 C141-E056-01EN

9) The device shall assert DDMARDY- within t

LI

after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host.

10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

11) To transfer the first word of data: the host shall negate HSTROBE no sooner than t

LI

after the device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than t

DVS

after the driving the first word of data onto DD (15:0).

5.5.4.2 The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.8 and 5.6.4.2 for specific timing requirements):

1) The host shall drive a data word onto DD (15:0).

2) The host shall generate an HSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t

CYC

for the selected Ultra DMA mode.

3) The host shall not change the state of DD (15:0) until at least t

DVH

after generating an

HSTROBE edge to latch the data.

4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra

DMA burst is paused, whichever occurs first.

5.5.4.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.9 and 5.6.4.2 for specific timing requirements).

a) Host pausing an Ultra DMA data out burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.

Note: The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges. If the host does not assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate

DDMARDY- and wait t

RP

before negating DMARQ.

3) The host shall resume an Ultra DMA burst by generating an HSTROBE edge.

C141-E056-01EN 5 - 77

b) Device pausing an Ultra DMA data out burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by negating DDMARDY-.

3) The host shall stop generating HSTROBE edges within t

RFS

of the device negating

DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an

HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.

5.5.4.4 Terminating an Ultra DMA data out burst

a) Host terminating an Ultra DMA data out burst

The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.10 and 5.6.4.2 for specific timing requirements):

1) The host shall initiate termination of an Ultra DMA burst by not generating

HSTROBE edges.

2) The host shall assert STOP no sooner than t

SS

after it last generated an HSTROBE edge. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

3) The device shall negate DMARQ within t

LI

after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

4) The device shall negate DDMARDY- with t

LI

after the host has negated STOP. The device shall not assert DDMARDY- again until after the Ultra DMA burst termination is complete.

5) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

6) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5)

7) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted

HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

8) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

5 - 78 C141-E056-01EN

9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

10) The device shall release DDMARDY- within t

IORDYZ

after the host has negated

DMACK-.

11) The host shall neither negate STOP nor negate HSTROBE until at least t

ACK

after negating DMACK-.

12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

b) Device terminating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing requirements):

1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.

3) The host shall stop generating an HSTROBE edges within t

RFS

of the device negating

DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an

HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall negate DMARQ no sooner than t

RP

after negating DDMARDY-.

The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

6) The host shall assert STOP with t

LI

after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

7) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE. HSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted

HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

C141-E056-01EN 5 - 79

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DDMARDY- within t

IORDYZ

after the host has negated DMACK-.

13) The host shall neither negate STOP nor HSTROBE until at least t

ACK

after negating

DMACK-.

14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

5.5.5

Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a) Both the host and the device shall have a 16-bit CRC calculation function.

b) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d) For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e) At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of DMACK-.

f) The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous

Ultra DMa burst in the same command. If a miscompare error occurs during one or more

Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g) For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one.

ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h) A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

5 - 80 C141-E056-01EN

I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.

Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.

5.5.6

Series termination required for Ultra DMA

Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device.

Table 5.15 Recommended series termination for Ultra DMA

Signal

DIOR-:HDMARDY-:HSTROBE

DIOW-:STOP

CS0-, CS1-

Host Termination Device Termination

33 ohm

33 ohm

33 ohm

82 ohm

82 ohm

82 ohm

DA0, DA1, DA2

DMACK-

DD15 through DD0

DMARQ

INTRQ

IORDY:DDMARDY-

:DSTROBE

33 ohm

33 ohm

33 ohm

82 ohm

82 ohm

82 ohm

82 ohm

82 ohm

Inductor

33 ohm

33 ohm

22 ohm

Note: Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra

DMA Mode. For signals also requiring a pull-up or pull-down resistor at the host see Figure 5.7.

Figure 5.7

Ultra DMA termination with pull-up or pull-down

C141-E056-02EN 5 - 81

5.6

Timing

5.6.1

PIO data transfer

Figure 5.8 shows of the data transfer timing between the device and the host system.

t0

Addresses t1 t9

DIOR-/DIOWt2 t2i

Write data

DD0-DD15 t3 t4

Read data

DD0-DD15 t5 t6 t10 t11

IORDY t12 t10 t11 t12 t6 t9 t4 t5

Symbol t0 t1 t2 t2i t3

Timing parameter

Cycle time

Data register selection setup time for DIOR-/DIOW-

Pulse width of DIOR-/DIOW-

Recovery time of DIOR-/DIOW-

Data setup time for DIOW-

Data hold time for DIOW-

Time from DIOR- assertion to read data available

Data hold time for DIOR-

Data register selection hold time for DIOR-/DIOW-

Time from DIOR-/DIOW- assertion to IORDY "low" level

Time from validity of read data to IORDY "high" level

Pulse width of IORDY

Figure 5.8

PIO data transfer timing

Min.

Max.

Unit

120

25

— ns ns

70

25

20

— ns ns ns

10

20

5

10

0

35

— 1,250 ns ns ns ns ns ns ns

5 - 82 C141-E056-01EN

5.6.2

Multiword data transfer

Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system.

t0

DMARQ

DMACK-

DIOR-/DIOWtI tC tD tJ tK

Write data

DD0-DD15 tG tH

Read data

DD0-DD15 tE tF

Symbol t0 tC

Timing parameter

Cycle time

Delay time from DMACK assertion to DMARQ negation tH tI tJ tD tE tF tG tK

Pulse width of DIOR-/DIOW-

Data setup time for DIOR-

Data hold time for DIOR-

Data setup time for DIOW-

Data hold time for DIOW-

DMACK setup time for DIOR-/DIOW-

DMACK hold time for DIOR-/DIOW-

Continuous time of high level for DIOR-/DIOW-

Figure 5.9

Multiword DMA data transfer timing (mode 2)

10

0

5

25

Min.

Max.

Unit

120 — ns

— 35 ns

70

5

20

30

— ns ns ns ns

— ns ns ns ns

C141-E056-01EN 5 - 83

5.6.3

Ultra DMA data transfer

Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts.

Table 5.16 contains the values for the timings for each of the Ultra DMA Modes.

5.6.3.1 Initiating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

5 - 84

Note:

The definitions for the STOP, HDMARDY-and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

Figure 5.10 Initiating an Ultra DMA data in burst

C141-E056-01EN

5.6.3.2 Ultra DMA data burst timing requirements

Table 5.16 Ultra DMA data burst timing requirements (1 of 2)

t

LI t

MLI t

UI t

AZ t t t t t t t t t t t t

NAME

CYC t2

CYC

DS

DH

DVS

DVH

FS

ZAH

ZAD

ENV

SR

RFS

RP

MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MIN MAX MIN MAX MIN MAX

114 75 55

235

15

5

70

6

0

0

20

0

230

150

10

156

10

5

48

6

0

0

20

0

200

150

10

117

7

5

34

6

0

0

20

0

COMMENT

Cycle time (from STROBE edge to

STROBE edge)

Two cycle time (from rising edge to next rising edge or from falling edge to next falling edge of STROBE)

Data setup time (at recipient)

Data hold time (at recipient)

Data valid setup time at sender (from data bus being valid until STROBE edge)

Data valid hold time at sender (from

STROBE edge until data may become invalid)

170 First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)

150 Limited interlock time (see Note 1)

Interlock time with minimum (see Note 1)

Unlimited interlock time (see Note 1)

10 Maximum time allowed for output drivers to release (from being asserted or negated)

20

0

20

0

20

0

Minimum delay time required for output drivers to assert or negate (from released state)

20

160

70

50

75

20

125

70

30

60

20

100

70 Envelope time (from DMACK- to STOP and HDMARDY- during data in burst initiation and from DMACK to STOP during data out burst initiation)

20 STROBE-to-DMARDY-time (if DMARDYis negated before this long after STROBE edge, the recipient shall receive no more than one additional data word)

50 Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY)

Ready-to-pause time (that recipient shall wait to initiate pause after negating

DMARDY-)

C141-E056-01EN 5 - 85

Table 5.16 Ultra DMA data burst timing requirements (2 of 2)

t t t t

NAME

IORDYZ

ZIORDY

ACK

SS

MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX

20 20 20 Pull-up time before allowing IORDY to be released

0 0 0

20

50

20

50

20

50

Minimum time device shall wait before driving IORDY

Setup and hold times for DMACK- (before assertion or negation)

Time from STROBE edge to negation of

DMARQ or assertion of STOP (when sender terminates a burst)

Notes:

1) t

UI

, t

MLI

and t

LI

indicate sender -to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. t

UI

is an unlimited interlock, that has no maximum time value. t

MLI

is a limited time-out that has a defined minimum. t

LI

is a limited time-out, that has a defined maximum.

2) All timing parameters are measured at the connector of the device to which the parameter applies. For example, the sender shall stop generating STROBE edges t

RFS

after the negation of DMARDY-. Both

STROBE and DMARDY- timing measurements are taken at the connector of the sender.

3) All timing measurement switching points (low to high and high to low) are to be taken at 1.5 V.

5 - 86 C141-E056-01EN

5.6.3.3 Sustained Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

Figure 5.11 Sustained Ultra DMA data in burst

C141-E056-01EN 5 - 87

5.6.3.4 Host pausing an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Notes:

1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t

RP

after HDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the host may receive zero, one or two more data words from the device.

Figure 5.12 Host pausing an Ultra DMA data in burst

5 - 88 C141-E056-01EN

5.6.3.5 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.13 Device terminating an Ultra DMA data in burst

C141-E056-01EN 5 - 89

5.6.3.6 Host terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.14 Host terminating an Ultra DMA data in burst

5 - 90 C141-E056-01EN

5.6.3.7 Initiating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

Figure 5.15 Initiating an Ultra DMA data out burst

C141-E056-01EN 5 - 91

5.6.3.8 Sustained Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

Figure 5.16 Sustained Ultra DMA data out burst

5 - 92 C141-E056-01EN

5.6.3.9 Device pausing an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Notes:

1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t

RP

after DDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the device may receive zero, one or two more data words from the host.

Figure 5.17 Device pausing an Ultra DMA data out burst

C141-E056-01EN 5 - 93

5.6.3.10 Host terminating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.18 Host terminating an Ultra DMA data out burst

5 - 94 C141-E056-01EN

5.6.3.11 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.19 Device terminating an Ultra DMA data out burst

C141-E056-01EN 5 - 95

5.6.4

Power-on and reset

Figure 5.20 shows power-on and reset (hardware and software reset) timing.

(1) Only master device is present

Clear Reset *1

Power-on

RESET-

Software reset tM tN

BSY

DASPtP

*1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset.

(2) Master and slave devices are present (2-drives configuration)

[Master device]

BSY

DASP-

[Slave device]

BSY

PDIAG-

DASP-

Clear Reset tN tP tQ tS tR

Symbol tM Pulse width of RESET-

Timing parameter tN tP tQ tR tS

Time from RESET- negation to BSY set

Time from RESET- negation to DASP- or DIAG- negation

Self-diagnostics execution time

Time from RESET- negation to DASP- assertion (slave device)

Duration of DASP- assertion

Figure 5.20 Power-on Reset Timing

Min.

Max.

Unit

25 —

µ s

— 400 ns

— 1

— 30 ms s

— 400

— 31 ms s

5 - 96 C141-E056-01EN

CHAPTER 6 OPERATIONS

6.1

Device Response to the Reset

6.2

Address Translation

6.3

Power Save

6.4

Defect Management

6.5

Read-Ahead Cache

6.6

Write Cache

6.1

Device Response to the Reset

This section describes how the PDIAG- and DASP- signals responds when the power of the

IDD is turned on or the IDD receives a reset or diagnostic command.

C141-E056-01EN 6 - 1

6.1.1

Response to power-on

After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).

The master device recognizes presence of the slave device when it confirms assertion of the

DASP- signal. Then, the master device checks a PDIAG- signal to see if the slave device has successfully completed the power-on diagnostics.

If the master device cannot confirm assertion of the DASP- signal within 450 ms, the master device recognizes that no slave device is connected.

After the slave device (device 1) releases its own power-on reset state, the slave device shall report its presence and the result of power-on diagnostics to the master device as described below:

DASP- signal: Asserted within 400 ms, and negated after the first command is received from the host or within 31 seconds or after executing software reset, which ever comes first.

PDIAG- signal: Negated within 1 ms and asserted within 30 seconds, then negated within 31 seconds.

Power on

Master device

Power On Reset-

Status Reg.

BSY bit

Max. 31 sec.

Checks DASP- for up to

450 ms.

If presence of a slave device is confirmed, PDIAG- is checked for up to 31 seconds.

Slave device

Power On Reset-

BSY bit

PDIAG-

DASP-

Max. 1 ms.

Max. 30 sec.

Max. 400 ms.

Max. 31 sec.

Figure 6.1

Response to power-on

6 - 2 C141-E056-01EN

.

6.1.2

Response to hardware reset

Response to RESET- (hardware reset through the interface) is similar to the power-on reset.

Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal. Then the master device checks a

PDIAG- signal to see if the slave device has successfully completed the self-diagnostics.

If the master device cannot confirm assertion of the DASP- signal within 450 ms, the master device recognizes that no slave device is connected.

After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below:

DASP- signal: Asserted within 400 ms, and negated after the first command is received from the host or within 31 seconds or after executing software reset, which ever comes first.

PDIAG- signal: Negated within 1 ms and asserted within 30 seconds, then negated within 31 seconds

Reset-

Master device

Status Reg.

BSY bit

Checks DASP- for up to

450 ms.

Max. 31 sec.

If presence of a slave device is confirmed, PDIAG- is checked for up to 31 seconds.

Slave device

BSY bit

PDIAG-

DASP-

Max. 1 ms.

Max. 30 sec.

Max. 400 ms.

Max. 31 sec.

Figure 6.2

Response to hardware reset

C141-E056-01EN 6 - 3

6.1.3

Response to software reset

The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.

After the slave device receives the software reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below:

PDIAG- signal: negated within 1 ms and asserted within 30 seconds then negated within 31 seconds.

When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the

PDIAG- signal, and negates the DASP- signal when asserting the PDIAG- signal.

X'3F6' Reg.

Master device

Status Reg.

BSY bit

X"0C" or X"04"

X"00"

Max. 31 sec.

If the slave device is preset, DASP- is checked for up to

31 seconds.

Slave device

BSY bit

PDIAG-

DASP-

Max. 1 ms.

Max. 30 sec.

Figure 6.3

Response to software reset

6 - 4 C141-E056-01EN

6.1.4

Response to diagnostic command

When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully.

The master device does not check the DASP- signal.

After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command, it shall report the result of the self-diagnostics to the master device as described below:

PDIAG- signal: negated within 1 ms and asserted within 5 seconds then negated within 6 seconds.

When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the

PDIAG- signal, and negates the DASP- signal when asserting the PDIAG- signal.

X'1F7' Reg.

Write

Master device

Status Reg.

BSY bit

Max. 6 sec.

If the slave device is preset, DASP- signal is checked for up to

6 seconds.

Slave device

BSY bit

PDIAG-

DASP-

Max. 1 ms.

Max. 5 sec.

Figure 6.4

Response to diagnostic command

C141-E056-01EN 6 - 5

6.2 Address Translation

When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation).

Following subsections explains the CHS translation mode.

6.2.1

Default parameters

In the logical to physical address translation, the logical cylinder, head, and sector addresses are translated to the physical cylinder, head, and sector addresses based on the number of heads and the number of sectors per track which are specified with an INITIALIZE DEVICE

PARAMETERS command. This is called as the current translation mode.

If the number of heads and the number of sectors are not specified with an INITIALIZE DEVICE

PARAMETERS command, the default values listed in Table 6.1 are used. This is called as the default translation mode. The parameters in Table 6.1 are called BIOS specification.

Table 6.1

Default parameters

Number of cylinders

Parameters

(logical)

Number of head

Number of sectors/track

Formatted capacity (MB)

MPC3065AH MPC3045AH

13,456 9,408

15

63

6,510.5

4,551.9

As long as the formatted capacity of the IDD does not exceed the value shown on Table 6.1, the host can freely specify the number of cylinders, heads, and sectors per track.

Generally, the device recognizes the number of heads and sectors per track with the

INITIALIZE DEVICE PARAMETER command. However, it cannot recognizes the number of cylinders. In other words, there is no way for the device to recognize a host access area on logical cylinders. Thus the host should manage cylinder access to the device.

The host can specify a logical address freely within an area where an address can be specified

(within the specified number of cylinders, heads, and sectors per track) in the current translation mode.

The host can read an addressable parameter information from the device by the IDENTIFY

DEVICE command (Words 54 to 56).

6 - 6 C141-E056-01EN

6.2.2

Logical address

(1) CHS mode

Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command. The head address is advanced at the subsequent sector from the last sector of the current physical head address.

The first physical sector of the subsequent physical sector is the consecutive logical sector from the last sector of the current physical sector.

Figure 6.5 shows an example (assuming there is no track skew).

Physical sector

Physical cylinder 0

Physical head 0

1 2

LS

1

LS

2

3

. .

. .

LH0

62 63

LS

63

64

LS

1

. .

126

LS

. .

63

127

LS

1

. .

189

LS

. .

63

LH1 LH2

190

. .

LS

1

. .

241

LS

52

242 243

SP SP

LH3

Physical cylinder 0

Physical sector

1 . .

11

LS LS

Physical head 1 53

. .

63

12

LS

1

. .

. .

LH3 LH4

74

LS

63

75

LS

1

. .

137

LS

. .

63

LH5

138 . .

LS

200

LS

1

. .

63

LH6

201

. . . .

LS

1

. . . .

. . . .

LH7

242

SP

243

SP ex: Zone 0

Physical parameter

- Physical sector: 1 to 241 (For the rest, 2 spare sectors)

Specification of INITIALIZE DEVICE PARAMETERS command

- Logical head: LH=0 to 14

- Logical sector: LS=1 to 63

Figure 6.5

Address translation (example in CHS mode)

C141-E056-01EN 6 - 7

(2) LBA mode

Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. The logical address is advanced at the subsequent sector from the last sector of the current track. The first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track.

Figure 6.6 shows an example of (assuming there is no track skew).

Physical cylinder 0

Physical head 0

Physical sector

1 2 3

LBA

0

LBA

1

LBA

2

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

240 241

LBA

239

LBA

240

242

SP

243

SP

Physical cylinder 0

Physical head 1

1 2 3

LBA

241

LBA

242

LBA

243

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

240 241

LBA

480

LBA

481

242

SP

243

SP ex: Zone 0

Physical parameter

- Physical sector: 1 to 241 (For the rest, 2 spare sectors)

Figure 6.6

Address translation (example in LBA mode)

6.3

Power Save

The host can change the power consumption state of the device by issuing a power command to the device.

6.3.1

Power save mode

There are four types of power consumption state of the device including active mode where all circuits are active.

In the power save mode, power supplying to the part of the circuit is turned off. There are three types of power save modes:

Idle mode

Standby mode

Sleep mode

6 - 8 C141-E056-01EN

(1) Active mode

In this mode, all the electric circuit in the device are active and seek, read, or write operation is possible.

A device enters the active mode under the following conditions:

Power-on sequence is completed.

A command with accessing the medium is issued in Idle mode or Standby mode. And in case that the following command with accessing the host is issued when the device is in

Active mode, the device is stayed in the active mode after processing.

Reset

A power command other than CHECK POWER MODE command is issued.

(2) Idle mode

In this mode, the VCM circuit is turned off. Although the device interface can receive a command in case of accessing the drive, it will take much more time than that in the active mode because it can not access the drive directly at once.

The device enters the Idle mode under the following conditions.

IDLE command or IDLE IMMEDIATE command is issued in the active mode or Standby mode. And in case that the following command with accessing the host is issued when the device is in Idle mode, the device is still stayed in the Idle mode after processing.

Reset

IDLE command or IDLE IMMEDIATE command

A command without accessing the medium

(3) Standby mode

In this mode, the VCM circuit is turned off and the spindle motor is stopped.

The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately.

The drive enters the standby mode under the following conditions:

A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode.

When automatic power down sequence is enabled, the timer has elapsed.

A reset is issued in the sleep mode.

C141-E056-02EN 6 - 9

When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode.

Reset (hardware or software)

STANDBY command

STANDBY IMMEDIATE command

A command without accessing the drive

CHECK POWER MODE command

(4) Sleep mode

The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset.

The drive enters the sleep mode under the following condition:

A SLEEP command is issued.

Issued commands are invalid (ignored) in this mode.

6.3.2

Power commands

The following commands are available as power commands.

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

SLEEP

CHECK POWER MODE

6.4

Defect Management

Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatting at the factory shipment.

All the user space area are formatted at shipment from the factory based on the default parameters listed in Table 6.1.

6 - 10 C141-E056-02EN

6.4.1

Spare area

Following two types of spare area are provided in the user space.

1) Spare sector for sector slip: used for alternating defective sectors at formatting in shipment in case that a physical track contains one or two defective sectors (2 sectors/track)

2) Spare cylinder for track slip: used for alternative assignment for the third and subsequent defective sectors in case that a physical track contains three or more defective sectors, and also used by automatic alternative assignment (78 cylinders/drive).

3) Spare cylinder for alternative assignment: used for automatic alternative assignment (1 cylinder/drive).

6.4.2

Alternating defective sectors

The two alternating methods described below are available:

(1) Sector slip processing

A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector (physically adjacent sector to the defective sector).

When defective sector is present, the sector slip processing is performed in the formatting.

Figure 6.7 shows an example where (physical) sector 5 is defective on head 0 in cylinder 0.

Index

Cylinder 0

1 2

Sector (physical)

3 4 5

Defective sector

6 7 8

SP

Head 0

1 2 3 4

Sector (logical) unused

5 6 7

If an access request to sector 5 is specified, the device accesses physical sector 6 instead of sector 5.

Figure 6.7

Sector slip processing

C141-E056-02EN 6 - 11

(2) Track slip processing

Track slip processing is the method that ensures all the sectors contained in a physical track in track slip area. The processing is performed when a physical track contains three or more defective sectors. But automatic alternation assignment is not performed after shipment.

Track slip area is set to the most inner Zone 14, and the same number sectors as that in a physical track containing defective sectors are used in track slip area (spare sectors are not included).

Figure 6.8 shows an example that cylinder 0, head 0 is at track slip processsing.

Index

Sector (physical)

1 2

Cylinder 0

Head 0

3 4 5 6 unused unused unused unused unused unused

3 4 5 6 1 2

Cylinder 0

Head 1

Cylinder 0

Head 0

Sector 1 2

1

Track slip 0

Head 0

Track slip 0

Head 1

Cylinder 0

Head 0

Sector 1

1

Cylinder 0

Head 0

Sector 163

2

3

3

4

4

81

5

5

82

Cylinder 0

Head 0

Sector 241 unused

6

Figure 6.8

Track slip processing

241 242 243

SP SP unused unused unused

241 242

SP

243

SP

Cylinder 0

Head 0

Sector 241

161 162

161 162

(3) Automatic alternate assignment

The device performs the automatic assignment at following case.

1) When ECC correction performance is increased during read error retry, a read error is recovered.

6 - 12 C141-E056-02EN

Before automatic alternate assignment, the device performs rewriting the corrected data to the erred sector and rereading. If no error occurs at rereading, the automatic alternate assignment is not performed.

2) When a write error occurs and the error does not recovered.

Figure 6.9 shows an example where (physical) sector 5 is automatic alternated on head 0 in cylinder 0.

Index

Cylinder 0

Head 0

Sector (physical)

1 2 3

1 2

Sector (logical)

3

4 5

Defective sector

6

4

(unused)

6

7

7

242

SP

299

243

SP

300

Alternate cylinder

Head 0

Already assigned

Defective sector is assigned to unassigned sector.

When an access request to sector 5 is specified, the device accesses the alternated sector in the alternate cylinder instead of sector 5. When an access request to sectors next to sector 5 is specified, the device seeks to cylinder 0, head 0, and continues the processing.

Figure 6.9

Automatic Alternate assignment

C141-E056-02EN 6 - 13

6.5

Read-Ahead Cache

After a read command which reads the data from the disk medium is completed, the readahead cache function reads the subsequent data blocks automatically and stores the data in the data buffer.

When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium. The host can access the data at higher speed.

6.5.1

Data buffer configuration

The device has a 512-KB data buffer. The buffer is used by divided into three parts; for MPU work, for auto transfer of write commands, for read cache of read commands (see Figure 6.10).

for MPU work

32 KB

(32,768 bytes)

512 KB (524,288 bytes) for R/W command

480 KB (491,520 bytes)

Figure 6.10 Data buffer configuration

The read-ahead operation is performed at execution of the READ SECTOR(S), READ

MULTIPLE, or READ DMA command, and read-ahead data are stored in the buffer for read cache.

6 - 14 C141-E056-02EN

6.5.2

Caching operation

The caching operation is performed only at receipt of the following commands. The device transfers data from the data buffer to the host system if the following data exist in the data buffer.

All sector data to be processed by the command

A part of data including the starting sector to be processed by the command

When a part of data to be processed exist in the data buffer, the remaining data are read from the disk medium and are transferred to the host system.

(1) Commands that are object of caching operation

The following commands are object of caching operation.

READ SECTOR (S)

READ MULTIPLE

READ DMA

When the caching operation is disabled by the SET FEATURES command, no caching operation is performed.

(2) Data that are object of caching operation

The following data are object of caching operation.

1) Read-ahead data read from the disk medium in the data buffer after completion of the command that are object of caching operation.

2) Data transferred to the host system once by requesting with the command that are object of caching operation. But, when the sequential hit occurs continuously, the caching data required by the host becomes invalid.

(3) Invalidating caching data

Caching data in the data buffer is invalidated in the following case.

1) Commands other than the following commands are issued (all caching data are invalidated)

READ SECTOR(S)

READ DMA

READ MULTIPLE

2) Caching operation is disabled by the SET FEATURES command.

3) Command issued by the host is terminated with an error.

4) Soft reset or hard reset is executed, or power is turned off.

C141-E056-02EN 6 - 15

6.5.3

Usage of read segment

This subsection explains the usage of the read segment buffer at following cases.

(1) Miss-hit (no hit)

A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media.

1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the lead of segment.

HAP

Segment only for read

DAP

2) Transfers the requested data that already read to the host system with reading the requested data from the disk media.

HAP

Stores the read-requested data upto this point

Read-requested data

Empty area

DAP

3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive continues to read till the read segment becomes full.

HAP

(stopped)

Read-requested data

Read Ahead Data

(stopped)

DAP

4) Following shows the cache enabled data for next read command.

Cache enabled data

Start LBA Last LBA

6 - 16 C141-E056-02EN

(3) Sequential read

When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive tries to fill the whole of buffer space with the read ahead data.

a. Sequential command just after non-sequential command

1) At receiving the sequential read command, the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data.

HAP

Mis-hit data Empty data

DAP

2) The disk drive transfers the requested data that is already read to the host system with reading the requested data.

HAP

Mis-hit data Requested data Empty data

DAP

3) After completion of the reading and transferring the requested data to the host system, the disk drive performs the read-ahead operation continuously.

HAP

Mis-hit data Requested data

Readahead data

Empty data

DAP

C141-E056-02EN 6 - 17

6 - 18

4) The disk drive performs the read-ahead operation for all area of segment with overwriting the requested data. Finally, the cache data in the buffer is as follows.

HAP

Read-ahead data

DAP

Last LBA Start LBA b. Sequential hit

When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system.

The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.

1) In the case that the contents of buffer is as follows at receiving a read command;

HAP (Completion of transferring requested data)

Read-ahead data Hit data

DAP

Last LBA Start LBA

2) The disk drive starts the read-ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data.

HAP

Read-ahead data New read-ahead data Hit data

DAP

C141-E056-02EN

HAP

3) After completion of data transfer of hit data, the disk drive performs the read-ahead operation for the data area of which the disk drive transferred hit data.

Read-ahead data

DAP

4) Finally, the cache data in the buffer is as follows.

Read-ahead data

Start LBA Last LBA

(3) Full hit (hit all)

All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read-ahead operation.

1) In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command, the disk drive sets the HAP to the address of which the hit data is stored.

HAP

Last position at previous read command

HAP (set to hit position for data transfer)

Cache data Full hit data Cache data

Last position at previous read command

DAP

C141-E056-02EN 6 - 19

2) The disk drive transfers the requested data but does not perform the read-ahead operation.

Cache data Full hit data

HAP

(stopped)

Cache data

3) The cache data for next read command is as follows.

Cache data

Start LBA

Last LBA

(4) Partially hit

A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly.

Following is an example of partially hit to the cache data.

Cache data

Start LBA

Last LBA

1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data.

HAP

Partially hit data Lack data

DAP

6 - 20 C141-E056-02EN

2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time.

Requested data to be transferred

HAP

(stopped)

Partially hit data Lack data

DAP

3) The cache data for next read command is as follows.

Cache data

Last LBA

Start LBA

C141-E056-02EN 6 - 21

6.6

Write Cache

The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed.

When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium. After transferring data of sectors requested by the host system, the drive generates the interrupt of command complete.

Also, the drive sets the normal end status in the Status register. The drive continues writing data on the disk medium. When all data requested by the host are written on the disk medium, actual write operation is completed.

The drive receives the next command continuously. If the received command is a "sequential write" (data to be written by a command is logically sequent to data of previous command), the drive starts data transfer and receives data of sectors requested by the host system. At this time, if the write operation of the previous command is still been executed, the drive continuously executes the write operation of the next command from the sector next to the last sector of the previous write operation. Thus, the latency time for detecting a target sector of the next command is eliminated. This shortens the access time. The drive generates an interrupt of command complete after completion of data transfer requested by the host system as same as at previous command. When the write operation of the previous command had been completed, the latency time occurs to search the target sector.

If the received command is not a "sequential write", the drive receives data of sectors requested by the host system as same as "sequential write". The drive generates the interrupt of command complete after completion of data transfer requested by the host system.

Received data is processed after completion of the write operation to the disk medium of the previous command.

Even if a hard reset or soft reset is received or the write cache function is disabled by the SET

FEATURES command during unwritten data is kept, the instruction is not executed until remaining unwritten data is written onto the disk medium.

When an error occurs during the write operation, the drive makes retry as much as possible. If the error cannot be recovered by retry, the drive stops the write operation. And the write operation is not performed even if the write data is remained. After an error occurs at above write operation, the drive posts the error status to the host system at next command. (The drive does not execute this command, sets the error status that occurred at the write operation, and generates the interrupt for abnormal end. However, when the drive receives a write command after the completion of error processing, the drive posts the error after writing the write data of the write command.)

6 - 22 C141-E056-02EN

At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state.

The default state is “write cache enable”, and can be disable by the SET FEATURES command.

The write cache function is operated with the following command.

WRITE SECTOR(S)

WRITE MULTIPLE

WRITE DMA

IMPORTANT

When the write cache function is enabled, the transferred data from the host by the WRITE SECTOR(S) is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function.

C141-E056-02EN 6 - 23

Comments concerning this manual can be directed to one of the following addresses:

FUJITSU LIMITED

Business Planning

Solid Square East Tower

580 Horikawa-cho,Saiwai-ku, Kawasaki,

210-0913, Japan

TEL:

FAX:

81-44-540-4056

81-44-540-4123

FUJITSU COMPUTER PRODUCTS OF AMERICA, INC.

2904 Orchard Parkway, San Jose,

California 95134-2009, U.S.A.

TEL: 1-408-432-6333

FAX: 1-408-432-3908

FUJITSU CANADA INC.

2800 Matheson Blvd. East, Mississauga, Toronto,

Ontario L4W 4X5, CANADA

TEL:

FAX:

1-905-602-5454

1-905-602-5457

FUJITSU EUROPE LIMITED

2, Longwalk Road, Stockley Park, Uxbridge,

Middlesex UB11 1AB, ENGLAND

TEL:

FAX:

44-81-573-4444

44-81-573-2643

FUJITSU DEUTSCHLAND GmbH

Frankfurter Ring 211, 80807 München, GERMANY

TEL:

FAX:

49-89-323780

49-89-32378100

FUJITSU NORDIC AB

Kung Hans Väg 12, S-192 68 Sollentura, SWEDEN

TEL:

FAX:

46-8-626-6000

46-8-626-6711

FUJITSU ITALIA S.p.A.

Via Nazario Sauro, 38 20099 Sesto S. Giovanni (MI), ITALY

TEL:

FAX:

39-2-26294-1

39-2-26294-201

FUJITSU FRANCE S.A.

I, Place des Etas-Unis, SILIC 310,

94588 Rungis Cedex, FRANCE

TEL: 33-1-41-80-38-80

FAX: 33-1-41-80-38-66

FUJITSU ICL ESPAÑA S.A.

Almagro 40, 28010 Madrid, SPAIN

TEL:

FAX:

34-91-681-8100

34-91-681-8125

FUJITSU AUSTRALIA LIMITED

2 Julius Avenue (Cnr Delhi Road) North Ryde N.S.W. 2113,

AUSTRALIA

TEL:

FAX:

61-2-9776-4555

61-2-9776-4556

FUJITSU HONG KONG LTD.

Room 2521, Sun Hung Kai Centre, 30 Harbour Road, HONG

HONG

TEL: 852-2827-5780

FAX: 852-2827-4724

FUJITSU KOREA LTD.

Coryo Finance Center Bldg, 23-6, YoulDo-Dong,

Young DungPo-Gu, Seoul, Republic of KOREA

TEL:

FAX:

82-2-3787-6000

82-2-3787-6070

FUJITSU COMPUTERS (SINGAPORE) PTE. LTD

20 Science Park Road #03-01,

TELETECH PARK SINGAPORE SCIENCE PARK II,

Singapore 117674

TEL:

FAX:

65-777-6577

65-771-5499

FUJITSU TAIWAN LTD.

8F, Hun Tai Center, 168-170, Tun Hwa North Road,

1st Sec., Taipei, TAIWAN

TEL:

FAX:

886-2-545-7700

886-2-717-4644

FUJITSU SYSTEMS BUSINESS (MALAYSIA) SDN. BHD.

Fujitsu Plaza, 1A, Jalan Tandang 204, P.O. Box 636 Pejabat Pos

Jalan Sultan

46770 Petaling Jaya, Selangor Darul Ehsan, Malaysia

TEL:

FAX:

60-3-793-3888

60-3-793-0888

FUJITSU SYSTEMS BUSINESS (THAILAND) LTD.

12th F1., Olympia Thai Tower, 444 Rachadapisek Road,

Samsennok, Huay Kwang, Bangkok 10320, Thailand

TEL: 66-2-512-6066

FAX: 66-2-512-6068

10

Reader Comment Form

We would appreciate your comments and suggestions for improving this publication.

Publication No.

Rev. Letter Title

FUJITSU LIMITED

Current Date

How did you use this publication?

Learning

Reference

Installing

Maintaining

Sales

Operating

Is the material presented effectively?

Fully covered

What is your overall rating of this publication?

Very Good

Good

Fair

Poor

Very Poor

What is your occupation?

Your other comments may be entered here. Please be specific and give page, paragraph and line number references where applicable.

Well

Illustrated

Well

Organized

Clean

Your Name & Return Address

Thank you for your interest. Please send this sheet to one of the addresses in a left page.

advertisement

Related manuals

Download PDF

advertisement

Table of contents