Two 500M‐8GHz Wideband Balun‐ LNA‐I/Q‐Mixers

  Two 500M‐8GHz Wideband Balun‐ LNA‐I/Q‐Mixers
Master’s Thesis Two 500M‐8GHz Wideband Balun‐
LNA‐I/Q‐Mixers
Lin Zhu Supervised by Martin Liliebladh, LTH, Lund University Examined by Prof. Pietro Andreani, LTH, Lund University
April 2012
Two 500M‐8GHz Wideband Balun‐LNA‐I/Q‐Mixers Lin Zhu Copyright © Lin Zhu, 2012 The Department of Electrical and Information Technology Lund University Box 118, 221 00 Lund SWEDEN Author’s email: mas09zli@student.lu.se 2
ABSTRACT
Two wideband balun-LNA configurations have been designed in 65nm
COMS technology. Both of them employ a single-to-differential (S-to-D)
conversion topology composed of a common gate (CG) stage and a
common source (CS) stage, providing output balancing and noise and
distortion cancelling. One is inductorless and the other one exploits gainboosting current-balancing topology. With 2.5V and 2.5V/1.8V supply the
LNAs achieve voltage gains of 24.5dB and 22.8dB, noise figures of below
or close to 3dB, input second-order intercept points (IIP2) of 31dB and
41.8dB, respectively. In addition, the sensitivity of IIP2 is deeply
investigated.
Balun-LNA I/Q-mixers, which combine the balun-LNA cores and doublebalanced mixers, are also designed in the same CMOS technology to
resolve the bandwidth limitation in traditional direct-conversion receivers.
With 2.5V supply, around 20dB conversion gain, 3dB DSB noise figure,
18.3dB IIP2 and -3dB IIP3 are obtained by the BLIXER using LNA.A over
the bandwidth of 0.5 to 8GHz, while consuming 29mW DC power. The
counterpart, the BLIXER using LNA.B, achieves around 20dB conversion
gain, 4dB DSB noise figure, 38dB IIP2 and 2.8dB IIP3 over the same
bandwidth while dissipating 15mW from 2.5/1.8V supplies.
3
ACKNOWLEDGMENTS
This work couldn’t have been completed without the help of many people.
They have all enriched my life in some way, and I would like to take this
opportunity to thank them. So here goes… (In no particular order)
I would like to start by thanking my examiner, Professor Pietro Andreani
for giving me the opportunity to take part into this project. Also, I want to
express my appreciation to him for taking time to read and evaluate my
thesis.
Moreover, I would like to thank my supervisor, Martin Liliebladh, for his
support along these months, his invaluable help at all times and for his
endless patience.
I am also extremely grateful to Professor Henrik Sjöland for his help on my
paper. I do appreciate Dr Ping Lu for always finding time to help me. In
addition, I want to specially thank Wenjia Duan, who has always managed
to cheer me up. Thanks also go to all my classmates, colleagues and friends
for their assistance and friendship during the course of the study. They have
made my graduate studies an enjoyable and memorable experience of my
life.
Finally, but definitely not less important, I would like to thank my family.
Without my parents, this experience would have never been possible. I
would like to thank them for their caring, their strength of spirit and
support, not only these months, but my whole life, which has made me the
way I am.
Lin Zhu
Lund, April 2012
4
CONTENTS
Abstract
..................................................................................................3 Acknowledgments............................................................................................4 Contents
..................................................................................................5 Chapter1 Introduction.........................................................................8 1.1 1.2 ProjectOverview.........................................................................9 ThesisOrganization.................................................................10 Chapter2 TheoriesforRFReceivers............................................11 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 2.4.3 2.5 2.5.1 2.5.2 2.5.3 2.5.4 ReceiverArchitecture.............................................................12 BasicReceiverPerformanceMatrices...............................14 ReceiverSensitivity............................................................................14 NoiseFigure..........................................................................................14 HarmonicsandIntermodulationDistortions..........................15 1‐dBCompressionPoint(CP1).....................................................17 DesignIssuesforDirectConversionReceivers..............17 DCOffsets...............................................................................................17 I/QMismatch........................................................................................19 Even‐OrderDistortion......................................................................19 Flicker(1/ƒ)Noise..............................................................................20 LowNoiseAmplifiers...............................................................20 ImpedanceMatching.........................................................................22 Noise.........................................................................................................23 Linearity..................................................................................................24 Mixers............................................................................................24 ConversionGain(Loss)....................................................................24 NoiseFigure..........................................................................................24 LinearityandIsolation......................................................................25 Double‐BalancedMixer....................................................................25 Chapter3 Widebandnoisecancellingbalun‐LNAs..................27 3.1 3.1.1 Topology......................................................................................28 OutputBalancing(BalunOperation)..........................................28 5
3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.3 NoiseCancelling..................................................................................29 Transconductance‐Scaling..............................................................30 DistortionCancelling.........................................................................32 Scaled‐gmBalun‐LNA(LNA.A)...............................................34 InputMatching.....................................................................................35 GainandNoiseFigure.......................................................................35 Gain‐BoostingCurrent‐BalancingEqual‐gmBalun‐LNA
(LNA.B)..........................................................................................37 Chapter4 TheBLIXER........................................................................40 4.1 4.2 4.2.1 4.2.2 TheBasicBLIXERTopology..................................................41 TheI/Q‐BLIXERImplementations......................................42 I/Q‐BLIXERusingLNA.A..................................................................42 I/Q‐BLIXERusingLNA.B..................................................................45 Chapter5 SimulationResults..........................................................47 5.1 5.1.1 5.2.2 5.3 5.4 5.4.1 5.4.2 5.5 5.5.1 5.5.2 5.6 SimulationResultsforLNA.A................................................47 Gain,NoiseFigure,InputMatchingandDCPower
Consumption.........................................................................................47 Linearity..................................................................................................49 SimulationResultsforLNA.B................................................51 Gain,NoiseFigure,InputMatchingandDCPower
Consumption.........................................................................................51 Linearity..................................................................................................51 IIP2Analysis...............................................................................53 SimulationResultsforI/Q‐BLIXERusingLNA.A............56 ConversionGain,InputMatchingandNoiseFigure.............56 Linearity..................................................................................................59 SimulationResultsforI/QBLIXERusingLNA.B............61 ConversionGain,InputMatchingandNoiseFigure.............61 Linearity..................................................................................................64 PerformancesSummary.........................................................66 Chapter6 Conclusions.......................................................................67 5.1.2 5.2 5.2.1 6.1 6.2 References
Conclusions.................................................................................67 Futurework................................................................................68 ...............................................................................................69 ListofFigures ...............................................................................................72 ListofTables ...............................................................................................74 6
Acronyms
...............................................................................................75 Appendix1
...............................................................................................76 7
CHAPTER1
INTRODUCTION
1
INTRODUCTION
I
n recent years, RF receiver designers made efforts on replacing
analogue components with digital ones, striving towards the ideal
software defined radio (SDR) where all signal processing is done in
software. Such an ideal SDR platform may form an exceptionally flexible
and reprogrammable receiver that can cope with many different standards,
e.g., IS-95, GSM, UTMS, LTE and especially the various military
standards. A software defined radio can also avoid the "limited spectrum"
assumptions of previous kinds of radios by using spread spectrum and ultrawideband techniques, which allow several transmitters to transmit in the
8
same place on the same frequency with very little interference, typically
combined with one or more error detection and correction techniques to fix
all the errors caused by that interference. Consequently, the demand of
(ultra) wideband integrated RF building blocks with high performance has
driven the market and research to explore an area of wideband CMOS
RFIC designs for applications in a RF front-end transceiver.
Mixer
RF Filter
Balun
Differential
Output
LNA
LPF
LO
Figure 1.1 Block diagram of a RF receiver
Figure 1.1 shows a conventional direct conversion receiver front-end
architecture. To take the advantages of differential LNA design, e.g. even
order harmonic distortion rejection, a balun is commonly used to convert
the single-end input signal from the antenna to a pair of balanced signal fed
to the LNA. The balun is usually implemented on the PCB due to its large
form factor. Therefore, proper impedance transformation and matching
networks are often needed on the PCB, too, resulting in increased
complexity and cost of the PCB. On the other hand, if the balun is
implemented on chip, it consumes a lot of area which is very expensive in
today’s IC process. The evolution of circuitry provides the possibility to
remove the balun, simultaneously keeping the single-end to differential
conversion. This kind of circuit is the so-called Balun-LNA.
1.1 ProjectOverview
Two wideband balun-LNA configurations have been designed in
STMicroelectronics 65nm COMS technology. Both of them employ a
single-end-to-differential (S-to-D) conversion topology composed of a
common gate (CG) stage and a common source (CS) stage, providing
output balancing and noise and distortion cancelling. One uses gm-scaling
9
technique and the other one exploits gain-boosting current-balancing
topology. With 2.5V and 2.5V/1.8V supplies the LNAs achieve voltage
gains of 24.5dB and 22.8dB, noise figures of below or close to 3dB, input
second-order intercept points (IIP2) of 31dB and 41.8dB, respectively. In
addition, the sensitivity of IIP2 is deeply investigated with Monte-Carlo
analyses.
Then Balun-LNA I/Q-mixers, which combine the balun-LNA cores and
double-balanced mixers, are also designed in the same CMOS technology
to resolve the bandwidth limitation in traditional direct-conversion
receivers. With 2.5V supply, around 20dB conversion gain, 3dB DSB noise
figure, 18.3dB IIP2 and -3dB IIP3 are obtained by the BLIXER using
LNA.A over the bandwidth of 0.5 to 8GHz, while consuming 29mW DC
power. The counterpart, the BLIXER using LNA.B, achieves around 20dB
conversion gain, 4dB DSB noise figure, 38dB IIP2 and 2.8dB IIP3 over the
same bandwidth while dissipating 15mW from 2.5/1.8V supplies.
1.2 ThesisOrganization
In this thesis report only the key points of the work are presented. The
repetitive work and theories could be found in [4]. The thesis is structured
as follows. Chapter 2 covers the main concepts and theories of RF receivers
and circuits. The circuits of balun-LNAs designed in this work are
introduced in Chapter 3. Chapter 4 describes the topology and
implementations of the BLIXER. In Chapter 5, simulation results are given
followed by discussions. The conclusion is drawn in Chapter 6.
10
CHAPTER2
THEORYFORRFRECEIVERS
2
THEORYFORRFRECEIVERS
A
RF receiver accurately extracts and selectively detects a desired
signal in the presence of noise and interferers that are often several
times than the desired signal. This is done through several
operations, such as amplifying, filtering, demodulation, and analogue-todigital conversion, with adequate signal-to-noise ratio (SNR) before digital
signal processing. The received RF signal can be strong or extremely weak,
while there can be a strong blocking signal(s) with a certain offset from the
wanted frequency, which needs to be rejected. These translate into
11
requirements in terms of sensitivity, noise figure, dynamic range, and
intermodulation performance.
In a radio receiver circuit, the RF front-end is a generic term for all the
circuitry between the antenna and the first intermediate frequency (IF)
stage. It consists of all the components in the receiver that process the
signal at the original incoming radio frequency (RF), before it is converted
to a lower intermediate frequency.
In this chapter, the fundamentals of receivers are reviewed including
architectures and parameters of performance. In addition, blocks which
consist of RF front-ends are also briefly introduced.
2.1 ReceiverArchitecture
Traditional Superheterodyne receivers were the most widely used receiver
architecture because of its excellent sensitivity and selectivity. However,
the direct translation of the RF spectrum to the baseband eliminates the
need of the expensive and bulky off-chip components, and allows the
channel selection filtering to be performed by a simple on-chip low-pass
filter. Specifically, the direct conversion takes advantage from the zero
intermediate frequency (IF) since a zero IF implies that the image of the
desired signal is itself. Compared with Superheterodyne architecture,
therefore, there is no need for image rejection filters and thus circuits
become easy to implement. Furthermore, it is possible to process
subsequent signals at very low frequency with a zero IF. In addition, the
flexibility inherent in digital approaches opens the possibility for a
‘universal’ receiver, one that can accommodate many different standards
with one piece of hardware [3]. Therefore, direct-conversion approach can
provide highly integrated, low-cost, and low-power solutions for wireless
products, and has become the most actively explored architecture of
receivers. In this work the direct conversion receiver topology is used.
12
sinω0t
LNA
+
-
I
+
-
Q
Mixers
This Work
cosω0t
Figure 2.1 Block diagram of a Direct Conversion Receiver
A simple block diagram of homodyne (direct conversion) receivers is
shown in Figure 2.1. The single-end signal received by the antenna is fed to
the band-pass filter for band selection. Usually, there should be a balun [5]
made of coils, which converts the single-end signal to differential, before
the differential LNA. In this design, however, we use a topology of
wideband balun-LNA with simultaneous output balancing, noise-cancelling
and distortion-cancelling but without coils instead. The low noise amplifier
amplifies the signal, also suppressing the noise contributed by the following
stages along the signal path.
Then the differential signal is down-converted to the baseband by mixing
with 0/90˚ phase shifted local oscillator frequencies to get a correct
demodulated signal. Specifically, if the phases of RF and LO signal are
coincident or anti-coincident, the demodulated signal at maximum strength
is obtained; if the phases are quadrature, the demodulated signal is zero.,
Two mixers where quadrature LO signals are applied, therefore, are needed
in order to provide arbitrary phase relationships between RF and LO signals.
By combining the two outputs (I and Q), it is possible to obtain
demodulated signal with arbitrary input phase.
13
2.2 BasicReceiverPerformanceMatrices
2.2.1 ReceiverSensitivity
Receiver sensitivity is the minimum signal strength (Pin,min) that a receiver
is able to detect, and maintain a target bit-error-rate (BER).
,
10
10
, (2.1)
where K is the Boltzmann constant; T0 is the temperature in Kelvin; B is the
desired signal bandwidth; NFrx is the total receiver noise figure and SNRmin
is the minimum required signal to noise ratio. Since the SNRmin is
determined by modems, codec schemes and target data rates, it is apparent
that the noise figure becomes a significant item when evaluating the
sensitivity.
2.2.2 NoiseFigure
Noise Figure indicates the noise deterioration of a block. It is defined as the
ratio of input signal-to-noise ratio (SNRin) to output signal-to-noise ratio
(SNRout).
10 log
10 log ,
(2.2)
where NF and NR stand for Noise Figure and Noise Ratio, respectively.
According to the Friis’ Formula, the noise figure of a receiver can be
approximately expressed as
,
(2.3)
where NRRest is the overall noise factor of the subsequent stages of the LNA.
From the equation 2.3, it is obvious that the overall noise figure of a
receiver is primarily established by the noise figure of its first amplifying
stage. Subsequent stages have a diminishing effect on signal-to-noise ratio.
14
For this reason, the first stage amplifier in a receiver is often called the lownoise amplifier (LNA). The overall noise figure is dominated by the noise
figure of the LNA, if the gain is sufficiently high.
2.2.3 HarmonicsandIntermodulationDistortions
A nonlinear system can be approximated by a polynomial.
⋯,
(2.4)
where x denotes the input signal and y represents the output signal.
Normally, the terms for higher orders diminish, as systems are only weakly
nonlinear. So equation 2.4 can be truncated after the third-order term. Now
consider that a single sinusoid
2
is applied to the weakly
nonlinear system as described in equation 2.4, the output is
y
sin 2
sin 4
sin 6
,
(2.5)
This expression shows the harmonics distortions appear at the multiple of
the fundamental frequency, as shown in Figure 2.2. Harmonic distortions
can be reduced by filtering the output signal.
Another problem that is needed to consider is the intermodulation distortion
(IMD). If there is a second received signal, whose frequency (f1) is close to
the frequency of interest (f2), significant frequency components at f2 ± f1
(2nd –order IM) and 2f2 ± f1 (3rd –order IM), and their images are produced
by the nonlinear system, as shown in Figure 2.2.
If we see the diagram of input and output power, as shown in Figure 2.3,
the fundamental frequency has a slope of one, the 2nd –order and 3rd –order
intermodulation frequencies have slopes of two and three. In real systems,
the curves saturate before intersection due to losses and nonlinearity in the
systems. The extrapolated intersections of linear parts, however, are used as
important parameters to measure the linearity of the system. The
definitions of 2nd –order input intercept point (IIP2), 2nd –order output
15
intercept point (OIP2), 3rd –order input intercept point (IIP3) and 3rd –order
output intercept point (OIP3) are summarized in Figure 2.3.
The IMDs are not easy to be filtered as the created IM frequencies could be
very close to the desired signal, e.g. the 3rd-order IM shown in Figure 2.2.
Furthermore, in a direct conversion receiver the 2nd-order IM also becomes
problematical due to the feedthrough of mixers, which will be discussed
later.
Figure 2.2 Harmonics and Intermodulation [1]
16
IF Output
Power
OIP3
OIP2
Second-Order
IM Term
1dB
Desired
Output
Third-Order
IM Term
CP1 IIP2
IIP3
RF Input
Power
Figure 2.3 Definition of receiver linearity parameters
2.2.4 1‐dBCompressionPoint(CP1)
Under linear operation, the conversion gain (loss) of the mixer will be
constant, regardless of input RF power. If the input RF power increases by
1 dB, then the output IF power will also increase by 1dB. However, as the
RF power becomes too large, the amplification of signals is eventually
going into saturation when applying increasing input power. The 1 dB
compression point is a measure of the linearity of the receiver and is
defined as the input RF power required to increase the conversion loss by 1
dB from ideal; see Figure 2.3.
2.3 DesignIssuesforDirectConversionReceivers
2.3.1 DCOffsets
A direct conversion receiver down-converts the desired signal to zero
frequency or close to zero frequency. Therefore, a strong, nearby signal,
17
including the receiver's own LO, can mix with itself down to zero-IF (this is
known as “self-mixing”) and generate a dc level that appears as interference
at the center of the desired band. This could corrupt the signal and, more
importantly, saturate the following stages. Specifically, the gain of the
variable gain amplifier (VGA) provides very high voltage gain, e.g. 60dB.
If the DC offsets exists at the output of the mixer, it would be amplified by
the VGA and appear at the input of the ADC. As a result, this amplified
offset would saturate the ADC, thereby prohibiting the process of the
desired signal.
There are two main mechanisms of self-mixing, namely LO leakage and
interfere leakage. Figure 2.4 shows self-mixing of LO due to the finite
isolation typical of silicon-based ICs between the LO and RF ports of a
mixer. Since the LO is typically a strong signal in order to provide
sufficient drive for the mixer switching transistors, the LO can leak with
sufficiently high amplitude through these unintended paths back to the
frontend LNA. Therefore, the LO signal can reflect off the LNA output
back into the mixer RF input and mix with itself, thereby generating a static
DC level. The situation is exacerbated if the LO signal leaks back to the
LNA input and is amplified before reaching the mixer input. Likewise, as
shown in Figure 2.5, a strong nearby interferer, such as another user’s LO,
can also generate DC offsets by finding a path to the mixer LO port and
mixing with itself [18].
VGA
LNA
ADC
LO
Figure 2.4 Self-mixing of LO (LO Leakage)
18
VGA
LNA
ADC
LO
Figure 2.5 Self-mixing of interferes (Interferes Leakage)
2.3.2 I/QMismatch
Usually, the Direct Conversion Receiver requires quadrature LO
frequencies for down-conversion. A 90˚ shifted LO (Q signal) frequency
must be applied to the mixer together with a non-shifted one (I signal). The
errors in the 90˚ phase shift as well as mismatches in the amplitudes of the I
and Q LO frequencies corrupt the down-converted signal constellation,
thereby raising the bit error rate. To minimized the I/Q mismatches some
I/Q calibration techniques have been developed, as stated in [2].
2.3.3 Even‐OrderDistortion
In DCRs even-order distortion, which is normally dominated by the secondorder distortion, becomes problematic. If there are two strong interferers
close to the signal of interest, they would create a low frequency interferer
beat in the presence of the 2nd-order distortion. Ideally, this low frequency
interferer is ignorable. In reality, however, mixers always exhibit a finite
direct feedthrough from RF port to IF port, as illustrated in Figure 2.6. The
low frequency 2nd-order intermodulation would present at the IF port
without any frequency translation, thus distorting the desire signal. The
second-order nonlinearity can be characterized using ‘second intercept
point,’ IP2.
Even-order distortion can be alleviated by using fully differential circuits.
The signal taken from the antenna, however, is always single-end. Thus a
single-end to differential conversion is required. In addition, more power is
19
dissipated by differential pairs. Therefore, in direct conversion receivers an
LNA should have both good IP2 and IP3 performances.
Feedthrough
LNA
RF
IF
LO
Figure 2.6 Feedthrough from RF to IF
2.3.4 Flicker(1/ƒ)Noise
Flicker noise is inherently associated with MOS transistors with a 1/ƒ, or
pink power density spectrum. The mean-square 1/ƒ drain noise current is
given by
∙
∙ ∙∆ ,
(2.6)
where K is the process-dependent constant, W and L are channel width and
length, respectively.
The flicker noise dominates at low frequency, close to DC. Thus, it acts as
the same as the DC offsets, thereby corrupting the desired signal after
mixing. The effects of flicker noise can be reduced by applying blocks with
very large devices after the mixer since the signal after mixing operates at
low frequency. In addition, periodic offset cancellation technique that is
introduced in the section of DC offset can also suppress the flicker noise.
2.4 LowNoiseAmplifiers
Using an LNA, the effect of noise from subsequent stages of the receiving
chain is reduced by the gain of the LNA, while the noise of the LNA itself
20
is injected directly into the received signal. Thus, it is necessary for an LNA
to boost the desired signal power while adding as little noise and distortion
as possible, so that the retrieval of this signal is possible in the later stages
in the system. A good LNA has a low NF, a large enough gain and should
have large enough intermodulation and compression point (IIP2, IIP3 and
CP1). Further criteria are operating bandwidth, gain flatness and stability.
Basically, LNAs can be categorised into two configurations: commonsource (CS) and common-gate (CG), as shown in Figure 2.7. The commongate configuration is known as its robustness and simplicity. The input
impedance of the circuit is determined by the transconductance of the input
transistor, which provides possibility of wideband impedance matching.
However, a gm=20mS is required for most applications to match the input
impedance of 50 Ω. Such a gm results in high power consumption for a
given process. Although there are methods that make use of transformers to
reduce gm [3], they are not easy to achieve with on-chip coils for standard
CMOS technology due to limitation of the Q factor.
Common-source
Common-gate
RF Input
RF Input
Figure 2.7 Simple CS and CG LNA Configurations
The common-source configuration is power saving compared with the CG
configuration. It also provides much better isolation due to the small
parasitic capacitance Cgd. In addition, input matching can be achieved using
inductive degeneration. For those reasons, the CS configuration is very
popular in narrow band designs.
In this design we take advantages of both CG and CS configurations by
using an LNA topology which combining them together. That will be
discussed later.
21
2.4.1 ImpedanceMatching
In the case of a complex source impedance ZS and load impedance ZL as
shown in Figure 2.8, maximum power transfer is obtained when
∗
,
(2.7)
where * indicates the complex conjugate. Minimum reflection is obtained
when
.
(2.8)
In an LNA, the input impedance matching is important. For instance, the
frequency response of the antenna filter that precedes the LNA will deviate
from its normal operation if there are reflections from the LNA back to the
filter. Furthermore, undesirable reflections from the LNA back to the
antenna must also be avoided. The quality of the termination is defined by
the reflection coefficient (Γ).
(2.9)
Usually, the performance of the impedance matching is measured by S11
parameter.
Zs = Rs + jXs
+
Vs
ZL = RL + jXL
‐
Figure 2.8 Simple network for impedance matching
22
2.4.2 Noise
2.4.2.1 Thermalnoiseofresistors
The thermal noise of a resistor can be modelled as a voltage noise source in
series with a noiseless resistor, as displayed in Figure 2.9.
Vn 2
+
R
Figure 2.9 Example of resistor thermal noise model
The noise power of the voltage source is
4
∆ ,
(2.10)
where K is Boltzmann’s constant, T is the absolute temperature in kelvins,
and Δf is the noise bandwidth in hertz.
2.4.2.2 DrainCurrentNoiseinMOSFETs
The drain current noise in MOSFETs is commonly modelled as current
source across the drain and source in shunt with the transconductor of the
transistor. The noise has a power given by
4
∆ ,
(2.11)
2.4.2.3 OtherNoiseSources
There are a lot of noise sources in MOSFETs, for instance, shot noise
popcorn noise as well as the flicker noise described in 2.3.4.
2.4.2.4 NoiseFigure
The noise factor of an LNA is defined as
23
.
(2.12)
(2.13)
The noise figure is defined as
10 log
2.4.3 Linearity
As illustrated in section 2.2.3, there would be harmonics and interferes
during the receiving operation. An LNA must not only simply amplify
signals without adding much noise, but also remain linear even when strong
signals are being received. The parameters that are most commonly used to
measure the linearity of an LNA are IP3 and CP1. Due the even order
distortion issue in DCR, IP2 is also needed to take into consideration.
2.5 Mixers
In a RF front-end the mixer receives the signal from the LNA and mixes it
with the signal from a local oscillator to convert the signal to a lower
frequency called intermediate frequency.
2.5.1 ConversionGain(Loss)
The conversion gain of a mixer is defined as the ratio of the desired IF
output to the value of the RF input.
2.5.2 NoiseFigure
Noise Figure is defined as
10 log
10 log
.
(2.14)
Two representation of noise figure are used, namely single-sideband (SSB)
NF and double-sideband (DSB) NF. When the desired signal only resides at
one frequency, SSB NF is used to measure the performance of a mixer. In
24
cases where desired signals are found in both sidebands of the input, the
DSB NF is applicable.
It is obvious that the SSB NF will be normally 3dB greater than the DSB
NF, since both have the same IF noise but the former has signal power in
only a single sideband.
2.5.3 LinearityandIsolation
Since a mixer cannot be absolutely linear, it also suffers from the problems
of harmonics and intermodulation. The parameters, IP3 and CP1, described
in section 2.2.3 can be used to measure the linearity of a mixer as well.
Another problem for a mixer is isolation. As discussed in 2.3.1 and 2.3.3, if
there are leakages among the three ports of a mixer, signals will mix with
itself or feedthrough, causing DC offsets or even-order distortions, thus
degrading the performances of a down-conversion receiver. Unfortunately,
there will always be some small amount of power leakage among the RF,
LO and IF ports. The isolation is usually measured by the S12 parameter.
Typically, 25-35dB, 20-30dB and 25-35dB isolation is required for LO to
RF, LO to IF and RF to IF, respectively.
2.5.4 Double‐BalancedMixer
Figure 2.10 shows a typical double-balanced mixer. The transistors driven
by LO signals switch alternatively to form a multiplication function,
multiplying the linear RF signal current from with the LO signal. The
circuit in Figure 2.10 consists of two single-balanced mixers that are
connected in antiparallel. Consequently, this type of mixer provides a high
degree of LO-IF isolation by summing the LO to zero at output. Typically,
40-60dB of LO-IF isolation is achievable. On the other hand, since the
switches are driven by the LO signal, vLO must be chosen large enough.
25
IF Out
VLO+
VLO-
IDC+IRFcosωRFt
VLO+
IDC-IRFcosωRFt
Figure 2.10 Double-balanced mixer
26
CHAPTER3
WIDEBANDNOISECANCELLINGBALUN‐
LNAS
3
WIDEBANDNOISECANCELLING
BALUN‐LNAS
T
he rapid downscaling of CMOS technology has led to more
compact and faster RF circuits. Application examples are Bluetooth
standard (2.4, 3.6 and 5 GHz) and satellite (0.95-2.15GHz). A
wideband LNA can replace several LC-tuned LNAs typically used in
multiband and multimode narrow-band receivers, improving chip area
effectiveness and fitting better with the trend towards flexible radios with as
27
much signal processing as possible in the digital domain (toward “software
defined radio”) [16]. There are two key challenges associated with
wideband LNAs: 1) the broadband characteristic, i.e., relatively flat gain,
low noise figure (NF) and impedance matching over the covered frequency
band; 2) the linearity. A high linearity is essential to minimize unwanted
mixing of in-band blockers, which can consume much more power than the
desired frequency.
In addition, differential signal is preferred in the receiving chain to reduce
2nd –order distortion and to reject power supply and substrate noise. The
signal received from the antenna, however, is always single-end. Therefore,
it is inevitable to convert the single-end signal into differential before the
LNA. Off-chip baluns with low losses are typically solution for narrowband
applications, which calls for several off-chip devices in case of wideband
operation. On the other hand, wideband passive baluns typically have high
loss, degrading the overall NF of a receiver significantly [11].
Recent works on wideband low noise amplifiers based on single-todifferential (S-to-D) topology [9][10] with noise cancelling scheme have
shown reliable RF performances such as output balancing, moderate noise
figure, high linearity and broadband input matching. In this chapter, two
wideband Balun-LNAs using the S-to-D topology designed in 65nm CMOS
technology are going to be introduced followed by in-depth discussion of
each performance.
3.1 Topology
3.1.1 OutputBalancing(BalunOperation)
The S-to-D topology serves as a useful single ended to differential
converter, which takes input from the antenna and drives the differential
inputs of the mixer. It combines a common gate (CG) stage and a common
source (CS) stage, as shown in Figure 3.1. The CG stage provides wideband
input matching and an in-phase gain
28
,
∙
,
.
(3.1)
where gm,CG represents the transconductance of the common-gate stage.
While the CS stage provides an anti-phase gain
,
,
∙
. (3.2)
When the gains of the two stages are equal the functionality of a balun is
realized.
Vn,CG
RCG
RCS
+
gmCG
VOUT
Vn,CS
-
in
gmCS
Vn,in
RS
Vin
VS
IBIAS
Figure 3.1 The basic common-gate-common-source single-to-differential topology
3.1.2 NoiseCancelling
It is well known that the CG amplifier presents a high noise figure, which is
usually greater than 3dB due to the impedance matching and a gm of 20mS.
This topology addresses the problem by using a properly designed CS stage
to cancel the noise of the CG transistor, which dominates in the CG stage.
As shown in Figure 3.1 where solid and dashed lines represent signals and
noise, respectively, the noise current due to the CG transistor generates an
29
in-phase noise voltage on the source resistor (vn,in) and an amplified antiphase noise voltage across RCG (vn,CG).
,
∙
,
,
. (3.3)
The CS stage also amplifies the noise voltage (vn,in) leading to an anti-phase
noise voltage (vn,CS), which is fully correlated with vn,CG, across RCS.
,
,
∙
,
.
(3.4)
For equal CS and CG gain, the noise due to CG transistor is fully cancelled
by differential sensing.
3.1.3 Transconductance‐Scaling
According the previous work [11], there are three main configurations to
implement the balun-LNA, as follows.
1) The transconductance of the CS and CG transistors are equal and the
load resistors are equal, too. In this situation, gmCG=gmCS and RCG=RCS.
2) The gm of CS stage is scaled up n times while keeping that of CG not
changed. The loads are kept equal, therefore, gmCS=n · gmCG and RCG=RCS.
3) The gm of CS stage is n times bigger than that of CG, however, the load
resistor of CS stage is n times smaller than the load of CG stage, leading to
gmCS=n · gmCG and RCS=n · RCG.
Figure 3.2 [11] displays the noise figure, voltage gain (Av) and gain
imbalance (ΔAv) versus the scaling factor n for the three configurations.
Configuration 1) fails to achieve low noise though the noise of CG is
cancelled. One of the reasons is that this configuration cannot provide high
GBW since the transconductance of the two transistors are fixed to 20mS
for input matching. Thus, in wideband applications, there is not enough
gain to suppress the noise. Another reason is the noise from CS stage
becomes significant due to its low gm (≈1/Rs) and is magnified by the
voltage division of ½ by Rs and Rin. However, this configuration is still
30
attractive due to its equal DC level at the output. A gain-boosting scheme is
invented to overcome the problem of gain and noise, which will be
introduced in section 3.3.
Configuration 2) provides decreasing NF and growing voltage gain when
the factor n increases. Although the noise of CG is not fully cancelled, the
configuration takes advantage of increased transconductance of the CS
stage, suppressing the total noise figure. The gain imbalance, however, is
unacceptable.
Configuration 3) shows an even faster decrease gain of NF with increasing
n. this is because the noise of CS transistor shrinks and the gain and gain
imbalance remain constant with respect to n. In this case, due to the fully
cancelled noise of CG transistor and increased transconductance of CS
transistor, it is possible to obtain a NF below 2dB with a big n value. In
addition, the gain and gain imbalance maintain at a constant level with
respect of n. For the advantages above, this configuration is used to design
one of the LNAs in this work (LNA.A).
31
Figure 3.2 Noise Figure (NF), voltage gain (Av) and gain imbalance (ΔAv) versus
impedance scaling factor ‘n’ for three different cases [11]
3.1.4 DistortionCancelling
Not only the noise, but also the distortion of CG transistor is cancelled,
providing remarkably enhanced IIP2 and IIP3 for the LNAs.
Figure 3.3 shows the small signal equivalent circuit of the CG stage of the
LNA. Weakly nonlinear behaviour is assumed and distortion is assumed to
originate only from the nonlinear memory-less voltage to current
conversion of the matching device. Using a Taylor approximation, the
nonlinear voltage (vin) generated by the signal source (vs) via RS can be
written as
∙
32
.
(3.5)
where α1 represents the first Taylor coefficients and vNL represents all the
nonlinear terms.
vout,CG
ids,CG
Rs
RCG
vin
iin
vs
Figure 3.3 Small signal equivalent circuits of the CG stage
Obviously, the output
,
∙
∙
1
∙
∙
.
(3.6)
Using the discussion in 3.1.1 and assuming the input impedance is perfectly
matched (RS=1/gm,CG), we obtain
,
∙
∙
∙
.
(3.7)
As a result, the nonlinearity of the CG stage is subtracted by the differential
sensing of the output,
,
,
∙
.
(3.8)
Therefore, the distortion caused by the CS stage dominates in this kind of
circuits. Unfortunately, high linearity is only available in a very small range
of Vgs of the CS transistor. The stability of the IIP2, however, becomes a
problem. In practical implementation, the IIP2 of this topology is also
relatively sensitive to components mismatches.
33
One way to improve the stability of IIP2 is to adopt a differential current
balancer (DCB) [12], consisting of cascaded amplifiers and cross-coupled
capacitors, as the DCB shown in Figure 3.5. However, the current balancer
cannot be employed on gm-scaled circuits since the DCB requires equal
output resistance of the cascaded transistors to cancel imbalances. But this
is not possible for a scaled circuit.
3.2 Scaled‐gmBalun‐LNA(LNA.A)
Figure 3.4 depicts the schematic of the Inducotrless Scaled-gm NoiseCancelling Balun-LNA (LNA.A). It employs the S-to-D conversion
described in 3.1. In LNA.A, configuration 3) described in 3.1.3 is used.
Both of the CG and CS stages are cascaded to provide better isolation
leading to higher voltage gain. M1 and M3 have the same gm as normal
cascade configurations, and so do M2 and M4. The CG stage is biased using
a resistor (RBIAS) to avoid internal or external inductors. And the resistor can
also provide a bias voltage to M2.
2.5V
R1
R2
+ VOUT -
VB2
M3
VB1
VB3
M4
M1
Rs=50
VS
Lbond
M2
RBIAS
CEXT
Figure 3.4 Inducotrless Scaled-gm Noise-Cancelling Balun-LNA (LNA.A)
34
3.2.1 InputMatching
As discussed in 2.4, the input impedance of CG configuration is 1/gm over a
large range of frequency bandwidth. In this circuit, a bias resistor RBIAS is
connected in parallel with the CG transistor to provide DC current path for
the CG transistor, so that the total input impedance becomes
//
.
(3.9)
RBIAS needs to be large to avoid affecting impedance and gain much; on the
other hand, it cannot be too large, which consumes a lot of power.
Typically, 350-500Ω is acceptable.
An external capacitor (CEXT) is adopted to form a π-network, which helps to
provide a broad input matching, together with the input bondwire
inductance and the input capacitance. Depending on the application and
requirement the CEXT can be removed and the input matching would only be
degraded by a few dB.
3.2.2 GainandNoiseFigure
The gain of the LNA is the differential of CS and CG stages.
,
(3.10)
Where gm1 and gm2 are the transconductance of M1 and M2, respectively.
To simplify the calculation of NF, only the thermal noise of the source and
load resistor and of the CG transistors is taken into account assuming γ=
2/3, which is known to be optimistic for short channel devices. To begin
with, the noise power generated by the source resistor at the output is given
by
,
4
∙
35
∙
.
(3.11)
The CG transistor generates a current noise source which can be converted
into a voltage noise at the input of the CG and CS stages, namely
can be expressed as
.
,
,
,
(3.12)
This noise voltage will be amplified by the CG stage, then generating a
voltage noise power (
,
) via the load resistor R1. This noise is given by
As the noise
4
,
∙
.
(3.13)
is at the input of both CG and CS stages, it will also be
,
amplified by the CS stage, leading to a noise (
CS stage (R2). This noise is expressed as
∙
,
Finally, the noise power (
,
) via the load resistor of
. (3.14)
) caused by the load resistors is given by
,
,
4
. (3.15)
Using equation 2.11 and assuming Rin=1/gm1, it is easy to calculate the
noise factor of the circuit:
,
,
,
,
,
1
∙
∙
, (3.16)
where the second, third and fourth term of NR account for noise of M1, M2
and load resistors, respectively.
36
When the input impedance is matched to Rs, 3.16 can be written as
1
,
(3.17)
3.3 Gain‐BoostingCurrent‐BalancingEqual‐gmBalun‐
LNA(LNA.B)
Figure 3.5 shows the schematic of the gain-boosting current-balancing
equal-gm Balun-LNA. It consists of an S-to-D amplifier, an inverter based
gain-boosting amplifier (gmx) and a differential current balancer (DCB).
2.5V
R1
R2
+ VOUT VB2
DCB
M8
M7
C6
C5
VB1
1.8V
M5
M4
M6
C3
C4
vo1p
M3
gmx
vo1n
X
M1
C2
RS = 50
VIN
VS
C1
gmx
M2
LEXT
Figure 3.5 Gain-Boosting Current-Balancing Equal-gm Balun-LNA (LNA.B)
The S-to-D amplifier achieves output balancing while realizing wideband
input impedance matching. Unlike the S-to-D topology of LNA.A, this
37
amplifier applies equal biased and sized transistors (equal gm) for both
common gate and common source stages, leading to better linearity.
The DCB, which corrects the errors of the two branches, can be applied on
this topology. It can be treated as a current controlled current source with
unity gain, offering the desired differential balancing inherently. Using the
double cascaded amplifiers (M5-M8) with cross-coupled capacitors (C3-C6),
the DCB significantly increases the precision of outputs balancing. The
final differential imbalance should be just the residual of the original error
so that distortions can be minimized. Moreover, the DCB improves the
balun-LNA’s reverse isolation and linearity by lowering the swing at vo1p
and vo1n, where distortion arising from the nonlinear output resistance of
M1-M4
The extra gmx can be seen as an amplifier with transconductance of gmx. It
enhances the gain of the circuit, helps to achieve good input matching and
self-biases M1 and M2 simultaneously.
The circuit works as follows. The common source stage composed of gmx
and M2 generates an anti-phase output signal at point X. Assuming that the
signal at X is –A · vin, vout+ is given by
∙
∙
∙
∙ 1
∙
∙
. (3.18)
The gain is boosted by this scheme and the noise and input resistance are
reduced. Moreover, the negative output is given by
∙
∙
∙
∙
∙
∙
.
∙
(3.19)
Thus, in order to balance the outputs,
should be satisfied.
38
(3.20)
An external inductor is used to achieve a wideband impedance matching.
The input resistance of the circuit is
.
(3.21)
When gm1=gm2 and R1=R2=R, the voltage gain can be written as
2∙
∙
(3.22)
Similarly to the calculation for LNA.A, when assuming Gm1·Rs=1, the noise
factor with respect to Rs becomes
1
, (3.23)
where the second, third and fourth term account for M1, M2 and load
resistors noise. The γ is assumed 2/3.
39
CHAPTER4
THEBLIXERS
4
THEBLIXERS
T
he software defined radio (SDR) and ultra-wideband technique has
become increasingly popular. The rapid development of these kinds
of applications demands receivers operating over a large range of
bandwidth, i.e. up to 6GHz for SDR or 10GHz for UWB. The bandwidth,
however, is limited in traditional receivers. Specifically, active mixers have
capacitance input impedance due to the gate-source parasitic capacitance.
When a passive mixer is used, a voltage buffer or transconductance stage,
which also loads the LNA capacitively, is often required between the LNA
output and the input of mixer(s). The so-called BLIXER topology based on
40
the LNAs described in Chapter 3 resolves the bandwidth problem by
lowering the impedance at RF nodes. In this chapter, the implementation of
these circuits is introduced and analysed.
4.1 TheBasicBLIXERTopology
Figure 4.1 shows the basic BLIXER Topology consisting of the balun-LNA
core of Figure 3.1 with a cascaded double-balanced mixer which has been
shown in Figure 2.10. The balun-LNA core is applied to provide input
matching, single-end to differential conversion and amplification. The
circuit also perform noise cancelling and distortion cancelling, but at IF
outputs instead since the switching transistors are driven by the LO signals.
RF signals only appear at three nodes: the input and the drains of the two
amplifying transistors, implying only the impedance of these three nodes
limits the RF bandwidth. If these three nodes are loaded with low
impedance, high bandwidth is achievable. For input matching, the input is
loaded with 50Ω. Moreover, the impedance at drains of M1 and M2 equal
1/gm of mixer transistors, which are similar to that of the amplifying
transistor. Thus, the impedance at all the RF nodes is equal to or lower than
50Ω, allowing for high bandwidth. If only the gate-source capacitance of
transistors is taken into account, the RF bandwidth of the BIXER is limited
by the fT of the switching transistors. fT is given by
,
,
,
(4.1)
which is typically an order of magnitude higher than that of the balun-LNA
with a voltage gain in the order of 20dB [17].
Moreover, the power efficiency of the BLIXER is also attractive since the
mixer re-uses the current of the LNA, allowing for high conversion gain is
available without dissipating a lot of power.
41
Load
Load
IF Out
VLO+
M3
M4
M5
M6
VLO-
Double-Balanced
Mixer
Balun-LNA
Core
gmCG ·vrf
gmCS ·vrf
M1
RS = 50
VS
M2
IBIAS
Figure 4.1 Basic BLIXER topology consisting of the balun-LNA core of Figure 3.1 with
cascaded double-balanced mixer
4.2 TheI/Q‐BLIXERImplementations
4.2.1 I/Q‐BLIXERusingLNA.A
As discussed in 2.1, quadrature LO signals are required for down
conversion receivers. In the I/Q-BLIXER, two double balanced mixers in
parallel are employed. Figure 4.2 shows a completed schematic of I/QBLIXER using LNA.A driven by LO waveforms with 25% duty cycle. The
LNA is slightly modified compared with that is shown in section 3.2. The
bias resistor RBIAS is replaced by a RF choke LBIAS and moved off chip.
This RF choke not only provides the path for DC current of CG stage, but
also helps improve the input impedance matching at low frequency. An off
42
chip capacitor is also applied to form a π-network together with the
bonding wire which can be modeled as inductor of 1~2nH.
The cascaded transistors are replaced by the mixers’ switching transistors
which are driven by the LO signals. Due to the application of quadrature
LO signals, which has been explained in 2.1, two double-balanced mixers
are used with parallel connection.
The LO signals applied to the mixers are square waveform with 25% duty
cycle, as shown in Figure 4.3, making the voltage gain at IF of the I/QBLIXER is
,
√
∙
,
.
√
∙
∙
(4.2)
where √2/π equals the fundamental Fourier component of a 25% duty
cycle LO signal.
There is a reduction of 7dB for the voltage gain due to the factor of √2/π.
However, the DC voltage drop across the load resistors is
∙
∙
∙
(4.3)
since the CG and CS DC current flow through each load for only ¼ period
with 25% duty cycle LO signals. This provides the opportunity to increase
the load resistor to compensate the gain reduction. If the load resistors are
doubled, extra 6dB voltage gain is obtained, consequently, only 1dB lower
than that of the balun-LNA.
As the LNA.A uses the scaled-gm topology, which means
∙
.
(4.4)
Consider when VLO I+ is high, there are two current paths from supply to
ground, which are R1-R2-M3-M1 and R3-M4-M2. The load for the CG stage
is R1+R2 and that for CS stage is R3. In order to get the same gain for both
43
CG and CS stages, the loads need to be divided into two parts, as shown in
Figure 4.2.
∙
(4.5)
should be satisfied. In this design, we set R1=R3=R5=R7=R/n and
R1+R2=R3+R4=R5+R6=R7+R8=R, so that all the IF outputs are well
balanced.
2.5V
R1
n·R
IF I+
R
R2
C1
R3
C3
(n-1)·C
C5
R5
R7
C7
C2
R4
C4
C
C6
R6
R8
C8
IF IW
W
W
n·W
VLO I+
M3
M4
VLO IM5
IF Q-
IF Q+
W
n·W
VLO Q+
M6
M7
M8
VLO QM9
M10
VB,CS
VB,CG
M1 gm1˜ 20mS
RS = 50
VS
CEXT
Lbond
M2 gm2=n·gm1
LBIAS
Figure 4.2 I/Q-BLIXER using LNA.A driven by LO waveforms with 25% duty cycle
44
VLO Q+
VLO Q-
VLO I+
VLO I-
Figure 4.3 25% duty cycle LO waveforms
4.2.2 I/Q‐BLIXERusingLNA.B
Figure 4.4 shows the I/Q-BLIXER using LNA.B driven by LO waveforms
with 25% duty cycle. The LNA core is the one described in section 3.3.
Two double-balanced mixers are inserted between the loads and the double
current balancer.
As the LNA.B employs equal gm amplifying transistors, the load resistors
and capacitors are kept equal, so that there is no need to split them.
The same 25% duty cycle square wave LO signals, which is shown in
Figure 4.3, are applied to the mixers’ transistors. Thus, the voltage gain is
given by
,
√
∙
,
.
√
∙2∙
∙
.(4.6)
Though 7dB is lost due to the factor of √2/π, we can double the load
resistors to compensate it as described in the previous section.
45
2.5V
C
R
R
R1
IF I+
C
R2
C
IF I-
M7
M8
M9
R3
IF Q+
VLO I-
VLO I+
R
R
C
R4
IF Q-
VLO Q-
VLO Q+
M10
M11
M12
M13
M14
VB2
M6
M5
C5
C6
VB1
M3
M4
C3
C4
X
M1
1.8V
C2
M4
Rf
M3
RS = 50
VS
VIN
Cext
Lbond
C1
M2
LEXT
Figure 4.4 I/Q-BLIXER using LNA.B driven by LO waveforms with 25% duty cycle
46
CHAPTER5
SIMULATIONRESULTS
5
SIMULATIONRESULTS
5.1 SimulationResultsforLNA.A
5.1.1 Gain,NoiseFigure,InputMatchingandDCPower
Consumption
The circuits of LNAs have been designed in 65nm COMS technology and
simulated with 50fF capacitive loads in the frequency range between
600MHz and 5GHz. Parameters of the circuits are shown in Table 5.1. The
47
LNA.A was simulated with CS transistor of 90μm width to compare the
performance to LNA.B.
W1/L(μm)
W2/L(μm)
W3/L(μm)
W4/L(μm)
LNA.A
66/0.06
90/0.06
LNA.B
26/0.06
26/0.06
10/0.06
5/0.06
gm1(mS)
gm2(mS)
gm3(mS)
gm4(mS)
LNA.A
21.8
59.7
LNA.B
17
17
8.3
3.2
Table 5.1 Parameters of the LNAs
The red curves in Figure 5.1 show the gain, noise figure and the S11
parameter of the LNA.A and the blue curves are for LNA.B. A voltage gain
greater than 20dB is obtained for LNA.A up to 5GHz and a noise figure
below 3dB is achievable up to 4GHz. The noise figure can be suppressed
by enhancing the gain, however, a trade-off among power consumption,
gain and bandwidth is always needed to take into consideration. In addition,
S11 parameter is below -12dB, which provides good enough input
matching.
The LNA consumes 10mA current from a 2.5V supply. The CG stage takes
2.5mA and the CS stage take 7.5mA since the transconductance of the CS
transistor is set 3 times (~60mS) as that of the CG transistor.
48
Figure 5.1 Simulation Results of the two LNAs
5.1.2 Linearity
Two sinusoidal tones located at 2.4 / 2.41GHz are chosen to simulate the
linearity of the circuits. The LNA.A achieves 31dB for IIP2 and -2.1dB for
IIP3; see Figure 5.2 and Figure 5.3.
49
Figure 5.2 IIP2 simulation of LNA.A
Figure 5.3 IIP3 simulation of LNA.A
Linearity simulations with two tone signals with 10MHz space from 0.5 to
6GHz are also implemented, as shown in Figure 5.4. As all the transistor
dimensions and biases are optimized for 2.4GHz application, the LNA
achieves the best IIP2 performance at 2.4GHz; nevertheless, the IIP2 is still
above 20dB up to 3.5GHz.
50
40
dB
30
20
10
IIP2
0
IIP3
-10
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Frequency/GHz
Figure 5.4 IIP2 and IIP3 versus input RF frequency for LNA.A
5.2 SimulationResultsforLNA.B
5.2.1 Gain,NoiseFigure,InputMatchingandDCPower
Consumption
The blue dotted curves in Figure 5.1 show the voltage gain, noise figure and
the S11 parameter of the LNA.B. A voltage gain greater than 22dB is
obtained up to 5GHz and a noise figure below 3dB is achievable also over
this bandwidth. The S11 parameter is below -12dB.
The two circuits of LNA.A and LNA.B achieve almost the same NF, close
or less than 3dB; however, the gain of LNA.B is higher. That implies that
LNA.B requires higher gain to suppress the noise figure as discussed in
3.1.3.
The LNA.B dissipates 17mW from 2.5V/1.8V supplies. Each branch takes
3mA from 2.5V; and the gmx consumes 1.5mA from 1.8V supply voltage.
5.2.2 Linearity
The same two sinusoidal tones, which locate at 2.4 / 2.41GHz, are taken to
simulate the linearity. The LNA.B, which benefits from the equal sized and
51
biased transistors as well as the current-balancing scheme, shows 40dB and
5.8dB for IIP2 and IIP3, respectively; see Figure 5.5 and Figure 5.6.
Figure 5.5 IIP2 simulation of LNA.B
Figure 5.6 IIP3 simulation of LNA.B
Linearity simulations with two tone signals with 10MHz space from 0.5 to
6GHz are also implemented, as shown in Figure 5.7 and Figure 5.4. As all
52
the transistor dimensions and biases are optimized for 2.4GHz application,
the LNA achieves the best IIP2 performance at 2.4GHz; nevertheless, the
IIP2 is still above 30dB up to 6GHz.
50
40
dB
30
IP2
20
IP3
10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Frequency/GHz
Figure 5.7 IIP2 and IIP3 versus input RF frequency for LNA.B
5.3 IIP2Analysis
Components mismatches may cause variation of IIP2. In this section, the
IIP2 against components mismatches and Vgs of the CS transistor are
analysed.
Another circuits using topology of LNA.A but with 250μm CS transistor,
which achieves the same IIP2 and power consumption as the 90μm one,
was simulated to find out the effects on IIP2 due to components
mismatches. In order to test this, the circuits are simulated by Monte Carlo
analysis. We present, in Figure 5.8, the IIP2 result of a 200-points,
mismatch only, Monte Carlo simulation of LNA.A with dimension of
90/0.06μm CS transistor which is biased by a fixed voltage. The average
IIP2 of this circuit is 28.3dB; however, only 83.5% of the IIP2 are greater
than 25dB, implying the IIP2 is very sensitive to components mismatches.
Figure 5.9 shows the stability of IIP2 is improved by replacing the CS
transistor by a larger one (250/0.06μm). The IIP2 greater than 25dB
53
account for 96% of total runs. This is because mismatch is always an
absolute value, not a percentage of the parameters’ value. So a large
transistor is less sensitive to mismatches than a small one. According to the
equation
∙
∙
.
(5.1)
The mismatch on W causes a small change on Id, and then results in
imbalance at outputs, thus deteriorating the linearity. Consequently, the
250μm transistor has less mismatch, leading to stable IIP2.The LNA.B,
which benefits from the DCB, provides stable IIP2 even though the
dimension of transistors is small, as shown in Figure 5.10. The IIP2 greater
than 35dB occupy 92.5% among total runs.
Figure 5.8 Monte Carlo analyse of IIP2, LNA.A, W2=90μm
54
Figure 5.9 Monte Carlo analyse of IIP2, LNA.A, W2=250μm
Figure 5.10 Monte Carlo analyse of IIP2, LNA.B
Another way to emulate the effects of matching is to vary the bias voltage
of the CS stage since the distortions of the CS stage dominates the output
distortion. To tune the bias voltage of the CS transistor is helpful to find an
optimized bias point for linearity. Figure 5.11 compares the simulated IIP2
55
sensitivity with respect to Vgs of CS stages. It can be seen that the LNA.B
has the widest window of IIP2, verifying that the DCB does help to
improve the IIP2 as well as the stability.
Figure 5.11 Vgs of CS stagesVS IIP2
5.4 SimulationResultsforI/Q‐BLIXERusingLNA.A
5.4.1 ConversionGain,InputMatchingandNoiseFigure
The measured voltage conversion gain from RF port to IF port is 20.5dB at
IF bandwidth of 500MHz when input frequency is 2.4GHz, as shown in
Figure 5.12. The DSB Noise Figure of the I/Q-BLIXER at 2.4GHz LO
frequency is 2.7dB and the SSB NF is 5.7dB; see Figure 5.13.
56
Figure 5.12 Conversion gain of BLIXER using LNA.A for fIF=500MHz
NFSSB
NFDSB
Figure 5.13 Noise Figure of BLIXER using LNA.A for fIF=500MHz
The S11 parameter is below -14dB between 500MHz and 8GHz; see Figure
5.14
57
Figure 5.14 S11 parameter simulation for the BLIXER using LNA.A
Figure 5.15 shows the wideband RF performance of the BLIXER. The
conversion gain remains flat within 1.5dB up to 8GHz at 50MHz IF
frequency. From 0.5-8GHz, the double sideband noise figure and the single
sideband noise figure are below 3.23dB and 6.18dB, respectively, using a
fixed IF of 50MHz.
58
Conversion Gain
NF(DSB)
NF(SSB)
25
20
15
dB
fIF = 50MHz
10
5
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
RF frequency/GHz
Figure 5.15 Conversion gain (GC), NFSSB and NFDSB of the I/Q-BLIXER using LNA.A
5.4.2 Linearity
Two tones at 5.2GHz and 5.7GHz, which represents two IEEE 802.11a
interferers, are used to test the IP3 performance. Using an LO frequency of
4.6GHz, the 3rd –order intermodulation product locates at 100MHz. the
simulated IIP3 is -3dB, as shown in Figure 5.16.
59
Figure 5.16 IIP3 simulation for BLIXER using LNA.A
The IIP2 equals 18.3dB using 2.4GHz (802.11b/g) and 5.7GHz (802.11a)
input tones and LO of 3.2GHz; see Figure 5.17. In addition, 5.7GHz and
5.8GHz signals (two 802.11a interferes) are taken to simulate the
intermodulation for tones that leak through the mixer. The intermodulation
product at 100MHz shows IIP2s greater than 30dB, regardless of the LO
frequency.
60
Figure 5.17 IIP2 simulation for BLIXER using LNA.A
5.5 SimulationResultsforI/QBLIXERusingLNA.B
5.5.1 ConversionGain,InputMatchingandNoiseFigure
The measured voltage conversion gain from RF port to IF port is 20.22dB
at IF bandwidth of 500MHz when input frequency is 2.4GHz, as shown in
Figure 5.18. The DSB Noise Figure of the I/Q-BLIXER at 2.4GHz LO
frequency is 3.4dB and the SSB NF is 6.4dB; see Figure 5.19. The noise is
higher than that of the BLIXER using LNA.A. This is due to the noise of
the CS stage as stated in section 3.1.3. In addition, Figure 5.20 shows the
S11 parameter is below -10dB up to 8GHz.
61
Figure 5.18 Conversion gain of BLIXER using LNA.B for fIF=500MHz
SSB
DSB
Figure 5.19 Noise Figure of BLIXER using LNA.B for fIF=500MHz
62
Figure 5.20 S11 parameter simulation for the BLIXER using LNA.B
Figure 5.21 shows the conversion gain, DSB NF and SSB NF against the
input RF frequency with a fixed IF frequency of 50MHz. The conversion
gain remains flat within 1.5dB up to 8GHz and the NFDSB is below 4.2dB
over this bandwidth.
63
Conversion Gain
NF DSB
NF SSB
25
20
15
dB
fIF = 50MHz
10
5
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
RF Frequency / GHz
Figure 5.21 Conversion gain (GC), NFSSB and NFDSB of the I/Q-BLIXER using LNA.B
5.5.2 Linearity
The same tones used to simulate the linearity of the BLIXER using LNA.A
are used here to test the IIP2 and IIP3 of the BLIXER using LNA.B. Two
tones at 5.2GHz and 5.7GHz with LO frequency of 4.6GHz give the IIP3 of
2.8dB; see Figure 5.22. The IIP2 equals 38dB using 2.4GHz and 5.7GHz
input tones and LO of 3.2GHz; see Figure 5.23. Also, 5.7GHz and 5.8GHz
signals show IIP2s greater than 40dB, regardless of the LO frequency.
64
Figure 5.22 IIP3 simulation for BLIXER using LNA.B
Figure 5.23 IIP2 simulation for BLIXER using LNA.B
65
5.6 PerformancesSummary
Table 5.2 lists the obtained performances of the designed BLIXERs using
the balun-LNA cores in this work.
Process
Supply Voltage
Bandwidth
Voltage
Conversion Gain
Noise Figure
(DSB)
Noise Figure
(SSB)
S11
IIP2
IIP3
DC Power
BLIXER using LNA.A
STMicroelectronics 65nm
CMOS
2.5V
0.5-8GHz
BLIXER using LNA.B
STMicroelectronics 65nm
CMOS
2.5/1.8V
0.5-8GHz
>19.6dB
>18.8dB
<3.2dB
<4.2dB
<6.2dB
<7.2dB
<-12dB
18.3dBm
-3dBm
29mW
<-9dB
37dBm
2.8dBm
15mW
Table 5.2 Performances summary of the BLIXERs
66
CHAPTER6
CONCLUSIONS
6
CONCLUSIONS
6.1 Conclusions
Two wideband balun-LNAs have been designed in STMicroelectronics
65nm COMS technology. Both of them employ a single-end-to-differential
conversion topology composed of a common gate (CG) amplifying stage
and a common source (CS) stage, providing output balancing and noise and
distortion cancelling. One uses transconductance-scaling technique and the
other one exploits gain-boosting current-balancing topology. With 2.5V and
67
2.5V/1.8V supplies the LNAs achieve voltage gains of 24.5dB and 22.8dB,
noise figures of below or close to 3dB, IIP2 of 31dB and 41.8dB,
respectively. The gain-boosting current-balancing Balun-LNA (LNA.B)
with equal transconductance and DCB provides better IP2 performance,
both the IIP2 and stability, with small transistors, but suffers the problem of
noise figure due to the noise from CS stage. The unequal-gm topology has
better noise performance but unstable IIP2 if the CS transistor is not wide
enough. To get stable IIP2, large transistors are required but that calls for
more area. In addition, it consumes more power than the equal-gm LNA.
Balun-LNA I/Q-mixers, which combine the balun-LNA cores and doublebalanced mixers, are also designed in the same CMOS technology to
resolve the bandwidth limitation in traditional direct-conversion receivers.
With 2.5V supply, around 20dB conversion gain, 3dB DSB noise figure,
18.3dB IIP2 and -3dB IIP3 are obtained by the BLIXER using LNA.A over
the bandwidth of 0.5 to 8GHz, while consuming 29mW DC power. The
counterpart, the BLIXER using LNA.B, achieves around 20dB conversion
gain, 4dB DSB noise figure, 38dB IIP2 and 2.8dB IIP3 over the same
bandwidth while dissipating 15mW from 2.5/1.8V supplies.
6.2 Futurework
The BLIXER topology greatly improves the operating bandwidth of
receivers, however, the conversion gain is limited as the current reused
double-balanced mixer does not provide any gain. Future work can be done
by connecting an active mixer to the any of the balun-LNAs and try to
enhance the voltage conversion gain and minimize the noise figure as much
as possible for applications which do not require very high bandwidth.
68
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69
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[11] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B.
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[12] P. Mak and R. Martins, “A 0.46mm2 4dB-NF Unified Receiver FrontEnd for Full-Band Mobile TV in 65nm CMOS,” IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, pp. 172-174, Feburary.2011.
[13] M. A. Martins, P. Mak and R. P. Martins, “A single-to-differential
LNA topology with robust output gain-phase balancing against balun
imbalance,” IEEE International Symposium of Circuits and Systems
(ISCAS), pp. 289-292, 2011.
[14] P.-I. Mak and R. Martins, “Design of an ESD-Protected UltraWideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners”,
IEEE Trans. Circuits Syst. I, vol. 56, pp. 933-942, May 2009.
[15] S. Robert, O. Abed-Meraim, L. Lo Coco,“Wide-band variable-gain
LNA in 65 nm CMOS with inverter based amplifier for multi-tuners cable
TV reception,” 2009 Proceedings of ESSCIRC, pp. 104-107, 2009.
[16] F. Bruccoleri, E. A.M. Klumperink, B. Nauta, “Wde-Band CMOS
Low-Noise Amplifier Exploiting Thermal Noise Canceling,” IEEE Journal
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[17] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts and B.
Nauta. “The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology,”
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2008
70
[18] R. Svitek and S. Raman, “DC Offsets in Direct-Conversion Receivers:
Characterization and Implications,” IEEE Microwave Magazine, pp. 76-86,
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[19] F. Marki and C. Marki, “Mixer Basics Primer - A Tutorial for RF &
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[20] P. Mak and R. P. Martins, “A 0.46-mm2 4-dB NF Unified Receiver
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71
LISTOFFIGURES
Figure 1.1 Block diagram of a RF receiver ................................................... 9 Figure 2.1 Block diagram of a Direct Conversion Receiver ....................... 13 Figure 2.2 Harmonics and Intermodulation [1] .......................................... 16 Figure 2.3 Definition of receiver linearity parameters................................ 17 Figure 2.4 Self-mixing of LO (LO Leakage) .............................................. 18 Figure 2.5 Self-mixing of interferes (Interferes Leakage) .......................... 19 Figure 2.6 Feedthrough from RF to IF ........................................................ 20 Figure 2.7 Simple CS and CG LNA Configurations .................................. 21 Figure 2.8 Simple network for impedance matching .................................. 22 Figure 2.9 Example of resistor thermal noise model .................................. 23 Figure 2.10 Double-balanced mixer............................................................ 26 Figure 3.1 The basic common-gate-common-source single-to-differential
topology ................................................................................... 29 Figure 3.2 Noise Figure (NF), voltage gain (Av) and gain imbalance (ΔAv)
versus impedance scaling factor ‘n’ for three different cases [11]
.................................................................................................. 32 Figure 3.3 Small signal equivalent circuits of the CG stage ....................... 33 Figure 3.4 Inducotrless Scaled-gm Noise-Cancelling Balun-LNA (LNA.A)
.................................................................................................. 34 Figure 3.5 Gain-Boosting Current-Balancing Equal-gm Balun-LNA
(LNA.B) ................................................................................... 37 Figure 4.1 Basic BLIXER topology consisting of the balun-LNA core of
Figure 3.1 with cascaded double-balanced mixer ....................................... 42 Figure 4.2 I/Q-BLIXER using LNA.A driven by LO waveforms with 25%
duty cycle ................................................................................. 44 Figure 4.3 25% duty cycle LO waveforms ................................................. 45 Figure 4.4 I/Q-BLIXER using LNA.B driven by LO waveforms with 25%
duty cycle ................................................................................. 46 Figure 5.1 Simulation Results of the two LNAs ......................................... 49 Figure 5.2 IIP2 simulation of LNA.A ......................................................... 50 Figure 5.3 IIP3 simulation of LNA.A ......................................................... 50 Figure 5.4 IIP2 and IIP3 versus input RF frequency for LNA.A................ 51 Figure 5.5 IIP2 simulation of LNA.B ......................................................... 52 Figure 5.6 IIP3 simulation of LNA.B ......................................................... 52 72
Figure 5.7 IIP2 and IIP3 versus input RF frequency for LNA.B ................ 53 Figure 5.8 Monte Carlo analyse of IIP2, LNA.A, W2=90μm .................... 54 Figure 5.9 Monte Carlo analyse of IIP2, LNA.A, W2=250μm .................. 55 Figure 5.10 Monte Carlo analyse of IIP2, LNA.B ...................................... 55 Figure 5.11 Vgs of CS stagesVS IIP2 ......................................................... 56 Figure 5.12 Conversion gain of BLIXER using LNA.A for fIF=500MHz.. 57 Figure 5.13 Noise Figure of BLIXER using LNA.A for fIF=500MHz ....... 57 Figure 5.14 S11 parameter simulation for the BLIXER using LNA.A ...... 58 Figure 5.15 Conversion gain (GC), NFSSB and NFDSB of the I/Q-BLIXER
using LNA.A.......................................................................... 59 Figure 5.16 IIP3 simulation for BLIXER using LNA.A............................. 60 Figure 5.17 IIP2 simulation for BLIXER using LNA.A............................. 61 Figure 5.18 Conversion gain of BLIXER using LNA.B for fIF=500MHz .. 62 Figure 5.19 Noise Figure of BLIXER using LNA.B for fIF=500MHz ....... 62 Figure 5.20 S11 parameter simulation for the BLIXER using LNA.B....... 63 Figure 5.21 Conversion gain (GC), NFSSB and NFDSB of the I/Q-BLIXER
using LNA.B .......................................................................... 64 Figure 5.22 IIP3 simulation for BLIXER using LNA.B ............................. 65 Figure 5.23 IIP2 simulation for BLIXER using LNA.B ............................. 65 73
LISTOFTABLES
Table 5.1 Parameters of the LNAs .............................................................. 48 Table 5.2 Performances summary of the BLIXERs ................................... 66 74
ACRONYMS
CDMA
CMOS
GSM
UWB
SDR
CG
CS
S-to-D
IMD
RF
IF
SNR
NF
NR
SSB
DSB
Code Division Multiple Access
Complementary Metal Oxide Semiconductor
Global System for Mobile Communications
Ultra Wideband
Software Defined Radio
Common Gate
Common Source
Single-end-to-Differential
Intermodulation Distortions
Radio Frequency
Intermediate Frequency
Signal-to-Noise Ratio
Noise Figure
Noise Ratio
Signal-Side Band
Double-Side Band
75
APPENDIX
1
L. Zhu and M. Liliebladh, “Comparison and IIP2 analysis of two Wideband
Balun-LNAs Designed in 65nm CMOS,” Norchip, November 2011.
76
Comparison and IIP2 Analysis of Two Wideband
Balun-LNA Designed in 65nm COMS
Lin Zhu, Martin Liliebladh
Dept. of Electrical and Information Technology
Lund University, Sweden
zhu.lin.gm@gmail.com, martin.liliebladh@eit.lth.se
Abstract—Two wideband Balun-LNA configurations have been
designed in 65nm COMS technology. Both of them employ a
single-to-differential (S-to-D) conversion topology composed of
a common gate (CG) and a common source (CS) amplifying
stages, providing output balancing and noise cancelling. One is
inductorless and the other one exploits gain-boosting currentbalancing topology. With 2.5V and 2.5V/1.8V supply the LNAs
achieve voltage gains of 24.5dB and 22.8dB, noise factors of
below or close to 3dB, input second-order intercept points
(IIP2) of 31dB and 41.8dB, respectively. In addition, the
sensitivity of IIP2 is deeply investigated.
Keywords-low noise amplifiers (LNA), Balun-LNA, common
gate, common source, self-biasing, single-to-differential (S-to-D),
second-order input-referred intercept point (IIP2), noisecancelling, gain-boosting current-balancing, Monte Carlo.
I.
INTRODUCTION
Recent works on wideband low noise amplifiers (LNAs)
based on single-to-differential (S-to-D) topology [1] [2] have
shown reliable RF performances such as output balancing,
moderate noise figure (NF), high linearity and broadband
input matching. This topology serves as a useful singleended to differential converter, which takes input from the
antenna and drives the differential inputs of the mixer. This
topology combines a common gate (CG) and a common
source (CS) amplifying stages, as shown in Figure 1. The
CG stage provides wideband input matching and in-phase
gain (gm,CG · RCG), while the CS stage provides an anti-phase
gain (-gm,CS · RCS). When the gains of the two stages are equal
the functionality of a Balun is realized.
However, it is well known that the CG amplifier presents
a high noise factor, which is usually greater than 3dB. This
topology addresses the problem by using a properly designed
CS stage to cancel the noise of the CG transistor, which
dominates in the CG stage [3]. The noise current due to the
CG transistor generates an in-phase noise voltage on the
source resistor (vn,in) and an amplified anti-phase noise
voltage across RCG (vn,CG). The CS stage also amplifies the
noise voltage (vn,in) leading to an in-phase noise voltage
(vn,CS), which is fully correlated with vn,CG, across RCS. For
equal CS and CG gain, the noise due to CG transistor is fully
cancelled by differential sensing.
Two wideband Balun-LNAs using the S-to-D topology
were designed in 65nm CMOS technology to investigate
IIP2 property. In the inductorless LNA the gm of CS stage is
scaled up n times and the load resistor is scaled down n times
(gm,CS=n·gm,CG, RCG=n·RCS), while still keeping balanced gain
Figure 1. The basic common-gate-common-source single-to-differential
topology
for the two stages (gm,CS · RCS = gm,CG · RCG). In the gainboosting current-balancing Balun-LNA [4], the transistors
are of equal size and biased same (equal gm). Normal equalgm scheme suffers the problem of noise. The noise from CS
stage becomes significant due to its low gm (≈1/Rs) and is
magnified by the voltage division of ½ by Rs and Zin, leading
to degradation of noise performance. But the topology
presented in section II. B addresses this by adopting an extra
amplifier between the CS and CG stages to improve the gain,
thus suppressing the noise.
Not only the noise, but also the distortion of CG
transistor is cancelled, as shown in [3], providing remarkably
enhanced IIP2 and IIP3. The stability of the IIP2, however,
becomes a problem since high linearity is only available in a
very small range of Vgs of the CS transistor. In practical
implementation, the IIP2 of this topology is also relatively
sensitive to components mismatches.
One way to improve the stability of IIP2 is to adopt a
differential current balancer (DCB) [5], consisting of
cascaded amplifiers and cross-coupled capacitors, as the
DCB shown in Figure 3. It can be treated as a current
controlled current source with unity gain, offering the
desired differential balancing inherently. Using the double
cascaded amplifiers (M5-M8) with cross-coupled capacitors
(C1-C4), the DCB significantly increases the precision of
2.5V
2.5V
R1
R1
R2
R2
+ VOUT -
+ VOUT -
VB2
DCB
VB2
M3
VB3
M8
M7
M4
C5
1.8V
VB1
VB1
M1
M5
M4
M6
C3
RS = 50Ω
M2
VS
C6
RBIAS
CEXT
C4
M3
gmx
X
M1
C2
RS = 50Ω
Figure 2. Schematic of inductorless noise-cancelling Balun-LNA
VIN
VS
outputs balancing. The final differential imbalance should be
just the residual of the original error so that distortions can
be minimized.
However, the current balancer cannot be employed on
scaled circuits as discussed before. The DCB requires equal
output resistance of the cascaded transistors to cancel
imbalances. But this is not possible for a scaled circuit.
The paper is structured as follows. Section II presents
two topologies of Balun-LNAs. Simulated results for both
LNA designs are given in Section III followed by discussion
about IIP2 performance. The conclusions are drawn in
Section IV.
II. INDUCTORLESS NOISE-CANCELING BALUN-LNA
(LNA.A) AND GAIN-BOOSTING CURRENT-BALANCING
BALUN-LNA (LNA.B) TOPOLOGIES
A. Inductorless Noise-Canceling Balun-LNA (LNA.A)
Figure 2 depicts the schematic of the inductorless noisecanceling Balun. It employs the S-to-D conversion described
in the previous section. Both of the CG and CS stages are
cascaded to achieve a high voltage gain. The CG stage is
biased using a resistor to avoid internal or external inductors.
And the resistor can also provide a bias voltage to M2. So the
input impedance becomes
1
,
//R
1
An external capacitor (CEXT) is adopted to form a π-network,
which gives a broad input match, together with the input
bondwire inductance and the input capacitance. Depending
on the application or requirement the CEXT can be removed
and the input matching would only be degraded by a few dB.
When the input impedance is matched to Rs, the NF with
respect to Rs is
gmx
C1
M2
LEXT
Figure 3. Schematic of Gain-boosting Current-balancing BalunLNA
2
1
3
where the second, third and fourth term of NF account for
noise of M1, M2 and load resistors , respectively.
B. Gain-boosting Current-balancing Balun-LNA (LNA.B)
Figure 3 shows the schematic of the gain-boosting
current-balancing Balun-LNA. It consists of an S-toD amplifier, an inverter based gain-boosting amplifier (gmx),
and a differential current balancer (DCB).
The S-to-D amplifier achieves output balancing while
realizing wideband input impedance matching. Unlike the Sto-D topology of LNA.A, this amplifier applies equal biased
and sized transistors (equal gm) for both common gate and
common source stages, leading to better linearity. Moreover,
the DCB, which corrects the errors of the two branches, can
be applied on this topology. The extra gmx can be seen as an
amplifier with transconductance of gmx. It enhances the gain
of the circuit, helps to achieve good input matching and selfbiases M1 and M2 simultaneously.
The circuit works as follows. The common source stage
composed of gmx and M2 generates an anti-phase output
signal at point X. Assuming that the signal at X is -Avin, vout+
is given by
∙
∙ 1
∙
∙
∙
∙
4
∙
∙
∙
∙
∙
∙
∙
5
24
Gain (dB)
The gain is boosted by this scheme and the noise and input
resistance are reduced. Moreover, the negative output is
given by
20
So in order to balance the outputs, 0.5
6
1
1.5
2
2.5
3
3.5
4
4.5
5
1
1.5
2
2.5
3
3.5
4
4.5
5
2.5
3
3.5
Frequency (GHz)
4
4.5
5
3.1
An external inductor is used to achieve a wideband
impedance matching. The input resistance is
,
NF (dB)
3
should be satisfied.
1
4
8
where the second, third and fourth term account for M1, M2
and load resistors noise.
2.8
-10
S11 (dB)
4
2.9
2.7
0.5
7
When assuming Gm1·Rs=1, the noise factor with respect
to Rs becomes
III.
22
-15
-20
LNA.A
LNA.B
-25
-30
0.5
1
SIMUALTION RESULTS AND DISCCUSION
The circuits designed in 65nm COMS technology have
been simulated with 50fF capacitive loads in the frequency
range between 600MHz and 5GHz. Parameters of the
circuits are shown in Table I. the LNA.A was simulated with
transistors of 90μm or 250μm width to find out the effects of
components mismatches. Since all the other parameters in
the circuit were equal the power consumption, gain, NF and
S11 reported in this section are valid for both 90 and 250μm
width amplifiers.
TABLE I.
PARAMETERS OF THE CIRCUITS
LNA.A
LNA.B
W1(μm)
66
26
W2(μm)
90/250
LNA.A
LNA.B
gm1(mS)
21
17
76
26
gm2(mS)
W3(μm)
10
gm3(mS)
8.3
17
W4(μm)
5
gm4(mS)
3.2
Length of all transistors is 0.06 μm
LNA.A consumes 25mW from a 2.5V supply and
LNA.B dissipates 17mW from 2.5V/1.8V supplies. Figure 4
shows the gain, noise factor and the S11 parameter of the
two LNAs. The two circuits achieve almost same NF, close
or less than 3dB, however, the gain of LNA.B is higher. That
implies that LNA.B requires higher gain to suppress the
noise as discussed in Section I. In addition, good input
matching (<11dB) is obtained by both the LNA topologies.
Table II compares the overall performance of the BalunLNAs in this paper with the state-of-art in 65nm CMOS,
showing feasibility of the configurations.
1.5
2
Figure 4. Simulation Results of two LNAs
TABLE II.
Band
(GHz)
Gain
(dB)
NF
(dB)
Input
Matching
IIP2
(dB)
IIP3
(dB)
Power
(mW)
COMPARISON OF BALUN-LNAS IN 65NM CMOS
LNA,A*
LNA.B
[3]
[4]
(sim)
[6]
0.6-5
0.6-5
0.2-5.2
0.17-1.7
0.05-10
24.5
22.8
13-16
25.6
24-25
<3.1
<3.1
<3.5
2.5
2.7-3.6
Matched
Matched
Matched
Matched
Matched
31
41.8
>20
44.8
-2.1
5.1
>0
5.6
25
17
14
11.6
32.4
(max)
-2
(max)
21.7
*For both 90μm and 250μm width transistor configurations
Two sinusoidal tones located at 2.4 / 2.41GHz are taken
to simulate the linearity of the circuits. LNA.A achieves
31dB for IIP2 and -2.1dB for IIP3. And its counterpart,
which benefits from the equal sized and biased transistors as
well as the current-balancing scheme, shows 41.84dB and
5.1dB for IIP2 and IIP3, respectively.
In order to test the IIP2 sensitivity against components
mismatches, the circuits are simulated by Monte Carlo
analysis. We present in Figure 5 the IIP2 result of a 200
points of mismatch only Monte Carlo simulation of LNA.A
with dimension of 90/0.06μm CS transistor which is biased
by a fixed voltage. The average IIP2 of this circuit is 28.3dB,
however, Only 83.5% of the IIP2 are greater than 25dB,
implying the IIP2 is very sensitive to components
mismatches. Figure 6 shows the stability of IIP2 is improved
50
by replacing the CS transistor by a larger one (250/0.06μm).
The IIP2 greater than 25dB account for 96% of total runs.
This is because mismatch is always an absolute value, not a
percentage of parameters of components. So a large
transistor is less sensitive to mismatches than a small one.
According to the equation
mu = 28.2556
45
Number of Runs
40
35
30
25
20
∙
15
10
5
0
18
20
22
24
26
IIP2 (dB)
28
30
32
Figure 5. Monte Carlo Simulation of IIP2, LNA.A, W2=90μm
100
mu = 30.4687
90
Number of Runs
70
60
50
40
30
, the mismatch on W causes a small change on Id, and then
results in imbalance at outputs, thus deteriorating the
linearity. Consequently, the 250μm transistor has less
mismatch, leading to stable IIP2.The LNA.B, which benefits
from the DCB, provides stable IIP2 even though the
dimension of transistors is small, as shown in Figure 7. The
IIP2 greater than 35dB occupy 92.5% among total runs.
20
IV.
10
20
25
30
35
40
45
IIP2 (dB)
50
55
60
Figure 6. Monte Carlo Simulation of IIP2, LNA.A, W2=250μm
120
mu = 39.7543
Number of Runs
100
80
60
The gain-boosting current-balancing Balun-LNA with
equal gm and DCB provides better IP2 performance, both
IIP2 and stability, with small transistors, but suffers the
problem of noise factor due to the noise from CS stage. The
unequal gm topology has better noise performance but with
very unstable IIP2 if CS transistor is not big enough. To get
stable IIP2, large transistors are required but that calls for
more area. In addition, it consumes more power than the
equal- gm LNA.
[1]
20
20
25
30
35
40
45
IIP2 (dB)
50
55
60
[2]
Figure 7. Monte Carlo Simulation of IIP2, LNA.B
50
[3]
40
[4]
IIP2(dB)
30
[5]
20
10
[6]
LNA.A, 90μm CS
LNA.A, 250μm CS
LNA.B
0
-10
0.4
CONCLUSION
REFERENCES
40
0
9
Another way to emulate the effects of matching is to vary
the bias voltage of the CS stage. Figure 8 compares the
simulated IIP2 sensitivity with respect to Vgs of CS stages. It
can be seen that the LNA.B has the widest window of IIP2,
verifying that the DCB does help to improve the IIP2 as well
as the stability.
80
0
∙
0.45
0.5
0.55 0.6
0.65 0.7 0.75 0.8
Vgs for Common Source Stage (V)
Figure 8. Vgs VS IIP2
0.85
0.9
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S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B.
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P. Mak and R. Martins, “A 0.46mm2 4dB-NF Unified Receiver
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