HM6264BI Series 8,192-word 8-bit High Speed CMOS Static RAM ×

HM6264BI Series 8,192-word 8-bit High Speed CMOS Static RAM ×
HM6264BI Series
8,192-word × 8-bit High Speed CMOS Static RAM
ADE-203-492A (Z)
Rev. 1.0
Sep. 5, 1996
Description
The Hitachi HM6264BI is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher
performance and low power consumption by 1.5 µm CMOS process technology. The device,
packaged in 450 mil SOP (foot print pitch width), 600 mil plastic DIP, is available for high density
mounting.
Features
• High speed
 Fast access time: 100/120 ns (max)
• Low power
 Standby: 10 µW (typ)
 Operation: 15 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
 Three state output
• Directly TTL compatible
 All inputs and outputs
• Battery backup operation capability
• Operating temperature range
 –40_C to +85_C
Ordering Information
Type No.
Access time
Package
HM6264BLPI-10
HM6264BLPI-12
100 ns
120 ns
600-mil, 28-pin plastic DIP (DP-28)
HM6264BLFPI-10T
HM6264BLFPI-12T
100 ns
120 ns
450-mil, 28-pin plastic SOP(FP-28DA)
HM6264BI Series
Pin Arrangement
HM6264BLPI/BLFPI Series
NC
A12
A7
A6
A5
A4
A3
1
2
A2
A1
A0
8
9
10
11
12
21
20
19
18
17
VCC
WE
CS2
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
13
14
16
15
I/O5
I/O4
I/O1
I/O2
I/O3
VSS
28
27
26
25
24
3
4
5
6
7
23
22
(Top view)
Pin Description
Pin name
Function
A0 to A12
Address input
I/O1 to I/O8
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
NC
No connection
VCC
Power supply
VSS
Ground
2
HM6264BI Series
Block Diagram
A11
A8
A9
A7
A12
A5
A6
A4
Row
decoder
I/O1
CS2
CS1
VCC
VSS
Column I/O
Input
data
control
I/O8
Memory array
256 × 256
Column decoder
A1 A2 A0 A10 A3
Timing pulse generator
Read, Write control
WE
OE
3
HM6264BI Series
Function Table
WE
CS1
CS2
OE
Mode
VCC current
I/O pin
Ref. cycle
×
H
×
×
Not selected (power down)
ISB, ISB1
High-Z
—
×
×
L
×
Not selected (power down)
ISB, ISB1
High-Z
—
H
L
H
H
Output disable
ICC
High-Z
—
H
L
H
L
Read
ICC
Dout
Read cycle (1)–(3)
L
L
H
H
Write
ICC
Din
Write cycle (1)
L
L
H
L
Write
ICC
Din
Write cycle (2)
Note: ×: H or L
Absolute Maximum Ratings
Parameter
1
Power supply voltage*
1
Symbol
Value
VCC
–0.5 to +7.0
Unit
V
2
3
Terminal voltage*
VT
–0.5* to VCC + 0.3* V
Power dissipation
PT
1.0
W
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–40 to +85
°C
Notes: 1. Relative to VSS
2. VT min: –3.0 V for pulse half-width ² 50 ns
3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
VIH
2.4
—
VCC + 0.3
V
—
0.6
V
Input high voltage
Input low voltage
Note:
4
VIL
–0.3*
1. VIL min: –3.0 V for pulse half-width ² 50 ns
1
HM6264BI Series
DC Characteristics (Ta = –40 to +85°C, VCC = 5 V ±10%, VSS = 0 V)
Parameter
Symbol Min
Typ*1 Max Unit Test conditions
Input leakage current
|ILI|
—
—
2
µA
Vin = VSS to VCC
Output leakage current
|ILO|
—
—
2
µA
CS1 = VIH or CS2 = VIL or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power supply
current
ICCDC
—
7
20
mA
CS1 = VIL, CS2 = VIH, II/O = 0 mA
others = VIH/VIL
Average operating power ICC1
supply current
—
30
50
mA
Min cycle, duty = 100%,
CS1 = VIL, CS2 = VIH, II/O = 0 mA
others = VIH/VIL
ICC2
—
3
8
mA
Cycle time = 1 µs, duty = 100%, II/O = 0 mA
CS1 ² 0.2 V, CS2 ³ VCC – 0.2 V,
VIH ³ VCC – 0.2 V, VIL ² 0.2 V
ISB
—
1
3
mA
CS1 = VIH, CS2 = VIL
—
2
200
µA
CS1 ³ VCC – 0.2 V, CS2 ³ VCC – 0.2 V or
0 V ² CS2 ² 0.2 V, 0 V ² Vin
Standby power supply
current
ISB1*
2
Output low voltage
VOL
—
—
0.4
V
IOL = 2.1 mA
Output high voltage
VOH
2.4
—
—
V
IOH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. VIL min = –0.3V
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
1
Input capacitance*
Input/output capacitance*
Note:
1
Symbol
Min
Typ
Max
Unit
Test conditions
Cin
—
—
5
pF
Vin = 0 V
CI/O
—
—
7
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
5
HM6264BI Series
AC Characteristics (Ta = –40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 0.6 V to 2.4 V
Input and output timing reference level: 1.5 V
Input rise and fall time: 10 ns
Output load: 1 TTL Gate + CL (100 pF) (Including scope & jig)
Read Cycle
HM6264BI-10 HM6264BI-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Read cycle time
tRC
100
—
120
—
ns
Address access time
tAA
—
100
—
120
ns
CS1
tCO1
—
100
—
120
ns
CS2
tCO2
—
100
—
120
ns
tOE
—
50
—
60
ns
CS1
tLZ1
10
—
10
—
ns
2
CS2
tLZ2
10
—
10
—
ns
2
Output enable to output in low-Z
tOLZ
5
—
5
—
ns
2
Chip deselection in to output in high-Z CS1
tHZ1
0
35
0
40
ns
1, 2
CS2
tHZ2
0
35
0
40
ns
1, 2
Output disable to output in high-Z
tOHZ
0
35
0
40
ns
1, 2
Output hold from address change
tOH
10
—
10
—
ns
Chip select access time
Output enable to output valid
Chip selection to output in low-Z
Notes
Notes: 1. tHZ is defined as the time at which the outputs achieve the open circuit conditions and are
not referred to output voltage levels.
2. At any given temperature and voltage condition, tHZ maximum is less than tLZ minimum both
for a given device and from device to device.
3. Address must be valid prior to or simultaneously with CS1 going low or CS2 going high.
6
HM6264BI Series
Read Timing Waveform (1) (:( = VIH)
tRC
Address
Valid address
tAA
tCO1
CS1
tLZ1
tCO2
CS2
tHZ1
tLZ2
tOE
tHZ2
tOLZ
OE
tOHZ
Dout
High Impedance
Valid data
tOH
Read Timing Waveform (2) (:( = VIH, 2( = VIL)
Address
Valid address
t AA
t OH
Dout
t OH
Valid data
7
HM6264BI Series
Read Timing Waveform (3) (:( = VIH, 2( = VIL)*
3
t CO1
CS1
t HZ1
t LZ1
t HZ2
CS2
t CO2
t LZ2
Dout
Valid data
Write Cycle
HM6264BI-10 HM6264BI-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
100
—
120
—
ns
Chip selection to end of write
tCW
80
—
85
—
ns
2
Address setup time
tAS
0
—
0
—
ns
3
Address valid to end of write
tAW
80
—
85
—
ns
Write pulse width
tWP
60
—
70
—
ns
1, 9
Write recovery time
tWR
0
—
0
—
ns
4
WE to output in high-Z
tWHZ
0
35
0
40
ns
5
Data to write time overlap
tDW
40
—
40
—
ns
Data hold from write time
tDH
0
—
0
—
ns
Output active from end of write
tOW
5
—
5
—
ns
Output disable to output in high-Z
tOHZ
0
35
0
40
ns
5
Notes: 1. A write occurs during the overlap of a low CS1, and high CS2, and a high WE. A write
begins at the latest transition among CS1 going low,CS2 going high and WE going low. A
write ends at the earliest transition among CS1 going high CS2 going low and WE going
high. Time tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of
write cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of the
opposite phase to the outputs must not be applied.
6. If CS1 goes low simultaneously with WE going low after WE goes low, the outputs remain in
high impedance state.
7. Dout is the same phase of the written data in this write cycle.
8. Dout is the read data of the next address
9. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a
problem of data bus contention
tWP ³ tWHZ max + tDW min.
8
HM6264BI Series
Write Timing Waveform (1) (2( Clock)
tWC
Address
Valid address
OE
tCW
tWR
CS1
*6
CS2
WE
tAW
tAS
tWP
tOHZ
Dout
Din
tDW
High Impedance
High Impedance
tDH
Valid data
9
HM6264BI Series
Write Timing Waveform (2) (2( Low Fixed) (2( = VIL)
tWC
Address
Valid address
tAW
tWR
tCW
CS1
*6
CS2
tWP
WE
tAS
tOH
tOW
tWHZ
*7
Dout
tDW
tDH
*5
Din
10
High Impedance
Valid data
*8
HM6264BI Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ*1 Max
Unit
Test conditions*3
VCC for data retention
VDR
2.0
—
V
CS1 ³ VCC –0.2 V,
CS2 ³ VCC –0.2 V or CS2 ² 0.2 V
Vin ³ 0 V
Data retention current
ICCDR
—
1*
100*
µA
VCC = 3.0 V, 0 V ² Vin ² VCC
CS1 ³ VCC –0.2 V, CS2 ³ VCC –0.2 V
or 0 V ² CS2 ² 0.2 V
Chip deselect to data
retention time
tCDR
0
—
—
ns
See retention waveform
Operation recovery time
tR
5
—
—
ms
1
—
2
Notes: 1. Reference data at Ta = 25°C.
2. VIL min = –0.3V.
3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2
controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high
impedance state. If CS1 controls data retention mode, CS2 must be CS2 ³ VCC – 0.2 V or 0
V ² CS2 ² 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high
impedance state.
Low VCC Data Retention Timing Waveform (1) (&6 Controlled)
tCDR
Data retention mode
tR
VCC
4.5 V
2.4 V
VDR
CS1
0V
CS1 ≥ VCC – 0.2 V
11
HM6264BI Series
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
Data retention mode
VCC
4.5 V
tCDR
tR
CS2
VDR
0.4 V
CS2 ≤ 0.2 V
0V
Package Dimensions
HM6264BLFPI Series (DP-28)
Unit: mm
35.6
36.5 Max
15
13.4
14.6 Max
28
14
1.2
15.24
2.54 ± 0.25
0.48 ± 0.10
0.51 Min
1.9 Max
2.54 Min 5.7 Max
1
+ 0.11
0.25 – 0.05
0° – 15°
12
HM6264BI Series
HM6264BLPI Series (FP-28DA)
Unit: mm
18.3
18.75 Max
15
3.0 Max
14
+ 0.10
0.40 – 0.05
0.1 Min
1.27 ± 0.10
11.8 ± 0.3
0.17
1
0.895
+ 0.08
– 0.07
8.4
28
0 – 10 °
1.0
13
HM6264BI Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or
part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or
any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the
examples described herein.1
5. No license is granted by implication or otherwise under any patents or other rights of any third
party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s
products are requested to notify the relevant Hitachi sales offices when planning to use the
products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
USA
Tel: 415-589-8300
Fax: 415-583-4207
14
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 0628-585000
Fax: 0628-778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
HM6264BI Series
Revision Record
Rev.
Date
Contents of Modification
Drawn by
Approved by
0.0
Dec. 1, 1995
Initial issue
I. Ogiwara
K. Yoshizaki
1.0
Sep. 5, 1996
Deletion of Preliminary
15
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