a CMOS Complete DDS AD9831

a CMOS Complete DDS AD9831
a
CMOS
Complete DDS
AD9831
FEATURES
3 V/5 V Power Supply
25 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Parallel Loading
Powerdown Option
72 dB SFDR
125 mW (5 V) Power Consumption
40 mW (3 V) Power Consumption
48-Pin TQFP
GENERAL DESCRIPTION
This DDS device is a numerically controlled oscillator employing a phase accumulator, a sine look-up table and a 10-bit D/A
converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Clock rates up to 25 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is effected
by loading registers through the parallel microprocessor
interface.
A powerdown pin allows external control of a powerdown
mode. The part is available in a 48-pin TQFP package.
APPLICATIONS
DDS Tuning
Digital Demodulation
FUNCTIONAL BLOCK DIAGRAM
DVDD
DGND
AVDD
REFOUT
AGND
MCLK
FS ADJUST
ON-BOARD
REFERENCE
FSELECT
FREQ0 REG
PHASE
ACCUMULATOR
(32-BIT)
MUX
Σ
12
SIN
ROM
REFIN
FULL-SCALE
CONTROL
10-BIT DAC
COMP
IOUT
FREQ1 REG
PHASE0 REG
AD9831
PHASE1 REG
MUX
PHASE2 REG
PHASE3 REG
PARALLEL REGISTER
SLEEP
TRANSFER CONTROL
RESET
MPU INTERFACE
D0
D15
WR
A0
A1
A2
PSEL0
PSEL1
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
= +3.3 V 6 10%; +5 V 6 10%; AGND = DGND = 0 V; T = T to T ; REFIN =
AD9831–SPECIFICATIONS1 (VREFOUT;
R = 3.9 kV; R = 300 V for IOUT unless otherwise noted)
DD
A
SET
Parameter
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate (fMAX)
IOUT Full Scale
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS2
Dynamic Specifications
Signal to Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range (SFDR)3
Narrow Band (± 50 kHz)
Wide Band (± 2 MHz)
Clock Feedthrough
Wake-Up Time4
Powerdown Option
VOLTAGE REFERENCE
Internal Reference @ +25°C
TMIN to TMAX
REFIN Input Impedance
Reference TC
REFOUT Output Impedance
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
POWER SUPPLIES
AVDD
DVDD
IAA
IDD
IAA + IDD5
Low Power Sleep Mode6
MIN
MAX
LOAD
AD9831A
Units
Test Conditions/Comments
10
25
4
5
1.5
Bits
MSPS nom
mA nom
mA max
V max
±1
± 0.5
LSB typ
LSB typ
50
–53
dB min
dBc max
–72
–70
–50
–60
1
Yes
dBc min
dBc min
dBc min
dBc typ
ms typ
1.21
1.21 ± 7%
10
100
300
Volts typ
Volts min/max
MΩ typ
ppm/°C typ
Ω typ
VDD – 0.9
0.9
10
10
V min
V max
µA max
pF max
2.97/5.5
2.97/5.5
12
2.5 + 0.33/MHz
15
24
1
V min/V max
V min/V max
mA max
mA typ
mA max
mA max
mA max
fMCLK = 25 MHz, fOUT = 1 MHz
fMCLK = 25 MHz, fOUT = 1 MHz
fMCLK = 6.25 MHz, fOUT = 2.11 MHz
5 V Power Supply
3 V Power Supply
5 V Power Supply
5 V Power Supply
3 V Power Supply
5 V Power Supply
1 MΩ Resistor Tied Between REFOUT and AGND
NOTES
1
Operating temperature range is as follows: A Version: –40°C to +85°C.
2
100% production tested.
3
fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz.
4
See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
6
The Low Power Sleep Mode current is typically 2 mA when a 1 M Ω resistor is not tied between REFOUT and AGND.
The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
RSET
3.9kΩ
10nF
REFOUT
ON-BOARD
REFERENCE
12
SIN
ROM
REFIN
FS
ADJUST
FULL-SCALE
CONTROL
10-BIT DAC
COMP
AVDD
10nF
IOUT
300Ω
50pF
AD9831
Figure 1. Test Circuit with Which Specifications Are Tested
–2–
REV. A
AD9831
TIMING CHARACTERISTICS
(VDD = +3.3 V 6 10%, +5 V 6 10%; AGND = DGND = 0 V, unless otherwise noted)
Parameter
Limit at
TMIN to TMAX
(A Version)
Units
Test Conditions/Comments
t1
t2
t3
t4 *
t4A*
t5
t6
t7
t8
t9 *
t9A*
t10
40
16
16
8
8
8
t1
5
3
8
8
t1
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MCLK Period
MCLK High Duration
MCLK Low Duration
WR Rising Edge to MCLK Rising Edge
WR Rising Edge After MCLK Rising Edge
WR Pulse Width
Duration between Consecutive WR Pulses
Data/Address Setup Time
Data/Address Hold Time
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
RESET Pulse Duration
*See Pin Description section.
Guaranteed by design but not production tested.
t1
MCLK
t2
t4
t3
t5
t4A
WR
t6
Figure 2. Clock Synchronization Timing
t6
t5
WR
t8
t7
A0, A1, A2
DATA
VALID DATA
VALID DATA
Figure 3. Parallel Timing
MCLK
t9A
t9
FSELECT
PSEL0, PSEL1
VALID DATA
VALID DATA
t10
RESET
Figure 4. Control Timing
REV. A
–3–
VALID DATA
AD9831
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
NC
IOUT
AVDD
REFIN
FS ADJUST
AVDD
COMP
NC
AGND
NC
NC
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
TQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
AVDD
(TA = +25°C unless otherwise noted)
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1
36
AGND
35
RESET
SLEEP 3
34
A0
DVDD 4
33
A1
DVDD 5
32
A2
31
DB0
30
DB1
29
DGND
DVDD 9
28
DB2
FSELECT 10
27
DB3
PSEL0 11
PSEL1 12
26
DB4
25
DVDD
PIN 1
IDENTIFIER
REFOUT 2
DGND 6
AD9831
MCLK 7
TOP VIEW
(Not to Scale)
WR 8
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DB5
DB6
DB7
DB8
DB9
DB10
DB12
DB11
DB13
DB14
DB15
DGND
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
ORDERING GUIDE
Model
Temperature
Range
Package
Package
Description Option*
AD9831AST
– 40°C to +85°C 48-Pin TQFP ST-48
EVAL-AD9831EB Evaluation Board
*ST = Thin Quad Flatpack (TQFP).
–4–
REV. A
AD9831
PIN DESCRIPTION
Mnemonic
Function
POWER SUPPLY
AVDD
Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between AVDD
and AGND. AVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
AGND
Analog Ground.
DVDD
Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD
and DGND. DVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
DGND
Digital Ground.
ANALOG SIGNAL AND REFERENCE
IOUT
Current Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
FS ADJUST
Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the
magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
IOUTFULL-SCALE = 12.5 × VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 3.9 kΩ typical
REFIN
Voltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831
accepts a reference of 1.21 V nominal.
REFOUT
Voltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is
made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGITAL INTERFACE AND CONTROL
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one
MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change
on FSELECT should not coincide with an MCLK rising edge.
WR
Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9831. The data is loaded
into the AD9831 on the rising edge of the WR pulse. This data is then loaded into the destination register on the
MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR rising
edge should occur before an MCLK rising edge. The data will then be loaded into the destination register on the
MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destination
register will be loaded on the next MCLK rising edge.
D0–D15
Data Bus, Digital Inputs for destination registers.
A0–A2
Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1 Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value being
input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the
inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1
are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising
edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase
register.
SLEEP
Low Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. The AD9831 is re-enabled by taking
SLEEP high.
RESET
Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog
output of midscale.
REV. A
–5–
AD9831
±2 MHz about the fundamental frequency. The narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±50 kHz about the fundamental frequency.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9831’s output spectrum.
Differential Nonlinearity
Table I. Control Registers
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Register
Size
Description
FREQ0 REG
32 Bits
FREQ1 REG
32 Bits
Frequency Register 0. This defines the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Frequency Register 1. This defines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the
output of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the contents of this register are added to
the output of the phase accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the contents of this register are added to
the output of the phase accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the
output of the phase accumulator.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (fMCLK/2) but excluding the dc component. Signal to (Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantization noise. The theoretical Signal to (Noise + Distortion) ratio
for a sine wave input is given by
PHASE0 REG 12 Bits
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit converter, Signal to (Noise + Distortion) = 61.96 dB.
PHASE1 REG 12 Bits
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9831, THD is defined as
2
THD = 20 log
2
(V 2 +V 3
2
2
+V 4 +V 5
+V 6
PHASE2 REG 12 Bits
2
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
PHASE3 REG 12 Bits
Output Compliance
The output compliance refers to the maximum voltage which
can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the
output compliance are generated, the AD9831 may not meet
the specifications listed in the data sheet.
Table II. Addressing the Control Registers
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the fundamental frequency and images of the MCLK frequency are
present at the output of a DDS device. The spurious free dynamic range (SFDR) refers to the largest spur or harmonic
which is present in the band of interest. The wide band SFDR
gives the magnitude of the largest harmonic or spur relative to
the magnitude of the fundamental frequency in the bandwidth
A2
A1
A0
Destination Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FREQ0 REG 16 LSBs
FREQ0 REG 16 MSBs
FREQ1 REG 16 LSBs
FREQ1 REG 16 MSBs
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
Table III. Frequency Register Bits
D15
D0
MSB
LSB
Table IV. Phase Register Bits
D15
D14
D13
D12
D11
D0
X
X
X
X
MSB
LSB
–6–
REV. A
Typical Performance Characteristics–AD9831
25
–40
AVDD = DVDD = +3.3V
TA = +25°C
–45
–50
+5V
SFDR (±2MHz) – dB
TOTAL CURRENT – mA
20
15
10
+3.3V
25MHz
–55
10MHz
–60
–65
–70
5
–75
0
5
10
15
20
MCLK FREQUENCY – MHz
–80
25
Figure 5. Typical Current Consumption vs. MCLK
Frequency
0
0.2
fOUT/fMCLK
0.1
0.3
0.4
Figure 8. Wide Band SFDR vs. fOUT/fMCLK for Various
MCLK Frequencies
–50
60
fOUT/fMCLK = 1/3
AVDD = DVDD = +3.3V
fOUT = fMCLK/3
AVDD = DVDD = +3.3V
–55
SNR – dB
SFDR (±50kHz) – dB
55
–60
–65
50
–70
45
–75
–80
10
15
20
MCLK FREQUENCY – MHz
40
10
25
Figure 6. Narrow Band SFDR vs. MCLK Frequency
15
20
MCLK FREQUENCY – MHz
25
Figure 9. SNR vs. MCLK Frequency
–40
60
fOUT/fMCLK = 1/3
AVDD = DVDD = +3.3V
AVDD = DVDD = +3.3V
–45
10MHz
–50
SNR – dB
SFDR (±2MHz) – dB
55
–55
50
25MHz
45
–60
–65
10
15
20
MCLK FREQUENCY – MHz
40
25
Figure 7. Wide Band SFDR vs. MCLK Frequency
REV. A
0
0.1
0.2
fOUT/fMCLK
0.3
0.4
Figure 10. SNR vs. fOUT/fMCLK for Various MCLK
Frequencies
–7–
AD9831–Typical Performance Characteristics
10
0
AVDD = DVDD = +2.97V
–10
–20
–30
10dB/DIV
WAKE-UP TIME – ms
7.5
5.0
–40
–50
–60
–70
2.5
–80
–90
0
–40
–100
–30
–20
TEMPERATURE – °C
0
–10
START 0Hz
RBW 300Hz
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–60
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
START 0Hz
RBW 300Hz
VBW 1kHz
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
Figure 12. fMCLK = 25 MHz, fOUT = 1.1 MHz, Frequency
Word = B439581
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–60
–60
–70
–80
–80
–90
–90
–100
–100
VBW 1kHz
STOP 12.5MHz
ST 277 SEC
–50
–70
START 0Hz
RBW 300Hz
VBW 1kHz
Figure 15. fMCLK = 25 MHz, fOUT = 4.1 MHz, Frequency
Word = 29FBE76D
10dB/DIV
10dB/DIV
STOP 12.5MHz
ST 277 SEC
Figure 14. fMCLK = 25 MHz, fOUT = 3.1 MHz, Frequency
Word = 1FBE76C9
10dB/DIV
10dB/DIV
Figure 11. Wake-Up Time vs. Temperature
VBW 1kHz
STOP 12.5MHz
ST 277 SEC
START 0Hz
RBW 300Hz
Figure 13. fMCLK = 25 MHz, fOUT = 2.1 MHz, Frequency
Word = 15810625
VBW 1kHz
STOP 12.5MHz
ST 277 SEC
Figure 16. fMCLK = 25 MHz, fOUT = 5.1 MHz, Frequency
Word = 34395810
–8–
REV. A
0
0
–10
–10
–20
–20
–30
–30
–40
–40
10dB/DIV
10dB/DIV
AD9831
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
START 0Hz
RBW 300Hz
VBW 1kHz
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
Figure 17. fMCLK = 25 MHz, fOUT = 6.1 MHz, Frequency
Word = 3E76C8B4
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–60
–60
–70
–80
–80
–90
–90
–100
–100
VBW 1kHz
STOP 12.5MHz
ST 277 SEC
START 0Hz
RBW 300Hz
Figure 18. fMCLK = 25 MHz, fOUT = 7.1 MHz, Frequency
Word = 48B43958
REV. A
STOP 12.5MHz
ST 277 SEC
–50
–70
START 0Hz
RBW 300Hz
VBW 1kHz
Figure 19. fMCLK = 25 MHz, fOUT = 8.1 MHz, Frequency
Word = 52F1A9FC
10dB/DIV
10dB/DIV
–50
VBW 1kHz
STOP 12.5MHz
ST 277 SEC
Figure 20. fMCLK = 25 MHz, fOUT = 9.1 MHz, Frequency
Word = 5D2F1AA0
–9–
AD9831
CIRCUIT DESCRIPTION
Numerical Controlled Oscillator + Phase Modulator
The AD9831 provides an exciting new level of integration for
the RF/Communications system designer. The AD9831 combines the Numerical Controlled Oscillator (NCO), SINE LookUp Table, Frequency and Phase Modulators, and a Digital-toAnalog Converter on a single integrated circuit.
This consists of two frequency select registers, a phase accumulator and four phase offset registers. The main component of the
NCO is a 32-bit phase accumulator which assembles the phase
component of the output signal. Continuous time signals have a
phase range of 0 to 2π. Outside this range of numbers, the
sinusoid functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator simply
scales the range of phase numbers into a multibit digital word.
The phase accumulator in the AD9831 is implemented with 32
bits. Therefore, in the AD9831, 2π = 232. Likewise, the ∆Phase
term is scaled into this range of numbers 0 < ∆Phase < 232 – 1.
Making these substitutions into the equation above
The internal circuitry of the AD9831 consists of three main
sections. These are:
Numerical Controlled Oscillator (NCO) + Phase Modulator
SINE Look-Up Table
Digital-to-Analog Converter
The AD9831 is a fully integrated Direct Digital Synthesis
(DDS) chip. The chip requires one reference clock, one low
precision resistor and eight decoupling capacitors to provide
digitally created sine waves up to 12.5 MHz. In addition to the
generation of this RF signal, the chip is fully capable of a broad
range of simple and complex modulation schemes. These
modulation schemes are fully implemented in the digital domain
allowing accurate and simple realization of complex modulation
algorithms using DSP techniques.
THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude
form a(t) = sin (ωt). However, these are nonlinear and not easy
to generate except through piece wise construction. On the
other hand, the angular information is linear in nature. That is,
the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2πf.
f = ∆Phase × fMCLK/232
where 0 < ∆Phase < 232
With a clock signal of 25 MHz and a phase word of 051EB852
hex
f = 51EB852 × 25 MHz/232 = 0.500000000465 MHz
The input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register
and this is controlled by the FSELECT pin. NCOs inherently
generate continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Registers. The contents of this register are added to the most significant bits of the
NCO. The AD9831 has four PHASE registers, the resolution
of these registers being 2π/4096.
Sine Look-Up Table (LUT)
MAGNITUDE
+1
0
–1
2π
PHASE
0
Figure 21. Sine Wave
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that
period can be determined.
∆Phase = ωδt
Solving for ω
ω = ∆Phase/δt = 2πf
Solving for f and substituting the reference clock frequency for
the reference period (1/fMCLK = δt)
f = ∆Phase × fMCLK/2π
The AD9831 builds the output based on this simple equation.
A simple DDS chip can implement this equation with three
major subcircuits.
To make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase information maps directly into amplitude, a ROM LUT converts the
phase information into amplitude. To do this, the digital phase
information is used to address a sine ROM LUT. Although the
NCO contains a 32-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 232 entries.
It is necessary only to have sufficient phase resolution in the
LUTs such that the dc error of the output waveform is dominated by the quantization error in the DAC. This requires the
look-up table to have two more bits of phase resolution than the
10-bit DAC.
Digital-to-Analog Converter
The AD9831 includes a high impedance current source 10-bit
DAC, capable of driving a wide range of loads at different
speeds. Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of a
single external resistor (RSET).
The DAC is configured for single ended operation. The load
resistor can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance
range. Since full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistor.
However, if the DAC full-scale output current is significantly
less than 4 mA, the DAC’s linearity may degrade.
–10–
REV. A
AD9831
DSP and MPU Interfacing
MCLK cycle introduced otherwise. When these inputs change
value, there will be a pipeline delay before control is transferred
to the selected register—there will be a pipeline delay before the
analog output is controlled by the selected register. There is a
similar delay when a new word is written to a register. PSEL0,
PSEL1, FSELECT and WR have latencies of six MCLK cycles.
The AD9831 has a parallel interface, with 16 bits of data being
loaded during each write cycle.
The frequency or phase registers are loaded by asserting the WR
signal. The destination register for the 16 bit data is selected
using the address inputs A0, A1 and A2. The phase registers
are 12 bits wide so, only the 12 LSBs need to be valid—the
4 MSBs of the 16 bit word do not have to contain valid data.
Data is loaded into the AD9831 by pulsing WR low, the data
being latched into the AD9831 on the rising edge of WR. The
values of inputs A0, A1 and A2 are also latched into the
AD9831 on the WR rising edge. The appropriate destination
register is updated on the next MCLK rising edge. If the WR
rising edge coincides with the MCLK rising edge, there is an
uncertainty of one MCLK cycle regarding the loading of the
destination register—the destination register may be loaded
immediately or the destination register may be updated on the
next MCLK rising edge. To avoid any uncertainty, the times
listed in the specifications should be complied with.
The flow chart in Figure 22 shows the operating routine for the
AD9831. When the AD9831 is powered up, the part should be
reset using RESET. This will reset the phase accumulator to
zero so that the analog output is at midscale. RESET does not
reset the phase and frequency registers. These registers will
contain invalid data and, therefore, should be set to zero by the
user.
The registers to be used should be loaded, the analog output
being fMCLK/232 × FREG where FREG is the value loaded into
the selected frequency register. This signal will be phase shifted
by the amount specified in the selected phase register (2π/4096
× PHASEREG where PHASEREG is the value contained in the
selected phase register). When FSELECT, PSEL0 and PSEL1
are programmed, there will be a pipeline delay of approximately
6 MCLK cycles before the analog output reacts to the change
on these inputs.
FSELECT, PSEL0 and PSEL1 are sampled on the MCLK
rising edge. Again, these inputs should be valid when an
MCLK rising edge occurs as there will be an uncertainty of one
RESET
DATA WRITE
FREG<0, 1> = 0
PHASEREG<0, 1, 2, 3> = 0
DATA WRITE
FREG<0> = fOUT0/fMCLK*232
FREG<1> = fOUT1/fMCLK*232
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
WAIT 6 MCLK CYCLES
DAC OUTPUT
VOUT = VREFIN*6.25*ROUT/RSET*(1 + SIN(2π(FREG*fMCLK*t/232 + PHASEREG/212)))
YES
CHANGE PHASE?
NO
NO
CHANGE FOUT?
YES
NO
CHANGE FSELECT
NO
CHANGE FREG?
CHANGE PHASEREG?
YES
CHANGE PSEL0, PSEL1
YES
Figure 22. Flow Chart for AD9831 Initialization and Operation
REV. A
–11–
AD9831
APPLICATIONS
The AD9831 contains functions which make it suitable for
modulation applications. The part can be used to perform
simple modulation such as FSK. More complex modulation
schemes such as GMSK and QPSK can also be implemented
using the AD9831. In an FSK application, the two frequency
registers of the AD9831 are loaded with different values; one
frequency will represent the space frequency while the other will
represent the mark frequency. The digital data stream is fed to
the FSELECT pin which will cause the AD9831 to modulate
the carrier frequency between the two values.
The AD9831 has four phase registers; this enables the part to
perform PSK. With phase shift keying, the carrier frequency is
phase shifted, the phase being altered by an amount which is
related to the bit stream being input to the modulator. The
presence of four shift registers eases the interaction needed
between the DSP and the AD9831.
The frequency and phase registers can be written to continuously, if required. The maximum update rate equals the
frequency of the MCLK. However, if a selected register is
loaded with a new word, there will be a delay of 6 MCLK cycles
before the analog output will change accordingly.
The AD9831 is also suitable for signal generator applications.
With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator. In addition,
the part is fully specified for operation with a +3.3 V ± 10%
power supply. Therefore, in portable applications where current
consumption is an important issue, the AD9831 is perfect.
Grounding and Layout
The printed circuit board that houses the AD9831 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it
gives the best shielding. Digital and analog ground planes
should only be joined in one place. If the AD9831 is the only
device requiring an AGND to DGND connection, then the
ground planes should be connected at the AGND and DGND
pins of the AD9831. If the AD9831 is in a system where multiple devices require AGND to DGND connections, the
connection should be made at one point only, a star ground
point that should be established as close as possible to the
AD9831.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD9831 to avoid noise coupling. The power
supply lines to the AD9831 should use as large a track as is
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.
Good decoupling is important. The analog and digital supplies
to the AD9831 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND respectively with 0.1 µF ceramic capacitors
in parallel with 10 µF tantalum capacitors. To achieve the best
from the decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the
AVDD and DVDD of the AD9831, it is recommended that the
system’s AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD9831 and AGND and the recommended digital
supply decoupling capacitors between the DVDD pins and
DGND.
–12–
REV. A
AD9831
AD9831 Evaluation Board
Using the AD9831 Evaluation Board
The AD9831 Evaluation Board allows designers to evaluate the
high performance AD9831 DDS Modulator with a minimum of
effort.
The AD9831 Evaluation kit is a test system designed to simplify
the evaluation of the AD9831. Provisions to control the
AD9831 from the printer port of an IBM-compatible PC are
included along with the necessary software. An application note
is also available with the evaluation board which gives information on operating the evaluation board.
To prove that this device will meet the user’s waveform synthesis requirements, the user only requires a 3.3 V or 5 V power
supply, an IBM-compatible PC and a spectrum analyzer along
with the evaluation board. The evaluation setup is shown
below.
The DDS Evaluation kit includes a populated, tested AD9831
printed circuit board along with the software which controls the
AD9831 in a Windows environment.
IBM COMPATIBLE PC
An area is available on the evaluation board where the user can
add additional circuits to the evaluation test set. Users may
want to build custom analog filters for the output or add buffers
and operational amplifiers which are to be used in the final
application.
XO vs. External Clock
PARALLEL PORT
CENTRONICS
PRINTER CABLE
AD9831.EXE
AD9831
EVALUATION
BOARD
Figure 23. AD9831 Evaluation Board Setup
REV. A
Prototyping Area
The AD9831 can operate with master clocks up to 25 MHz. A
25 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and an external CMOS
clock connected to the part, if required.
Power Supply
Power to the AD9831 Evaluation Board must be provided externally through the pin connections. The power leads should
be twisted to reduce ground loops.
–13–
AD9831
DVDD
AVDD
C1, C2, C3
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
C4, C5, C6
0.1µF
DVDD
LATCH
D0
D1
D2
D3
D4
D5
D6
D7
AVDD
38, 43, 47
DVDD
4, 5, 9, 25
C14
0.1µF
14
VDD
AVDD
D15
D15
U2
J1
74HC574
PC
INTERFACE
CK
REFIN
C15
0.1µF
22
VDD
LOAD
REFIN
D7
74HC574
31
CK
D0
LATCH
32
34
8
WR
R3
10kΩ
35
RESET
PSEL1
12
LK1
PSEL0
11
LK2
LK5
U4
2
D0
REFOUT
LOAD
10
LK3
7
MCLK
A0
DVDD
SW
RESET
C10
10µF
J3
C9
0.1µF
C11
0.1µF
AVDD
C12
10µF
PSEL1
PSEL0
40
R5
3.9kΩ
FSELECT
MCLK
IOUT
IOUT
3
LK4
J2
DVDD
WR
DVDD
WR
C8
10nF
A2
FSADJUST
FSELECT
41
AD9831
U3
D7
R2
10kΩ
COMP
C7
10nF
42
DVDD
LATCH
R1
10kΩ
D8
LOAD
WR
RESET
RESET
21
39
R6
300Ω
SLEEP
DGND
AGND
6, 13, 29
1, 36, 46
MCLK
R4
50Ω
DVDD
C13
0.1µF
DVDD
U1
OUT
DGND
XTAL1
Figure 24. AD9831 Evaluation Board Layout
COMPONENT LIST
Integrated Circuits
XTAL1
U2, U3
U4
OSC XTAL 25 MHz
74HC574 Latches
AD9831 (48-Pin TQFP)
Capacitors
C1–C6
C7, C8
C9, C11, C13–C15
C10, C12
0.1 µF Ceramic Chip Capacitor
10 nF Ceramic Capacitor
0.1 µF Ceramic Capacitor
10 µF Tantalum Capacitor
Resistors
R1–R3
R4
R5
R6
10 kΩ Resistor
50 Ω Resistor
3.9 kΩ Resistor
300 Ω Resistor
Links
LK1–LK4
LK5
Switch
SW
Sockets
MCLK, PSEL0,
PSEL1, FSELECT,
IOUT, REFIN
Connectors
J1
J2, J3
–14–
Three Pin Link
Two Pin Link
End Stackable Switch (SDC
Double Throw)
Sub-Miniature BNC Connector
36-Pin Edge Connector
PCB Mounting Terminal Block
REV. A
AD9831
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Thin Quad Flatpack (TQFP)
ST-48
0.063 (1.60) MAX
0.276 (7.0) BSC
0.276 (7.0) BSC
37
36
48
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.006 (0.15)
0.002 (0.05)
0° – 7°
REV. A
0° MIN
0.007 (0.18)
0.004 (0.09)
12
13
0.019 (0.5)
BSC
–15–
25
24
0.011 (0.27)
0.006 (0.17)
0.354 (9.00) BSC
0.030 (0.75)
0.018 (0.45)
0.354 (9.00) BSC
0.030 (1.45)
(0.75)
0.057
0.018 (1.35)
(0.45)
0.053
–16–
PRINTED IN U.S.A.
C2171–12–9/96
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement