DATA SHEET FAMILY SPECIFICATIONS HCMOS family characteristics March 1988

DATA  SHEET FAMILY SPECIFICATIONS HCMOS family characteristics March 1988
INTEGRATED CIRCUITS
DATA SHEET
FAMILY SPECIFICATIONS
HCMOS family characteristics
March 1988
File under Integrated Circuits, IC06
INTEGRATED CIRCUITS
DATA SHEET
Package outline drawings
January 1996
File under Integrated Circuits, IC06
Philips Semiconductors
Package outline drawings
INDEX
PACKAGE VERSIONS
DESCRIPTION
PAGE
DIP
SOT27-1
plastic dual in-line package; 14 leads (300 mil)
3
SOT38-4
plastic dual in-line package; 16 leads (300 mil)
4
SOT146-1
plastic dual in-line package; 20 leads (300 mil)
5
SOT101-1
plastic dual in-line package; 24 leads (600 mil)
6
SOT222-1
plastic dual in-line package; 24 leads (300 mil)
7
SOT117-1
plastic dual in-line package; 28 leads (600 mil)
8
SOT96-1
plastic small outline package; 8 leads; body width 3.9 mm
9
SOT108-1
plastic small outline package; 14 leads; body width 3.9 mm
10
SOT109-1
plastic small outline package; 16 leads; body width 3.9 mm
11
SOT162-1
plastic small outline package; 16 leads; body width 7.5 mm
12
SOT163-1
plastic small outline package; 20 leads; body width 7.5 mm
13
SOT137-1
plastic small outline package; 24 leads; body width 7.5 mm
14
SOT136-1
plastic small outline package; 28 leads; body width 7.5 mm
15
SOT337-1
plastic shrink small outline package; 14 leads; body width 5.3 mm
16
SOT338-1
plastic shrink small outline package; 16 leads; body width 5.3 mm
17
SOT339-1
plastic shrink small outline package; 20 leads; body width 5.3 mm
18
SOT340-1
plastic shrink small outline package; 24 leads; body width 5.3 mm
19
SOT402-1
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
20
SOT403-1
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
21
SOT360-1
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
22
SOT355-1
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
23
SO
SSOP
TSSOP
January 1996
2
Philips Semiconductors
Package outline drawings
DIP
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
MH
8
14
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.2
inches
0.17
0.020
0.13
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT27-1
050G04
MO-001AA
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-03-11
3
Philips Semiconductors
Package outline drawings
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.020
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.030
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-01-14
SOT38-4
January 1996
EUROPEAN
PROJECTION
4
Philips Semiconductors
Package outline drawings
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
11
20
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
inches
0.17
0.020
0.13
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
D
e
e1
L
ME
MH
w
Z (1)
max.
6.40
6.22
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.0
0.25
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.078
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT146-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
SC603
5
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-05-24
Philips Semiconductors
Package outline drawings
seating plane
DIP24: plastic dual in-line package; 24 leads (600 mil)
SOT101-1
ME
D
A2
L
A
A1
c
e
Z
b1
w M
(e 1)
b
MH
13
24
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.1
0.51
4.0
1.7
1.3
0.53
0.38
0.32
0.23
32.0
31.4
14.1
13.7
2.54
15.24
3.9
3.4
15.80
15.24
17.15
15.90
0.25
2.2
inches
0.20
0.020
0.16
0.066
0.051
0.021
0.015
0.013
0.009
1.26
1.24
0.56
0.54
0.10
0.60
0.15
0.13
0.62
0.60
0.68
0.63
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT101-1
051G02
MO-015AD
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-23
6
Philips Semiconductors
Package outline drawings
seating plane
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
MH
b
13
24
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.70
0.38
3.94
1.63
1.14
0.56
0.43
0.36
0.25
31.9
31.5
6.73
6.48
2.54
7.62
3.51
3.05
8.13
7.62
10.03
7.62
0.25
2.05
inches
0.185
0.015
0.155
0.064
0.045
0.022
0.017
0.014
0.010
1.256
1.240
0.265
0.255
0.100
0.300
0.138
0.120
0.32
0.30
0.395
0.300
0.01
0.081
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
OUTLINE
VERSION
SOT222-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-03-11
MS-001AF
7
Philips Semiconductors
Package outline drawings
seating plane
handbook, full
pagewidthdual in-line package; 28 leads (600 mil)
DIP28:
plastic
SOT117-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
15
28
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.1
0.51
4.0
1.7
1.3
0.53
0.38
0.32
0.23
36.0
35.0
14.1
13.7
2.54
15.24
3.9
3.4
15.80
15.24
17.15
15.90
0.25
1.7
inches
0.20
0.020
0.16
0.066
0.051
0.020
0.014
0.013
0.009
1.41
1.34
0.56
0.54
0.10
0.60
0.15
0.13
0.62
0.60
0.68
0.63
0.01
0.067
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT117-1
051G05
MO-015AH
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-14
8
Philips Semiconductors
Package outline drawings
SO
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.050
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
9
o
8
0o
Philips Semiconductors
Package outline drawings
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.050
0.028
0.024
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06S
MS-012AB
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
10
o
8
0o
Philips Semiconductors
Package outline drawings
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.050
0.041
0.228
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.01
0.01
0.028
0.004
0.012
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07S
MS-012AC
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
11
o
8
0o
Philips Semiconductors
Package outline drawings
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A
X
c
HE
y
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
10.5
10.1
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.41
0.40
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT162-1
075E03
MS-013AA
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
12
Philips Semiconductors
Package outline drawings
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013AC
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
13
Philips Semiconductors
Package outline drawings
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.419
0.043
0.050
0.055
0.394
0.016
inches
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013AD
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
14
Philips Semiconductors
Package outline drawings
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
bp
0
detail X
w M
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.419
0.043
0.050
0.055
0.394
0.016
inches
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013AE
January 1996
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
15
Philips Semiconductors
Package outline drawings
SSOP
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
D
SOT337-1
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
7
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.4
0.9
8
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT337-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
96-01-18
MO-150AB
16
o
Philips Semiconductors
Package outline drawings
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
D
SOT338-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
8
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.00
0.55
8
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT338-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-01-14
95-02-04
MO-150AC
17
o
Philips Semiconductors
Package outline drawings
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
D
SOT339-1
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.9
0.5
8
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT339-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08
95-02-04
MO-150AE
18
o
Philips Semiconductors
Package outline drawings
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT340-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08
95-02-04
MO-150AG
19
o
Philips Semiconductors
Package outline drawings
TSSOP
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
20
o
Philips Semiconductors
Package outline drawings
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
21
o
Philips Semiconductors
Package outline drawings
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-06-16
95-02-04
MO-153AC
22
o
Philips Semiconductors
Package outline drawings
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
January 1996
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-06-16
95-02-04
MO-153AD
23
INTEGRATED CIRCUITS
Package information
Supersedes data of 2001 Nov 02
File under Integrated Circuits, IC06
2002 Aug 08
Philips Semiconductors
Package information
PACKAGE INFORMATION
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
TSSOP (PW)
PIN COUNT
74HCU04
27-1
108-1
337-1
402-1
14
74HCTU04
27-1
108-1
74HC00
27-1
108-1
337-1
402-1
14
74HCT00
27-1
108-1
337-1
402-1
14
74HC02
27-1
108-1
337-1
402-1
14
74HCT02
27-1
108-1
337-1
402-1
14
74HC03
27-1
108-1
337-1
402-1
14
74HCT03
27-1
108-1
337-1
402-1
14
74HC04
27-1
108-1
337-1
402-1
14
74HCT04
27-1
108-1
337-1
402-1
14
74HC08
27-1
108-1
337-1
402-1
14
74HCT08
27-1
108-1
337-1
402-1
14
74HC10
27-1
108-1
337-1
402-1
14
74HCT10
27-1
108-1
337-1
402-1
14
74HC42
38-4
109-1
16
74HCT42
38-4
109-1
16
74HC107
27-1
108-1
337-1
402-1
14
74HCT107
27-1
108-1
337-1
402-1
14
74HC109
38-4
109-1
74HCT109
38-4
109-1
338-1
74HC11
27-1
108-1
337-1
402-1
14
74HCT11
27-1
108-1
337-1
402-1
14
74HC112
38-4
109-1
338-1
403-1
16
74HCT112
38-4
109-1
338-1
403-1
16
74HC123
38-4
109-1
338-1
403-1
16
74HCT123
38-4
109-1
338-1
403-1
16
74HC125
27-1
108-1
337-1
402-1
14
74HCT125
27-1
108-1
337-1
402-1
14
74HC126
27-1
108-1
337-1
402-1
14
74HCT126
27-1
108-1
337-1
402-1
14
74HC132
27-1
108-1
337-1
402-1
14
74HCT132
27-1
108-1
337-1
402-1
14
74HC133
27-1
108-1
16
74HCT133
27-1
108-1
16
74HC137
38-4
109-1
74HCT137
38-4
109-1
74HC138
38-4
109-1
338-1
403-1
16
74HCT138
38-4
109-1
338-1
403-1
16
74HC139
38-4
109-1
338-1
403-1
16
2002 Aug 08
14
16
16
338-1
16
16
2
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
TSSOP (PW)
PIN COUNT
74HCT139
38-4
109-1
338-1
403-1
16
74HC14
27-1
108-1
337-1
402-1
14
74HCT14
27-1
108-1
337-1
402-1
14
74HC147
38-4
109-1
338-1
16
74HCT147
38-4
109-1
338-1
16
74HC151
38-4
109-1
338-1
403-1
16
74HCT151
38-4
109-1
338-1
403-1
16
74HC153
38-4
109-1
338-1
403-1
16
74HCT153
38-4
109-1
338-1
403-1
16
74HC154
101-1
137-1
340-1
355-1
24
74HCT154
101-1
137-1
340-1
355-1
24
74HC157
38-4
109-1
338-1
403-1
16
74HCT157
38-4
109-1
338-1
403-1
16
74HC158
38-4
109-1
74HCT158
38-4
109-1
74HC160
38-4
109-1
74HCT160
38-4
109-1
74HC161
38-4
109-1
338-1
403-1
16
74HCT161
38-4
109-1
338-1
403-1
16
74HC162
38-4
109-1
16
74HCT162
38-4
109-1
16
74HC163
38-4
109-1
338-1
403-1
16
74HCT163
38-4
109-1
338-1
403-1
16
74HC164
27-1
108-1
337-1
402-1
14
74HCT164
27-1
108-1
337-1
402-1
14
74HC165
38-4
109-1
338-1
403-1
16
74HCT163
38-4
109-1
338-1
403-1
16
74HC164
27-1
108-1
337-1
402-1
16
74HCT164
27-1
108-1
337-1
402-1
16
74HC165
38-4
109-1
338-1
403-1
16
74HCT165
38-4
109-1
338-1
403-1
16
74HC166
38-4
109-1
338-1
403-1
16
74HCT166
38-4
109-1
338-1
74HC173
38-4
109-1
338-1
74HCT173
38-4
109-1
338-1
74HC174
38-4
109-1
338-1
403-1
16
74HCT174
38-4
109-1
338-1
403-1
16
74HC175
38-4
109-1
338-1
403-1
16
74HCT175
38-4
109-1
338-1
403-1
16
2002 Aug 08
16
16
338-1
16
16
3
16
403-1
16
16
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
74HC181
101-1
137-1
24
74HCT181
101-1
137-1
24
74HC182
38-4
109-1
16
74HCT182
38-4
109-1
16
74HC190
38-4
109-1
16
74HCT190
38-4
109-1
16
74HC191
38-4
109-1
74HCT191
38-4
109-1
74HC192
38-4
109-1
74HCT192
38-4
109-1
74HC193
38-4
109-1
338-1
74HCT193
38-4
109-1
338-1
16
74HC194
38-4
109-1
338-1
16
74HCT194
38-4
109-1
338-1
16
74HC195
38-4
109-1
338-1
16
74HCT195
38-4
109-1
338-1
16
74HC20
27-1
108-1
337-1
74HCT20
27-1
108-1
337-1
14
74HC21
27-1
108-1
337-1
14
74HCT21
27-1
108-1
337-1
14
74HC221
38-4
109-1
338-1
16
74HCT221
38-4
109-1
338-1
16
74HC237
38-4
109-1
338-1
16
74HCT237
38-4
109-1
338-1
16
74HC238
38-4
109-1
338-1
403-1
16
74HCT238
38-4
109-1
338-1
403-1
16
74HC240
146-1
163-1
339-1
360-1
20
74HCT240
146-1
163-1
339-1
360-1
20
74HC241
146-1
163-1
339-1
360-1
20
74HCT241
146-1
163-1
339-1
360-1
20
74HC242
27-1
108-1
337-1
74HCT242
27-1
108-1
74HC243
27-1
108-1
337-1
14
74HCT243
27-1
108-1
337-1
14
74HC244
146-1
163-1
339-1
360-1
20
74HCT244
146-1
163-1
339-1
360-1
20
74HC245
146-1
163-1
339-1
360-1
20
74HCT245
146-1
163-1
339-1
360-1
20
2002 Aug 08
SSOP (DB)
338-1
TSSOP (PW)
403-1
PIN COUNT
16
16
338-1
16
16
403-1
402-1
16
14
14
14
4
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
TSSOP (PW)
PIN COUNT
74HC251
38-4
109-1
338-1
403-1
16
74HCT251
38-4
109-1
338-1
403-1
16
74HC253
38-4
109-1
338-1
16
74HCT253
38-4
109-1
338-1
16
74HC257
38-4
109-1
338-1
403-1
16
74HCT257
38-4
109-1
338-1
403-1
16
74HC258
38-4
109-1
338-1
74HCT258
38-4
109-1
74HC259
38-4
109-1
338-1
403-1
16
74HCT259
38-4
109-1
338-1
403-1
16
74HC27
38-4
109-1
338-1
403-1
16
74HCT27
38-4
109-1
338-1
403-1
16
74HC273
146-1
163-1
339-1
360-1
20
74HCT273
146-1
163-1
339-1
360-1
20
74HC280
27-1
108-1
337-1
402-1
14
74HCT280
27-1
108-1
402-1
14
74HC283
38-4
109-1
338-1
403-1
16
74HCT283
38-4
109-1
338-1
403-1
16
74HC297
38-4
109-1
16
74HCT297
38-4
109-1
16
74HC299
146-1
163-1
339-1
20
74HCT299
146-1
163-1
339-1
20
74HC30
27-1
108-1
337-1
402-1
14
74HCT30
27-1
108-1
337-1
402-1
14
74HC32
27-1
108-1
337-1
402-1
14
74HCT32
27-1
108-1
337-1
402-1
14
74HC354
146-1
163-1
20
74HCT354
146-1
163-1
20
74HC356
146-1
163-1
20
74HCT356
146-1
163-1
20
74HC365
38-4
109-1
338-1
74HCT365
38-4
109-1
338-1
74HC366
38-4
109-1
74HCT366
38-4
109-1
338-1
74HC367
38-4
109-1
338-1
403-1
16
74HCT367
38-4
109-1
338-1
403-1
16
74HC368
38-4
109-1
338-1
74HCT368
38-4
109-1
338-1
2002 Aug 08
16
16
403-1
16
16
16
5
16
16
403-1
16
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
TSSOP (PW)
PIN COUNT
74HC373
146-1
163-1
339-1
360-1
20
74HCT373
146-1
163-1
339-1
360-1
20
74HCT374
146-1
163-1
339-1
360-1
20
74HC374
146-1
163-1
339-1
360-1
20
74HCT377
146-1
163-1
339-1
360-1
20
74HC377
146-1
163-1
339-1
360-1
20
74HC390
38-4
109-1
338-1
403-1
16
74HCT390
38-4
109-1
338-1
74HC393
27-1
108-1
337-1
402-1
14
74HCT393
27-1
108-1
337-1
402-1
14
74HC4002
27-1
108-1
337-1
402-1
14
74HCT4002
27-1
108-1
337-1
74HC4015
38-4
109-1
16
74HCT4015
38-4
109-1
16
74HC4016
38-4
109-1
16
74HCT4016
38-4
109-1
16
74HC4017
38-4
109-1
16
74HCT4017
38-4
109-1
16
74HC40102
38-4
109-1
16
74HCT40102
38-4
109-1
16
74HC40103
38-4
109-1
338-1
74HCT40103
38-4
109-1
338-1
74HC40104
38-4
109-1
16
74HCT40104
38-4
109-1
16
74HC40105
38-4
109-1
338-1
74HCT40105
38-4
109-1
338-1
74HC4020
38-4
109-1
338-1
403-1
16
74HCT4020
38-4
109-1
338-1
403-1
16
74HC4024
27-1
108-1
337-1
74HCT4024
27-1
108-1
74HC4040
38-4
109-1
74HCT4024
27-1
108-1
74HC4046A
38-4
109-1
338-1
74HCT4046A
38-4
109-1
338-1
74HC4049
38-4
109-1
16
74HCT4049
38-4
109-1
16
74HC4059
101-1
137-1
24
74HCT4059
101-1
137-1
24
2002 Aug 08
16
14
403-1
16
16
403-1
16
16
14
14
338-1
403-1
16
16
6
403-1
16
16
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
TSSOP (PW)
PIN COUNT
74HC4050
38-4
109-1
338-1
403-1
16
74HCT4050
38-4
109-1
74HC4051
38-4
109-1
338-1
74HCT4051
38-4
109-1
338-1
74HC4052
38-4
109-1
338-1
74HCT4052
38-4
109-1
338-1
74HC4053
38-4
109-1
338-1
403-1
16
74HCT4053
38-4
109-1
338-1
403-1
16
74HC4060
38-4
109-1
338-1
403-1
16
74HCT4060
38-4
109-1
338-1
74HCT4066
101-1
137-1
340-1
355-1
24
74HC4066
101-1
137-1
340-1
355-1
24
74HC4067
101-1
137-1
340-1
355-1
24
74HCT4067
101-1
137-1
340-1
355-1
24
74HC4075
27-1
108-1
337-1
74HCT4075
27-1
108-1
337-1
74HC4094
38-4
109-1
338-1
16
74HCT4094
38-4
109-1
338-1
16
74HC423
38-4
109-1
16
74HCT423
38-4
109-1
16
74HC4316
38-4
109-1
338-1
403-1
16
74HCT4316
38-4
109-1
338-1
403-1
16
74HC4351
146-1
163-1
339-1
20
74HCT4351
146-1
163-1
339-1
20
74HC4352
146-1
163-1
20
74HCT4352
146-1
163-1
20
74HC4510
38-4
109-1
16
74HCT4510
38-4
109-1
16
74HC4511
38-4
109-1
16
74HCT4511
38-4
109-1
16
74HC4515
101-1
137-1
24
74HCT4515
101-1
137-1
24
74HC4516
38-4
109-1
16
74HCT4516
38-4
109-1
16
74HC4514
101-1
137-1
2002 Aug 08
16
340-1
7
403-1
16
16
403-1
16
16
16
14
402-1
14
24
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
TSSOP (PW)
PIN COUNT
74HCT4514
101-1
137-1
340-1
74HC4518
38-4
109-1
16
74HCT4518
38-4
109-1
16
74HC4520
38-4
109-1
338-1
74HCT4520
38-4
109-1
338-1
74HC4538
38-4
109-1
338-1
403-1
16
74HCT4538
38-4
109-1
338-1
403-1
16
74HC4543
38-4
109-1
16
74HCT4543
38-4
109-1
16
74HC533
146-1
163-1
20
74HCT533
146-1
163-1
20
74HC534
146-1
163-1
20
74HCT534
146-1
163-1
20
74HC540
146-1
163-1
339-1
74HCT540
146-1
163-1
339-1
74HC541
146-1
163-1
339-1
360-1
20
74HCT541
146-1
163-1
339-1
360-1
20
74HC5555
38-4
109-1
16
74HCT5555
38-4
109-1
16
74HC563
146-1
163-1
20
74HCT563
146-1
163-1
74HC564
146-1
163-1
20
74HCT564
146-1
163-1
20
74HC573
146-1
163-1
339-1
360-1
20
74HCT573
146-1
163-1
339-1
360-1
20
74HC574
146-1
163-1
339-1
360-1
20
74HCT574
146-1
163-1
339-1
360-1
20
74HC58
27-1
108-1
337-1
74HC583
38-4
109-1
16
74HCT583
38-4
109-1
16
74HC594
38-4
109-1
74HCT594
38-4
109-1
74HC595
38-4
109-1
338-1
403-1
16
74HCT595
38-4
109-1
338-1
403-1
16
74HC597
38-4
109-1
338-1
403-1
16
74HCT597
38-4
109-1
338-1
24
403-1
16
16
20
20
339-1
20
14
338-1
16
16
16
74HC6323A
96-1
8
74HCT6323A
96-1
8
2002 Aug 08
8
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
74HC640
146-1
163-1
339-1
20
74HCT640
146-1
163-1
339-1
20
74HC643
146-1
163-1
20
74HCT643
146-1
163-1
20
74HC646
101-1
137-1
340-1
24
74HCT646
101-1
137-1
340-1
24
74HC648
101-1
137-1
24
74HCT648
101-1
137-1
24
74HC652
101-1
137-1
24
74HCT652
101-1
137-1
24
74HC670
38-4
109-1
338-1
16
74HCT670
38-4
109-1
338-1
16
74HC688
146-1
163-1
339-1
360-1
20
74HCT688
146-1
163-1
339-1
360-1
20
74HC7014
27-1
108-1
14
74HCT7014
27-1
108-1
14
74HC7030
117-1
136-1
28
74HCT7030
117-1
136-1
28
74HC7046A
38-4
109-1
74HCT7046A
38-4
109-1
16
74HC7080
146-1
163-1
20
74HCT7080
146-1
163-1
20
74HC7132
27-1
108-1
14
74HCT7132
27-1
108-1
14
74HC7245
146-1
163-1
20
74HCT7245
146-1
163-1
20
74HC7266
27-1
108-1
74HCT7266
27-1
108-1
74HC73
27-1
108-1
74HCT73
27-1
108-1
74HC74
27-1
108-1
74HCT74
27-1
108-1
74HC7403
38-4
109-1
16
74HCT7403
38-4
109-1
16
74HC7404
102-1
163-1
18 / 20
74HCT7404
102-1
163-1
18 / 20
74HC75
38-4
109-1
338-1
74HCT75
38-4
109-1
338-1
2002 Aug 08
TSSOP (PW)
338-1
PIN COUNT
16
337-1
14
14
14
337-1
14
14
337-1
9
402-1
403-1
14
16
16
Philips Semiconductors
Package information
PART NUMBER
DIL (N)
SO (D)
SSOP (DB)
74HC7540
146-1
163-1
339-1
74HCT7540
146-1
163-1
74HC7541
146-1
163-1
74HCT7541
146-1
163-1
20
74HC7597
38-4
109-1
16
74HC7597
38-4
109-1
16
74HC7731
38-4
109-1
16
74HCT7731
38-4
109-1
16
74HC85
38-4
109-1
338-1
74HCT85
38-4
109-1
338-1
74HC86
27-1
108-1
337-1
402-1
14
74HC86
27-1
108-1
337-1
402-1
14
74HC9014
146-1
163-1
20
74HCT9014
146-1
163-1
20
74HC9015
146-1
163-1
74HCT9015
146-1
163-1
20
74HC9046A
38-4
109-1
16
74HCT9046A
38-4
109-1
74HC9114
146-1
163-1
20
74HCT9114
146-1
163-1
20
74HC9115
146-1
163-1
20
74HCT9115
146-1
163-1
20
74HC93
27-1
108-1
74HCT93
27-1
108-1
14
74HC9323A
96-1
8
74HCT9323A
96-1
8
74HCT1284
146-1
PIN COUNT
20
20
339-1
20
403-1
403-1
337-1
163-1
339-1
10
16
16
360-1
2002 Aug 08
TSSOP (PW)
20
16
14
360-1
20
Philips Semiconductors
FAMILY
SPECIFICATIONS
HCMOS family characteristics
A subset of the family, designated as XX74HCTXXXXX,
with the same features and functions as the “HC-types”,
will operate at standard TTL power supply voltage
(5 V ± 10%) and logic input levels (0.8 to 2.0 V) for use as
pin-to-pin compatible CMOS replacements to reduce
power consumption without loss of speed. These types are
also suitable for converted switching from TTL to CMOS.
GENERAL
These family specifications cover the common electrical
ratings and characteristics of the entire HCMOS
74HC/HCT/HCU family, unless otherwise specified in the
individual device data sheet.
INTRODUCTION
The 74HC/HCT/HCU high-speed Si-gate CMOS logic
family combines the low power advantages of the
HE4000B family with the high speed and drive capability of
the low power Schottky TTL (LSTTL).
Another subset, the XX74HCUXXXXX, consists of
single-stage unbuffered CMOS compatible devices for
application in RC or crystal controlled oscillators and other
types of feedback circuits which operate in the linear
mode.
The family will have the same pin-out as the 74 series and
provide the same circuit functions.
HANDLING MOS DEVICES
Inputs and outputs are protected against electrostatic
effects in a wide variety of device-handling situations.
However, to be totally safe, it is desirable to take handling
precautions into account
(see also “HANDLING PRECAUTIONS”).
In these families are included several HE4000B family
circuits which do not have TTL counterparts, and some
special circuits.
The basic family of buffered devices, designated as
XX74HCXXXXX, will operate at CMOS input logic levels
for high noise immunity, negligible typical quiescent supply
and input current. It is operated from a power supply of
2 to 6 V.
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT
74HC
74HCT
SYMBOL PARAMETER
UNIT CONDITIONS
min. typ.
max.
min. typ. max.
6.0
4.5
VCC
DC supply voltage
2.0
5.0
VI
DC input voltage range
0
VCC
VO
DC output voltage range
0
Tamb
operating ambient temperature range −40
Tamb
operating ambient temperature range −40
tr, tf
input rise and fall times except for
Schmitt-trigger inputs
5.0
5.5
V
0
VCC
V
VCC
0
VCC
V
+85
−40
+85
°C
+125
−40
+125
°C
500
ns
1000
6.0
500
400
see DC and AC
CHAR. per device
VCC = 2.0 V
6.0
VCC = 4.5 V
VCC = 6.0 V
Note
1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating
supply voltage is 10 V.
March 1988
2
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR 74HCU
74HCU
SYMBOL
PARAMETER
UNIT CONDITIONS
min. typ. max.
VCC
DC supply voltage
2.0
5.0
6.0
V
VI
DC input voltage range
0
VCC
V
VO
DC output voltage range
0
VCC
V
Tamb
operating ambient temperature range
−40
+85
°C
Tamb
operating ambient temperature range
−40
+125 °C
see DC and AC
CHAR. per device
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
MIN. MAX.
UNIT CONDITIONS
VCC
DC supply voltage
−0.5
+7
V
±IIK
DC input diode current
20
mA
±IOK
DC output diode current
20
mA
±IO
DC output source or sink
current
±ICC;
±IGND
for VI < −0.5 or VI > VCC + 0.5 V
for VO < −0.5 or VO > VCC + 0.5 V
for −0.5 V < VO < VCC + 0.5 V
standard outputs
25
mA
bus driver outputs
35
mA
50
mA
DC VCC or GND current for
types with:
standard outputs
bus driver outputs
Tstg
storage temperature range
Ptot
power dissipation per package
−65
70
mA
+150
°C
for temperature range: −40 to +125 °C
74HC/HCT/HCU
plastic DIL
750
mW
above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO)
500
mW
above +70 °C: derate linearly with 8 mW/K
Note
1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating
supply voltage is 11 V.
March 1988
3
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
DC CHARACTERISTICS FOR 74HC
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
VIH
VIL
VOH
VOH
VOH
VOL
VOL
VOL
HIGH level input
voltage
1.5
1.5
3.15 2.4
3.15
3.15
4.5
4.2
4.2
4.2
6.0
HIGH level output
voltage
all outputs
HIGH level output
voltage
standard outputs
HIGH level output
voltage
bus driver outputs
LOW level output
voltage
all outputs
LOW level output
voltage
standard outputs
LOW level output
voltage
bus driver outputs
3.2
VI
OTHER
max.
1.5
LOW level input
voltage
1.2
UNIT V
CC
(V)
V
V
2.0
0.8
0.5
0.5
0.5
2.1
1.35
1.35
1.35
4.5
2.8
1.8
1.8
1.8
6.0
V
2.0
1.9
2.0
1.9
1.9
4.4
4.5
4.4
4.4
4.5
5.9
6.0
5.9
5.9
6.0
3.98 4.32
3.84
3.7
5.48 5.81
5.34
5.2
3.98 4.32
3.84
3.7
5.48 5.81
5.34
5.2
V
2.0
4.5
6.0
V
4.5
6.0
0
0.1
0.1
0.1
0
0.1
0.1
0.1
0
0.1
0.1
0.1
0.15 0.26
0.33
0.4
0.16 0.26
0.33
0.4
0.15 0.26
0.33
0.4
0.16 0.26
0.33
0.4
V
2.0
4.5
6.0
V
4.5
6.0
V
4.5
6.0
VIH
or
VIL
−IO = 20 µA
−IO = 20 µA
−IO = 20 µA
−IO = 4.0 mA
VIH
or
VIL
−IO = 5.2 mA
VIH
or
VIL
−IO = 7.8 mA
−IO = 6.0 mA
VIH
or
VIL
IO = 20 µA
VIH
or
VIL
IO = 4.0 mA
VIH
or
VIL
IO = 6.0 mA
IO = 20 µA
IO = 20 µA
IO = 5.2 mA
IO = 7.8 mA
±II
input leakage current
0.1
1.0
1.0
µA
6.0
VCC
or
GND
±IOZ
3-state OFF-state
current
0.5
5.0
10.0
µA
6.0
VIH
or
VIL
ICC
quiescent supply
current
SSI
2.0
20.0
40.0
µA
6.0
flip-flops
4.0
40.0
80.0
6.0
MSI
8.0
80.0
160.0
6.0
VCC IO = 0
or
IO = 0
GND
IO = 0
LSI
50.0
500
1000
6.0
IO = 0
March 1988
4
VO = VCC
or GND
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125
UNIT
VCC
(V)
VI
OTHER
min. typ. max. min. max. min. max.
2.0
1.6
2.0
2.0
V
4.5
to
5.5
V
4.5
to
5.5
4.4
V
4.5
VIH
or
VIL
−IO = 20 µA
3.84
3.7
V
4.5
VIH
or
VIL
−IO = 4.0 mA
3.84
3.7
V
4.5
VIH
or
VIL
−IO = 6.0 mA
0.1
V
4.5
VIH
or
VIL
IO = 20 µA
0.33
0.4
V
4.5
VIH
or
VIL
IO = 4.0 mA
0.26
0.33
0.4
V
4.5
VIH
or
VIL
IO = 6.0 mA
input leakage
current
0.1
1.0
1.0
µA
5.5
VCC
or
GND
±IOZ
3-state OFF-state
current
0.5
5.0
10.0
µA
5.5
VIH
or
VIL
VO = VCC or
GND per input
pin;
other inputs at
VCC or GND;
IO = 0
ICC
quiescent supply
current
SSI
2.0
20.0
40.0
µA
5.5
IO = 0
flip-flops
4.0
40.0
80.0
MSI
8.0
80.0
160.0
5.5
VCC
or
GND
LSI
50.0
500
1000
5.5
VIH
HIGH level input
voltage
VIL
LOW level input
voltage
VOH
HIGH level output
voltage
all outputs
4.4
4.5
4.4
VOH
HIGH level output
voltage
standard outputs
3.98
4.32
VOH
HIGH level output
voltage
bus driver outputs
3.98
4.32
VOL
LOW level output
voltage
all outputs
0
0.1
0.1
VOL
LOW level output
voltage
standard outputs
0.15
0.26
VOL
LOW level output
voltage
bus driver outputs
0.16
±II
March 1988
1.2
0.8
0.8
5
0.8
5.5
IO = 0
IO = 0
IO = 0
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25
−40 to +85 −40 to +125
UNIT
VCC
(V)
VI
OTHER
min. typ. max. min. max. min. max.
∆ICC
additional quiescent
supply current per
input pin for unit load
coefficient is 1
(note 1)
100
450
360
490
µA
4.5
to
5.5
VCC
other inputs at
−2.1 V VCC or GND;
IO = 0
Note
1. The additional quiescent supply current per input is determined by the ∆ICC unit load, which has to be multiplied by
the unit load coefficient as given in the individual data sheets. For dual supply systems the theoretical worst-case
(VI = 2.4 V; VCC = 5.5 V) specification is: ∆ICC = 0.65 mA (typical) and 1.8 mA (maximum) across temperature.
March 1988
6
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
DC CHARACTERISTICS FOR 74HCU
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCU
SYMBOL PARAMETER
+25
−40 to +85
−40 to +125
UNIT V
CC
(V)
VI
OTHER
min. typ. max. min. max. min. max.
VIH
VIL
VOH
VOH
VOL
VOL
HIGH level input
voltage
1.7
1.4
1.7
1.7
3.6
2.6
3.6
3.6
4.5
4.8
3.4
4.8
4.8
6.0
LOW level input
voltage
HIGH level output
voltage
HIGH level output
voltage
LOW level output
voltage
LOW level output
voltage
V
V
2.0
0.6
0.3
0.3
0.3
1.9
0.9
0.9
0.9
4.5
2.6
1.2
1.2
1.2
6.0
V
2.0
1.8
2.0
1.8
1.8
4.0
4.5
4.0
4.0
4.5
5.5
6.0
5.5
5.5
6.0
3.98 4.32
3.84
3.7
5.48 5.81
5.34
5.2
V
2.0
4.5
6.0
0
0.2
0.2
0.2
0
0.5
0.5
0.5
V
4.5
0
0.5
0.5
0.5
6.0
0.15 0.26
0.33
0.4
0.16 0.26
0.33
0.4
V
2.0
4.5
6.0
VIH
or
VIL
−IO = 20 µA
VCC
or
GND
−IO = 4.0 mA
VIH
or
VIL
IO = 20 µA
VCC
or
GND
IO = 4.0 mA
±II
input leakage current
0.1
1.0
1.0
µA
6.0
VCC
or
GND
ICC
quiescent supply
current SSI
2.0
20.0
40.0
µA
6.0
VCC
or
GND
March 1988
7
−IO = 20 µA
−IO = 20 µA
−IO = 5.2 mA
IO = 20 µA
IO = 20 µA
IO = 5.2 mA
IO = 0
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
tTHL/ tTLH
tTHL/ tTLH
output transition time
standard outputs
output transition time
bus driver outputs
UNIT
VCC
(V)
ns
2.0
WAVEFORMS
max.
19
75
95
110
7
15
19
22
4.5
6
13
16
19
6.0
14
60
75
90
5
12
15
18
4.5
4
10
13
15
6.0
ns
2.0
Figs 3 and 4
Figs 3 and 4
AC CHARACTERISTICS FOR 74HCU
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCU
SYMBOL PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
tTHL/ tTLH
output transition time
UNIT
VCC
(V)
ns
2.0
WAVEFORMS
max.
19
75
95
110
7
15
19
22
4.5
6
13
16
19
6.0
Fig.1
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
UNIT
VCC
(V)
WAVEFORMS
max.
tTHL/ tTLH
output transition time
standard outputs
7
15
19
22
ns
4.5
Figs 8 and 9
tTHL/ tTLH
output transition time
bus driver outputs
5
12
15
18
ns
4.5
Figs 8 and 9
March 1988
8
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
HCU TYPES
AC waveforms 74HCU
tr
handbook, halfpage
tf
VCC
90%
INPUT
50%
10%
GND
tPHL
tPLH
90%
50%
OUTPUT
10%
tTHL
tTLH
MGK564
Fig.1 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Test circuit for 74HCU
VCC
handbook, halfpage
PULSE
GENERATOR
VI
VO
D.U.T
RT
CL
50 pF
MGK565
CL
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance Zo of
the pulse generator.
Fig.2 Test circuit.
March 1988
9
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
HC TYPES
AC waveforms 74HC
tr
handbook, halfpage
tf
VCC
90%
INPUT
50%
10%
GND
tPHL
tPLH
90%
50%
OUTPUT
10%
tTHL
tTLH
MGK564
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
AC waveforms 74HC
1/fmax
tf
handbook, full pagewidth
tr
VCC
90%
CLOCK
INPUT
50%
10 %
GND
tWH
tWL
th
th
VCC
DATA
INPUT
50%
GND
tsu
tsu
tTLH
tTHL
90%
OUTPUT
50%
10%
trem
SET,
RESET,
PRESET
INPUT
tPLH
tPHL
VCC
50%
GND
MGK569
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
(2) For AC measurements: tr = tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.4
March 1988
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
10
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
Test circuit for 74HC
VCC
handbook, halfpage
VI
PULSE
GENERATOR
VO
D.U.T
RT
CL
50 pF
MGK565
CL
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance Zo of
the pulse generator.
Fig.5 Test circuit.
AC waveforms 74HC (continued)
tf
handbook, full pagewidth
tr
VCC
90%
OUTPUT
ENABLE
50%
10%
GND
tPLZ
OUTPUT
LOW-to-OFF
OFF-to-LOW
tPZL
50%
10%
tPHZ
90%
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
MGK562
tPZH
50%
outputs
enabled
outputs
disabled
Fig.6 Propagation delays of 3-state outputs.
March 1988
11
outputs
enabled
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
Test circuit for 74HC
VCC
handbook, full pagewidth
PULSE
GENERATOR
VCC
VI
VO
RL = 1 kΩ
D.U.T
RT
CL
50 pF
MGK563
Switch position
TEST
SWITCH
tPZH
tPZL
tPHZ
tPLZ
GND
VCC
GND
VCC
Note
1. For open-drain N-channel outputs tPLZ and tPZL are applicable.
CL
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance Zo of
the pulse generator.
Fig.7 Test circuit for 3-state outputs.
HCT TYPES
AC waveforms 74HCT
tr
handbook, halfpage
tf
3V
90%
INPUT
1.3 V
10%
GND
tPHL
tPLH
90%
1.3 V
OUTPUT
10%
tTHL
tTLH
MGK567
Fig.8 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
March 1988
12
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC waveforms 74HCT
1/fmax
tf
handbook, full pagewidth
tr
3V
90%
CLOCK
INPUT
1.3 V
10%
GND
tWH
tWL
th
th
3V
DATA
INPUT
1.3 V
GND
tsu
tsu
tTLH
tTHL
90%
OUTPUT
1.3 V
10%
trem
SET,
RESET,
PRESET
INPUT
tPLH
tPHL
3V
1.3 V
GND
MGK568
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals
(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual
active levels of the forcing signals are specified in the individual device data sheet.
(2) For AC measurements: tr = tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.9
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
Test circuit for 74HCT
VCC
handbook, halfpage
PULSE
GENERATOR
VI
VO
D.U.T
RT
CL
50 pF
MGK565
CL
=
load capacitance including jig and probe capacitance (see AC
CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance Zo of
the pulse generator.
Fig.10 Test circuit.
March 1988
13
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC waveforms 74HCT (continued)
tf
handbook, full pagewidth
tr
90%
OUTPUT
ENABLE
1.3 V
10%
tPLZ
tPZL
OUTPUT
LOW-to-OFF
OFF-to-LOW
1.3 V
10%
tPHZ
tPZH
90%
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
1.3 V
outputs
enabled
MGK566
outputs
enabled
outputs
disabled
Fig.11 Propagation delays of 3-state outputs.
Test circuit for 74HCT
VCC
handbook, full pagewidth
PULSE
GENERATOR
VI
VCC
VO
RL = 1 kΩ
D.U.T
RT
CL
50 pF
MGK563
Switch position
TEST
SWITCH
tPZH
tPZL
tPHZ
tPLZ
GND
VCC
GND
VCC
Note
1. For open-drain N-channel outputs tPLZ and tPZL are applicable.
CL
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance Zo of
the pulse generator.
Fig.12 Test circuit for 3-state outputs.
March 1988
14
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
conditions under which the limits in the “DC
CHARACTERISTICS” and “AC CHARACTERISTICS”
tables will be met. The table should not be seen as a set of
limits guaranteed by the manufacturer, but as the
conditions used to test the devices and guarantee that
they will then meet the limits in the DC and AC
CHARACTERISTICS tables.
DATA SHEET SPECIFICATION GUIDE
INTRODUCTION
The 74HCMOS data sheets have been designed for
ease-of-use. A minimum of cross-referencing for more
information is needed.
TYPICAL PROPAGATION DELAY AND FREQUENCY
DC CHARACTERISTICS
The typical propagation delays listed at the top of the data
sheets are the average of tPLH and tPHL for the longest data
path through the device with a 15 pF load.
The “DC CHARACTERISTICS” table reflects the DC limits
used during testing. The values published are guaranteed.
The threshold values of VIH and VIL can be tested by the
user. If VIH and VIL are applied to the inputs, the output
voltages will be those published in the “DC
CHARACTERISTICS” table. There is a tendency, by
some, to use the published VIH and VIL thresholds to test a
device for functionality in a “function-table exercizer”
mode. This frequently causes problems because of the
noise present at the test head of automated test
equipment with cables up to 1 metre. Parametric tests,
such as those used for the output levels under the VIH and
VIL conditions are done fairly slowly, in the order of
milliseconds, so that there is no noise at the inputs when
the outputs are measured. But in functionality testing, the
outputs are measured much faster, so there can be noise
on the inputs, before the device has assumed its final and
correct output state. Thus, never use VIH and VIL to test the
functionality of any HCMOS device type; instead, use input
voltages of VCC (for the HIGH state) and 0 V (for the LOW
state). In no way does this imply that the devices are
noise-sensitive in the final system.
For clocked devices, the maximum frequency of operation
is also given. The typical operating frequency is the
maximum device operating frequency with a 50% duty
factor and no constraints on tr and tf.
LOGIC SYMBOLS
Two logic symbols are given for each device - the
conventional one (Logic Symbol) which explicitly shows
the internal logic (except for complex logic) and the IEC
Logic Symbol as developed by the IEC (International
Electrotechnical Commission).
The IEC has been developing a very powerful symbolic
language that can show the relationship of each input of a
digital logic current to each output without explicitly
showing the internal logic.
Internationally, Working Group 2 of IEC Technical
Committee TC-3 has prepared a new document
(Publication 617-12) which supersedes
Publication 117-15, published in 1972.
In the data sheets, it may appear strange that the typical
VIL is higher than the maximum VIL. However, this is
because VILmax is the maximum VIL (guaranteed) for all
devices that will be recognized as a logic LOW. However,
typically a higher VIL will also be recognized as a logic
LOW. Conversely, the typical VIH is lower than its minimum
guaranteed level.
RATINGS
The “RATINGS” table (Limiting values in accordance with
the Absolute Maximum System - IEC134) lists the
maximum limits to which the device can be subjected
without damage. This doesn’t imply that the device will
function at these extreme conditions, only that, when these
conditions are removed and the device operated within the
Recommended Operating Conditions, it will still be
functional and its useful life won’t have been shortened.
For 74HCMOS, unlike TTL, no output HIGH short-circuit
current is specified. The use of this current, for example, to
calculate propagation delays with capacitive loads, is
covered by the HCMOS graphs showing the output drive
capability and those showing the dependence of
propagation delay on load capacitance.
The maximum rated supply voltage of 7 V is well below the
typical breakdown voltage of 18 V.
The quiescent supply current ICC is the leakage current of
all the reversed-biased diodes and the OFF-state MOS
transistors. It is measured with the inputs at VCC or GND
and is typically a few nA.
RECOMMENDED OPERATING CONDITIONS
The “RECOMMENDED OPERATING CONDITIONS”
table lists the operating ambient temperature and the
March 1988
15
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC CHARACTERISTICS
The “AC CHARACTERISTICS” table lists the guaranteed
limits when a device is tested under the conditions given in
the AC Test Circuits and Waveforms section.
TEST CIRCUITS
Good high-frequency wiring practices should be used in
test circuits. Capacitor leads should be as short as
possible to minimize ripples on the output waveform
transitions and undershoot. Generous ground metal
(preferably a ground-plane) should be used for the same
reasons. A VCC decoupling capacitor should be provided
at the test socket, also with short leads. Input signals
should have rise and fall times of 6 ns, a signal swing of
0 V to VCC for 74HC and 0 V to 3 V for 74HCT; a 1.0 MHz
square wave is recommended for most propagation delay
tests. The repetition rate must be increased for testing
fmax. Two pulse generators are usually required for testing
such parameters as set-up time, hold time and removal
time. fmax is also tested with 6 ns input rise and fall times,
with a 50% duty factor, but for typical fmax as high as
60 MHz, there are no constraints on rise and fall times.
March 1988
16
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
DEFINITIONS OF SYMBOLS AND TERMS USED IN
HCMOS DATA SHEETS
Currents
Positive current is defined as conventional current flow
into a device.
Negative current is defined as conventional current flow
out of a device.
ICC
Quiescent power supply current; the current
flowing into the VCC supply terminal.
∆ICC
Additional quiescent supply current per input
pin at a specified input voltage and VCC.
IGND
Quiescent power supply current; the current
flowing into the GND terminal.
II
Input leakage current; the current flowing into a
device at a specified input voltage and VCC.
IIK
Input diode current; the current flowing into a
device at a specified input voltage.
IO
Output source or sink current: the current
flowing into a device at a specified output
voltage.
VIL
LOW level input voltage; the range of input
voltages that represents a logic LOW level in
the system.
VOH
HIGH level output voltage; the range of
voltages at an output terminal with a specified
output loading and supply voltage. Device
inputs are conditioned to establish a HIGH level
at the output.
VOL
LOW level output voltage; the range of voltages
at an output terminal with a specified output
loading and supply voltage. Device inputs are
conditioned to establish a LOW level at the
output.
VT+
Trigger threshold voltage; positive-going signal.
VT−
Trigger threshold voltage; negative-going
signal.
Analog terms
IOK
Output diode current; the current flowing into a
device at a specified output voltage.
RON
IOZ
OFF-state output current; the leakage current
flowing into the output of a 3-state device in the
OFF-state, when the output is connected to
VCC or GND.
ON-resistance; the effective ON-state
resistance of an analog switch, at a specified
voltage across the switch and output load.
∆RON
∆ON-resistance; the difference in
ON-resistance between any two switches of an
analog device at a specified voltage across the
switch and output load.
IS
Analog switch leakage current; the current
flowing into an analog switch at a specified
voltage across the switch and VCC.
Capacitances
Voltages
All voltages are referenced to GND (ground), which is
typically 0 V.
GND
Supply voltage; for a device with a single
negative power supply, the most negative
power supply, used as the reference level for
other voltages; typically ground.
VCC
Supply voltage; the most positive potential on
the device.
VEE
Supply voltage; one of two (GND and VEE)
negative power supplies.
VH
Hysteresis voltage; difference between the
trigger levels, when applying a positive and a
negative-going input signal.
VIH
HIGH level input voltage; the range of input
voltages that represents a logic HIGH level in
the system.
March 1988
17
CI
Input capacitance; the capacitance measured
at a terminal connected to an input of a device.
CI/O
Input/Output capacitance; the capacitance
measured at a terminal connected to an I/O-pin
(e.g. a transceiver).
CL
Output load capacitance; the capacitance
connected to an output terminal including jig
and probe capacitance.
CPD
Power dissipation capacitance; the capacitance
used to determine the dynamic power
dissipation per logic function, when no extra
load is provided to the device.
CS
Switch capacitance; the capacitance of a
terminal to a switch of an analog device.
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC switching parameters
fi
Input frequency; for combinatorial logic devices
the maximum number of inputs and outputs
switching in accordance with the device
function table. For sequential logic devices the
clock frequency using alternate HIGH and LOW
for data input or using the toggle mode,
whichever is applicable.
fo
Output frequency; each output.
fmax
Maximum clock frequency; clock input
waveforms should have a 50% duty factor and
be such as to cause the outputs to be switching
from 10%VCC to 90%VCC in accordance with
the device function table.
th
Hold time; the interval immediately following the
active transition of the timing pulse (usually the
clock pulse) or following the transition of the
control input to its latching level, during which
interval the data to be recognized must be
maintained at the input to ensure their
continued recognition. A negative hold time
indicates that the correct logic level may be
released prior to the timing pulse and still be
recognized.
t r,
tf
Clock input rise and fall times; 10% and 90%
values.
tPHL
Propagation delay; the time between the
specified reference points, normally the 50%
points for 74HC and 74HCU devices on the
input and output waveforms and the 1.3 V
points for the 74HCT devices, with the output
changing from the defined HIGH level to the
defined LOW level.
tPLH
tPHZ
Propagation delay; the time between the
specified reference points, normally the 50%
points for 74HC and 74HCU devices on the
input and output waveforms and the 1.3 V point
for the 74HCT devices, with the output
changing from the defined LOW level to the
defined HIGH level.
3-state output disable time; the time between
the specified reference points, normally the
50% points for the 74HC and 74HCU devices
and the 1.3 V points for the 74HCT devices on
the output enable input voltage waveform and a
point representing 10% of the output swing on
the output voltage waveform of a 3-state
device, with the output changing from
a HIGH level (VOH) to a high impedance
OFF-state (Z).
March 1988
18
tPLZ
3-state output disable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and the 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and a point
representing 10% of the output swing on the
output voltage waveform of a 3-state
device, with the output changing from a LOW
level (VOL) to a high impedance OFF-state (Z).
tPZH
3-state output enable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and the 50%
point on the output voltage waveform of a
3-state device, with the output changing from a
high impedance OFF-state (Z) to a HIGH level
(VOH).
tPZL
3-state output enable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and the 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and the 50%
point on the output voltage waveform of a
3-state device, with the output changing from a
high impedance OFF-state (Z) to a LOW level
(VOL).
trem
Removal time; the time between the end of an
overriding asynchronous input, typically a clear
or reset input, and the earliest permissible
beginning of a synchronous control input,
typically a clock input, normally measured at
the 50% points for 74HC devices and the 1.3 V
points for the 74HCT devices on both input
voltage waveforms.
tsu
Set-up time; the interval immediately preceding
the active transition of the timing pulse (usually
the clock pulse) or preceding the transition of
the control input to its latching level, during
which interval the data to be recognized must
be maintained at the input to ensure their
recognition. A negative set-up time indicates
that the correct logic level may be initiated
sometime after the active transition of the
timing pulse and still be recognized.
Philips Semiconductors
HCMOS family characteristics
tTHL
Output transition time; the time between two
specified reference points on a waveform,
normally 90% and 10% points, that is changing
from HIGH-to-LOW.
tTHL
Output transition time; the time between two
specified reference points on a waveform,
normally 10% and 90% points, that is changing
from LOW-to-HIGH.
tW
Pulse width; the time between the 50%
amplitude points on the leading and trailing
edges of a pulse for 74HC and 74HCU devices
and at the 1.3 V points for 74HCT devices.
March 1988
FAMILY SPECIFICATIONS
19
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