SmartReflex Power and Performance Management Technologies:

SmartReflex Power and Performance Management Technologies:
W H I T E
PA P E R
By Brian Carlson
and Bill Giolma
Strategic marketing
Wireless business unit
Semiconductor group
Introduction
SmartReflex™ Power and Performance
Management Technologies: reduced
power consumption, optimized performance
New SmartReflex 2 power and performance technologies:
Wireless mobile devices are approaching
• Dynamically adjusts transistor performance versus leakage
an impasse. With the convergence of new
• Dynamically lowers voltages for idle memory banks
computing, communication and entertainment
• Automates the application of SmartReflex™ technologies in the design process
applications on wireless handsets, power
Holistic power management approach
demands are increasing rapidly, yet battery
Managing power budgets for wireless mobile devices, both today and moving forward, will
capacity cannot keep up. At the same time,
be an unprecedented challenge that can only be resolved by an aggressive, holistic power
consumers
devices
want
they
can
sleek,
slip
compact
mobile
into
pocket.
a
Integration at the chip level – often combining multiple processing cores in the same
management approach. This approach starts with process technologies and moves upward
to hardware, system-on-a-chip (SOC) architectures and software.
Wireless carriers clamor for increased capabilities in handsets so that they can develop
new applications that will increase their average revenue per user (ARPU). Subscribers
welcome the increased functionality. As a result, video, mobile digital TV, high-fidelity audio,
device – and smaller, submicron fabrication
3-D video games, digital photography, strong security applications and other functions could
processes help to reduce the size of wireless
soon jeopardize the long-held industry minimum of four hours of talk time and 120+ hours
handsets while enabling added functionality.
of standby on a single battery charge. Battery capacity simply cannot keep pace with the
Unfortunately, smaller submicron processes
exciting new functionality on mobile handsets. While consumers demand new applications,
exacerbate the problem of standby leakage
they also want smaller, sleeker mobile devices, accelerating the trend toward higher levels
of silicon integration and smaller submicron process geometries.
power.
Wireless handset and other mobile device
manufacturers
are
challenged
to
reduce
power consumption while enhancing system
performance; in other words, do more for less.
SmartReflex™ power and performance management technologies from Texas Instruments (TI)
– now significantly improved with second-generation SmartReflex 2 techniques – have productproven, intelligent and adaptive capabilities that
aggressively meet these challenges and provide
a pathway to future solutions.
Key benefits
• TI’s SmartReflex™ technologies
combine intelligent and adaptive silicon,
circuit design and software to solve power and performance management challenges at smaller process nodes. OEMs can offer sleeker, multimediaenabled mobile devices with long
battery life and less heat dissipation.
• SmartReflex technologies enable high performance at low power.
• SmartReflex technologies embed
intelligence to adaptively adjust voltage, frequency and power based on device
activity, modes of operation and
temperature for maximum power
reduction.
• With SmartReflex technologies, you
can add new multimedia applications
to mobile wireless devices without
sacrificing standby time, talk time or
battery life.
• SmartReflex technologies cross
traditional boundary lines in systems, managing multiple processing cores
such as DSPs and other functional blocks.
• SmartReflex technologies solve the
chip-level leakage power challenge
that is exacerbated at smaller,
deep-submicron process geometries.
• TI has shipped more than 1 billion
devices with SmartReflex technologies.
2
Texas Instruments
Traditional power management techniques such as low-power modes, clock gating and dynamic voltage
and frequency scaling (DVFS) have commonly been implemented in wireless handsets, personal digital assistants (PDAs), laptop computers and other power-sensitive devices.
Designers will continue to apply these techniques, of course, but the industry’s current trends necessitate
comprehensive and aggressive solutions that address both power and performance.
For high-performance, power-sensitive applications, power reduction is only half the challenge. Providing
higher performance while consuming less energy per function is imperative. The sophisticated applications
coming to mobile handsets operate at much higher frequencies than voice communications. For example,
simple audio on a wireless mobile device typically operates at less than 20 MHz, whereas a video application
may require a frequency of 200 MHz or more.
Just managing the hundreds of thousands of pixels in a high-resolution video display generates a
tremendous number of power-consuming processing cycles. Only creative new power reduction techniques
that cross functional blocks and include multiple processing cores will allow systems to adapt dynamically
and achieve high performance with less power.
In addition to dynamic power (the power that is consumed when transistors switch), wireless mobile devices
are encountering new standby leakage power challenges caused by shrinking component geometries. Smaller,
more highly integrated components are needed to fit more functionality into the compact new form factors
consumers demand. Unfortunately, moving down the process scale from 90 to 65 to 45 nanometer (nm) has an
exponential effect on leakage power; leakage thus becomes an increasingly significant percentage of a device’s
total power.
Moreover, while process technologies shrink, the extra on-chip memory added to support new applications
becomes a prime source of standby leakage power. Power dissipation translates to heat, and in mobile wireless
devices heat is more than just a discomfort to users: it can have considerable negative effects on performance,
eroding the reliability and durability of the system itself.
SmartReflex power
and performance
management technologies
Traditional power strategies have focused on dynamic power reduction, but the holistic approach of TI’s
rich, product-proven SmartReflex technologies takes a more comprehensive system-wide perspective on the
nterrelated issues of power and performance, addressing both dynamic and standby leakage power. The
SmartReflex portfolio of power and performance management technologies addresses today’s mobile device
challenges with a pathway to future solutions.
SmartReflex technologies comprise silicon intellectual property (IP); techniques that you can apply at the
system-on-a-chip (SOC) design level; and system software that manages many of the hardware-enabled
SmartReflex technologies and interfaces seamlessly to other power management techniques based in
operating systems (OS) or third-party software subsystems. SmartReflex 2 adds the automatic application of
key power management techniques in the design flow to these capabilities. TI is leveraging SmartReflex technologies for industry-leading power and performance management in custom and standard product devices.
SmartReflex™ power and performance management technologies: reduced power consumption, optimized performance
February 2008
Texas Instruments 3
TI SmartReflex™ 2 Technologies
Aggressive power management involving all system
components - silicon technology, SoC design and software
Reductions in both active and static power
Power domain
partitioning
Voltage and
frequency scaling
SmartReflex circuits
and methodologies
Dual-gate
length libraries
Retention flops
in the logic
Low leakage
SRAM design
SRAM dedicated
power switches
Embedded
power switches
*New SmartReflex 2 Technologies
Silicon IP
At the silicon level, TI has a track record as an industry pioneer in sophisticated power and performance
capabilities, many of which have transitioned into SmartReflex technologies. One major emerging challenge
that SmartReflex technologies address is standby leakage power, which becomes a significantly greater
part of a device’s total power at smaller process nodes. You can apply several SmartReflex technologies to
drastically limit leakage from a device. For example, SmartReflex technologies combine to reduce standby
leakage power in the OMAP3430 processor by as much as three orders of magnitude. Today, many of TI’s
90-nm and all of its 65-nm wireless components implement SmartReflex technologies to reduce leakage
power. In the future, all new devices at the 90-, 65-, 45-nm and smaller process nodes will incorporate these
breakthrough technologies.
SmartReflex™ power and performance management technologies: reduced power consumption, optimized performance
February 2008
4
Texas Instruments
New with SmartReflex 2 technology – SmartReflex 2 enhances these silicon techniques with forward
body biasing (FBB) and reverse body biasing (RBB), unique techniques that modulate the body voltage of
transistor cells or blocks dynamically to gain performance and reduce leakage. For several CMOS process
nodes, TI has employed transistors with short and long gate lengths in order to increase switching speed or
reduce leakage. FBB and RBB carry this technique a step further by enabling small modifications in transistor
threshold voltages after the device has been manufactured and is in operation. Tests indicate that FBB can
increase performance by as much as 15 percent and RBB can reduce leakage by as much as 40 percent
depending on device operating temperatures.
Another SmartReflex technology at the silicon level is a library of power management cells that enable
power switching, isolation and voltage shifting, thus facilitating a granular approach to partitioning a device’s
power domains. By structuring the device with multiple power domains, functional blocks can be powered
down or put into a standby power mode when they are not active, thus reducing power consumption while
ensuring optimal performance. To simplify chip-level integration, SmartReflex technologies feature an
easy-to-use, nonintrusive design flow.
New with SmartReflex 2 technology – As power management techniques become increasingly
complex, it becomes important to simplify their implementation in the design process. SmartReflex 2
Silicon IP
Technology
Description
Retention SRAM
and logic
SRAM and logic retention cells support dynamic power switching
without state loss, lowering voltage and reducing leakage
Dual gate lengths
Longer gate length for lower leakage and shorter gate length for
higher performance
Power management
cell library
Switching, isolation and level shifters support multiple domains in
SOC implementations
Process and
temperature sensor
Adapts voltage dynamically in response to silicon processes and
temperature variations
Design flow support
Complete, nonintrusive support for easily integrating SmartReflex
technologies
Adaptive body
biasing
Modulates transistor bias voltages dynamically in order to optimize
switching speed versus leakage FBB and RBB together are called
adaptive body biasing (ABB) (SmartReflex 2)
SmartReflex PriMer
Automates the implementation of SmartReflex power management
techniques in the design and provides a UPF-compliant
specification (SmartReflex 2)
SRAM retention
til access (RTA)
Reduces leakage while retaining contents in SRAM arrays by
lowering the voltage on idle memory blocks (SmartReflex 2)
SmartReflex™ power and performance management technologies: reduced power consumption, optimized performance
February 2008
Texas Instruments 5
technology addresses this issue with SmartReflex PriMer, a user-friendly tool that simplifies design, reduces
development time, and improves verification without compromising the flexibility needed to meet different
product requirements. SmartReflex PriMer automatically generates a Universal Power Format (UPF)-compliant
specification, complete with power management features that include RTL descriptions of power domain
insertion and protocol control, FBB/RBB and SRAM power management controllers, and a full suite of power
management verification and assertion checks. By providing these details automatically, SmartReflex PriMer
conserves power and improves design reliability while speeding time to market.
New with SmartReflex 2 technology – SmartReflex 2 technology adds SRAM retention ‘til access
(RTA), a technique of reducing power leakage in memory arrays by automatically lowering the voltage
in memory banks when they are not being accessed. When the entire chip is idle, the entire array is put
into a low-leakage state. Memory access logic also runs on a lower voltage to conserve power.
SOC design
In addition to established hardware techniques such as DVFS and clock gating that address dynamic power,
SmartReflex technologies also include new innovative techniques at the architectural level of SOC design to
address standby leakage power. For example, adaptive voltage scaling (AVS), dynamic power switching (DPS)
and standby leakage management (SLM) are creative new technologies in the SmartReflex portfolio.
SOC architectural and design technologies
Technology
Description
Adaptive voltage
scaling (AVS)
Maintains high performance while minimizing voltage based on
silicon process and temperature
Dynamic power
switching (DPS)
Dynamically switches between power modes based on system
activity to reduce leakage power
Dynamic voltage and
frequency scaling (DVFS)
Dynamically adjusts voltage and frequency to adapt to the
performance required
Multiple domains
(voltage/power/clock)
Enables distinct physical domains for granular power/performance
management by software
Standby leakage
management (SLM)
Maintains lowest standby power mode compatible with required
system responsiveness to reduce leakage power
System software
At the system software level, SmartReflex technologies include intelligent software that manages many of the
lower level hardware-enabled technologies. For example, SmartReflex technologies include host processor
power management, which features several capabilities deployed at the system level, such as a workload
monitor, workload predictor, resource manager and device driver power management software. Additionally,
the SmartReflex framework features the TI DSP/BIOS™ software kernel foundation.
SmartReflex™ power and performance management technologies: reduced power consumption, optimized performance
February 2008
6
Texas Instruments
SmartReflex technologies cross many traditional boundary lines, such as the distinction between
processing cores. First- and second-generation power management solutions were by and large
vendor-specific and limited in scope. They could only be applied to certain functional blocks or specific
cores. As a result, these solutions only addressed a small portion of the device’s power budget. In contrast,
SmartReflex technologies support multiple cores, hardware accelerators, functional blocks, peripherals
and other system components. In addition, SmartReflex system-level technologies are open to OS-based
and third-party power management software so that you can develop a collaborative and cooperative
environment with regards to power and performance.
System software
Technology
Description
OS support
Provides an open environment for blending with operating systems
and
supports Symbian and Linux
Software power
management framework
Intelligent control for power and performance management that is
transparent to application programs and legacy code - Monitors
system
activity, not just processor activity
Workload monitoring
and
prediction
Determines system performance needs used to make intelligent
power
and performance management decisions
Policy and domain
managers
Dynamically controls the system, providing the performance needed
at
the lowest power
DSP/BIOS software
kernel foundation
Power and performance management software for DSPs
SmartReflex
technologies:
a holistic solution
TI’s SmartReflex technologies embody a holistic, comprehensive approach to enable devices with the highest
performance with the lowest power in the industry. This is possible because TI is one of the few semiconductor suppliers maintaining a broad-based and focused approach to its business, including advanced process
technologies, its own silicon foundries, many years of system-level expertise and advanced IP.
The system expertise TI developed while working closely with wireless OEMs and manufacturers in
other industries is an invaluable resource for SmartReflex technologies. With this extensive system-level
knowledge, SmartReflex technologies work in unison, complementing each other and coordinating activities
throughout the system. Only with this intimate knowledge and a thorough understanding of wireless mobile
devices could SmartReflex technologies have the tremendous impact that they have already had on all facets
of a system.
As a consequence of its extensive support over the years for handset manufacturers, TI has focused its
research and development efforts to have an immediate effect on wireless mobile devices. TI’s development
of extensive product-specific IP is applied in SmartReflex technologies.
SmartReflex™ power and performance management technologies: reduced power consumption, optimized performance
February 2008
Texas Instruments 7
TI’s leadership in chip fabrication technologies means that the company can develop SmartReflex
technologies within the context of the process technologies used to produce the chips. As a result,
SmartReflex technologies can address the issue of leakage power head-on. And because TI operates
its own foundries, it is able to monitor, control and ensure the production quality of each device.
The OMAP3430
processor with
SmartReflex™
technologies
The multi-core OMAP3430 mobile multimedia applications processor provides an excellent example of
SmartReflex technologies used to reduce power consumption at the SOC level. With more than 150 million
on-chip transistors, the 65-nm OMAP3430 processor features aggressive power management techniques
that enable multi-standard video encode and decode in handheld applications.
The SmartReflex technologies employed by the device include multiple voltage domains with multiple
discrete operating/performance points (OPPs) for cores and peripherals; 11 major power domains for
fine-grained leakage control throughout the device; split-rail memories separating memory logic from arrays
(allowing voltage rescaling for active power reduction or faster response); SRAM RTA; AVS to compensate
for circuit temperature changes as well as changing levels of activity; and core logic designed with full
power-down in standby mode.
TI designers also used SmartReflex PriMer in creating the OMAP3430 processor, ensuring power
design reliability and helping TI bring the complex device to customers more quickly. The OMAP3430
processor’s successful power management implementation results in an active power reduction of 66
percent and a reduction in leakage power of two to three orders of magnitude.
NaviLink™
GPS
Fast
IrDA
Hollywood™
Mobile DTV
WiLink™
mWLAN
Trace
Analyzer
Emulator
Pod
Trace
JTAG/
Emulation
I/F
UART/IrDA
NAND
Flash
Mobile
DDR
SDRC
GPMC
OMAP3430
I2C
SPI
NOR
FLASH
ARM®
Cortex™-A8
IVA™ 2+
Accelerator
PowerVR SGX
Image Signal
Processor (ISP)
SDIO
Shared Memory Controller/DMA
Coexistence
BlueLink™ Data
Bluetooth®
Voice
Flashing
TCS
Modem Control/Data
Chipset
Voice
UART
McBSP
McBSP
Camera
Module
Camera-Serial
Sub Camera
MS/MMC/SD/SDIO
MS/MMC/SD/SDIO
Card
Video DAC
S-Video
TV
PAL/NTSC
Display
Controller
Parallel-Serial
QVGA
XGA
Color TFT Color TFT
Display
Display
TWL5030
I2C
Battery
Charger
System Interface
Power Reset
Clock Manager
McBSP
McBSP
Boot/Secure ROM
M-Shield™ Security Technology: SHA-1/MD5,
DES/3DES, RNG, AES, PKA, Secure WDT, Keys
GPIO
Camera I/F
Serial-Parallel
Timers, Interrupt Controller, Mailbox
McBSP
USB
GPIO
High-Speed (HS)
USB 2 OTG Controller
SPI
TSC2046 Touch
Screen Controller
Power Manager
Voice
Audio
Audio/Voice
Codec
On/Off
Reset
32 kHz Crystal
Audio
In/Out
HS USB
Transceiver
Key Pad
USB
Connector
LED
Keypad
Battery
SmartReflex™ power and performance management technologies: reduced power consumption, optimized performance
February 2008
The future of power
and performance
management
The effects of SmartReflex technology on power consumption and system performance are constantly
demonstrated in the vast number of mobile wireless devices that feature these innovative solutions. Indeed,
TI has already shipped more than 1 billion components with embedded SmartReflex technologies.
The solid foundation for SmartReflex technologies now extends outward with the second-generation
features of SmartReflex 2: dynamic adjustment of transistor performance versus leakage, lower voltages
for unused memory banks and the automatic application of power management techniques in the design
process. TI’s roadmap for such capabilities stretches far into the future, penetrating deeper into wireless
mobile devices while at the same time leveraging the application of SmartReflex technologies into other
high-performance, power-sensitive industry segments.
The forces of the marketplace do not rest. Wireless mobile devices and other battery-operated systems
must aggressively add new functionality and applications to attract users. New styles and popular industrial
design will change the form factors that mobile devices come in, driving chips toward higher integration and
smaller process geometries where new SmartReflex solutions await. As SmartReflex technologies continue
to evolve, they will remain on the critical path for mobile applications well into the future.
For more information
www.ti.com.smartreflex
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Clocks and Timers
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interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
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