LTC2345-16 Octal, 16-Bit, 200ksps Differential SoftSpan ADC with Wide Input Common Mode Range

LTC2345-16 Octal, 16-Bit, 200ksps Differential SoftSpan ADC with Wide Input Common Mode Range

applicaTions

n n n n

Programmable Logic Controllers

Industrial Process Control

Medical Imaging

High Speed Data Acquisition

LTC2345-16

Octal, 16-Bit, 200ksps

Differential SoftSpan ADC with

Wide Input Common Mode Range

DescripTion FeaTures

n n n n n n n n n n n n n n n n

200ksps per Channel Throughput

Eight Simultaneous Sampling Channels

±1.25LSB INL (Maximum)

Guaranteed 16-Bit, No Missing Codes

Differential, Wide Common Mode Range Inputs

Per-Channel SoftSpan Input Ranges:

±4.096V, 0V to 4.096V, ±2.048V, 0V to 2.048V

±5V, 0V to 5V, ±2.5V, 0V to 2.5V

91dB Single-Conversion SNR (Typical)

−113dB THD (Typical) at f

IN

= 2kHz

102dB CMRR (Typical) at f

IN

= 200Hz

Rail-to-Rail Input Overdrive Tolerance

Guaranteed Operation to 125°C

Integrated Reference and Buffer (4.096V)

SPI CMOS (1.8V to 5V) and LVDS Serial I/O

Internal Conversion Clock, No Cycle Latency

81mW Power Dissipation (Typical)

48-Lead (7mm x 7mm) QFN Package

The LTC

®

2345-16 is a 16-bit, low noise 8-channel simultaneous sampling successive approximation register

(SAR) ADC with differential, wide common mode range inputs. Operating from a 5V low voltage supply and using the internal reference and buffer, each channel of this

SoftSpan

TM

ADC can be independently configured on a conversion-by-conversion basis to accept ±4.096, 0V to 4.096V, ±2.048V, or 0V to 2.048V signals. Individual channels may also be disabled to increase throughput on the remaining channels.

The wide input common mode range and 102dB CMRR of the LTC2345-16 analog inputs allow the ADC to directly digitize a variety of signals, simplifying signal chain design.

This input signal flexibility, combined with ±1.25LSB INL, no missing codes at 16 bits, and 91dB SNR, makes the

LTC2345-16 an ideal choice for many applications requiring wide dynamic range.

The LTC2345-16 supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces. Between one and eight lanes of data output may be employed in CMOS mode, allowing the user to optimize bus width and throughput.

L

, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673.

Other Patents pending.

Typical applicaTion

5V

ARBITRARY

0V

5V

BIPOLAR

5V

FULLY

DIFFERENTIAL

0V

5V

UNIPOLAR

0V 0V

DIFFERENTIAL INPUTS IN+ / IN– WITH

WIDE INPUT COMMON MODE RANGE

IN0

+

IN0

S/H

S/H

S/H

S/H

S/H

S/H

IN7

+

IN7

S/H

S/H

MUX

0.1µF

5V

2.2µF

1.8V TO 5V

0.1µF

V

DD

V

DDLBYP

CMOS OR LVDS

I/O INTERFACE

OV

DD

LVDS/ CMOS

PD

LTC2345-16

SDO0

16-BIT

SAR ADC

SDO7

SCKO

SCKI

SDI

CS

BUSY

CNV

REFBUF

47µF

REFIN

0.1µF

GND

234516 TA01a

SAMPLE

CLOCK

EIGHT SIMULTANEOUS

SAMPLING CHANNELS

For more information www.linear.com/LTC2345-16

Integral Nonlinearity vs

Output Code and Channel

1.00

0.75

0.50

0.25

0

–0.25

–0.50

–0.75

–1.00

–32768

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN

+

)

ALL CHANNELS

–16384 0

OUTPUT CODE

16384 32768

234516 TA01b

234516f

1

LTC2345-16

absoluTe MaxiMuM raTings

(Notes 1, 2)

Supply Voltage (V

DD

Supply Voltage (OV

DD

) ..................................................6V

) ................................................6V

Internal Regulated Supply Bypass (V

DDLBYP

Analog Input Voltage

IN0

+

to IN7

+

,

) ... (Note 3)

IN0

to IN7

(Note 4) ................(–0.3V) to (V

DD

+ 0.3V)

REFIN .................................................... –0.3V to 2.8V

REFBUF, CNV (Note 4) ............. –0.3V to (V

Digital Input Voltage (Note 4) ..... –0.3V to (OV

Digital Output Voltage (Note 4) .. –0.3V to (OV

DD

DD

DD

+ 0.3V)

+ 0.3V)

+ 0.3V)

Power Dissipation .............................................. 500mW

Operating Temperature Range

LTC2345C ................................................ 0°C to 70°C

LTC2345I .............................................–40°C to 85°C

LTC2345H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

pin conFiguraTion

TOP VIEW

IN6–

IN6+

IN5–

IN5+

IN4–

IN4+

IN3–

IN3+

IN2–

IN2+

IN1–

IN1+

9

10

11

12

7

8

3

4

5

6

1

2

49

GND

UK PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

T

JMAX

= 150°C, θ

JA

= 34°C/W

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

31

30

29

28

27

26

25

36

35

34

33

32

SDO7

SDO–/SDO6

SDO+/SDO5

SCKO–/SDO4

SCKO+/SCKO

OV

DD

GND

SCKI–/SCKI

SCKI+/SDO3

SDI–/SDO2

SDI+/SDO1

SDO0

orDer inForMaTion

( http://www.linear.com/product/LTC2345-16#orderinfo )

LEAD FREE FINISH

LTC2345CUK-16#PBF

LTC2345IUK-16#PBF

TAPE AND REEL

LTC2345CUK-16#TRPBF LTC2345UK-16

LTC2345IUK-16#TRPBF

PART MARKING*

LTC2345UK-16

PACKAGE DESCRIPTION

48-Lead (7mm × 7mm) Plastic QFN

48-Lead (7mm × 7mm) Plastic QFN

TEMPERATURE RANGE

0°C to 70°C

–40°C to 85°C

LTC2345HUK-16#PBF LTC2345HUK-16#TRPBF LTC2345UK-16 48-Lead (7mm × 7mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

2

For more information www.linear.com/LTC2345-16

234516f

LTC2345-16

elecTrical characTerisTics temperature range, otherwise specifications are at T

A

The

l

denotes the specifications which apply over the full operating

= 25°C. (Note 5)

I

SYMBOL

V

V

IN

+

IN

PARAMETER

Absolute Input Range

(IN0

+

to IN7

+

)

Absolute Input Range

(IN0

to IN7

)

V

IN

+ – V

IN

– Input Differential Voltage

Range

V

V

IHCNV

ILCNV

INCNV

Input Common Mode

Rejection Ratio

CNV High Level Input Voltage

CNV Low Level Input Voltage

CNV Input Current

CONDITIONS

(Note 6)

(Note 6)

V

CM

Input Common Mode Voltage

Range

I

V

IN

+ – V

IN

– Input Differential Overdrive

Tolerance

IN

C

IN

Analog Input Leakage Current

Analog Input Capacitance

CMRR

SoftSpan 7: ±V

SoftSpan 6: ±V

REFBUF

REFBUF

SoftSpan 5: 0V to V

Range (Note 6)

/1.024 Range (Note 6)

REFBUF

SoftSpan 4: 0V to V

REFBUF

SoftSpan 3: ±0.5 • V

REFBUF

SoftSpan 2: ±0.5 • V

REFBUF

Range (Note 6)

/1.024 Range (Note 6)

Range (Note 6)

/1.024 Range (Note 6)

SoftSpan 1: 0V to 0.5 • V

REFBUF

Range (Note 6)

(Note 6)

(Note 7)

Sample Mode

Hold Mode

V

IN

+ = V

IN

− = 3.6V

P-P

200Hz Sine

V

IN

= 0V to V

DD l l l l l l l l l l

– V

–0.5 • V

–0.5 •

– V

REFBUF

REFBUF

V

0

0

REFBUF

0

/1.024

REFBUF

/1.024

0 l l l l l l

MIN

0

0

−V

DD

–1

84

1.3

–10

TYP

50

10

102

MAX

V

DD

V

DD

V

REFBUF

V

REFBUF

/1.024

V

REFBUF

/1.024 V

REFBUF

0.5 • V

REFBUF

0.5 • V

REFBUF

/1.024

0.5 • V

REFBUF

V

DD

V

DD

1

0.5

10

UNITS

V

V

V

µA pF pF dB

V

V

V

V

V

V

V

V

V

V

μA

converTer characTerisTics temperature range, otherwise specifications are at T

A

The

l

denotes the specifications which apply over the full operating

= 25°C. (Note 8)

TYP MAX SYMBOL PARAMETER

Resolution

INL

DNL

ZSE

FSE

CONDITIONS

No Missing Codes

Transition Noise SoftSpans 7 and 6: ±4.096V and ±4V Ranges

SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges

SoftSpans 3 and 2: ±2.048V and ±2V Ranges

SoftSpan 1: 0V to 2.048V Range

(Note 9) Integral Linearity Error

Differential Linearity Error (Note 10)

Zero-Scale Error (Note 11)

Zero-Scale Error Drift

Full-Scale Error

Full-Scale Error Drift

(Note 11) l l l l l l

MIN

16

16

–1.25

−0.9

−750

−0.13

0.63

1.2

1.2

2.3

±0.50

±0.20

±65

±2

±0.025

±2.5

1.25

0.9

750

0.13

UNITS

Bits

Bits

LSB

RMS

LSB

RMS

LSB

RMS

LSB

RMS

LSB

LSB

μV

μV/°C

%FS ppm/°C

For more information www.linear.com/LTC2345-16

234516f

3

LTC2345-16

DynaMic accuracy otherwise specifications are at T

A

The

l

denotes the specifications which apply over the full operating temperature range,

= 25°C. A

IN

= –1dBFS. (Notes 8, 12)

SYMBOL PARAMETER

SINAD Signal-to-(Noise +

Distortion) Ratio

SNR

THD

SFDR

Signal-to-Noise Ratio

Total Harmonic Distortion

Spurious Free Dynamic

Range

Channel-to-Channel

Crosstalk

–3dB Input Bandwidth

Aperture Delay

Aperture Delay Matching

Aperture Jitter

Transient Response

CONDITIONS

SoftSpans 7 and 6: ±4.096V and ±4V Ranges, f

IN

SoftSpans 3 and 2: ±2.048V and ±2V Ranges, f

IN

SoftSpan 1: 0V to 2.048V Range, f

IN

= 2kHz

= 2kHz

SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, f

IN

= 2kHz

= 2kHz

SoftSpans 7 and 6: ±4.096V and ±4V Ranges, f

IN

SoftSpans 3 and 2: ±2.048V and ±2V Ranges, f

IN

SoftSpan 1: 0V to 2.048V Range, f

IN

= 2kHz

= 2kHz

SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, f

IN

= 2kHz

= 2kHz

SoftSpans 7 and 6: ±4.096V and ±4V Ranges, f

IN

SoftSpans 3 and 2: ±2.048V and ±2V Ranges, f

IN

SoftSpan 1: 0V to 2.048V Range, f

IN

= 2kHz

= 2kHz

SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, f

IN

= 2kHz

= 2kHz

SoftSpans 7 and 6: ±4.096V and ±4V Ranges, f

SoftSpans 3 and 2: ±2.048 and ±2V Ranges, f

IN

SoftSpan 1: 0V to 2.048V Range, f

IN

= 2kHz

IN

= 2kHz

SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, f

IN

= 2kHz

= 2kHz

One Channel Converting 3.6V

P-P

Crosstalk to All Other Channels

200Hz Sine in ±2.048V Range,

Full-Scale Step, 0.005% Settling l l l l l l l l l l l l l l l l

MIN

87.2

81.3

81.4

75.7

87.3

81.5

81.6

75.8

99

95

96

96

31

1

150

3

200

TYP

91.0

85.6

85.8

80.0

91.0

85.6

85.8

80.0

–113

–111

–110

–108

114

113

112

109

−107

MAX

–99

–95

–96

–95

UNITS

dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB

MHz ns ps ps

RMS ns

inTernal reFerence characTerisTics operating temperature range, otherwise specifications are at T

A

The

l

denotes the specifications which apply over the full

= 25°C. (Note 8)

SYMBOL

V

REFIN

V

REFIN

PARAMETER

Internal Reference Output Voltage

Internal Reference Temperature Coefficient

Internal Reference Line Regulation

Internal Reference Output Impedance

REFIN Voltage Range

CONDITIONS

(Note 13)

V

DD

= 4.75V to 5.25V

REFIN Overdriven (Note 6) l

MIN

2.043

1.25

TYP

2.048

5

0.1

20

MAX

2.053

20

2.2

UNITS

V ppm/°C mV/V kΩ

V

4

For more information www.linear.com/LTC2345-16

234516f

LTC2345-16

reFerence buFFer characTerisTics operating temperature range, otherwise specifications are at T

A

The

l

denotes the specifications which apply over the full

= 25°C. (Note 8)

SYMBOL

V

REFBUF

I

REFBUF

PARAMETER CONDITIONS

Reference Buffer Output Voltage REFIN Overdriven, V

REFIN

= 2.048V

REFBUF Voltage Range REFBUF Overdriven (Notes 6, 14)

REFBUF Input Impedance

REFBUF Load Current

V

REFIN

= 0V, Buffer Disabled

V

REFBUF

V

REFBUF

= 5V, 8 Channels Enabled (Notes 14, 15)

= 5V, Acquisition Mode (Note 14) l l l

MIN

4.091

2.5

TYP

4.096

13

1.5

0.39

MAX

4.101

5

1.9

UNITS

V

V kΩ mA mA

DigiTal inpuTs anD DigiTal ouTpuTs full operating temperature range, otherwise specifications are at T

A

The

l

denotes the specifications which apply over the

= 25°C. (Note 8)

CONDITIONS MIN TYP MAX UNITS SYMBOL PARAMETER

CMOS Digital Inputs and Outputs

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

I

SOURCE

I

SINK

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

V

ICM

I

ICM

V

OD

V

OCM

I

OZ

LVDS Digital Inputs and Outputs

V

ID

R

ID

Differential Input Voltage

On-Chip Input Termination

Resistance

Common-Mode Input Voltage

Common-Mode Input Current

Differential Output Voltage

Common-Mode Output Voltage

Hi-Z Output Leakage Current

V

IN

= 0V to OV

DD

I

OUT

= –500μA

I

OUT

= 500μA

V

OUT

= 0V to OV

DD

V

OUT

= 0V

V

OUT

= OV

DD

CS = 0V, V

ICM

= 1.2V

CS = OV

DD

V

IN

+ = V

IN

– = 0V to OV

DD

R

L

= 100Ω Differential Termination

R

L

= 100Ω Differential Termination

V

OUT

= 0V to OV

DD l l l l l l l l l l l l l

0.8 •  OV

DD

–10

OV

DD

 – 0.2

–10

200

80

0.3

–10

275

1.1

–10

5

–50

50

350

106

10

1.2

350

1.2

0.2 •  OV

DD

10

0.2

10

600

130

2.2

10

425

1.3

10 mV

Ω

V

μA mV

V

μA pF

V

V

V

V

μA

μA mA mA

For more information www.linear.com/LTC2345-16

234516f

5

LTC2345-16

power requireMenTs range, otherwise specifications are at T

A

The

l

denotes the specifications which apply over the full operating temperature

= 25°C. (Note 8)

CONDITIONS MIN TYP MAX UNITS SYMBOL PARAMETER

CMOS I/O Mode

V

DD

OV

DD

I

VDD

Supply Voltage

Supply Voltage

Supply Current l l

4.75

1.71

5.00

I

OVDD

P

D

Supply Current

Power Dissipation

200ksps Sample Rate, 8 Channels Enabled

200ksps Sample Rate, 8 Channels Enabled, V

REFBUF

= 5V (Note 14)

Acquisition Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

200ksps Sample Rate, 8 Channels Enabled (C

L

= 25pF)

Acquisition Mode

Power Down Mode

200ksps Sample Rate, 8 Channels Enabled

Acquisition Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade) l l l l l l l l l l l l

15.3

13.7

1.3

65

65

1.8

1

1

81

6.5

0.33

0.33

5.25

5.25

2.6

20

20

95

11

1.2

2.6

17.6

15.8

2.1

225

500 mA

μA

μA mW mW mW mW mA mA mA

μA

µA

V

V

LVDS I/O Mode

V

DD

OV

DD

I

VDD

Supply Voltage

Supply Voltage

Supply Current l l

4.75

2.375

5.00

I

OVDD

P

D

Supply Current

Power Dissipation

200ksps Sample Rate, 8 Channels Enabled

200ksps Sample Rate, 8 Channels Enabled, V

REFBUF

= 5V (Note 14)

Acquisition Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

200ksps Sample Rate, 8 Channels Enabled (R

L

= 100Ω)

Acquisition or (R

L

Power Down Mode

= 100Ω)

200ksps Sample Rate, 8 Channels Enabled

Acquisition Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade) l l l l l l l l l l l l

17.9

16.2

2.8

65

65

7

7

1

107

32

0.33

0.33

5.25

5.25

20.6

18.6

3.8

225

500

8.5

8.0

20

125

39

1.2

2.6

mA mA mA

μA

µA

V

V mA mA

μA mW mW mW mW

aDc TiMing characTerisTics temperature range, otherwise specifications are at T

A

The

l

denotes the specifications which apply over the full operating

= 25°C. (Note 8)

SYMBOL

f

SMPL t

CYC

PARAMETER

Maximum Sampling Frequency

Time Between Conversions

CONDITIONS

8 Channels Enabled

7 Channels Enabled

6 Channels Enabled

5 Channels Enabled

4 Channels Enabled

3 Channels Enabled

2 Channels Enabled

1 Channel Enabled

8 Channels Enabled, f

7 Channels Enabled, f

6 Channels Enabled, f

SMPL

SMPL

SMPL

= 200ksps

= 225ksps

5 Channels Enabled, f

SMPL

= 266ksps

= 300ksps

4 Channels Enabled, f

SMPL

3 Channels Enabled, f

SMPL

2 Channels Enabled, f

SMPL

= 375ksps

= 450ksps

1 Channel Enabled, f

SMPL

= 625ksps

= 1000ksps l l l l l l l l l l l l l l l l

MIN

5000

4444

3750

3333

2666

2222

1600

1000

TYP MAX

200

225

266

300

375

450

625

1000

UNITS

ns ns ns ns ns ns ns ns ksps ksps ksps ksps ksps ksps ksps ksps

234516f

6

For more information www.linear.com/LTC2345-16

LTC2345-16

aDc TiMing characTerisTics temperature range, otherwise specifications are at T

SYMBOL PARAMETER

A

The

l

denotes the specifications which apply over the full operating

= 25°C. (Note 8)

CONDITIONS MIN TYP MAX UNITS

t

CONV t

ACQ

Conversion Time

Acquisition Time

(t

ACQ

= t

CYC

– t

CONV

– t

BUSYLH

)

N Channels Enabled, 1 ≤ N ≤ 8

8 Channels Enabled, f

7 Channels Enabled, f

6 Channels Enabled, f

SMPL

SMPL

SMPL

= 200ksps

= 225ksps

5 Channels Enabled, f

SMPL

= 266ksps

= 300ksps

4 Channels Enabled, f

SMPL

3 Channels Enabled, f

SMPL

2 Channels Enabled, f

SMPL

= 375ksps

= 450ksps

1 Channel Enabled, f

SMPL

= 625ksps

= 1000ksps l l l l l l l l l l l

455 • N – 35

565

564

425

563

451

562

495

450

40

420

505 • N – 35

975

924

735

823

661

722

605

510

555 • N – 35 t

CNVH t

CNVL t

BUSYLH t

QUIET t

PDH t

PDL

CNV High Time

CNV Low Time

CNV

to BUSY Delay

Digital I/O Quiet Time from CNV

PD High Time

PD Low Time t

WAKE

REFBUF Wake-Up Time

CMOS I/O Mode

↑ t t t

SCKI t

SCKIH t

SCKIL t

SSDISCKI t

HSDISCKI t

DSDOSCKI t

HSDOSCKI

SCKI Period

SCKI High Time

SCKI Low Time

SDI Setup Time from SCKI

SDI Hold Time from SCKI

SDO Data Valid Delay from SCKI ↑

SDO Remains Valid Delay from SCKI ↑

SDO to SCKO Skew t

SKEW t

DSDOBUSYL t

EN

SDO Data Valid Delay from BUSY ↓

Bus Enable Time After CS ↓ t

DIS

Bus Relinquish Time After CS ↑

LVDS I/O Mode

SCKI Period t

SCKI t

SCKIH t

SCKIL t

SSDISCKI t

HSDISCKI t

DSDOSCKI

SCKI High Time

SCKI Low Time

SDI Setup Time from SCKI

SDI Hold Time from SCKI

SDO Data Valid Delay from SCKI

HSDOSCKI

SKEW t

DSDOBUSYL t

EN t

DIS

SDO Remains Valid Delay from SCKI

SDO to SCKO Skew

SDO Data Valid Delay from BUSY

Bus Enable Time After CS

Bus Relinquish Time After

CS

C

L

= 25pF

C

REFBUF

= 47μF, C

REFIN

= 0.1μF

(Notes 16, 17)

(Note 16)

(Note 16)

C

L

= 25pF (Note 16)

C

L

= 25pF (Note 16)

(Note 16)

C

L

= 25pF (Note 16)

(Note 16)

(Note 16)

(Note 18)

(Note 18)

(Note 18)

(Notes 10, 18)

(Notes 10, 18)

(Notes 10, 18)

(Notes 10, 18)

(Note 10)

(Note 10) l l l l l l l l l l l l l l l l l l l l l l l l l l

1.5

–1

0

4

1.5

1.5

1.2

–0.2

10

4

4

2

1

20

40

40

1

–0.4

0

200

0

0

30

7.5

1

15

15

6

0.4

50

15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns

For more information www.linear.com/LTC2345-16

234516f

7

LTC2345-16

aDc TiMing characTerisTics

Note 1:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2:

All voltage values are with respect to ground.

Note 3:

V

DDLBYP

is the output of an internal voltage regulator, and should only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, as described in the Pin Functions section. Do not connect this pin to any external circuitry.

Note 4:

When these pin voltages are taken below ground or above V

OV

DD currents of up to 100mA below ground or above V

DD latch-up.

or OV

DD

DD

without

or

, they will be clamped by internal diodes. This product can handle

Note 5:

V

DD

= 5V unless otherwise specified.

Note 6:

Recommended operating conditions.

Note 7:

Exceeding these limits on any channel may corrupt conversion results on other channels. Refer to Absolute Maximum Ratings section for pin voltage limits related to device reliability.

Note 8:

V

DD

= 5V, OV

DD

= 2.5V, f

SMPL

= 200ksps, internal reference and buffer, fully differential input signal drive in SoftSpan ranges 7 and 6, bipolar input signal drive in SoftSpan ranges 3 and 2, unipolar input signal drive in SoftSpan ranges 5, 4 and 1, unless otherwise specified.

Note 9:

Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 10:

Guaranteed by design, not subject to test.

Note 11:

For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale error for these SoftSpan ranges is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. For unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage measured from 0.5LSB when the output code flickers between 0000 0000

0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan ranges is the worst-case deviation of the last code transition from ideal and includes the effect of offset error.

Note 12:

All specifications in dB are referred to a full-scale input in the relevant SoftSpan input range, except for crosstalk, which is referred to the crosstalk injection signal amplitude.

Note 13:

Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.

Note 14:

When REFBUF is overdriven, the internal reference buffer must be disabled by setting REFIN = 0V.

Note 15:

I

REFBUF active channels.

varies proportionally with sample rate and the number of

Note 16:

Parameter tested and guaranteed at OV

DD and OV

DD

= 5.25V.

= 1.71V, OV

DD

= 2.5V,

Note 17:

A t

SCKI

period of 10ns minimum allows a shift clock frequency of up to 100MHz for rising edge capture.

Note 18:

V

ICM

= 1.2V, V

ID

= 350mV for LVDS differential input pairs.

CMOS Timings

0.8 • OV

DD t

DELAY

0.8 • OV

DD

0.2 • OV

DD

0.2 • OV

DD t

DELAY

0.8 • OV

DD

0.2 • OV

DD

50%

LVDS Timings (Differential)

t

WIDTH

50%

+200mV t

DELAY

+200mV

–200mV t

WIDTH

–200mV t

DELAY

+200mV

–200mV

0V

Figure 1. Voltage Levels for Timing Specifications

0V

234516 F01

234516 F01b

234516f

8

For more information www.linear.com/LTC2345-16

LTC2345-16

Typical perForMance characTerisTics

Reference and Buffer (V

REFBUF

 = 4.096V), f

SMPL

T

A

= 200ksps, unless otherwise noted.

= 25°C, V

DD

 = 5V, OV

DD

 = 2.5V, Internal

1.00

Integral Nonlinearity vs Output Code and Channel

0.75

0.50

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN

+

)

ALL CHANNELS

0.25

0

1.00

Differential Nonlinearity vs Output Code and Channel

0.75

ALL RANGES

ALL CHANNELS

0.50

0.25

0

1.00

Integral Nonlinearity vs Output Code and Range

0.75

BIPOLAR DRIVE (IN

= 2.5V)

ONE CHANNEL

0.50

0.25

±2.048V AND ±2V

RANGES

0

–0.25

–0.50

–0.75

–0.25

–0.50

–0.75

–0.25

–0.50

–0.75

–1.00

–32768 –16384 0

OUTPUT CODE

16384 32768

234516 G01

–1.00

0 16384 32768

OUTPUT CODE

49152 65536

234516 G02

–1.00

–32768 –16384 0

OUTPUT CODE

16384 32768

234516 G03

1.00

Integral Nonlinearity vs Output Code and Range

0.75

FULLY DIFFERENTIAL DRIVE (IN

= –IN

+

)

ONE CHANNEL

0.50

0.25

0

±2.048V AND ±2V

RANGES

–0.25

–0.50

–0.75

–1.00

–32768

±4.096V AND ±4V

RANGES

–16384 0

OUTPUT CODE

16384 32768

234516 G04

0

–0.25

–0.50

–0.75

–1.00

0

1.00

0.75

0.50

Integral Nonlinearity vs Output Code and Range

UNIPOLAR DRIVE (IN

= 0V)

ONE CHANNEL

0V TO 2.048V RANGE

0.25

0V TO 4.096V AND 0V TO 4V RANGES

16384 32768

OUTPUT CODE

49152 65536

234516 G05

Integral Nonlinearity vs Output Code

1.00

0.75

0.50

0.25

0

–0.25

IN

+

/IN

±4.096V RANGE

ARBITRARY DRIVE

COMMON MODE

SWEPT 0V TO 5V

–0.50

–0.75

–1.00

–32768

FULLY DIFFERENTIAL DRIVE (IN

= –IN

+

)

–16384 0

OUTPUT CODE

16384 32768

234516 G06

200000

DC Histogram (Zero-Scale)

±4.096V RANGE

160000

120000

80000

40000

0

–4 –3 –2 –1 0

CODE

1 2 3

234516 G07

4

200000

DC Histogram (Near Full-Scale)

160000

120000

80000

40000

±4.096V RANGE

0

32753 32755 32757

CODE

32759 32761

234516 G08

–100

–120

–140

–160

–180

0

–20

–40

–60

–80

0

f

32k Point FFT f

SMPL

IN

 = 2kHz

 = 200kHz,

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN )

SNR = 91.1dB

THD = –111dB

SINAD = 91.1dB

SFDR = 112dB

20 40 60

FREQUENCY (KHz)

80 100

234516 G09

For more information www.linear.com/LTC2345-16

234516f

9

LTC2345-16

Typical perForMance characTerisTics

T

A

Reference and Buffer (V

REFBUF

 = 4.096V), f

SMPL

= 200ksps, unless otherwise noted.

= 25°C, V

DD

 = 5V, OV

DD

 = 2.5V, Internal

–20

–40

0

f

32k Point Arbitrary Two-Tone FFT

SMPL

 = 200kHz, IN

Sine, IN

+

 = –7dBFS 2kHz

 = –7dBFS 3.1kHz Sine

±4.096V RANGE

ARBITRARY DRIVE

SFDR = 120dB

SNR = 91.3dB

–60

0

–20

–40

–60

0V TO 4.096V RANGE

UNIPOLAR DRIVE (IN

= 0V)

SNR = 85.8dB

THD = –111dB

SINAD = 85.8dB

SFDR = 112dB

92

SNR

–80

–80

f

32k Point FFT f

SMPL

IN

 = 2kHz

= 200kHz,

96

f

SNR, SINAD vs V

REFBUF

IN

 = 2kHz

,

±V

FULLY DIFFERENTIAL DRIVE (IN

RANGE

= –IN

+

)

94

SINAD

–100

–100

90

–120

–120

–140

–140

88

–160

–160

–180

0 20 40 60

FREQUENCY (kHz)

80 100

234516 G10

–180

0 20 40 60

FREQUENCY (kHz)

80 100

234516 G11

86

2.5

3 3.5

4

REFBUF VOLTAGE (V)

4.5

234516 G12

5

–100

f

THD, Harmonics vs V

REFBUF

IN

 = 2kHz

,

–105

±V

FULLY DIFFERENIAL DRIVE (IN

RANGE

= –IN

+

)

THD –110

–115

–120

–125

–130

–135

–140

2.5

3

2ND

3RD

3.5

4

REFBUF VOLTAGE (V)

4.5

234516 G13

5

102

SNR, SINAD vs Input Frequency

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN )

98

94

90

86

82

78

100 1k 10k

FREQUENCY (Hz)

SNR

SINAD

100k

234516 G14

–70

THD, Harmonics vs Input Frequency

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN )

–80

–90

–100

–110

THD

2ND

–120

3RD

–130

100 1k 10k

FREQUENCY (Hz)

100k

234516 G15

–100

THD, Harmonics vs Input

Common Mode, f

IN

= 2kHz

1V

PP

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE

–105

–110

–115

–120

–125

–130

0

3RD

THD

2ND

1 2 3

INPUT COMMON MODE (V)

4

234516 G16

5

92.0

f

SNR, SINAD vs Input Level,

IN

 = 2kHz

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN )

91.8

SNR

91.6

SINAD

91.4

91.2

91.0

–40 –30 –20

INPUT LEVEL (dBFS)

–10

234516 G17

0

120

110

100

150

CMRR vs Input Frequency and

Channel

140

IN

+

= IN

±4.096V RANGE

= 3.6V

pp

SINE

ALL CHANNELS

130

90

80

10 100 1k 10k

FREQUENCY (Hz)

100k 1M

234516 G18

234516f

10

For more information www.linear.com/LTC2345-16

LTC2345-16

Typical perForMance characTerisTics

Reference and Buffer (V

REFBUF

 = 4.096V), f

SMPL

T

A

= 200ksps, unless otherwise noted.

= 25°C, V

DD

 = 5V, OV

DD

 = 2.5V, Internal

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

10

Crosstalk vs Input Frequency and

Channel

100

IN0

+

= –IN0

±4.096V RANGE

= 3.6V

PP

SINE

ALL CHANNELS CONVERTING

1k 10k

FREQUENCY (Hz)

100k

CH1

CH7

1M

234516 G19

93.0

f

SNR, SINAD vs Temperature,

IN

 = 2kHz

92.5

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN )

92.0

91.5

91.0

90.5

90.0

SINAD

SNR

89.5

89.0

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G20

–105

f

THD, Harmonics vs Temperature,

IN

= 2kHz

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN )

–110

–115

–120

–125

–130

THD

2ND

3RD

–135

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G21

INL, DNL vs Temperature

0.5

0.4

0.3

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN = –IN )

0.2

0.1

MAX INL

0.0

–0.1

–0.2

MAX DNL

MIN DNL

MIN INL

–0.3

–0.4

–0.5

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G22

0.100

Positive Full-Scale Error vs

Temperature and Channel

0.075

±4.096V RANGE

ALL CHANNELS

0.050

0.025

0.000

–0.025

–0.050

–0.075

–0.100

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G23

0.100

Negative Full-Scale Error vs

Temperature and Channel

0.075

±4.096V RANGE

ALL CHANNELS

0.050

0.025

0.000

–0.025

–0.050

–0.075

–0.100

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G24

Zero-Scale Error vs

Temperature and Channel

3

2

1

5

4

±4.096V RANGE

ALL CHANNELS

0

–1

–2

–3

–4

–5

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G25

Supply Current vs Temperature

20

18

16

14

12

10

I

VDD

8

6

4

2

0

–2

I

OVDD

–4

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G26

1000

Power-Down Current vs Temperature

I

VDD

100

10

1

0.1

I

OVDD

0.01

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G27

For more information www.linear.com/LTC2345-16

234516f

11

LTC2345-16

Typical perForMance characTerisTics

Reference and Buffer (V

REFBUF

 = 4.096V), f

SMPL

T

A

= 200ksps, unless otherwise noted.

= 25°C, V

DD

 = 5V, OV

DD

 = 2.5V, Internal

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

1.0

0.8

0.6

0.4

Offset Error vs Input Common

Mode and Channel

±4.096V RANGE

ALL CHANNELS

1 2 3

INPUT COMMON MODE (V)

4

234516 G28

5

18

Supply Current vs Sampling Rate

16

14

12

10

8

6

4

2

0

0

I

VDD

I

OVDD

40 80 120 160

SAMPLING FREQUENCY (kHz)

200

234516 G31

2.052

Internal Reference Output vs Temperature

15 UNITS

2.051

2.050

2.049

2.048

2.047

2.046

2.045

2.044

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

234516 G29

150

140

130

120

110

100

90

80

70

60

50

10

PSRR vs Frequency

100

OV

DD

V

DD

1k 10k

FREQUENCY (Hz)

IN

+

= IN

= 0V

100k 1M

234516 G30

50

40

30

20

10

0

0

90

Power Dissipation vs Sampling

Rate, N Channels Enabled

80

N = 8

N = 4

N = 2

70

N = 1

60

200 400 600 800

SAMPLING FREQUENCY (kHz)

1000

234516 G32

32768

Step Response

(Large-Signal Settling)

24576

16384

8192

0

–8192

±2.048V RANGE

IN

IN

= 200.0061kHz SQUARE WAVE

= 2.048V

DRIVEN BY 50Ω SOURCE

–16384

–24576

–32768

–50 0 50 100 150 200 250 300 350 400 450

SETTLING TIME (ns)

234516 G33

Step Response (Fine Settling)

100

80

60

40

20

0

–20

–40

–60

–80

±2.048V RANGE

IN

+

= 200.0061kHz

SQUARE WAVE

IN

= 2.048V

DRIVEN BY 50Ω SOURCE

–100

–50 0 50 100 150 200 250 300 350 400 450

SETTLING TIME (ns)

234516 G34

234516f

12

For more information www.linear.com/LTC2345-16

LTC2345-16

pin FuncTions

Pins that are the Same for All Digital I/O Modes

IN0

+

to IN7

+

, IN0

to IN7

(Pins 1, 2, 3, 4, 5, 6, 7, 8, 9,

10, 11, 12, 13, 14, 47, and 48):

Positive and Negative

Analog Inputs, Channels 0 to 7. The converter simultaneously samples and digitizes (V

IN

+ – V

IN

–) for all channels.

Wide input common mode range (0V ≤ V

CM

≤ V

DD

) and high common mode rejection allow the inputs to accept a wide variety of signal swings. Full-scale input range is determined by the channel’s SoftSpan configuration.

GND (Pins 15, 16, 17, 18, 20, 30, 41, 44, 45, 46, 49):

Ground. Solder all GND pins to a solid ground plane.

REFIN (Pin 19):

Bandgap Reference Output/Reference

Buffer Input. An internal bandgap reference nominally outputs 2.048V on this pin. An internal reference buffer amplifies V

REFIN

to create the converter master reference voltage V

REFBUF

= 2 •  V

REFIN

on the REFBUF pin. When using the internal reference, bypass REFIN to GND (Pin

20) close to the pin with a 0.1μF ceramic capacitor to filter the bandgap output noise. If more accuracy is desired, overdrive REFIN with an external reference in the range of 1.25V to 2.2V.

REFBUF (Pin 21):

Internal Reference Buffer Output. An internal reference buffer amplifies V converter master reference voltage V

REFIN

REFBUF

to create the

= 2 •  V

REFIN

on this pin, nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 20) close to the pin with a 47μF ceramic capacitor. The internal reference buffer may be disabled by grounding its input at REFIN.

With the buffer disabled, overdrive REFBUF with an external reference voltage in the range of 2.5V to 5V. When using the internal reference buffer, limit the loading of any external circuitry connected to REFBUF to less than 10µA.

Using a high input impedance amplifier to buffer V

REFBUF to any external circuits is recommended.

PD (Pin 22):

Power Down Input. When this pin is brought high, the LTC2345-16 is powered down and subsequent conversion requests are ignored. If this occurs during a conversion, the device powers down once the conversion completes. If this pin is brought high twice without an intervening conversion, an internal global reset is initiated, equivalent to a power-on-reset event. Logic levels are determined by OV

DD

.

LVDS/ CMOS (Pin 23):

I/O Mode Select. Tie this pin to OV mode. Logic levels are determined by OV

DD

.

DD to select LVDS I/O mode, or to ground to select CMOS I/O

CNV (Pin 24):

Conversion Start Input. A rising edge on this pin puts the internal sample-and-holds into the hold mode and initiates a new conversion. CNV is not gated by CS , allowing conversions to be initiated independent of the state of the serial I/O bus.

BUSY (Pin 38):

Busy Output. The BUSY signal indicates that a conversion is in progress. This pin transitions lowto-high at the start of each conversion and stays high until the conversion is complete. Logic levels are determined by OV

DD

.

V

DDLBYP

(Pin 40):

Internal 2.5V Regulator Bypass Pin. The voltage on this pin is generated via an internal regulator operating off of V

DD

. This pin must be bypassed to GND close to the pin with a 2.2μF ceramic capacitor. Do not connect this pin to any external circuitry.

V

DD

(Pins 42, 43):

5V Power Supply. The range of V is 4.75V to 5.25V. Connect Pins 42 and 43 together and bypass the V

DD

DD

network to GND with a shared 0.1μF ceramic capacitor close to the pins.

For more information www.linear.com/LTC2345-16

234516f

13

LTC2345-16

pin FuncTions

CMOS I/O Mode

SDO0 to SDO7 (Pins 25, 26, 27, 28, 33, 34, 35, and 36):

CMOS Serial Data Outputs, Channels 0 to 7. The most recent conversion result along with channel configuration information is clocked out onto the SDO pins on each rising edge of SCKI. Output data formatting is described in the Digital Interface section. Leave unused SDO outputs unconnected. Logic levels are determined by OV

DD

.

SCKI (Pin 29):

CMOS Serial Clock Input. Drive SCKI with the serial I/O clock. SCKI rising edges latch serial data in on SDI and clock serial data out on SDO0 to SDO7. For standard SPI bus operation, capture output data at the receiver on rising edges of SCKI. SCKI is allowed to idle either high or low. Logic levels are determined by OV

DD

.

OV

DD

(Pin 31):

I/O Interface Power Supply. In CMOS I/O mode, the range of OV

DD

is 1.71V to 5.25V. Bypass OV

DD to GND (Pin 30) close to the pin with a 0.1μF ceramic capacitor.

SCKO (Pin 32):

CMOS Serial Clock Output. SCKI rising edges trigger transitions on SCKO that are skew-matched to the serial output data streams on SDO0 to SDO7. The resulting SCKO frequency is half that of SCKI. Rising and falling edges of SCKO may be used to capture SDO data at the receiver (FPGA) in double data rate (DDR) fashion. For standard SPI bus operation, SCKO is not used and should be left unconnected. SCKO is forced low at the falling edge of BUSY. Logic levels are determined by OV

DD

.

SDI (Pin 37):

CMOS Serial Data Input. Drive this pin with the desired 24-bit SoftSpan configuration word (see Table 1a), latched on the rising edges of SCKI. If all channels will be configured to operate only in SoftSpan 7, tie SDI to OV

Logic levels are determined by OV

DD

.

DD

.

CS (Pin 39):

Chip Select Input. The serial data I/O bus is enabled when CS is low and is disabled and Hi-Z when

CS is high. CS also gates the external shift clock, SCKI.

Logic levels are determined by OV

DD

.

LVDS I/O Mode

SDO0, SDO7, SDI (Pins 25, 36 and 37):

CMOS Serial

Data I/O. In LVDS I/O mode, these pins are Hi-Z.

SDI

+

SCKI

, SDI

(Pins 26 and 27):

LVDS Positive and Negative

Serial Data Input. Differentially drive SDI

. The SDI

+

/SDI

+

/SDI

+

/

input pair is internally terminated with a 100Ω differential resistor when CS = 0.

with the desired 24-bit SoftSpan configuration word (see Table

1a), latched on both the rising and falling edges of SCKI

SCKI

+

, SCKI

(Pins 28 and 29):

LVDS Positive and Negative

Serial Clock Input. Differentially drive SCKI the serial I/O clock. SCKI

+

/SCKI

+

/SCKI

with

rising and falling edges

and clock serial data out latch serial data in on SDI on SDO

+

/SDO

+

. Idle SCKI transitioning CS . The SCKI

/SDI

+

/SCKI

+

/SCKI

low, including when

input pair is internally terminated with a 100Ω differential resistor when CS = 0.

OV

DD

(Pin 31):

I/O Interface Power Supply. In LVDS I/O mode, the range of OV

DD

is 2.375V to 5.25V. Bypass OV

DD to GND (Pin 30) close to the pin with a 0.1μF ceramic capacitor.

SCKO

Negative Serial Clock Output. SCKO copy of the input serial I/O clock received on SCKI

SDO

+

, SCKO

(Pins 32 and 33):

LVDS Positive and to capture SDO

SCKO

+

/SCKO

outputs a

. Use the rising and falling edges of SCKO

+

/SCKO

+

/SDO

output pair must be differentially terminated with a 100Ω resistor at the receiver (FPGA).

+

+

/SCKI skew-matched with the serial output data stream on SDO

/SCKO

+

/

,

data at the receiver (FPGA). The

SDO

SCKI

+

+

, SDO

/SCKI

(Pins 34 and 35):

LVDS Positive and Negative Serial Data Output. The most recent conversion result along with channel configuration information is clocked out onto SDO

+

/SDO

on both rising and falling edges of

, beginning with channel 0. The SDO resistor at the receiver (FPGA).

+

/SDO

– output pair must be differentially terminated with a 100Ω

CS (Pin 39):

Chip Select Input. The serial data I/O bus is enabled when CS is low, and is disabled and Hi-Z when

CS is high.

SCKI

CS also gates the external shift clock, SCKI

+

/

. The internal 100Ω differential termination resistors on the SCKI

+

/SCKI

and SDI

+

/SDI

input pairs are disabled when CS is high. Logic levels are determined by OV

DD

.

234516f

14

For more information www.linear.com/LTC2345-16

LTC2345-16

conFiguraTion Tables

Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each

Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 24-Bit SoftSpan Configuration Word S[23:0]. Use

Serial Interface to Write SoftSpan Configuration Word to LTC2345-16, as shown in Figure 19

BINARY SoftSpan CODE

SS[2:0]

011

010

001

000

111

110

101

100

ANALOG INPUT RANGE

±V

REFBUF

±V

REFBUF

0V to V

REFBUF

0V to V

/1.024

REFBUF

/1.024

±0.5 • V

REFBUF

±0.5 • V

REFBUF

/1.024

0V to 0.5 • V

REFBUF

Channel Disabled

FULL SCALE RANGE

2 • V

REFBUF

2 •

V

V

REFBUF

/1.024

V

REFBUF

REFBUF

/1.024

V

REFBUF

V

REFBUF

0.5 • V

/1.024

REFBUF

Channel Disabled

BINARY FORMAT OF

CONVERSION RESULT

Two’s Complement

Two’s Complement

Straight Binary

Straight Binary

Two’s Complement

Two’s Complement

Straight Binary

All Zeros

Table 1b. Reference Configuration Table. The LTC2345-16 Supports Three Reference Configurations. Analog Input Range Scales with the Converter Master Reference Voltage, V

REFBUF

REFERENCE CONFIGURATION V

REFIN

V

REFBUF

BINARY SoftSpan CODE

SS[2:0]

ANALOG INPUT RANGE

Internal Reference with

Internal Buffer

External Reference with

Internal Buffer

(REFIN Pin Externally

Overdriven)

2.048V

1.25V

(Min Value)

2.2V

(Max Value)

4.096V

2.5V

4.4V

011

010

001

111

110

101

111

110

101

100

100

011

010

001

111

110

101

100

011

010

±4.096V

±4V

0V to 4.096V

0V to 4V

±2.048V

±2V

0V to 2.048V

±2.5V

±2.441V

0V to 2.5V

0V to 2.441V

±1.25V

±1.221V

0V to 1.25V

±4.4V

±4.297V

0V to 4.4V

0V to 4.297V

±2.2V

±2.148V

001 0V to 2.2V

For more information www.linear.com/LTC2345-16

234516f

15

LTC2345-16

conFiguraTion Tables

Table 1b. Reference Configuration Table (Continued). The LTC2345-16 Supports Three Reference Configurations. Analog Input Range

Scales with the Converter Master Reference Voltage, V

REFBUF

REFERENCE CONFIGURATION

External Reference

Unbuffered

(REFBUF Pin

Externally Overdriven,

REFIN Pin Grounded)

V

REFIN

0V

0V

V

REFBUF

2.5V

(Min Value)

5V

(Max Value)

BINARY SoftSpan CODE

SS[2:0]

111

110

101

100

011

010

001

111

110

101

100

011

010

001

ANALOG INPUT RANGE

±2.5V

±2.441V

0V to 2.5V

0V to 2.441V

±1.25V

±1.221V

0V to 1.25V

±5V

±4.883V

0V to 5V

0V to 4.883V

±2.5V

±2.441V

0V to 2.5V

16

For more information www.linear.com/LTC2345-16

234516f

LTC2345-16

FuncTional block DiagraM

CMOS I/O Mode

V

DD

V

DDLBYP

LTC2345-16

2.5V

REGULATOR

IN6

+

IN6

IN7

+

IN7

IN4

+

IN4

IN5

+

IN5

IN2

+

IN2

IN3

+

IN3

IN0

+

IN0

IN1

+

IN1

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

16-BIT

SAR ADC

2.048V

REFERENCE

20k

REFERENCE

BUFFER

2

×

GND REFIN REFBUF

16 BITS

CMOS

SERIAL

I/O

INTERFACE

OV

DD

SDO0

SDO7

SCKO

SDI

SCKI

CS

CONTROL

LOGIC

BUSY

CNV PD LVDS/ CMOS

234516 BD01

For more information www.linear.com/LTC2345-16

234516f

17

LTC2345-16

FuncTional block DiagraM

LVDS I/O Mode

IN6

+

IN6

IN7

+

IN7

IN4

+

IN4

IN5

+

IN5

IN2

+

IN2

IN3

+

IN3

IN0

+

IN0

IN1

+

IN1

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

V

DD

V

DDLBYP

LTC2345-16

2.5V

REGULATOR

16-BIT

SAR ADC

OV

DD

16 BITS

LVDS

SERIAL

I/O

INTERFACE

SDO

+

SDO

SCKO

+

SCKO

SDI

+

SDI

SCKI

+

SCKI

CS

2.048V

REFERENCE

20k

REFERENCE

BUFFER

2 ×

GND REFIN REFBUF

CONTROL

LOGIC

BUSY

CNV PD LVDS/ CMOS

234516 BD02

18

For more information www.linear.com/LTC2345-16

234516f

LTC2345-16

TiMing DiagraM

CS = PD = 0

SAMPLE N

CNV

BUSY

SCKI

SDI

CONVERT

DON’T CARE

SCKO

SDO0

SDO7

DON’T CARE

DON’T CARE

CMOS I/O Mode

SAMPLE N + 1

ACQUIRE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15

CONVERSION RESULT

CHANNEL 0

CONVERSION N

CHANNEL ID SoftSpan CONVERSION RESULT

CHANNEL 1

CONVERSION N

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15

CONVERSION RESULT

CHANNEL 7

CONVERSION N

CHANNEL ID SoftSpan CONVERSION RESULT

CHANNEL 0

CONVERSION N

234516 TD01

LVDS I/O Mode

CS = PD = 0

CNV

(CMOS)

SAMPLE N

BUSY

(CMOS)

SCKI

(LVDS)

CONVERT

SDI

(LVDS)

DON’T CARE S23

ACQUIRE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1

24

S0

25 26 186 187 188 189 190 191 192

SAMPLE

N + 1

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

SCKO

(LVDS)

SDO

(LVDS)

DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0

CONVERSION RESULT

CHANNEL 0

CONVERSION N

C2 C1 C0 SS2 SS1 SS0 D15 D14 D13

CHANNEL ID SoftSpan

CHANNEL 1

CONVERSION N

0 C2 C1 C0 SS2 SS1 SS0 D15

CHANNEL ID SoftSpan

CONVERSION

RESULT

CHANNEL 7

CONVERSION N

CHANNEL 0

CONVERSION N

234516 TD02

For more information www.linear.com/LTC2345-16

234516f

19

LTC2345-16

applicaTions inForMaTion

OVERVIEW

The LTC2345-16 is a 16-bit, low noise 8-channel simultaneous sampling successive approximation register

(SAR) ADC with differential, wide common mode range inputs. Using the integrated low-drift reference and buffer

(V

REFBUF 

= 4.096V nominal), each channel of this SoftSpan

ADC can be independently configured on a conversionby-conversion basis to accept ±4.096V, 0V to 4.096V,

±2.048V, or 0V to 2.048V signals. The input signal range may be expanded up to ±5V using an external 5V reference. Individual channels may also be disabled to increase throughput on the remaining channels.

The wide input common mode range and high CMRR

(102dB typical, V

IN

+ = V

IN

– = 3.6V

P-P

200Hz Sine) of the

LTC2345-16 analog inputs allow the ADC to directly digitize a variety of signals, simplifying signal chain design.

This input signal flexibility, combined with ±1.25LSB INL, no missing codes at 16-bits, and 91dB SNR, makes the

LTC2345-16 an ideal choice for many applications requiring wide dynamic range.

The LTC2345-16 supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces, enabling it to communicate equally well with legacy microcontrollers and modern FPGAs. In CMOS mode, applications may employ between one and eight lanes of serial output data, allowing the user to optimize bus width and data throughput. The

LTC2345-16 typically dissipates 81mW when converting eight analog input channels simultaneously at 200ksps per channel throughput. An optional power-down mode may be employed to further reduce power consumption during inactive periods.

CONVERTER OPERATION

The LTC2345-16 operates in two phases. During the acquisition phase, the sampling capacitors in each channel’s sample-and-hold (S/H) circuit connect to their respective analog input pins and track the differential analog input voltage (V

IN

+ – V

IN

–). A rising edge on the CNV pin transitions all channels’ S/H circuits from track mode to hold mode, simultaneously sampling the input signals on all channels and initiating a conversion. During the conversion phase, each channel’s sampling capacitors are connected, one channel at a time, to a 16-bit charge redistribution capacitor D/A converter (CDAC). The CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input voltage with binary-weighted fractions of the channel’s SoftSpan full-scale range

(e.g., V

FSR

/2, V

FSR

/4 … V

FSR

/65536) using a differential comparator. At the end of this process, the CDAC output approximates the channel’s sampled analog input. Once all channels have been converted in this manner, the ADC control logic prepares the 16-bit digital output codes from each channel for serial transfer.

TRANSFER FUNCTION

The LTC2345-16 digitizes each channel’s full-scale voltage range into 2

16

levels. In conjunction with the ADC master reference voltage, V

REFBUF

, a channel’s SoftSpan configuration determines its input voltage range, full-scale range,

LSB size, and the binary format of its conversion result, as shown in Tables 1a and 1b. For example, employing the internal reference and buffer (V

REFBUF

= 4.096V nominal),

SoftSpan 7 configures a channel to accept a ±4.096V bipolar analog input voltage range, which corresponds to a

8.192V full-scale range with a 125μV LSB. Other SoftSpan configurations and reference voltages may be employed to convert both larger and smaller bipolar and unipolar input ranges. Conversion results are output in two’s complement binary format for all bipolar SoftSpan ranges, and in straight binary format for all unipolar SoftSpan ranges.

The ideal two’s complement transfer function is shown in

Figure 2, while the ideal straight binary transfer function is shown in Figure 3.

234516f

20

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

011...111

011...110

000...001

000...000

111...111

111...110

BIPOLAR

ZERO

100...001

100...000

–FSR/2

FSR = +FS – –FS

1LSB = FSR/65536

–1

LSB

0V 1

LSB

INPUT VOLTAGE (V)

FSR/2 – 1LSB

234516 F02

Figure 2. LTC2345-16 Two’s Complement Transfer Function

111...111

111...110

100...001

100...000

011...111

011...110

UNIPOLAR

ZERO

000...001

000...000

0V

FSR = +FS

1LSB = FSR/65536

INPUT VOLTAGE (V)

FSR – 1LSB

235816 F03

Figure 3. LTC2345-16 Straight Binary Transfer Function

ANALOG INPUTS

Each channel of the LTC2345-16 simultaneously samples the voltage difference (V

IN

+ – V

IN

–) between its analog input pins over a wide common mode input range while attenuating unwanted signals common to both input pins by the common-mode rejection ratio (CMRR) of the ADC. Wide common mode input range coupled with high CMRR allows the IN

+

/IN

analog inputs to swing with an arbitrary relationship to each other, provided each pin remains between ground and V

DD

. This unique feature of the LTC2345-16 enables it to accept a wide variety of signal swings, including traditional classes of analog input signals such as pseudo-differential unipolar, pseudo-differential bipolar, and fully differential, simplifying signal chain design.

In all SoftSpan ranges, each channel’s analog inputs can be modeled by the equivalent circuit shown in Figure 4.

At the start of acquisition, the 40pF sampling capacitors

(C

(R

IN

) connect to the analog input pins IN

+

/IN

through the sampling switches, each of which has approximately 130Ω

IN

) of on-resistance. The initial voltage on both sampling capacitors at the start of acquisition is approximately equal to the sampled common-mode voltage (V to IN

IN

+ + V

IN

–)/2 from the prior conversion. The external circuitry connected

+

and IN

must source or sink the charge that flows through R

IN

as the sampling capacitors settle from their initial voltages to the new input pin voltages over the course of the acquisition interval. During conversion and power down modes, the analog inputs draw only a small leakage current. The diodes at the inputs provide ESD protection.

IN

+

IN

V

DD

V

DD

R

IN

130Ω

C

IN

40pF

R

IN

130Ω

C

IN

40pF

BIAS

VOLTAGE

234516 F04

Figure 4. Equivalent Circuit for Differential Analog Inputs,

Single Channel Shown

For more information www.linear.com/LTC2345-16

234516f

21

LTC2345-16

applicaTions inForMaTion

Bipolar SoftSpan Input Ranges

For channels configured in SoftSpan ranges 7, 6, 3, or

2, the LTC2345-16 digitizes the differential analog input voltage (V

±V

REFBUF

IN

+ – V

IN

–) over a bipolar span of ±V

REFBUF

/1.024, ±0.5 • V

REFBUF

, or ±0.5 • V

REFBUF

,

/1.024, respectively, as shown in Table 1a. These SoftSpan ranges are useful for digitizing input signals where IN

+

and IN include fully differential input signals, where IN

+

– swing above and below each other. Traditional examples

IN

and

are driven 180 degrees out-of-phase with respect to each other centered around a common mode voltage

(V

IN

+  +  V

IN

–)/2, and pseudo-differential bipolar input signals, where IN level, driven on IN

+

swings above and below a reference

. Regardless of the chosen SoftSpan range, the wide common mode input range and high CMRR of the IN

+

/IN

analog inputs allow them to swing with an arbitrary relationship to each other, provided each pin remains between ground and V

DD

. The output data format for all bipolar SoftSpan ranges is two’s complement.

Unipolar SoftSpan Input Ranges

For channels configured in SoftSpan ranges 5, 4, or 1, the

LTC2345-16 digitizes the differential analog input voltage

(V

IN to V

+ – V

IN

–) over a unipolar span of 0V to V

REFBUF

REFBUF

/1.024, or 0V to 0.5 • V

REFBUF

, 0V

, respectively, as shown in Table 1a. These SoftSpan ranges are useful for

. A digitizing input signals where IN

+

remains above IN traditional example includes pseudo-differential unipolar input signals, where IN level, driven on IN the IN

+

swings above a ground reference

. Regardless of the chosen SoftSpan range, the wide common mode range and high CMRR of

+

/IN

analog inputs allow them to swing with an arbitrary relationship to each other, provided each pin remains between ground and V

DD

. The output data format for all unipolar SoftSpan ranges is straight binary.

INPUT DRIVE CIRCUITS

The initial voltage on each channel’s sampling capacitors at the start of acquisition must settle to the new input pin voltages during the acquisition interval. The external circuitry connected to IN

+

and IN the charge that flows through R

IN

must source or sink

as this settling occurs.

The LTC2345-16 sampling network RC time constant of

5.2ns implies a 16-bit settling time to a full-scale step of approximately 11 • ( R

IN

 •  C

IN

) = 57ns. The impedance and self-settling of external circuitry connected to the analog input pins will increase the overall settling time required.

Low impedance sources can directly drive the inputs of the LTC2345-16 without gain error, but high impedance sources should be buffered to ensure sufficient settling during acquisition and to optimize the linearity and distortion performance of the ADC. Settling time is an important consideration even for DC input signals, as the voltages on the sampling capacitors will differ from the analog input pin voltages at the start of acquisition.

Most applications should use a buffer amplifier to drive the analog inputs of the LTC2345-16. The amplifier provides low output impedance, enabling fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the charge flow at the analog inputs when entering acquisition.

Input Filtering

The noise and distortion of an input buffer amplifier and other supporting circuitry must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier with a lowbandwidth filter to minimize noise. The simple one-pole

RC lowpass filter shown in Figure 5 is sufficient for many applications.

At the output of the buffer, a lowpass RC filter network formed by the 130Ω sampling switch on-resistance (R

IN

) and the 40pF sampling capacitance (C

IN

) limits the input bandwidth on each channel to 31MHz, which is fast enough to allow for sufficient transient settling during acquisition while simultaneously filtering driver wideband noise. A buffer amplifier with low noise density should be selected to minimize SNR degradation over this bandwidth. An additional filter network may be placed between the buffer output and ADC input to further minimize the noise contribution of the buffer and reduce disturbances to the buffer from ADC acquisition transients. A simple one-pole lowpass RC filter is sufficient for many applications. It is important that the RC time constant of this filter be small

234516f

22

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

UNIPOLAR

INPUT SIGNAL

5V

0V

LOWPASS

SIGNAL FILTER

160Ω

10nF

+

BUFFER

AMPLIFIER

IN0

+

IN0

LTC2345-16

BW = 100kHz

ONLY CHANNEL 0 SHOWN FOR CLARITY

Figure 5. Unipolar Signal Chain with Input Filtering

234516 F05 enough to allow the analog inputs to completely settle to

16-bit resolution within the ADC acquisition time (t

ACQ

), as insufficient settling can limit INL and THD performance.

Also note that the minimum acquisition time varies with sampling frequency (f channels.

SMPL

) and the number of enabled

High quality capacitors and resistors should be used in the RC filters since these components can add distortion.

NPO/COG and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems.

Buffering Arbitrary and Fully Differential Analog Input

Signals

The wide common mode input range and high CMRR of the LTC2345-16 allow each channel’s IN

+

and IN to swing with an arbitrary relationship to each other, provided each pin remains between ground and V

DD

pins

. This unique feature of the LTC2345-16 enables it to accept a wide variety of signal swings, simplifying signal chain design. In many applications, connecting a channel’s IN and IN

+

pins directly to the existing signal chain circuitry will not allow the channel’s sampling network to settle to

16-bit resolution within the ADC acquisition time (t

ACQ

). In these cases, it is recommended that two unity-gain buffers be inserted between the signal source and the ADC input pins, as shown in Figure 6a. Table 2 lists several amplifier and lowpass filter combinations recommended for use in this circuit. The LT6237 combines fast settling, high linearity, and low offset with 1.1nV/√ Hz input-referred noise density, enabling it to achieve the full ADC data sheet SNR and THD specifications, as shown in the FFT plots in Figures 6b to 6e. In applications where slightly degraded SNR performance is acceptable, it is possible to drive the LTC2345-16 using the lower-power LT6234.

The LT6234 combines fast settling, good linearity, and low offset with 1.9nV/√ Hz input-referred noise density, enabling it to drive the LTC2345-16 with only 0.3dB SNR loss compared with the LT6237 when a 40.2Ω, 1nF filter is employed. As shown in Table 2, the LT6237 may be used without a lowpass filter at a loss of ≤1dB SNR due to increased wideband noise.

Table 2. Recommended Amplifier and Filter Combinations for the Buffer Circuits in Figures 6a and 9. AC Performance Measured

Using Circuit in Figure 6a, ±4.096V Range for Fully Differential Input Drive, ±2.048V Range for Bipolar Input Drive

AMPLIFIER

R

FILT

(Ω)

C

FILT

(nF)

INPUT SIGNAL DRIVE

SNR

(dB)

THD

(dB)

SINAD

(dB)

SFDR

(dB)

½ LT6237

½ LT6234

½ LT6237

½ LT6234

½ LT6237

½ LT6234

40.2

40.2

40.2

40.2

0

0

1

0

0

1

1

1

FULLY DIFFERENTIAL

FULLY DIFFERENTIAL

BIPOLAR

BIPOLAR

BIPOLAR

BIPOLAR

91.0

90.7

85.8

85.5

85.4

82.1

−114

−114

−110

−110

−110

−108

91.0

90.7

85.8

85.5

85.4

82.1

115

115

112

112

112

110

For more information www.linear.com/LTC2345-16

234516f

23

LTC2345-16

applicaTions inForMaTion

5V

ARBITRARY DIFFERENTIAL

5V

FULLY

6V

OPTIONAL

LOWPASS FILTERS

R

FILT

0V 0V IN+

+

AMPLIFIER

C

FILT

IN0

+

IN0

LTC2345-16

5V

BIPOLAR

5V

UNIPOLAR

0V

0V

DIFFERENTIAL INPUTS IN+ / IN– WITH

WIDE INPUT COMMON MODE RANGE

IN–

+

AMPLIFIER

–2V

R

FILT

C

FILT

REFBUF

47µF

REFIN

0.1µF

ONLY CHANNEL 0 SHOWN FOR CLARITY

234516 F06a

Figure 6a. Buffering Arbitrary, Fully Differential, Bipolar, and Unipolar Signals. See

Table 2 For Recommended Amplifier and Filter Combinations

–20

–40

–60

–80

–100

–120

–140

–160

0

Arbitrary Drive

±4.096V RANGE

ARBITRARY DRIVE

SFDR = 120dB

SNR = 91.3dB

–180

0 20 40 60

FREQUENCY (kHz)

80 100

234516 F06b

Figure 6b. Two-Tone Test. IN

+

= –7dBFS 2kHz Sine, IN

=

–7dBFS 3.1kHz Sine, Common Mode = 2.5V, 32k Point FFT, f

SMPL

= 200ksps. Circuit Shown in Figure 6a with LT6237

Amplifiers, R

FILT

= 40.2Ω, C

FILT

= 1nF

–100

–120

–140

–160

–20

–40

–60

–80

0

Fully Differential Drive

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN = –IN

+

)

SNR = 91.3dB

THD = –113dB

SINAD = 91.2dB

SFDR = 115dB

–180

0 20 40 60

FREQUENCY (kHz)

80 100

234516 F06c

Figure 6c. IN

Shown in Figure 6a with LT6237 Amplifiers, R

C

FILT

= 1nF

+

/IN

= –1dBFS 2kHz Fully Differential Sine,

Common Mode = 2.5V, 32k Point FFT, f

SMPL

= 200ksps. Circuit

FILT

= 40.2Ω,

–20

–40

–60

–80

–100

0

Bipolar Drive

±2.048V RANGE

BIPOLAR DRIVE (IN

= 2.5V)

SNR = 86.0dB

THD = –110dB

SINAD = 86.0dB

SFDR = 113dB

–120

–140

–160

–180

0 20 40 60

FREQUENCY (kHz)

80 100

234516 F06d

Figure 6d. IN

+

= –1dBFS 2kHz Bipolar Sine, IN

Point FFT, f

SMPL

LT6237 Amplifiers, R

FILT

= 40.2Ω, C

FILT

= 1nF

= 2.5V, 32k

= 200ksps. Circuit Shown in Figure 6a with

24

–20

–40

–60

–80

–100

0

Unipolar Drive

0V TO 4.096V RANGE

UNIPOLAR DRIVE (IN

= 0V)

SNR = 86.1dB

THD = –109dB

SINAD = 86.0dB

SFDR = 110dB

–120

–140

–160

–180

0 20 40 60

FREQUENCY (kHz)

80 100

234516 F06e

Figure 6e. IN

FFT, f

SMPL

Amplifiers, R

+

= –1dBFS 2kHz Unipolar Sine, IN

FILT

= 40.2Ω, C

FILT

= 1nF

= 0V, 32k Point

= 200ksps. Circuit Shown in Figure 6a with LT6237

234516f

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

The two-tone test shown in Figure 6b demonstrates the arbitrary input drive capability of the LTC2345-16. This test simultaneously drives IN sine wave and IN

+

with a −7dBFS 2kHz single-ended

with a −7dBFS 3.1kHz single-ended sine wave. Together, these signals sweep the analog inputs across a wide range of common mode and differential mode voltage combinations, similar to the more general arbitrary input signal case. They also have a simple spectral representation. An ideal differential converter with no common-mode sensitivity will digitize this signal as two

−7dBFS spectral tones, one at each sine wave frequency.

The FFT plot in Figure 6b demonstrates the LTC2345-16 response approaches this ideal, with 120dB of SFDR limited by the converter's second harmonic distortion response to the 2kHz sine wave on IN

+

.

The ability of the LTC2345-16 to accept arbitrary signal swings over a wide input common mode range with high

CMRR can simplify application solutions. Figure 7 depicts one way of using the LTC2345-16 to digitize signals of this type. Two channels of the LTC2345-16 simultaneously sense the voltage on and bidirectional current through a sense resistor over a wide common mode range. In many applications of this type, the impedance of the external circuitry is low enough that the ADC sampling network can fully settle without buffering.

The common mode input range of the LTC2345-16 includes

V

DD

, allowing the circuit shown in Figure 8a to amplify and measure a load current (I

LOAD

) from a single 5V supply.

Figure 8b shows a measured transient supply current step of an LTC3207 LED driver load. Note the LTC6252 supplies limit the usable current sense range of this circuit to 50mA to 450mA.

Figure 9a illustrates a more general method of amplifying an input signal. The amplifier stage provides a differential gain of approximately 10V/V to the desired sensor signal while the unwanted common mode signal is attenuated by the ADC CMRR. Figure 9b shows measured CMRR performance of this solution, which is competitive with the best commercially available instrumentation amplifiers.

R

SENSE

V

S1

I

SENSE

V

S2

IN0

+

IN0

LTC2345-16

IN1

+

IN1

REFBUF REFIN

47µF 0.1µF

234516 F07

ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY

I

SENSE

=

V

S1

– V

S2

R

SENSE

0V ≤ V

S1

0V ≤ V

S2

≤ 5V

≤ 5V

Figure 7. Simultaneously Sense Voltage (CH0) and Current

(CH1) Over a Wide Common Mode Range

5V

1Ω 274Ω

2.49k

5V

+

IN0

+

IN0

V

DD

LTC2345-16

I

LOAD

LOAD

LTC6252

REFBUF

47µF

REFIN

0.1µF

ONLY CHANNEL 0 SHOWN FOR CLARITY

234516 F08a

Figure 8a. Sense 50mA to 450mA Current from Single 5V

Supply with Amplification

200

180

160

140

120

100

0V TO 4.096V RANGE

80

0 10 20 30 40 50 60 70 80 90 100

TIME (µs)

234516 F08b

Figure 8b. Transient Supply Current Step Measured Using

Circuit in Figure 8a Loaded with LTC3207 LED Driver

For more information www.linear.com/LTC2345-16

234516f

25

LTC2345-16

applicaTions inForMaTion

IN+

+

6V

½ LT6237

LOWPASS FILTERS

40.2Ω

IN–

2.49k

1nF

549Ω

2.49k

IN0

+

IN0

1nF

LTC2345-16

40.2Ω

+

–2V

½ LT6237 BW ~ 4MHz

ONLY CHANNEL 0 SHOWN FOR CLARITY

REFBUF

47µF

REFIN

0.1µF

234516 F09a

Figure 9a. Digitize Differential Signals with High CMRR

150

140

130

120

110

100

90

IN

+

±4.096V RANGE

= IN

= 5V pp

SINE

80

10 100 1k

FREQUENCY (Hz)

10k 100k

234516 F09b

Figure 9b. CMRR vs Input Frequency. Circuit Shown in Figure 9a

Buffering Single-Ended Analog Input Signals

While the circuit shown in Figure 6a is capable of buffering single-ended input signals, the circuit shown in Figure 10 is preferable when the single-ended signal reference level is inherently low impedance and doesn't require buffering.

This circuit eliminates one driver and lowpass filter, reducing part count, power dissipation, and SNR degradation due to driver noise. Using the recommended driver and filter combinations in Table 2, the performance of this circuit with single-ended input signals is on par with the performance of the circuit in Figure 6a.

ADC REFERENCE

As shown previously in Table 1b, the LTC2345-16 supports three reference configurations. The first uses both the internal bandgap reference and reference buffer. The second externally overdrives the internal reference but retains the internal buffer, which isolates the external reference from

ADC conversion transients. This configuration is ideal for sharing a single precision external reference across multiple ADCs. The third disables the internal buffer and overdrives the REFBUF pin externally.

Internal Reference with Internal Buffer

The LTC2345-16 has an on-chip, low noise, low drift

(20ppm/°C maximum), temperature compensated bandgap reference that is factory trimmed to 2.048V. The reference output connects through a 20kΩ resistor to

26

5V

UNIPOLAR

IN+

6V

+

AMPLIFIER

–2V

OPTIONAL

LOWPASS FILTER

R

FILT

0V

C

FILT

IN0

+

IN0

LTC2345-16

IN–

REFBUF

47µF

REFIN

0.1µF

ONLY CHANNEL 0 SHOWN FOR CLARITY

234516 F10

Figure 10. Buffering Single-Ended Input Signals. See Table 2 For Recommended

Amplifier and Filter Combinations

For more information www.linear.com/LTC2345-16

234516f

LTC2345-16

applicaTions inForMaTion

the REFIN pin, which serves as the input to the on-chip reference buffer, as shown in Figure 11a. When employing the internal bandgap reference, the REFIN pin should be bypassed to GND (Pin 20) close to the pin with a 0.1μF ceramic capacitor to filter wideband noise. The reference buffer amplifies V

REFIN

to create the converter master

= 2 •  V

REFIN reference voltage V

REFBUF

on the REFBUF pin, nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 20) close to the pin with at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or

X5R, 10V, 0805 size) to compensate the reference buffer, absorb transient conversion currents, and minimize noise.

0.1µF

47µF

LTC2345-16

REFIN

REFBUF

REFERENCE

BUFFER

6.5k

GND

20k

6.5k

BANDGAP

REFERENCE

234516 F11a

External Reference with Internal Buffer

If more accuracy and/or lower drift is desired, REFIN can be easily overdriven by an external reference since 20kΩ of resistance separates the internal bandgap reference output from the REFIN pin, as shown in Figure 11b. The valid range of external reference voltage overdrive on the

REFIN pin is 1.25V to 2.2V, resulting in converter mas-

REFBUF

between 2.5V and 4.4V, ter reference voltages V respectively. Linear Technology offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power, and high accuracy, the LTC6655-2.048 is well suited for use with the

LTC2345-16 when overdriving the internal reference. The

LTC6655-2.048 offers 0.025% (maximum) initial accuracy and 2ppm/°C (maximum) temperature coefficient for high precision applications. The LTC6655-2.048 is fully specified over the H-grade temperature range, complementing the extended temperature range of the LTC2345-16 up to

125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF ceramic capacitor close to the REFIN pin is recommended.

External Reference with Disabled Internal Buffer

The internal reference buffer supports V

REFBUF

= 4.4V maximum. By grounding REFIN, the internal buffer may be disabled allowing REFBUF to be overdriven with an external reference voltage between 2.5V and 5V, as shown

Figure 11a. Internal Reference with Internal Buffer Configuration

LTC6655-2.048

2.7µF

47µF

LTC2345-16

REFIN

REFBUF

20k

BANDGAP

REFERENCE

REFERENCE

BUFFER

6.5k

GND

6.5k

234516 F11b

Figure 11b. External Reference with Internal Buffer Configuration

For more information www.linear.com/LTC2345-16

234516f

27

LTC2345-16

applicaTions inForMaTion

LTC6655-5 47µF

LTC2345-16

REFIN

REFBUF

REFERENCE

BUFFER

6.5k

GND

20k

6.5k

BANDGAP

REFERENCE

234516 F11c

Figure 11c. External Reference with Disabled Internal

Buffer Configuration

in Figure 11c. Maximum input signal swing and SNR are achieved by overdriving REFBUF using an external 5V reference. The buffer feedback resistors load the REFBUF pin with 13kΩ even when the reference buffer is disabled.

The LTC6655-5 offers the same small size, accuracy, drift, and extended temperature range as the LTC6655-2.048, and achieves a typical SNR of 92dB when paired with the

LTC2345-16. Bypass the LTC6655-5 to GND (Pin 20) close to the REFBUF pin with at least a 47μF ceramic capacitor

(X7R, 10V, 1210 size or X5R, 10V, 0805 size) to absorb transient conversion currents and minimize noise.

The LTC2345-16 converter draws a charge (Q

CONV

) from the REFBUF pin during each conversion cycle. On short time scales most of this charge is supplied by the external

REFBUF bypass capacitor, but on longer time scales all of the charge is supplied by either the reference buffer, or when the internal reference buffer is disabled, the external reference. This charge draw corresponds to a DC current equivalent of I

REFBUF

= Q

CONV

 •  f

SMPL

, which is proportional to sample rate. In applications where a burst of samples is taken after idling for long periods of time, as shown in

Figure 12, I

REFBUF

quickly transitions from approximately

0.4mA to 1.5mA (V

REFBUF

= 5V, f

SMPL

 = 200kHz). This current step triggers a transient response in the external reference that must be considered, since any deviation in

V

REFBUF

affects converter accuracy. If an external reference is used to overdrive REFBUF, the fast settling LTC6655 family of references is recommended.

Internal Reference Buffer Transient Response

For optimum performance in applications employing burst sampling, the external reference with internal reference buffer configuration should be used. The internal reference buffer incorporates a proprietary design that minimizes movements in V

REFBUF

when responding to a burst of

CNV

IDLE

PERIOD

IDLE

PERIOD

Figure 12. CNV Waveform Showing Burst Sampling

234516 F12

234516f

28

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

conversions following an idle period. Figure 13 compares the burst conversion response of the LTC2345-16 with an input near full scale for two reference configurations. The first configuration employs the internal reference buffer with REFIN externally overdriven by an LTC6655-2.048, while the second configuration disables the internal reference buffer and overdrives REFBUF with an external

LTC6655-4.096. In both cases REFBUF is bypassed to

GND with a 47µF ceramic capacitor.

2

1

4

3

6

5

±4.096V SOFTSPAN

IN

IN

+

= 4V

= 0V

EXTERNAL REFERENCE ON REFBUF

0

–1

–2

0

INTERNAL REFERENCE BUFFER

100 200 300

TIME (µs)

400 500

234516 F13

f

Figure 13. Burst Conversion Response of the LTC2345-16,

SMPL 

= 200ksps

DYNAMIC PERFORMANCE

Fast Fourier transform (FFT) techniques are used to test the ADC’s frequency response, distortion, and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2345-16 provides guaranteed tested limits for both AC distortion and noise measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies below half the sampling frequency, excluding DC. Figure 14 shows that the LTC2345-16 achieves a typical SINAD of 91.1dB in the ±4.096V range at a 200kHz sampling rate with a fully differential 2kHz input signal.

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

0

±4.096V RANGE

FULLY DIFFERENTIAL DRIVE (IN

= –IN )

SNR = 91.1dB

THD = –111dB

SINAD = 91.1dB

SFDR = 112dB

20 40 60

FREQUENCY (KHz)

80 100

234516 F14

Figure 14. 32k Point FFT f

SMPL

= 200ksps, f

IN

= 2kHz

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 14 shows that the LTC2345-16 achieves a typical SNR of 91.1dB in the ±4.096V range at a 200kHz sampling rate with a fully differential 2kHz input signal.

Total Harmonic Distortion (THD)

Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (f

THD is expressed as:

SMPL

/2).

THD = 20log

V

2

2

+ V

3

2

V

1

+ V

4

2

...V

N

2 where V

1

is the RMS amplitude of the fundamental frequency and V

2

through V

N

are the amplitudes of the second through Nth harmonics, respectively. Figure 14 shows

For more information www.linear.com/LTC2345-16

234516f

29

LTC2345-16

applicaTions inForMaTion

that the LTC2345-16 achieves a typical THD of –111dB

(N = 6) in the ±4.096V range at a 200kHz sampling rate with a fully differential 2kHz input signal.

POWER CONSIDERATIONS

The LTC2345-16 provides two power supply pins: the 5V core power supply (V

DD

) and the digital input/output (I/O) interface power supply (OV

Power Supply Sequencing

DD

). The flexible OV

DD

supply allows the LTC2345-16 to communicate with CMOS logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. When using LVDS I/O mode, the range of OV is 2.375V to 5.25V.

DD

The LTC2345-16 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2345-16 has an internal power-on-reset (POR) circuit which resets the converter on initial power-up and whenever V

DD

drops below 2V. Once the supply voltage re-enters the nominal supply voltage range, the POR reinitializes the ADC. No conversions should be initiated until at least 10ms after a POR event to ensure the initialization period has ended.

When employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the REFBUF bypass capacitor. Any conversion initiated before these times will produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2345-16 sampling and conversion is controlled by

CNV. A rising edge on CNV transitions all channels’ S/H circuits from track mode to hold mode, simultaneously sampling the input signals on all channels and initiating a conversion. Once a conversion has been started, it cannot be terminated early except by resetting the ADC, as discussed in the Reset Timing section. For optimum performance, drive CNV with a clean, low jitter signal and avoid transitions on data I/O lines leading up to the rising edge of CNV. Additionally, to minimize channel-to-channel crosstalk, avoid high slew rates on the analog inputs for

100ns before and after the rising edge of CNV. Converter status is indicated by the BUSY output, which transitions low-to-high at the start of each conversion and stays high until the conversion is complete. Once CNV is brought high to begin a conversion, it should be returned low between

40ns and 60ns later or after the falling edge of BUSY to minimize external disturbances during the internal conversion process. If CNV is returned low after the falling edge of BUSY, it should be held low for at least 420ns before bringing it high again, since the converter acquisition time (t

ACQ

) is set by the CNV low time (t

CNVL

) in this case.

Internal Conversion Clock

The LTC2345-16 has an internal clock that is trimmed to achieve a maximum conversion time of 555 • N – 35ns with N channels enabled. With a minimum acquisition time of 565ns when converting eight channels simultaneously, throughput performance of 200ksps is guaranteed without any external adjustments.

Power Down Mode

When PD is brought high, the LTC2345-16 is powered down and subsequent conversion requests are ignored. If this occurs during a conversion, the device powers down once the conversion completes. In this mode, the device draws only a small regulator standby current resulting in a typical power dissipation of 0.33mW. To exit power down mode, bring the PD pin low and wait at least 10ms before initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the REFBUF bypass capacitor. Any conversion initiated before these times will produce invalid results.

Reset Timing

A global reset of the LTC2345-16, equivalent to a poweron-reset event, may be executed without needing to cycle the supplies. This feature is useful when recovering from system-level events that require the state of the entire sys-

234516f

30

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

tem to be reset to a known synchronized value. To initiate a global reset, bring PD high twice without an intervening conversion, as shown in Figure 15. The reset event is triggered on the second rising edge of PD, and asynchronously ends based on an internal timer. Reset clears all serial data output registers and restores the internal SoftSpan configuration register default state of all channels in SoftSpan 7.

If reset is triggered during a conversion, the conversion is immediately halted. The normal power down behavior associated with PD going high is not affected by reset. Once

PD is brought low, wait at least 10ms before initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the

REFBUF bypass capacitor. Any conversion initiated before these times will produce invalid results.

Auto Nap Mode

The LTC2345-16 automatically enters nap mode after a conversion has finished and completely powers up once a new conversion is initiated on the rising edge of CNV. Auto nap mode causes the power dissipation of the LTC2345-

16 to decrease as the sampling frequency is reduced, as shown in Figure 16. This decrease in average power dissipation occurs because a portion of the LTC2345-16 circuitry is turned off during nap mode, and the fraction of the conversion cycle (t the sampling frequency (f

CYC

) spent napping increases as

SMPL

) is decreased.

10

8

6

4

2

0

0

18

16

14

12

I

VDD

I

OVDD

40 80 120 160

SAMPLING FREQUENCY (kHz)

200

234516 F16

Figure 16. Power Dissipation of the LTC2345-16

Decreases with Decreasing Sampling Frequency

DIGITAL INTERFACE

The LTC2345-16 features CMOS and LVDS serial interfaces, selectable using the LVDS/ CMOS pin. The flexible OV

DD supply allows the LTC2345-16 to communicate with any

CMOS logic operating between 1.8V and 5V, including

2.5V and 3.3V systems, while the LVDS interface supports low noise digital designs. In CMOS mode, applications may employ between one and eight lanes of serial data output, allowing the user to optimize bus width and data

PD

CNV

BUSY

RESET t

PDH t

WAKE t

CNVH t

PDL t

CONV

SECOND RISING EDGE OF

PD TRIGGERS RESET

RESET TIME

SET INTERNALLY

Figure 15. Reset Timing for the LTC2345-16

234516 F15

For more information www.linear.com/LTC2345-16

234516f

31

LTC2345-16

applicaTions inForMaTion

CS = PD = 0

SAMPLE N t

CNVH

CNV

BUSY t

BUSYLH t

CONV t

SCKI t

CYC t

CNVL t

ACQ

RECOMMENDED DATA TRANSACTION WINDOW t

SCKIH

SCKI

SDI DON’T CARE t

DSDOBUSYL t

SSDISCKI

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 t

SCKIL t

HSDISCKI

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 t

HSDOSCKI

SOFTSPAN CONFIGURATION WORD FOR CONVERSION N + 1

SAMPLE N + 1 t

QUIET t

SKEW

SCKO

SDO0

SDO7

DON’T CARE

DON’T CARE

D15

D15 t

DSDOSCKI

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0

CONVERSION RESULT

C2 C1 C0 SS2 SS1 SS0 D15

CHANNEL ID SOFTSPAN CONVERSION RESULT

CHANNEL 0

24-BIT PACKET

CONVERSION N

CHANNEL 1

24-BIT PACKET

CONVERSION N

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0

CONVERSION RESULT

C2 C1 C0 SS2 SS1 SS0 D15

CHANNEL ID SOFTSPAN CONVERSION RESULT

CHANNEL 7

24-BIT PACKET

CONVERSION N

CHANNEL 0

24-BIT PACKET

CONVERSION N

234516 TD01

Figure 17. Serial CMOS I/O Mode

throughput. Together, these I/O interface options enable the LTC2345-16 to communicate equally well with legacy microcontrollers and modern FPGAs.

Serial CMOS I/O Mode

As shown in Figure 17, in CMOS I/O mode the serial data bus consists of a serial clock input, SCKI, serial data input, SDI, serial clock output, SCKO, and eight lanes of serial data output, SDO0 to SDO7. Communication with the LTC2345-16 across this bus occurs during predefined data transaction windows. Within a window, the device accepts 24-bit SoftSpan configuration words for the next conversion on SDI and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on SDO0 to SDO7. New data transaction windows open 10ms after powering up or resetting the LTC2345-16, and at the end of each conversion on the falling edge of BUSY. In the recommended use case, the data transaction should be completed with a minimum t

QUIET

time of 20ns prior to the start of the next conversion, as shown in Figure 17. New SoftSpan configuration words are only accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with no additional analog input settling time required before starting the next conversion.

It is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended.

Just prior to the falling edge of BUSY and the opening of a new data transaction window, SCKO is forced low and

SDO0 to SDO7 are updated with the latest conversion results from analog input channels 0 to 7, respectively.

Rising edges on SCKI serially clock conversion results and analog input channel configuration information out on SDO0 to SDO7 and trigger transitions on SCKO that are skew-matched to the data on SDO0 to SDO7. The resulting

234516f

32

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

SCKO frequency is half that of SCKI. SCKI rising edges also latch SoftSpan configuration words provided on SDI, which are used to program the internal 24-bit SoftSpan configuration register. See the section Programming the

SoftSpan Configuration Register in CMOS I/O Mode for further details. SCKI is allowed to idle either high or low in CMOS I/O mode. As shown in Figure 18, the CMOS bus is enabled when CS is low and is disabled and Hi-Z when CS is high, allowing the bus to be shared across multiple devices.

The data on SDO0 to SDO7 are grouped into 24-bit packets consisting of a 16-bit conversion result plus

2-bit trailing zero pad, 3-bit analog channel ID, and 3-bit

SoftSpan code, all presented MSB first. As suggested in

Figures 17 and 18, each SDO lane outputs these packets for all analog input channels in a sequential, circular manner. For example, the first 24-bit packet output on

SDO0 corresponds to analog input channel 0, followed by the packets for channels 1 through 7. The data output on SDO0 then wraps back to channel 0, and this pattern repeats indefinitely. Other SDO lanes follow a similar circular pattern, except the first packet presented on each lane corresponds to its associated analog input channel.

When interfacing the LTC2345-16 with a standard SPI bus, capture output data at the receiver on rising edges of

SCKI. SCKO is not used in this case. Multiple SDO lanes

PD = 0

BUSY are also usually not useful in this case. In other applications, such as interfacing the LTC2345-16 with an FPGA or CPLD, rising and falling edges of SCKO may be used to capture serial output data on SDO0 to SDO7 in double data rate (DDR) fashion. Capturing data using SCKO adds robustness to delay variations over temperature and supply.

Full Eight Lane Serial CMOS Output Data Capture

As shown in Table 3, full 200ksps per channel throughput can be achieved with a 45MHz SCKI frequency by capturing the first packet (24 SCKI cycles total) from all eight serial data output lanes SDO0 to SDO7. This configuration also allows conversion results from all channels to be captured using as few as 16 SCKI cycles if the 3-bit analog channel

ID and 3-bit SoftSpan code are not needed and the device

SoftSpan configuration is not being changed. Multi-lane data capture is usually best suited for use with FPGA or CPLD capture hardware, but may be useful in other application-specific cases.

Fewer Than Eight Lane Serial CMOS Output Data Capture

Applications that cannot accommodate the full eight lanes of serial data capture may employ fewer lanes without reconfiguring the LTC2345-16. For example, capturing the first two packets (48 SCKI cycles total) from SDO0,

SDO2, SDO4, and SDO6 provides data for analog input

CS

SCKI DON’T CARE

SDI DON’T CARE

SCKO

Hi-Z

SDO0

Hi-Z

NEW SoftSpan CONFIGURATION WORD

(OVERWRITES INTERNAL CONFIG REGISTER)

CHANNEL 0 PACKET t

EN

SDO7

Hi-Z

CHANNEL 7 PACKET

CHANNEL 1 PACKET

TWO ALL-ZERO WORDS AND ONE PARTIAL WORD

(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)

CHANNEL 2 PACKET

CHANNEL 3 PACKET

(PARTIAL)

CHANNEL 0 PACKET CHANNEL 1 PACKET

CHANNEL 2 PACKET

(PARTIAL)

Figure 18. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS

DON’T CARE

DON’T CARE

Hi-Z

Hi-Z t

DIS

Hi-Z

234516 F18

For more information www.linear.com/LTC2345-16

234516f

33

LTC2345-16

applicaTions inForMaTion

channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respectively, using four output lanes. Similarly, capturing the first four packets (96 SCKI cycles total) from SDO0 and SDO4 provides data for analog input channels 0 to 3 and 4 to

7, respectively, using two output lanes. If only one lane can be accommodated, capturing the first eight packets

(192 SCKI cycles total) from SDO0 provides data for all analog input channels. As shown in Table 3, full 200ksps per channel throughput can be achieved with a 90MHz

SCKI frequency in the four lane case, but the maximum

CMOS SCKI frequency of 100MHz limits the throughput to less than 200ksps per channel in the two lane and one lane cases. Finally, note that in choosing the number of lanes and which lanes to use for data capture, the user is not restricted to the specific cases mentioned above. Other choices may be more optimal in particular applications.

Programming the SoftSpan Configuration Register in

CMOS I/O Mode

The internal 24-bit SoftSpan configuration register controls the SoftSpan range for all analog input channels of the LTC2345-16. The default state of this register after power-up or resetting the device is all ones, configuring each channel to convert in SoftSpan 7, the ± V

REFBUF range

(see Table 1a). The state of this register may be modified by providing a new 24-bit SoftSpan configuration word on

SDI during the data transaction window shown in Figure

17. New SoftSpan configuration words are only accepted within this recommended data transaction window, but

SoftSpan changes take effect immediately with no additional analog input settling time required before starting the next conversion. Setting a channel’s SoftSpan code to

SS[2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in t

CONV

on the next conversion. Similarly, enabling a previously disabled channel requires no additional analog input settling time before starting the next conversion. The mapping between the serial SoftSpan configuration word, the internal SoftSpan configuration register, and each channel’s 3-bit SoftSpan code is illustrated in Figure 19.

If fewer than 24 SCKI rising edges are provided during a data transaction window, the partial word received on SDI will be ignored and the SoftSpan configuration register will not be updated. If exactly 24 SCKI rising edges are provided, the SoftSpan configuration register will be updated to match the received SoftSpan configuration word, S[23:0].

The one exception to this behavior occurs when S[23:0] is all zeros. In this case, the SoftSpan configuration register will not be updated, allowing applications to retain the current SoftSpan configuration state by idling SDI low. If more than 24 SCKI rising edges are provided during a data transaction window, each complete 24-bit word received on SDI will be interpreted as a new SoftSpan configuration word and applied to the SoftSpan configuration register as described above. Any partial words are ignored.

Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 17 and 18.

After the opening of a new data transaction window at the falling edge of BUSY, the user supplies a 24-bit SoftSpan configuration word on SDI during the first 24 SCKI cycles.

This new word overwrites the internal configuration register

Table 3. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Eight Channels

Enabled. Shaded Entries Denote Throughputs That Are Not Achievable In a Given Configuration. Calculated Using f

SCKI Cycles)/(t

ACQ,MIN

– t

QUIET

)

SCKI

= (Number of

I/O MODE

NUMBER OF SDO

LANES

8

8

NUMBER OF SCKI

CYCLES

16

24

200ksps/CHANNEL

(t

ACQ

REQUIRED f

SCKI

= 565ns)

(MHz) TO ACHIEVE THROUGHPUT OF

100ksps/CHANNEL

(t

ACQ

= 5565ns)

50ksps/CHANNEL

(t

ACQ

= 15565ns)

30

45

3

5

2

2

CMOS

LVDS

4

2

1

1

48

96

192

96

90

Not Achievable

Not Achievable

180 (360Mbps)

9

18

35

18 (36Mbps)

4

7

13

7 (14Mbps)

234516f

34

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

SCKI

SDI DON’T CARE

CMOS I/O MODE

t

SCKI t

SCKIH t

SSDISCKI

S23

1 2 3 4 5 6 t

7 8

SCKIL t

HSDISCKI

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

SoftSpan CONFIGURATION WORD

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

LVDS I/O MODE

t

SCKI t

SCKIH

S23

1 2 3 4 t

SCKIL

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 t

SSDISCKI t

SSDISCKI

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 t

HSDISCKI

S4 S3 S2 S1 S0 t

HSDISCKI

SoftSpan CONFIGURATION WORD

23 22 21

CHANNEL 7 SoftSpan

CODE SS[2:0]

20 19 18

CHANNEL 6 SoftSpan

CODE SS[2:0]

INTERNAL 24-BIT SoftSpan CONFIGURATION REGISTER

(SAME FOR CMOS AND LVDS)

17 16 15

CHANNEL 5 SoftSpan

CODE SS[2:0]

14 13 12

CHANNEL 4 SoftSpan

CODE SS[2:0]

11 10 9

CHANNEL 3 SoftSpan

CODE SS[2:0]

8 7 6

CHANNEL 2 SoftSpan

CODE SS[2:0]

5 4 3

CHANNEL 1 SoftSpan

CODE SS[2:0]

2 1 0

CHANNEL 0 SoftSpan

CODE SS[2:0]

234516 F19

Figure 19. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan

Configuration Register, and SoftSpan Code for Each Analog Input Channel

contents following the 24th SCKI rising edge. The user then holds SDI low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional SCKI cycles applied. SoftSpan settings may be retained across multiple conversions by holding SDI low for the entire data transaction window, regardless of the number of SCKI cycles applied.

Serial LVDS I/O Mode

In LVDS I/O mode, information is transmitted using positive and negative signal pairs (LVDS differentially encoded as (LVDS

+

+

/LVDS

− LVDS

) with bits

). These signals are typically routed using differential transmission lines with 100Ω characteristic impedance. Logical 1’s and 0’s are nominally represented by differential +350mV and

−350mV, respectively. For clarity, all LVDS timing diagrams and interface discussions adopt the logical rather than physical convention.

As shown in Figure 20, in LVDS I/O mode the serial data bus consists of a serial clock differential input, SCKI, serial data differential input, SDI, serial clock differential output,

SCKO, and serial data differential output, SDO. Communication with the LTC2345-16 across this bus occurs during predefined data transaction windows. Within a window, the device accepts 24-bit SoftSpan configuration words for the next conversion on SDI and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on SDO. New data transaction windows open 10ms after powering up or resetting the LTC2345-16, and at the end of each conversion on the falling edge of BUSY. In the recommended use case, the data transaction should be completed with a minimum t

QUIET

time of 20ns prior to the start of the next conversion, as shown in Figure 20. New SoftSpan configuration words are only accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with no additional analog input

For more information www.linear.com/LTC2345-16

234516f

35

LTC2345-16

applicaTions inForMaTion

CS = PD = 0

SAMPLE N t

CNVH

CNV

(CMOS)

BUSY

(CMOS) t

CONV t

BUSYLH t

CYC t

CNVL

SAMPLE N + 1

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE t

DSDOBUSYL

SCKO

(LVDS)

SDO

(LVDS)

DON’T CARE t

ACQ t

SCKI

RECOMMENDED DATA TRANSACTION WINDOW t

SCKIH t

QUIET

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t

SCKIL t

SSDISCKI t

SSDISCKI t

HSDISCKI

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

24 25 26 t

HSDISCKI

185 186 187 188 189 190 191 192

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1 t

HSDOSCKI t

SKEW

D15 t

DSDOSCKI

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0

CONVERSION RESULT

CHANNEL 0

24-BIT PACKET

CONVERSION N

C2 C1 C0 SS2 SS1 SS0 D15 D14 D13 0

CHANNEL ID SoftSpan

CHANNEL 1

24-BIT PACKET

CONVERSION N

C2 C1 C0

CHANNEL ID SoftSpan

CHANNEL 7

SS2 SS1 SS0 D15

24-BIT PACKET

CONVERSION N

CONVERSION

RESULT

CHANNEL 0

24-BIT PACKET

CONVERSION N

234516 F20

Figure 20. Serial LVDS I/O Mode

settling time required before starting the next conversion.

It is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended.

Just prior to the falling edge of BUSY and the opening of a new data transaction window, SDO is updated with the latest conversion results from analog input channel 0. Both rising and falling edges on SCKI serially clock conversion results and analog input channel configuration information out on SDO. SCKI is also echoed on SCKO, skew-matched to the data on SDO. Whenever possible, it is recommended that rising and falling edges of SCKO be used to capture

DDR serial output data on SDO, as this will yield the best robustness to delay variations over supply and temperature. SCKI rising and falling edges also latch SoftSpan configuration words provided on SDI, which are used to program the internal 24-bit SoftSpan configuration register.

See the section Programming the SoftSpan Configuration

Register in LVDS I/O Mode for further details. As shown in

Figure 21, the LVDS bus is enabled when CS is low and is disabled and Hi-Z when CS is high, allowing the bus to be shared across multiple devices. Due to the high speeds involved in LVDS signaling, LVDS bus sharing must be carefully considered. Transmission line limitations imposed by the shared bus may limit the maximum achievable bus clock speed. LVDS inputs are internally terminated with a 100Ω differential resistor when CS  = 0, while outputs must be differentially terminated with a 100Ω resistor at the receiver (FPGA). SCKI must idle in the low state in

LVDS I/O mode, including when transitioning CS .

The data on SDO are grouped into 24-bit packets consisting of a 16-bit conversion result plus 2-bit trailing zero pad, 3-bit analog channel ID, and 3-bit SoftSpan code, all presented MSB first. As suggested in Figures 20 and 21,

SDO outputs these packets for all analog input channels in a sequential, circular manner. For example, the first

24-bit packet output on SDO corresponds to analog input channel 0, followed by the packets for channels 1 through

7. The data output on SDO then wraps back to channel 0, and this pattern repeats indefinitely.

234516f

36

For more information www.linear.com/LTC2345-16

LTC2345-16

applicaTions inForMaTion

Serial LVDS Output Data Capture

As shown in Table 3, full 200ksps per channel throughput can be achieved with a 180MHz SCKI frequency by capturing eight packets (96 SCKI cycles total) of DDR data from

SDO. The LTC2345-16 supports LVDS SCKI frequencies up to 250MHz.

Programming the SoftSpan Configuration Register in

LVDS I/O Mode

The internal 24-bit SoftSpan configuration register controls the SoftSpan range for all analog input channels of the LTC2345-16. The default state of this register after power-up or resetting the device is all ones, configuring each channel to convert in SoftSpan 7, the ± V

REFBUF

range

(see Table 1a). The state of this register may be modified by providing a new 24-bit SoftSpan configuration word on

SDI during the data transaction window shown in Figure

20. New SoftSpan configuration words are only accepted within this recommended data transaction window, but

SoftSpan changes take effect immediately with no additional analog input settling time required before starting the next conversion. Setting a channel’s SoftSpan code to

SS[2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in t

CONV

on the next conversion. Similarly, enabling a previously disabled channel requires no additional analog input settling time before starting the next conversion. The mapping between the serial SoftSpan configuration word, the internal SoftSpan configuration register, and each channel’s 3-bit SoftSpan code is illustrated in Figure 19.

If fewer than 24 SCKI edges (rising plus falling) are provided during a data transaction window, the partial word received on SDI will be ignored and the SoftSpan configuration register will not be updated. If exactly 24

SCKI edges are provided, the SoftSpan configuration register will be updated to match the received SoftSpan configuration word, S[23:0]. The one exception to this behavior occurs when S[23:0] is all zeros. In this case, the SoftSpan configuration register will not be updated, allowing applications to retain the current SoftSpan configuration state by idling SDI low. If more than 24 SCKI edges are provided during a data transaction window, each complete 24-bit word received on SDI will be interpreted as a new SoftSpan configuration word and applied to the

SoftSpan configuration register as described above. Any partial words are ignored.

Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 20 and 21.

After the opening of a new data transaction window at the falling edge of BUSY, the user supplies a 24-bit DDR

SoftSpan configuration word on SDI during the first 12

SCKI cycles. This new word overwrites the internal configuration register contents following the 12 th

SCKI falling edge. The user then holds SDI low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional SCKI cycles applied. SoftSpan settings may be retained across multiple conversions by holding SDI low for the entire data transaction window, regardless of the number of

SCKI cycles applied.

PD = 0

BUSY

(CMOS)

CS

(CMOS)

SCKI

(LVDS)

DON’T CARE

SDI

(LVDS)

DON’T CARE

SCKO

(LVDS)

Hi-Z

SDO

(LVDS)

Hi-Z t

EN

NEW SoftSpan CONFIGURATION WORD

(OVERWRITES INTERNAL CONFIG REGISTER)

TWO ALL-ZERO WORDS AND ONE PARTIAL WORD

(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)

CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET

CHANNEL 3 PACKET

(PARTIAL)

Figure 21. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS

t

DIS

DON’T CARE

DON’T CARE

Hi-Z

Hi-Z

234516 F21

For more information www.linear.com/LTC2345-16

234516f

37

LTC2345-16

boarD layouT

To obtain the best performance from the LTC2345-16, a four-layer printed circuit board (PCB) is recommended.

Layout for the PCB should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC.

Also minimize the length of the REFBUF to GND (Pin 20) bypass capacitor return loop, and avoid routing CNV near signals which could potentially disturb its rising edge.

Supply bypass capacitors should be placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. A single solid ground plane is recommended for this purpose. When possible, screen the analog input traces using ground.

Reference Design

For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer to DC2326A , the evaluation kit for the LTC2345-16.

38

For more information www.linear.com/LTC2345-16

234516f

package DescripTion

Please refer to http://www.linear.com/product/LTC2345-16#packaging for the most recent package drawings.

LTC2345-16

UK Package

48-Lead Plastic QFN (7mm

×

7mm)

(Reference LTC DWG # 05-08-1704 Rev C)

0.70 ±0.05

5.15 ±0.05

5.50 REF

(4 SIDES) 6.10 ±0.05 7.50 ±0.05

5.15 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

7.00 ±0.10

(4 SIDES)

PIN 1 TOP MARK

(SEE NOTE 6)

0.75 ±0.05

R = 0.10

TYP

R = 0.115

TYP

PIN 1

CHAMFER

C = 0.35

47 48

0.40 ±0.10

1

2

5.15 ±0.10

5.50 REF

(4-SIDES)

5.15 ±0.10

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

(UK48) QFN 0406 REV C

0.25 ±0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

For more information www.linear.com/LTC2345-16

234516f

39

LTC2345-16

Typical applicaTion

Sense Current from Rail with Amplification

5V

I

LOAD

LOAD

274Ω

2.49k

5V

+

LTC6252

IN0

IN0

+

V

LTC2345-16

DD

ONLY CHANNEL 0 SHOWN FOR CLARITY

REFBUF

47µF

REFIN

0.1µF

234516 TA02

relaTeD parTs

PART NUMBER

ADCs

LTC2345-18

DESCRIPTION

LTC2348-18/LTC2348-16

LTC2378-20 / LTC2377-20 /

LTC2376-20

LTC2338-18 / LTC2337-18 /

LTC2336-18

LTC2328-18 / LTC2327-18 /

LTC2326-18

LTC2373-18 / LTC2372-18

LTC2379-18 / LTC2378-18 /

LTC2377-18 / LTC2376-18

LTC2380-16 / LTC2378-16 /

LTC2377-16 / LTC2376-16

LTC2389-18 / LTC2389-16

LTC1859 / LTC1858 /

LTC1857

LTC1606 / LTC1605

DACs

LTC2756 / LTC2757

COMMENTS

18-Bit, 200ksps, 8-Channel Simultaneous

Sampling, ±5LSB INL, Serial ADC

18-/16-Bit, 200ksps, 8-Channel Simultaneous

Sampling, ±3/±1LSB INL, Serial ADC

20-Bit, 1Msps/500ksps/250ksps,

±0.5ppm INL Serial, Low Power ADC

18-Bit, 1Msps/500ksps/250ksps, Serial,

Low Power ADC

18-Bit, 1Msps/500ksps/250ksps, Serial,

Low Power ADC

18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC

5V Supply, SoftSpan Inputs with Wide Common Mode Range, 91.8dB SNR,

Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package

±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,

Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package

2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and

4mm × 3mm DFN-16 Packages

5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package

18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial,

Low Power ADC

16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial,

Low Power ADC

5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,

MSOP-16 Package

5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,

DGC, 5mm × 5mm QFN-32 Package

2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

18-Bit/16-Bit, 2.5Msps, Parallel/Serial ADC 5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or

Serial I/O 7mm × 7mm LQFP-48 and QFN-48 Packages

16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,

SSOP-28 Package

16-Bit, 250ksps/100ksps, Parallel ADC ±10V Input, 5V Supply, 75mW/55mW, SSOP-28 and SO-28 Packages

18-Bit, Serial/Parallel I

OUT

SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges,

SSOP-28/7mm × 7mm LQFP-48 Package

16-Channel 16-/12-Bit ±10V V

OUT

SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package LTC2668

References

LTC6655

LTC6652

Amplifiers

LT6236/LT6237/LT6238

Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

215MHz, 3.5mA/Amplifier, 1.1nV/√ Hz

LT6233/LT6234/LT6235

LTC6252/LTC6253/

LTC6254

Single/Dual/Quad Operational Amplifier with

Low Wideband Noise

Single/Dual/Quad Low Noise Rail-to-Rail Output

Op Amps

720MHz, 3.5mA Power Efficient Rail-to-Rail I/O

Op Amp

60MHz,1.2mA,1.2nV/√ Hz ,15V/μs,0.5mV

720MHz GBW, Unity Gain Stable, Low Noise

40

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX : (408) 434-0507

For more information www.linear.com/LTC2345-16

234516f

LT 0216 • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2016

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals