PWM Controller and Transformer Driver with Quad-Channel Isolators ADuM3470 ADuM3471

PWM Controller and Transformer Driver with Quad-Channel Isolators ADuM3470 ADuM3471
PWM Controller and Transformer
Driver with Quad-Channel Isolators
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Isolated PWM controller
Integrated transformer driver
Regulated adjustable output: 3.3 V to 24 V
2 W output power
70% efficiency at guaranteed load of 400 mA at 5.0 V output
Quad dc-to-25 Mbps (NRZ) signal isolation channels
20-lead SSOP package
High temperature operation: 105°C maximum
High common-mode transient immunity: >25 kV/µs
200 kHz to 1 MHz adjustable oscillator frequency
Soft start function at power-up
Pulse-by-pulse overcurrent protection
Thermal shutdown
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
Qualified for automotive applications
T1
X1
VDDA
VISO
RECT
VDD1
DRIVER
VREG
X2
ADuM3470/ADuM3471/
ADuM3472/ADuM3473/
ADuM3474
PRIMARY
CONVERTER
REG
5V
SECONDARY
CONTROLLER
VIB/VOB
CH B
PRIMARY
DATA
I/O
4CH
VIC/VOC
CH C
FB
OC
CH A
VIA/VOA
VDD2
FB
SECONDARY
DATA
I/O
4CH
VIA/VOA
VIB/VOB
VIC/VOC
CH D
VID/VOD
VID/VOD
GND2
GND1
09369-001
Data Sheet
Figure 1. Functional Block Diagram
ADuM3470
ADuM3471
APPLICATIONS
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Power supply start-up bias and gate drives
Isolated sensor interfaces
Process controls
Automotive
ADuM3472
GENERAL DESCRIPTION
ADuM3473
ADuM3474
09369-003
The ADuM3470/ADuM3471/ADuM3472/ADuM3473/
ADuM3474 devices1 are quad-channel digital isolators with an
integrated PWM controller and transformer driver for an isolated
dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler®
technology, the dc-to-dc converter provides up to 2 W of regulated,
isolated power at 3.3 V to 24 V from a 5.0 V input supply or from
a 3.3 V supply. This eliminates the need for a separate, isolated
dc-to-dc converter in 2 W isolated designs. The iCoupler chip scale
transformer technology is used to isolate the logic signals, and the
integrated transformer driver with isolated secondary side control
provides higher efficiency for the isolated dc-to-dc converter. The
result is a small form factor, total isolation solution. The ADuM347x
isolators provide four independent isolation channels in a variety of
channel configurations and data rates (see the Ordering Guide).
Figure 2. Block Diagrams of I/O Channels
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
Rev. B
Document Feedback
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Technical Support
www.analog.com
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 19
Applications ....................................................................................... 1
Terminology .................................................................................... 24
General Description ......................................................................... 1
Applications Information .............................................................. 25
Functional Block Diagrams ............................................................. 1
Application Schematics ............................................................. 25
Revision History ............................................................................... 2
Transformer Design ................................................................... 26
Specifications..................................................................................... 3
Transformer Turns Ratio ........................................................... 26
Electrical Characteristics—5 V Primary Input Supply/
5 V Secondary Isolated Supply ................................................... 3
Transformer ET Constant ......................................................... 27
Electrical Characteristics—3.3 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 5
Transformer Isolation Voltage .................................................. 27
Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 7
Transient Response .................................................................... 27
Transformer Primary Inductance and Resistance ................. 27
Switching Frequency .................................................................. 27
Electrical Characteristics—5 V Primary Input Supply/
15 V Secondary Isolated Supply ................................................. 9
Component Selection ................................................................ 27
Package Characteristics ............................................................. 11
Thermal Analysis ....................................................................... 28
Regulatory Approvals................................................................. 11
Propagation Delay-Related Parameters ................................... 28
Insulation and Safety-Related Specifications .......................... 11
DC Correctness and Magnetic Field Immunity ..................... 29
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Insulation Characteristics.......................................................... 12
Power Consumption .................................................................. 30
Recommended Operating Conditions .................................... 12
Insulation Lifetime ..................................................................... 31
Absolute Maximum Ratings.......................................................... 13
Outline Dimensions ....................................................................... 32
ESD Caution ................................................................................ 13
Ordering Guide .......................................................................... 33
Pin Configurations and Function Descriptions ......................... 14
Automotive Products ................................................................. 33
Printed Circuit Board (PCB) Layout ....................................... 28
Power Considerations ................................................................ 30
REVISION HISTORY
5/14—Rev. A to Rev. B
Change to Table 4 ............................................................................. 9
7/13—Rev. 0 to Rev. A
Changed VDD1 Pin to NC Pin ....................................... Throughout
Changes to Features Section, Applications Section,
General Description Section, and Figure 1 ................................... 1
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Table 4 ............................................................................ 9
Changes to Regulatory Approvals Section .................................. 11
Changes to Figure 3 and Table 9 ................................................... 12
Changes to Figure 4 and Table 12 ................................................. 14
Changes to Figure 5 and Table 13 ................................................. 15
Changes to Figure 6 and Table 14................................................. 16
Changes to Figure 7 and Table 15................................................. 17
Changes to Figure 8, Table 16, and Table 17 ............................... 18
Change to Figure 9 ......................................................................... 19
Changes to Terminology Section ................................................. 24
Changes to Applications Information Section, Application
Schematics Section, Figure 38, Figure 39, and Figure 40 .......... 25
Changes to Transformer Turns Ratio Section ............................ 26
Changes to Transformer ET Constant Section,
Transient Response Section, and Table 19 .................................. 27
Changes to Figure 41...................................................................... 28
Changes to Power Consumption Section and Figure 45........... 30
Changes to Insulation Lifetime Section and Figure 48 ............. 31
Changes to Ordering Guide .......................................................... 33
Added Automotive Products Section .......................................... 33
10/10—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ VDD1 = VDDA ≤ 5.5 V; VDD2 = VREG = VISO = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 5.0 V.
Table 1.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage
Feedback Voltage Setpoint
Line Regulation
Load Regulation
Output Ripple
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VFB
VISO (LINE)
VISO (LOAD)
VISO (RIP)
4.5
1.125
5.0
1.25
1
1
50
5.5
1.375
10
2
V
V
mV/V
%
mV p-p
IISO = 0 mA, VISO = VFB × (R1 + R2)/R2
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 50 mA to 200 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
ROC = 50 kΩ
ROC = 270 kΩ
VOC = VDD2 (open loop)
Output Noise
VISO (N)
100
mV p-p
Switching Frequency
fSW
RON
1000
200
318
0.5
kHz
kHz
kHz
Ω
VUV+
VUV−
VUVH
2.8
2.6
0.2
192
Switch On Resistance
Undervoltage Lockout, VDD1, VDD2
Supplies
Positive Going Threshold
Negative Going Threshold
Hysteresis
DC to 2 Mbps Data Rate 1
Maximum Output Supply Current 2
Efficiency at Maximum Output
Supply Current 3
iCOUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
Available VISO Supply Current 4
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
IDD1 Supply Current, Full VISO Load
IISO (MAX)
515
V
V
V
400
mA
%
70
IDD1 (Q)
IISO = 0 mA, f ≤ 1 MHz
14
15
16
17
18
30
30
30
30
30
mA
mA
mA
mA
mA
IDD1 (D)
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
44
46
48
50
52
mA
mA
mA
mA
mA
390
388
386
384
382
550
mA
mA
mA
mA
mA
mA
IISO (LOAD)
IDD1 (MAX)
f ≤ 1 MHz
VISO = 5.0 V
IISO = IISO (MAX)
CL = 15 pF, f = 12.5 MHz
Rev. B | Page 3 of 36
CL = 0 pF, f = 0 MHz, VDD1 = 5 V,
IISO = 400 mA
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter
I/O Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
AC SPECIFICATIONS
A Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Propagation Delay Skew
Channel-to-Channel Matching
C Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
At Logic High Output
At Logic Low Output
Refresh Rate
Symbol
IIA, IIB, IIC, IID
VIH
VIL
VOAH, VOBH,
VOCH, VODH
Min
−20
2.0
Typ
+0.01
VDD1 − 0.3,
VISO − 0.3
VDD1 − 0.5,
VISO − 0.5
Max
+20
5.0
Unit
µA
V
V
V
IOx = −20 µA, VIx = VIxH
4.8
V
IOx = −4 mA, VIx = VIxH
0.8
VOAL, VOBL,
VOCL, VODL
Data Sheet
Test Conditions/Comments
0.0
0.1
V
IOx = 20 µA, VIx = VIxL
0.0
0.4
V
IOx = 4 mA, VIx = VIxL
1000
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
PW
1
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
55
100
40
50
50
CL = 15 pF, CMOS signal levels
PW
tPHL, tPLH
PWD
40
25
30
45
60
8
5
tPSK
15
tPSKCD
tPSKOD
tR/tF
8
15
|CMH|
|CML|
fr
25
25
ns
Mbps
ns
ns
ps/°C
ns
2.5
ns
ns
ns
35
35
1.0
kV/µs
kV/µs
Mbps
CL = 15 pF, CMOS signal levels
VCM = 1000 V, transient
magnitude = 800 V
VIx = VDD1 or VISO
VIx = 0 V
The contributions of supply current values for all four channels are combined at identical data rates.
The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3
The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4
This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
1
2
Rev. B | Page 4 of 36
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V ≤ VDD1 = VDDA ≤ 3.6 V; VDD2 = VREG = VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 3.3 V, VDD2 = VREG = VISO = 3.3 V.
Table 2.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage
Feedback Voltage Setpoint
Line Regulation
Load Regulation
Output Ripple
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VFB
VISO (LINE)
VISO (LOAD)
VISO (RIP)
3.0
1.125
3.3
1.25
1
1
50
3.6
1.375
10
2
V
V
mV/V
%
mV p-p
IISO = 0 mA, VISO = VFB × (R1 + R2)/R2
IISO = 0 mA
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
IISO = 20 mA to 100 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
ROC = 50 kΩ
ROC = 270 kΩ
VOC = VDD2 (open loop)
Output Noise
VISO (N)
100
mV p-p
Switching Frequency
fSW
RON
1000
200
318
0.6
kHz
kHz
kHz
Ω
VUV+
VUV−
VUVH
2.8
2.6
0.2
V
V
V
70
mA
%
192
Switch On Resistance
Undervoltage Lockout, VDD1, VDD2
Supplies
Positive Going Threshold
Negative Going Threshold
Hysteresis
DC to 2 Mbps Data Rate 1
Maximum Output Supply Current 2
Efficiency at Maximum Output
Supply Current 3
iCOUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
Available VISO Supply Current 4
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
IDD1 Supply Current, Full VISO Load
I/O Input Currents
IISO (MAX)
515
250
IDD1 (Q)
IISO = 0 mA, f ≤ 1 MHz
9
10
11
11
12
20
20
20
20
20
mA
mA
mA
mA
mA
IDD1 (D)
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
28
29
31
32
34
mA
mA
mA
mA
mA
244
243
241
240
238
350
mA
mA
mA
mA
mA
mA
IISO (LOAD)
CL = 15 pF, f = 12.5 MHz
IDD1 (MAX)
IIA, IIB, IIC, IID
f ≤ 1 MHz,
VISO = 3.3 V
IISO = IISO (MAX)
−10
+0.01
Rev. B | Page 5 of 36
+10
µA
CL = 0 pF, f = 0 MHz, VDD1 = 3.3 V,
IISO = 250 mA
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
AC SPECIFICATIONS
A Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Propagation Delay Skew
Channel-to-Channel Matching
C Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
At Logic High Output
At Logic Low Output
Refresh Rate
Symbol
VIH
VIL
VOAH, VOBH,
VOCH, VODH
Min
1.6
Typ
VDD1 − 0.3,
VISO − 0.3
VDD1 − 0.5,
VISO − 0.5
Max
5.0
Unit
V
V
V
IOx = −20 µA, VIx = VIxH
4.8
V
IOx = −4 mA, VIx = VIxH
0.4
VOAL, VOBL,
VOCL, VODL
Data Sheet
Test Conditions/Comments
0.0
0.1
V
IOx = 20 µA, VIx = VIxL
0.0
0.4
V
IOx = 4 mA, VIx = VIxL
1000
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
PW
1
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
60
100
40
50
50
CL = 15 pF, CMOS signal levels
PW
tPHL, tPLH
PWD
40
25
30
60
75
8
5
tPSK
45
tPSKCD
tPSKOD
tR/tF
8
15
|CMH|
|CML|
fr
25
25
ns
Mbps
ns
ns
ps/°C
ns
2.5
ns
ns
ns
35
35
1.0
kV/µs
kV/µs
Mbps
CL = 15 pF, CMOS signal levels
VCM = 1000 V, transient
magnitude = 800 V
VIx = VDD1 or VISO
VIx = 0 V
The contributions of supply current values for all four channels are combined at identical data rates.
The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3
The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4
This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
1
2
Rev. B | Page 6 of 36
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ VDD1 = VDDA ≤ 5.5 V; VDD2 = VREG = VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 3.3 V.
Table 3.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage
Feedback Voltage Setpoint
Line Regulation
Load Regulation
Output Ripple
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VFB
VISO (LINE)
VISO (LOAD)
VISO (RIP)
3.0
1.125
3.3
1.25
1
1
50
3.6
1.375
10
2
V
V
mV/V
%
mV p-p
IISO = 0 mA, VISO = VFB × (R1 + R2)/R2
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 50 mA to 200 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
ROC = 50 kΩ
ROC = 270 kΩ
VOC = VDD2 (open loop)
Output Noise
VISO (N)
100
mV p-p
Switching Frequency
fSW
RON
1000
200
318
0.5
kHz
kHz
kHz
Ω
VUV+
VUV−
VUVH
2.8
2.6
0.2
V
V
V
70
mA
%
192
Switch On Resistance
Undervoltage Lockout, VDD1, VDD2
Supplies
Positive Going Threshold
Negative Going Threshold
Hysteresis
DC to 2 Mbps Data Rate 1
Maximum Output Supply Current 2
Efficiency at Maximum Output
Supply Current 3
iCOUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
Available VISO Supply Current 4
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
IDD1 Supply Current, Full VISO Load
I/O Input Currents
IISO (MAX)
515
400
IDD1 (Q)
IISO = 0 mA, f ≤ 1 MHz
9
9
10
10
10
30
30
30
30
30
mA
mA
mA
mA
mA
IDD1 (D)
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
33
33
33
33
33
mA
mA
mA
mA
mA
393
392
390
389
388
375
mA
mA
mA
mA
mA
mA
IISO (LOAD)
CL = 15 pF, f = 12.5 MHz
IDD1 (MAX)
IIA, IIB, IIC, IID
f ≤ 1 MHz
VISO = 3.3 V
IISO = IISO (MAX)
−20
+0.01
Rev. B | Page 7 of 36
+20
µA
CL = 0 pF, f = 0 MHz, VDD1 = 5 V,
IISO = 400 mA
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
AC SPECIFICATIONS
A Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Propagation Delay Skew
Channel-to-Channel Matching
C Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
At Logic High Output
At Logic Low Output
Refresh Rate
Symbol
VIH
VIL
VOAH, VOBH,
VOCH, VODH
Min
2.0
Typ
VDD1 − 0.3,
VISO − 0.3
VDD1 − 0.5,
VISO − 0.5
Max
5.0
Unit
V
V
V
IOx = −20 µA, VIx = VIxH
4.8
V
IOx = −4 mA, VIx = VIxH
0.8
VOAL, VOBL,
VOCL, VODL
Data Sheet
Test Conditions/Comments
0.0
0.1
V
IOx = 20 µA, VIx = VIxL
0.0
0.4
V
IOx = 4 mA, VIx = VIxL
1000
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
PW
1
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
55
100
40
50
50
CL = 15 pF, CMOS signal levels
PW
tPHL, tPLH
PWD
40
25
30
50
70
8
5
tPSK
15
tPSKCD
tPSKOD
tR/tF
8
15
|CMH|
|CML|
fr
25
25
ns
Mbps
ns
ns
ps/°C
ns
2.5
ns
ns
ns
35
35
1.0
kV/µs
kV/µs
Mbps
CL = 15 pF, CMOS signal levels
VCM = 1000 V, transient
magnitude = 800 V
VIx = VDD1 or VISO
VIx = 0 V
The contributions of supply current values for all four channels are combined at identical data rates.
The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3
The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4
This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
1
2
Rev. B | Page 8 of 36
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/15 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ VDD1 = VDDA ≤ 5.5 V; VREG = VISO = 15 V; VDD2 = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 39). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VREG = VISO = 15 V, VDD2 = 5.0 V.
Table 4.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage
Feedback Voltage Setpoint
VDD2 Linear Regulator
Regulator Voltage
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VFB
13.5
1.125
15
1.25
16.5
1.375
V
V
IISO = 0 mA, VISO = VFB × (R1 + R2)/R2
IISO = 0 mA
VDD2
4.6
5.0
5.7
V
1.5
20
3
V
mV/V
%
mV p-p
VREG = 7 V to 15 V, IDD2 = 0 mA
to 50 mA
IDD2 = 50 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 20 mA to 100 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
ROC = 50 kΩ
ROC = 270 kΩ
VOC = VDD2 (open loop)
Dropout Voltage
Line Regulation
Load Regulation
Output Ripple
VDD2 (DO)
VISO (LINE)
VISO (LOAD)
VISO (RIP)
0.5
1
1
200
Output Noise
VISO (N)
500
mV p-p
Switching Frequency
fSW
RON
1000
200
318
0.5
kHz
kHz
kHz
Ω
VUV+
VUV−
VUVH
2.8
2.6
0.2
V
V
V
70
mA
%
192
Switch On Resistance
Undervoltage Lockout, VDD1, VDD2 Supplies
Positive Going Threshold
Negative Going Threshold
Hysteresis
DC to 2 Mbps Data Rate 1
Maximum Output Supply Current 2
Efficiency at Maximum Output
Supply Current 3
iCOUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
Available VISO Supply Current 4
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
IDD1 Supply Current, Full VISO Load
IISO (MAX)
515
100
IDD1 (Q)
IISO = 0 mA, f ≤ 1 MHz
25
27
29
31
33
45
45
45
45
45
mA
mA
mA
mA
mA
IDD1 (D)
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
73
83
93
102
112
mA
mA
mA
mA
mA
91
89
86
83
80
425
mA
mA
mA
mA
mA
mA
IISO (LOAD)
IDD1 (MAX)
f ≤ 1 MHz
VISO = 5.0 V
IISO = IISO (MAX)
CL = 15 pF, f = 12.5 MHz
Rev. B | Page 9 of 36
CL = 0 pF, f = 0 MHz, VDD1 = 5 V,
IISO = 100 mA
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter
I/O Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
AC SPECIFICATIONS
A Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Propagation Delay Skew
Channel-to-Channel Matching
C Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
At Logic High Output
At Logic Low Output
Refresh Rate
Symbol
IIA, IIB, IIC, IID
VIH
VIL
VOAH, VOBH,
VOCH, VODH
Min
−20
2.0
Typ
+0.01
VDD1 − 0.3,
VISO − 0.3
VDD1 − 0.5,
VISO − 0.5
Max
+20
5.0
Unit
µA
V
V
V
IOx = −20 µA, VIx = VIxH
4.8
V
IOx = −4 mA, VIx = VIxH
0.8
VOAL, VOBL,
VOCL, VODL
Data Sheet
Test Conditions/Comments
0.0
0.1
V
IOx = 20 µA, VIx = VIxL
0.0
0.4
V
IOx = 4 mA, VIx = VIxL
1000
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
PW
1
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
55
100
40
50
50
CL = 15 pF, CMOS signal levels
PW
tPHL, tPLH
PWD
40
25
30
45
60
8
5
tPSK
15
tPSKCD
tPSKOD
tR/tF
8
15
|CMH|
|CML|
fr
25
25
ns
Mbps
ns
ns
ps/°C
ns
2.5
ns
ns
ns
35
35
1.0
kV/µs
kV/µs
Mbps
CL = 15 pF, CMOS signal levels
VCM = 1000 V, transient
magnitude = 800 V
VIx = VDD1 or VISO
VIx = 0 V
The contributions of supply current values for all four channels are combined at identical data rates.
The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3
The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4
This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
1
2
Rev. B | Page 10 of 36
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
PACKAGE CHARACTERISTICS
Table 5.
Parameter
RESISTANCE AND CAPACITANCE
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction to Ambient Thermal
Resistance
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Symbol
Min
Typ
Max
Unit
RI-O
CI-O
CI
θJA
1012
2.2
4.0
50.5
Ω
pF
pF
°C/W
TSSD
TSSD-HYS
150
20
°C
°C
Test Conditions/Comments
f = 1 MHz
Thermocouple is located at the center of
the package underside; test conducted on
a 4-layer board with thin traces 3
TJ rising
The device is considered a 2-terminal device: Pin 1 to Pin 10 are shorted together, and Pin 11 to Pin 20 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
1
2
REGULATORY APPROVALS
The ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 are approved by the organizations listed in Table 6. Refer to Table 11
and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation
waveforms and insulation levels.
Table 6.
UL
Recognized under the UL 1577 component
recognition program 1
Single protection, 2500 V rms isolation
voltage
File E214100
CSA
Approved under CSA Component Acceptance
Notice #5A
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 600 V rms (848 V peak) maximum
working voltage
File 205078
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying an insulation test voltage of ≥3000 V rms
for 1 sec (current leakage detection limit = 10 µA).
2
In accordance with DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying
an insulation test voltage of ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
1
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 7.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
2500
>5.1
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
>5.1
mm
Minimum Internal Distance (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>400
II
mm
V
Rev. B | Page 11 of 36
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Distance through insulation
DIN IEC 112/VDE 0303, Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking branded on the component denotes DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
Table 8.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Test Conditions/Comments
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Tests Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
RS
150
1.25
>109
°C
A
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 3)
Case Temperature
Side 1 Current
Insulation Resistance at TS
VIO = 500 V
1.25
1.00
0.75
0.50
0.25
0
0
50
100
150
CASE TEMPERATURE (°C)
200
09369-002
SAFE OPERATING VDD1 CURRENT (A)
1.50
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 9.
Parameter
Operating Temperature
Supply Voltages 1
VDD1 at VISO = 3.3 V
VDD1 at VISO = 5.0 V
VDD1 at VISO = 5.0 V
Minimum Load
1
Symbol
TA
Min
−40
Max
+105
Unit
°C
VDD1
VDD1
VDD1
IISO (MIN)
3.0
3.0
4.5
10
3.6
3.6
5.5
V
V
V
mA
All voltages are relative to their respective grounds.
Rev. B | Page 12 of 36
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 11. Maximum Continuous Working Voltage
Supporting 50-Year Minimum Lifetime1
Table 10.
Parameter
Storage Temperature Range (TST)
Ambient Operating Temperature
Range (TA)
Supply Voltages1
VDD1,2 VDDA, VDD2
VREG, X1, X2
Input Voltage (VIA, VIB, VIC, VID)1, 3
Output Voltage (VOA, VOB, VOC, VOD)1, 3
Average Output Current per Pin4
Common-Mode Transients5
Rating
−55°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to +20.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
−100 kV/µs to +100 kV/µs
All voltages are relative to their respective grounds.
VDD1 is the power supply for the push-pull transformer.
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the Printed Circuit Board (PCB) Layout section.
4
See Figure 3 for maximum rated current values for various temperatures.
5
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.
1
2
3
Parameter
AC Voltage, Bipolar
Waveform
AC Voltage, Unipolar
Waveform
Basic Insulation
DC Voltage
Basic Insulation
1
Applicable
Certification
All certifications
Max
565
Unit
V peak
848
V peak
Working voltage
per IEC 60950-1
848
V peak
Working voltage
per IEC 60950-1
Refers to the continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 13 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Data Sheet
X1 1
20
VREG
*GND1 2
19
GND2*
NC 3
18
VDD2
X2 4
ADuM3470
17
FB
VIA 5
TOP VIEW
(Not to Scale)
16
VOA
15
VOB
VIC 7
14
VOC
VID 8
13
VOD
VDDA 9
12
OC
*GND1 10
11
GND2*
VIB 6
NOTES
1. NC = NO INTERNAL CONNECTION.
2. PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
09369-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADuM3470 Pin Configuration
Table 12. ADuM3470 Pin Function Descriptions
Pin No.
1
2, 10
Mnemonic
X1
GND1
3
4
5
6
7
8
9
11, 19
NC
X2
VIA
VIB
VIC
VID
VDDA
GND2
12
OC
13
14
15
16
17
VOD
VOC
VOB
VOA
FB
18
VDD2
20
VREG
Description
Transformer Driver Output 1.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
No Internal Connection.
Transformer Driver Output 2.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in openloop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Rev. B | Page 14 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
X1 1
20 VREG
*GND1 2
19 GND2*
NC 3
18 VDD2
X2 4
ADuM3471
17 FB
VIA 5
TOP VIEW
(Not to Scale)
16 VOA
VIB 6
VIC 7
15 VOB
14 VOC
VOD 8
13 VID
VDDA 9
12 OC
*GND1 10
11 GND2*
NOTES
1. NC = NO INTERNAL CONNECTION.
2. PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
09369-005
Data Sheet
Figure 5. ADuM3471 Pin Configuration
Table 13. ADuM3471 Pin Function Descriptions
Pin No.
1
2, 10
Mnemonic
X1
GND1
3
4
5
6
7
8
9
11, 19
NC
X2
VIA
VIB
VIC
VOD
VDDA
GND2
12
OC
13
14
15
16
17
VID
VOC
VOB
VOA
FB
18
VDD2
20
VREG
Description
Transformer Driver Output 1.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
No Internal Connection.
Transformer Driver Output 2.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in openloop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Rev. B | Page 15 of 36
X1 1
20
VREG
*GND1 2
19
GND2*
NC 3
18
VDD2
X2 4
ADuM3472
17
FB
VIA 5
TOP VIEW
(Not to Scale)
16
VOA
15
VOB
VOC 7
14
VIC
VOD 8
13
VID
VDDA 9
12
OC
*GND1 10
11
GND2*
VIB 6
NOTES
1. NC = NO INTERNAL CONNECTION.
2. PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
Data Sheet
09369-006
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Figure 6. ADuM3472 Pin Configuration
Table 14. ADuM3472 Pin Function Descriptions
Pin No.
1
2, 10
Mnemonic
X1
GND1
3
4
5
6
7
8
9
11, 19
NC
X2
VIA
VIB
VOC
VOD
VDDA
GND2
12
OC
13
14
15
16
17
VID
VIC
VOB
VOA
FB
18
VDD2
20
VREG
Description
Transformer Driver Output 1.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
No Internal Connection.
Transformer Driver Output 2.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in openloop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Rev. B | Page 16 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
X1 1
20
VREG
*GND1 2
19
GND2*
NC 3
18
VDD2
X2 4
ADuM3473
17
FB
VIA 5
TOP VIEW
(Not to Scale)
16
VOA
15
VIB
VOC 7
14
VIC
VOD 8
13
VID
VDDA 9
12
OC
*GND1 10
11
GND2*
VOB 6
NOTES
1. NC = NO INTERNAL CONNECTION.
2. PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
09369-007
Data Sheet
Figure 7. ADuM3473 Pin Configuration
Table 15. ADuM3473 Pin Function Descriptions
Pin No.
1
2, 10
Mnemonic
X1
GND1
3
4
5
6
7
8
9
11, 19
NC
X2
VIA
VOB
VOC
VOD
VDDA
GND2
12
OC
13
14
15
16
17
VID
VIC
VIB
VOA
FB
18
VDD2
20
VREG
Description
Transformer Driver Output 1.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
No Internal Connection.
Transformer Driver Output 2.
Logic Input A.
Logic Output B.
Logic Output C.
Logic Output D.
Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in openloop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
Logic Input D.
Logic Input C.
Logic Input B.
Logic Output A.
Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Rev. B | Page 17 of 36
X1 1
20
VREG
*GND1 2
19
GND2*
NC 3
18
VDD2
X2 4
ADuM3474
17
FB
VOA 5
TOP VIEW
(Not to Scale)
16
VIA
15
VIB
VOC 7
14
VIC
VOD 8
13
VID
VDDA 9
12
OC
*GND1 10
11
GND2*
VOB 6
NOTES
1. NC = NO INTERNAL CONNECTION.
2. PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED TO EACH OTHER; IT IS
RECOMMENDED THAT BOTH PINS BE CONNECTED TO A COMMON GROUND.
Data Sheet
09369-008
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Figure 8. ADuM3474 Pin Configuration
Table 16. ADuM3474 Pin Function Descriptions
Pin No.
1
2, 10
Mnemonic
X1
GND1
3
4
5
6
7
8
9
11, 19
NC
X2
VOA
VOB
VOC
VOD
VDDA
GND2
12
OC
13
14
15
16
17
VID
VIC
VIB
VIA
FB
18
VDD2
20
VREG
Description
Transformer Driver Output 1.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
No Internal Connection.
Transformer Driver Output 2.
Logic Output A.
Logic Output B.
Logic Output C.
Logic Output D.
Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in openloop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
Logic Input D.
Logic Input C.
Logic Input B.
Logic Input A.
Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Table 17. Truth Table (Positive Logic)
VIx Input1
High
Low
1
VDD1 State
Powered
Powered
VDD2 State
Powered
Powered
VOxOutput1
High
Low
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
Rev. B | Page 18 of 36
Notes
Normal operation, data is high
Normal operation, data is low
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
TYPICAL PERFORMANCE CHARACTERISTICS
1500
1400
80
1300
70
1200
60
1100
EFFICIENCY (%)
fSW (kHz)
1000
900
800
700
600
500
400
50
40
30
20
300
–40°C
+25°C
+105°C
10
100
100
150
200
250
300
350
400
450
500
ROC (kΩ)
0
70
70
60
60
EFFICIENCY (%)
80
50
40
30
50
100
150
200
250
300
350
400
450
500
LOAD CURRENT (mA)
Figure 10. Typical Efficiency at Various Switching Frequencies with
Coilcraft Transformer, 5 V Input to 5 V Output
0
EFFICIENCY (%)
50
40
30
350
400
450
500
LOAD CURRENT (mA)
09369-011
300
100
150
200
250
300
350
400
450
500
50
40
30
1MHz
700kHz
500kHz
200kHz
10
0
250
50
20
1MHz
700kHz
500kHz
200kHz
200
500
Figure 13. Single-Supply Efficiency with Coilcraft Transformer, fSW = 500 kHz
60
150
450
LOAD CURRENT (mA)
60
100
400
VDD1 = 5V, VISO = 5V
VDD1 = 5V, VISO = 3.3V
VDD1 = 3.3V, VISO = 3.3V
0
70
50
350
30
70
0
300
40
80
10
250
50
80
20
200
10
0
0
150
20
1MHz
700kHz
500kHz
200kHz
10
100
Figure 12. Typical Efficiency over Temperature with Coilcraft Transformer,
fSW = 500 kHz, 5 V Input to 5 V Output
80
20
50
LOAD CURRENT (mA)
09369-010
EFFICIENCY (%)
Figure 9. Switching Frequency (fSW) vs. ROC Resistance
EFFICIENCY (%)
0
09369-013
50
0
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
LOAD CURRENT (mA)
Figure 14. Typical Efficiency at Various Switching Frequencies with
Coilcraft Transformer, 5 V Input to 15 V Output
Figure 11. Typical Efficiency at Various Switching Frequencies with
Halo Transformer, 5 V Input to 5 V Output
Rev. B | Page 19 of 36
09369-014
0
09369-009
0
09369-012
200
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
80
Data Sheet
15
70
10
ICH (mA)
50
40
30
5
1MHz
700kHz
500kHz
200kHz
10
0
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
LOAD CURRENT (mA)
VDD1 = 5V, VISO = 5V
VDD1 = 5V, VISO = 3.3V
VDD1 = 3.3V, VISO = 3.3V
0
Figure 15. Typical Efficiency at Various Switching Frequencies with
Halo Transformer, 5 V Input to 15 V Output
0
5
10
15
20
25
DATA RATE (Mbps)
09369-029
20
09369-026
EFFICIENCY (%)
60
Figure 18. Typical Single-Supply ICH Supply Current per Forward Data Channel
(15 pF Output Load)
15
80
70
10
50
ICH (mA)
EFFICIENCY (%)
60
40
30
5
20
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
LOAD CURRENT (mA)
0
09369-027
0
Figure 16. Typical Efficiency over Temperature with Coilcraft Transformer,
fSW = 500 kHz, 5 V Input to 15 V Output
0
5
10
20
25
Figure 19. Typical Single-Supply ICH Supply Current per Reverse Data Channel
(15 pF Output Load)
80
5
VDD1 = 5V, VISO = 5V
VDD1 = 5V, VISO = 3.3V
VDD1 = 3.3V, VISO = 3.3V
70
4
60
50
IISO (D) (mA)
EFFICIENCY (%)
15
DATA RATE (Mbps)
09369-030
VDD1 = 5V, VISO = 5V
VDD1 = 5V, VISO = 3.3V
VDD1 = 3.3V, VISO = 3.3V
–40°C
+25°C
+105°C
10
40
30
3
2
20
1
10
10
20
30
40
50
60
70
80
90 100 110 120 130 140
LOAD CURRENT (mA)
Figure 17. Double-Supply Efficiency with Coilcraft Transformer, fSW = 500 kHz
Rev. B | Page 20 of 36
0
0
5
10
15
20
25
DATA RATE (Mbps)
Figure 20. Typical Single-Supply IISO (D) Dynamic Supply Current
per Output Channel (15 pF Output Load)
09369-031
0
09369-028
VDD1 = 5V, VISO = 15V
VDD1 = 5V, VISO = 12V
0
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
5
5
4
IISO (D) (mA)
4
3
2
3
2
1
1
0
5
10
15
20
25
DATA RATE (Mbps)
0
09369-032
0
0
5
10
15
20
25
DATA RATE (Mbps)
Figure 21. Typical Single-Supply IISO (D) Dynamic Supply Current
per Input Channel
09369-035
IISO (D) (mA)
VDD1 = 5V, V ISO = 15V
VDD1 = 5V, V ISO = 12V
VDD1 = 5V, VISO = 5V
VDD1 = 5V, VISO = 3.3V
VDD1 = 3.3V, VISO = 3.3V
Figure 24. Typical Double-Supply IISO (D) Dynamic Supply Current
per Output Channel (15 pF Output Load)
5
30
VDD1 = 5V, V ISO = 15V
VDD1 = 5V, V ISO = 12V
VDD1 = 5V, V ISO = 15V
VDD1 = 5V, V ISO = 12V
25
4
IISO (D) (mA)
ICH (mA)
20
15
3
2
10
0
5
10
15
20
25
DATA RATE (Mbps)
0
09369-033
0
0
10
15
20
25
DATA RATE (Mbps)
Figure 22. Typical Double-Supply ICH Supply Current per Forward Data
Channel (15 pF Output Load)
Figure 25. Typical Double-Supply IISO (D) Dynamic Supply Current
per Input Channel
30
6
VDD1 = 5V, V ISO = 15V
VDD1 = 5V, V ISO = 12V
25
5
4
15
3
10
2
5
1
0
5
10
15
DATA RATE (Mbps)
20
25
0
09369-034
0
Figure 23. Typical Double-Supply ICH Supply Current per Reverse Data
Channel (15 pF Output Load)
VISO AT 10mA
VISO AT 50mA
VISO AT 400mA
0
5
10
15
TIME (ms)
20
25
30
09369-037
VISO (V)
20
ICH (mA)
5
09369-036
1
5
Figure 26. Typical VISO Startup with 10 mA, 50 mA, and 400 mA Output Load,
5 V Input to 5 V Output
Rev. B | Page 21 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
6.0
5
Data Sheet
COUT = 47µF, L1 = 47µH
5.5
5.0
VISO (V)
4
VISO (V)
3
4.5
6.0
COUT = 47µF, L1 = 100µH
5.5
5.0
2
4.5
0
5
10
15
20
25
30
TIME (ms)
Figure 27. Typical VISO Startup with 10 mA, 50 mA, and 400 mA Output Load,
5 V Input to 3.3 V Output
1.0
90% LOAD
0.5
0
–2
0
2
10% LOAD
4
6
8
10
12
14
TIME (ms)
09369-041
0
09369-038
VISO AT 10mA
VISO AT 50mA
VISO AT 400mA
ILOAD (A)
1
Figure 30. Typical VISO Load Transient Response at 10% to 90% of 400 mA Load,
fSW = 500 kHz, 5 V Input to 5 V Output
4.0
5
COUT = 47µF, L1 = 47µH
3.5
3.0
VISO (V)
4
VISO (V)
3
4.0
COUT = 47µF, L1 = 100µH
3.5
3.0
0
0
5
10
15
20
25
30
TIME (ms)
09369-039
VISO AT 10mA
VISO AT 50mA
VISO AT 250mA
Figure 28. Typical VISO Startup with 10 mA, 50 mA, and 250 mA Output Load,
3.3 V Input to 3.3 V Output
1.0
90% LOAD
0.5
0
–2
0
2
10% LOAD
4
6
8
10
12
14
TIME (ms)
09369-042
1
ILOAD (A)
2
Figure 31. Typical VISO Load Transient Response at 10% to 90% of 400 mA Load,
fSW = 500 kHz, 5 V Input to 3.3 V Output
18
4.0
16
3.5
COUT = 47µF, L1 = 47µH
3.0
VISO (V)
14
VISO (V)
12
4.0
10
COUT = 47µF, L1 = 100µH
3.5
8
3.0
6
0
5
10
15
TIME (ms)
20
25
30
Figure 29. Typical VISO Startup with 10 mA, 20 mA, and 100 mA Output Load,
5 V Input to 15 V Output
1.0
90% LOAD
0.5
0
–2
0
2
4
10% LOAD
6
TIME (ms)
8
10
12
14
09369-044
0
09369-040
VISO AT 10mA
VISO AT 20mA
VISO AT 100mA
2
ILOAD (A)
4
Figure 32. Typical VISO Load Transient Response at 10% to 90% of 250 mA Load,
fSW = 500 kHz, 3.3 V Input to 3.3 V Output
Rev. B | Page 22 of 36
Data Sheet
18
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
3.34
COUT = 47µF, L1 = 47µH, L2 = 47µH
16
18
3.30
COUT = 47µF, L1 = 100µH, L2 = 100µH
14
3.28
12
20
0
–2
90% LOAD
10% LOAD
100
2
10
6
X1 (V)
200
14
18
22
26
30
34
TIME (ms)
X2 ON
10
0
–2
X1 ON
–1
0
1
2
TIME (µs)
Figure 36. Typical VISO Output Voltage Ripple at 250 mA Load,
fSW = 500 kHz, 3.3 V Input to 3.3 V Output
Figure 33. Typical VISO Load Transient Response at 10% to 90% of 100 mA Load,
fSW = 500 kHz, 5 V Input to 15 V Output
15.4
5.04
15.2
VISO (V)
5.02
VISO (V)
3.32
09369-047
16
ILOAD (A)
VISO (V)
12
09369-043
VISO (V)
14
5.00
15.0
14.8
4.98
14.6
20
10
X1 ON
0
–2
–1
0
1
2
TIME (µs)
3.34
VISO (V)
3.32
3.30
3.28
20
X1 ON
–1
0
1
2
TIME (µs)
09369-046
X1 (V)
X2 ON
0
–2
10
0
–2
X1 ON
–1
0
1
2
TIME (µs)
Figure 37. Typical VISO Output Voltage Ripple at 100 mA Load,
fSW = 500 kHz, 5 V Input to 15 V Output
Figure 34. Typical VISO Output Voltage Ripple at 400 mA Load,
fSW = 500 kHz, 5 V Input to 5 V Output
10
X2 ON
Figure 35. Typical VISO Output Voltage Ripple at 400 mA Load,
fSW = 500 kHz, 5 V Input to 3.3 V Output
Rev. B | Page 23 of 36
09369-048
X1 (V)
X2 ON
09369-045
X1 (V)
20
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Data Sheet
TERMINOLOGY
IDD1 (Q)
IDD1 (Q) is the minimum operating current drawn at the VDD1 power
input when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic supply
current.
IDD1 (D)
IDD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps with
the full capacitive load representing the maximum dynamic
load conditions. Treat resistive loads on the outputs separately
from the dynamic load.
IDD1 (MAX)
IDD1 (MAX) is the input current under full dynamic and VISO load
conditions.
tPHL Propagation Delay
The tPHL propagation delay is measured from the 50% level of
the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal.
tPLH Propagation Delay
The tPLH propagation delay is measured from the 50% level of
the rising edge of the VIx signal to the 50% level of the rising
edge of the VOx signal.
Propagation Delay Skew (tPSK)
tPSK is the magnitude of the worst-case difference in tPHL and/or
tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended
operating conditions.
Channel-to-Channel Matching
Channel-to-channel matching is the absolute value of the difference in propagation delays between two channels when operated
with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. B | Page 24 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
APPLICATIONS INFORMATION
D1
L1
VISO =
+3.3V
TO +15V
T1
The ADuM347x devices implement undervoltage lockout
(UVLO) with hysteresis on the VDDA power input. This feature
ensures that the converter does not go into oscillation due to
noisy input power or slow power-on ramp rates.
CIN
1 X1
20 VREG
2 GND1
19 GND2
3 NC
18 VDD2
4 X2
5 VIA/VOA
6 VIB/VOB
7 VIC/VOC
VDD1
0.1µF
R2
15 VIB/VOB
14 VIC/VOC
13 VID/VOD
9 VDDA
12 OC
10 GND1
11 GND 2
ROC 100kΩ
D1
L1
T1
47µH
47µF
COUT1
L2
COUT2
VDD1
CIN
D2
VISO =
+12V TO
+24V
UNREGULATED
+6V TO
+12V
47µF
47µH
D3
R1
D4
1 X1
20 VREG
2 GND1
19 GND2
3 NC
4 X2
5 VIA/VOA
7 VIC/VOC
VDD1
0.1µF
ADuM3470/
ADuM3471/
ADuM3472/
ADuM3473/
ADuM3474
0.1µF
+5V
18 VDD2
17 FB
VFB
16 VIA/VOA
R2
15 VIB/VOB
14 VIC/VOC
8 VID/VOD
13 VID/VOD
9 VDDA
12 OC
10 GND1
11 GND 2
ROC 100kΩ
VISO = VFB × (R1 + R2)/R2
FOR VISO = 15V OR LESS, VREG CAN CONNECT TO VISO.
Figure 39. Doubling Power Supply
D1
L1
T1
47µH
47µF
COUT1
VISO =
COARSELY
REGULATED
+5V TO +15V
VDD1
CIN
D2
L2
COUT2
47µF
UNREGULATED
–5V TO –15V
47µH
D3
R1
D4
Figure 40, which also uses a voltage doubling secondary circuit,
is an example of a coarsely regulated, positive power supply and
an unregulated, negative power supply for outputs of approximately ±5 V, ±12 V, and ±15 V.
VISO = VFB × (R1 + R2)/R2
VFB
16 VIA/VOA
8 VID/VOD
6 VIB/VOB
For all the circuits shown in Figure 38 to Figure 40, the isolated
output voltage (VISO) can be set with the voltage dividers, R1
and R2 (values 1 kΩ to 100 kΩ) using the following equation:
+5V
17 FB
Figure 38. Single Power Supply
APPLICATION SCHEMATICS
Figure 39 shows a voltage doubling circuit that can be used for a
single supply with an output that exceeds 15 V; 15 V is the largest
supply that can be connected to the regulator input, VREG (Pin 20).
In the circuit shown in Figure 39, the output voltage can be as high
as 24 V, and the voltage at the VREG pin can be as high as 12 V.
When using the circuit shown in Figure 39 to obtain an output
voltage lower than 10 V (for example, VDD1 = 3.3 V, VISO = 5 V),
connect VREG to VISO directly.
ADuM3470/
ADuM3471/
ADuM3472/
ADuM3473/
ADuM3474
0.1µF
VISO = VFB × (R1 + R2)/R2
FOR VISO = 3.3V OR 5V, CONNECT V REG , VDD2 , AND V ISO.
A minimum load current of 10 mA is recommended to ensure
optimum load regulation. Smaller loads can generate excess noise
on the output due to short or erratic PWM pulses. Excess noise
generated in this way can cause regulation problems in some
circumstances.
The ADuM347x devices have three main application schematics,
as shown in Figure 38 to Figure 40. Figure 38 has a center-tapped
secondary and two Schottky diodes that provide full wave
rectification for a single output, typically for power supplies of
3.3 V, 5 V, 12 V, and 15 V. For single supplies when VISO = 3.3 V
or 5 V, VREG, VDD2, and VISO can be connected together.
R1
D2
1 X1
20 VREG
2 GND1
3 NC
4 X2
5 VIA/VOA
6 VIB/VOB
7 VIC/VOC
8 VID/VOD
VDD1
0.1µF
19 GND2
ADuM3470/
ADuM3471/
ADuM3472/
ADuM3473/
ADuM3474
18 VDD2
17 FB
0.1µF
+5V
VFB
16 VIA/VOA
R2
15 VIB/VOB
14 VIC/VOC
13 VID/VOD
9 VDDA
12 OC
10 GND1
11 GND 2
ROC 100kΩ
VISO = VFB × (R1 + R2)/R2
where VFB is the internal feedback voltage (approximately 1.25 V).
Rev. B | Page 25 of 36
Figure 40. Positive Supply and Unregulated Negative Supply
09369-017
The secondary (VISO) side controller regulates the output using
a feedback voltage, VFB, from a resistor divider on the output to
create a PWM control signal that is sent to the primary (VDD1) side
by a dedicated iCoupler data channel labeled VFB. The primary side
PWM converter varies the duty cycle of the X1 and X2 switches
to modulate the oscillator circuit and control the power being
sent to the secondary side. This feedback allows for significantly
higher power and efficiency.
VDD1
09369-015
The dc-to-dc converter section of the ADuM347x uses a
secondary side controller architecture with isolated pulse-width
modulation (PWM) feedback. VDD1 power is supplied to an oscillating circuit that switches current to the primary side of an external
power transformer using internal push-pull switches at the X1
and X2 pins. Power transferred to the secondary side of the transformer is full wave rectified with external Schottky diodes (D1
and D2), filtered with the L1 inductor and COUT capacitor, and
regulated to the isolated power supply voltage from 3.3 V to 15 V.
47µH
COUT
47µF
09369-016
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
TRANSFORMER DESIGN
Custom transformers were designed for use in the circuits shown
in Figure 38, Figure 39, and Figure 40 (see Table 18). The transformers designed for use with the ADuM347x differ from other
transformers used with isolated dc-to-dc converters that do not
regulate the output voltage. The output voltage is regulated by a
PWM controller in the ADuM347x that varies the duty cycle of
the primary side switches in response to a secondary side feedback voltage, VFB, received through an isolated digital channel.
The internal controller has a maximum duty cycle of 40%.
TRANSFORMER TURNS RATIO
To determine the transformer turns ratio—taking into account
the losses for the primary switches and the losses for the secondary
diodes and inductors—the external transformer turns ratio for
the ADuM347x can be calculated using Equation 1.
NS
NP
=
VISO + VD
(1)
VDD1 ( MIN ) × D × 2
where:
NS/NP is the primary to secondary turns ratio.
VISO is the isolated output supply voltage.
VD is the Schottky diode voltage drop (0.5 V maximum).
VDD1 (MIN) is the minimum input supply voltage.
D is the duty cycle = 0.30 for a 30% typical duty cycle (40% is
the maximum duty cycle).
2 is a multiplier factor used for the push-pull switching cycle.
NS
NP
The circuit shown in Figure 39 uses double windings and diode
pairs to create a doubler circuit; therefore, half the output voltage,
VISO/2, is used, as shown in Equation 2.
=
2
+ VD
(2)
VDD1 ( MIN ) × D × 2
For the circuit shown in Figure 39 using the 5 V to 15 V reference
design in Table 18 and with VDD1 (MIN) = 4.5 V, the turns ratio is
NS/NP = 3.
The circuit shown in Figure 40 also uses double windings and
diode pairs to create a doubler circuit. However, because a
positive and negative output voltage are created, VISO is used,
and the external transformer turns ratio can be calculated using
Equation 3.
NP
For a 3.3 V input to 3.3 V output isolated single power supply
and with VDD1 (MIN) = 3.0 V, the turns ratio is also NS/NP = 2.
Therefore, the same transformer turns ratio, NS/NP = 2, can be
used for the three single power applications: 5 V to 5 V, 5 V to
3.3 V, and 3.3 V to 3.3 V.
VISO
where:
NS/NP is the primary to secondary turns ratio.
VISO is the isolated output supply voltage. VISO/2 is used because
the circuit uses two pairs of diodes, creating a doubler circuit.
VD is the Schottky diode voltage drop (0.5 V maximum).
VDD1 (MIN) is the minimum input supply voltage.
D is the duty cycle = 0.30 for a 30% typical duty cycle (40% is
the maximum duty cycle).
2 is a multiplier factor used for the push-pull switching cycle.
NS
For the circuit shown in Figure 38 using the 5 V to 5 V reference
design in Table 18 and with VDD1 (MIN) = 4.5 V, the turns ratio is
NS/NP = 2.
Data Sheet
=
VISO + VD
(3)
VDD1 ( MIN ) × D × 2
where:
NS/NP is the primary to secondary turns ratio.
VISO is the isolated output supply voltage.
VD is the Schottky diode voltage drop (0.5 V maximum).
VDD1 (MIN) is the minimum input supply voltage.
D is the duty cycle = 0.35 for a 35% typical duty cycle (40% is
the maximum duty cycle).
2 is a multiplier factor used for the push-pull switching cycle.
For the circuit shown in Figure 40, the duty cycle, D, is set to 0.35
for a 35% typical duty cycle to reduce the maximum voltages seen
by the diodes for a ±15 V supply.
For the circuit shown in Figure 40 using the +5 V to ±15 V reference design in Table 18 and with VDD1 (MIN) = 4.5 V, the turns
ratio is NS/NP = 5.
Table 18. Transformer Reference Designs
Part No.
JA4631-BL
JA4650-BL
KA4976-AL
TGSAD-260V6LF
TGSAD-290V6LF
TGSAD-292V6LF
TGAD-260NARL
TGAD-290NARL
TGAD-292NARL
Manufacturer
Coilcraft
Coilcraft
Coilcraft
Halo Electronics
Halo Electronics
Halo Electronics
Halo Electronics
Halo Electronics
Halo Electronics
Turns Ratio,
PRI:SEC
1CT:2CT
1CT:3CT
1CT:5CT
1CT:2CT
1CT:3CT
1CT:5CT
1CT:2CT
1CT:3CT
1CT:5CT
ET Constant
(V × µs Min)
18
18
18
14
14
14
14
14
14
Total Primary
Inductance (µH)
255
255
255
389
389
389
389
389
389
Rev. B | Page 26 of 36
Total Primary
Resistance (Ω)
0.2
0.2
0.2
0.8
0.8
0.8
0.8
0.8
0.8
Isolation
Voltage (rms)
2500
2500
2500
2500
2500
2500
1500
1500
1500
Isolation
Type
Basic
Basic
Basic
Supplemental
Supplemental
Supplemental
Functional
Functional
Functional
Reference
Figure 38
Figure 39
Figure 40
Figure 38
Figure 39
Figure 40
Figure 38
Figure 39
Figure 40
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
TRANSFORMER ET CONSTANT
The next transformer design factor to consider is the ET constant.
This constant determines the minimum V × µs constant of the
transformer over the operating temperature. ET values of 14 V × µs
and 18 V × µs were selected for the ADuM347x transformer
designs listed in Table 18 using the following equation:
ET ( MIN ) =
VDD1 ( MAX )
The ADuM347x devices also have an open-loop mode where
the output voltage is not regulated and is dependent on the
transformer turns ratio, NS/NP, and the conditions of the output
including output load current and the losses in the dc-to-dc
converter circuit. This open-loop mode is selected when the OC
pin is connected high to the VDD2 pin. In open-loop mode, the
switching frequency is 318 kHz.
TRANSIENT RESPONSE
f SW ( MIN ) × 2
where:
VDD1 (MAX) is the maximum input supply voltage.
fSW (MIN) is the minimum primary switching frequency = 300 kHz
in startup.
2 is a multiplier factor used for the push-pull switching cycle.
TRANSFORMER PRIMARY INDUCTANCE AND
RESISTANCE
Another important characteristic of the transformer for designs
with the ADuM347x is the primary inductance. Transformers
for the ADuM347x are recommended to have between 60 µH to
100 µH of inductance per primary winding. Values of primary
inductance in this range are needed for smooth operation of the
ADuM347x pulse-by-pulse current-limit circuit, which can help
protect against a build-up of saturation currents in the transformer.
If the inductance is specified for the total of both primary windings, for example, as 400 µH, the inductance of one winding is
one-fourth of two equal windings, or 100 µH.
Another important characteristic of the transformer for designs
with the ADuM347x is primary resistance. Primary resistance as
low as is practical (less than 1 Ω) helps to reduce losses and
improves efficiency. The dc primary resistance can be measured
and specified, and is shown for the transformers in Table 18.
TRANSFORMER ISOLATION VOLTAGE
Isolation voltage and isolation type should be determined for
the requirements of the application and then specified. The
transformers in Table 18 have been specified for 2500 V rms
for supplemental or basic isolation and for 1500 V rms functional
isolation. Other isolation levels and isolation voltages can be
specified and requested from the transformer manufacturers
listed in Table 18 or from other manufacturers.
SWITCHING FREQUENCY
The ADuM347x switching frequency can be adjusted from
200 kHz to 1 MHz by changing the value of the ROC resistor
shown in Figure 38, Figure 39, and Figure 40. The value of the
ROC resistor needed for the desired switching frequency can be
determined from the switching frequency vs. ROC resistance curve
shown in Figure 9. The output filter inductor value and output
capacitor value for the ADuM347x application schematics have
been designed to be stable over the switching frequency range of
500 kHz to 1 MHz, when loaded from 10% to 90% of the maximum load.
The load transient response of the ADuM347x output voltage for
10% to 90% of the full load is shown in Figure 30 to Figure 33
for the application schematics in Figure 38 and Figure 39. The
response shown is slow but stable and can have more output
change than desired for some applications. The output voltage
change with load transient is reduced, and the output is shown
to remain stable by adding more inductance to the output circuits,
as shown in the second VISO output waveform in Figure 30 to
Figure 33. For additional improvement in transient response,
add a 0.1 µF ceramic capacitor (CFB) in parallel with the high
feedback resistor. This value helps to reduce the overshoot and
undershoot during load transients.
COMPONENT SELECTION
The ADuM347x digital isolators with 2 W dc-to-dc converters
require no external interface circuitry for the logic interfaces.
Power supply bypassing is required at the input and output supply
pins. Note that a low ESR ceramic bypass capacitor of 0.1 µF is
required on Side 1 between Pin 9 and Pin 10, and on Side 2
between Pin 18 and Pin 19, as close to the chip pads as possible.
The power supply section of the ADuM347x uses a high oscillator
frequency to efficiently pass power through the external power
transformer. In addition, normal operation of the data section of
the iCoupler introduces switching transients on the power supply
pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency
capacitor; ripple suppression and proper regulation require a large
value capacitor. To suppress noise and reduce ripple, large value
ceramic capacitors of X5R or X7R dielectric type are recommended. The recommended capacitor value is 10 µF for VDD1 and
47 µF for VISO. These capacitors have a low ESR and are available
in moderate 1206 or 1210 sizes for voltages up to 10 V. For output
voltages larger than 10 V, two 22 µF ceramic capacitors can be
used in parallel. See Table 19 for recommended components.
Table 19. Recommended Components
Part No.
GRM32ER71A476KE15L
GRM32ER71C226KEA8L
GRM31CR71A106KA01L
MBR0540T1G
Manufacturer
Murata
Murata
Murata
ON Semiconductor
LQH3NPN470MM0
ME3220-104KL
LQH6PPN470M43
LQH6PPN101M43
Murata
Coilcraft
Murata
Murata
Rev. B | Page 27 of 36
Value
47 µF, 10 V, X7R, 1210
22 µF, 16 V, X7R, 1210
10 µF, 10 V, X7R, 1206
Schottky, 0.5 A, 40 V,
SOD-123
47 µH, 0.41 A, 1212
100 µH, 0.34 A, 1210
47 µH, 1.10 A, 2424
100 µH, 0.80 A, 2424
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Inductors must be selected based on the value and supply
current needed. Most applications with switching frequencies
between 500 kHz and 1 MHz and load transients between 10%
and 90% of full load are stable with the 47 μH inductor value
listed in Table 19. Values as large as 200 μH can be used for power
supply applications with a switching frequency as low as 200 kHz
to help stabilize the output voltage or for improved load transient
response (see Figure 30 to Figure 33). Inductors in a small 1212
or 1210 size are listed in Table 19 with a 47 μH value and a 0.41 A
current rating to handle the majority of applications below a
400 mA load, and with a 100 μH value and a 0.34 A current
rating to handle a load up to 300 mA.
Recommended Schottky diodes have low forward voltage to
reduce losses and high reverse voltage of up to 40 V to withstand
the peak voltages available in the doubling circuits shown in
Figure 39 and Figure 40.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Figure 41 shows the recommended PCB layout for the
ADuM347x. Note that the total lead length between the ends
of the low ESR capacitor and the VDDx and GNDx pins must not
exceed 2 mm. Installing a bypass capacitor with traces more
than 2 mm in length can result in data corruption.
VREG
GND2
NC
FB
VIA/VOA
VIB/VOB
VIB/VOB
VIC/VOC
VIC/VOC
VID/VOD
VID/VOD
VDDA
OC
GND1
GND2
The ADuM347x parts consist of two internal die attached to a
split lead frame with two die attach paddles. For the purposes
of thermal analysis, the die are treated as a thermal unit, with
the highest junction temperature reflected in the θJA value from
Table 5. The value of θJA is based on measurements taken with
the parts mounted on a JEDEC standard, 4-layer board with
fine width traces and still air.
Under normal operating conditions, the ADuM347x devices
operate at full load across the full temperature range without
derating the output current. However, following the recommendations in the Printed Circuit Board (PCB) Layout section
decreases thermal resistance to the PCB, allowing increased
thermal margins at high ambient temperatures.
PROPAGATION DELAY-RELATED PARAMETERS
09369-025
VIA/VOA
THERMAL ANALYSIS
The ADuM347x devices have a thermal shutdown circuit
that shuts down the dc-to-dc converter and the outputs of the
ADuM347x when a die temperature of approximately 160°C
is reached. When the die cools below approximately 140°C, the
ADuM347x dc-to-dc converter and outputs turn on again.
VDD2
X2
The board layout in Figure 41 shows enlarged pads for Pin 2
and Pin 10 (GND1) on Side 1 and Pin 11 and Pin 19 (GND2)
on Side 2. Large diameter vias should be implemented from the
pad to the ground planes and power planes to increase thermal
conductivity and to reduce inductance. Multiple vias in the
thermal pads can significantly reduce temperatures inside the
chip. The dimensions of the expanded pads are left to the discretion of the designer and depend on the available board space.
Figure 41. Recommended PCB Layout
In applications that involve high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between pins
that exceed the absolute maximum ratings specified in Table 10,
thereby leading to latch-up and/or permanent damage.
The ADuM3470/ADuM3471/ADuM3472/ADuM3473/
ADuM3474 are power devices that dissipate approximately 1 W
of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation device,
the devices primarily depend on heat dissipation into the PCB
through the GNDx pins. If the devices are used at high ambient
temperatures, provide a thermal path from the GNDx pins to the
PCB ground plane.
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a component (see Figure 42). The propagation delay to a logic low output
can differ from the propagation delay to a logic high output.
INPUT (VIx)
50%
tPLH
OUTPUT (VOx)
tPHL
50%
09369-018
X1
GND1
Data Sheet
Figure 42. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM347x component.
Propagation delay skew refers to the maximum amount that the
propagation delay differs between multiple ADuM347x components operating under the same conditions.
Rev. B | Page 28 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1 µs, periodic sets of
refresh pulses indicative of the correct input state are sent to ensure
dc correctness at the output. If the decoder receives no internal
pulses for more than approximately 5 µs, the input side is assumed
to be unpowered or nonfunctional, and the isolator output is forced
to a default state by the watchdog timer circuit (see Table 17).
This situation should occur in the ADuM347x devices only
during power-up and power-down operations.
The limitation on the magnetic field immunity of the ADuM347x
is set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur.
The 3.3 V operating condition of the ADuM347x is examined
because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude of >1.0 V.
The decoder has a sensing threshold of approximately 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ πrn2; n = 1, 2, …, N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM347x transformers. Figure 44 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 44, the ADuM347x is extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example, a 0.5 kA current must be placed 5 mm away
from the ADuM347x to affect the operation of the component.
1k
DISTANCE = 5mm
0.1
10k
100k
1M
10M
100M
Figure 44. Maximum Allowable Current
for Various Current-to-ADuM347x Spacings
At combinations of strong magnetic field and high frequency, any
loops formed by PCB traces can induce error voltages sufficiently
large to trigger the thresholds of succeeding circuitry. Care should
be taken in the layout of such traces to avoid this possibility.
1
0.1
09369-019
0.01
100M
DISTANCE = 100mm
1
MAGNETIC FIELD FREQUENCY (Hz)
10
10k
100k
10M
1M
MAGNETIC FIELD FREQUENCY (Hz)
10
1k
100
0.001
1k
DISTANCE = 1m
100
0.01
Given the geometry of the receiving coil in the ADuM347x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 43.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approximately 50% of the sensing threshold and does not cause a faulty
output transition. Similarly, if such an event occurs during a
transmitted pulse (and is of the worst-case polarity), it reduces
the received pulse from >1.0 V to 0.75 V—still well above the
0.5 V sensing threshold of the decoder.
09369-020
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
MAXIMUM ALLOWABLE CURRENT (kA)
Data Sheet
Figure 43. Maximum Allowable External Magnetic Flux Density
Rev. B | Page 29 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
POWER CONSUMPTION
The VDD1 power supply provides power to the iCoupler data
channels, as well as to the power converter. For this reason,
the quiescent currents drawn by the power converter and the
primary and secondary I/O channels cannot be determined
separately. All of these quiescent power demands are combined
in the IDD1 (Q) current (see the simplified diagram in Figure 45).
The total IDD1 supply current is equal to the sum of the quiescent
operating current; the dynamic current, IDD1 (D), demanded by
the I/O channels; and any external IISO load.
IDD1 (Q)
IDD1 (D)
IISO
FB
PRIMARY
CONVERTER
SECONDARY
CONTROLLER
IDDP (D)
IISO (D)
Figure 45. Power Consumption Within the ADuM347x
Dynamic I/O current is consumed only when operating a channel
at speeds higher than the refresh rate of fr. The dynamic current
of each channel is determined by its data rate. Figure 18 and
Figure 22 show the current for a channel in the forward direction,
meaning that the input is on the primary side of the part. Figure 19
and Figure 23 show the current for a channel in the reverse direction, meaning that the input is on the secondary side of the part.
Figure 18, Figure 19, Figure 22, and Figure 23 assume a typical
15 pF output load.
The following relationship allows the total IDD1 current to be
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4
(1)
where:
IDD1 is the total supply input current.
IISO is the current drawn by the secondary side external load.
E is the power supply efficiency at the given output load from
Figure 13 or Figure 17 at the VISO and VDD1 condition of interest.
ICHn is the current drawn by a single channel, determined from
Figure 18, Figure 19, Figure 22, or Figure 23, depending on
channel direction.
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of IDD1 and IISO (LOAD).
POWER CONSIDERATIONS
Soft Start Mode and Current-Limit Protection
When the ADuM347x device first receives power from VDD1, it is
in soft start mode, and the output voltage, VISO, is increased
gradually while it is below the start-up threshold. In soft start
mode, the width of the PWM signal is increased gradually by
the primary converter to limit the peak current during VISO
power-up. When the output voltage is larger than the start-up
threshold, the PWM signal can be transferred from the secondary controller to the primary converter, and the dc-to-dc converter
switches from soft start mode to the normal PWM control mode.
If a short circuit occurs, the push-pull converter shuts down for
approximately 2 ms and then enters soft start mode. If, at the end
of soft start, a short circuit still exists, the process is repeated,
which is called hiccup mode. If the short circuit is cleared, the
ADuM347x device enters normal operation.
SECONDARY
DATA
I/O
4CH
09369-024
PRIMARY
DATA
I/O
4CH
Data Sheet
(2)
where:
IISO (LOAD) is the current available to supply an external secondary
side load.
IISO (MAX) is the maximum external secondary side load current
available at VISO.
IISO (D)n is the dynamic load current drawn from VISO by an
output or input channel, as shown for a single supply in Figure 20
or Figure 21 or for a double supply in Figure 24 or Figure 25.
The ADuM347x devices also have a pulse-by-pulse current
limit, which is active in startup and normal operation. This
current limit protects the primary switches, X1 and X2, from
exceeding approximately 1.2 A peak and also protects the
transformer windings.
Data Channel Power Cycle
The ADuM347x data input channels on the primary side and
the data input channels on the secondary side are protected from
premature operation by UVLO circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive,
and all input channel drivers and refresh circuits are idle. Outputs
are held in a low state to prevent transmission of undefined states
during power-up and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that time,
the data channels are initialized to their default low output state
until they receive data pulses from the secondary side.
The primary side input channels sample the input and send a
pulse to the inactive secondary output. The secondary side
converter begins to accept power from the primary, and the VISO
voltage starts to rise. When the secondary side UVLO is reached,
the secondary side outputs are initialized to their default low state
until data, either a transition or a dc refresh pulse, is received from
the corresponding primary side input. It can take up to 1 μs after
the secondary side is initialized for the state of the output to
correlate with the primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid one propagation delay after the
secondary side becomes active.
Rev. B | Page 30 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. Analog Devices conducts
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM347x devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 11 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases. Treat any crossinsulation voltage waveform that does not conform to Figure 47
or Figure 48 as a bipolar ac waveform, and limit its peak voltage
to the 50-year lifetime voltage value listed in Table 11.
The voltage presented in Figure 48 is shown as sinusoidal for
illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors
for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest.
The values shown in Table 11 summarize the peak voltages for
50 years of service life in several operating conditions. In many
cases, the working voltage approved by agency testing is higher
than the 50-year service life voltage. Operation at working
voltages higher than the service life voltage listed in Table 11
leads to premature insulation failure.
The insulation lifetime of the ADuM347x depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates, depending on
whether the waveform is bipolar ac, dc, or unipolar ac. Figure 46,
Figure 47, and Figure 48 illustrate these different isolation
voltage waveforms.
Rev. B | Page 31 of 36
RATED PEAK VOLTAGE
09369-021
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side until either the UVLO level is
reached and the outputs are placed in their default low state,
or the outputs detect a lack of activity from the inputs and the
outputs are set to their default value before the secondary power
reaches UVLO.
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines the
maximum working voltage recommended by Analog Devices.
0V
Figure 46. Bipolar AC Waveform
RATED PEAK VOLTAGE
09369-023
Because the rate of charge of the secondary side is dependent
on the soft start cycle, loading conditions, input voltage, and
output voltage level selected, care should be taken in the design
to allow the converter to stabilize before valid data is required.
0V
Figure 47. DC Waveform
RATED PEAK VOLTAGE
0V
Figure 48. Unipolar AC Waveform
09369-022
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Data Sheet
OUTLINE DIMENSIONS
7.50
7.20
6.90
11
20
5.60
5.30
5.00
1
8.20
7.80
7.40
10
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
COMPLIANT TO JEDEC STANDARDS MO-150-AE
Figure 49. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
Rev. B | Page 32 of 36
0.95
0.75
0.55
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ORDERING GUIDE
Model 1, 2, 3
ADuM3470ARSZ
ADuM3470CRSZ
ADuM3470WARSZ
ADuM3470WCRSZ
ADuM3471ARSZ
ADuM3471CRSZ
ADuM3471WARSZ
ADuM3471WCRSZ
ADuM3472ARSZ
ADuM3472CRSZ
ADuM3472WARSZ
ADuM3472WCRSZ
ADuM3473ARSZ
ADuM3473CRSZ
ADuM3473WARSZ
ADuM3473WCRSZ
ADuM3474ARSZ
ADuM3474CRSZ
ADuM3474WARSZ
ADuM3474WCRSZ
Number
of Inputs,
VDD1 Side
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
Number
of Inputs,
VISO Side
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
Maximum
Data Rate
(Mbps)
1
25
1
25
1
25
1
25
1
25
1
25
1
25
1
25
1
25
1
25
Maximum
Propagation
Delay, 5 V (ns)
100
60
100
60
100
60
100
60
100
60
100
60
100
60
100
60
100
60
100
60
Maximum
Pulse Width
Distortion (ns)
40
8
40
8
40
8
40
8
40
8
40
8
40
8
40
8
40
8
40
8
Temperature
Range (°C)
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
Package
Description
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
20-Lead SSOP
Package
Option
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
RS-20
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
3
Tape and reel are available. The addition of an RL7 suffix designates a 7” (500 units) tape and reel option.
1
2
AUTOMOTIVE PRODUCTS
The ADuM3470W, ADuM3471W, ADuM3472W, ADuM3473W, and ADuM3474W models are available with controlled manufacturing
to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications
that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the
automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative
for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. B | Page 33 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
NOTES
Rev. B | Page 34 of 36
Data Sheet
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
NOTES
Rev. B | Page 35 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
NOTES
©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09369-0-5/14(B)
Rev. B | Page 36 of 36
Data Sheet
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