advertisement
STM32F405xx
STM32F407xx
ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB
OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Datasheet
-
production data
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
WLCSP90
FBGA
UFBGA176
(10 × 10 mm)
Features
• Core: ARM 32-bit Cortex™-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
– Up to 1 Mbyte of Flash memory
– Up to 192+4 Kbytes of SRAM including 64-
Kbyte of CCM (core coupled memory) data
RAM
– Flexible static memory controller supporting Compact Flash, SRAM,
PSRAM, NOR and NAND memories
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 1.8 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1% accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low power
– Sleep, Stop and Standby modes
– V
BAT
supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
• Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M4 Embedded Trace Macrocell™
• Up to 140 I/O ports with interrupt capability
– Up to 136 fast I/Os up to 84 MHz
– Up to 138 5 V-tolerant I/Os
• Up to 15 communication interfaces
– Up to 3 × I
2
C interfaces (SMBus/PMBus)
– Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO
7816 interface, LIN, IrDA, modem control)
– Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I
2
S to achieve audio class accuracy via internal audio PLL or external clock
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller with on-chip PHY
– USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface up to
54 Mbytes/s
• True random number generator
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar
Reference
Table 1. Device summary
Part number
STM32F405xx
STM32F407xx
STM32F405RG, STM32F405VG, STM32F405ZG,
STM32F405OG, STM32F405OE
STM32F407VG, STM32F407IG, STM32F407ZG,
STM32F407VE, STM32F407ZE, STM32F407IE
June 2013
This is information on a product in full production.
DocID022152 Rev 4 1/185
www.st.com
1
1
2
Contents
Contents
STM32F405xx, STM32F407xx
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15
®
Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 19
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 19
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 22
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 22
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 28
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Universal synchronous/asynchronous receiver transmitters (USART) . 33
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 35
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/185 DocID022152 Rev 4
3
4
5
STM32F405xx, STM32F407xx Contents
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 37
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 38
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up / power-down (regulator ON) . . . . . . 80
Operating conditions at power-up / power-down (regulator OFF) . . . . . 80
Embedded reset and power control block characteristics . . . . . . . . . . . 80
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 102
DocID022152 Rev 4 3/185
Contents STM32F405xx, STM32F407xx
6
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 155
SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 156
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 171
USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 173
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
List of tables
List of tables
STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 83
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Typical and maximum current consumptions in V
BAT
mode. . . . . . . . . . . . . . . . . . . . . . . . 89
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash memory programming with V
PP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
DocID022152 Rev 4 5/185
List of tables STM32F405xx, STM32F407xx
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PCLK1
= 42 MHz.,V
DD
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 138
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 139
Switching characteristics for PC Card/CF read and write cycles
Switching characteristics for PC Card/CF read and write cycles
WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 159
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 160
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 162
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 164
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 167
6/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx List of tables
DocID022152 Rev 4 7/185
List of figures
List of figures
STM32F405xx, STM32F407xx
Compatible board design between STM32F10xx/STM32F4xx for LQFP64 . . . . . . . . . . . . 15
Compatible board design between STM32F2xx and STM32F4xx
Startup in regulator OFF mode: slow V
slope
- power-down reset risen after V
CAP_1
/V
CAP_2
Startup in regulator OFF mode: fast V
- power-down reset risen before V
CAP_1
slope
/V stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27
CAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 89
current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 90
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx List of figures
I2S master timing diagram (Philips protocol)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Power supply and reference decoupling (V
REF+
Power supply and reference decoupling (V
REF+ not connected to V
DDA connected to V
DDA
). . . . . . . . . . . . . 133
). . . . . . . . . . . . . . . . 133
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 139
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 140
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 141
PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 148
PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 148
PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 150
PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 151
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 154
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 154
WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . 159
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 160
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 162
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 164
LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 167
DocID022152 Rev 4 9/185
List of figures STM32F405xx, STM32F407xx
USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 172
10/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
1 Introduction
Introduction
This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to
Section 2.1: Full compatibility throughout the family
The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the
STM32F4xx reference manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming manual (PM0214) available from www.st.com.
DocID022152 Rev 4 11/185
Description
2 Description
STM32F405xx, STM32F407xx
The STM32F405xx and STM32F407xx family is based on the high-performance ARM
®
Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The
Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document.
The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces.
•
Up to three I
2
Cs
• Three SPIs, two I
2
Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
•
Four USARTs plus two UARTs
• An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
•
Two CANs
• An SDIO/MMC interface
•
Ethernet and the camera interface available on STM32F407xx devices only.
New advanced peripherals include an SDIO, an enhanced flexible static memory control
(FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to
Table 2: STM32F405xx and STM32F407xx: features and peripheral counts
for the list of peripherals available on each part number.
The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to
Section : Internal reset OFF
. A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.
These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications:
• Motor drive and application control
•
Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
• Alarm systems, video intercom, and HVAC
•
Home audio appliances
12/185 DocID022152 Rev 4
shows the general block diagram of the device family.
Peripherals
Flash memory in
Kbytes
SRAM in
Kbytes
System
Backup
FSMC memory controller
Ethernet
Generalpurpose
Advanced
-control
Timers
Basic
IWDG
WWDG
RTC
Random number generator
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts
STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix
No
1024
No
192(112+16+64)
4
10
2
2
Yes
Yes
Yes
Yes
512
Yes
(1)
512 1024 512 1024 512 1024
Yes
Peripherals
Communi cation interfaces
SPI / I2S
I
2
C
USART/
UART
USB
OTG FS
USB
OTG HS
CAN
SDIO
Camera interface
GPIOs
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts
STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix
3/2 (full duplex)
(2)
3
51 72
No
82 114
4/2
Yes
Yes
2
Yes
72 82
Yes
114 140
12-bit ADC
Number of channels
16 13 16 24
3
13 16 24 24
12-bit DAC
Number of channels
Maximum CPU frequency
Operating voltage
Yes
2
168 MHz
Operating temperatures
1.8 to 3.6 V
(3)
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 LQFP144
UFBGA176
LQFP176
1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip
Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I
2
S audio mode.
3. V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF
).
STM32F405xx, STM32F407xx Description
The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle.
The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The
STM32F405xx and STM32F407xx, however, are not drop-in replacements for the
STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted.
,
give compatible board designs between the
STM32F40x, STM32F2xxx, and STM32F10xxx families.
Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64
49
48
47
64
1
VSS
VSS
33
32
31
16
17
VSS
VSS
0
Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the
STM32F4xx configuration ai18489
DocID022152 Rev 4 15/185
Description STM32F405xx, STM32F407xx
Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package
76
75
73
VSS
51
50
49
100
99 (VSS)
1
19 20
25
26
VSS
0
Ω resistor or soldering bridge present for the STM32F10xxx
VDD
VSS
Two 0
Ω resistors connected to:
- VSS for the STM32F10xx
- VSS for the STM32F4xx
VDD
- VSS, VDD or NC for the STM32F2xx
VSS
VSS
VSS for STM32F10xx
VDD for STM32F4xx
VSS configuration, not present in the
STM32F4xx configuration ai18488c
Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
109
108
106
V
SS
73
72
71
V
SS
Signal from external power supply supervisor
144
143 (PDR_ON)
30 31
37
V
SS
0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the
STM32F4xx configuration
1 36
V
SS
V
DD
V
SS
Two 0 Ω resistors connected to:
- V
SS
for the STM32F10xx
V
DD
V
SS
V
SS
for STM32F10xx
V
DD
for STM32F4xx
- V
SS
, V
DD
or NC for the STM32F2xx
- V
DD
or signal from external power supply supervisor for the STM32F4xx ai18487d
16/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
Figure 4. Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 and BGA176 packages
133
132 89
88
Signal from external power supply supervisor
176
171 (PDR_ON)
1 44
45
V
DD
V
SS
Two 0 Ω resistors connected to:
- V
SS
, V
DD
or NC for the STM32F2xx
- V
DD
or signal from external power supply supervisor for the STM32F4xx
MS19919V3
DocID022152 Rev 4 17/185
Description STM32F405xx, STM32F407xx
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
TRACECLK
TRACED[3:0]
MII or RMII as AF
MDIO as AF
DP, DM
ULPI:CK, D[7:0], DIR, STP, NXT
ID, VBUS, SOF
140 AF
D[7:0]
CMD, CK as AF
4 compl. channels (TIM1_CH1[1:4]N,
4 channels (TIM1_CH1[1:4]ETR,
BKIN as AF
4 compl. channels (TIM1_CH1[1:4]N,
4 channels (TIM1_CH1[1:4]ETR,
BKIN as AF
2 channels as AF
1 channel as AF
1 channel as AF
RX, TX, CK,
CTS, RTS as AF
RX, TX, CK,
CTS, RTS as AF
MOSI, MISO,
SCK, NSS as AF
VDDREF_ADC
8 analog inputs common to the 3 ADCs
8 analog inputs common to the ADC1 & 2
8 analog inputs for ADC3
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[15:0]
PI[11:0]
CCM data RAM 64 KB
JTAG & SW
ETM
MPU
NVIC
D-BUS
ARM Cortex-M4
168 MHz
FPU
I-BUS
S-BUS
Ethernet MAC
10/100
USB
OTG HS
DMA/
FIFO
DMA/
FIFO
DMA2
DMA1
8 Streams
FIFO
8 Streams
FIFO
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
GPIO PORT I
EXT IT. WKUP
SDIO / MMC
Figure 5. STM32F40x block diagram
TIM1 / PWM
16b
TIM8 / PWM
16b
TIM9
TIM10
16b
16b
TIM11 smcard irDA smcard irDA
USART1
USART6
SPI1
@V
DDA
Temperature sensor
ADC1
ADC2
ADC3
IF
16b
AHB3
External memory controller (FSMC)
SRAM, PSRAM, NOR Flash,
PC Card (ATA), NAND Flash
DMA2
Flash up to
1 MB
SRAM 112 KB
SRAM 16 KB
AHB2 168 MHz
AHB1 168 MHz
Reset & control
AHB/APB2 AHB/APB1
WWDG
TIM6
TIM7
@V
DDA
DAC1
DAC2
DMA1
16b
16b
ITF
@V
DDA
RC HS
RC L S
P L L1&2
RNG
Camera interface
USB
OTG FS
VDD
POR reset
Int
Power managmt
Voltage regulator
3.3 to 1.2 V
@V
DD
Supply supervision
POR/PDR
BOR
PVD
@V
DD
@V
DDA
XTAL OSC
4- 16MHz
IWDG
PWR interface
@V
BAT
XTAL 32 kHz
RTC
AWU
Backup register
4 KB BKPSRAM
TIM2
TIM3
TIM4
TIM5
32b
16b
16b
32b
TIM12
TIM13
16b
16b
TIM14
16b
USART2
USART3 smcard irDA smcard irDA
UART4
UART5
SP2/I2S2
SP3/I2S3
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS bxCAN1 bxCAN2
CLK, NE [3:0], A[23:0],
D[31:0], OEN, WEN,
NBL[3:0], NL, NREG,
NWAIT/IORDY, CD
NIORD, IOWR, INT[2:3]
INTN, NIIS16 as AF
HSYNC, VSYNC
PUIXCLK, D[13:0]
DP
DM
ID, VBUS, SOF
VDD = 1.8 to 3.6 V
VSS
VCAP1, VCPA2
VDDA, VSSA
NRST
OSC_IN
OSC_OUT
VBAT = 1.65 to 3.6 V
OSC32_IN
OSC32_OUT
RTC_AF1
RTC_AF1
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels
2 channels as AF
1 channel as AF
1 channel as AF
RX, TX as AF
CTS, RTS as AF
RX, TX as AF
CTS, RTS as AF
RX, TX as AF
RX, TX as AF
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
MOSI/SD, MISO/SD_ext, SCK/CK
NSS/WS, MCK as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
TX, RX
TX, RX
DAC1_OUT as AF
DAC2_OUT as AF
MS19920V3
1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2. The camera interface and ethernet are available only on STM32F407xx devices.
18/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
2.2.1 ARM
®
Cortex™-M4F core with embedded Flash and SRAM
Note:
The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.
The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software.
shows the general block diagram of the STM32F40x family.
Cortex-M4F is binary compatible with Cortex-M3.
2.2.3
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM
®
Cortex™-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz.
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data.
DocID022152 Rev 4 19/185
Description
2.2.5
STM32F405xx, STM32F407xx
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.
2.2.7
All STM32F40x products embed:
•
Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
•
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or V
BAT mode.
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
20/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
64-Kbyte
CCM data RAM
ARM
Cortex-M4
Figure 6. Multi-AHB matrix
GP
DMA1
GP
DMA2
MAC
Ethernet
USB OTG
HS
Description
2.2.8
S0 S1 S2 S3 S4 S5 S6 S7
M0
ICODE
M1
DCODE
M2
M3
M4
M5
M6
Flash memory
SRAM1
112 Kbyte
SRAM2
16 Kbyte
AHB1 peripherals
AHB2 peripherals
FSMC
Static MemCtl
Bus matrix-S
APB1
APB2 ai18490c
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.
The DMA can be used with the main peripherals:
•
SPI and I
2
S
•
I
2
C
•
USART
•
General-purpose, basic and advanced-control timers TIMx
•
DAC
•
SDIO
•
Camera interface (DCMI)
•
ADC.
DocID022152 Rev 4 21/185
Description STM32F405xx, STM32F407xx
2.2.9 Flexible static memory controller (FSMC)
The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip
Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM,
NOR Flash and NAND Flash.
Functionality overview:
•
Write FIFO
•
Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.
2.2.10 Nested vectored interrupt controller (NVIC)
The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M4F.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt latency.
The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines.
2.2.12 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL
22/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
clock entry is available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is
84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I
2
S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.
At startup, boot pins are used to select one out of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
2.2.14 Power supply schemes
Note:
•
V
DD
= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V
DD
pins.
• V
SSA
, V
DDA
= 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
•
V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V
DD
is not present.
Figure 21: Power supply scheme
V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF ).
in order to identify the packages supporting this option.
2.2.15 Power supply supervisor
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V
DD threshold, V
POR/PDR
or V
BOR
is below a specified
, without the need for an external reset circuit.
DocID022152 Rev 4 23/185
Description STM32F405xx, STM32F407xx
The device also features an embedded programmable voltage detector (PVD) that monitors the V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold. An interrupt can be generated when V higher than the V
DD
PVD
/V
DDA
drops below the V
PVD
threshold and/or when V
DD
/V
DDA
threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
is
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin.
An external power supply supervisor should monitor V
DD reset mode as long as V
DD
and should maintain the device in
is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to
Figure 7: Power supply supervisor interconnection with internal reset OFF
.
Figure 7. Power supply supervisor interconnection with internal reset OFF
V
DD
External V
DD
power supply supervisor
Ext. reset controller active when
V
DD
< 1.7 V or 1.8 V
(1)
PDR_ON
NRST
Application reset signal (optional)
V
DD
MS31383V3
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.
The V
DD
specified threshold, below which the device must be maintained under reset, is
). This supply voltage can drop to 1.7 V when the device operates in the
0 to 70 °C temperature range.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•
The brownout reset (BOR) circuitry is disabled
• The embedded programmable voltage detector (PVD) is disabled
•
V
BAT
functionality is no more available and V
BAT
pin should be connected to V
DD
All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal.
24/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Figure 8. PDR_ON and NRST control with internal reset OFF
V DD
Description
PDR = 1.7 V or 1.8 V
(1) time
Reset by other source than power supply supervisor
NRST
PDR_ON PDR_ON time
MS19009V6
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.
The regulator has four operating modes:
•
Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
•
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when regulator is ON:
•
MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.
Table 14: General operating conditions
.
•
LPR is used in the Stop modes
The LP regulator mode is configured by software when entering Stop mode.
•
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost)
DocID022152 Rev 4 25/185
Description STM32F405xx, STM32F407xx
Two external ceramic capacitors should be connected on V
CAP_1
& V
CAP_2
pin. Refer to
Figure 21: Power supply scheme
and
Figure 16: VCAP_1/VCAP_2 operating conditions
All packages have regulator ON feature.
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V
12
voltage source through V
CAP_1
and V
CAP_2
pins.
Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targetted maximum frequency. Refer to
Table 14: General operating conditions
.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors.
Figure 21: Power supply scheme
When the regulator is OFF, there is no more internal monitoring on V
12 supply supervisor should be used to monitor the V
12
. An external power
of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V
12 power domain.
In regulator OFF mode the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V
12 domain which is not reset by the NRST pin.
logic power
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.
Figure 9. Regulator OFF
V
12
External V
CAP_1/2
power supply supervisor
Ext. reset controller active when V
CAP_1/2
< Min V
12
Application reset signal (optional)
V
DD
V
12
PA0
V
DD
NRST
BYPASS_REG
V
CAP_1
V
CAP_2 ai18498V4
26/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Note:
Description
The following conditions must be respected:
•
V
DD
should always be higher than V between power domains.
CAP_1
and V
CAP_2 to avoid current injection
•
If the time for V
CAP_1
and V and V
CAP_2 reach V
12
CAP_2 to reach V
12 minimum value is faster than the time for
V
DD
to reach 1.8 V, then PA0 should be kept low to cover both conditions: until V
CAP_1
minimum value and until V
DD reaches 1.8 V (see
).
•
Otherwise, if the time for V
CAP_1 than the time for V
DD
).
and V
CAP_2 to reach V
12
minimum value is slower
to reach 1.8 V, then PA0 could be asserted low externally (see
•
If V
CAP_1
and V
CAP_2
go below V
12
minimum value and V a reset must be asserted on PA0 pin.
DD
is higher than 1.8 V, then
The minimum value of V
12
depends on the maximum frequency targeted in the application
(see Table 14: General operating conditions
).
Figure 10. Startup in regulator OFF mode: slow V
- power-down reset risen after V
CAP_1
/V
CAP_2
DD
slope stabilization
V
DD
PDR = 1.7 V or 1.8 V
(2)
V
12
Min V
12
V
CAP_1
/V
CAP_2 time
NRST
1. This figure is valid both whatever the internal reset mode (onON or OFFoff).
2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.
time ai18491e
DocID022152 Rev 4 27/185
Description STM32F405xx, STM32F407xx
Figure 11. Startup in regulator OFF mode: fast V
DD
- power-down reset risen before V
CAP_1
/V
CAP_2
slope stabilization
V
DD
PDR = 1.7 V or 1.8 V
(2)
V
12
Min V
12
V
CAP_1
/V
CAP_2 time
NRST
PA0 asserted externally time ai18492d
1. This figure is valid both whatever the internal reset mode (onON or offOFF).
2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges.
2.2.17 Regulator ON/OFF and internal reset ON/OFF availability
LQFP64
LQFP100
LQFP144
LQFP176
Table 3. Regulator ON/OFF and internal reset ON/OFF availability
Regulator ON Regulator OFF Internal reset ON
Internal reset
OFF
Yes No
Yes No
WLCSP90
UFBGA176
Yes
BYPASS_REG set to V
SS
Yes
BYPASS_REG set to V
DD
Yes
PDR_ON set to
V
DD
Yes
PDR_ON connected to an external power supply supervisor
28/185
The backup domain of the STM32F405xx and STM32F407xx includes:
•
The real-time clock (RTC)
• 4 Kbytes of backup SRAM
•
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in V
BAT
and standby mode. This memory area is disabled by default to minimize power consumption (see
Section 2.2.19: Low-power modes
). It can be enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data when V
DD
power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see
Section 2.2.19: Low-power modes
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the V
DD
supply when present or from the V
BAT
pin.
The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the V
12
domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V
12
domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
DocID022152 Rev 4 29/185
Description STM32F405xx, STM32F407xx
Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed and the V
12
domain is controlled by an external power.
2.2.20 V
BAT
operation
Note:
The V
BAT
pin allows to power the device V supercapacitor, or from V present.
DD
BAT
domain from an external battery, an external when no external battery and an external supercapacitor are
V
BAT
operation is activated when V
DD
is not present.
The V
BAT
pin supplies the RTC, the backup registers and the backup SRAM.
When the microcontroller is supplied from V
BAT do not exit it from V
BAT
operation.
, external interrupts and RTC alarm/events
When PDR_ON pin is not connected to V
DD more available and V
BAT
(internal reset OFF), the V
pin should be connected to V
DD
.
BAT
functionality is no
2.2.21 Timers and watchdogs
The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.
All timer counters can be frozen in debug mode.
compares the features of the advanced-control, general-purpose and basic timers.
Timer type
Timer
Table 4. Timer feature comparison
Counter resolutio n
Counter type
Prescaler factor
DMA request generatio n
Capture/ compare channels
Complementar y output
Max interface clock
(MHz)
Max timer clock
(MHz)
Advanced
-control
TIM1,
TIM8
16-bit
Up,
Down,
Up/dow n
Any integer between 1 and 65536
Yes 4 Yes 84 168
30/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
Timer type
General purpose
Basic
Timer
TIM2,
TIM5
TIM3,
TIM4
TIM9
TIM10
,
TIM11
TIM12
TIM13
,
TIM14
TIM6,
TIM7
Counter resolutio n
Table 4. Timer feature comparison (continued)
Counter type
Prescaler factor
DMA request generatio n
Capture/ compare channels
Complementar y output
Max interface clock
(MHz)
Max timer clock
(MHz)
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Up,
Down,
Up/dow n
Up,
Down,
Up/dow n
Any integer between 1 and 65536
Any integer between 1 and 65536
Up
Up
Up
Up
Up
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Yes
Yes
No
No
No
No
Yes
4
4
2
1
2
1
0
No
No
No
No
No
No
No
42
42
84
84
42
42
42
84
84
168
168
84
84
84
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
• Output compare
•
PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
DocID022152 Rev 4 31/185
Description STM32F405xx, STM32F407xx
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F40x devices
•
TIM2, TIM3, TIM4, TIM5
The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
32/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:
•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
2.2.22 Inter-integrated circuit interface (I²C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz) . They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware
CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.
DocID022152 Rev 4 33/185
Description STM32F405xx, STM32F407xx
USART name
Standard features
Modem
(RTS/
CTS)
LIN
Table 5. USART feature comparison
SPI master irDA
Smartcard
(ISO 7816)
Max. baud rate in Mbit/s
(oversampling by 16)
Max. baud rate in Mbit/s
(oversampling by 8)
APB mapping
USART1
USART2
USART3
UART4
UART5
USART6
X
X
X
X
X
X
X
X
X
-
-
X
X
X
X
X
X
X
X
X
X
-
-
X
X
X
X
X
X
X
X
X
X
-
-
X
5.25
2.62
2.62
2.62
2.62
5.25
10.5
5.25
5.25
5.25
5.25
10.5
APB2
(max.
84 MHz)
APB1
(max.
42 MHz)
APB1
(max.
42 MHz)
APB1
(max.
42 MHz)
APB1
(max.
42 MHz)
APB2
(max.
84 MHz)
2.2.24 Serial peripheral interface (SPI)
The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.
Two standard I
2
S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I
2
S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.
All I
2
Sx can be served by the DMA controller.
2.2.26 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I
2
S application. It allows to achieve error-free I
2
S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.
34/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
The PLLI2S configuration can be modified to manage an I
2
S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I
2
S flow with an external PLL (or Codec output).
2.2.27 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.
Peripheral available only on the STM32F407xx devices.
The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The
STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz
(MII) from the STM32F407xx.
The STM32F407xx includes the following features:
•
Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40x reference manual for details)
•
Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and group addresses)
• 32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
DocID022152 Rev 4 35/185
Description STM32F405xx, STM32F407xx
2.2.29 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the
USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:
•
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
4 bidirectional endpoints
•
8 host channels with periodic OUT support
•
HNP/SNP/IP inside (no need for any external resistor)
•
For OTG/Host modes, a power switch is needed in case bus-powered devices are connected
36/185
The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to
480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 6 bidirectional endpoints
•
12 host channels with periodic OUT support
• Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.
• Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
• for OTG/Host modes, a power switch is needed in case bus-powered devices are connected
DocID022152 Rev 4
STM32F405xx, STM32F407xx Description
The camera interface is not available in STM32F405xx devices.
STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports continuous mode or snapshot (a single frame) mode
•
Capability to automatically crop the image
2.2.33 Random number generator (RNG)
All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.
Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally
DocID022152 Rev 4 37/185
Description STM32F405xx, STM32F407xx
connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.
As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
• external triggers for conversion
• input voltage reference V
REF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F40x through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
38/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
3 Pinouts and pin description
Pinouts and pin description
Figure 12. STM32F40x LQFP64 pinout
VBAT
PC13
PC14
PC15
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0_WKUP
PA1
PA2
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3 46
4
45
5
44
6
43
7
42
8
41
9
LQFP64
40
10
39
11
38
12
37
13
36
14
35
15
34
16
17 18 19 20 21 22 23 24 25 26 27 28
33
29 30 31 32
VDD
VCAP_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12 ai18493b
DocID022152 Rev 4 39/185
Pinouts and pin description STM32F405xx, STM32F407xx
Figure 13. STM32F40x LQFP100 pinout
VDD
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14
PC15
VSS
15
16
17
18
19
20
21
22
23
24
25
9
10
11
12
13
14
6
7
4
5
8
1
2
3
LQFP100
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VSS
VCAP_2
PA13
PA12
PA 11
PA10
PA9
PA8
61
60
59
58
57
56
55
54
53
52
51
67
66
65
64
63
62
75
74
73
72
71
70
69
68 ai18495c
40/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Figure 14. STM32F40x LQFP144 pinout
Pinouts and pin description
18
19
20
21
22
12
13
14
15
16
17
6
7
8
9
10
11
3
4
5
1
2
32
33
34
35
36
23
24
25
26
27
28
29
30
31
V
SS
V
DD
PF6
PF7
PF8
PF9
PF10
PF0
PF1
PF2
PF3
PF4
PF5
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14
PC15
PH0
PH1
NRST
PC0
PC1
PC2
PC3
V
DD
V
SSA
V
REF+
V
DDA
PA0
PA1
PA2
LQFP144
91
90
89
88
87
97
96
95
94
93
92
86
85
84
108
107
106
105
104
103
102
101
100
99
98
77
76
75
74
73
83
82
81
80
79
78
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PG4
PG3
PG2
PD15
PD14
V
DD
V
SS
PD13
V
DD
V
SS
V
CAP_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
V
DD
V
SS
PG8
PG7
PG6
PG5 ai18496b
DocID022152 Rev 4 41/185
Pinouts and pin description
Figure 15. STM32F40x LQFP176 pinout
STM32F405xx, STM32F407xx
14
15
16
17
18
19
9
10
11
12
13
20
21
22
23
24
6
7
4
5
8
1
2
3
36
37
38
39
40
31
32
33
34
35
41
42
43
44
25
26
27
28
29
30
V
SS
V
DD
PF0
PF1
PF2
PF3
PF4
PF5
V
SS
V
DD
PF6
PE2
PE3
PE4
PE5
PE6
V
BAT
PI8
PC13
PC14
PC15
PI9
PI10
PI11
PF7
PF8
PF9
PF10
PH0
PH1
NRST
PC0
PC1
PC2
PC3
V
DDA
V
SSA
V
REF+
V
DDA
PA0
PA1
PA2
PH2
PH3
LQFP176
101
100
99
98
97
96
95
94
93
92
91
90
89
PG3
PG2
PD15
PD14
V
DD
V
SS
PD13
PD12
PD11
PD10
PD9
PC9
PC8
PC7
PC6
V
DD
V
SS
PG8
PG7
PG6
PG5
PG4
PI1
PI0
PH15
PH14
PH13
V
DD
V
SS
V
CAP_2
PA13
PA12
PA11
PA10
PA9
PA8
PD8
PB15
PB14
PB13
PB12
V
DD
V
SS
PH12
117
116
115
114
113
112
123
122
121
120
119
118
111
110
109
108
132
131
130
129
128
127
126
125
124
107
106
105
104
MS19916V3
42/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Pinouts and pin description
1
K
L
M
G
H
J
N
P
R
C
D
E
F
A
B
PC15
PH0
PH1
NRST
PF7
PF10
VSSA
VREF-
VREF+
VDDA
PE3
PE4
VBAT
PC13
PC14
4
Figure 16. STM32F40x UFBGA176 ballout
5 6 7 8 9 10 11 2
PA1
PA2
PA3
PF6
PF9
PC0
PE2
PE5
PI7
PI8
PF0
VSS
PE1
PE6
PI6
PI9
PI10
VDD
VSS
PF2
VDD
PF1
PH3
PH4
PF3 PF4 PH5
PE0
PB9
PI5
PI4
PI11
PH2
PF5
PF8
PC1
VDD
BYPASS_
REG
PC2 PC3
PA0
PA6
PA4
PA5
PC4
PC5
PA7 PB1 PB0
PB8 PB5 PG14
PB7 PB6 PG15
VDD
PDR_ON
VDD
VSS
BOOT0 VSS
VSS
VSS
VSS
VSS
VSS
PB2
PF13
PF12
PF11
PG1
PG0
PF15
PF14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PG13
PG12
VDD
VSS
VSS
VDD
PE8
PE7
VSS
VSS
VSS
VSS
VSS
PB4
PG11
VDD
VSS
VSS
VSS
VSS
VSS
VSS
PB3
PG10
PG9
PD4
VSS
VDD
PE9
PE10
VCAP_1 PH6
VDD
PE11
PE12
PE13
PE14
PE15
PD7
PD6
PD5
PD3
12 13 14 15
PH12
PH11
PH8
VSS
VSS
VDD
PC12
PD0
PD1
PD2
PH13
PA15
PC11
PI3
PH15
PH14
PA14
PC10
VSS VCAP_2 PC9
PI2
PI1
PI0
PH7
PB12
PB10
VDD
VDD
VDD
PG5
PH10
PH9
PD12
PB13
PB11
PC8
PG8
PG7
PG4
PD15
PD14
PD11
PD9
PA13
PA12
PA11
PA10
PA9
PA8
PD10
PD8
PB14 PB15
PC7
PC6
PG6
PG3
PG2
PD13 ai18497b
1. This figure shows the package top view.
DocID022152 Rev 4 43/185
Pinouts and pin description STM32F405xx, STM32F407xx
A
B
C
10
Figure 17. STM32F40x WLCSP90 ballout
9 8 7 6 5 4 3 2
VBAT PC13 PDR_ON BOOT0 PB4
1
PD7 PD4 PC12
PA14
VDD
PC14
PC15 VDD PB7 PB3 PD6 PD2 PA15
PI1
VCAP_2
PA0 VSS PB9 PB6 PD5 PD1 PC11 PI0 PA12 PA11
D PC2
BYPASS_
REG
PB8
PB5 PD0 PC10
PA13
PA10 PA9
E
PA8
PC0
PC3
VSS
VSS VDD VSS VDD PC9 PC8 PC7
F
G
PH0
PH1
PA1
NRST VDDA PA5
VDD PE10 PE14 VCAP_1 PC6 PD14 PD15
PB0 PE7 PE13 PE15 PD10 PD12 PD11
H VSSA PA3 PA6 PB1 PE8 PE12 PB10 PD9 PD8 PB15
J PA2 PA4
PA7
PB2
PE9 PE11 PB11 PB12 PB14
PB13
MS30402V1
Name
Pin name
Pin type
1. This figure shows the package bump view.
I/O structure
Table 6. Legend/abbreviations used in the pinout table
Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
S
I
Supply pin
Input only pin
I/O
FT
TTa
B
RST
Input / output pin
5 V tolerant I/O
3.3 V tolerant I/O directly connected to ADC
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes
Alternate functions
Functions selected through GPIOx_AFR registers
Additional functions
Functions directly selected/enabled through peripheral registers
44/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Pin number
Pinouts and pin description
Table 7. STM32F40x pin and ball definitions
Pin name
(function after reset)
(1)
Alternate functions Additional functions
-
-
-
-
-
-
-
-
-
-
-
1 1 A2 1
2 2 A1 2
3 3 B1 3
4 4 B2 4
5 5 B3 5
1 A10 6
-
6
-
C1
D2
6
7
PE2
PE3
PE4
PE5
PE6
V
BAT
PI8
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
I/O FT
(2)(
3)
TRACECLK/ FSMC_A23 /
ETH_MII_TXD3 /
EVENTOUT
TRACED0/FSMC_A19 /
EVENTOUT
TRACED1/FSMC_A20 /
DCMI_D4/ EVENTOUT
TRACED2 / FSMC_A21 /
TIM9_CH1 / DCMI_D6 /
EVENTOUT
TRACED3 / FSMC_A22 /
TIM9_CH2 / DCMI_D7 /
EVENTOUT
EVENTOUT
2 A9 7 7 D1 8 PC13 I/O FT
(2)
(3)
EVENTOUT
-
-
3 B10 8
-
8 E1 9
4 B9 9 9 F1 10
D3 11
PC14/OSC32_IN
(PC14)
I/O FT
PC15/
OSC32_OUT
(PC15)
PI9
I/O FT
I/O FT
(2)(
3)
(2)(
3)
-
-
-
-
-
-
-
E3
E4
12
13
PI10
PI11
I/O FT
I/O FT
EVENTOUT
EVENTOUT
CAN1_RX / EVENTOUT
ETH_MII_RX_ER /
EVENTOUT
OTG_HS_ULPI_DIR /
EVENTOUT
-
-
-
-
-
F2 14
F3 15
10 E2 16
V
SS
V
DD
PF0
S
S
I/O FT
FSMC_A0 / I2C2_SDA /
EVENTOUT
RTC_TAMP1,
RTC_TAMP2,
RTC_TS
RTC_OUT,
RTC_TAMP1,
RTC_TS
OSC32_IN
(4)
OSC32_OUT
(4)
DocID022152 Rev 4 45/185
Pinouts and pin description STM32F405xx, STM32F407xx
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
-
-
-
-
-
-
-
-
-
-
12 H2 18
13 J2 19
-
-
-
14
15
J3
K3
20
21
C9 10 16 G2 22
B8 11 17 G3 23
-
-
-
-
-
-
-
-
11 H3 17
18 K2 24
19 K1 25
20 L3 26
21
22
5 F10 12 23 G1 29
6 F9 13 24 H1 30
7 G10 14 25 J1 31
8 E10 15 26
9 16 27
L2
L1
M2
M3
27
28
32
33
10 D10 17 28 M4 34
PF1
PF2
PF3
PF4
PF5
V
SS
V
DD
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
(4)
(4)
(4)
FSMC_A1 / I2C2_SCL /
EVENTOUT
FSMC_A2 / I2C2_SMBA /
EVENTOUT
FSMC_A3/EVENTOUT
FSMC_A4/EVENTOUT
FSMC_A5/EVENTOUT
PF6
PF7
PF8
PF9
I/O FT
I/O FT
I/O FT
I/O FT
PF10
PH0/OSC_IN
(PH0)
PH1/OSC_OUT
(PH1)
I/O FT
I/O FT
I/O FT
NRST I/O
RS
T
(4)
(4)
(4)
(4)
(4)
TIM10_CH1 /
FSMC_NIORD/
EVENTOUT
TIM11_CH1/FSMC_NREG
/ EVENTOUT
TIM13_CH1 /
FSMC_NIOWR/
EVENTOUT
TIM14_CH1 / FSMC_CD/
EVENTOUT
FSMC_INTR/ EVENTOUT
EVENTOUT
EVENTOUT
PC0
PC1
PC2
I/O FT
I/O FT
I/O FT
(4)
(4)
(4)
OTG_HS_ULPI_STP/
EVENTOUT
ETH_MDC/ EVENTOUT
SPI2_MISO /
OTG_HS_ULPI_DIR /
ETH_MII_TXD2
/I2S2ext_SD/ EVENTOUT
ADC3_IN9
ADC3_IN14
ADC3_IN15
ADC3_IN4
ADC3_IN5
ADC3_IN6
ADC3_IN7
ADC3_IN8
OSC_IN
OSC_OUT
(4)
(4)
ADC123_IN10
ADC123_IN11
ADC123_IN12
46/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Pinouts and pin description
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
11
-
E9 18 29
19 30
M5
G3
35
36
12 H10 20 31 M1 37
N1 -
13 G9 22 33
14 C10 23 34
R1
N3
39
40
15 F8 24 35 N2 41
16 J10 25 36 P2 42
-
-
-
-
-
-
-
-
-
21 32 P1 38
-
-
-
-
-
-
-
-
F4
G4
H4
J4
43
44
45
46
PC3
V
V
V
REF
–
V
REF+
V
DD
SSA
DDA
PA0/WKUP
(PA0)
PA1
PA2
PH2
PH3
PH4
PH5
I/O FT
(4)
SPI2_MOSI / I2S2_SD /
OTG_HS_ULPI_NXT /
ETH_MII_TX_CLK/
EVENTOUT
ADC123_IN13
S
S
S
S
S
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
(5)
(4)
(4)
USART2_CTS/
UART4_TX/
ETH_MII_CRS /
TIM2_CH1_ETR/
TIM5_CH1 / TIM8_ETR/
EVENTOUT
USART2_RTS /
UART4_RX/
ETH_RMII_REF_CLK /
ETH_MII_RX_CLK /
TIM5_CH2 / TIM2_CH2/
EVENTOUT
USART2_TX/TIM5_CH3 /
TIM9_CH1 / TIM2_CH3 /
ETH_MDIO/ EVENTOUT
ETH_MII_CRS/EVENTOU
T
ADC123_IN0/WKUP
(4
)
ADC123_IN1
ADC123_IN2
ETH_MII_COL/EVENTOU
T
I2C2_SCL /
OTG_HS_ULPI_NXT/
EVENTOUT
I2C2_SDA/ EVENTOUT
DocID022152 Rev 4 47/185
Pinouts and pin description STM32F405xx, STM32F407xx
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
17 H9 26 37 R2 47 PA3 I/O FT
(4)
USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL/
EVENTOUT
ADC123_IN3
18 E5 27 38
D9
V
SS
S
L4 48 BYPASS_REG I FT
19 E4 28 39 K4 49 V
DD
S
20 J9 29 40
21 G8 30 41
22 H8 31 42
23
24
25
J8
-
-
32 43
33 44
34 45
26 G7 35 46
N4
P4
P3
R3
N5
P5
R5
50
51
52
53
54
55
56
PA4
PA5
PA6
PA7 I/O FT
PC4
PC5
PB0
I/O TTa
I/O TTa
I/O FT
I/O FT
I/O FT
I/O FT
(4)
(4)
(4)
(4)
(4)
(4)
(4)
SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS/
EVENTOUT
SPI1_SCK/
OTG_HS_ULPI_CK /
TIM2_CH1_ETR/
TIM8_CH1N/ EVENTOUT
ADC12_IN4
/DAC_OUT1
ADC12_IN5/DAC_OU
T2
SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK /
TIM3_CH1 / TIM1_BKIN/
EVENTOUT
SPI1_MOSI/ TIM8_CH1N
/ TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
ETH_RMII_CRS_DV/
EVENTOUT
ADC12_IN6
ADC12_IN7
ETH_RMII_RX_D0 /
ETH_MII_RX_D0/
EVENTOUT
ETH_RMII_RX_D1 /
ETH_MII_RX_D1/
EVENTOUT
TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2 /
TIM1_CH2N/ EVENTOUT
ADC12_IN14
ADC12_IN15
ADC12_IN8
48/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Pinouts and pin description
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
28 J7 37 48 M6 58
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
49 R6 59
50 P6 60
51 M8 61
52 N8 62
53 N6 63
54 R7 64
55 P7 65
56 N7 66
57 M7 67
G6 38 58 R8 68
H6 39 59 P8 69
-
-
J6 40 60 P9 70
-
-
61
62
M9
N9
71
72
F6 41 63 R9 73
J5 42 64 P10 74
H5 43 65 R10 75
G5 44 66 N11 76
27 H7 36 47 R4 57 PB1
PB2/BOOT1
(PB2)
PF11
PF12
V
SS
V
DD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
V
SS
V
DD
PE10
PE11
PE12
PE13
I/O FT
(4)
TIM3_CH4 / TIM8_CH3N/
OTG_HS_ULPI_D2/
ETH_MII_RXD3 /
TIM1_CH3N/ EVENTOUT
I/O FT
I/O FT
I/O FT
S
S
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
EVENTOUT
DCMI_D12/ EVENTOUT
FSMC_A6/ EVENTOUT
FSMC_A7/ EVENTOUT
FSMC_A8/ EVENTOUT
FSMC_A9/ EVENTOUT
FSMC_A10/ EVENTOUT
FSMC_A11/ EVENTOUT
FSMC_D4/TIM1_ETR/
EVENTOUT
FSMC_D5/ TIM1_CH1N/
EVENTOUT
FSMC_D6/TIM1_CH1/
EVENTOUT
I/O FT
S
S
I/O FT
I/O FT
I/O FT
I/O FT
FSMC_D7/TIM1_CH2N/
EVENTOUT
FSMC_D8/TIM1_CH2/
EVENTOUT
FSMC_D9/TIM1_CH3N/
EVENTOUT
FSMC_D10/TIM1_CH3/
EVENTOUT
ADC12_IN9
DocID022152 Rev 4 49/185
Pinouts and pin description STM32F405xx, STM32F407xx
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
F5 45 67
G4 46 68 R11
29 H4 47 69 R12 79
30
-
-
-
J4
-
M12 85
M13 86
-
-
L13 87
L12 88
-
-
-
-
-
-
-
-
K12 89
H12 90
J12 91
50/185
P11
48 70 R13
77
78
80
31 F4 49 71 M10 81
32 50 72 N10 82
M11 83
N12 84
PH9
PH10
PH11
PH12
V
SS
V
DD
PE14
PE15
PB10
PB11
V
CAP_1
V
DD
PH6
PH7
PH8
I/O FT
I/O FT
I/O FT
I/O FT
FSMC_D11/TIM1_CH4/
EVENTOUT
FSMC_D12/TIM1_BKIN/
EVENTOUT
SPI2_SCK / I2S2_CK /
I2C2_SCL/ USART3_TX /
OTG_HS_ULPI_D3 /
ETH_MII_RX_ER /
TIM2_CH3/ EVENTOUT
I2C2_SDA/USART3_RX/
OTG_HS_ULPI_D4 /
ETH_RMII_TX_EN/
ETH_MII_TX_EN /
TIM2_CH4/ EVENTOUT
S
S
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
DocID022152 Rev 4
I2C2_SMBA / TIM12_CH1
/ ETH_MII_RXD2/
EVENTOUT
I2C3_SCL /
ETH_MII_RXD3/
EVENTOUT
I2C3_SDA /
DCMI_HSYNC/
EVENTOUT
I2C3_SMBA /
TIM12_CH2/ DCMI_D0/
EVENTOUT
TIM5_CH1 / DCMI_D1/
EVENTOUT
TIM5_CH2 / DCMI_D2/
EVENTOUT
TIM5_CH3 / DCMI_D3/
EVENTOUT
STM32F405xx, STM32F407xx Pinouts and pin description
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
33
34
35
36 H1 54 76 R15
-
-
J3
J1
J2
51 73 P12
52 74 P13
53 75 R14
92
93
94
95
H2 55 77 P15 96
H3 56 78 P14 97
G3 57 79 N15
G1 58 80 N14
98
99
G2 59 81 N13 100
PB12
PB13
PB14
PB15
PD8
PD9
PD10
PD11
PD12
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
SPI2_NSS / I2S2_WS /
I2C2_SMBA/
USART3_CK/ TIM1_BKIN
/ CAN2_RX /
OTG_HS_ULPI_D5/
ETH_RMII_TXD0 /
ETH_MII_TXD0/
OTG_HS_ID/ EVENTOUT
SPI2_SCK / I2S2_CK /
USART3_CTS/
TIM1_CH1N /CAN2_TX /
OTG_HS_ULPI_D6 /
ETH_RMII_TXD1 /
ETH_MII_TXD1/
EVENTOUT
SPI2_MISO/ TIM1_CH2N
/ TIM12_CH1 /
OTG_HS_DM/
USART3_RTS /
TIM8_CH2N/I2S2ext_SD/
EVENTOUT
SPI2_MOSI / I2S2_SD/
TIM1_CH3N / TIM8_CH3N
/ TIM12_CH2 /
OTG_HS_DP/
EVENTOUT
FSMC_D13 /
USART3_TX/ EVENTOUT
FSMC_D14 /
USART3_RX/ EVENTOUT
FSMC_D15 /
USART3_CK/ EVENTOUT
FSMC_CLE /
FSMC_A16/USART3_CT
S/ EVENTOUT
FSMC_ALE/
FSMC_A17/TIM4_CH1 /
USART3_RTS/
EVENTOUT
OTG_HS_VBUS
RTC_REFIN
DocID022152 Rev 4 51/185
Pinouts and pin description STM32F405xx, STM32F407xx
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
-
-
-
-
-
-
60 82 M15 101
-
83
84
102
J13 103
F2 61 85 M14 104
F1 62 86 L14 105
-
-
-
-
-
-
-
-
-
-
-
-
-
-
87 L15 106
88 K15 107
89 K14 108
90 K13 109
91 J15 110
92 J14 111
-
-
-
-
-
93 H14 112
94 G12 113
95 H13 114
37 F3 63 96 H15 115
PG8
V
SS
V
DD
PC6
PD13
V
SS
V
DD
PD14
PD15
PG2
PG3
PG4
PG5
PG6
PG7
I/O FT
S
S
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
I/O FT
38 E1 64 97 G15 116
39 E2 65 98 G14 117
PC7
PC8
FSMC_A18/TIM4_CH2/
EVENTOUT
FSMC_D0/TIM4_CH3/
EVENTOUT/ EVENTOUT
FSMC_D1/TIM4_CH4/
EVENTOUT
FSMC_A12/ EVENTOUT
FSMC_A13/ EVENTOUT
FSMC_A14/ EVENTOUT
FSMC_A15/ EVENTOUT
FSMC_INT2/ EVENTOUT
FSMC_INT3
/USART6_CK/
EVENTOUT
USART6_RTS /
ETH_PPS_OUT/
EVENTOUT
I/O FT
I/O FT
I2S2_MCK /
TIM8_CH1/SDIO_D6 /
USART6_TX /
DCMI_D0/TIM3_CH1/
EVENTOUT
I2S3_MCK /
TIM8_CH2/SDIO_D7 /
USART6_RX /
DCMI_D1/TIM3_CH2/
EVENTOUT
TIM8_CH3/SDIO_D0
/TIM3_CH3/ USART6_CK
/ DCMI_D2/ EVENTOUT
52/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Pinouts and pin description
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
40 E3 66 99 F14 118
41 D1 67 100 F15 119
42 D2 68 101 E15 120
43 D3 69 102 D15 121
44 C1 70 103 C15 122
PC9
PA8
PA9
PA10
PA11
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
45 C2 71 104 B15 123
C3 E14 131
PA12 I/O FT
46 D4 72 105 A15 124
47 B1 73 106 F13 125
E7 74 107 F12 126
48 E6 75 108 G13 127
PA13
(JTMS-SWDIO)
V
CAP_2
V
SS
V
DD
I/O FT
S
S
S
E12 128 PH13 I/O FT
E13 129
D13 130
PH14
PH15
I/O FT
I/O FT
PI0 I/O FT
I2S_CKIN/ MCO2 /
TIM8_CH4/SDIO_D1 /
/I2C3_SDA / DCMI_D3 /
TIM3_CH4/ EVENTOUT
MCO1 / USART1_CK/
TIM1_CH1/ I2C3_SCL/
OTG_FS_SOF/
EVENTOUT
USART1_TX/ TIM1_CH2 /
I2C3_SMBA / DCMI_D0/
EVENTOUT
USART1_RX/ TIM1_CH3/
OTG_FS_ID/DCMI_D1/
EVENTOUT
USART1_CTS / CAN1_RX
/ TIM1_CH4 /
OTG_FS_DM/
EVENTOUT
USART1_RTS /
CAN1_TX/ TIM1_ETR/
OTG_FS_DP/
EVENTOUT
JTMS-SWDIO/
EVENTOUT
OTG_FS_VBUS
TIM8_CH1N / CAN1_TX/
EVENTOUT
TIM8_CH2N / DCMI_D4/
EVENTOUT
TIM8_CH3N / DCMI_D11/
EVENTOUT
TIM5_CH4 / SPI2_NSS /
I2S2_WS / DCMI_D13/
EVENTOUT
DocID022152 Rev 4 53/185
Pinouts and pin description STM32F405xx, STM32F407xx
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
-
B2
-
-
-
D14 132
C14 133
PI1
PI2
I/O FT
I/O FT
C13 134 PI3 I/O FT
-
-
-
-
-
D9 135
C9 136
49 A2 76 109 A14 137
V
SS
V
DD
PA14
(JTCK/SWCLK)
S
S
I/O FT
50 B3 77 110 A13 138
PA15
(JTDI)
I/O FT
51 D5 78 111 B14 139
52 C4 79 112 B13 140
53 A3 80 113 A12 141
D6 81 114 B12 142
C5 82 115 C12 143
54 B4 83 116 D12 144
PC10
PC11
PC12
PD0
PD1
PD2
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
SPI2_SCK / I2S2_CK /
DCMI_D8/ EVENTOUT
TIM8_CH4 /SPI2_MISO /
DCMI_D9 / I2S2ext_SD/
EVENTOUT
TIM8_ETR / SPI2_MOSI /
I2S2_SD / DCMI_D10/
EVENTOUT
JTCK-SWCLK/
EVENTOUT
JTDI/ SPI3_NSS/
I2S3_WS/TIM2_CH1_ET
R / SPI1_NSS /
EVENTOUT
SPI3_SCK / I2S3_CK/
UART4_TX/SDIO_D2 /
DCMI_D8 / USART3_TX/
EVENTOUT
UART4_RX/ SPI3_MISO /
SDIO_D3 /
DCMI_D4/USART3_RX /
I2S3ext_SD/ EVENTOUT
UART5_TX/SDIO_CK /
DCMI_D9 / SPI3_MOSI
/I2S3_SD / USART3_CK/
EVENTOUT
FSMC_D2/CAN1_RX/
EVENTOUT
FSMC_D3 / CAN1_TX/
EVENTOUT
TIM3_ETR/UART5_RX/
SDIO_CMD / DCMI_D11/
EVENTOUT
54/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Pinouts and pin description
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
-
-
-
-
-
-
-
-
84 117 D11 145
A4 85 118 D10 146
C6 86 119 C11 147
-
-
-
-
120 D8 148
121 C8 149
B5 87 122 B11 150
A5 88 123 A11 151
124 C10 152
125 B10 153
126 B9 154
127 B8 155
128 A8 156
129 A7 157
PD3
PD4
PD5
V
SS
V
DD
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
I/O FT
I/O FT
I/O FT
S
S
I/O FT
I/O FT
FSMC_CLK/
USART2_CTS/
EVENTOUT
FSMC_NOE/
USART2_RTS/
EVENTOUT
FSMC_NWE/USART2_TX
/ EVENTOUT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
FSMC_NWAIT/
USART2_RX/ EVENTOUT
USART2_CK/FSMC_NE1/
FSMC_NCE2/
EVENTOUT
USART6_RX /
FSMC_NE2/FSMC_NCE3
/ EVENTOUT
FSMC_NCE4_1/
FSMC_NE3/ EVENTOUT
FSMC_NCE4_2 /
ETH_MII_TX_EN/
ETH _RMII_TX_EN/
EVENTOUT
FSMC_NE4 /
USART6_RTS/
EVENTOUT
FSMC_A24 /
USART6_CTS
/ETH_MII_TXD0/
ETH_RMII_TXD0/
EVENTOUT
FSMC_A25 / USART6_TX
/ETH_MII_TXD1/
ETH_RMII_TXD1/
EVENTOUT
DocID022152 Rev 4 55/185
Pinouts and pin description STM32F405xx, STM32F407xx
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
-
E8 130 D7 158
F7 131 C7 159
132 B7 160
V
SS
V
DD
PG15
S
S
I/O FT
55 B6 89 133 A10 161
PB3
(JTDO/
TRACESWO)
I/O FT
56 A6 90 134 A9 162
PB4
(NJTRST)
I/O FT
57 D7 91 135 A6
58 C7 92 136 B6
59 B7 93 137 B5
61 D8 95 139 A5
62 C8 96 140 B4
163
164
165
60 A7 94 138 D6 166
167
168
PB5
PB6
PB7
BOOT0
PB8
PB9
I/O FT
I/O FT
I/O FT
I B
I/O FT
I/O FT
USART6_CTS /
DCMI_D13/ EVENTOUT
JTDO/ TRACESWO/
SPI3_SCK / I2S3_CK /
TIM2_CH2 / SPI1_SCK/
EVENTOUT
NJTRST/ SPI3_MISO /
TIM3_CH1 / SPI1_MISO /
I2S3ext_SD/ EVENTOUT
I2C1_SMBA/ CAN2_RX /
OTG_HS_ULPI_D7 /
ETH_PPS_OUT/TIM3_CH
2 / SPI1_MOSI/
SPI3_MOSI / DCMI_D10 /
I2S3_SD/ EVENTOUT
I2C1_SCL/ TIM4_CH1 /
CAN2_TX /
DCMI_D5/USART1_TX/
EVENTOUT
I2C1_SDA / FSMC_NL /
DCMI_VSYNC /
USART1_RX/ TIM4_CH2/
EVENTOUT
TIM4_CH3/SDIO_D4/
TIM10_CH1 / DCMI_D6 /
ETH_MII_TXD3 /
I2C1_SCL/ CAN1_RX/
EVENTOUT
SPI2_NSS/ I2S2_WS /
TIM4_CH4/ TIM11_CH1/
SDIO_D5 / DCMI_D7 /
I2C1_SDA / CAN1_TX/
EVENTOUT
V
PP
56/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Pinouts and pin description
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions Additional functions
-
-
-
97 141 A4
98 142 A3
169
170
PE0
PE1
I/O FT
I/O FT
TIM4_ETR / FSMC_NBL0
/ DCMI_D2/ EVENTOUT
FSMC_NBL1 / DCMI_D3/
EVENTOUT
63 99 D5 -
A8 143 C6 171
64 A1
10
0
144 C5 172
V
V
SS
PDR_ON
DD
S
I
S
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D4 173
C4 174
C3 175
C2 176
PI4
PI5
PI6
PI7
I/O FT
I/O FT
I/O FT
I/O FT
TIM8_BKIN / DCMI_D5/
EVENTOUT
TIM8_CH1 /
DCMI_VSYNC/
EVENTOUT
TIM8_CH2 / DCMI_D6/
EVENTOUT
TIM8_CH3 / DCMI_D7/
EVENTOUT
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset
ON mode), then PA0 is used as an internal Reset (active low).
Pins
(1)
PE2
PE3
CF
Table 8. FSMC pin definition
FSMC
NOR/PSRAM/
SRAM
NOR/PSRAM Mux NAND 16 bit
LQFP100
(2)
A23
A19
A23
A19
Yes
Yes
WLCSP90
(2)
DocID022152 Rev 4 57/185
Pinouts and pin description STM32F405xx, STM32F407xx
PE7
PE8
PE9
PE10
PE11
PE12
PF12
PF13
PF14
PF15
PG0
PG1
PE13
PE14
PE15
PD8
PD9
PD10
PD11
PF5
PF6
PF7
PF8
PF9
PF10
PF1
PF2
PF3
PF4
PE4
PE5
PE6
PF0
Pins
(1)
D10
D11
D12
D13
D14
D15
D4
D5
D6
D7
D8
D9
CF
A6
A7
A8
A9
A10
A0
A1
A2
A3
A4
A5
NIORD
NREG
NIOWR
CD
INTR
D4
D5
D6
D7
D8
D9
A6
A7
A8
A9
A10
A11
D10
D11
D12
D13
D14
D15
A16
Table 8. FSMC pin definition (continued)
FSMC
LQFP100
(2)
NOR/PSRAM/
SRAM
NOR/PSRAM Mux NAND 16 bit
A1
A2
A3
A4
A5
A20
A21
A22
A0
A20
A21
A22
DA10
DA11
DA12
DA13
DA14
DA15
A16
DA4
DA5
DA6
DA7
DA8
DA9
D10
D11
D12
D13
D14
D15
CLE
D4
D5
D6
D7
D8
D9
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
Yes
Yes
Yes
-
WLCSP90
(2)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
58/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Pinouts and pin description
Pins
(1)
CF
Table 8. FSMC pin definition (continued)
FSMC
LQFP100
(2)
NOR/PSRAM/
SRAM
NOR/PSRAM Mux NAND 16 bit
WLCSP90
(2)
PD12
PD13
PD14
PD15
PG2
PG3
PG4
PG5
D0
D1
PG6
PG7
PD0
PD1
PD3
PD4
D2
D3
PD5
PD6
PD7
NOE
NWE
NWAIT
PG9
PG10 NCE4_1
PG11 NCE4_2
PG12
PG13
PG14
PB7
PE0
PE1
A17
A18
D0
D1
A12
A13
A14
A15
D2
D3
CLK
NOE
NWE
NWAIT
NE1
NE2
NE3
NE4
A24
A25
NADV
NBL0
NBL1
A17
A18
DA0
DA1
DA2
DA3
CLK
NOE
NWE
NWAIT
NE1
NE2
NE3
NE4
A24
A25
NADV
NBL0
NBL1
ALE
D0
D1
INT2
INT3
D2
D3
NOE
NWE
NWAIT
NCE2
NCE3
Yes
1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column.
2. Ports F and G are not available in devices delivered in 100-pin packages.
-
-
-
-
Yes
Yes
-
-
Yes
Yes
-
-
-
-
-
Yes
Yes
Yes
Yes
-
Yes
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
Yes
Yes
Yes
Yes
-
-
-
-
Yes
Yes
Yes
Yes
DocID022152 Rev 4 59/185
AF0 AF1 AF2 AF3 AF4 AF5
Table 9. Alternate function mapping
AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
Port
SYS TIM1/2 TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
AF14 AF15
PA5
PA6
Port A
PA7
PA0
PA1
PA2
PA3
PA4
PA8
PA9
MCO1
PA10
PA11
PA12
PA13
PA14
PA15
JTMS-
SWDIO
JTCK-
SWCLK
JTDI
TIM2_CH1_E
TR
TIM2_CH2 TIM5_CH2
TIM2_CH3 TIM5_CH3 TIM9_CH1
TIM2_CH4 TIM5_CH4 TIM9_CH2
SPI1_NSS
SPI3_NSS
I2S3_WS
TIM2_CH1_E
TR
TIM8_CH1N SPI1_SCK
TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO
TIM1_CH1N TIM3_CH2 TIM8_CH1N
TIM1_CH2
TIM 5_CH1 TIM8_ETR
I2C3_SMB
A
SPI1_MOSI
USART2_CTS UART4_TX
USART2_TX
USART2_RX
USART2_CK
ETH_MII_CRS
ETH_MII
_RX_CLK
ETH_RMII__REF
_CLK
ETH_MDIO
OTG_HS_ULPI_
D0
ETH _MII_COL
OTG_HS_ULPI_
TIM13_CH1
CK
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
OTG_HS_SO
F
DCMI_HSYN
C
EVENTOUT
EVENTOUT
DCMI_PIXCK EVENTOUT
TIM14_CH1
ETH_MII _RX_DV
ETH_RMII
_CRS_DV
EVENTOUT
USART1_TX
EVENTOUT
DCMI_D0 EVENTOUT
TIM1_CH3
TIM1_CH4
TIM1_ETR
USART1_RX OTG_FS_ID
USART1_CTS CAN1_RX OTG_FS_DM
USART1_RTS CAN1_TX OTG_FS_DP
EVENTOUT
EVENTOUT
EVENTOUT
TIM 2_CH1
TIM 2_ETR
SPI1_NSS
SPI3_NSS/
I2S3_WS
EVENTOUT
EVENTOUT
AF0 AF1 AF2 AF3 AF4 AF5
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
Port
SYS TIM1/2 TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
AF14 AF15
PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N
OTG_HS_ULPI_
D1
OTG_HS_ULPI_
D2
ETH _MII_RXD2
ETH _MII_RXD3 PB1
PB2
PB9
TIM1_CH3N TIM3_CH4 TIM8_CH3N
PB3
PB4
PB5
PB6
PB7
Port B
PB8
JTDO/
TRACES
WO
NJTRST TIM3_CH1
TIM3_CH2
I2C1_SMB
A
SPI1_MISO
SPI1_MOSI
TIM4_CH1 I2C1_SCL
SPI3_MOSI
I2S3_SD
I2S3ext_SD
CAN2_RX
OTG_HS_ULPI_
D7
USART1_TX CAN2_TX
ETH _PPS_OUT
TIM4_CH2 I2C1_SDA USART1_RX
SPI2_NSS
I2S2_WS
PB10
PB11
PB12
PB13
TIM1_BKIN
TIM1_CH1N
I2C2_SMB
A
SPI2_NSS
I2S2_WS
SPI2_SCK
I2S2_CK
I2S2ext_SD
DCMI_D10
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
OTG_HS_ULPI_
D3
ETH_ MII_RX_ER
D4
ETH _MII_TX_EN
ETH
_RMII_TX_EN
ETH _MII_TXD0
ETH _RMII_TXD0
ETH _MII_TXD1
ETH _RMII_TXD1
OTG_HS_ID
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
OTG_HS_DM EVENTOUT PB14
PB15
RTC_
REFIN
FSMC_NL
DCMI_VSYN
C
Port
AF0
SYS
PC0
PC1
PC2
PC3
PC4
PC5
Port C
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
MCO2
AF1
TIM1/2
AF2
TIM3/4/5
AF3 AF4
TIM8/9/10/1
1
I2C1/2/3
AF5
SPI1/SPI2/
I2S2/I2S2ext
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
AF9
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
SPI2_MISO
SPI2_MOSI
I2S2_SD
I2S2ext_SD
AF10 AF11
OTG_FS/
OTG_HS
ETH
OTG_HS_ULPI_
STP
ETH_MDC
OTG_HS_ULPI_
DIR
OTG_HS_ULPI_
NXT
ETH _MII_TXD2
ETH
_MII_TX_CLK
ETH_MII_RXD0
ETH_RMII_RXD0
ETH _MII_RXD1
ETH _RMII_RXD1
TIM3_CH1 TIM8_CH1
TIM3_CH2 TIM8_CH2
TIM3_CH3 TIM8_CH3
I2S2_MCK
I2S3ext_SD
I2S3_MCK
USART6_TX
USART6_RX
USART6_CK
SPI3_SCK/
I2S3_CK
SPI3_MISO/
SPI3_MOSI
I2S3_SD
USART3_TX/
USART3_RX UART4_RX
USART3_CK UART5_TX
AF12
FSMC/SDIO/
OTG_FS
AF13
DCMI
SDIO_D3 DCMI_D4
SDIO_CK DCMI_D9
AF14
SDIO_D6 DCMI_D0
SDIO_D7 DCMI_D1
SDIO_D0 DCMI_D2
SDIO_D1 DCMI_D3
AF15
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
Port
Port D
PD7
PD12
PD13
PD14
PD15
PD8
PD9
PD10
PD11
PD0
PD1
PD2
PD3
PD4
PD5
PD6
AF0
SYS
AF1
TIM1/2
AF2
TIM3/4/5
AF3 AF4
TIM8/9/10/1
1
I2C1/2/3
AF5
SPI1/SPI2/
I2S2/I2S2ext
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
AF9
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
AF10
OTG_FS/
OTG_HS
AF11
ETH
AF12
FSMC/SDIO/
OTG_FS
AF13
DCMI
AF14 AF15
TIM3_ETR
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
TIM4_CH1 USART3_RTS
TIM4_CH2
TIM4_CH3
TIM4_CH4
FSMC_CLK EVENTOUT
FSMC_NOE EVENTOUT
FSMC_NWE EVENTOUT
FSMC_NWAIT EVENTOUT
FSMC_NE1/
FSMC_NCE2
EVENTOUT
FSMC_D13 EVENTOUT
FSMC_D14 EVENTOUT
FSMC_D15 EVENTOUT
FSMC_A16 EVENTOUT
FSMC_A17 EVENTOUT
FSMC_A18 EVENTOUT
FSMC_D0 EVENTOUT
FSMC_D1 EVENTOUT
Port
AF0
SYS
AF1
TIM1/2
AF2
TIM3/4/5
AF3 AF4
TIM8/9/10/1
1
I2C1/2/3
AF5
SPI1/SPI2/
I2S2/I2S2ext
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
AF9
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
PE0
PE1
TIM4_ETR
PE2
Port E
PE7
PE8
PE9
PE10
PE11
PE3
PE4
PE5
PE6
PE12
PE13
PE14
PE15
TRACECL
K
TRACED0
TRACED1
TRACED2 TIM9_CH1
TRACED3 TIM9_CH2
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
AF10
OTG_FS/
OTG_HS
AF11 AF12 AF13
AF14 AF15
ETH
FSMC/SDIO/
OTG_FS
DCMI
ETH _MII_TXD3
FSMC_NBL0 DCMI_D2
FSMC_NBL1 DCMI_D3
FSMC_A23
EVENTOUT
EVENTOUT
EVENTOUT
FSMC_A19 EVENTOUT
FSMC_A20 DCMI_D4 EVENTOUT
FSMC_A21 DCMI_D6
FSMC_A22 DCMI_D7
EVENTOUT
EVENTOUT
FSMC_D4 EVENTOUT
FSMC_D5 EVENTOUT
FSMC_D6 EVENTOUT
FSMC_D7 EVENTOUT
FSMC_D8 EVENTOUT
FSMC_D9 EVENTOUT
FSMC_D10 EVENTOUT
FSMC_D11 EVENTOUT
FSMC_D12 EVENTOUT
Port
Port F
PF3
PF4
PF5
PF6
PF7
PF8
PF0
PF1
PF2
PF9
PF10
PF11
PF12
PF13
PF14
PF15
AF0
SYS
AF1
TIM1/2
AF2
TIM3/4/5
AF3 AF4
TIM8/9/10/1
1
I2C1/2/3
AF5
SPI1/SPI2/
I2S2/I2S2ext
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
AF9
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
I2C2_SDA
I2C2_SCL
I2C2_
SMBA
AF10
OTG_FS/
OTG_HS
TIM10_CH1
TIM11_CH1
TIM13_CH1
AF11
ETH
AF12 AF13
AF14 AF15
FSMC/SDIO/
OTG_FS
DCMI
FSMC_A0 EVENTOUT
FSMC_A1 EVENTOUT
FSMC_A2 EVENTOUT
FSMC_A3 EVENTOUT
FSMC_A4 EVENTOUT
FSMC_A5 EVENTOUT
FSMC_NIORD EVENTOUT
FSMC_NREG EVENTOUT
FSMC_
NIOWR
EVENTOUT
FSMC_INTR EVENTOUT
DCMI_D12 EVENTOUT
FSMC_A6 EVENTOUT
FSMC_A7 EVENTOUT
FSMC_A8 EVENTOUT
FSMC_A9 EVENTOUT
Port
PG4
PG5
PG6
PG7
PG0
PG1
PG2
PG3
PG8
Port G
PG9
PG10
PG11
PG12
PG13
PG14
PG15
AF0
SYS
AF1
TIM1/2
AF2
TIM3/4/5
AF3 AF4
TIM8/9/10/1
1
I2C1/2/3
AF5
SPI1/SPI2/
I2S2/I2S2ext
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
AF9
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
AF10
OTG_FS/
OTG_HS
USART6_
RTS
USART6_RX
USART6_
RTS
UART6_CTS
USART6_TX
USART6_
CTS
AF11
ETH
AF12 AF13
AF14 AF15
FSMC/SDIO/
OTG_FS
DCMI
FSMC_A10 EVENTOUT
FSMC_A11 EVENTOUT
FSMC_A12 EVENTOUT
FSMC_A13 EVENTOUT
FSMC_A14 EVENTOUT
FSMC_A15 EVENTOUT
FSMC_INT2 EVENTOUT
ETH _PPS_OUT
FSMC_NE2/
FSMC_NCE3
FSMC_
NCE4_1/
FSMC_NE3
ETH _MII_TX_EN
ETH _RMII_
TX_EN
FSMC_NCE4_
2
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
FSMC_NE4 EVENTOUT
ETH _MII_TXD0
ETH _RMII_TXD0
ETH _MII_TXD1
ETH _RMII_TXD1
FSMC_A24 EVENTOUT
FSMC_A25 EVENTOUT
DCMI_D13 EVENTOUT
Port
PH6
Port H
PH7
PH8
PH0
PH1
PH2
PH3
PH4
PH5
PH9
PH10
PH11
PH12
PH13
PH14
PH15
AF0
SYS
AF1
TIM1/2
AF2
TIM3/4/5
AF3 AF4
TIM8/9/10/1
1
I2C1/2/3
AF5
SPI1/SPI2/
I2S2/I2S2ext
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
AF9
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
I2C2_SCL
I2C2_SDA
I2C2_SMB
A
I2C3_SCL
I2C3_SDA
I2C3_SMB
A
AF10
OTG_FS/
OTG_HS
OTG_HS_ULPI_
NXT
AF11
ETH
ETH _MII_CRS
ETH _MII_COL
ETH _MII_RXD3
AF12
FSMC/SDIO/
OTG_FS
AF13
DCMI
AF14 AF15
DCMI_HSYN
C
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TIM5_CH1
TIM5_CH2
TIM5_CH3
TIM8_CH1N
TIM8_CH2N
TIM8_CH3N
CAN1_TX
DCMI_D1 EVENTOUT
DCMI_D2 EVENTOUT
DCMI_D3 EVENTOUT
EVENTOUT
DCMI_D4 EVENTOUT
DCMI_D11 EVENTOUT
Port
PI0
Port I
PI5
PI6
PI7
PI8
PI9
PI10
PI11
PI1
PI2
PI3
PI4
AF0
SYS
AF1
TIM1/2
AF2
TIM3/4/5
TIM5_CH4
AF3 AF4
TIM8/9/10/1
1
I2C1/2/3
AF5
SPI1/SPI2/
I2S2/I2S2ext
Table 9. Alternate function mapping (continued)
AF6 AF7 AF8
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
AF9
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
TIM8_CH4 SPI2_MISO
TIM8_ETR
SPI2_MOSI
I2S2_SD
TIM8_BKIN
SPI2_NSS
I2S2_WS
SPI2_SCK
I2S2_CK
I2S2ext_SD
TIM8_CH1
TIM8_CH2
TIM8_CH3
AF10
OTG_FS/
OTG_HS
AF11
ETH
CAN1_RX
OTG_HS_ULPI_
DIR
ETH _MII_RX_ER
AF12
FSMC/SDIO/
OTG_FS
AF13
DCMI
AF14 AF15
DCMI_D13 EVENTOUT
DCMI_D8 EVENTOUT
DCMI_D9 EVENTOUT
DCMI_D10 EVENTOUT
DCMI_D5 EVENTOUT
DCMI_
VSYNC
EVENTOUT
DCMI_D6 EVENTOUT
DCMI_D7 EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
STM32F405xx, STM32F407xx Memory mapping
The memory map is shown in
.
Figure 18. STM32F40x memory map
Reserved
CORTEX-M4 internal peripherals
Reserved
AHB3
Reserved
0xE010 0000 - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0xA000 1000 - 0xDFFF FFFF
0xA000 0FFF
0x6000 0000
0x5006 0C00 - 0x5FFF FFFF
0x5006 0BFF
AHB2
0xFFFF FFFF
512-Mbyte
block 7
Cortex-M4's internal peripherals
0xE000 0000
0xDFFF FFFF
512-Mbyte
block 6
Not used
0xC000 0000
0xBFFF FFFF
512-Mbyte
block 5
FSMC registers
0xA000 0000
0x9FFF FFFF
512-Mbyte
block 4
FSMC bank 3
& bank4
0x8000 0000
0x7FFF FFFF
512-Mbyte
block 3
FSMC bank1
& bank2
0x6000 0000
0x5FFF FFFF
512-Mbyte
block 2
Peripherals
0x4000 0000
0x3FFF FFFF
512-Mbyte
block 1
SRAM
0x2000 0000
0x1FFF FFFF
512-Mbyte
block 0
Code
0x0000 0000
Reserved
SRAM (16 KB aliased by bit-banding)
SRAM (112 KB aliased by bit-banding)
0x2002 0000 - 0x3FFF FFFF
0x2001 C000 - 0x2001 FFFF
0x2000 0000 - 0x2001 BFFF
Reserved
Option Bytes
Reserved
System memory + OTP
Reserved
0x1FFF C008 - 0x1FFF FFFF
0x1FFF C000 - 0x1FFF C007
0x1FFF 7A10 - 0x1FFF 7FFF
0x1FFF 0000 - 0x1FFF 7A0F
0x1001 0000 - 0x1FFE FFFF
CCM data RAM
(64 KB data SRAM)
0x1000 0000 - 0x1000 FFFF
Reserved
0x0810 0000 - 0x0FFF FFFF
Flash
Reserved
Aliased to Flash, system memory or SRAM depending on the BOOT pins
0x0800 0000
-
0x080F FFFF
0x0010 0000 - 0x07FF FFFF
0x0000 0000 - 0x000F FFFF
Reserved
AHB1
Reserved
APB2
Reserved
APB1
0x5000 0000
0x4008 0000 - 0x4FFF FFFF
0x4007 FFFF
0x4002 000
0x4001 5800 - 0x4001 FFFF
0x4001 57FF
0x4001 0000
0x4000 7800 - 0x4000 FFFF
0x4000 7FFF
DocID022152 Rev 4
0x4000 0000 ai18513f
69/185
Memory mapping STM32F405xx, STM32F407xx
Bus
Cortex-M4
AHB3
AHB2
Table 10. STM32F40x register boundary addresses
Boundary address Peripheral
0xE00F FFFF - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0xA000 1000 - 0xDFFF FFFF
0xA000 0000 - 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
0x8000 0000 - 0x8FFF FFFF
0x7000 0000 - 0x7FFF FFFF
0x6000 0000 - 0x6FFF FFFF
0x5006 0C00- 0x5FFF FFFF
0x5006 0800 - 0x5006 0BFF
0x5005 0400 - 0x5006 07FF
0x5005 0000 - 0x5005 03FF
0x5004 0000- 0x5004 FFFF
0x5000 0000 - 0x5003 FFFF
0x4008 0000- 0x4FFF FFFF
Reserved
Cortex-M4 internal peripherals
Reserved
FSMC control register
FSMC bank 4
FSMC bank 3
FSMC bank 2
FSMC bank 1
Reserved
RNG
Reserved
DCMI
Reserved
USB OTG FS
Reserved
70/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Memory mapping
Table 10. STM32F40x register boundary addresses (continued)
Bus Boundary address Peripheral
AHB1
0x4004 0000 - 0x4007 FFFF
0x4002 9400 - 0x4003 FFFF
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0x4002 5000 - 0x4002 5FFF
0x4002 4000 - 0x4002 4FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0x4002 3400 - 0x4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1C00 - 0x4002 1FFF
0x4002 1800 - 0x4002 1BFF
0x4002 1400 - 0x4002 17FF
0x4002 1000 - 0x4002 13FF
0x4002 0C00 - 0x4002 0FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
0x4001 5800- 0x4001 FFFF
USB OTG HS
Reserved
ETHERNET MAC
Reserved
DMA2
DMA1
Reserved
BKPSRAM
Flash interface register
RCC
Reserved
CRC
Reserved
GPIOI
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Reserved
DocID022152 Rev 4 71/185
Memory mapping STM32F405xx, STM32F407xx
Table 10. STM32F40x register boundary addresses (continued)
Bus Boundary address Peripheral
APB2
0x4001 4C00 - 0x4001 57FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2400 - 0x4001 2BFF
0x4001 2000 - 0x4001 23FF
0x4001 1800 - 0x4001 1FFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0800 - 0x4001 0FFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 7800- 0x4000 FFFF
Reserved
TIM11
TIM10
TIM9
EXTI
SYSCFG
Reserved
SPI1
SDIO
Reserved
ADC1 - ADC2 - ADC3
Reserved
USART6
USART1
Reserved
TIM8
TIM1
Reserved
72/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Memory mapping
Table 10. STM32F40x register boundary addresses (continued)
Bus Boundary address Peripheral
APB1
0x4000 7800 - 0x4000 7FFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Reserved
DAC
PWR
Reserved
CAN2
CAN1
Reserved
I2C3
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3 / I2S3
SPI2 / I2S2
I2S2ext
TIM12
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
IWDG
WWDG
RTC & BKP Registers
Reserved
TIM14
TIM13
DocID022152 Rev 4 73/185
Electrical characteristics STM32F405xx, STM32F407xx
5.1.1
Unless otherwise specified, all voltages are referenced to V
SS
.
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A the selected temperature range).
= 25 °C and T
A
= T
A max (given by
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).
Unless otherwise specified, typical data are based on T
A
= 25 °C, V
DD
1.8 V
≤ V tested.
DD
= 3.3 V (for the
≤ 3.6 V voltage range). They are given only as design guidelines and are not
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ)
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.5
The loading conditions used for pin parameter measurement are shown in
.
Pin input voltage
The input voltage measurement on a pin of the device is described in
Figure 19. Pin loading conditions Figure 20. Pin input voltage
74/185
C = 50 pF
STM32F pin
OSC_OUT (Hi-Z when
using HSE or LSE)
MS19011V1
VIN
STM32F pin
OSC_OUT (Hi-Z when
using HSE or LSE)
MS19010V1
DocID022152 Rev 4
STM32F405xx, STM32F407xx
5.1.6 Power supply scheme
VBAT =
1.65 to 3.6V
Figure 21. Power supply scheme
VBAT
Power switch
Electrical characteristics
Backup circuitry
(OSC32K,RTC,
Wakeup logic
Backup registers, backup RAM)
OUT
IN
IO
Logic
GPIOs
15 × 100 nF
+ 1 × 4.7 μF
2 × 2.2 μF
VDD
VCAP_1
VCAP_2
VDD
1/2/...14/15
VSS
1/2/...14/15
BYPASS_REG
PDR_ON
VDD
100 nF
+ 1 μF
100 nF
+ 1 μF
VDDA
VREF
VREF+
VREF-
VSSA
Voltage regulator
Reset controller
ADC
Analog:
RCs,
PLL,..
Kernel logic
(CPU, digital
& RAM)
Flash memory
MS19911V2
1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the
PCB to ensure the good functionality of the device.
2. To connect BYPASS_REG and PDR_ON pins, refer to
Section 2.2.16: Voltage regulator
3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
4. The 4.7 µF ceramic capacitor must be connected to one of the V
DD
pin.
5. V
DDA
=V
DD
and V
SSA
=V
SS
.
DocID022152 Rev 4 75/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 22. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
5.2
VDDA
ai14126
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in
Table 11: Voltage characteristics
,
Table 12: Current characteristics
, and
Table 13: Thermal characteristics
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
V
Symbol
V
DD
V
–V
IN
SS
|
ΔV
DDx
|
|V
SSX
− V
SS
ESD(HBM)
Table 11. Voltage characteristics
Ratings
External main supply voltage (including V
DDA
,
Input voltage on five-volt tolerant pin
Input voltage on any other pin
Variations between different V
DD
(2)
power pins
V
DD
)
(1)
| Variations between all the different ground pins
Electrostatic discharge voltage (human body model)
Min Max
–0.3
4.0
V
SS
–0.3
V
DD
+4
V
SS
–0.3
4.0
50
50
Absolute maximum ratings (electrical sensitivity)
Unit
V mV
1. All main power (V , V
DDA
) and ground (V supply, in the permitted range.
SS
, V
SSA
) pins must always be connected to the external power
2. V
IN
maximum value must always be respected. Refer to
for the values of the maximum allowed
injected current.
76/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol
Table 12. Current characteristics
Ratings Max.
Unit
I
I
VDD
VSS
I
INJ(PIN)
(2)
Total current into V
DD power lines (source)
(1)
Total current out of V
SS ground lines (sink)
(1)
Output current sunk by any I/O and control pin
150
150
25
I
IO
Output current source by any I/Os and control pin
Injected current on five-volt tolerant I/O
(3)
Injected current on any other pin
(4)
Total injected current (sum of all I/O and control pins)
(5)
25
–5/+0
±5 mA
ΣI
INJ(PIN)
(4)
±25
1. All main power (V , V
DDA
) and ground (V supply, in the permitted range.
SS
, V
SSA
) pins must always be connected to the external power
2. Negative injection disturbs the analog performance of the device. See note in
Section 5.3.20: 12-bit ADC characteristics
.
3. Positive injection is not possible on these I/Os. A negative injection is induced by V
<V
SS
. I
for the values of the maximum allowed input voltage.
INJ(PIN)
must
4. A positive injection is induced by V
IN
>V
DD
while a negative injection is induced by V
IN
<V
SS
. I
INJ(PIN)
must
5. When several inputs are submitted to a current injection, the maximum
ΣI positive and negative injected currents (instantaneous values).
INJ(PIN)
is the absolute sum of the
Symbol
T
STG
T
J
Table 13. Thermal characteristics
Ratings
Storage temperature range
Maximum junction temperature
Value
–65 to +150
125
Unit
°C
°C
5.3.1 General operating conditions
Symbol
f
HCLK
Parameter
Table 14. General operating conditions
Internal AHB clock frequency
Conditions
VOS bit in PWR_CR register = 0
(1)
VOS bit in PWR_CR register= 1 f
PCLK1 f
PCLK2
V
DD
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
Analog operating voltage
(ADC limited to 1.2 M samples)
V
DDA
(3)(4)
Analog operating voltage
(ADC limited to 1.4 M samples)
V
BAT
Backup operating voltage
Must be the same potential as
V
DD
(5)
1.8
(2)
2.4
1.65
Min Typ Max Unit
0 144
0
0
0
1.8
(2)
168
42
84
3.6
MHz
V
2.4
3.6
3.6
V
V
DocID022152 Rev 4 77/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
V
12
V
IN
P
D
T
A
T
J
Table 14. General operating conditions (continued)
Parameter Conditions Min
Regulator ON:
1.2 V internal voltage on
V
CAP_1
/V
CAP_2 pins
Regulator OFF:
1.2 V external voltage must be supplied from external regulator on V
CAP_1
/V
CAP_2 pins
VOS bit in PWR_CR register = 0
(1)
Max frequency 144MHz
VOS bit in PWR_CR register= 1
Max frequency 168MHz
Max frequency 144MHz
Max frequency 168MHz
Typ
1.08
1.14
1.20
1.26
1.10
1.14
1.20
1.26
Input voltage on RST and FT pins
(6)
Input voltage on TTa pins
Input voltage on B pin
Power dissipation at T
A for suffix 6 or T
A suffix 7
(7)
= 85 °C
= 105 °C for
Ambient temperature for 6 suffix version
Ambient temperature for 7 suffix version
Junction temperature range
2 V ≤ V
DD
≤ 3.6 V
V
DD
≤ 2 V
LQFP64
LQFP100
LQFP144
LQFP176
UFBGA176
WLCSP90
Maximum power dissipation
Low power dissipation
(8)
Maximum power dissipation
Low power dissipation
(8)
6 suffix version
7 suffix version
Max Unit
1.20
1.32
1.20
1.30
–0.3
–0.3
–0.3
-
-
-
-
-
-
-
-
-
-
–40
543
85
–40 105
–40 105
–40 125
–40 105
–40 125
5.5
5.2
V
DDA
0.3
+
5.5
435
465
500
526
513
V
V
V
V
V mW
°C
°C
°C
1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole temperature range, when the system clock frequency is between 30 and 144 MHz.
2. V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF
).
3. When the ADC is used, refer to
4. If V
REF+
pin is present, it must respect the following condition: V
DDA
-V
REF+
< 1.2 V.
5. It is recommended to power V
V
DDA and V
DDA from the same source. A maximum difference of 300 mV between V can be tolerated during power-up and power-down operation.
DD and
6. To sustain a voltage higher than V
DD
+0.3, the internal pull-up and pull-down resistors must be disabled.
7. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
Jmax
.
8. In low power dissipation state, T
A
can be extended to this range as long as T
J
does not exceed T
Jmax
.
78/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Operating power supply range
Table 15. Limitations depending on the operating power supply range
ADC operation
Maximum
Flash memory access frequency with no wait state
(f
Flashmax
)
Maximum Flash memory access frequency with wait states
(1) (2)
I/O operation
Clock output
Frequency on
I/O pins
V
DD
=1.8 to
2.1 V
(3)
Conversion time up to
1.2 Msps
20 MHz
(4)
160 MHz with 7 wait states
– Degraded speed performance
– No I/O compensation up to 30 MHz
Possible
Flash memory operations
8-bit erase and program operations only
V
2.4 V
V
DD
DD
= 2.1 to
= 2.4 to
2.7 V
Conversion time up to
1.2 Msps
Conversion time up to
2.4 Msps
22 MHz
24 MHz
168 MHz with 7 wait states
168 MHz with 6 wait states
– Degraded speed performance
– No I/O compensation up to 30 MHz
– Degraded speed performance
– I/O compensation works up to 48 MHz
16-bit erase and program operations
16-bit erase and program operations
V
DD
= 2.7 to
3.6 V
(5)
Conversion time up to
2.4 Msps
30 MHz
168 MHz with 5 wait states
– Full-speed operation
– I/O compensation works
– up to
60 MHz when V
DD
=
3.0 to 3.6 V
– up to
48 MHz when V
DD
=
2.7 to 3.0 V
32-bit erase and program operations
1. It applies only when code executed from Flash memory access, when code executed from RAM, no wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.
3. V
DD
/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF
).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.
5.3.2 V
CAP_1
/V
CAP_2
external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
EXT the V
CAP_1
/V
CAP_2
pins. C
EXT
is specified in
to
DocID022152 Rev 4 79/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 23. External capacitor C
EXT
C
ESR
R
Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Symbol
Table 16. V
CAP_1
/V
CAP_2
operating conditions
(1)
Parameter Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF
< 2
Ω
1. When bypassing the voltage regulator, the two 2.2 µF V replaced by two 100 nF decoupling capacitors.
CAP
capacitors are not required and should be
Subject to general operating conditions for T
A
.
Table 17. Operating conditions at power-up / power-down (regulator ON)
Symbol Parameter Min Max Unit
t
VDD
V
DD
rise time rate
V
DD
fall time rate
20
20
∞
∞
µs/V
5.3.5
Subject to general operating conditions for T
A
.
Table 18. Operating conditions at power-up / power-down (regulator OFF)
(1)
Symbol Parameter Conditions Min Max Unit
t t
VDD
VCAP
V
DD
rise time rate
V
DD
fall time rate
V
CAP_1 rate
and V
CAP_2 rise time
Power-up
Power-down
Power-up
V
CAP_1 rate
and V
CAP_2
fall time
Power-down
20
20
20
20
∞
∞
∞
∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V minimum value of V
12
.
DD
reach below
µs/V
Embedded reset and power control block characteristics
The parameters given in
are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
80/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 19. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
PVD
V
PVDhyst
(1)
V
POR/PDR
V
PDRhyst
(1)
V
BOR1
V
BOR2
V
BOR3
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
2.09
1.98
2.23
2.13
2.14
2.04
2.30
2.19
2.19
2.08
2.37
2.25
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
2.39
2.29
2.45
2.35
2.51
2.39
Programmable voltage detector level selection
PLS[2:0]=011 (rising edge) 2.54
2.60
2.65
PLS[2:0]=011 (falling edge)
2.44
2.51
2.56
PLS[2:0]=100 (rising edge)
2.70
2.76
2.82
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
2.59
2.86
2.65
2.66
2.93
2.84
2.71
2.99
3.02
PLS[2:0]=110 (rising edge) 2.96
3.03
3.10
PLS[2:0]=110 (falling edge)
2.85
2.93
2.99
PLS[2:0]=111 (rising edge) 3.07
3.14
3.21
PLS[2:0]=111 (falling edge)
2.95
3.03
3.09
PVD hysteresis
Power-on/power-down reset threshold
Falling edge
Rising edge
PDR hysteresis
Brownout level 1 threshold
Falling edge
Rising edge
Brownout level 2 threshold
Brownout level 3 threshold
Falling edge
Rising edge
Falling edge
Rising edge
100 -
1.60
1.68
1.76
1.64
1.72
1.80
40 -
2.13
2.19
2.24
2.23
2.29
2.33
2.44
2.50
2.56
2.53
2.59
2.63
2.75
2.83
2.88
2.85
2.92
2.97
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V mV
V
V mV
V
V
V
V
V
V
DocID022152 Rev 4 81/185
Electrical characteristics
5.3.6
STM32F405xx, STM32F407xx
Table 19. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
V
BORhyst
(1)
T
RSTTEMPO
(1)(2)
BOR hysteresis
Reset temporization
I
RUSH
(1)
InRush current on voltage regulator power-on (POR or wakeup from Standby)
E
RUSH
(1)
InRush energy on voltage regulator power-on (POR or wakeup from Standby)
I
V
DD
= 1.8 V, T
A
RUSH
= 105 °C,
= 171 mA for 31 µs
-
0.5
-
-
100 -
1.5
3.0
mV ms
160 200 mA
5.4
µC
1. Guaranteed by design, not tested in production.
2. The reset temporization is measured from the power-on (POR reset or wakeup from V when first instruction is read by the user application code.
BAT
) to the instant
Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in
Figure 22: Current consumption measurement scheme
.
All Run mode current consumption measurements given in this section are performed using a CoreMark-compliant code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
At startup, all I/O pins are configured as analog inputs by firmware.
•
All peripherals are disabled except if it is explicitly mentioned.
•
The Flash memory access time is adjusted to f
HCLK
frequency (0 wait state from 0 to
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to
168 MHz).
•
When the peripherals are enabled HCLK is the system clock, f
PCLK1 f
PCLK2
= f
HCLK
/2, except is explicitly mentioned.
= f
HCLK
/4, and
•
The maximum values are obtained for V
DD
= 3.6 V and maximum ambient temperature
(T
A
), and the typical values for T
A
= 25 °C and V
DD
= 3.3 V unless otherwise specified.
82/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 20. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM
(1)
Typ Max
(2)
Symbol Parameter Conditions f
HCLK
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
I
DD
Supply current in
Run mode
External clock peripherals enabled
External clock
(3)
(3)
, all
, all peripherals disabled
(4)(5)
(4)(5)
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
(6)
8 MHz
4 MHz
2 MHz
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
(6)
8 MHz
4 MHz
2 MHz
87
67
56
44
30
16
12
9
5
3
2
40
31
26
20
14
8
6
5
3
2
2 mA
1. Code and data processing running from SRAM1 using boot pins.
2. Based on characterization, tested in production at V
DD max and f
HCLK
max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when f
HCLK
> 25 MHz.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.
5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.
6. In this case HCLK = system clock/2.
17
15
14
54
43
38
32
26
42
28
24
20
102
80
69
56
20
18
16
15
14
14
24
22
21
61
50
45
39
33
49
35
31
28
109
86
75
62
27
25
24
22
21
21
DocID022152 Rev 4 83/185
Electrical characteristics STM32F405xx, STM32F407xx
Table 21. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Typ Max
(1)
Symbol Parameter Conditions f
HCLK
Unit
T
A
= 25 °C T
A
= 85 °C T
A
= 105 °C
168 MHz 93 109 117
I
DD
Supply current in Run mode
External clock
(2)
, all peripherals enabled
(3)(4)
External clock
(2)
, all peripherals disabled
(3)(4)
16
15
61
52
48
42
32
27
23
18
89
79
65
49
19
16
15
14
33
24
21
4
3
46
40
37
30
20
16
11
6
76
67
53
37
7
4
3
2
22
12
10
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
8 MHz
4 MHz
2 MHz
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
8 MHz
4 MHz
2 MHz mA
23
22
69
60
56
50
39
35
30
25
96
86
73
56
26
23
22
21
41
31
29
1. Based on characterization, tested in production at V
DD max and f
HCLK
max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when f
HCLK
> 25 MHz.
3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.
84/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF
30
25
20
15
50
45
40
35
10
5
0
0
-45 °C
0 °C
25 °C
55 °C
85 °C
105 °C
20 40 60 80 100
CPU Frequency (MHz
120 140 160 180
MS19974V1
Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON
70
60
50
40
30
100
90
80
20
10
0
0 20 40 60 80 100
CPU Frequency (MHz
120 140 160 180
-45°C
0°C
25°C
55°C
85°C
105°C
MS19975V1
DocID022152 Rev 4 85/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF
60
50
40
30
20
10
-45°C
0°C
25°C
55°C
85°C
105°C
0
0 20 40 60 80 100
CPU Frequency (MHz
120 140 160 180
MS19976V1
Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON
120
100
80
60
40
20
0
0 20 40 60 80 100
CPU Frequency (MHz
120 140 160 180
-45°C
0°C
25°C
55°C
85°C
105°C
MS19977V1
86/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol
Table 22. Typical and maximum current consumption in Sleep mode
Typ Max
(1)
Parameter Conditions f
HCLK
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
I
DD
Supply current in
Sleep mode
External clock
(2)
, all peripherals enabled
External clock
(2)
, all peripherals disabled
(3)
8 MHz
4 MHz
2 MHz
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
30 MHz
25 MHz
16 MHz
8 MHz
4 MHz
2 MHz
59
46
38
30
20
11
8
6
3
2
2
12
9
8
7
5
3
2
2
1
1
1 mA
1. Based on characterization, tested in production at V
DD max and f
HCLK
max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when f
HCLK
> 25 MHz.
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).
16
15
14
27
22
20
19
17
34
24
21
18
77
61
53
44
16
15
14
14
13
13
23
22
21
35
29
28
26
24
41
31
28
25
84
67
60
51
23
22
21
21
21
21
DocID022152 Rev 4 87/185
Electrical characteristics STM32F405xx, STM32F407xx
Table 23. Typical and maximum current consumptions in Stop mode
Typ Max
Symbol Parameter Conditions
T
A
=
25 °C
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Supply current in
Stop mode with main regulator in
Run mode
I
DD_STOP
Supply current in
Stop mode with main regulator in
Low Power mode
Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)
Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)
Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)
Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)
0.45
0.40
0.31
0.28
1.5
11.00
20.00
1.5
11.00
20.00
1.1
1.1
8.00
15.00
8.00
15.00
Unit
mA
Table 24. Typical and maximum current consumptions in Standby mode
Typ Max
(1)
Symbol Parameter Conditions
T
A
= 25 °C
T
A
=
85 °C
T
A
=
105 °C
V
DD
=
1.8 V
V
DD
=
2.4 V
V
DD
=
3.3 V
V
DD
= 3.6 V
Backup SRAM ON, lowspeed oscillator and RTC ON
I
DD_STBY
Supply current in Standby mode
Backup SRAM OFF, lowspeed oscillator and RTC ON
Backup SRAM ON, RTC
OFF
Backup SRAM OFF, RTC
OFF
1. Based on characterization, not tested in production.
3.0
2.4
2.4
1.7
3.4
2.7
2.6
1.9
4.0
3.3
3.0
2.2
20
16
12.5
9.8
36
32
24.8
19.2
Unit
µA
88/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 25. Typical and maximum current consumptions in V
BAT
mode
Typ Max
(1)
Symbol Parameter Conditions
T
A
= 25 °C
T
A
=
85 °C
T
A
=
105 °C
V
BAT
=
1.8 V
V
BAT
=
2.4 V
V
BAT
=
3.3 V
V
BAT
= 3.6 V
I
DD_VBA
T
Backup domain supply current
Backup SRAM ON, low-speed oscillator and RTC ON
Backup SRAM OFF, low-speed oscillator and RTC ON
Backup SRAM ON, RTC OFF
Backup SRAM OFF, RTC OFF
1. Based on characterization, not tested in production.
1.29
1.42
1.68
0.62
0.73
0.96
0.79
0.81
0.10
0.10
0.86
0.10
6
3
5
2
11
5
10
4
Unit
µA
Figure 28. Typical V
BAT
current consumption (LSE and RTC ON/backup RAM OFF)
2.5
2
1.5
1
3.5
3
0.5
0
0
1.65V
1.8V
2V
2.4V
2.7V
3V
3.3V
3.6V
10 20 30 40 50 60 70 80 90 100
Temperature in (°C)
MS19990V1
DocID022152 Rev 4 89/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 29. Typical V
BAT
current consumption (LSE and RTC ON/backup RAM ON)
6
5
4
3
2
1
1.65V
1.8V
2V
2.4V
2.7V
3V
3.3V
3.6V
0
0 10 20 30 40 50 60 70 80 90 100
Temperature in (°C)
MS19991V1
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in
Table 47: I/O static characteristics
For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 27: Peripheral current consumption
), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the MCU
90/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I
SW
=
V
DD
× f
SW
×
C where
I
SW
is the current sunk by a switching I/O to charge/discharge the capacitive load
V
DD
is the MCU supply voltage f
SW
is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = C
INT
+ C
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.
DocID022152 Rev 4 91/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 26. Switching output I/O current consumption
Parameter Conditions
(1)
I/O toggling frequency (f
SW
)
Typ
2 MHz
I
DDIO
I/O switching current
V
V
C
EXT
C = C
INT
V
C
DD
C = C
V
C
EXT
C = C
INT
V
C
C = C
= 3.3 V
C = C
DD
DD
EXT
INT
DD
DD
EXT
INT
INT
+ C
(2)
= 3.3 V
= 0 pF
+ C
= 3.3 V
EXT
+ C
= 10 pF
+ C
EXT
EXT
= 3.3 V
= 22 pF
= 3.3 V
+ C
+ C
= 33 pF
+ C
EXT
+ C
S
S
S
S
60 MHz
2 MHz
8 MHz
25 MHz
50 MHz
60 MHz
2 MHz
8 MHz
8 MHz
25 MHz
50 MHz
60 MHz
2 MHz
8 MHz
25 MHz
50 MHz
25 MHz
50 MHz
60 MHz
2 MHz
8 MHz
25 MHz
50 MHz
60 MHz
1. C
S
is the PCB board capacitance including the pad pin. C
S
= 7 pF (estimated value).
2. This test is performed by cutting the LQFP package pin (pad removal).
3. At 60 MHz, C maximum load is specified 30 pF.
0.02
2.65
3.48
0.23
0.95
2.86
0.17
0.66
1.70
0.10
0.38
1.18
2.47
0.14
0.51
0.86
1.30
1.22
3.90
8.82
-
(3)
3.20
4.69
8.06
0.30
Unit
mA
92/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in
under the following conditions:
•
At startup, all I/O pins are configured as analog pins by firmware.
•
All peripherals are disabled unless otherwise mentioned
•
The code is running from Flash memory and the Flash memory access time is equal to
5 wait states at 168 MHz.
•
The code is running from Flash memory and the Flash memory access time is equal to
4 wait states at 144 MHz, and the power scale mode is set to 2.
•
ART accelerator and Cache off.
•
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with one peripheral clocked on (with only the clock applied)
•
When the peripherals are enabled: HCLK is the system clock, f
PCLK1 f
PCLK2
= f
HCLK
/2.
= f
HCLK
/4, and
•
The typical values are obtained for V
DD specified.
= 3.3 V and T
A
= 25 °C, unless otherwise
AHB1
AHB2
Table 27. Peripheral current consumption
Peripheral
(1)
168 MHz 144 MHz
GPIO A
GPIO B
GPIO C
GPIO D
GPIO E
GPIO F
GPIO G
GPIO H
GPIO I
OTG_HS + ULPI
CRC
BKPSRAM
DMA1
DMA2
ETH_MAC +
ETH_MAC_TX
ETH_MAC_RX
ETH_MAC_PTP
OTG_FS
DCMI
0.44
4.57
0.07
0.11
6.15
6.24
0.49
0.45
0.45
0.45
0.47
0.45
0.44
0.45
3.28
4.59
1.04
0.33
3.55
0.06
0.08
4.75
4.8
0.36
0.33
0.34
0.34
0.35
0.33
0.33
0.34
2.54
3.69
0.80
Unit
mA mA
DocID022152 Rev 4 93/185
Electrical characteristics
AHB3
APB1
STM32F405xx, STM32F407xx
Table 27. Peripheral current consumption (continued)
Peripheral
(1)
168 MHz 144 MHz
FSMC
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
PWR
USART2
USART3
UART4
UART5
I2C1
I2C2
I2C3
SPI2/I2S2
(2)
SPI3/I2S3
(2)
CAN1
CAN2
DAC
DAC channel 1
(3)
DAC channel 2
(4)
DAC channel 1 and
2
(3)(4)
WWDG
1.69
0.04
1.68
0.04
0.27
0.27
0.04
0.17
0.17
0.17
0.17
0.17
0.18
0.18
0.79
0.15
0.16
0.33
2.18
0.80
0.58
0.62
0.17/0.16
0.16/0.14
0.27
0.26
0.14
0.91
0.91
0.21
0.21
0.03
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.61
0.11
0.12
0.26
1.67
0.61
0.44
0.48
0.13/0.12
0.12/0.12
0.21
0.20
0.10
0.89
0.89
Unit
mA
94/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 27. Peripheral current consumption (continued)
Peripheral
(1)
168 MHz 144 MHz
APB2
SDIO
TIM1
TIM8
TIM9
TIM10
TIM11
ADC1
(5)
ADC2
(5)
ADC3
(5)
SPI1
USART1
USART6
0.64
1.47
1.58
0.68
0.45
0.47
2.20
2.04
2.10
0.14
0.34
0.34
1. HSE oscillator with 4 MHz crystal and PLL are ON.
2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I
2
S peripheral.
3. EN1 bit is set in DAC_CR register.
4. EN2 bit is set in DAC_CR register.
5. ADON bit set in ADC_CR2 register.
0.36
0.38
2.10
1.93
0.54
1.14
1.22
0.54
2.00
0.12
0.27
0.28
Unit
mA
5.3.7 Wakeup time from low-power mode
The wakeup times given in
is measured on a wakeup phase with a 16 MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current operating mode:
•
Stop or Standby mode: the clock source is the RC oscillator
• Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V
DD voltage conditions summarized in
supply
Symbol
t
WUSLEEP
(2)
Table 28. Low-power mode wakeup timings
Parameter
Wakeup from Sleep mode
Min
(1)
-
Typ
1
(1)
Max
-
(1)
Unit
µs
Wakeup from Stop mode (regulator in Run mode) 13 t
WUSTOP
(2)
Wakeup from Stop mode (regulator in low power mode) 17 40
µs
Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode)
110 t
WUSTDBY
(2)(3)
Wakeup from Standby mode 260 375 480 µs
1. Based on characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
3. t
WUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively.
DocID022152 Rev 4 95/185
Electrical characteristics STM32F405xx, STM32F407xx
High-speed external user clock generated from an external source
The characteristics given in
result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions summarized in
Symbol
Table 29. High-speed external user clock characteristics
Parameter Conditions Min
f
HSE_ext
External user clock source frequency
(1)
V
HSEH
V
HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)
C in(HSE)
DuCy
(HSE)
I
L
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
OSC_IN high or low time
OSC_IN rise or fall time
(1)
(1)
OSC_IN input capacitance
Duty cycle
(1)
OSC_IN Input leakage current
1. Guaranteed by design, not tested in production.
V
SS
≤ V
IN
≤ V
DD
1
0.7V
DD
V
SS
5
-
45
-
-
Typ
5
-
-
-
-
-
-
-
Max Unit
50
V
DD
0.3V
DD
-
10
-
55
±1
MHz
V ns pF
%
µA
Low-speed external user clock generated from an external source
The characteristics given in
result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions summarized in
Symbol
Table 30. Low-speed external user clock characteristics
Parameter
f
LSE_ext
V
LSEH
User External clock source frequency
(1)
OSC32_IN input pin high level voltage
V
LSEL t w(LSE) t f(LSE) t r(LSE) t f(LSE)
C in(LSE)
DuCy
(LSE)
I
L
OSC32_IN input pin low level voltage
OSC32_IN high or low time
OSC32_IN rise or fall time
(1)
(1)
OSC32_IN input capacitance
Duty cycle
(1)
OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production.
Conditions
V
SS
≤ V
IN
≤ V
DD
Min
-
0.7V
DD
V
SS
450
-
-
30
-
Typ
32.768
-
-
-
-
5
-
-
Max
1000
V
DD
0.3V
DD
-
50
-
70
±1
Unit
kHz
V ns pF
%
µA
96/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Figure 30. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10% tr(HSE)
THSE tf(HSE)
External clock source fHSE_ext
OSC_IN tW(HSE)
IL
STM32F tW(HSE) t ai17528
Figure 31. Low-speed external clock source AC timing diagram
VLSEH
VLSEL
90%
10% tr(LSE)
TLSE tf(LSE) tW(LSE) tW(LSE) t
External clock source fLSE_ext
OSC32_IN
IL
STM32F ai17529
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in
. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
DocID022152 Rev 4 97/185
Electrical characteristics
Note:
STM32F405xx, STM32F407xx
Symbol
Table 31. HSE 4-26 MHz oscillator characteristics
(1) (2)
Parameter Conditions Min Typ Max Unit
f
OSC_IN
R
F
Oscillator frequency
Feedback resistor
4
-
-
200
26
-
MHz k Ω
I
DD
HSE current consumption
V
DD
=3.3 V,
ESR= 30 Ω,
C
L
=5 pF@25 MHz
V
DD
=3.3 V,
ESR= 30 Ω,
C
L
=10 pF@25 MHz
Startup
-
449
532 -
-
µA g m t
SU(HSE
(3)
Oscillator transconductance
Startup time V
DD
is stabilized
5
-
-
2 -
mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
3. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
For C
L1
and C
L2
, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see
). C
L1
and C
L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
and C
L2
. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
L1
and C
L2
.
For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 32. Typical application with an 8 MHz crystal
Resonator with integrated capacitors
CL1
OSC_IN fHSE
8 MH z resonator
RF
Bias controlled gain
REXT(1)
OSC_OU T
STM32F
CL2 ai17530
1. R
EXT
value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in
. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
98/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Note:
5.3.9
Electrical characteristics
Symbol
Table 32. LSE oscillator characteristics (f
LSE
= 32.768 kHz)
(1)
Parameter Conditions Min Typ Max Unit
R
F
I
DD g m t
SU(LSE)
(2)
Feedback resistor
LSE current consumption
Oscillator Transconductance
-
-
2.8
18.4
-
-
-
1
-
M
Ω
µA
µA/V startup time V
DD
is stabilized 2 -
1. Guaranteed by design, not tested in production.
2. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer s
For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 33. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors
CL1
32.768 kH z resonator
OSC32_IN
RF
Bias controlled gain
OSC32_OU T
CL2 fLSE
STM32F ai17531
Internal clock source characteristics
The parameters given in
are derived from tests performed under
ambient temperature and V
DD
supply voltage conditions summarized in
.
High-speed internal (HSI) RC oscillator
Symbol
f
HSI
ACC
HSI t su(HSI)
(3)
I
DD(HSI)
Table 33. HSI oscillator characteristics
(1)
Parameter Conditions Min Typ Max Unit
Frequency -
User-trimmed with the RCC_CR register
-
Accuracy of the HSI oscillator
Factorycalibrated
T
A
= –40 to
105 °C
(2)
T
A
= –10 to 85 °C
T
A
= 25 °C
–8
–4
–1
HSI oscillator startup time
HSI oscillator power consumption
-
-
16
-
-
-
-
2.2
60
-
1
4.5
4
1
4
80
MHz
%
%
%
%
µs
µA
DocID022152 Rev 4 99/185
Electrical characteristics STM32F405xx, STM32F407xx
1. V
DD
= 3.3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Low-speed internal (LSI) RC oscillator
Symbol
Table 34. LSI oscillator characteristics
(1)
Parameter
f
LSI
(2) t su(LSI)
(3)
I
DD(LSI)
(3)
Frequency
LSI oscillator startup time
LSI oscillator power consumption
1. V
DD
= 3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Min
17
-
-
Typ
32
15
0.4
Figure 34. ACC
LSI
versus temperature
Max
47
40
0.6
Unit
kHz
µs
µA
50
40
30
20
10
0
-10
-20
-30
-40
-45 -35 -25 -15 -5 5 15 25 35
Temperat ure (°C)
45 55 65 75 85 95 105 max avg min
MS19013V1
The parameters given in
are derived from tests performed under
temperature and V
DD
supply voltage conditions summarized in
100/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol
f
PLL_IN f
PLL_OUT f
PLL48_OUT f
VCO_OUT t
LOCK
Jitter
(3)
I
DD(PLL)
(4)
I
DDA(PLL)
(4)
Table 35. Main PLL characteristics
Parameter Conditions Min
PLL input clock
(1)
PLL multiplier output clock
48 MHz PLL multiplier output clock
PLL VCO output
PLL lock time
VCO freq = 192 MHz
VCO freq = 432 MHz
RMS
Cycle-to-cycle jitter
Period Jitter
System clock
120 MHz peak to peak
RMS peak to peak
Cycle to cycle at 50 MHz on 1000 samples
Main clock output (MCO) for
RMII Ethernet
Main clock output (MCO) for MII
Ethernet
Bit Time CAN jitter
PLL power consumption on VDD
PLL power consumption on
VDDA
Cycle to cycle at 25 MHz on 1000 samples
Cycle to cycle at 1 MHz on 1000 samples
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
0.95
(2)
24
192
75
100
-
-
-
-
-
-
-
-
0.15
0.45
0.30
0.55
Typ
48
-
25
-
-
1
-
±150
15
±200
32
40
330
-
-
Max
2.10
168
75
432
200
300
-
-
-
-
-
-
-
0.40
0.75
0.40
0.85
Unit
MHz
MHz
MHz
MHz
µs ps mA mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Based on characterization, not tested in production.
Symbol
f
PLLI2S_IN f
PLLI2S_OUT f
VCO_OUT t
LOCK
Table 36. PLLI2S (audio PLL) characteristics
Parameter Conditions Min
PLLI2S input clock
(1)
PLLI2S multiplier output clock
PLLI2S VCO output
PLLI2S lock time
VCO freq = 192 MHz
VCO freq = 432 MHz
0.95
(2)
-
192
75
100
Typ
1
-
-
-
-
Max
2.10
216
432
200
300
Unit
MHz
MHz
MHz
µs
DocID022152 Rev 4 101/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 36. PLLI2S (audio PLL) characteristics (continued)
Parameter Conditions Min Typ
Jitter
(3)
Master I
WS I
2
2
S clock jitter
S clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
Average frequency of
12.288 MHz
N = 432, R = 5 on 1000 samples
Cycle to cycle at 48 KHz on 1000 samples
RMS
peak to peak
-
-
-
-
I
I
DD(PLLI2S)
(4)
DDA(PLLI2S)
(4)
PLLI2S power consumption on
V
DD
PLLI2S power consumption on
V
DDA
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
0.30
0.55
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Based on characterization, not tested in production.
90
±280
90
400
-
-
Max
-
-
-
-
0.40
0.75
0.40
0.85
Unit
ps ps ps mA mA
5.3.11 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
). It is available only on the main PLL.
Symbol
Table 37. SSCG parameters constraint
Parameter
f
Mod md
Modulation frequency
Peak modulation depth
MODEPER * INCSTEP
1. Guaranteed by design, not tested in production.
Min
-
0.25
-
Typ
-
-
-
Max
(1)
10
2
2
15
−1
Unit
KHz
%
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER
= round f
PLL_IN
⁄ (
Mod
) ] f
PLL_IN and f
Mod must be expressed in Hz.
As an example:
If f
PLL_IN
= 1 MHz, and f
MOD
= 1 kHz, the modulation depth (MODEPER) is given by equation 1:
MODEPER
=
[
6
⁄ ( ×
3
) ]
=
250
102/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP
= round
[ ( (
2
15
–
1
×
MODEPER
) ] f
VCO_OUT must be expressed in MHz.
With a modulation depth (md) =
±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP
= round
[ ( (
2
15
–
1
) 2 240 ⁄ ( × ×
250
) ]
=
126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized
%
=
( ×
100
×
5
) ⁄ ( (
2
15
–
1
) PLLN )
As a result: md quantized
%
=
( × 100 × 5 ) ⁄ ( ( 2
15
–
1 )
=
2.002%(peak)
and
show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
PLL_OUT
nominal.
T mode
is the modulation period.
md is the modulation depth.
Figure 35. PLL output clock waveforms in center spread mode
Frequency (PLL_OUT) md
F0 md tmode
2 x tmode
Time ai17291
DocID022152 Rev 4 103/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 36. PLL output clock waveforms in down spread mode
Frequency (PLL_OUT)
F0
2 x md tmode
2 x tmode
Time ai17292
Symbol
I
DD
Flash memory
The characteristics are given at T
A
=
–
40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Parameter
Supply current
Table 38. Flash memory characteristics
Conditions Min
Write / Erase 8-bit mode, V
DD
= 1.8 V
Write / Erase 16-bit mode, V
DD
= 2.1 V
Write / Erase 32-bit mode, V
DD
= 3.3 V
-
-
-
Typ
5
8
12
Max
-
-
-
Unit
mA
Symbol
t prog
Table 39. Flash memory programming
Parameter Conditions Min
(1)
Word programming time t
ERASE16KB
Sector (16 KB) erase time
Program/erase parallelism
(PSIZE) = x 8/16/32
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
Program/erase parallelism
(PSIZE) = x 32
-
-
-
-
Typ Max
(1)
Unit
16 100
(2)
400
300
250
800
600
500
µs ms
104/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol
Table 39. Flash memory programming (continued)
Parameter Conditions
t
ERASE64KB
Sector (64 KB) erase time
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
Program/erase parallelism
(PSIZE) = x 32
Program/erase parallelism
(PSIZE) = x 8 t
ERASE128KB
Sector (128 KB) erase time
Program/erase parallelism
(PSIZE) = x 16
V t
ME prog
Mass erase time
Programming voltage
Program/erase parallelism
(PSIZE) = x 32
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
Program/erase parallelism
(PSIZE) = x 32
32-bit program operation
16-bit program operation
8-bit program operation
1. Based on characterization, not tested in production.
2. The maximum programming time is measured after 100K erase operations.
Min
(1)
-
-
-
-
-
-
-
-
-
2.7
2.1
1.8
Typ Max
(1)
1200 2400
700 1400
550 1100
2
1.3
1
16
11
8
-
-
-
4
2.6
2
32
22
16
3.6
3.6
3.6
Unit
ms s s
V
V
V
DocID022152 Rev 4 105/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 40. Flash memory programming with V
PP
Parameter Conditions Min
(1)
Typ Max
(1)
t prog t
ERASE16KB t
ERASE64KB t
ERASE128KB t
ME
V prog
V
PP
Double word programming
Sector (16 KB) erase time
Sector (64 KB) erase time
Sector (128 KB) erase time
Mass erase time
Programming voltage
T
A
= 0 to +40 °C
V
DD
V
PP
= 3.3 V
= 8.5 V t
I
PP
VPP
(3)
V
PP
voltage range
Minimum current sunk on the V
PP
pin
Cumulative time during which V
PP is applied
1. Guaranteed by design, not tested in production.
2. The maximum programming time is measured after 100K erase operations.
3. V
PP
should only be connected during programming/erasing.
-
-
-
-
-
-
2.7
7
10
16
230
490
875
6.9
-
-
-
-
100
(2)
-
-
3.6
-
-
9
-
1
Unit
µs ms s
V
V mA hour
Symbol
Table 41. Flash memory endurance and data retention
Value
Parameter Conditions
Min
(1)
N t
END
RET
Endurance
Data retention
T
A
= –40 to +85 °C (6 suffix versions)
T
A
= –40 to +105 °C (7 suffix versions)
1 kcycle
(2)
at T
A
= 85 °C
1 kcycle
(2)
at T
A
= 105 °C
10 kcycles
(2)
at T
A
= 55 °C
1. Based on characterization, not tested in production.
2. Cycling performed over the whole temperature range.
10
30
10
20
Unit
kcycles
Years
106/185
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
A device reset allows normal operations to be resumed.
The test results are given in
. They are based on the EMS levels and classes defined in application note AN1709.
Symbol
Table 42. EMS characteristics
Parameter Conditions
Level/
Class
V
FESD
V
EFTB
Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be applied through 100 pF on V
DD
and V pins to induce a functional disturbance
SS
V
DD
= 3.3 V, LQFP176, T
A f
HCLK
IEC 61000-4-2
= +25 °C,
= 168 MHz, conforms to
V
DD
= 3.3 V, LQFP176, T
A
+25 °C, f
HCLK to IEC 61000-4-2
=
= 168 MHz, conforms
2B
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC
?
code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.
DocID022152 Rev 4 107/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
S
EMI
Parameter
Table 43. EMI characteristics
Conditions
Monitored frequency band
V
DD
= 3.3 V, T
A
= 25 °C, LQFP176 package, conforming to SAE J1752/3
EEMBC, code running from Flash with
ART accelerator enabled
Peak level
V
DD
= 3.3 V, T
A
= 25 °C, LQFP176 package, conforming to SAE J1752/3
EEMBC, code running from Flash with
ART accelerator and PLL spread spectrum enabled
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI level
Max vs.
[f
HSE
/f
CPU
]
25/168 MHz
19
16
18
3.5
32
25
29
4
Unit
dBµV
-
dBµV
5.3.14 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.
Symbol Ratings
Table 44. ESD absolute maximum ratings
Conditions Class
Maximum value
(1)
Unit
V
V
ESD(HBM)
ESD(CDM)
Electrostatic discharge voltage (human body model)
Electrostatic discharge voltage (charge device model)
T
T
A
A
= +25 °C conforming to JESD22-A114
= +25 °C conforming to JESD22-C101
1. Based on characterization results, not tested in production.
2. On V
BAT
pin, V
ESD(HBM) is limited to 1000 V.
2
II
2000
(2)
500
V
Static latchup
Two complementary static tests are required on six parts to assess the latchup performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
108/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Symbol
LU
Parameter
Static latch-up class
Table 45. Electrical sensitivities
Conditions
T
A
= +105 °C conforming to JESD78A
Electrical characteristics
Class
II level A
As a general rule, current injection to the I/O pins, due to external voltage below V
SS above V
DD
or
(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of
5 uA/+0 uA range), or other functional failure (for example reset, oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.
The test results are given in
.
Symbol
Table 46. I/O current injection susceptibility
Functional susceptibility
Description
Negative injection
Positive injection
Unit
I
INJ
(1)
Injected current on all FT pins
Injected current on any other pin
–5
–5
+0
+5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
mA
General input/output characteristics
Unless otherwise specified, the parameters given in
are derived from tests
performed under the conditions summarized in
. All I/Os are CMOS and TTL compliant.
DocID022152 Rev 4 109/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol Parameter
Table 47. I/O static characteristics
Conditions Min Typ Max
V
IL
V
IH
(1)
V
IL
V
Input low level voltage
Input high level voltage
Input low level voltage
Input high level voltage
TTL ports
2.7 V
≤
V
DD
≤
3.6 V
CMOS ports
1.8 V
≤
V
DD
≤
3.6 V
-
2.0
-
0.7V
DD
-
-
-
-
-
200
V hys
I lkg
R
PU
I/O Schmitt trigger voltage hysteresis
(2)
IO FT Schmitt trigger voltage hysteresis
(2)
I/O input leakage current
(4)
I/O FT input leakage current
(4)
Weak pull-up equivalent resistor
(5)
All pins except for
PA10 and
PB12
PA10 and
PB12
V
SS
≤
V
IN
≤
V
DD
V
IN
=
5 V
V
IN
=
V
SS
5% V
DD
(3)
-
-
-
30
8
-
-
-
40
11
-
±1
3
50
15
R
PD
All pins except for
PA10 and
PB12
V
IN
=
V
DD
30 40 50
Weak pull-down equivalent resistor
PA10 and
PB12
8 11 15
C
IO
(6)
I/O pin capacitance 5
1. Tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum
(~10% order)
.
6. Guaranteed by design, not tested in production.
0.8
-
0.3V
DD
-
-
-
Unit
V mV
µA k Ω pF
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters.
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to
±8 mA, and sink or source up to
±20 mA (with a relaxed V
OL
/V
OH
) except PC13, PC14 and PC15 which can sink or source up to
±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
110/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in
. In particular:
•
The sum of the currents sourced by all the I/Os on V
DD,
I consumption of the MCU sourced on V
DD,
VDD
(see
plus the maximum Run cannot exceed the absolute maximum rating
•
The sum of the currents sunk by all the I/Os on V
SS
I consumption of the MCU sunk on V
SS
VSS
(see
).
plus the maximum Run
cannot exceed the absolute maximum rating
Output voltage levels
Unless otherwise specified, the parameters given in
are derived from tests performed under ambient temperature and V
DD
supply voltage conditions summarized in
. All I/Os are CMOS and TTL compliant.
Symbol
Table 48. Output voltage characteristics
(1)
Parameter Conditions Min Max Unit
V
V
V
V
OL
(2)
OH
(3)
OL
OH
(2)
(3)
Output low level voltage for an I/O pin when 8 pins are sunk at same time
Output high level voltage for an I/O pin when 8 pins are sourced at same time
Output low level voltage for an I/O pin when 8 pins are sunk at same time
Output high level voltage for an I/O pin when 8 pins are sourced at same time
V
OL
(2)(4)
Output low level voltage for an I/O pin when 8 pins are sunk at same time
V
OH
(3)(4)
Output high level voltage for an I/O pin when 8 pins are sourced at same time
CMOS port
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
TTL port
I
IO
=+ 8mA
2.7 V < V
DD
< 3.6 V
I
IO
= +20 mA
2.7 V < V
DD
< 3.6 V
V
V
DD
2.4
DD
-
-
-
–0.4
–1.3
0.4
-
-
0.4
-
1.3
V
V
V
V
OL
(2)(4)
Output low level voltage for an I/O pin when 8 pins are sunk at same time
0.4
I
IO
= +6 mA
2 V < V
DD
< 2.7 V
V
DD
–0.4
-
V
V
OH
(3)(4)
Output high level voltage for an I/O pin when 8 pins are sourced at same time
1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
2. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
IO
(I/O ports and control pins) must not exceed I
VDD
.
4. Based on characterization data, not tested in production.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in
DocID022152 Rev 4 111/185
Electrical characteristics STM32F405xx, STM32F407xx
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature and V
DD in
supply voltage conditions summarized
Table 49. I/O AC characteristics
(1)(2)(3)
OSPEEDRy
[1:0] bit value
(1)
Symbol Parameter Conditions Min Typ Max Unit
00 f max(IO)out
Maximum frequency
(4)
C
L
= 50 pF, V
DD >
2.70 V
C
L
= 50 pF, V
DD >
1.8 V
C
L
= 10 pF, V
DD >
2.70 V
C
L
= 10 pF, V
DD >
1.8 V -
-
-
-
-
-
-
2
2
TBD
TBD
MHz t f(IO)out t r(IO)out
Output high to low level fall time
Output low to high level rise time
C
L
= 50 pF, V
DD
= 1.8 V to
3.6 V
-
-
-
TBD
TBD ns
01
10 f max(IO)out
Maximum frequency
(4) t f(IO)out t r(IO)out f max(IO)out
Maximum frequency
(4) t f(IO)out t r(IO)out
Output high to low level fall time
Output low to high level rise time
Output high to low level fall time
Output low to high level rise time
C
L
= 50 pF, V
DD >
2.70 V
C
L
= 50 pF, V
DD >
1.8 V
C
L
= 10 pF, V
DD >
2.70 V
C
L
= 10 pF, V
DD >
1.8 V
C
L
= 50 pF, V
DD
< 2.7 V
C
L
= 10 pF, V
DD
> 2.7 V
C
L
= 50 pF, V
DD
< 2.7 V
C
L
= 10 pF, V
DD
> 2.7 V
C
L
= 40 pF, V
DD >
2.70 V
C
L
= 40 pF, V
DD >
1.8 V
C
L
= 10 pF, V
DD >
2.70 V
C
L
= 10 pF, V
DD >
1.8 V
C
L
= 50 pF,
2.4 < V
DD
< 2.7 V
C
L
= 10 pF, V
DD
> 2.7 V
C
L
= 50 pF,
2.4 < V
DD
< 2.7 V
C
L
= 10 pF, V
DD
> 2.7 V -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
12.5
(5)
50
(5)
TBD
TBD
TBD
TBD
TBD
50
(5)
25
100
(5)
TBD
MHz ns
MHz
TBD
TBD
TBD
TBD ns
112/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 49. I/O AC characteristics
(1)(2)(3)
(continued)
OSPEEDRy
[1:0] bit value
(1)
Symbol Parameter Conditions Min Typ Max
11
F max(IO)ou t t t f(IO)out r(IO)out
Maximum frequency
(4)
Output high to low level fall time
Output low to high level rise time
C
L
= 30 pF, V
DD >
2.70 V
C
L
= 30 pF, V
DD >
1.8 V
C
L
= 10 pF, V
DD >
2.70 V
C
L
= 10 pF, V
DD >
1.8 V
C
L
= 20 pF,
2.4 < V
DD
< 2.7 V
C
L
= 10 pF, V
DD
> 2.7 V
C
L
= 20 pF,
2.4 < V
DD
< 2.7 V
C
L
= 10 pF, V
DD
> 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
(5)
50
(5)
200
(5)
TBD
TBD
TBD
TBD
TBD
t
EXTIpw
Pulse width of external signals detected by the EXTI controller
10 -
1. Based on characterization data, not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. TBD stands for “to be defined”.
4. The maximum frequency is defined in
.
5. For maximum frequencies above 50 MHz, the compensation cell should be used.
-
Unit
MHz ns ns
Figure 37. I/O AC characteristics definition
10%
50%
90% 10%
50%
90%
EXTERNAL
OUTPUT
ON 50pF tr(IO)out
T tr(IO)out
Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF
ai14131
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R
PU
(see
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature and V
DD in
supply voltage conditions summarized
DocID022152 Rev 4 113/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
V
IL(NRST)
(1)
V
IH(NRST)
(1)
V
IL(NRST)
(1)
V
IH(NRST)
(1)
Table 50. NRST pin characteristics
Parameter
NRST Input low level voltage
NRST Input high level voltage
NRST Input low level voltage
NRST Input high level voltage
V hys(NRST)
R
PU
V
F(NRST)
(1)
V
NF(NRST)
(1)
NRST Schmitt trigger voltage hysteresis
Weak pull-up equivalent resistor
(2)
NRST Input filtered pulse
NRST Input not filtered pulse
T
NRST_OUT
Generated reset pulse duration
Conditions
TTL ports
2.7 V ≤ V
DD
≤ 3.6 V
CMOS ports
1.8 V
≤ V
DD
≤ 3.6 V
-
-
2
0.7V
DD
V
IN
=
V
SS
V
DD
> 2.7 V
Internal
Reset source
Min
-
30
-
300
20
Typ
-
-
200
40
-
-
-
Max
0.8
0.3V
DD
-
50
100
-
-
-
-
Unit
mV k
Ω ns ns
µs
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution the series resistance must be minimum
(~10% order)
.
to
V
Figure 38. Recommended NRST pin protection
External reset circuit
(1)
NRST
(2)
VDD
RPU
0.1 μF
Filter
Internal Reset
STM32Fxxx ai14132c
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
. Otherwise the reset is not taken into account by the device.
IL(NRST)
max level specified in
The parameters given in
Section 5.3.16: I/O port characteristics
for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
114/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol
Table 51. Characteristics of TIMx connected to the APB1 domain
(1)
Parameter Conditions Min Max Unit
t t res(TIM) f
EXT
Res
TIM
COUNTER
Timer resolution time
AHB/APB1 prescaler distinct from 1, f
TIMxCLK
84 MHz
=
AHB/APB1 prescaler = 1, f
TIMxCLK
= 42 MHz
1
11.9
1
23.8
Timer external clock frequency on CH1 to CH4
Timer resolution
16-bit counter clock period when internal clock is selected
f
TIMxCLK
= 84 MHz
APB1= 42 MHz
32-bit counter clock period when internal clock is selected
0
0
-
1
0.0119
1
0.0119
-
-
-
f
TIMxCLK
/2
42
16/32
65536
780
-
51130563 t t t t
TIMxCLK ns
TIMxCLK ns
MHz
MHz bit
TIMxCLK
µs
TIMxCLK
µs t
MAX_COUNT
Maximum possible count
-
65536 × 65536
51.1
t
TIMxCLK
1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers.
s
DocID022152 Rev 4 115/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 52. Characteristics of TIMx connected to the APB2 domain
(1)
Parameter Conditions Min Max Unit
t
TIMxCLK t res(TIM)
Timer resolution time
AHB/APB2 prescaler distinct from 1, f
168 MHz
TIMxCLK
=
AHB/APB2 prescaler = 1, f
TIMxCLK
= 84 MHz
1
5.95
1
11.9
-
-
-
t f
EXT
Res
TIM
COUNTER
Timer external clock frequency on CH1 to
CH4
Timer resolution
16-bit counter clock period when internal clock is selected
f
TIMxCLK
=
168 MHz
APB2 = 84 MHz
0
0
-
1 f
TIMxCLK
84
16
65536 t
MAX_COUNT
Maximum possible count 32768
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
/2 ns t
TIMxCLK ns
MHz
MHz bit t
TIMxCLK t
TIMxCLK
I
2
C interface characteristics
The STM32F405xx and STM32F407xx I
2
C interface meets the requirements of the standard I
2
C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V
DD is disabled, but is still present.
The I
2
C characteristics are described in
. Refer also to
Section 5.3.16: I/O port characteristics
for more details on the input/output alternate function characteristics (SDA
and SCL).
Symbol
t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL)
Parameter
Table 53. I
2
C characteristics
Standard mode I
2
C
(1)
Min Max
Fast mode I
2
C
(1)(2)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
4.7
4.0
250
0
(3)
-
-
-
-
Min
1.3
0.6
100
0
Max
-
-
-
900
(4)
SDA and SCL rise time
SDA and SCL fall time -
1000
300
20 + 0.1C
b
-
300
300
Unit
µs ns
116/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol
Table 53. I
2
C characteristics (continued)
Standard mode I
2
C
(1)
Fast mode I
2
C
(1)(2)
Parameter
Min Max Min Max
Unit
t t t h(STA) su(STA) su(STO) t w(STO:STA)
C b
Start condition hold time
Repeated Start condition setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus line
4.0
4.7
4.0
4.7
-
-
-
-
-
400
0.6
0.6 -
0.6
1.3
-
-
-
-
400
µs
μs
μs pF
1. Guaranteed by design, not tested in production.
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I
2 achieve fast mode I clock.
2
C frequencies. It must be at least 4 MHz to
C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I
2
C fast mode
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
Figure 39. I
2
C bus AC waveforms and measurement circuit
V DD_I2C V DD_I2C
I²C bus
R
P
R
P
R
S
R
S
SDA
SCL
STM32Fxx
S T AR T REPEATED
S T AR T
S D A tf(SDA)
SCL tw(SCLH) th(STA) tr(SDA) tw(SCLL) tsu(SDA) th(SDA) tr(SCL) tf(SCL)
1. Rs= series protection resistor.
2. Rp = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
tsu(STA)
S TOP tsu(STO)
S T AR T tw(STO:STA) ai14979c
DocID022152 Rev 4 117/185
Electrical characteristics STM32F405xx, STM32F407xx
Table 54. SCL frequency (f
PCLK1
= 42 MHz.,V
DD
= 3.3 V)
(1)(2)
I2C_CCR value f
SCL
(kHz)
R
P
= 4.7 k
Ω
400 0x8019
300
200
100
50
0x8021
0x8032
0x0096
0x012C
20 0x02EE
1. R
P
= External pull-up resistance, f
SCL
= I
2
C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of tolerance on the achieved speed components used to design the application.
±5%. For other speed ranges, the
SPI interface characteristics
Unless otherwise specified, the parameters given in
for SPI are derived from tests performed under the ambient temperature, f
PCLKx frequency and V
with the following configuration:
DD
supply voltage
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 V
DD
Section 5.3.16: I/O port characteristics
for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Symbol
f
SCK
1/t c(SCK)
Parameter
Table 55. SPI dynamic characteristics
(1)
Conditions Min
SPI clock frequency
Master mode, SPI1,
2.7V < V
DD
< 3.6V
Slave mode, SPI1,
2.7V < V
DD
< 3.6V
Master mode, SPI1/2/3,
1.7V < V
DD
< 3.6V
Slave mode, SPI1/2/3,
1.7V < V
DD
< 3.6V
-
-
Duty(SCK)
Duty cycle of SPI clock frequency
Slave mode 30
Typ
-
-
50
Max
42
42
21
21
70
Unit
MHz
%
118/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
t su(NSS) t h(NSS) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO)
(2)
Symbol
t w(SCKH) t w(SCKL) t dis(SO)
(3) t v(SO) t h(SO) t v(MO) t h(MO)
Table 55. SPI dynamic characteristics
(1)
(continued)
Parameter
SCK high and low time
NSS setup time
NSS hold time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid/hold time
Data output valid time
Data output hold time
Conditions Min Typ Max
Master mode, SPI presc = 2,
2.7V < V
DD
< 3.6V
Master mode, SPI presc = 2,
1.7V < V
DD
< 3.6V
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
Slave mode
Master mode
Slave mode
Slave mode, SPI presc = 2
Slave mode, SPI1,
2.7V < V
DD
< 3.6V
Slave mode, SPI1/2/3
1.7V < V
DD
< 3.6V
Slave mode (after enable edge),
SPI1, 2.7V < V
DD
< 3.6V
Slave mode (after enable edge),
SPI2/3, 2.7V < V
DD
< 3.6V
Slave mode (after enable edge),
SPI1, 1.7V < V
DD
< 3.6V
Slave mode (after enable edge),
SPI2/3, 1.7V < V
DD
< 3.6V
Master mode (after enable edge),
SPI1 , 2.7V < V
DD
< 3.6V
Master mode (after enable edge),
SPI1/2/3 , 1.7V < V
DD
< 3.6V
T
PCLK
-0.5 T
PCLK
T
PCLK
2.5
4
0
0
0
-
-
-
-
-
-
-2 T
4 x T
PCLK
2 x T
PCLK
6.5
2.5
PCLK
-
-
-
-
-
11
12
15.5
18
-
-
-
-
-
T
PCLK
+0.5
T
PCLK
4 x T
-
-
-
-
-
PCLK
7.5
16.5
13
16.5
19
20.5
2.5
4.5
+2
Master mode (after enable edge) 0 -
Unit
ns
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
DocID022152 Rev 4 119/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 40. SPI timing diagram - slave mode and CPHA = 0
NSS input tc(SCK) tSU(NSS)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1 tw(SCKH) tw(SCKL) ta(SO)
MISO
OUT P UT tsu(SI)
MOSI
I NPUT tv(SO)
MS B O UT
M SB IN th(SI) th(SO)
BI T6 OUT
B I T1 IN tr(SCK) tf(SCK)
LSB OUT tdis(SO)
LSB IN th(NSS)
Figure 41. SPI timing diagram - slave mode and CPHA = 1
ai14134c
NSS input tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 tw(SCKH) tw(SCKL)
MISO
OUT P UT ta(SO) tsu(SI)
MOSI
I NPUT tc(SCK) tv(SO)
MS B O UT th(SI)
M SB IN B I T1 IN th(SO)
BI T6 OUT th(NSS) tr(SCK) tf(SCK) tdis(SO)
LSB OUT
LSB IN ai14135
120/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Figure 42. SPI timing diagram - master mode
Electrical characteristics
NSS input
High tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
MOSI
OUTUT tsu(MI) tw(SCKH) tw(SCKL)
MS BIN th(MI)
M SB OUT tv(MO)
BI T6 IN
B I T1 OUT th(MO) tr(SCK) tf(SCK)
LSB IN
LSB OUT ai14136
DocID022152 Rev 4 121/185
Electrical characteristics STM32F405xx, STM32F407xx
I
2
S interface characteristics
Unless otherwise specified, the parameters given in
for the i
2
S interface are derived from tests performed under the ambient temperature, f
PCLKx
frequency and V
supply voltage conditions summarized in
, with the following configuration:
DD
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 V
DD
Section 5.3.16: I/O port characteristics
for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 56. I
2
S dynamic characteristics
(1)
Symbol Parameter Conditions
f
MCK
I
2
S main clock output f
CK
D
CK t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t h(SD_ST) t v(SD_MT) t h(SD_MT)
I
2
S clock frequency
Master data: 32 bits
Slave data: 32 bits
I
2
S clock frequency duty cycle Slave receiver
WS valid time
WS hold time
WS setup time
WS hold time
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Master mode
Master mode
Slave mode
Slave mode
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
1. Data based on characterization results, not tested in production.
2. The maximum value of 256 x F
S
is 42 MHz (APB1 maximum frequency).
256 x
8K
-
0
0
-
30
1
0
7.5
2
0
0
256 x F
S
(2)
-
-
-
-
-
64 x F
S
64 x F
S
70
6
-
-
-
-
2.5
27
20
-
MHz
MHz
% ns
Note: Refer to the I
2
S section of RM0090 reference manual for more details on the sampling frequency (F
S
). f
MCK
, f
CK
, and D
CK
values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. D
CK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV +
ODD). F
S
maximum value is supported for each mode/condition.
122/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Figure 43. I
2
S slave timing diagram (Philips protocol)
tc(CK)
CPOL = 0
CPOL = 1 tw(CKH) tw(CKL) th(WS)
WS input
SDtransmit tsu(WS)
LSB transmit
(2) tsu(SD_SR)
LSB receive
(2)
MSB transmit
MSB receive tv(SD_ST)
Bitn transmit th(SD_SR)
Bitn receive th(SD_ST)
LSB transmit
LSB receive
SDreceive ai14881b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
Figure 44. I
2
S master timing diagram (Philips protocol)
(1)
tf(CK) tr(CK) tc(CK)
CPOL = 0 tw(CKH)
CPOL = 1 tv(WS) tw(CKL) th(WS)
WS output
SDtransmit
LSB transmit
(2) tsu(SD_MR)
LSB receive
(2)
MSB transmit
MSB receive tv(SD_MT)
Bitn transmit th(SD_MR)
Bitn receive th(SD_MT)
LSB transmit
LSB receive
SDreceive ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
USB OTG FS characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
DocID022152 Rev 4 123/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 57. USB OTG FS startup time
Parameter
t
STARTUP
(1)
USB OTG FS transceiver startup time
1. Guaranteed by design, not tested in production.
Max
1
Unit
µs
Symbol
Table 58. USB OTG FS DC electrical characteristics
Parameter Conditions Min.
(1)
Typ. Max.
(1)
Unit
V
DD
USB OTG FS operating voltage
V
DI
(3)
Differential input sensitivity
Input levels
Output levels
R
PD
V
CM
(3)
Differential common mode range
V
SE
(3)
Single ended receiver threshold
V
OL
V
OH
Static output level low
Static output level high
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM)
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
R
PU
PA12, PB15 (USB_FS_DP,
USB_HS_DP)
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
I(USB_FS_DP/DM,
USB_HS_DP/DM)
Includes V
DI range
R
L
of 1.5 k
Ω
to 3.6 V
(4)
R
L
of 15 k
Ω
to V
SS
(4)
V
IN
= V
DD
V
IN
= V
SS
V
IN
= V
SS
3.0
(2)
0.2
0.8
1.3
-
2.8
17
0.65
1.1
1.5
-
-
-
-
-
-
21
1.8
3.6
-
2.5
2.0
0.3
3.6
24
2.0
2.1
0.25
0.37
0.55
k
Ω
1. All the voltages are measured from the local ground potential.
2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full
USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V V
DD
voltage range.
3. Guaranteed by design, not tested in production.
4. R
L
is the load connected on the USB OTG FS drivers
V
V
V
Figure 45. USB OTG FS timings: definition of data signal rise and fall time
Crossover points
Differen tial
Data L ines
VCRS
VS S tf tr ai14137
124/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 59. USB OTG FS electrical characteristics
(1)
Driver characteristics
Symbol Parameter Conditions Min Max
t r t f t rfm
V
CRS
Rise time
Fall time
(2)
(2)
Rise/ fall time matching
Output signal crossover voltage
C
L
C
L
= 50 pF
= 50 pF t r
/t f
4
4
90
1.3
20
20
110
2.0
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
Unit
ns ns
%
V
USB HS characteristics
Unless otherwise specified, the parameters given in
for ULPI are derived from tests performed under the ambient temperature, f
HCLK and V
DD
supply voltage conditions summarized in
, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5V
DD
.
Refer to Section
Section 5.3.16: I/O port characteristics
input/outputcharacteristics.
Symbol
Table 60. USB HS DC electrical characteristics
Parameter
Input level V
DD
USB OTG HS operating voltage
1. All the voltages are measured from the local ground potential.
Min.
(1)
2.7
Max.
(1)
3.6
Unit
V
Table 61. USB HS clock timing parameters
(1)
Parameter Symbol Min Nominal Max
f
HCLK
value to guarantee proper operation of
USB HS interface
Frequency (first transition) 8-bit ±10%
Frequency (steady state) ±500 ppm
Duty cycle (first transition) 8-bit ±10%
Duty cycle (steady state) ±500 ppm
F
START_8BIT
F
STEADY
D
START_8BIT
D
STEADY
Time to reach the steady state frequency and duty cycle after the first transition
T
STEADY
Clock startup time after the de-assertion of SuspendM
Peripheral
Host
T
START_DEV
T
START_HOST
PHY preparation time after the first transition of the input clock
T
PREP
30
54
59.97
40
49.975
-
-
-
-
60
60
50
50
-
-
-
-
Unit
MHz
66 MHz
60.03
MHz
60 %
50.025
%
1.4
5.6
-
ms ms
µs
DocID022152 Rev 4 125/185
Electrical characteristics STM32F405xx, STM32F407xx
1. Guaranteed by design, not tested in production.
Table 62. ULPI timing
Parameter Symbol
Control in (ULPI_DIR) setup time
Control in (ULPI_NXT) setup time
Control in (ULPI_DIR, ULPI_NXT) hold time
Data in setup time
Data in hold time
Control out (ULPI_STP) setup time and hold time
Data out available from clock rising edge
1. V
DD
= 2.7 V to 3.6 V and T
A
= –40 to 85 °C.
t
SC
t
HC t
SD t
HD t
DC t
DD
Figure 46. ULPI timing diagram
Min.
0
-
-
0
-
-
-
Value
(1)
Max.
2.0
1.5
-
2.0
-
9.2
10.7
Unit
ns
Clock tSC tSD tHC
Control In
(ULPI_DIR,
ULPI_NXT) data In
(8-bit) tHD tDC tDC
Control out
(ULPI_STP) data out
(8-bit) tDD ai17361c
Ethernet characteristics
Unless otherwise specified, the parameters given in
,
SMI, RMII and MII are derived from tests performed under the ambient temperature, f
HCLK frequency summarized in
and VDD supply voltage conditions summarized in
, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5V
DD
.
Section 5.3.16: I/O port characteristics
for more details on the input/output
characteristics.
126/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol
Table 63. Ethernet DC electrical characteristics
Parameter
Input level V
DD
Ethernet operating voltage
1. All the voltages are measured from the local ground potential.
Min.
(1)
2.7
Max.
(1)
3.6
Unit
V
gives the list of Ethernet MAC signals for the SMI (station management interface) and
shows the corresponding timing diagram.
Figure 47. Ethernet SMI timing diagram
tMDC
ETH_MDC td(MDIO)
ETH_MDIO(O) tsu(MDIO) th(MDIO)
ETH_MDIO(I)
MS31384V1
Symbol
Table 64. Dynamic characteristics: Ehternet MAC signals for SMI
(1)
Parameter Min Typ Max
t
MDC
T d(MDIO) t su(MDIO) t h(MDIO)
MDC cycle time( 2.38 MHz)
Write data valid time
Read data setup time
Read data hold time
411
6
12
0
1. Data based on characterization results, not tested in production.
420
10
-
-
425
13
-
-
gives the list of Ethernet MAC signals for the RMII and
corresponding timing diagram.
Figure 48. Ethernet RMII timing diagram
Unit
ns
RMII_REF_CLK t d(TXEN) t d(TXD)
RMII_TX_EN
RMII_TXD[1:0] t su(RXD) t su(CRS)
RMII_RXD[1:0]
RMII_CRS_DV t ih(RXD) t ih(CRS) ai15667
DocID022152 Rev 4 127/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 65. Dynamic characteristics: Ethernet MAC signals for RMII
Rating Min Typ Max
t su(RXD) t ih(RXD) t su(CRS) t ih(CRS) t d(TXEN) t d(TXD)
Receive data setup time
Receive data hold time
Carrier sense set-up time
Carrier sense hold time
Transmit enable valid delay time
Transmit data valid delay time
2
1
0.5
2
8
8.5
-
-
-
-
9.5
10
-
-
-
-
11
11.5
gives the list of Ethernet MAC signals for MII and
corresponding timing diagram.
Figure 49. Ethernet MII timing diagram
Unit
ns ns ns ns ns ns
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER t su(RXD) t su(ER) t su(DV)
MII_TX_CLK t ih(RXD) t ih(ER) t ih(DV) t d(TXEN) t d(TXD)
MII_TX_EN
MII_TXD[3:0] ai15668
Symbol
Table 66. Dynamic characteristics: Ethernet MAC signals for MII
(1)
Parameter Min Typ Max
t su(RXD) t ih(RXD) t su(DV) t ih(DV) t su(ER) t ih(ER) t d(TXEN) t d(TXD)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
Error setup time
Error hold time
Transmit enable valid delay time
Transmit data valid delay time
9
10
9
8
6
8
0
0
1. Data based on characterization results, not tested in production.
10
10
14
15
-
-
-
-
-
-
Unit
ns
128/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
CAN (controller area network) interface
Section 5.3.16: I/O port characteristics
for more details on the input/output alternate
function characteristics (CANTX and CANRX).
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
.
PCLK2 frequency and V
DDA
supply voltage
Symbol
V
DDA
V
REF+ f
ADC f
TRIG
(4)
V
AIN
R
AIN
(4)
Parameter
Power supply
Positive reference voltage
ADC clock frequency
External trigger frequency
Conversion voltage range
(5)
Table 67. ADC characteristics
Conditions Min
1.8
(1)
1.8
(1)(2)(3)
V
DDA
= 1.8
(1)(3)
to
2.4 V
V
DDA
= 2.4 to 3.6 V
(3) f
ADC
= 30 MHz,
12-bit resolution
0.6
0.6
-
-
0 (V
SSA or V
REFtied to ground)
External input impedance
See
Equation 1
for details
-
R
ADC
(4)(6)
Sampling switch resistance
C
ADC
(4)
Internal sample and hold capacitor
-
t lat
(4) t latr
(4) t
S
(4) t
STAB
(4)
Injection trigger conversion latency
Regular trigger conversion latency
Sampling time
Power-up time f
ADC
= 30 MHz f
ADC
= 30 MHz f
ADC
= 30 MHz
-
-
-
-
0.100
3
-
15
-
-
Typ
-
-
30
-
-
-
4
-
-
-
-
-
-
2
Max
3.6
V
DDA
18
36
1764
17
V
REF+
50
6
-
0.100
3
(7)
0.067
2
(7)
16
480
3
Unit
V
V
MHz
MHz kHz
1/f
ADC
V
κΩ
κΩ pF
µs
1/f
ADC
µs
1/f
ADC
µs
1/f
ADC
µs
DocID022152 Rev 4 129/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol Parameter
Table 67. ADC characteristics (continued)
Conditions Min Typ Max Unit
t
CONV
(4) f
ADC
= 30 MHz
12-bit resolution f
ADC
= 30 MHz
10-bit resolution
0.50
0.43
-
16.40
16.34
Total conversion time (including sampling time) f
ADC
= 30 MHz
8-bit resolution f
ADC
= 30 MHz
6-bit resolution
0.37
0.30
-
16.27
16.20
9 to 492 (t
S
for sampling +n-bit resolution for successive approximation)
1/f
µs
µs
µs
µs
ADC f
S
(4)
Sampling rate t
(f
ADC
S
= 30 MHz, and
= 3 ADC cycles)
12-bit resolution
Single ADC
12-bit resolution
Interleave Dual ADC mode
-
-
-
-
2
3.75
Msps
Msps
12-bit resolution
Interleave Triple ADC mode
6 Msps
I
I
VREF+
(4)
VDDA
(4)
ADC V
REF
DC current consumption in conversion mode
ADC V
DDA
DC current consumption in conversion mode
-
300
1.6
500
1.8
µA mA
1. V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF
).
2. It is recommended to maintain the voltage difference between V
REF+
and V
DDA below 1.8 V.
3. V
DDA
-V
REF+
< 1.2 V.
4. Based on characterization, not tested in production.
5. V
REF+
is internally connected to V
DDA
and V
REF-
is internally connected to V
SSA
.
6. R
ADC
maximum value is given for V
DD
=1.8 V, and minimum value for V
DD
=3.3 V.
7. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in
.
Equation 1: R
AIN
max formula
R
AIN
= f
ADC
×
(
C k 0.5
ADC
× ln
)
( 2
N +
)
–
R
ADC
The formula above (
Equation 1
) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.
130/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Note:
Electrical characteristics
a
Symbol
Table 68. ADC accuracy at f
ADC
= 30 MHz
(1)
Parameter Test conditions Typ Max
(2)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error f
PCLK2 f
ADC
= 60 MHz,
= 30 MHz, R
AIN
V
DDA
= 1.8
(3)
< 10 k
to 3.6 V
Ω,
±2
±1.5
±1.5
±1
±1.5
±5
±2.5
±3
±2
±3
LSB
1. Better performance could be achieved in restricted V
DD
, frequency and temperature ranges.
2. Based on characterization, not tested in production.
3. V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF
).
ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
does not affect the ADC accuracy.
INJ(PIN)
and
ΣI
INJ(PIN)
in
Figure 50. ADC accuracy characteristics
[1LSB IDEAL =
V REF+
4096
V DDA
(or depending on package)]
4096
EG
4095
4094
4093
(2)
ET
(3)
7
4
3
6
5
2
1
EO
EL
1L SBIDEAL
ED
(1)
0
VSSA
1 2 3 456 7
4093 4094 4095 4096
VDDA ai14395c
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. E
T
= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
DocID022152 Rev 4 131/185
Electrical characteristics STM32F405xx, STM32F407xx
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Figure 51. Typical connection diagram using the ADC
VAIN
RAIN(1)
AINx
Cparasitic
VDD
VT
0.6 V
VT
0.6 V
IL±1 µA
STM32F
Sample and hold ADC converter
RADC(1)
12-bit converter
CADC(1) ai17534
AIN
, R
ADC
and C
ADC
.
2. C f pad capacitance (roughly 5 pF). A high C
ADC
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
should be reduced.
parasitic
value downgrades conversion accuracy. To remedy this,
132/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in
or
, depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 52. Power supply and reference decoupling (V
REF+ not connected to
V
DDA
)
STM32F
V REF+
(See note 1)
1 µF // 10 nF
V DDA
1 µF // 10 nF
V SSA/V REF-
(See note 1) ai17535
1. V
REF+
and V
REF– inputs are both available on UFBGA176. V
REF+
and V
REF–
REF+ is also available on LQFP100, LQFP144, are not available, they are internally connected to V
DDA and V
SSA
.
Figure 53. Power supply and reference decoupling (V
REF+ connected to
V
DDA
)
STM32F
V
REF+
/V
DDA
(See note 1)
1 µF // 10 nF
V
REF–
/V
SSA
(See note 1) ai17536
1. V
REF+
and V
REF– inputs are both available on UFBGA176. V
REF+
and V
REF–
REF+ is also available on LQFP100, LQFP144, are not available, they are internally connected to V
DDA and V
SSA
.
DocID022152 Rev 4 133/185
Electrical characteristics STM32F405xx, STM32F407xx
5.3.21 Temperature sensor characteristics
Symbol
Table 69. Temperature sensor characteristics
Parameter Min Typ Max
T
L
(1)
Avg_Slope
(1)
V
25
(1) t
START
(2)
T
S_temp
(3)(2)
V
SENSE
linearity with temperature
Average slope
Voltage at 25 °C
Startup time
ADC sampling time when reading the temperature (1 °C accuracy)
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
-
-
-
-
10
±1
2.5
0.76
6
-
±2
10
-
Unit
°C mV/°C
V
µs
µs
Symbol
Table 70. Temperature sensor calibration values
Parameter Memory address
TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V
DDA
=3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V
DDA
=3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
5.3.22 V
BAT
monitoring characteristics
Symbol
Table 71. V
BAT
monitoring characteristics
Parameter Min
T
R
Q
Er
(1)
S_vbat
(2)(2)
Resistor bridge for V
BAT
Ratio on V
BAT
measurement
Error on Q
ADC sampling time when reading the V
BAT
1 mV accuracy
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
-
-
–1
5
Typ
50
2
-
-
Max
-
-
+1
-
Unit
K Ω
%
µs
134/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
The parameters given in
are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Symbol
Table 72. Embedded internal reference voltage
Parameter Conditions Min Typ Max
T
V
REFINT
S_vrefint
(1)
Internal reference voltage
ADC sampling time when reading the internal reference voltage
–40 °C < T
A
< +105 °C 1.18 1.21
V
RERINT_s
(2)
Internal reference voltage spread over the temperature range
V
DD
= 3 V
T
Coeff
(2) t
START
(2)
Temperature coefficient
Startup time
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
10
-
-
-
-
3
30
6
-
1.24
5
50
10
Unit
V
µs mV ppm/°C
µs
Symbol
V
REFIN_CAL
Table 73. Internal reference voltage calibration values
Parameter Memory address
Raw data acquired at temperature of 30 °C, V
DDA
=3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B
Symbol
V
DDA
V
REF+
V
SSA
R
LOAD
(2)
R
O
(2)
C
LOAD
(2)
Parameter
Analog supply voltage
Reference supply voltage
Ground
Resistive load with buffer
ON
Table 74. DAC characteristics
Min Typ Max Unit
1.8
(1)
1.8
(1)
0 -
-
3.6
3.6
0
Comments
V
V V
REF+
≤ V
DDA
V
5 k
Ω
Impedance output with buffer OFF
Capacitive load
DAC_OUT min
(2)
Lower DAC_OUT voltage with buffer ON
DAC_OUT max
(2)
Higher DAC_OUT voltage with buffer ON
-
-
-
-
0.2 -
-
15
50
-
V
DDA
– 0.2 k Ω pF
V
V
When the buffer is OFF, the
Minimum resistive load between
DAC_OUT and V
SS accuracy is 1.5 M
Ω
to have a 1%
Maximum capacitive load at
DAC_OUT pin (when the buffer is
ON).
It gives the maximum output excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at V
REF+
=
3.6 V and (0x1C7) to (0xE38) at
V
REF+
= 1.8 V
DocID022152 Rev 4 135/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol Parameter
Table 74. DAC characteristics (continued)
DAC_OUT min
(2)
Lower DAC_OUT voltage with buffer OFF
DAC_OUT max
(2)
Higher DAC_OUT voltage with buffer OFF
Min Typ
-
0.5
Max
-
Unit
mV
V
REF+
– 1LSB V
Comments
It gives the maximum output excursion of the DAC.
I
VREF+
(4)
I
DDA
(4)
DAC DC V
REF
current consumption in quiescent mode (Standby mode)
DAC DC VDDA current consumption in quiescent mode
(3)
-
-
-
170
50
280
475
240
75
380
625
µA
µA
µA
With no load, worst code (0x800) at V
REF+
= 3.6 V in terms of DC consumption on the inputs
With no load, worst code (0xF1C) at V
REF+
= 3.6 V in terms of DC consumption on the inputs
With no load, middle code (0x800) on the inputs
With no load, worst code (0xF1C) at V
REF+
= 3.6 V in terms of DC consumption on the inputs
DNL
(4)
INL
(4)
Differential non linearity
Difference between two consecutive code-1LSB)
Integral non linearity
(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)
-
-
-
-
-
-
-
±0.5
±2
±1
±4
LSB
Given for the DAC in 10-bit configuration.
LSB
LSB
Given for the DAC in 12-bit configuration.
Given for the DAC in 10-bit configuration.
LSB
Given for the DAC in 12-bit configuration.
Offset
(4)
Offset error
(difference between measured value at Code
(0x800) and the ideal value
= V
REF+
/2)
-
-
-
-
-
-
-
±10
±3
±12
±0.5
mV
LSB
LSB
%
Given for the DAC in 12-bit configuration
Given for the DAC in 10-bit at
V
REF+
= 3.6 V
Given for the DAC in 12-bit at
V
REF+
= 3.6 V
Given for the DAC in 12-bit configuration
Gain error
(4)
THD
(4)
Gain error t
SETTLING
(4)
Settling time (full scale: for a
10-bit input code transition between the lowest and the highest input codes when
DAC_OUT reaches final value ±4LSB
Total Harmonic Distortion
Buffer ON
-
3
-
6
-
µs dB
C
LOAD
R
LOAD
≤ 50 pF,
≥ 5 kΩ
C
LOAD
R
LOAD
≤ 50 pF,
≥ 5 kΩ
136/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Symbol Parameter
Table 74. DAC characteristics (continued)
Min Typ Max Unit Comments
Update rate
(2) t
WAKEUP
(4)
PSRR+
(2)
Max frequency for a correct
DAC_OUT change when small variation in the input code (from code i to i+1LSB)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
Power supply rejection ratio
(to V
DDA
) (static DC measurement)
-
-
-
6.5
1
10
–67 –40
MS/s
µs dB
C
LOAD
R
LOAD
C
LOAD
≤ 50 pF,
≥ 5 kΩ
≤ 50 pF, R
LOAD
≥ 5 kΩ input code between lowest and highest possible ones.
No , C
LOAD
= 50 pF
1. V
DD
/V
DDA
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF
).
2. Guaranteed by design, not tested in production.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.
4. Guaranteed by characterization, not tested in production.
Figure 54. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
LOAD
12-bit digital to analog converter
DACx_OUT
C
LOAD ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.
Unless otherwise specified, the parameters given in
for the FSMC interface are derived from tests performed under the ambient temperature, f
HCLK and V
DD
frequency
supply voltage conditions summarized in
, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section
Section 5.3.16: I/O port characteristics
for more details on the input/output
characteristics.
DocID022152 Rev 4 137/185
Electrical characteristics STM32F405xx, STM32F407xx
Asynchronous waveforms and timings
represent asynchronous waveforms and
provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
AddressSetupTime = 1
•
AddressHoldTime = 0x1
•
DataSetupTime = 0x1
•
BusTurnAroundDuration = 0x0
In all timing tables, the
T
HCLK
is the HCLK clock period.
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t w(NE)
FSMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)
FSMC_NOE
138/185
FSMC_NWE t v(A_NE) t h(A_NOE)
FSMC_A[25:0]
Address t v(BL_NE) t h(BL_NOE)
FSMC_NBL[1:0] t su(Data_NOE) t su(Data_NE)
Data t h(Data_NE) t h(Data_NOE)
FSMC_D[15:0] t v(NADV_NE) t w(NADV)
FSMC_NADV
(1) ai14991c
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1)(2)
Symbol Parameter Min Max Unit
t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE)
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
2T
HCLK
–0.5 2 T
HCLK
+1 ns
0.5
3 ns
2T
HCLK
–2 2T
HCLK
+ 2 ns
0 ns
4.5
ns
4 ns
DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1)(2)
t v(BL_NE)
FSMC_NEx low to FSMC_BL valid 1.5
ns
FSMC_BL hold time after FSMC_NOE high 0 ns t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)
Data to FSMC_NEx high setup time
Data to FSMC_NOEx high setup time
Data hold time after FSMC_NOE high
Data hold time after FSMC_NEx high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
T
HCLK
+4 -
T
HCLK
0
+4 -
-
-
-
0 -
2
T
HCLK ns ns ns ns ns ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t w(NE)
FSMC_NEx
FSMC_NOE t v(NWE_NE) t w(NWE) t h(NE_NWE)
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[1:0] t v(A_NE) t v(BL_NE) t v(Data_NE) t h(A_NWE)
Address t h(BL_NWE)
NBL t h(Data_NWE)
Data
FSMC_D[15:0] t v(NADV_NE) t w(NADV)
FSMC_NADV
(1) ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
(1)(2)
Symbol Parameter Min Max Unit
t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE)
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
3T
HCLK
3T
HCLK
+ 4 ns
T
HCLK
–0.5
T
HCLK
+0.5
ns
T
T
HCLK
–1
HCLK
–1
-
T
HCLK
+2 ns
ns
0 ns
DocID022152 Rev 4 139/185
Electrical characteristics STM32F405xx, STM32F407xx
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
(1)(2)
t h(A_NWE)
Address hold time after FSMC_NWE high T
HCLK
– 2 ns
FSMC_NEx low to FSMC_BL valid 1.5
ns t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)
FSMC_BL hold time after FSMC_NWE high
Data to FSMC_NEx low to Data valid
Data hold time after FSMC_NWE high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
T
HCLK
– 1
-
T
HCLK
–1
-
-
-
T
HCLK
+3 ns
ns
2 ns ns
T
HCLK
+0.5
ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms
t w(NE)
FSMC_NE t v(NOE_NE) t h(NE_NOE)
FSMC_NOE t w(NOE)
FSMC_NWE t v(A_NE) t h(A_NOE)
FSMC_A[25:16]
Address t v(BL_NE) t h(BL_NOE)
FSMC_NBL[1:0]
NBL t h(Data_NE)
FSMC_AD[15:0] t v(A_NE)
Address t v(NADV_NE) t w(NADV) t h(AD_NADV) t su(Data_NE) t su(Data_NOE)
Data t h(Data_NOE)
FSMC_NADV ai14892b
Table 77. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
Symbol Parameter Min Max
t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE)
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
3T
HCLK
–1 3T
HCLK
+1
2T
HCLK
–0.5
2T
HCLK
+0.5
T
HCLK
–1
0
T
HCLK
-
+1
3
Unit
ns ns ns ns ns
140/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 77. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
(continued)
t v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 1 2 ns t w(NADV)
FSMC_NADV low time T
HCLK
– 2 T
HCLK
+1 ns t h(AD_NADV)
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
T
HCLK
ns
ns t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)
Address hold time after FSMC_NOE high
FSMC_BL time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
Data to FSMC_NEx high setup time
Data to FSMC_NOE high setup time
Data hold time after FSMC_NEx high
Data hold time after FSMC_NOE high
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
T
HCLK
–1
0
-
T
HCLK
+4
T
HCLK
+4
0
0
-
-
-
-
-
2 ns ns ns ns ns ns
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
t w(NE)
FSMC_NEx
FSMC_NOE t v(NWE_NE) t w(NWE) t h(NE_NWE)
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0] t v(A_NE) t v(BL_NE) t v(A_NE)
Address t v(NADV_NE) t w(NADV) t h(A_NWE)
Address t h(BL_NWE)
NBL t v(Data_NADV)
Data t h(AD_NADV) t h(Data_NWE)
FSMC_NADV ai14891B
Table 78. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
Symbol
t w(NE) t v(NWE_NE) t w(NWE)
Parameter
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low tim e
Min Max Unit
4T
HCLK
–0.5
4T
HCLK
+3 ns
T
HCLK
–0.5
T
HCLK
-0.5
ns
2T
HCLK
–0.5
2T
HCLK
+3 ns
DocID022152 Rev 4 141/185
Electrical characteristics STM32F405xx, STM32F407xx
Table 78. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
t h(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time T
HCLK
-
FSMC_NEx low to FSMC_A valid 0 t v(A_NE) t v(NADV_NE) t w(NADV)
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
1
T
HCLK
– 2
2
T
HCLK
+ 1 t h(AD_NADV)
FSMC_AD(address) valid hold time after
FSMC_NADV high)
T
HCLK
–2 t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)
Address hold time after FSMC_NWE high
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_NADV high to Data valid
Data hold time after FSMC_NWE high
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
T
HCLK
T
HCLK
–2
-
-
T
HCLK
-
-
1.5
T
HCLK
–0.5
ns ns ns ns ns ns ns ns ns ns
Synchronous waveforms and timings
represent synchronous waveforms and
through
provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
•
MemoryType = FSMC_MemoryType_CRAM;
•
WriteBurst = FSMC_WriteBurst_Enable;
•
CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the
T
HCLK
FSMC_CLK = 60 MHz).
is the HCLK clock period (with maximum
142/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Figure 59. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
BUSTURN = 0
FSMC_CLK
Data latency = 0 td(CLKL-NExL) td(CLKL-NExH)
FSMC_NEx td(CLKL-NADVL)
FSMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV)
FSMC_A[25:16] td(CLKL-NOEL) td(CLKL-NOEH)
FSMC_NOE td(CLKL-ADV)
FSMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)
AD[15:0] tsu(NWAITV-CLKH)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
D1 tsu(ADV-CLKH) tsu(NWAITV-CLKH) th(CLKH-ADV)
D2 th(CLKH-NWAITV) th(CLKH-ADV) th(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893g
Table 79. Synchronous multiplexed NOR/PSRAM read timings
(1)(2)
Symbol Parameter Min Max
t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NOEL) t d(CLKL-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV) t su(ADV-CLKH)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
FSMC_CLK low to FSMC_NEx high (x= 0…2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NOE low
FSMC_CLK low to FSMC_NOE high
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid data before FSMC_CLK high
0
-
2
-
2T
HCLK
-
2
-
0
6
2
-
-
0
-
0
-
2
0
-
-
4.5
-
-
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
DocID022152 Rev 4 143/185
Electrical characteristics STM32F405xx, STM32F407xx
Table 79. Synchronous multiplexed NOR/PSRAM read timings
(1)(2)
(continued)
t h(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high 0 ns t su(NWAIT-CLKH) t h(CLKH-NWAIT)
FSMC_NWAIT valid before FSMC_CLK high
FSMC_NWAIT valid after FSMC_CLK high
4
0 -
ns ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
FSMC_CLK
Figure 60. Synchronous multiplexed PSRAM write timings
tw(CLK) tw(CLK)
BUSTURN = 0
Data latency = 0 td(CLKL-NExL) td(CLKL-NExH)
FSMC_NEx td(CLKL-NADVL)
FSMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV)
FSMC_A[25:16] td(CLKL-NWEL) td(CLKL-NWEH)
FSMC_NWE td(CLKL-ADV)
FSMC_AD[15:0] td(CLKL-ADIV) td(CLKL-Data)
AD[15:0] td(CLKL-Data)
D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH)
FSMC_NBL ai14992g
Symbol
Table 80. Synchronous multiplexed PSRAM write timings
(1)(2)
Parameter Min Max Unit
t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
FSMC_CLK low to FSMC_NEx high (x= 0…2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x=16…25)
2T
HCLK
-
1
-
0
-
-
0
-
1
-
0 ns ns ns ns ns ns
144/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
t d(CLKL-AIV)
Table 80. Synchronous multiplexed PSRAM write timings
(1)(2)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8
FSMC_CLK low to FSMC_NWE low -
-
0.5
t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)
FSMC_CLK low to FSMC_NWE high
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid data after FSMC_CLK low
FSMC_CLK low to FSMC_NBL high
FSMC_NWAIT valid before FSMC_CLK high
FSMC_NWAIT valid after FSMC_CLK high
0
0
-
0
4
0
-
-
3
-
-
-
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
ns ns ns ns ns ns ns ns
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings
FSMC_CLK tw(CLK) tw(CLK)
BUSTURN = 0 td(CLKL-NExL)
FSMC_NEx
Data latency = 0 td(CLKL-NExH) td(CLKL-NADVL)
FSMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV)
FSMC_A[25:0] td(CLKL-NOEL) td(CLKL-NOEH)
FSMC_NOE tsu(DV-CLKH)
FSMC_D[15:0] tsu(NWAITV-CLKH)
D1 th(CLKH-DV) tsu(DV-CLKH)
D2 th(CLKH-NWAITV) th(CLKH-DV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894f
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
Symbol Parameter Min Max
t w(CLK) t d(CLKL-NExL)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
2T
HCLK
–0.5
-
-
0.5
Unit
ns ns
DocID022152 Rev 4 145/185
Electrical characteristics STM32F405xx, STM32F407xx
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
(continued)
t d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 ns
FSMC_CLK low to FSMC_NADV low 2 ns t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NOEL) t d(CLKL-NOEH) t su(DV-CLKH) t h(CLKH-DV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NOE low
FSMC_CLK low to FSMC_NOE high
FSMC_D[15:0] valid data before FSMC_CLK high
FSMC_D[15:0] valid data after FSMC_CLK high
FSMC_NWAIT valid before FSMC_CLK high
FSMC_NWAIT valid after FSMC_CLK high
3
-
2
-
1.5
6
3
4
0
-
0
-
0.5
-
-
-
-
ns ns ns ns ns ns ns ns ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Figure 62. Synchronous non-multiplexed PSRAM write timings
FSMC_CLK tw(CLK) tw(CLK)
BUSTURN = 0 td(CLKL-NExL)
FSMC_NEx td(CLKL-NADVL)
FSMC_NADV
Data latency = 0 td(CLKL-NADVH) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV)
FSMC_A[25:0] td(CLKL-NWEL) td(CLKL-NWEH)
FSMC_NWE
FSMC_D[15:0] td(CLKL-Data)
D1 td(CLKL-Data)
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH)
FSMC_NBL td(CLKL-NBLH) th(CLKH-NWAITV) ai14993g
146/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 82. Synchronous non-multiplexed PSRAM write timings
(1)(2)
Symbol
t w(CLK) t d(CLKL-NExL)
Parameter
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t d(CLKL-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)
FSMC_CLK low to FSMC_NEx high (x= 0…2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NWE low
FSMC_CLK low to FSMC_NWE high
FSMC_D[15:0] valid data after FSMC_CLK low
FSMC_CLK low to FSMC_NBL high
FSMC_NWAIT valid before FSMC_CLK high
FSMC_NWAIT valid after FSMC_CLK high
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Min
2T
HCLK
-
2
-
6
-
6
-
1
-
3
4
0
Max Unit
-
1 ns ns
-
3
-
1
-
0
-
7
-
-
ns ns ns ns ns ns ns ns ns ns ns
PC Card/CompactFlash controller waveforms and timings
represent synchronous waveforms, and
and
provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:
•
COM.FSMC_SetupTime = 0x04;
• COM.FSMC_WaitSetupTime = 0x07;
•
COM.FSMC_HoldSetupTime = 0x04;
• COM.FSMC_HiZSetupTime = 0x00;
•
ATT.FSMC_SetupTime = 0x04;
• ATT.FSMC_WaitSetupTime = 0x07;
•
ATT.FSMC_HoldSetupTime = 0x04;
• ATT.FSMC_HiZSetupTime = 0x00;
•
IO.FSMC_SetupTime = 0x04;
• IO.FSMC_WaitSetupTime = 0x07;
•
IO.FSMC_HoldSetupTime = 0x04;
• IO.FSMC_HiZSetupTime = 0x00;
•
TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the
T
HCLK
is the HCLK clock period.
DocID022152 Rev 4 147/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 63. PC Card/CompactFlash controller waveforms for common memory read access
FSMC_NCE4_2
(1)
FSMC_NCE4_1 tv(NCEx-A) th(NCEx-AI)
FSMC_A[10:0] td(NREG-NCEx) td(NIORD-NCEx) th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE td(NCE4_1-NOE)
FSMC_NOE tw(NOE) tsu(D-NOE) th(NOE-D)
FSMC_D[15:0] ai14895b
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
Figure 64. PC Card/CompactFlash controller waveforms for common memory write access
FSMC_NCE4_1
FSMC_NCE4_2
High
FSMC_A[10:0] tv(NCE4_1-A)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD td(NCE4_1-NWE)
FSMC_NWE td(NREG-NCE4_1) td(NIORD-NCE4_1) tw(NWE)
FSMC_NOE
MEMxHIZ =1 td(D-NWE) tv(NWE-D) th(NCE4_1-AI) th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NWE-NCE4_1) th(NWE-D)
FSMC_D[15:0] ai14896b
148/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access
FSMC_NCE4_1 tv(NCE4_1-A) th(NCE4_1-AI)
FSMC_NCE4_2
High
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
FSMC_NREG
FSMC_NWE td(NCE4_1-NOE)
FSMC_NOE td(NREG-NCE4_1) tw(NOE) tsu(D-NOE)
FSMC_D[15:0]
(1) th(NCE4_1-NREG) th(NOE-D) td(NOE-NCE4_1) ai14897b
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
DocID022152 Rev 4 149/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access
FSMC_NCE4_1
FSMC_NCE4_2
High tv(NCE4_1-A) th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
FSMC_NREG td(NCE4_1-NWE)
FSMC_NWE td(NREG-NCE4_1) tw(NWE) td(NWE-NCE4_1) th(NCE4_1-NREG)
FSMC_NOE tv(NWE-D)
FSMC_D[7:0](1) ai14898b
1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).
Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access
FSMC_NCE4_1
FSMC_NCE4_2 tv(NCEx-A) th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR td(NIORD-NCE4_1)
FSMC_NIORD tw(NIORD) tsu(D-NIORD) td(NIORD-D)
FSMC_D[15:0] ai14899B
150/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access
FSMC_NCE4_1
FSMC_NCE4_2 tv(NCEx-A) th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIORD td(NCE4_1-NIOWR)
FSMC_NIOWR tw(NIOWR)
ATTxHIZ =1 th(NIOWR-D) tv(NIOWR-D)
FSMC_D[15:0] ai14900c
Symbol
Table 83. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space
(1)(2)
Parameter Min Max
t t v(NCEx-A)
FSMC_Ncex low to FSMC_Ay valid t h(NCEx_AI)
FSMC_NCEx high to FSMC_Ax invalid d(NREG-NCEx) t h(NCEx-NREG)
FSMC_NCEx low to FSMC_NREG valid
FSMC_NCEx high to FSMC_NREG invalid t d(NCEx-NWE)
FSMC_NCEx low to FSMC_NWE low t d(NCEx-NOE)
FSMC_NCEx low to FSMC_NOE low t w(NOE)
FSMC_NOE low width t d(NOE_NCEx)
FSMC_NOE high to FSMC_NCEx high t su (D-NOE) t h(N0E-D)
FSMC_D[15:0] valid data before FSMC_NOE high
FSMC_N0E high to FSMC_D[15:0] invalid t w(NWE)
FSMC_NWE low width t d(NWE_NCEx)
FSMC_NWE high to FSMC_NCEx high t d(NCEx-NWE)
FSMC_NCEx low to FSMC_NWE low t v(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid t h
(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid t d
(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
-
4
-
T
HCLK
+4
-
-
8T
HCLK
–1
5T
HCLK
+2.5
4.5
3
8T
HCLK
–0.5
5T
HCLK
–1
-
-
8T
HCLK
–1
13T
HCLK
–1
0
-
3.5
-
5T
HCLK
+0.5
5T
HCLK
+0.5
8T
HCLK
+1
-
-
-
8T
HCLK
+ 3
-
5T
HCLK
+ 1
0
-
-
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DocID022152 Rev 4 151/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 84. Switching characteristics for PC Card/CF read and write cycles
in I/O space
(1)(2)
Parameter Min Max
t w(NIOWR) t v(NIOWR-D) t h(NIOWR-D) t d(NCE4_1-NIOWR) t h(NCEx-NIOWR) t d(NIORD-NCEx) t h(NCEx-NIORD) t w(NIORD) t su(D-NIORD) t d(NIORD-D)
FSMC_NIOWR low width
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
FSMC_NCE4_1 low to FSMC_NIOWR valid
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCEx low to FSMC_NIORD valid
FSMC_NCEx high to FSMC_NIORD) valid
FSMC_NIORD low width
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
8T
HCLK
–1
-
8T
HCLK
– 2
-
5T
HCLK
–1.5
-
5T
HCLK
– 1.5
8T
HCLK
–0.5
9
0
-
5T
HCLK
– 1
-
5T
HCLK
+ 2.5
-
5T
HCLK
+ 2
-
-
-
-
NAND controller waveforms and timings
represent synchronous waveforms, and
and
provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:
•
COM.FSMC_SetupTime = 0x01;
•
COM.FSMC_WaitSetupTime = 0x03;
•
COM.FSMC_HoldSetupTime = 0x02;
•
COM.FSMC_HiZSetupTime = 0x01;
•
ATT.FSMC_SetupTime = 0x01;
•
ATT.FSMC_WaitSetupTime = 0x03;
•
ATT.FSMC_HoldSetupTime = 0x02;
•
ATT.FSMC_HiZSetupTime = 0x01;
•
Bank = FSMC_Bank_NAND;
•
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
•
ECC = FSMC_ECC_Enable;
•
ECCPageSize = FSMC_ECCPageSize_512Bytes;
•
TCLRSetupTime = 0;
•
TARSetupTime = 0.
In all timing tables, the
T
HCLK
is the HCLK clock period.
Unit
ns ns ns ns ns ns ns ns ns ns
152/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Figure 69. NAND controller waveforms for read access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE t d(ALE-NOE) t h(NOE-ALE)
FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D)
FSMC_D[15:0] ai14901c
Figure 70. NAND controller waveforms for write access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16) t d(ALE-NWE) t h(NWE-ALE)
FSMC_NWE
FSMC_NOE (NRE)
FSMC_D[15:0] t v(NWE-D) t h(NWE-D) ai14902c
DocID022152 Rev 4 153/185
Electrical characteristics STM32F405xx, STM32F407xx
Figure 71. NAND controller waveforms for common memory read access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE t d(ALE-NOE) t h(NOE-ALE) t w(NOE)
FSMC_NOE t su(D-NOE) t h(NOE-D)
FSMC_D[15:0] ai14912c
Figure 72. NAND controller waveforms for common memory write access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16) t d(ALE-NOE)
FSMC_NWE
FSMC_NOE t w(NWE) t h(NOE-ALE) t d(D-NWE) t v(NWE-D) t h(NWE-D)
FSMC_D[15:0] ai14913c
Symbol
Table 85. Switching characteristics for NAND Flash read cycles
(1)
Parameter Min Max
t w(N0E)
FSMC_NOE low width t su(D-NOE) t h(NOE-D) t d(ALE-NOE) t h(NOE-ALE)
1. C
L
= 30 pF.
FSMC_D[15-0] valid data before FSMC_NOE high
FSMC_D[15-0] valid data after FSMC_NOE high
FSMC_ALE valid before FSMC_NOE low
FSMC_NWE high to FSMC_ALE invalid
4T
HCLK
0.5
–
10
0
-
3T
HCLK
– 2
4T
HCLK
+ 3
-
-
3T
HCLK
-
Unit
ns ns ns ns ns
154/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Electrical characteristics
Table 86. Switching characteristics for NAND Flash write cycles
(1)
Symbol
t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE)
1. C
L
= 30 pF.
Parameter
FSMC_NWE low width
FSMC_NWE low to FSMC_D[15-0] valid
FSMC_NWE high to FSMC_D[15-0] invalid
FSMC_D[15-0] valid before FSMC_NWE high
FSMC_ALE valid before FSMC_NWE low
FSMC_NWE high to FSMC_ALE invalid
Min Max Unit
4T
HCLK
–1 4T
HCLK
+ 3 ns
0 ns
3T
HCLK
5T
HCLK
3T
-
HCLK
–2
–3
–2
-
-
3T
HCLK
ns ns ns ns
Unless otherwise specified, the parameters given in
for DCMI are derived from tests performed under the ambient temperature, f
HCLK
frequency and V summarized in
, with the following configuration:
DD
supply voltage
•
PCK polarity: falling
• VSYNC and HSYNC polarity: high
•
Data format: 14 bits
Figure 73. DCMI timing diagram
1/DCMI_PIXCLK
Pixel clock t su(HSYNC) t h(HSYNC)
HSYNC t su(VSYNC) t h(HSYNC)
VSYNC t su(DATA) t h(DATA)
DATA[0:13]
MS32414V1
Symbol
DCMI_PIXCLK
D pixel
Table 87. DCMI characteristics
(1)
Parameter Min
Frequency ratio DCMI_PIXCLK/f
HCLK
-
Pixel clock input
Pixel clock input duty cycle
-
30
Max
0.4
54
70
Unit
MHz
%
DocID022152 Rev 4 155/185
Electrical characteristics STM32F405xx, STM32F407xx
Symbol
Table 87. DCMI characteristics
(1)
(continued)
Parameter
t su(DATA) t h(DATA)
Data input setup time
Data hold time t su(HSYNC)
, t su(VSYNC)
HSYNC/VSYNC input setup time t h(HSYNC)
, t h(VSYNC)
HSYNC/VSYNC input hold time
1. Data based on characterization results, not tested in production.
Min
2.5
1
2
0.5
Max
-
-
-
-
Unit
ns
5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in
are derived from tests performed under ambient temperature, f
PCLKx frequency and V
DD
supply voltage conditions summarized in
with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5V
DD
Section 5.3.16: I/O port characteristics
for more details on the input/output
characteristics.
Figure 74. SDIO high-speed mode
tf tr
CK
D, CMD
(output) tW(CKH)
D, CMD
(input) tOV tC tISU tW(CKL) tOH tIH ai14887
156/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Figure 75. SD default mode
Electrical characteristics
CK
D, CMD
(output) tOVD tOHD ai14888
Symbol
Table 88. Dynamic characteristics: SD / MMC characteristics
(1)
Parameter Conditions
f
PP
Clock frequency in data transfer mode t
W(CKL) t
W(CKH)
SDIO_CK/f
PCLK2
frequency ratio
Clock low time
Clock high time
CMD, D inputs (referenced to CK) in MMC and SD HS mode fpp = 48 MHz fpp = 48 MHz t
ISU
Input setup time HS fpp = 48 MHz t
IH
Input hold time HS
CMD, D outputs (referenced to CK) in MMC and SD HS mode fpp = 48 MHz fpp = 48 MHz fpp = 48 MHz t
OV t
OH
Output valid time HS
Output hold time HS
CMD, D inputs (referenced to CK) in SD default mode t
ISUD
Input setup time SD t
IHD
Input hold time SD
CMD, D outputs (referenced to CK) in SD default mode t
OVD t
OHD
Output valid default time SD
Output hold default time SD
1. Data based on characterization results, not tested in production.
fpp = 24 MHz fpp = 24 MHz fpp = 24 MHz fpp = 24 MHz
Min
0
-
8.5
8.3
3
0
-
1
1.5
0.5
-
0.5
Typ
-
-
-
-
4.5
-
4.5
-
-
9
10
Max
-
-
48
8/3
Unit
MHz
ns
-
-
-
-
7
-
6
ns ns ns ns
Symbol
-
Table 89. RTC characteristics
Parameter Conditions
f
PCLK1
/RTCCLK frequency ratio
Any read/write operation from/to an RTC register
Min
4
Max
-
DocID022152 Rev 4 157/185
Package characteristics STM32F405xx, STM32F407xx
6.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
158/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Package characteristics
Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline
A1 ball location
D e1 e
E
Detail A e e2
G
Wafer back side
Detail A rotated by 90 °C
A2
A
Side view eee
Bump side
F
A1 b
Seating plane
A0JW_ME
Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
E e b
D
A
A1
A2
0.520
0.165
0.350
0.240
4.178
3.964
0.570
0.190
0.380
0.270
4.218
3.969
0.400
0.620
0.215
0.410
0.300
4.258
4.004
e1 e2
F
G
3.600
3.200
0.312
0.385
eee 0.050
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.0205
0.0065
0.0138
0.0094
0.1645
0.1561
0.0224
0.0075
0.015
0.0106
0.1661
0.1563
0.0157
0.1417
0.126
0.0123
0.0152
0.0244
0.0085
0.0161
0.0118
0.1676
0.1576
0.0020
DocID022152 Rev 4 159/185
Package characteristics STM32F405xx, STM32F407xx
Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline
A
A2
A1 b
E E1 e
D1
D
L1 c
L ai14398b
1. Drawing is not to scale.
Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
D
D1 b c
A
A1
A2
E
E1 e
θ
L
L1
0.050
1.350
0.170
0.090
1.600
0.150
1.450
1.400
0.220
0.270
0.200
12.000
10.000
12.000
10.000
0.0020
0.0531
0.0067
0.0035
0°
0.500
3.5°
0.450
0.600
1.000
7°
0.750
0°
0.0177
0.0551
0.0087
0.4724
0.3937
0.4724
0.3937
0.0197
3.5°
0.0236
0.0394
0.0630
0.0059
0.0571
0.0106
0.0079
7°
0.0295
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
160/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Package characteristics
Figure 78. LQFP64 recommended footprint
48 33
0.3
49
0.5
32
12.7
10.3
10.3
64 17
1.2
1 16
7.8
12.7
ai14909
1. Drawing is not to scale.
2. Dimensions are in millimeters.
DocID022152 Rev 4 161/185
Package characteristics STM32F405xx, STM32F407xx
Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
SEATING
PLANE
C ccc C
76
75
D
D1
D3
51
50
0.25 mm
GAUGE PLANE
L1
L
K
100
PIN 1
IDENTIFICATION
1 25
26 e
1L_ME_V4
1. Drawing is not to scale.
Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
(1) millimeters inches
Symbol
Min Typ Max Min Typ Max
L
L1 k ccc
E
E1
E3 e c
D
D1
D3
A
A1
A2 b
0.050
1.350
0.170
0.090
15.800
13.800
15.80v
13.800
0.450
1.400
0.220
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
1.600
0.150
1.450
0.270
0.200
16.200
14.200
16.200
14.200
0.750
0° 7°
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
0.6220
0.5433
0.0177
0°
0.0551
0.0087
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
0.6378
0.5591
0.0295
7°
0.0031
162/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Package characteristics
Figure 80. LQFP100 recommended footprint
75 51
76 50
0.5
0.3
16.7
14.3
100
1 25
26
1.2
12.3
16.7
ai14906
1. Drawing is not to scale.
2. Dimensions are in millimeters.
DocID022152 Rev 4 163/185
Package characteristics STM32F405xx, STM32F407xx
Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
Seating plane
C
A A2 A1 b c ccc C
0.25 mm gage plane k
D
D1
D3
A1
L1
L
109
108 73
72
E3 E1 E
Pin 1 identification
144
1 36
37 e
ME_1A
1. Drawing is not to scale.
E
E1
E3 e
L
L1 c
D
D1
D3
A
A1
A2 b
Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
0.050
1.350
0.170
0.090
21.800
19.800
1.400
0.220
1.600
0.150
1.450
0.270
0.200
22.200
20.200
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
0.0551
0.0087
21.800
19.800
0.450
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
22.200
20.200
0.750
0.8583
0.7795
0.0177
0.8661
0.7874
0.689
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
0.0630
0.0059
0.0571
0.0106
0.0079
0.874
0.7953
0.8740
0.7953
0.0295
164/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Package characteristics
Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
k ccc
0° 3.5° 7°
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0° 3.5° 7°
0.0031
Figure 82. LQFP144 recommended footprint
109
108
0.35
73
1.35
72
0.5
19.9
17.85
22.6
144
1
1. Drawing is not to scale.
2. Dimensions are in millimeters.
19.9
22.6
37
36 ai14905c
DocID022152 Rev 4 165/185
Package characteristics STM32F405xx, STM32F407xx
Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline
C
Seating plane
A2
A e
F ddd C
A1
A
A1 ball identifier
A1 ball index area
A
F
E
D
R
15
BOTTOM VIEW e
B
1
Ø
Ø
Øb (176 + 25 balls) eee fff
M
M
C
C
A B
TOP VIEW
A0E7_ME_V4
1. Drawing is not to scale.
Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
A
A1
A2
0.460
0.050
0.400
0.530
0.080
0.450
0.600
0.110
0.500
0.0181
0.002
0.0157
0.0209
0.0031
0.0177
0.0236
0.0043
0.0197
F ddd eee fff
E e b
D
0.230
9.900
9.900
0.280
10.000
10.000
0.650
0.450
0.330
10.100
10.100
0.0091
0.3898
0.3898
0.425
0.475
0.080
0.150
0.080
0.0167
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.0110
0.3937
0.3937
0.0256
0.0177
0.0130
0.3976
0.3976
0.0187
0.0031
0.0059
0.0031
166/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Package characteristics
Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline
C Seating plane
A A2
0.25 mm gauge plane k
A1 ccc C c
A1
HD
D
L
L1
ZD
ZE b
133
132
89
88
E
HE
176
Pin 1 identification
1 44
45 e
1T_ME
1. Drawing is not to scale.
Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches
(1)
Symbol millimeters
Min Typ Max Min Typ Max
0.0630
HD
HE
L
L1
ZD
ZE
E e
C
D
A
A1
A2 b
0.050
1.350
0.170
0.090
23.900
23.900
25.900
25.900
0.450
0.500
1.000
1.250
1.250
1.600
0.150
1.450
0.270
0.200
24.100
24.100
26.100
26.100
0.750
0.0020
0.0531
0.0067
0.0035
0.9409
0.9409
1.0200
1.0200
0.0177
0.0197
0.0394
0.0492
0.0492
0.0060
0.0106
0.0079
0.9488
0.9488
1.0276
1.0276
0.0295
DocID022152 Rev 4 167/185
Package characteristics STM32F405xx, STM32F407xx
Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
ccc k 0 °
0.080
7 °
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0 °
0.0031
7 °
Figure 85. LQFP176 recommended footprint
1.2
1
176
0.5
133
132
0.3
168/185
44
45
1. Dimensions are expressed in millimeters.
21.8
26.7
88
89
1.2
1T_FP_V1
DocID022152 Rev 4
STM32F405xx, STM32F407xx Package characteristics
The maximum chip-junction temperature, T
J using the following equation:
max, in degrees Celsius, may be calculated
T
J
max = T
A
max + (P
D
max x
Θ
JA
)
Where:
•
T
A
max is the maximum ambient temperature in
°C,
• Θ
JA
is the package junction-to-ambient thermal resistance, in
°C/W,
•
P
D
max is the sum of P
INT
max and P
I/O max (P
D
max = P
INT
max + P
I/O max),
•
P
INT
max is the product of I
DD and internal power.
V
DD
, expressed in Watts. This is the maximum chip
P
I/O
max represents the maximum power dissipation on output pins where:
P
I/O
max =
Σ (V
OL
× I
OL
) +
Σ((V
DD
– V
OH
) × I
OH
), taking into account the actual V
OL application.
/ I
OL
and V
OH
/ I
OH of the I/Os at low and high level in the
Symbol
Θ
JA
Table 96. Package thermal characteristics
Parameter Value
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.65 mm pitch
Thermal resistance junction-ambient
WLCSP90 - 0.400 mm pitch
46
43
40
38
39
38.1
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID022152 Rev 4 169/185
Part numbering STM32F405xx, STM32F407xx
Table 97. Ordering information scheme
STM32 F 405 R E Example:
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
405 = STM32F40x, connectivity
407= STM32F40x, connectivity, camera interface, Ethernet
T 6 xxx
Pin count
R = 64 pins
O = 90 pins
V = 100 pins
Z = 144 pins
I = 176 pins
Flash memory size
E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
Package
T = LQFP
H = UFBGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
170/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Appendix A Application block diagrams
Application block diagrams
A.1 USB OTG full speed (FS) interface solutions
Figure 86. USB controller configured as peripheral-only and used in Full speed mode
V
DD
5V to V
DD
Volatge regulator
(1)
STM32F4xx
OSC_IN
PA11//PB14
PA12/PB15
OSC_OUT
VBUS
DM
DP
V
SS
MS19000V5
1. External voltage regulator only needed when building a V
BUS
powered device.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
Figure 87. USB controller configured as host-only and used in full speed mode
V
DD
EN
GPIO
Current limiter power switch
(1)
5 V Pwr
Overcurrent
STM32F4xx
GPIO+IRQ
OSC_IN
VBUS
DM
DP
V
SS
OSC_OUT
PA11//PB14
PA12/PB15
MS19001V4
1. The current limiter is required only if the application has to support a V switch can be used if 5 V are available on the application board.
BUS
powered device. A basic power
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
DocID022152 Rev 4 171/185
Application block diagrams STM32F405xx, STM32F407xx
Figure 88. USB controller configured in dual mode and used in full speed mode
V
DD
5 V to V
DD voltage regulator (1)
V
DD
EN
GPIO
GPIO+IRQ
Overcurrent
Current limiter power switch
(2)
5 V Pwr
STM32F4xx
OSC_IN
OSC_OUT
PA9/PB13
PA11/PB14
PA12/PB15
PA10/PB12
VBUS
DM
DP
ID
(3)
V
SS
MS19002V3
1. External voltage regulator only needed when building a V
BUS
powered device.
2. The current limiter is required only if the application has to support a V switch can be used if 5 V are available on the application board.
BUS
powered device. A basic power
3. The ID pin is required in dual role only.
4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
172/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
A.2
Application block diagrams
USB OTG high speed (HS) interface solutions
Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode
USB HS
OTG Ctrl
STM32F4xx
FS PHY
DP
DM not connected
ULPI
ULPI_CLK
ULPI_D[7:0]
ULPI_DIR
ULPI_STP
ULPI_NXT
DP
DM
ID(2)
V
BUS
V
SS
USB connector
High speed
OTG PHY
PLL
XT1
24 or 26 MHz XT
(1)
MCO1 or MCO2
XI
MS19005V2
1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F40x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection.
2. The ID pin is required in dual role only.
DocID022152 Rev 4 173/185
Application block diagrams STM32F405xx, STM32F407xx
XTAL
25 MHz
Figure 90. MII mode using a 25 MHz crystal
STM32
MCU
HCLK(1)
OSC
Ethernet
MAC 10/100
TIM2
IEEE1588 PTP
Timer input trigger
Timestamp comparator
PLL
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
MII_CRS
MII_COL
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MDIO
MDC
PPS_OUT(2)
HCLK
MCO1/MCO2
PHY_CLK 25 MHz
Ethernet
PHY 10/100
MII
= 15 pins
MII + MDC
= 17 pins
XT1
MS19968V1
1. f
HCLK
must be greater than 25 MHz.
2. Pulse per second when using IEEE1588 PTP optional signal.
Figure 91. RMII with a 50 MHz oscillator
STM32
MCU
HCLK(1)
Ethernet
MAC 10/100
TIM2
IEEE1588 PTP
Timer input trigger
Timestamp comparator
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRX_DV
RMII_REF_CLK
MDIO
MDC
Ethernet
PHY 10/100
RMII
= 7 pins
RMII + MDC
= 9 pins
OSC
50 MHz
2.5 or 25 MHz
/2 or /20 synchronous
50 MHz
PLL
HCLK
PHY_CLK 50 MHz XT1 50 MHz
MS19969V1
1. f
HCLK
must be greater than 25 MHz.
174/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Application block diagrams
Figure 92. RMII with a 25 MHz crystal and PHY with PLL
STM32F
Ethernet
PHY 10/100
MCU
HCLK(1)
Ethernet
MAC 10/100
TIM2
IEEE1588 PTP
Timer input trigger
Timestamp comparator
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRX_DV
RMII_REF_CLK
MDIO
MDC
RMII
= 7 pins
REF_CLK
RMII + MDC
= 9 pins
XTAL
25 MHz
2.5 or 25 MHz
/2 or /20 synchronous
50 MHz
OSC
PLL
HCLK
MCO1/MCO2
PHY_CLK 25 MHz
XT1
PLL
1. f
HCLK
must be greater than 25 MHz.
2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block.
MS19970V1
DocID022152 Rev 4 175/185
Revision history STM32F405xx, STM32F407xx
176/185
Date
15-Sep-2011
24-Jan-2012
Revision
Table 98. Document revision history
Changes
1
2
Initial release.
Added WLCSP90 package on cover page.
Renamed USART4 and USART5 into UART4 and UART5, respectively.
Updated number of USB OTG HS and FS in
Table 2: STM32F405xx and STM32F407xx: features and peripheral counts
.
Updated
Figure 3: Compatible board design between
STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
Figure 4: Compatible board design between STM32F2xx and
STM32F4xx for LQFP176 and BGA176 packages
1 and 2.
Updated
Section 2.2.9: Flexible static memory controller (FSMC)
Modified I/Os used to reprogram the Flash memory for
CAN2 and
USB OTG FS in
.
Section 2.2.14: Power supply schemes
.
PDR_ON no more available on LQFP100 package. Updated
Section 2.2.16: Voltage regulator
. Updated condition to obtain a
minimum supply voltage of 1.7 V in the whole document.
Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for
Table 5: USART feature comparison
Removed support of I2C for OTG PHY in
Section 2.2.30: Universal serial bus on-the-go full-speed (OTG_FS)
.
Added
Table 6: Legend/abbreviations used in the pinout table
Table 7: STM32F40x pin and ball definitions
and V
SS
_8 by V
SS
SS
_3, V
SS
_4,
Table 7: STM32F40x pin and ball definitions
to better highlight I/O structure, and alternate functions
versus additional functions; signal corresponding to LQFP100 pin 99 changed from PDR_ON to V
SS
; EVENTOUT added in the list of alternate functions for all I/Os; ADC3_IN8 added as alternate function for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for PD11 and PD12, respectively; PH10 alternate function
TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O structure to TTa.
Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in
STM32F40x pin and ball definitions
Table 9: Alternate function mapping
Changed TCM data RAM to CCM data RAM in
Figure 18: STM32F40x memory map
Added I
VDD and I
VSS maximum values in
Table 12: Current characteristics
.
Added
Note 1
related to f
HCLK
, updated
Note 2
Table 14: General operating conditions
, and added maximum power dissipation values.
Updated
Table 15: Limitations depending on the operating power supply range
.
DocID022152 Rev 4
STM32F405xx, STM32F407xx Revision history
Date
24-Jan-2012
Table 98. Document revision history (continued)
Revision Changes
2
(continued)
Added
V
12
Table 19: Embedded reset and power control block characteristics
.
Updated
Flash memory (ART accelerator enabled) or RAM
. Added
Figure
,
,
.
Table 22: Typical and maximum current consumption in Sleep mode
Table 23: Typical and maximum current consumptions in Stop mode
Table 24: Typical and maximum current consumptions in
,
Table 25: Typical and maximum current consumptions in VBAT mode
Table 26: Switching output I/O current consumption
Section : On-chip peripheral current consumption
: modified conditions, and updated
Table 27: Peripheral current consumption
Note 2
.
Changed f
HSE_ext to 50 MHz and t r(HSE)
/t f(HSE) maximum value in
Table 29: High-speed external user clock characteristics
Added C in(LSE)
.
in
Table 30: Low-speed external user clock
Updated maximum PLL input clock frequency, removed related note, and deleted jitter for MCO for RMII Ethernet typical value in
. Updated maximum PLLI2S input clock
frequency and removed related note in
Table 36: PLLI2S (audio PLL) characteristics
.
Updated
Section : Flash memory
to specify that the devices are shipped to customers with the Flash memory erased. Updated
Table 38: Flash memory characteristics
, and added t
ME
in
Updated
.
Updated
Table 56: I2S dynamic characteristics
Updated
Figure 46: ULPI timing diagram
Added t
COUNTER
and t
MAX_COUNT in
Table 51: Characteristics of TIMx connected to the APB1 domain
Table 52: Characteristics of TIMx connected to the APB2 domain
Table 65: Dynamic characteristics: Ethernet MAC signals for RMII
Removed USB-IF certification in
Section : USB OTG FS characteristics
.
DocID022152 Rev 4 177/185
Revision history STM32F405xx, STM32F407xx
Date
24-Jan-2012
Table 98. Document revision history (continued)
Revision Changes
2
(continued)
Updated
Table 61: USB HS clock timing parameters
Updated
Updated
Table 68: ADC accuracy at fADC = 30 MHz
.
Updated
Note 1
in
Section 5.3.25: FSMC characteristics
, changed C
L
value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated
Synchronous multiplexed PSRAM write timings
.
Updated
Table 96: Package thermal characteristics
A.1: USB OTG full speed (FS) interface solutions
: modified
Figure 86: USB controller configured as peripheral-only and used in
Note 2
Figure 87: USB controller configured as host-only and used in full speed mode
Note 2
, changed
Figure 88: USB controller configured in dual mode and used in full speed mode
Note 3
.
A.2: USB OTG high speed (HS) interface solutions
figures USB OTG HS device-only connection in FS mode and USB
OTG HS host-only connection in FS mode, and updated Figure 89:
USB controller configured as peripheral, host, or dual-mode and used in high speed mode
Note 2
.
Added Appendix
A.3: Ethernet interface solutions
178/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Revision history
Date
31-May-2012
Table 98. Document revision history (continued)
Revision Changes
3
Updated
Figure 5: STM32F40x block diagram
Figure 7: Power supply supervisor interconnection with internal reset OFF
Added SDIO, added notes related to FSMC and SPI/I2S in
STM32F405xx and STM32F407xx: features and peripheral counts
Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices.
Added full information on WLCSP90 package together with corresponding part numbers.
Changed number of AHB buses to 3.
Modified available Flash memory sizes in
Modified number of maskable interrupt channels in
Nested vectored interrupt controller (NVIC)
Updated case of Regulator ON/internal reset ON, Regulator
ON/internal reset OFF, and Regulator OFF/internal reset ON in
Section 2.2.16: Voltage regulator
Updated standby mode description in
Section 2.2.19: Low-power modes
Added
Note 1
Figure 16: STM32F40x UFBGA176 ballout
.
Added
Note 1
Figure 17: STM32F40x WLCSP90 ballout
.
Updated
Table 7: STM32F40x pin and ball definitions
Added
Removed OTG_HS_INTN alternate function in
Table 7: STM32F40x pin and ball definitions
Table 9: Alternate function mapping
.
Removed I2S2_WS on PB6/AF5 in
Table 9: Alternate function mapping
Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and modified I2S3ext_SD on PC11 in
Table 9: Alternate function mapping
Added
Table 10: STM32F40x register boundary addresses
Updated
Figure 18: STM32F40x memory map
.
Updated V
DDA
and V
REF+
decoupling capacitor in
Figure 21: Power supply scheme
.
Added power dissipation maximum value for WLCSP90 in
.
Updated V
POR/PDR
Table 19: Embedded reset and power control block characteristics
.
Updated notes in
,
Flash memory (ART accelerator enabled) or RAM
Typical and maximum current consumption in Sleep mode
Updated maximum current consumption at T
A
Typical and maximum current consumptions in Stop mode
DocID022152 Rev 4 179/185
Revision history STM32F405xx, STM32F407xx
Date
31-May-2012
Table 98. Document revision history (continued)
Revision Changes
3
(continued)
Removed f
HSE_ext
typical value in
Table 29: High-speed external user clock characteristics
Table 31: HSE 4-26 MHz oscillator characteristics
Table 32: LSE oscillator characteristics (fLSE =
Added f
PLL48_OUT
.
maximum value in
Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics
.
Updated
Table 38: Flash memory characteristics
Table 39: Flash memory programming
Table 40: Flash memory programming with
.
Updated
Section : Output driving current
.
Note 4
updated and applied to t h(SDA)
Fast mode, and removed note 4 related to t h(SDA) minimum value.
in
accuracy vs. negative injection current below
Table 68: ADC accuracy at fADC = 30 MHz
.
Added WLCSP90 thermal resistance in
Table 96: Package thermal characteristics
.
Updated
Table 90: WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data
Updated
Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array
10 × 10 × 0.6 mm, package outline
Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data
.
Added
Figure 85: LQFP176 recommended footprint
.
Removed 256 and 768 Kbyte Flash memory density from
180/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Revision history
Date
04-Jun-2013
Table 98. Document revision history (continued)
Revision Changes
4
Modified
Note 1
Table 2: STM32F405xx and STM32F407xx: features and peripheral counts
.
Updated
title.
Updated
Note 3
Figure 21: Power supply scheme
Changed simplex mode into half-duplex mode in
Section 2.2.25: Interintegrated sound (I2S)
Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and
DAC_OUT2, respectively.
Figure 15: STM32F40x LQFP176 pinout
.
Changed pin number from F8 to D4 for PA13 pin in
STM32F40x pin and ball definitions
Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5 pins in
Table 9: Alternate function mapping
.
Changed system memory into System memory + OTP in
Added
Note 1
Table 16: VCAP_1/VCAP_2 operating conditions
.
Updated I
DDA description in
Removed PA9/PB13 connection to VBUS in
Figure 86: USB controller configured as peripheral-only and used in Full speed mode
Figure 87: USB controller configured as host-only and used in full speed mode
.
Updated SPI throughput on front page and
Section 2.2.24: Serial peripheral interface (SPI)
Updated operating voltages in
STM32F407xx: features and peripheral counts
Section 2.2.14: Power supply schemes
Updated
Section 2.2.15: Power supply supervisor
Updated “Regulator ON” paragraph in
Section 2.2.16: Voltage regulator
Removed note in
Section 2.2.19: Low-power modes
Corrected wrong reference manual in
Section 2.2.28: Ethernet MAC interface with dedicated DMA and IEEE 1588 support
Updated
Table 15: Limitations depending on the operating power supply range
Updated
Table 24: Typical and maximum current consumptions in
Updated
Table 25: Typical and maximum current consumptions in
Updated
Table 36: PLLI2S (audio PLL) characteristics
Updated
Updated
Table 48: Output voltage characteristics
Updated
Table 50: NRST pin characteristics
Updated
Table 55: SPI dynamic characteristics
Updated
Table 56: I2S dynamic characteristics
Deleted Table 59
Updated
Updated
Figure 47: Ethernet SMI timing diagram
DocID022152 Rev 4 181/185
Revision history STM32F405xx, STM32F407xx
Date
04-Jun-2013
Table 98. Document revision history (continued)
Revision Changes
4
(continued)
Updated
Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array
10 × 10 × 0.6 mm, package outline
Updated
Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array
10 × 10 × 0.6 mm mechanical data
Updated
Figure 5: STM32F40x block diagram
Updated
Updated footnote
(3)
Table 2: STM32F405xx and STM32F407xx: features and peripheral counts
Updated
Figure 3: Compatible board design between
STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
Updated
Figure 4: Compatible board design between STM32F2xx and
STM32F4xx for LQFP176 and BGA176 packages
Updated
Section 2.2.14: Power supply schemes
Updated
Section 2.2.15: Power supply supervisor
Updated
Section 2.2.16: Voltage regulator
Updated
Table 14: General operating conditions
(2)
.
Updated
Table 15: Limitations depending on the operating power supply range
, including footnote
(3)
.
Updated footnote
(1)
.
Updated footnote
(3)
Table 68: ADC accuracy at fADC = 30 MHz
.
Updated footnote
(1)
.
Updated
Updated
Figure 7: Power supply supervisor interconnection with internal reset OFF
Added
Section 2.2.17: Regulator ON/OFF and internal reset ON/OFF availability
.
Updated footnote
(2)
Figure 21: Power supply scheme
.
Replaced respectively “I2S3S_WS" by "I2S3_WS”, “I2S3S_CK” by
“I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in
Table 9: Alternate function mapping
Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14,
Table 9: Alternate function mapping
Replaced “DCMI_12” by “DCMI_D12” in
Table 7: STM32F40x pin and ball definitions
Removed the following sentence from
Section : I2C interface characteristics
: ”Unless otherwise specified, the parameters given in
are derived from tests performed under the
ambient temperature, f
PCLK1 frequency and V
.”.
DD
supply voltage
Table 7: STM32F40x pin and ball definitions on page 45
– For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1,
RTC_TS”
– for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2,
RTC_TS”.
– for pin PB15, added RTC_REFIN in Alternate functions column.
In
Table 9: Alternate function mapping on page 60
, for port
PB15, replaced “RTC_50Hz” by “RTC_REFIN”.
182/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx Revision history
Date
04-Jun-2013
Table 98. Document revision history (continued)
Revision Changes
4
(continued)
Updated
Updated
Figure 7: Power supply supervisor interconnection with internal reset OFF
Changed 1.2 V to
V
12
in
Section : Regulator OFF
Updated LQFP176 pin 48.
Updated
Updated
Updated operating voltage in
STM32F407xx: features and peripheral counts
.
Updated
Updated
Section 2.2.15: Power supply supervisor
.
Updated
Section 2.2.16: Voltage regulator
Updated
Updated
Table 3: Regulator ON/OFF and internal reset ON/OFF availability
.
Updated
Section 2.2.19: Low-power modes
Updated
Section 2.2.20: VBAT operation
Updated
Section 2.2.22: Inter-integrated circuit interface (I²C)
.
Updated pin 48 in
Figure 15: STM32F40x LQFP176 pinout
.
Updated
Table 6: Legend/abbreviations used in the pinout table
Updated
Table 7: STM32F40x pin and ball definitions
Updated
Table 14: General operating conditions
Updated
Table 15: Limitations depending on the operating power supply range
.
Updated
Section 5.3.7: Wakeup time from low-power mode
Updated
Table 33: HSI oscillator characteristics
Updated
Section 5.3.15: I/O current injection characteristics
.
Updated
Table 47: I/O static characteristics
.
Updated
Table 50: NRST pin characteristics
Updated
.
Updated
Figure 39: I2C bus AC waveforms and measurement circuit
.
Updated
Section 5.3.19: Communications interfaces
.
Updated
Added
Table 70: Temperature sensor calibration values
Added
Table 73: Internal reference voltage calibration values
.
Updated
Section 5.3.25: FSMC characteristics
Updated
Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics
.
Table 23: Typical and maximum current consumptions in Stop mode
Updated
Section : SPI interface characteristics
included
.
Updated
Section : I2S interface characteristics
Updated
Table 64: Dynamic characteristics: Ehternet MAC signals for
.
Updated
Table 66: Dynamic characteristics: Ethernet MAC signals for
DocID022152 Rev 4 183/185
Revision history STM32F405xx, STM32F407xx
Date
04-Jun-2013
Table 98. Document revision history (continued)
Revision Changes
4
(continued)
Updated
Table 64: Dynamic characteristics: Ehternet MAC signals for
.
Updated
Table 66: Dynamic characteristics: Ethernet MAC signals for
Updated
Table 79: Synchronous multiplexed NOR/PSRAM read timings
Updated
Table 80: Synchronous multiplexed PSRAM write timings
Updated
Table 81: Synchronous non-multiplexed NOR/PSRAM read timings
Updated
Table 82: Synchronous non-multiplexed PSRAM write timings
Section 5.3.26: Camera interface (DCMI) timing specifications
Table 87: DCMI characteristics
and addition of
Updated
Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics
including
.
Updated
184/185 DocID022152 Rev 4
STM32F405xx, STM32F407xx
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS. NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE
IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH
PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR
ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED
FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN
WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE,
AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS.
PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE
CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
DocID022152 Rev 4 185/185
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project